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US20110049576 Homogenous Cell Array  
A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array,...
US20080273410 Tungsten digitlines  
Methods, devices, and systems for using and forming tungsten digitlines have been described. The tungsten digitlines formed according to embodiments of the present disclosure can be formed with a...
US20140327050 STANDARD CELL HAVING CELL HEIGHT BEING NON-INTEGRAL MULTIPLE OF NOMINAL MINIMUM PITCH  
An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal...
US20090152595 SEMICONDUCTOR DEVICES AND METHOD OF TESTING SAME  
There are provided a semiconductor device having a pattern which allows electric failures to be sensitively detected at high speeds, and a method of testing the same. In one embodiment, the...
US20120273841 Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same  
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which...
US20120119263 WAFER LEVEL PACKAGING  
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least...
US20060043426 Method and apparatus for calculating wiring capacitance, and computer product  
A diagonal-capacitance calculating unit calculates diagonal capacitance based on the adjacent wirings in diagonally upward and downward direction from a target wiring. A basic-capacitance...
US20070235766 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN OBLIQUE GLOBAL SIGNAL WIRING AND SEMICONDUCTOR INTEGRATED CIRCUIT WIRING METHOD  
A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell...
US20060030138 Layout method for semiconductor integrated circuit device  
Provided is a layout method for a semiconductor integrated circuit device in which area pads and peripheral wiring patterns thereof can be automatically laid out. At least one of a plurality of...
US20110018035 Offset Geometries for Area Reduction in Memory Arrays  
An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding...
US20090109765 Single via structured IC device  
A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using...
US20090134431 NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND METHOD OF MANUFACTURING THE SAME  
A nonvolatile semiconductor storage apparatus includes: a plurality of first wirings; a plurality of second wirings which cross the plurality of first wirings; and a memory cell which is connected...
US20080290376 Semiconductor Integrated Circuit  
[The problems] In a semiconductor integrated circuit in which tilted wiring is used, the tilted wiring cannot be used effectively since the arrangement of blocks is restricted. [Means for solving]...
US20100001267 NRAM ARRAYS WITH NANOTUBE BLOCKS, NANOTUBE TRACES, AND NANOTUBE PLANES AND METHODS OF MAKING SAME  
NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in...
US20080067550 Flash memory device using double patterning technology and method of manufacturing the same  
Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and...
US20080203439 Semiconductor integrated circuit having plural transistors  
A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through...
US20070126028 Low resistance void-free contacts  
A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited...
US20050280036 Semiconductor product having a first and at least one further semiconductor circuit and method  
A semiconductor product includes a first semiconductor circuit and at least one further integrated semiconductor circuit arranged together on a semiconductor substrate. The first semiconductor...
US20090236638 Semiconductor Constructions  
The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The...
US20070029575 Structure and method of measuring the capacitance  
The structure and method of measuring the capacitance comprising a first buried doped area and a heavily doped area in a semiconductor substrate. The heavily doped area is parallel to the buried...
US20090085069 NAND-type Flash Array with Reduced Inter-cell Coupling Resistance  
In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of...
US20100127309 INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS  
A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor...
US20110133254 CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING  
An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement...
US20090315080 TRANSISTOR ARRAY WITH SHARED BODY CONTACT AND METHOD OF MANUFACTURING  
An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used...
US20070272949 Semiconductor integrated circuit, and method and apparatus for designing wiring pattern of semiconductor integrated circuit  
It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated...
US20090057743 Integrated Circuit Including Structures Arranged at Different Densities and Method of Forming the Same  
A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the...
US20060208283 Semiconductor device  
A semiconductor device includes a plurality of first word lines which extend in a first direction, a plurality of second word lines which extend in a direction orthogonal to the first direction, a...
US20090200579 Semiconductor device and layout method thereof  
A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer...
US20120001232 ROM CELL CIRCUIT FOR FINFET DEVICES  
The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor...
US20100244102 INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME  
In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to...
US20150048424 STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD  
A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a...
US20100078685 SEMICONDUCTOR MEMORY DEVICE  
There is provided a semiconductor memory device including: a first wiring layer; a second wiring layer; a third wiring layer; a memory array region; a first gate array region being formed at a...
US20120248504 Arrays Of Memory Cells And Methods Of Forming An Array Of Vertically Stacked Tiers Of Memory Cells  
An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented...
US20100059796 Shared masks for x-lines and shared masks for y-lines for fabrication of 3D memory arrays  
A structure and a method of manufacturing a three dimensional memory using a number of bit line masks that is less than the number of device layers. A first bit line mask is used to form a first...
US20090289281 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE  
A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that...
US20130049074 METHODS FOR FORMING CONNECTIONS TO A MEMORY ARRAY AND PERIPHERY  
Methods are disclosed for forming connections to a memory array and a periphery of the array. The methods include forming stacks of conductive materials on the array and the periphery and forming...
US20120223369 Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors  
Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface...
US20120261723 SEMICONDUCTOR DEVICE  
A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided...
US20050045918 Hybrid vertical twisted bitline architecture  
A method and apparatus of wiring a twisted signal such as those that may be used in a twisted bitline architecture of a memory. The twisted bitline architecture includes mixing twisted bitline...
US20100032726 Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions  
A semiconductor device includes a substrate portion including a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual bisecting line. A gate electrode level...
US20080224178 RESISTIVE MEMORY AND METHOD  
A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
US20110156102 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME  
A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is...
US20100032722 Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors  
A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of...
US20100148219 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply...
US20120074467 SWITCH ARRAY  
According to one embodiment, a switch array includes first and second switches provided in a switch unit. The first switch includes first and second memory cell transistors and a first pass...
US20070023784 Method for fabricating a memory cell arrangement with a folded bit line arrangement and corresponding memory cell arrangement with a folded bit line arrangement  
A memory cell arrangement, which has a size of 8F2 per memory cell, wherein F is a unit of length, comprises a plurality of active regions along a first direction in a semiconductor substrate, a...
US20120273842 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME  
A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word...
US20130043509 3-D STRUCTURED NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the...
US20090134432 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a...
US20110309414 Diode polarity for diode array  
A memory-array is disclosed in which an array of non-linear conductors such as diodes is constructed having an area per memory cell of 4F2 and comprises a plurality of conductors fabricated as...

Matches 1 - 50 out of 101 1 2 3 >