Matches 1 - 50 out of 113 1 2 3 >


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US20080121939 Methods of automatically generating dummy fill having reduced storage size  
The disclosure relates generally to production of lithography masks such as used in mass production of monolithic integrated circuits (IC's). Layers of such IC's often need to be filled with...
US20140183602 ALTERNATING TAP-CELL STRATEGY IN A STANDARD CELL LOGIC BLOCK FOR AREA REDUCTION  
An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located...
US20120286331 INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS  
Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in...
US20060081881 Circuit wiring laying-out apparatus, method of laying-out a circuit, signal-bearing medium embodying a program of laying-out wiring, wiring layout, and method of using a wiring layout  
A circuit wiring laying-out apparatus includes a wiring device that moves automatically a wiring in a first region to a second region, to make uniform a number of wirings in the circuit.
US20140151751 DENSITY GRADIENT CELL ARRAY  
One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of cells is associated with a dummy...
US20090321789 Triangle two dimensional complementary patterning of pillars  
A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three...
US20070063223 Semiconductor device having pattern-dummy and method for manufacturing the same using pattern-dummy  
A semiconductor device includes a main pattern disposed to overlap with an active region that is surrounded by a device isolating region, and the dummy pattern disposed on the device isolating...
US20140167117 Methods for Cell Boundary Encroachment and Layouts Implementing the Same  
A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of...
US20110084312 Methods for Cell Boundary Encroachment and Layouts Implementing the Same  
A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of...
US20150179627 PERFORMANCE-DRIVEN AND GRADIENT-AWARE DUMMY INSERTION FOR GRADIENT-SENSITIVE ARRAY  
The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured...
US20070175660 Warpage-reducing packaging design  
A flange and packaging assembly characterized by a structural lip configured to impart resistance to thermal-induced deformation (i.e. “stiffness”) to the flange during elevated temperature die...
US20080105904 Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network  
In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is...
US20060226447 Semiconductor integrated circuit and wafer having diffusion regions differing in thickness and method for manufacturing the same  
A semiconductor integrated circuit includes a rectangular low speed circuit area including a low speed circuit comprising a low speed transistor having a first source extension region and a first...
US20070272947 Low Power Consuming Semiconductor Device  
A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the...
US20100264204 Fingerprinted circuits and methods of making and indenifying same  
A circuit having a fingerprint for identification of a particular instantiation of the circuit. The circuit comprises a plurality of digital circuits or gates, the plurality digital circuits or...
US20050148117 Method for fabricating a flash-preventing window ball grid array semiconductor package  
A flash-preventing window ball grid array semiconductor package, a method for fabricating the same, and a chip carrier used in the semiconductor package are provided. The chip carrier has a...
US20120175683 Basic Cell Architecture For Structured ASICs  
A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC...
US20090146188 SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor storage device includes a plurality of integrated memory cells. Each cell includes a first inverter having a first driver transistor and a first load transistor which are formed on...
US20070221957 Semiconductor integrated circuit device and dummy pattern arrangement method  
A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region...
US20100006896 Semiconductor integrated circuit  
A semiconductor integrated circuit has: a substrate; a basic logic cell placed on the substrate and configured to function as a part of a logic circuit; and a dummy cell placed on the substrate...
US20130234210 METHOD OF MANUFACTURING METAL SILICIDE AND SEMICONDUCTOR STRUCTURE USING THE SAME  
A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization...
US20070152241 Gate Capacitor Having Horizontal Structure and Method for Manufacturing the Same  
A gate capacitor having a horizontal structure and a method for manufacturing the same is provided. The gate capacitor having a horizontal structure can be formed on a semiconductor substrate and...
US20080224176 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is...
US20070235763 Substrate band gap engineered multi-gate pMOS devices  
A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first...
US20100308377 SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is...
US20090236636 Closed Cell Array Structure Capable of Decreasing Area of non-well Junction Regions  
A closed cell array structure capable of decreasing area of non-well junction regions includes a plurality of closed cell units, arranged in a plane, each shaped as a polygon, and a plurality of...
US20050285146 Semiconductor device, manufacturing method of the semiconductor device, and design method of the semiconductor device  
A semiconductor device includes a plurality of primitive cells having multilayer wiring structures and formed on a substrate. The primitive cell includes a functional cell having a logic circuit...
US20130105864 LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY  
A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The...
US20090212327 STANDARD CELL LIBRARIES AND INTEGRATED CIRCUIT INCLUDING STANDARD CELLS  
A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction....
US20060145192 Denise array structure for non-volatile semiconductor memories  
The present invention describes an array structure (10) for non-volatile semiconductor memory elements (14, 16) with a high area density. This high density is obtained by the combination of a...
US20060113567 Semiconductor integrated circuit and method of producing same  
A semiconductor integrated circuit able to repair a defect of a circuit cell without greatly changing interconnects, that is, a semiconductor integrated circuit comprising a plurality of circuit...
US20140027819 CORNER LAYOUT FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES  
A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell...
US20100032635 ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION  
An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical...
US20090261312 INTEGRATED CIRCUIT INCLUDING AN ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD  
An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a...
US20050045916 Power voltage line layout of semiconductor cells using active area  
In a semiconductor integrated circuit layout, a power voltage line for supplying a power voltage to the semiconductor integrated circuit is connected to an active area where an NMOS transistor...
US20110095338 METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING  
The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention...
US20060208281 Contact in planar NROM technology  
A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second...
US20130049072 Arrays Of Recessed Access Devices, Methods Of Forming Recessed Access Gate Constructions, And Methods Of Forming Isolation Gate Constructions In The Fabrication Of Recessed Access Devices  
A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming...
US20070075336 Flash memory devices having shared sub active regions and methods of fabricating the same  
Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of...
US20140176216 INTEGRATED CIRCUIT COMPRISING A CLOCK TREE CELL  
The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells;standard cells (42, 43) placed next to one another,...
US20060124925 Electron device, operational device and display device  
An electron device includes at least an electrode layer, a semiconductor layer and an insulator layer laminated on a substrate, wherein the insulator layer contains a polyimide material obtained...
US20130334575 Damascene Word Line  
The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked...
US20090250726 LOW VT ANTIFUSE DEVICE  
A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell...
US20070262347 DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME  
A display substrate having a high aperture ratio includes gate and source metallic patterns, first and second gate insulating layers, and a pixel electrode. The gate metallic pattern includes a...
US20060249753 High-density nonvolatile memory array fabricated at low temperature comprising semiconductor diodes  
A memory cell is described suitable for use in a high-density monolithic three dimensional memory array. In preferred embodiments of the memory cell, a semiconductor junction diode formed of...
US20080217655 INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES  
An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at...
US20080296628 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME  
A semiconductor integrated circuit includes at least one first circuit portion and at least one second circuit portion. The first circuit portion includes a first interconnect or a diffusion layer...
US20090218600 Memory Cell Layout  
A method for manufacturing an integrated circuit and an integrated circuit are described. In one embodiment, the method for manufacturing the integrated circuit includes determining a layout for...
US20090289281 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE  
A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that...
US20060011946 Nitride semiconductor laser element  
A nitride semiconductor laser element capable of controlling the lateral confinement of light with a good reproducibility, the nitride semiconductor element comprising an n-type cladding layer...

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