WO/1999/052249 | October, 1999 | A RECEIVER FOR SPREAD SPECTRUM COMMUNICATIONS SIGNALS |
This application is a continuation of U.S. patent application Ser. No. 10/335,359, filed on Dec. 31, 2002, which claims the benefit of U.S. Provisional Application Ser. No. 60/379,196, filed on May 9, 2002, which are incorporated by reference as if fully set forth.
The present invention relates to midamble cancellation. More particularly the present invention relates to method and apparatus for performing midamble cancellation utilizing an algorithm enabling parallel cancellation of midamble for both data field 1 and data field 2 of a received TDD burst.
As shown in FIG. 1, a burst is received through a multipath channel having a time-delay spread of (W−1)*T_{c}, where W represents the number of chips and T_{c }represents chip duration. The time (delay)—spread channel causes inter-chip interference whereby the convolution tail of each field in the received burst protrudes upon the adjacent field. For example, the midamble inter-chip interference on the first W−1 chips of data field 2 may cause performance degradation of the data estimation procedure of the symbols corresponding to the first W−1 chips, unless a remedy for the interference is considered. This is especially true since the transmit power control (TPC) command (in uplink (UL) only) and transport format combination indicator (TFCI) bits are located immediately after the midamble and they are not protected by any channel coding scheme, it is desirable to eliminate midamble interference by employing a midamble cancellation procedure to improve data estimation for both data parts of the TDD burst and is a stand-alone procedure that can be used to enhance performance of any of the candidate data estimation algorithms.
Midamble cancellation (also referred to hereinafter as MDC) can also be applied to remove midamble interference from the convolution tail of Data field 1 into the first (W−1) chips of the midamble field, also shown in FIG. 1. This tail also results from the delay spread of the multipath channel and its inclusion into the data estimation of Data field 1 results in more observed data and leads to an exact block Toeplitz structure of the A^{H }A matrix in multi-user detection (MUD).
Midamble cancellation is used to remove the effect of the midamble from:
The first W−1 chips of the midamble field, allowing better modeling of the convolution tail of the first Data field protruding into the midamble field, further allowing modeling of the A^{H }A matrix to be exactly block Toeplitz; and the first W−1 chips of Data field 2. A technique is provided for calculation of midamble interference which significantly reduces the necessary hardware as well as processing time.
The invention will be understood from the accompanying figures, wherein like elements are designated by like numerals and, wherein:
FIG. 1 shows a transmitted burst, a channel and a received burst (TDD DPCH) which is useful in explaining the need for midamble cancellation.
FIG. 2 is a block diagram of data demodulation circuit for a base station, (BS) including a midamble cancellation block.
FIG. 3 is a block diagram of a data demodulation circuit for a user equipment (UE) similar to the BS circuit shown in FIG. 2.
FIG. 4 is a block diagram showing a circuit for midamble cancellation utilizing the cancellation algorithm of the present invention.
FIG. 5 is a simplified block diagram of a midamble cancellation engine.
FIG. 6 is a block diagram showing one of the processing elements of FIG. 5 in greater detail.
FIG. 7 is a block diagram showing how the midamble cancellation block interfaces with other circuits of the system.
FIG. 8 is a graphical representation of the manner in which processing of midamble sequences of the data fields are combined.
FIG. 9 is a block diagram of a midamble cancellation device embodying the principles of the present invention.
FIG. 10 is an illustration useful in explaining a processing element calculation.
FIG. 11 is an illustration useful in explaining how a processing breakdown can be managed.
FIG. 12 is an illustration useful in explaining the manner in which midamble shifts of Burst Type 2 are performed.
FIG. 13 is a simplified diagram showing the midamble cancellation processing timeline.
FIG. 14 is a simplified flow diagram of the midamble cancellation process.
FIGS. 15 and 16 respectively show preload and preprocessor state transition diagrams.
FIG. 17 is a processing element state transition diagram.
FIG. 18 is a midamble shift state transition diagram.
FIG. 19 is a midamble data packer state transition diagram.
FIG. 20 is a data output state transition diagram
FIG. 2 is a block diagram showing a data demodulation circuit 10 for demodulation of a TDD burst employed at a base station (BS). Circuit 10 includes a Steiner channel estimator 12 receiving a midamble portion of the burst. A midamble cancellation circuit 14 receives the TDD burst including data parts, midamble and the guard interval. The output of channel estimator 12 is applied to the post processing and midamble detection circuit 16 which develops channel responses at 16a, which are applied to the midamble cancellation circuit, and midamble shift numbers at 16b which are likewise applied to the midamble cancellation circuit 14.
The midamble shift numbers at 16b are also applied to code decision circuit 18 for determining channelization codes, provided at 18a, which are then applied to the multi-user detector (MUD) 20. Midamble cancellation circuit 14 utilizes the inputs described hereinabove for generating a midamble cancelled burst at 14a which is applied to the multi-user detector circuit 20.
As can clearly be seen, midamble cancellation is implemented before MUD processing. The midamble cancellation procedure initially constructs an estimate of the first W−1 chips of the midamble received in the midamble field and the first W−1 chips of the midamble spread into data field 2, respectively. The received midamble estimation is derived based on the channel responses provided by the channel estimator, 12 which utilizes a known algorithm for obtaining channel estimation, and midamble shift numbers obtained from the midamble detection block 16, which likewise uses a known algorithm to derive midamble shift numbers which, in turn, are utilized to derive channelization codes by code decision circuit 18 employing a known algorithm.
The received burst is stored in a buffer 32 which cooperates with the algorithm 30 of FIG. 4, performed by the midamble cancellation circuit 14 of FIG. 2, for example. The midamble interference from corresponding parts in the received bursts is removed. The resulting burst is fed into the MUD 20 shown in FIG. 2. The concept employed for midamble cancellation is the estimation of midamble interference according to acquired midamble shift numbers and channel responses derived from detection circuit 16, whereupon the estimated interference is used to cancel the effective midamble interference from the received burst.
Midamble cancellation is applied separately to the even and odd samples of the received over-sampled sequences.
FIG. 3 shows data demodulation circuit 11 employed by a user equipment (UE), wherein like elements as between FIGS. 2 and 3 are designated by like numerals and including the midamble cancellation block and differs from FIG. 2 in that the output 14 of cancellation circuit 14 is coupled to detection circuit 18 and blind code detection circuit 18, which provides detected midamble shifts 18b to MUD 20, in addition to the channelization codes.
The data employed in the cancellation circuitry of the present invention comprises:
The data inputs include a received data burst denoted by
Type: | vector of complex-values | |
Length: | 2560 chips | |
Range: | Unrestricted | |
K_{m }sets of complex channel coefficients:
[{{right arrow over (h)}^{1}, {right arrow over (h)}^{2}, . . . , {right arrow over (h)}^{K}^{m}} where {right arrow over (h)}^{i}=[h_{0}^{i}, h_{1}^{i}, h_{2}^{i}, . . . , h_{W−-1}^{i}]]
Type: | vector of complex-values | |
Length: | K_{m × }W | |
Range: | Unrestricted | |
K_{m }is the number of different midambles detected by the midamble detection algorithm in the post processing and midamble detection block 16 (see FIG. 2). W is the length of each channel response.
K_{m }midamble shift numbers: each number is used to generate a corresponding midamble code.
Type: | vector of integers | |
Length: | 1 × K_{m} | |
Range: | 1 to K_{m} | |
A microprocessor (not shown) forming part of the cancellation circuit 14 provides the association between channel impulse response and midamble shift (equivalent to midamble codes), which indicates which channel response belongs to which midamble shift (code).
The data outputs include:
Type: | vector of complex-values | |
Length: | 2560 chips | |
Range: | Unrestricted | |
The parameters of the algorithm are:
TABLE 1 | ||||||
Burst | Burst | Burst | Burst | Burst | ||
Param- | type 1 | type 1 | type 1 | type 2 | type 2 | |
eter | Description | long | nominal | short | nominal | short |
K | Maximum | 4 | 8 | 16 | 3 | 6 |
midamble shift | ||||||
W | Length of each | 114 | 57 | 28 or 29 | 64 | 32 |
channel | ||||||
response in | ||||||
chips | ||||||
L | Length of each | 512 | 512 | 512 | 256 | 256 |
midamble code | ||||||
FIG. 4 illustrates the midamble cancellation algorithm. The received data burst is stored in a buffer memory 32, so that the midamble interference effect on data estimation for both data field 1 and data field 2 can be removed. The active midamble codes of length L in the same time slot are derived according to the input detected midamble shift numbers applied at 34. The midamble codes are derived using conventional algorithms. Then two received midamble interference sequences are constructed at 36, 38, based on K_{m }associated pairs of the channel responses and active midamble codes. The first midamble interference corresponds to the first W−1 chip midamble received in the midamble field, which interferes with the convolution tail of the data field 1 protruding onto the midamble field, as indicated previously in FIG. 1. The received (W−1 chips) midamble sequence,
where m_{i}^{k }represents the i-th element of the midamble,
{circle around (x)} denotes the convolution operator. In other words, the received midamble sequence is a superposition of the K_{m }convolutions between the active midamble codes and channel responses. Equation (1) can be rewritten in a matrix form as follows:
where (
The second received midamble interference corresponds to the first W−1 chips of the received midamble tail into the data field 2 where the tail results from the delay spread of the channel, and it corrupts the first W−1 chips of the received data field 2 (see FIG. 1).
The procedure for constructing the midamble interference is similar to that for the data field 1 set forth above. However, in this case the convolution tail of the midamble field spreads into the data field 2. The midamble interference on the first W−1 chips of the data field 2,
After modeling the two midamble interference sequences by Equations (2) and (3), respectively, Equation (2) is cancelled from the first W−1 chips of the midamble field in the received stored data burst,
The output, at 42a, is applied to MUD 20, see FIG. 2, together with the output at 18a, to derive the estimated symbol sequences, appearing at output 20a.
The performance of the technique of the present invention is dependent on the accuracy of the channel estimation and midamble detection algorithm. With perfectly known channel responses, the implementation should result in less than 0.1 dB degradation in resultant signal-to noise ratio.
Since the midamble cancellation processing (circuit 14-FIG. 3) is completed before data demodulation (with MUD circuit 20), the processing time of midamble cancellation directly affects MUD related latency. Taking into account transmit power control (TPC) latency and especially latency in extracting raw TPC bits, latency of midamble cancellation processing should be less than 80≈0.03 timeslot.
Processing element (PE) adders perform a “multiplication” of midambles and channel responses as shown by “multiplier” 108 in FIG. 5. Each PE is provided with storage registers (i.e. accumulators) 104, 106 for each cancellation vector. Multiplexer, 110 selects the proper midamble output cancellation as will be more fully explained herein.
The following is a high-level description of the system design. FIG. 7 illustrates how the midamble cancellation block 72 interfaces with the other components of the system 70. During processing, the midamble cancellation block 72 has full access to the channel estimates RAMs 74, 76 without contention from other processes. The channel estimates consist of 16-bit complex values with real and imaginary components separated into 2 RAMs, 74, 76.
The midamble server 78 supplies 16-bit midamble sequences based on the midamble number and midamble shift. Each sequence corresponds to 16 1-bit values.
Channel Estimation (CHEST) 80 supplies configuration parameters that control the functionality of midamble cancellation. Also, CHEST supplies control signals that initiate midamble cancellation processing.
The computed interference sequences are stored into 2 pairs of RAMs 82-84 and 86-88. Each pair consists of a real component 82, 86 and an imaginary component 84, 88. One pair is for the data field 1 interference results and the second pair is for the data field 2 interference results.
From Equation 2 and Equation 3, set forth above, we can see that the processing consists of a large matrix multiplication. The size of the left-hand matrix is (W−1)×W*Km. The size of the right-hand vector is W*Km×1. The total number of multiplies is (W−1)*W*Km. Since the size of each midamble sample is 1 bit, the implementation of the multipliers can be simplified and implemented by a mux.
Based on Table 1, the worst-case number of multiplies occurs when W=57 and Km=8, resulting in a total of 25,536 multiplies. Performing these multiplies sequentially is unacceptable since the total number of clock cycles equals the number of multiplies. Instead, it is necessary to perform the multiplications for multiple rows in parallel by assigning a processing element (PE) to each row. The PE for each row can be conveniently implemented using a multiply and accumulate function. The total processing time then will be (W−1)*W*Km/NPE, where NPE is the number of PE's.
The greatest savings in processing time are achieved when NPE=the number of rows=(W−1). The worst case processing time, in this case, is W*Km. This occurs when W=29 and Km=16 and results in 464 cycles. If the processing time requirement permits it, the number of PE's could be made less than the total number of rows. The PE's could be allocated to a set of rows for part of the processing time and then reallocated to a different set of rows for the next part of the overall processing.
The approach set forth above assumes each of the equations (2) and (3) are processed separately and that the hardware will need to be duplicated for each of the equations. From Equation 2 and Equation 3 we see that the first multiplicand matrix is upper-triangular while the second matrix is lower triangular. We can combine the two matrices into a single matrix since there is no overlap between the two of them. This allows the processing of the two equations to be combined into one hardware process. FIG. 8 is a graphical representation of the combined processing.
The additional hardware consists of two (2) accumulators in each PE instead of 1, along with the associated control logic. Note that each PE performs a multiply and accumulate across a given row sequentially. Therefore, during any given clock cycle, only one of the two accumulators will be active and it will accumulate the results for either the upper triangular matrix multiply or for the lower one. By the end of a row, both accumulators have the results for both of the matrix multiplies.
The amount of hardware required to implement this function is directly related to the amount of time available for processing and to the bit widths used for the computations. Since the processing time and bit width requirements need not be firm, the design herein was chosen to be parameterized.
The parameterization occurs in two different aspects. First, the bit widths are parameterized allowing easy scaling of the design. Second, the amount of hardware used in parallel is also a parameter. The design is based on a basic processing element referred to as a PE. The number of required PE's depends on how parallel the design needs to be. Therefore, the number of PE's in the design is parameterized.
Note from the Equation 2 and Equation 3 that column i+1 in the matrices, is equal to column i shifted down by 1 row. This allows a simple architecture that uses a shift register 94 (see FIG. 9) to control the flow of the midamble data into the PE's. FIG. 9 is a block diagram of the midamble cancellation design.
In FIG. 9, there are 2 shift registers, an upper one 92 and a lower one 94. The lower shift register 94 supplies midamble data to each of the processing elements PE. The upper shift register supplies data to be shifted into the lower register 94. Timing and control is exerted by control circuit 102.
At the start of processing, the lower register 94 contains all of the data needed for the data field 1 calculation (lower triangular matrix—see FIG. 8). The upper register progressively supplies data for the data field 2 calculation (upper triangular matrix). At the completion of the processing, the lower shift register 94 contains all of the data needed for data field 2.
The size of the upper shift register 92 is fixed at 16 bits. The size of the lower shift register 94 is equal to the number of PE's and is therefore parameterized. The parameter can take on multiples of 16-bits. Each stage of the shift register contains one binary bit (0 or 1) which respectively control subtraction and addition operations.
Each shift register has a set of queue registers R that allow processing to be pipelined. The queue registers R are loaded with data from the next active midamble shift, by RAM 96 while the PEs process data stored in the working shift register 94 from the current midamble shift.
Note that data retrieved from the midamble RAM 96 is packed into 16-bit words before being stored into the shift registers 92, 94.
As set forth above, FIG. 5 is a simplified, high-level diagram of a PE in the midamble cancellation design. Note that there are two accumulators 104,106 however, some hardware is shared between the two processes. The PE “multiplies” the channel response vector by a midamble row at 108. The output selector controls the multiplexer 110 to select the contents of one of the accumulators 104, 106.
Since both the channel estimates and the midamble bits are complex-valued samples, the PEs need to perform complex arithmetic. However, a full multiplier is not necessary since the midamble value consists of a single bit.
According to 3GPP TS 25.221: m_{i}=(j)^{i}*m_{i }for all i=1, . . . , P
Therefore, the midamble sample represents 1 of 4 possible values:
1+0j
0+1j
−1+0j
0−1j
The channel estimate consists of a multi-bit complex value A+Bj.
Therefore, multiplying the channel responses by the midamble samples results in 1 of 4 possible outputs:
(A+Bj)(1+0j)=A+Bj
(A+Bj)(0+1j)=−B+Aj
(A+Bj)(−1+0j)=−A−Bj
(A+Bj)(0−1j)=B−Aj
From this we see that multiplication can be implemented with a pair of muxes (multiplexers) 120, 122 and a pair of adders/subtractors 124, 126, as shown in FIG. 6. The midamble bit value m_{i }at 128 controls the sign of the input (i.e. whether the samples get added or subtracted). The 2-bit phase at 130 controls how the inputs are muxed into the PE. The PE is initialized at 132, loading zeros into the accumulators 134, 136 through the multiplexers 131 each accumulating a real part REAL 1 and REAL 2 at 134a and 134b and an imaginary part Imag. 1 and Imag. 2 at 136a and 136b for each of the interference values, as shown at 36 and 38 in FIG. 4. Multiplexers 138 and 140 respectively select one of the values Real 1, REAL 2 and Imag. 1 and Imag. 2. Each value at the outputs of muxes 138, 140 is returned to the adder subtractors 124, 126 for the next addition/subtraction operation.
FIG. 10 graphically shows the matrix multiplication process and illustrates the role of a processing element in the midamble cancellation design. Each PE is assigned to a given row. It should be noted that each row contains data from both the lower-triangular and the upper triangular portions of the equations above. Therefore, the accumulators of each PE respectively contain data field 1 and data field 2 interference values at the end of the processing cycle for each row.
From a consideration of FIG. 8 it can be seen that a PE for the first row of the upper matrix U does not provide an output at that PE for the midamble associated with the left-hand-most column whereas there is an output at that PE for the left-hand most column of the first row of the lower matrix L. The PE assigned to the first row provides an output for all of the remaining columns for the lower matrix L and no outputs for the upper matrix U.
The pattern is repeated for each subsequent row wherein one more column position for each row yields an output for matrix U and one less column position yields an output for matrix L until, at the last row, there are no outputs for matrix L and all columns of the last row yield an output for matrix U.
For a given implementation of the MDC, the number of PE's may be less than the number of required calculations. In this case, the total number of rows is subdivided into sections whose size is the number of PE's. This is illustrated in FIG. 13. At the end of each processing step, the output data must be written out before the next process step begins. The processing step is repeated until all data has been processed. Note that the last processing steps may utilize less than the total number of PE's.
Table 2 shows the combined midamble matrix derived from combining Equation 2 and Equation 3 for a given midamble shift.
TABLE 2 |
Combined Midamble Matrix |
Note that the total number of midamble elements required for a given midamble shift consists of 0 to W−2 and L−(W−1) to L−1. Note also that since the midamble is repetitive, L−1 and 0 are contiguous. Therefore, the total elements required consist of a contiguous list from L−(W−1) to W−2. When a subset of the total rows is processed due to a limited number of PE's, the list of required elements remains contiguous since only the start and end points are altered. Therefore, retrieving midamble samples can be simplified by establishing a start point and sequentially retrieving data until all the required data has been retrieved. This simplifies the midamble packer control logic.
In reality, midamble cancellation establishes the end point and retrieves samples in reverse order. This is because the lower triangular matrix is processed first.
Note that the indices listed above are all relative to the basic midamble offsets for a particular midamble shift. The absolute midamble indices are discussed below.
FIG. 12 shows an example of how midamble cancellation calculates a midamble sample for burst type 2. As stated above, MDC requests an entire basic midamble sequence (of length P) from the midamble server at the start of processing and stores it in a local RAM. A specific user's midamble consists of L samples of a cyclically shifted version of the basic midamble.
MDC creates a shifted midamble sequence by addressing the midamble RAM in a circular fashion. The starting point is based on the midamble shift number.
Table 3 lists the equations from two (2) different versions of third generation (3G) specifications that define how to generate the initial midamble offsets based on the basic midamble. Both versions are shown as a reference, depending on what version is used for Spin 1 of the design. Table 4 and Table 5 list the initial offset values calculated from the corresponding equations for both long and short midamble, respectively.
TABLE 3 | ||
Equations to Calculate Midamble Shifts | ||
From TS 25.221 | ||
v3.3.0 | ||
Eq. 1(K′ − k)W | k = 1 to K′ | |
Eq. 2(K − k)W + floor(P/K) | k = K′ + 1 to K | |
From TS 25.221 | ||
v4.1.0 | ||
Eq. 1(K′ − k)W | k = 1 to K′ | |
Eq. 2(K − k − 1)W + floor(P/K) | k = K′ + 1 to K − 1 | |
Eq. 3(K′ − 1)W + floor(P/K) | k = K | |
TABLE 4 | ||
Initial Midamble Offsets for Long Midambles | ||
assumes: K′ = 8, K = 16, W = 57, P = 456, L = 512 | ||
k | v3.3.0 | v4.1.0 |
1 | 399 | 399 |
2 | 342 | 342 |
3 | 285 | 285 |
4 | 228 | 228 |
5 | 171 | 171 |
6 | 114 | 114 |
7 | 57 | 57 |
8 | 0 | 0 |
9 | 427 | 370 |
10 | 370 | 313 |
11 | 313 | 256 |
12 | 256 | 199 |
13 | 199 | 142 |
14 | 142 | 85 |
15 | 85 | 28 |
16 | 28 | 427 |
TABLE 5 | ||
Initial Midamble Offsets for Short Midambles | ||
assumes: K′ = 3, K = 6, W = 64, P = 192, L = 256 | ||
k | v3.3.0 | v4.1.0 |
1 | 128 | 128 |
2 | 64 | 64 |
3 | 0 | 0 |
4 | 160 | 96 |
5 | 96 | 32 |
6 | 32 | 160 |
FIG. 13 illustrates the processing timeline that corresponds to the block diagram.
Step 1: At the beginning of Steiner processing, CHEST kicks off the midamble cancellation preload process. During this process, midamble cancellation requests the entire basic midamble sequence from the midamble server and stores it into a local RAM.
Step 2: After post-processing is complete, CHEST kicks off midamble cancellation main processing. During this process, midamble cancellation retrieves midamble samples and channel responses for each active midamble shift.
Step 3: At the end of processing, each PE contains 2 accumulators full of data. The first accumulator from each PE (corresponding to data field 1 results) is sequentially muxed out and stored into RAMs (See RAM 82 and 84—FIG. 7). Next, the second accumulator (data field 2 results) from each processing element is muxed out sequentially and stored (RAMs 86 and 88).
Steps 4, 5: If the number of processing elements is less than W−1, steps 2 and 3 are repeated until all of the required processing is complete.
The following is a description of the processing flow and the finite state machines that control various processes within the midamble cancellation function.
FIG. 14 illustrates the processing that takes place for the midamble cancellation function. This is similar to the processing timeline shown in FIG. 13, but breaks down the control processes required.
There are two (2) control signals that start MDC processing. The first signal starts the MDC preload process (S1). The second control signal kicks off the MDC main processing (S2).
The available processing elements (PEs) are each assigned to process one row of the matrix multiplication (S3). If the total number of PE's is less than the total number of rows (W−1), then the PE's will be assigned to a first set of rows. Once processing is complete for this set of rows, the PE's will be reassigned to the next set of rows. This is repeated until all of the rows have been processed.
The next step is to loop through each midamble shift in order to look for an active midamble (S4). When an active shift is found, the matrix multiplication continues (S5).
The multiplication continues for the entire midamble sequence for the current shift. This continues until all midamble shifts have been processed. Once all of the active midamble shifts have been processed (S6), data is available for both data field 1 and data field 2 (S7). The data is sequentially output and written into the output RAMs.
The entire process is repeated until all W−1 rows are processed (S8).
The state machines, shown in FIGS. 15 through 20, control the processes depicted in the flowchart of FIG. 16.
The preload state machine, FIG. 15, requests the current midamble number from the midamble server and stores the data into a local RAM. The process is complete when the entire sequence is stored.
The preprocessor, FIG. 16, sequences through the active midamble parameter in order to count up the total number of active midambles that need to be processed.
The processing element state machine, FIG. 17, keeps track of the number of rows that have been processed and which PE's are assigned to each row. This state machine continues processing until all rows of the midamble cancellation matrix have been processed.
The midamble shift state machine, FIG. 18, sequences through each midamble shift in order to process each active shift. As the shift number is incremented, this state machine checks whether the current shift is active or not. If the midamble shift is active, the data packer state machine is kicked off in order to retrieve the midamble data. Once all of the midamble shifts have been processed, this state machine kicks off the data output state machine.
The midamble data packer state machine, FIG. 19, is responsible for retrieving midamble data from the local RAM and packing it into 16-bit words. The order in which the data is retrieved from RAM is based on the current midamble shift.
The data output state machine, FIG. 20, is responsible for writing the midamble cancellation output data sequentially into RAM. All of the data field 1 results are written first. The data field 2 results are written next.
The internal bit widths were chosen to accommodate the following maximum parameters:
TABLE 6 | |||||
Table of Processing Times for Various Parameters | |||||
K = 4 | K = 8 | K = 16 | K = 3 | K = 6 | |
NPEs | W = 114 | W = 57 | W = 29 | W = 64 | W = 32 |
16 | 4427 | 2221 | 1135 | 1013 | 511 |
32 | 2380 | 1181 | 610 | 578 | 295 |
48 | 1887 | 1205 | 610 | 581 | 295 |
64 | 1397 | 715 | 610 | 365 | 295 |
Table 6 lists the number of clock cycles required to perform midamble cancellation for the given parameters. The measurements were taken from the start of processing, excluding the midamble preload from the midamble server.