Johnson, Brian (Boise, ID)
Harrison, Ronnie M. (Boise, ID)

09/896030

06/28/2001

10/05/2004

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MICRON TECHNOLOGY INC (US)

711/167

713/503, 713/400

G06F13/16; G11C29/02; G06F1/12; G06F12/00

365/233, 713/600, 713/401, 711/167, 713/503, 713/400

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5150186		Pinney et al.	357/42	CMOS output pull-up driver
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5212601		Wilson	360/51	Disk drive data synchronizer with window shift synthesis
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5233564		Ohshima et al.	365/230.05	Multiport memory with test signal generating circuit controlling data transfer from RAM port to SAM port
5239206		Yanai	307/272.2	Synchronous circuit with clock skew compensating function and circuits utilizing same
5243703		Farmwald et al.	395/325	Apparatus for synchronously generating clock signals in a data processing system
5254883		Horowitz et al.	307/443	Electrical current source circuitry for a bus
5256989		Parker et al.	331/1A	Lock detection for a phase lock loop
5257294		Pinto et al.	375/120	Phase-locked loop circuit and method
5268639		Gasbarro et al.	324/158R	Testing timing parameters of high speed integrated circuit devices
5272729		Bechade et al.	375/118	Clock signal latency elimination network
5274276		Casper et al.	307/443	Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit
5276642		Lee	365/189.04	Method for performing a split read/write operation in a dynamic random access memory
5278460		Casper	307/296.5	Voltage compensating CMOS input buffer
5281865		Yamashita et al.	307/279	Flip-flop circuit
5283631		Koerner et al.	307/451	Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
5289580		Latif et al.	395/275	Programmable multiple I/O interface controller
5295164		Yamamura	375/120	Apparatus for providing a system clock locked to an external clock over a wide range of frequencies
5304952		Quiet et al.	331/1A	Lock sensor circuit and method for phase lock loop circuits
5311481		Casper et al.	365/230.06	Wordline driver circuit having a directly gated pull-down device
5311483		Takasugi	365/233	Synchronous type semiconductor memory
5313431		Uruma et al.	365/230.05	Multiport semiconductor memory device
5315269		Fujii	331/1A	Phase-locked loop
5315388		Shen et al.	348/718	Multiple serial access memory for use in feedback systems such as motion compensated television
5321368		Hoelzle	328/63	Synchronized, digital sequential circuit
5337285		Ware et al.	365/227	Method and apparatus for power control in devices
5341405		Mallard, Jr.	375/120	Data recovery apparatus and methods
5347177		Lipp	307/443	System for interconnecting VLSI circuits with transmission line characteristics
5347179		Casper et al.	307/451	Inverting output driver circuit for reducing electron injection into the substrate
5355391		Horowitz et al.	375/36	High speed bus system
5361002		Casper	327/530	Voltage compensating CMOS input buffer
5367649		Cedar	395/375	Programmable controller
5379299		Schwartz	370/108	High speed propagation delay compensation network
5390308		Ware et al.	395/400	Method and apparatus for address mapping of dynamic random access memory
5400283		Raad	365/203	RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver
5402389		Flannagan et al.	365/233	Synchronous memory having parallel output data paths
5408640		MacIntyre et al.	395/550	Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes
5410263		Waizman	327/141	Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle
5416436		Rainard	327/270	Method for time delaying a signal and corresponding delay circuit
5416909		Long et al.	395/275	Input/output controller circuit using a single transceiver to serve multiple input/output ports and method therefor
5420544		Ishibashi	331/11	Semiconductor integrated circuit, method of designing the same and method of manufacturing the same
5428311		McClure	327/276	Fuse circuitry to control the propagation delay of an IC
5428317		Sanchez et al.	331/1A	Phase locked loop with low power feedback path and method of operation
5430408		Ovens et al.	327/407	Transmission gate circuit
5430676		Ware et al.	365/189.02	Dynamic random access memory system
5432823		Gasbarro et al.	375/356	Method and circuitry for minimizing clock-data skew in a bus system
5438545		Sim	365/189.05	Data output buffer of semiconductor memory device for preventing noises
5440260		Hayashi et al.	327/278	Variable delay circuit
5440514		Flannagan et al.	365/194	Write control for a memory using a delay locked loop
5444667		Obara	365/233	Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals
5446696		Ware et al.	365/222	Method and apparatus for implementing refresh in a synchronous DRAM system
5448193		Baumert et al.	327/156	Normalization of apparent propagation delay
5451898		Johnson	327/563	Bias circuit and differential amplifier having stabilized output swing
5457407		Shu et al.	326/30	Binary weighted reference circuit for a variable impedance output buffer
5465076		Yamauchi et al.	331/179	Programmable delay line programmable delay circuit and digital controlled oscillator
5473274		Reilly et al.	327/159	Local clock generator
5473575		Farmwald et al.	365/230.06	Integrated circuit I/O using a high performance bus interface
5473639		Lee et al.	375/376	Clock recovery apparatus with means for sensing an out of lock condition
5485490		Leung et al.	375/371	Method and circuitry for clock synchronization
5488321		Johnson	327/66	Static high speed comparator
5489864		Ashuri	327/161	Delay interpolation circuitry
5497127		Sauer	331/17	Wide frequency range CMOS relaxation oscillator with variable hysteresis
5497355		Mills et al.	365/230.08	Synchronous address latching for memory arrays
5498990		Leung et al.	327/323	Reduced CMOS-swing clamping circuit for bus lines
5500808		Wang	364/578	Apparatus and method for estimating time delays using unmapped combinational logic networks
5502672		Kwon	365/189.05	Data output buffer control circuit
5506814		Hush et al.	365/230.03	Video random access memory device and method implementing independent two WE nibble control
5508638		Cowles et al.	326/38	Low current redundancy fuse assembly
5513327		Farmwald et al.	395/309	Integrated circuit I/O using a high performance bus interface
5532714		Knapp et al.	345/114	Method and apparatus for combining video images on a pixel basis
5539345		Hawkins	327/150	Phase detector apparatus
5544124		Zagar et al.	365/230.08	Optimization circuitry and control for a synchronous memory device with programmable latency period
5544203		Casasanta et al.	375/376	Fine resolution digital delay line with coarse and fine adjustment stages
5550783		Stephens, Jr. et al.	365/233	Phase shift correction circuit for monolithic random access memory
5552727		Nakao	327/159	Digital phase locked loop circuit
5555429		Parkinson et al.	395/800	Multiport RAM based multiprocessor
5557224		Wright et al.	327/115	Apparatus and method for generating a phase-controlled clock signal
5557781		Stones et al.	395/550	Combination asynchronous cache system and automatic clock tuning device and method therefor
5563546		Tsukada	327/408	Selector circuit selecting and outputting voltage applied to one of first and second terminal in response to voltage level applied to first terminal
5568075		Curran et al.	327/172	Timing signal generator
5568077		Sato et al.	327/199	Latch circuit
5572557		Aoki	375/376	Semiconductor integrated circuit device including PLL circuit
5572722		Vogley	395/555	Time skewing arrangement for operating random access memory in synchronism with a data processor
5574698		Raad	365/230.06	Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver
5576645		Farwell	327/94	Sample and hold flip-flop for CMOS logic
5577079		Zenno et al.	375/373	Phase comparing circuit and PLL circuit
5577236		Johnson et al.	395/551	Memory controller for reading data from synchronous RAM
5578940		Dillon et al.	326/30	Modular bus with single or double parallel termination
5578941		Sher et al.	326/34	Voltage compensating CMOS input buffer circuit
5579326		McClure	371/61	Method and apparatus for programming signal timing
5581197		Motley et al.	326/30	Method of programming a desired source resistance for a driver stage
5589788		Goto	327/276	Timing adjustment circuit
5590073		Arakawa et al.	365/185.08	Random access memory having flash memory
5594690		Rothenberger et al.	365/189.01	Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator
5614855		Lee et al.	327/158	Delay-locked loop
5619473		Hotta	365/238.5	Semiconductor memory device with dual address memory read amplifiers
5621340		Lee et al.	327/65	Differential comparator for amplifying small swing signals to a full swing output
5621690		Jungroth et al.	365/200	Nonvolatile memory blocking architecture and redundancy
5621739		Sine et al.	371/22.1	Method and apparatus for buffer self-test and characterization
5627780		Malhi	365/185.09	Testing a non-volatile memory
5627791		Wright et al.	365/222	Multiple bank memory with auto refresh to specified bank
5631872		Naritake et al.	365/227	Low power consumption semiconductor dynamic random access memory device by reusing residual electric charge on bit line pairs
5636163		Furutani et al.	365/233	Random access memory with a plurality amplifier groups for reading and writing in normal and test modes
5636173		Schaefer	365/230.03	Auto-precharge during bank selection
5636174		Rao	365/230.03	Fast cycle time-low latency dynamic random access memories and systems and methods using the same
5638335		Akiyama et al.	365/230.03	Semiconductor device
5646904		Ohno et al.	365/233	Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed
5652530		Ashuri	326/93	Method and apparatus for reducing clock-data skew by clock shifting
5657289		Hush et al.	365/230.05	Expandable data width SAM for a multiport RAM
5657481		Farmwald et al.	395/551	Memory device with a phase locked loop circuitry
5663921		Pascucci et al.	365/233	Internal timing method and circuit for programmable memories
5666322		Conkle	365/233	Phase-locked loop timing controller in an integrated circuit memory
5668763		Fujioka et al.	365/200	Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks
5668774		Furatani	365/233	Dynamic semiconductor memory device having fast operation mode and operating with low current consumption
5673005		Pricer	331/1R	Time standard circuit with delay line oscillator
5675274		Kobayashi et al.	327/158	Semiconductor clock signal generation circuit
5675588		Maruyama et al.	371/20.4	Testing apparatus for transmission system
5692165		Jeddeloh et al.	395/551	Memory controller with low skew control signal
5694065		Hamasaki et al.	327/108	Switching control circuitry for low noise CMOS inverter
5708611		Iwamoto	365/233X	Synchronous semiconductor memory device
5712580		Baumgartner et al.	327/12	Linear phase detector for half-speed quadrature clocking architecture
5719508		Daly	327/12	Loss of lock detector for master timing generator
5737342		Ziperovich	371/25.1	Method for in-chip testing of digital circuits of a synchronously sampled data detection channel
5740123		Uchida	365/233	Semiconductor integrated circuit for changing pulse width according to frequency of external signal
5751665		Tanoi	368/120	Clock distributing circuit
5767715		Marquis et al.	327/159	Method and apparatus for generating timing pulses accurately skewed relative to clock
5768177		Sakuragi	365/194	Controlled delay circuit for use in synchronized semiconductor memory
5774699		Nagae	395/551	System controller for controlling switching operations of various operation clocks for CPU, DRAM, and the like
5778214		Taya et al.	395/551	Bit-phase aligning circuit
5781499		Koshikawa	365/233	Semiconductor memory device
5784422		Heermann	375/355	Apparatus and method for accurate synchronization with inbound data packets at relatively low sampling rates
5789947		Sato	327/3	Phase comparator
5790612		Chengson et al.	375/373	System and method to reduce jitter in digital delay-locked loops
5794020		Tanaka et al.	395/552	Data transfer apparatus fetching reception data at maximum margin of timing
5805931		Morzano et al.	395/884	Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols
5812619		Runaldue	375/376	Digital phase lock loop and system for digital clock recovery
5822314		Chater-Lea	370/337	Communications system and method of operation
5831929		Manning	365/233	Memory device with staggered data paths
5841707		Cline et al.	365/194	Apparatus and method for a programmable interval timing generator in a semiconductor memory
5852378		Keeth	327/171	Low-skew differential signal converter
5872959		Nguyen et al.	395/552	Method and apparatus for parallel high speed data transfer
5889829		Chiao et al.	375/376	Phase locked loop with improved lock time and stability
5898242		Peterson	327/278	Self-calibrating clock circuit employing a continuously variable delay module in a feedback loop
5898674		Mawhinney et al.	370/247	System and method for performing non-disruptive diagnostics through a frame relay circuit
5917760		Millar	365/194	De-skewing data signals in a memory system
5920518		Harrison et al.	365/233	Synchronous clock generator including delay-locked loop
5926047		Harrison	327/159	Synchronous clock generator including a delay-locked loop signal loss detector
5926436		Toda et al.	365/236	Semiconductor memory device
5940608		Manning	395/551	Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
5940609		Harrison	395/559	Synchronous clock generator including a false lock detector
5946244		Manning	365/194	Delay-locked loop with binary-coupled capacitor
5953284		Baker et al.	365/233	Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
5964884		Partovi et al.	713/503	Self-timed pulse control circuit
5990719		Dai et al.	327/244	Adaptive filtering scheme for sampling phase relations of clock networks
6005823		Martin et al.	365/230.08	Memory device with pipelined column address path
6011732		Harrison et al.	365/194	Synchronous clock generator including a compound delay-locked loop
6014042		Nguyen	327/3	Phase detector using switched capacitors
6016282		Keeth	365/233	Clock vernier adjustment
6023489		Hatch	375/208	Method and apparatus for code synchronization in a global positioning system receiver
6026050		Baker et al.	635/233	Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
6026134		Duffy et al.	375/376	Phase locked loop (PLL) with linear parallel sampling phase detector
6029250		Keeth	713/400	Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
6038219		Mawhinney et al.	370/242	User-configurable frame relay network
6067592		Farmwald et al.	710/104	System having a synchronous memory device
6087857		Wang	327/5	Clock signal phase comparator
6101152		Farmwald et al.	365/233	Method of operating a synchronous memory device
6101197		Keeth et al.	370/517	Method and apparatus for adjusting the timing of signals over fine and coarse ranges
6105157		Miller	714/744	Salphasic timing calibration system for an integrated circuit tester
6147905		Seino	365/185.11	Non-volatile semiconductor memory device
6147916		Ogura	365/203	Semiconductor memory device with precharge voltage correction circuit
6160423		Haq	327/41	High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
6253360		Yoshiba	716/6	Timing generator
6262921		Manning	365/194	Delay-locked loop with binary-coupled capacitor
6269451		Mullarkey	713/401	Method and apparatus for adjusting data timing by delaying clock signal
6285726		Gaudet	375/376	10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports
6295328		Kim et al.	375/376	Frequency multiplier using delayed lock loop (DLL)
6298450		Liu et al.	713/502	Detecting states of signals
6327196		Mullarkey	365/194	Synchronous memory device having an adjustable data clocking circuit
6327318		Bhullar et al.	375/374	Process, voltage, temperature independent switched delay compensation scheme
6338127		Manning	711/167	Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
6377646		Sha	375/376	Spread spectrum at phase lock loop (PLL) feedback path
6378079		Mullarkey	713/401	Computer system having memory device with adjustable data clocking
6499111		Mullarkey	713/401	Apparatus for adjusting delay of a clock signal relative to a data signal

EP0171720				Data delay/memory circuit.
EP0295515				Signal generating apparatus.
EP0406786				Device for transforming a type "D" flip-flop into a flip-flop called type "B" able to sample data both on leading and trailing edges of the clock signal.
EP0450871				Interfaces for transmission lines.
EP0476585				Reference delay generator and electronic device using the same.
EP0655741				Memory device and serial-parallel data transform circuit.
EP0655834				Delay circuit using capacitor and transistor.
EP0680049				Synchronizer.
EP0703663				Programmable digital delay unit
EP0704848				Semiconductor pipeline memory device eliminating time loss due to difference between pipeline stages from data access
EP0704975				Digital phase locked loop having coarse and fine stepsize variable delay lines
EP0767538				Method and device for generating a signal
JP61237512				SEMICONDUCTOR INTEGRATED CIRCUIT
JP2112317
JP4135311
JP5136664
JP5282868
JP07319577				AUTOMATIC CLOCK PHASE ADJUSTING SYSTEM AND DUPLEX DATA PROCESSOR WITH AUTOMATIC CLOCK PHASE ADJUSTING FUNCTION
WO/1994/029871				METHOD AND APPARATUS FOR WRITING TO MEMORY COMPONENTS
WO/1995/022200				VOLTAGE CONTROLLED PHASE SHIFTER WITH UNLIMITED RANGE
WO/1995/022206				DELAY-LOCKED LOOP
WO/1996/010866				CMOS DYNAMIC LATCHING INPUT BUFFER CIRCUIT
WO/1997/014289				PROTOCOL FOR COMMUNICATION WITH DYNAMIC MEMORY
WO/1997/042557				ASYNCHRONOUS REQUEST/SYNCHRONOUS DATA DYNAMIC RANDOM ACCESS MEMORY

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Portka, Gary

Dorsey & Whitney LLP

What is claimed is:

1. A method of transferring digital signal packets out of a packetized memory device on a data bus, each digital signal packet including at least one packet word including a plurality of digital signals that are applied to respective latches in the packetized memory device, the method comprising: placing the packetized memory device in a synchronization mode of operation; generating a data clock signal responsive to a read clock signal and applying the data clock signal on a corresponding line of the data bus; generating a plurality of internal clock signals responsive to the read clock signal, each internal clock signal having a phase shift relative to the data clock signal; storing for each digital signal a phase command in a corresponding storage circuit associated with the digital signal, the phase command having a value corresponding to one of the internal clock signals; placing each digital signal on a corresponding data bus line responsive to the internal clock signal corresponding to the phase command stored in the associated storage circuit; receiving a phase adjustment command corresponding to a particular digital signal that is being synchronized, the phase adjustment command containing adjustment information for the phase command associated with the digital signal; adjusting the value of the phase command stored in the storage circuit associated with the digital signal being synchronized responsive to the phase adjustment command until the value of the phase command defines a timing offset between the digital signal and the data clock that allows an external device to successfully capture the digital signal responsive to the data clock signal; and repeating the operations of placing each digital signal on a corresponding bus line to adjusting the value of the phase command signal for each digital signal in the packet word.

2. The method of claim 1 wherein the values of the phase commands for all the digital signals are adjusted in parallel.

3. The method of claim 1 wherein adjusting the value of the phase command stored in the storage circuit comprises reading an initial value of the phase command from the storage circuit, incrementing or decrementing the values of the initial phase command response to the phase or adjustment command, to generate a new phase command, and storing the new phase command in the storage circuit.

4. The method of claim 1 wherein each storage circuit comprises a register.

5. The method of claim 1 wherein placing the packetized memory device in the synchronization mode comprises capturing a FLAG signal and generating a calibration signal when the FLAG signal has a predetermined binary value for two consecutive captures.

6. The method of claim 1 wherein adjusting the value of the phase command stored in the storage circuit associated with the digital signal being synchronized comprises: repetitively placing digital signals having expected values onto the corresponding data bus line; evaluating the digital signal captured responsive to the data clock signal to determine if captured digital signal has the expected value; identifying each phase command that caused the associated digital signal having the expected value to be captured; selecting a phase command for each digital signal from one of the phases that caused the associated digital signal having the expected value to be captured; and storing the selected phase command in the corresponding register.

7. The method of claim 6 wherein the operations of evaluating the captured digital signal to determine if the stored digital signal has the expected value through storing the selected phase command in the corresponding register are performed sequentially on each of the digital signals to sequentially select a phase command associated with each digital signal.

8. The method of claim 6 wherein evaluating the captured digital signal to determine if the digital signal has the expected value comprises: capturing the digital signal responsive to the data clock signal; generating expected values for the digital signal responsive to the values of the captured digital signal; and determining that the digital signal was successfully captured when the values of the captured digital signal corresponds to the generated expected values for the digital signal.

9. A method of adaptively adjusting respective timing offsets of a plurality of digital signals relative to a clock signal being output along with the digital signals to enable a circuit receiving the digital signals successfully to each of the digital signals responsive to the clock signal, the method comprising: storing in a respective storage circuit associated with each digital signal a corresponding phase command, the phase command defining a particular timing offset between the corresponding digital signal and the clock signal; outputting the clock signal; outputting each digital signal having the timing offset defined by the corresponding phase command; capturing the digital signals responsive to the clock signal; evaluating the captured digital signals to determine if each digital signal was successfully captured; generating a phase adjustment command to adjust the value of each phase command; repeating the operations of outputting the clock signal through generating a phase adjustment command for a plurality of phase adjustment commands for each digital signal; selecting for each digital signal a phase command that causes the digital signal to be successfully captured; and storing in the storage circuit associated with each digital signal the corresponding selected phase command.

10. The method of claim 9 wherein the operations of outputting a clock signal through generating a phase adjustment command are performed in parallel on all the digital signals.

11. The method of claim 9 wherein generating a phase adjustment command to adjust the value of each phase command comprises reading an initial value of the phase command from the storage circuit, incrementing or decrementing the values of the initial phase command in response to the phase adjustment command, to generate a new phase command, and storing the new phase command in the storage circuit.

12. The method of claim 9 wherein each storage circuit comprises a register.

13. The method of claim 9 wherein the clock signal corresponds to a data clock signal output from a packetized memory device and each digital signal corresponds to a data signal applied on a data bus of the packetized memory device.

14. The method of claim 12 wherein outputting each digital signal having the timing offset defined by the corresponding phase command comprises outputting a repeating 15 bit pseudo-random bit sequence of “111101011001000” for each digital signal, with the timing offset of this sequence being defined by the phase command.

15. The method of claim 12 wherein capturing the digital signals responsive to the clock signal comprises capturing the digital signals responsive to the rising and falling edges of the clock signal.

16. A read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal, the read synchronization circuit comprising: a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal, and each latch circuit storing a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal; a plurality of phase command registers, each phase command register storing a phase command and each register being associated with at least one of the latch circuits; a clock generation circuit coupled to latch circuits and the phase command registers, the clock generation circuit generating a plurality of internal clock signals and the external data clock signal responsive to a read clock signal, each internal clock signal and the external clock signal having a respective phase shift relative to the read clock signal, and the clock generation circuit selecting one of the internal clock signals for each latch circuit in response to the associated phase command and applying the selected internal clock signal to the clock terminal of the latch circuit to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal; and a control circuit coupled to the clock generation circuit and the phase command registers, the control circuit operable in response to a synchronization command to apply synchronization digital signals on the inputs of the latch circuits and to adjust the respective timing offsets between the external data clock signal and the synchronization digital signals output by each latch circuit by adjusting the respective values of the phase commands, and storing final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal.

17. The read synchronization circuit of claim 16 wherein the control circuit comprises: a read data pattern generator that generates the synchronization digital signals, each signal being a repeating pseudo-random bit sequence; a command buffer and address capture circuit adapted to latch and output command-address signals applied on a command address bus; a command decoder and sequencer coupled to the output of the command buffer and address capture circuit that generates a plurality of control signals responsive to the latched command-address signals, and generates a phase adjustment command word responsive to adjustment signals included in the latched command-address signals, the phase adjustment command word including information identifying a particular digital signal; and an up/down phase counter-controller coupled to the command decoder and sequencer to receive the phase adjustment command word, and coupled to the phase command registers, the counter-controller adjusting the value of the phase command stored in the register associated with the identified digital signal responsive to the phase adjustment command word.

18. The read synchronization circuit of claim 17 wherein the counter-controller adjusts the value of the phase command stored in each register by first reading a present value of the stored phase command, incrementing or decrementing the present value of the phase command responsive to the phase adjustment command to develop a new phase command word, and thereafter storing the new phase command in the register.

19. The read synchronization circuit of claim 16 wherein the clock generation circuit comprises: a programmable delay clock generator that generates N internal clock signals responsive to the read clock signal; and a plurality of multiplexers, each multiplexer having an output coupled to a respective clock terminal of a corresponding latch circuit, a plurality of selection inputs coupled to the associated phase command register to receive the stored phase command, and having N inputs coupled to the programmable delay clock generator to receive the N internal clock signals, each multiplexer applying a selected one of the N internal clock signals to the clock terminal of the corresponding latch responsive to the phase command.

20. The read synchronization circuit of claim 19 wherein the programmable delay clock generator comprises a delay-locked loop circuit.

21. The read synchronization circuit of claim 16 wherein each latch circuit comprises a data latch and a buffer.

22. A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a control circuit adapted to receive external control signals and operable in response to the external control signals to generate a plurality of internal control signals; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to the internal control signals; a column address circuit adapted to receive or apply data to at least one of the memory cells in the selected row corresponding to the column address responsive to the internal control signals; a write data path circuit adapted to couple data between a data bus and the column address circuit responsive to the internal control signals; and a read data path circuit adapted to couple data between the data bus and the column address circuit responsive to the internal control signals, the read data path circuit comprising a read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal, the read synchronization circuit comprising: a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal, and each latch circuit storing a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal; a plurality of phase command registers, each phase command register storing a phase command responsive to a control signal and each register being associated with at least one of the latch circuits; a clock generation circuit coupled to latch circuits and the phase command registers, the clock generation circuit generating a plurality of internal clock signals and the external data clock signal responsive to a read clock signal, each internal clock signal and the external clock signal having a respective phase shift relative to the read clock signal, and the clock generation circuit selecting one of the internal clock signals for each latch circuit in response to the associated phase command and applying the selected internal clock signal to the clock terminal of the latch circuit to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal; and a synchronization control circuit coupled to the clock generation circuit and the phase command registers, the control circuit operable in response to the initialization signals to apply synchronization digital signals on the inputs of the latch circuits and to adjust the respective timing offsets between the external data clock signal and the synchronization digital signals output by each latch circuit by adjusting the respective values of the phase commands, and storing final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal.

23. The memory device of claim 22 wherein the control circuit comprises: a read data pattern generator that generates the synchronization digital signals, each bit having a repeating 15 bit pseudo-random bit sequence for the synchronization signals; a command buffer and address capture circuit adapted to latch and output command-address signals applied on a command address bus; a command decoder and sequencer coupled to the output of the command buffer and address capture circuit that generates a plurality of control signals responsive to the latched command-address signals, and generates a phase adjustment command word responsive to adjustment signals included in the latched command-address signals, the phase adjustment command word including information identifying a particular digital signal; and an up/down phase counter-controller coupled to the command decoder and sequencer to receive the phase adjustment command word, and coupled to the phase command registers, the counter-controller adjusting the value of the phase command stored in the register associated with the identified digital signal responsive to the phase adjustment command word.

24. The memory device of claim 23 wherein the counter-controller adjusts the value of the phase command stored in each register by first reading a present value of the stored phase command, incrementing or decrementing the present value of the phase command responsive to the phase adjustment command to develop a new phase command word, and thereafter storing the new phase command in the register.

25. The memory device of claim 22 wherein the clock generation circuit comprises: a programmable delay clock generator that generates N internal clock signals responsive to the read clock signal; and a plurality of multiplexers, each multiplexer having an output coupled to a respective clock terminal of a corresponding latch circuit, a plurality of selection inputs coupled to the associated phase command register to receive the stored phase command, and having N inputs coupled to the programmable delay clock generator to receive the N internal clock signals, each multiplexer applying a selected one of the N internal clock signals to the clock terminal of the corresponding latch responsive to the phase command.

26. The memory device of claim 25 wherein the programmable delay clock generator comprises a delay-locked loop circuit.

27. The memory device of claim 22 wherein each latch circuit comprises a data latch and a buffer.

28. The memory device of claim 22 wherein the memory device comprises a packetized dynamic random access memory device.

29. The memory device of claim 28 wherein the packetized dynamic random access memory device comprises an SLDRAM.

30. A memory system, comprising: a memory device, comprising, at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a control circuit adapted to receive external control signals and operable in response to the external control signals to generate a plurality of internal control signals; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to the internal control signals; a column address circuit adapted to receive or apply data to at least one of the memory cells in the selected row corresponding to the column address responsive to the internal control signals; a write data path circuit adapted to couple data between a data bus and the column address circuit responsive to the internal control signals; and a read data path circuit adapted to couple data between the data bus and the column address circuit responsive to the internal control signals, the read data path circuit comprising a read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal, the read synchronization circuit comprising: a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal, and each latch circuit storing a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal; a plurality of phase command registers, each phase command register storing a phase command responsive to a control signal and each register being associated with at least one of the latch circuits; a clock generation circuit coupled to latch circuits and the phase command registers, the clock generation circuit generating a plurality of internal clock signals and the external data clock signal responsive to a read clock signal, each internal clock signal and the external clock signal having a respective phase shift relative to the read clock signal, and the clock generation circuit selecting one of the internal clock signals for each latch circuit in response to the associated phase command and applying the selected internal clock signal to the clock terminal of the latch circuit to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal; and a synchronization control circuit coupled to the clock generation circuit and the phase command registers, the control circuit operable in response to the internal control signals to apply synchronization digital signals on the inputs of the latch circuits and to adjust the respective timing offsets between the external data clock signal and the synchronization digital signals output by each latch circuit by adjusting the respective values of the phase commands, and storing final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal; and a memory controller coupled to the memory device.

31. The memory system of claim 30 wherein the clock generation circuit comprises: a programmable delay clock generator that generates N internal clock signals responsive to the read clock signal; and a plurality of multiplexers, each multiplexer having an output coupled to a respective clock terminal of a corresponding latch circuit, a plurality of selection inputs coupled to the associated phase command register to receive the stored phase command, and having N inputs coupled to the programmable delay clock generator to receive the N internal clock signals, each multiplexer applying a selected one of the N internal clock signals to the clock terminal of the corresponding latch responsive to the phase command.

32. The memory system of claim 31 wherein the programmable delay clock generator comprises a delay-locked loop circuit.

33. The memory system of claim 30 wherein each latch circuit comprises a data latch and a buffer.

34. The memory system of claim 30 wherein the memory device comprises a packetized dynamic random access memory device.

35. The memory system of claim 34 wherein the packetized dynamic random access memory device comprises an SLDRAM.

36. The memory system of claim 30 wherein the memory device comprises a double-data rate memory device and the external data clock signal comprises a data strobe signal DQS.

37. An integrated circuit adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, comprising: a circuit adapted to receive a plurality of input signals applied to respective other of the terminals and to generate a plurality of output signals on respective other of the terminals; a read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal, the read synchronization circuit comprising: a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal, and each latch circuit storing a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal; a plurality of phase command registers, each phase command register storing a phase command responsive to a control signal and each register being associated with at least one of the latch circuits; a clock generation circuit coupled to latch circuits and the phase command registers, the clock generation circuit generating a plurality of internal clock signals and the external data clock signal responsive to a read clock signal, each internal clock signal and the external clock signal having a respective phase shift relative to the read clock signal, and the clock generation circuit selecting one of the internal clock signals for each latch circuit in response to the associated phase command and applying the selected internal clock signal to the clock terminal of the latch circuit to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal; and a control circuit coupled to the clock generation circuit and the phase command registers, the control circuit operable in response to a synchronization command to apply synchronization digital signals on the inputs of the latch circuits and to adjust the respective timing offsets between the external data clock signal and the synchronization digital signals output by each latch circuit by adjusting the respective values of the phase commands, and storing final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal.

38. The integrated circuit of claim 37 wherein the control circuit comprises: a read data pattern generator that generates the synchronization digital signals, each bit having a repeating 15 bit pseudo-random bit sequence for the synchronization digital signals; a command buffer and address capture circuit adapted to latch and output command-address signals applied on a command address bus; a command decoder and sequencer coupled to the output of the command buffer and address capture circuit that generates a plurality of control signals responsive to the latched command-address signals, and generates a phase adjustment command word responsive to adjustment signals included in the latched command-address signals, the phase adjustment command word including information identifying a particular digital signal; and an up/down phase counter-controller coupled to the command decoder and sequencer to receive the phase adjustment command word, and coupled to the phase command registers, the counter-controller adjusting the value of the phase command stored in the register associated with the identified digital signal responsive to the phase adjustment command word.

39. The integrated circuit of claim 38 wherein the counter-controller adjusts the value of the phase command stored in each register by first reading a present value of the stored phase command, incrementing or decrementing the present value of the phase command responsive to the phase adjustment command to develop a new phase command word, and thereafter storing the new phase command in the register.

40. The integrated circuit of claim 37 wherein the clock generation circuit comprises: a programmable delay clock generator that generates N internal clock signals responsive to the read clock signal; and a plurality of multiplexers, each multiplexer having an output coupled to a respective clock terminal of a corresponding latch circuit, a plurality of selection inputs coupled to the associated phase command register to receive the stored phase command, and having N inputs coupled to the programmable delay clock generator to receive the N internal clock signals, each multiplexer applying a selected one of the N internal clock signals to the clock terminal of the corresponding latch responsive to the phase command.

41. The integrated circuit of claim 40 wherein the programmable delay clock generator comprises a delay-locked loop circuit.

42. The integrated circuit of claim 37 wherein each latch circuit comprises a data latch and a buffer.

43. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor, comprising, at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a control circuit adapted to receive external control signals and operable in response to the external control signals to generate a plurality of internal control signals; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to the internal control signals; a column address circuit adapted to receive or apply data to at least one of the memory cells in the selected row corresponding to the column address responsive to the internal control signals; a write data path circuit adapted to couple data between a data bus and the column address circuit responsive to the internal control signals; and a read data path circuit adapted to couple data between the data bus and the column address circuit responsive to the internal control signals, the read data path circuit comprising a read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal, the read synchronization circuit comprising: a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal, and each latch circuit storing a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal; a plurality of phase command registers, each phase command register storing a phase command responsive to a control signal and each register being associated with at least one of the latch circuits; a clock generation circuit coupled to latch circuits and the phase command registers, the clock generation circuit generating a plurality of internal clock signals and the external data clock signal responsive to a read clock signal, each internal clock signal and the external clock signal having a respective phase shift relative to the read clock signal, and the clock generation circuit selecting one of the internal clock signals for each latch circuit in response to the associated phase command and applying the selected internal clock signal to the clock terminal of the latch circuit to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal; and a synchronization control circuit coupled to the clock generation circuit and the phase command registers, the control circuit operable in response to the internal control signals to apply synchronization digital signals on the inputs of the latch circuits and to adjust the respective timing offsets between the external data clock signal and the synchronization digital signals output by each latch circuit by adjusting the respective values of the phase commands, and storing final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal.

44. The computer system of claim 43 wherein the clock generation circuit comprises: a programmable delay clock generator that generates N internal clock signals responsive to the read clock signal; and a plurality of multiplexers, each multiplexer having an output coupled to a respective clock terminal of a corresponding latch circuit, a plurality of selection inputs coupled to the associated phase command register to receive the stored phase command, and having N inputs coupled to the programmable delay clock generator to receive the N internal clock signals, each multiplexer applying a selected one of the N internal clock signals to the clock terminal of the corresponding latch responsive to the phase command.

45. The computer system of claim 44 wherein the programmable delay clock generator comprises a delay-locked loop circuit.

46. The computer system of claim 43 wherein each latch circuit comprises a data latch and a buffer.

47. The computer system of claim 43 wherein the memory device comprises a packetized dynamic random access memory device.

48. The computer system of claim 47 wherein the packetized dynamic random access memory device comprises an SLDRAM.

49. The computer system of claim 43 wherein the memory device comprises a double-data rate memory device and the external data clock signal comprises a data strobe signal DQS.

50. A read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal, the read synchronization circuit comprising: a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal, and each latch circuit storing a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal; a plurality of phase command registers, each phase command register storing a phase command and each register being associated with one of the latch circuits; a programmable delay clock generator that develops N internal clock signals responsive to the read clock signal; a plurality of multiplexers, each multiplexer having an output coupled to a respective clock terminal of a corresponding latch circuit, a plurality of selection inputs coupled to an associated phase command register to receive the stored phase command, and N inputs coupled to the generator to receive the N internal clocks signals, respectively, the multiplexer applying a selected internal clock signal on the output to clock the corresponding latch circuit in response to the phase command; a read data pattern generator coupled to the inputs of the latch circuits, the generator applying a synchronization signal to each input; and an up/down phase counter-controller coupled to the read data pattern generator and the phase command registers, the counter-controller operable to adjust the values of the phase commands stored in the registers in response to received phase adjustment command words to thereby adjust the respective timing offsets between the external data clock signal and the synchronization signal being output by the latch circuits, and the counter-controller storing final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal.

51. The read synchronization circuit of claim 50 wherein the counter-controller adjusts the value of the phase command stored in each register by first reading a present value of the stored phase command, incrementing or decrementing the present value of the phase command responsive to the phase adjustment command to develop a new phase command word, and thereafter storing the new phase command in the register.

52. The read synchronization circuit of claim 50 wherein the programmable delay clock generator comprises a delay-locked loop circuit.

53. The read synchronization circuit of claim 50 wherein each latch circuit comprises a data latch and a buffer.

54. A read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and an external data clock signal to enable an external device to latch the digital signals responsive to the external data clock signal, the read synchronization circuit comprising: a plurality of data storage means for storing respective signals and providing the stored signals on respective signal terminals, each data storage means storing the signal applied on an input and providing the stored signal on the corresponding signal terminal responsive to a clock signal; a plurality of phase storage means for storing respective phase commands, each phase storage means being associated with one of the data storage means; a clock generation means coupled to the data storage means and the phase storage means for generating a plurality of internal clock signals and the external data clock signal responsive to a read clock signal, each internal clock signal and the external clock signal having a respective phase shift relative to the read clock signal, and the clock generation means including selection means for selecting one of the internal clock signals for each data storage means in response to the associated phase command and applying the selected internal clock signal as the clock signal to the data storage means to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal; and a control means coupled to the clock generation means and the phase storage means for receiving a synchronization command and, in response to the synchronization command, applying a respective synchronization digital signals to each storage means and adjusting the respective timing offsets between the external data clock signal and each of the synchronization digital signals being provided on the signal terminals by each storage means by adjusting the respective values of the phase commands stored in the phase storage means, and storing final phase commands in each phase storage means that allow the synchronization digital signals to be successfully captured responsive to the external data clock signal.

55. The read synchronization circuit of claim 54 wherein the control means comprises: a data pattern generation means for generating the synchronization digital signals, each signal being a repeating pseudo-random bit sequence; a command buffering and address capturing means for latching command-address signals applied on a command address bus; a command decoding and sequencing means coupled to the command buffering and address capturing means for generating a plurality of control signals responsive to the latched command-address signals, and generating a phase adjustment command word responsive to adjustment signals included in the latched command-address signals, the phase adjustment command word including information identifying a particular digital signal; and a phase counter-controller means coupled to the command decoding and sequencing means to receive the phase adjustment command word and coupled to the phase storage means, the counter-controller means adjusting the value of the phase command stored in the phase storage means associated with the identified digital signal responsive to the phase adjustment command word.

56. The read synchronization circuit of claim 55 wherein the counter-controller means adjusts the value of the phase command stored in each phase storage means by first reading a present value of the stored phase command, incrementing or decrementing the present value of the phase command responsive to the phase adjustment command to develop a new phase command word, and thereafter storing the new phase command in the phase storage means.

57. The read synchronization circuit of claim 54 wherein the clock generation means comprises: a programmable delay clock generation means for generating N internal clock signals responsive to the read clock signal; and a plurality of multiplexing means, each multiplexing means having an output coupled to a corresponding data storage means to apply the clock signal to the storage means and including a plurality of selection inputs coupled to the associated phase storage means to receive the stored phase command, and having N inputs coupled to the programmable delay clock generation means to receive the N internal clock signals, each multiplexing means applying a selected one of the N internal clock signals to the clock terminal of the corresponding data storage means responsive to the phase command.

58. The read synchronization circuit of claim 57 wherein the programmable delay clock generation means comprises a delay-locked loop means.

59. The read synchronization circuit of claim 54 wherein each data storage means comprises a latching means for storing data and a buffer means coupled to the latching means for providing the stored data on the corresponding signal terminal.

60. A memory system, comprising: a system clock generator that develops a system read data clock signal; a memory device coupled to the clock generator to receive the system read data clock signal, comprising, at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a control circuit adapted to receive external control signals and operable in response to the external control signals to generate a plurality of internal control signals; a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to the internal control signals; a column address circuit adapted to receive or apply data to at least one of the memory cells in the selected row corresponding to the column address responsive to the internal control signals; a write data path circuit adapted to couple data between a data bus and the column address circuit responsive to the internal control signals; and a read data path circuit adapted to couple data between the data bus and the column address circuit responsive to the internal control signals, the read data path circuit comprising a read synchronization circuit that adaptively adjusts respective timing offsets of a plurality of digital signals applied on respective signal terminals and the system read data clock signal to enable an external device to latch the digital signals responsive to the system read data clock signal, the read synchronization circuit comprising: a plurality of latch circuits, each latch circuit including an input, an output coupled to a respective signal terminal, and a clock terminal, and each latch circuit storing a signal applied on the input and providing the stored signal on the signal terminal responsive to a clock signal applied on the clock terminal; a plurality of phase command registers, each phase command register storing a phase command responsive to a control signal and each register being associated with at least one of the latch circuits; an internal clock generation circuit coupled to latch circuits and the phase command registers, the internal clock generation circuit generating a plurality of internal clock signals responsive to the system read data clock signal, each internal clock signal and the system read data clock signal having a respective phase shift relative to the system read data clock signal, and the internal clock generation circuit selecting one of the internal clock signals for each latch circuit in response to the associated phase command and applying the selected internal clock signal to the clock terminal of the latch circuit to place digital signals on the corresponding signal terminal with a timing offset determined by the phase shift of the selected internal clock signal; and a synchronization control circuit coupled to the internal clock generation circuit and the phase command registers, the control circuit operable in response to the internal control signals to apply synchronization digital signals on the inputs of the latch circuits and to adjust the respective timing offsets between the system read data clock signal and the synchronization digital signals output by each latch circuit by adjusting the respective values of the phase commands, and storing final phase commands in each phase command register that allow the synchronization digital signals to be successfully captured responsive to the system read data clock signal; and a memory controller coupled to the memory device and coupled to the system read clock generator to receive the system read data clock signal.

61. The memory system of claim 60 wherein the clock generation circuit comprises: a programmable delay clock generator that generates N internal clock signals responsive to the read clock signal; and a plurality of multiplexers, each multiplexer having an output coupled to a respective clock terminal of a corresponding latch circuit, a plurality of selection inputs coupled to the associated phase command register to receive the stored phase command, and having N inputs coupled to the programmable delay clock generator to receive the N internal clock signals, each multiplexer applying a selected one of the N internal clock signals to the clock terminal of the corresponding latch responsive to the phase command.

62. The memory system of claim 61 wherein the programmable delay clock generator comprises a delay-locked loop circuit.

63. The memory system of claim 60 wherein each latch circuit comprises a data latch and a buffer.

64. The memory system of claim 60 wherein the memory device comprises a packetized dynamic random access memory device.

65. The memory system of claim 64 wherein the packetized dynamic random access memory device comprises an SLDRAM.

66. The memory system of claim 60 wherein the memory device comprises a double-data rate memory device and the external data clock signal comprises a data strobe signal DQS.

TECHNICAL FIELD

The present invention relates generally to semiconductor memories and other integrated circuit devices, and is directed, more particularly, to synchronizing digital signals being transferred over buses interconnecting such devices.

BACKGROUND OF THE INVENTION

Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.

Processors generally operate at a relatively high speed. Processors such as the Pentium III® and Pentium 4® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a lower clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a substantially lower frequency. Currently, for example, a processor having a 1 GHz clock frequency may be mounted on a mother board having a 133 MHz clock frequency for controlling the system memory devices and other components.

Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 1 GHz, to read data from or write data to a system memory device operating at, for example, 133 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.

System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.

A solution to this operating speed disparity has been proposed in the form of a computer architecture known as a synchronous link architecture. In the synchronous link architecture, the system memory may be coupled to the processor either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, synchronous link memory devices receive command packets that include both control and address information. The synchronous link memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.

An example of a computer system 10 using the synchronous link architecture is shown in FIG. 1 . The computer system 10 includes a processor 12 having a processor bus 14 coupled through a memory controller 18 and system memory bus 23 to three packetized or synchronous link dynamic random access memory (“SLDRAM”) devices 16 a-c . The computer system 10 also includes one or more input devices 20 , such as a keypad or a mouse, coupled to the processor 12 through a bus bridge 22 and an expansion bus 24 , such as an industry standard architecture (“ISA”) bus or a peripheral component interconnect (“PCI”) bus. The input devices 20 allow an operator or an electronic device to input data to the computer system 10 . One or more output devices 30 are coupled to the processor 12 to display or otherwise output data generated by the processor 12 . The output devices 30 are coupled to the processor 12 through the expansion bus 24 , bus bridge 22 and processor bus 14 . Examples of output devices 24 include printers and a video display units. One or more data storage devices 38 are coupled to the processor 12 through the processor bus 14 , bus bridge 22 , and expansion bus 24 to store data in or retrieve data from storage media (not shown). Examples of storage devices 38 and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.

In operation, the processor 12 sends a data transfer command via the processor bus 14 to the memory controller 18 , which, in turn, communicates with the memory devices 16 a-c via the system memory bus 23 by sending the memory devices 16 a-c command packets that contain both control and address information. Data is coupled between the memory controller 18 and the memory devices 16 a-c through a data bus portion of the system memory bus 23 . During a read operation, data is transferred from the SLDRAMs 16 a-c over the memory bus 23 to the memory controller 18 which, in turn, transfers the data over the processor 14 to the processor 12 . The processor 12 transfers write data over the processor bus 14 to the memory controller 18 which, in turn, transfers the write data over the system memory bus 23 to the SLDRAMs 16 a-c . Although all the memory devices 16 a-c are coupled to the same conductors of the system memory bus 23 , only one memory device 16 a-c at a time reads or writes data, thus avoiding bus contention on the memory bus 23 . Bus contention is avoided by each of the memory devices 16 a-c on the system memory 22 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.

The computer system 10 also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices 16 a-c also receive a master clock signal to provide internal timing signals, a data clock signal clocking data into and out of the memory device 16 , and a FLAG signal signifying the start of a command packet.

A typical command packet CA<0:39> for an SLDRAM is shown in FIG. 2 and is formed by 4 packet words CA<0:9>, each of which contains 10 bits of data. As will be explained in more detail below, each packet word CA<0:9> is applied on a command-address bus CA including 10 lines CA0-CA9. In FIG. 2 , the four packet words CA<0:9> comprising a command packet CA<0:39> are designated PW 1 -PW 4 . The first packet word PW ₁ contains 7 bits of data identifying the packetized DRAM 16 a-c that is the intended recipient of the command packet. As explained below, each of the packetized DRAMs is provided with a unique ID code that is compared to the 7 ID bits in the first packet word PW ₁ . Thus, although all of the packetized DRAMs 16 a-c will receive the command packet, only the packetized DRAM 16 a-c having an ID code that matches the 7 ID bits of the first packet word PW ₁ will respond to the command packet.

The remaining 3 bits of the first packet word PW ₁ as well as 3 bits of the second packet word PW ₂ comprise a 6 bit command. Typical commands are read and write in a variety of modes, such as accesses to pages or banks of memory cells. The remaining 7 bits of the second packet word PW ₂ and portions of the third and fourth packet words PW ₃ and PW ₄ comprise a 20 bit address specifying a bank, row and column address for a memory transfer or the start of a multiple bit memory transfer. In one embodiment, the 20 bit address is divided into 3 bits of bank address, 10 bits of row address, and 7 bits of column address. Although the command packet shown in FIG. 2 is composed of 4 packet words PW 1 -PW 4 each containing up to 10 bits, it will be understood that a command packet may contain a lesser or greater number of packet words, and each packet word may contain a lesser or greater number of bits.

The memory device 16 a is shown in block diagram form in FIG. 3 . Each of the memory devices 16 a-c includes a clock generator circuit 40 that receives a command clock signal CCLK and generates a large number of other clock and timing signals to control the timing of various operations in the memory device 16 a . The memory device 16 a also includes a command buffer 46 and an address capture circuit 48 which receive an internal clock signal ICLK, a command packet CA<0:9> on a 10 bit command-address bus CA, and a terminal 52 receiving a FLAG signal. A memory controller (not shown) or other device normally transmits the command packet CA<0:9> to the memory device 16 a in synchronism with the command clock signal CCLK. As explained above, the command packet CA<0:39>, which generally includes four 10-bit packet words PW 1 -PW 4 , contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and also signals the start of an initialization sequence. The command buffer 46 receives the command packet from the command-address bus CA, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the memory device 16 a or some other memory device 16 b , c. If the command buffer 46 determines that the command is directed to the memory device 16 a , it then provides the command to a command decoder and sequencer 60 . The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16 a during a memory transfer.

The address capture circuit 48 also receives the command packet from the command-address bus CA and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer 64 , which generates a corresponding 3-bit bank address on bus 66 , a 10-bit row address on bus 68 , and a 7-bit column address on bus 70 . The row and column addresses are processed by row and column address paths, as will be described in more detail below.

One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The SLDRAM 16 a shown in FIG. 3 largely avoids this problem by using a plurality of memory banks 80 , in this case eight memory banks 80 a-h . After a read from one bank 80 a , the bank 80 a can be precharged while the remaining banks 80 b-h are being accessed. Each of the memory banks 80 a-h receives a row address from a respective row latch/decoder/driver 82 a-h . All of the row latch/decoder/drivers 82 a-h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90 . However, only one of the row latch/d