| WO/1996/001907 | July, 1996 | NOVEL p53 RESPONSE GENES |
This application is a continuation of application Ser. No. 09/378,505, filed on Aug. 20, 1999, which is a continuation of application Ser. No. 08/941,676, filed on Sep. 30, 1997, the entire disclosures of which are hereby incorporated by reference.
a plurality of memory cells each of which has a threshold voltage corresponding to data, wherein a threshold voltage of each of said plurality of memory cells is allocated in a threshold voltage area indicating one of an erasing state and a programming state, and
a controller setting a threshold voltage of a memory cell allocated in said threshold voltage area indicating said erasing state to said threshold voltage area indicating said programming state in accordance with a program command,
wherein said program command has a first program command and a second program command,
wherein a threshold voltage of a memory cell allocated in said threshold voltage area indicating said erasing state is set to a first threshold voltage area indicating said programming state in accordance with said first program command, thereafter,
said threshold voltage of said memory cell set to said first threshold voltage area in accordance with said first program command is set to a second threshold voltage area indicating said programming state in accordance with said second program command, and
wherein a width of said first threshold voltage area is different from a width of said second threshold voltage area.
a plurality of memory cells each of which has a threshold voltage corresponding to data indicating one of a program state and an erase state,
a controller controlling a program operation in accordance with a program command, and
a voltage generator generating a voltage in said program operation,
wherein said program command has a first program command and a second program command,
wherein said controller controls a first program operation in accordance with said first program command, and controls a second program operation in accordance with said second program command,
wherein said voltage generator generates a first program voltage and a first verify voltage in said first program operation, and generates a second program voltage and a second verify voltage in said second program operation,
wherein a threshold voltage of a memory cell applied with said first program voltage is changed so as to move to a first region across said first verify voltage in said first program operation, and a threshold voltage of a memory cell applied with said second program voltage is changed so as to move to a second region across said second verify voltage in said second program operation, and
wherein a value of said first verify voltage is different from a value of said second verify voltage.
a nonvolatile semiconductor memory;
a data output circuit outputting data to be stored in said nonvolatile semiconductor memory; and
a command supply circuit, said nonvolatile semiconductor memory including:
a plurality of memory cells each of which has a threshold voltage corresponding to data, wherein a threshold voltage of each of said plurality of memory cells is allocated in a threshold voltage area indicating one of an erasing state and a programming state, and
a controller setting a threshold voltage of a memory cell allocated in said threshold voltage area indicating said erasing state to a first threshold voltage area indicating said programming state by programming data outputted from said data output circuit,
wherein said controller sets said threshold voltage of said memory cell to said first threshold voltage area to a second threshold voltage area indicating said programming state when a reprogram command is supplied from said command supply circuit, and
wherein a width of said first threshold voltage area is different from a width of said second threshold voltage area.
a nonvolatile semiconductor memory;
a data output circuit outputting data to be stored in said nonvolatile semiconductor memory; and
a command supply circuit, said nonvolatile semiconductor memory including:
a plurality of memory cells each of which has a threshold voltage corresponding to data indicating one of a program state and an erase state,
a controller controlling a program operation, and
a voltage generator generating a voltage in said program operation,
wherein said controller controls a first program operation for programming data outputted from said data output circuit, and controls a second program operation in accordance with a reprogram command supplied from said command supply circuit,
wherein said voltage generator generates a first program voltage and a first verify voltage in said first program operation, and generates a second program voltage and a second verify voltage in said second program operation,
wherein a threshold voltage of a memory cell applied with said first program voltage is changed so as to move to a first region across said first verify voltage in said first program operation, and a threshold voltage of a memory cell applied with said second program voltage is changed so as to move to a second region across said second verify voltage in said second program operation, and
wherein a value of said first verify voltage is different from a value of said second verify voltage.
This invention relates to a semiconductor integrated circuit device, such as a flash memory or the like, and to a data processing system, such as a digital still camera, in which such a semiconductor integrated circuit device is employed.
An example of a flash memory device has been disclosed in the 1994 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 61-62.
In this flash memory, a state in which the threshold voltage of each of the memory cells included in the flash memory is high, and a state in which the threshold voltage thereof is low, can be defined as, for example, an erased state and a written (programmed) state, respectively. In this case, writing can be performed after erase operations have been performed collectively in word line units, for example. Upon completion of erase and write operations, the application of pulse-shaped voltages and a verify operation are repeatedly performed until a desired threshold voltage is acquired so that a change in threshold voltage is not increased undesirably.
When the application and transition of the voltage from the threshold voltage in the erased state to the threshold voltage in the written state has been completed, it is difficult to vary the threshold voltage as the threshold voltage approaches the written state. Therefore, the application of the same pulse width will lead to a state in which only the verify operation is being performed even though the threshold voltage changes very little. Therefore, when it is desired to perform writing using a fixed write voltage level, the pulse width is made long as the threshold voltage approaches the written state. The voltage may be gradually increased as an alternative to the gradual increase in pulse width.
High-accuracy writing has heretofore been realized so that a write level (equivalent to a verify word line voltage at writing) is set as, for example, 1.5V with respect to a power source voltage Vcc of, for example, 3.3V, and a write pulse or the threshold voltage of each memory cell varies over a range from 0.1V to 0.2V.
With respect to a power source voltage of, for example, 3.3V, a write level has heretofore been set practically to, for example, 1.5V, corresponding to about one half the power source voltage. One obtained by adding a difference in threshold voltage, for obtaining a current difference required to detect the voltage using a sense amplifier, to the voltage is defined as the minimum or lowest voltage (Vev) in an erased state. Upon erasing, the application of an erase pulse is controlled by detecting whether or not the threshold voltage of each memory cell has reached above Vev. A low voltage operation and high reliability can be achieved by lowering the write voltage and thereby reducing Vev to as low a level as possible.
However, the actual circumstances or fact is that the characteristic of each memory cell is varied by about three digits in the time required to reach a threshold voltage leading from an erased state to a written state when voltages to be applied upon writing are the same. When the writing of data into the corresponding memory cell is performed under such a condition, there may be cases where the threshold voltage results in 0V or less according to memory cells in the case of normal variations in characteristic of each memory cell unless a change in threshold voltage of the memory cell is set as a write pulse (width or voltage) that reaches 0.2V or less. The 3-digit variation results in about 3V if converted into a variation in equivalent threshold voltage. Thus, since the amount of change in threshold voltage per write pulse is equivalent to a change of 0.2V until the threshold voltage of a memory cell latest in written state reaches a written state, since the threshold voltage of a memory cell shortest in time required to bring it into the written state has led to the written state, it is necessary to apply a pulse 15 times if calculated simply. It is necessary to perform a verify operation for making a decision as to whether the threshold voltage has reached a desired value for each pulse. This has led to a lengthy overhead during the write time.
An object of the present invention is to speed up a write operation made to a non-volatile memory cell.
Another object of the present invention is to make the speeding up of a write operation made to a non-volatile memory cell compatible with a high reliability of data retention.
The above and other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical features disclosed in the present application will be described briefly as follows.
Namely, a semiconductor integrated circuit, such as a flash memory device, has a plurality of electrically erasable and programmable non-volatile memory cells and includes a control means for supplying a pulse-shaped voltage to each non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control means has a first operating mode in which the amount of change in threshold voltage of each non-volatile memory cell, which varies each time the pulse-shaped voltage is applied thereto, is relatively large, and a second operating mode in which the amount of change in threshold voltage thereof is relatively small.
The amount of change in threshold voltage of each memory cell per pulse in a write voltage pulse or write voltage pulse train in a first operating mode (coarse write) and the amount of change in threshold voltage per pulse in a second operating mode (high-accuracy write) are defined as ΔVth1 and ΔVth2, for example, respectively. considering at this time where the difference (cell window) in voltage between the minimum threshold corresponding to an erased state in a threshold voltage distribution of a non-volatile memory cell and the maximum threshold corresponding to a written state in the threshold voltage distribution is fixed, then the number of pulses required to change the threshold voltage of each memory cell at ΔVth1 is smaller than that at ΔVth2. Therefore, the number of verify operations at the time that the first operating mode (ΔVth1) is used, is smaller than when the second operating mode (ΔVth2) is used. The time required to perform writing corresponds to the sum of the time required to change the threshold voltage of each memory cell itself and an overhead time, such as the time required to perform the verify operation. Thus, since a decrease in the number of verify operations results in a reduction in overhead, the write operation is speeded up as a whole.
It is desirable for the level (threshold voltage) to be written into a memory cell in the first operating mode to be higher than that in the second operating mode. Namely, a threshold voltage distribution in a written state,at ΔVth1 in which the amount of change in threshold voltage is relatively large, becomes greater than a threshold voltage distribution in a written state at ΔVth2 in the second operating mode. Thus, doing so is desired to avoid depleting. In other words, it is desired that a write verify voltage in the first operating mode (coarse write) be set higher than a write verify voltage in the second operating mode (high-accuracy write). Even if the cell window in the first operating mode is not set equal to that in the second operating mode, an erase level written into a memory cell in the first operating mode as a tendency to become higher than an erase level written into a memory cell in the second operating mode. Thus, the electric field between a floating gate and a semiconductor substrate of the memory cell written in the second write operating mode is lower than that of the memory cell written in the first operating mode at the time of information retention. Further, the information retention time of the memory cell written in the second write operating mode is longer than that of the memory cell written in the first operating mode. Namely, the memory cell written in the second operating mode exhibits an excellent information retention performance. In this sense, the second operating mode can be placed or detained as a high-accuracy write mode.
The control means can be provided with a rewrite control means for rewriting data written in the first operating mode in the second operating mode. Namely, after the data has been written into each memory cell in the first operating mode of short write time, it is renewed or rewritten in the second operating mode capable of narrowing the distribution of the threshold voltage of the memory cell. With respect to rewriting, the data is read from the corresponding memory cell and latched in its corresponding sense latch, and the latched data is defined as data to be written in the second operating mode.
The coarse write based on the first operating mode and the high-accuracy write based on the second operating mode can be controlled by switching according to conditions, such as address areas, the number of cumulatings for reprogramming, etc. as well as switching control on the rewriting executed in the first and second operating modes.
A memory mat exclusive to the coarse write and a memory mat exclusive to the high-accuracy write can be also dedicated.
The data to be written in the first operating mode may be set as binary data and the data to be written in the second operating mode may be set as multivalued data. At this time, the rewrite control means is capable of rewriting the binary data written in the first operating mode to the multivalued data in the second operating mode.
A semiconductor integrated circuit is able to have only the coarse write executed in the first operating mode as a writing mode. Namely, the semiconductor integrated circuit has a plurality of electrically erasable and programmable non-volatile memory cells and includes a control means for supplying a pulse-shaped voltage to each non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. At this time, the control means controls the second threshold voltage to a voltage that falls within a range lower than or equal to a power source voltage and higher than or equal to one half the power source voltage.
According to another aspect or viewpoint of the semiconductor integrated circuit having only the coarse write mode as a writing mode, the control means controls the second threshold voltage to a voltage ranging from below 3.3V to above 2V when the power source voltage is in the neighborhood of 3.3V.
At this time, the control means can set the amount of change in threshold voltage per pulse-shaped voltage to above 0.4V. According to a further aspect of the semiconductor integrated circuit, the control means can control the amount of change in threshold voltage per pulse-shaped voltage to above one third the difference between the first threshold voltage and the second threshold voltage.
According to a still further aspect of a semiconductor integrated circuit having only a rough or coarse write mode as a writing mode, the semiconductor integrated circuit having a memory array configuration, which is typified by a NAND type, has a plurality of electrically erasable and programmable non-volatile memory cells and a control means for supplying a pulse-shaped voltage to each non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage, whereby a control voltage for turning on a non-selected non-volatile memory cell is supplied to the non-selected non-volatile memory cell at the time of a read operation. At this time, the control means controls the second threshold voltage so as to reach a voltage lying within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to the control voltage and is higher than or equal to one half the power source voltage. Alternatively, the control means controls the second threshold voltage so as to reach a voltage that falls within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to 3.3V and is higher than or equal to 2V.
As described above, the characteristic of each memory cell is varied by about three digits in the time required to reach the threshold voltage leading from the erased state to the written state when the voltages to be applied upon writing are the same. When the writing of data into the corresponding memory cell is performed under such a condition, it is considered that there may be cases where the threshold voltage results in 0V or less according to memory cells in the case of normal variations in characteristic of each memory cell unless a change ΔVth1 in threshold voltage of the memory cell is set as a write pulse (width or voltage) that reaches 0.2V or less. In order to write data at high speed at this time, the amount of change ΔVth1 per write pulse is increased by making the pulse width long or by raising the voltage. However, the memory cell is apt to deplete due to this increase. The write level is rendered high to avoid this. If the threshold voltage in the written state is set to about 2.0V when the power source voltage is about 3.3V, for example, then ΔVth1 can be set to 0.4V. Since the 3-digit variation referred to above is equivalent to a threshold voltage variation of 3V, assuming the existence of the 3-digit variation, the pulse may be applied eight times. Since the number of verify operations is reduced as much, the data can be written at high speed. Namely, the write level was intended to fall below 1/2 the power source voltage in the art, whereas it is set so as to fall above one half the power source voltage herein.
The semiconductor integrated circuit can adopt a trimming means capable of trimming the minimum value (determining a period in which the initial write voltage in the write operation is supplied) of the pulse width of the pulse-shaped voltage. Further, the trimming means is capable of trimming the rate of gradual increase in pulse width of the pulse-shaped voltage. When the initial write voltage is applied to one semiconductor integrated circuit chip in the same pulse width as that in another semiconductor integrated circuit chip, needless write and verify operations in which the threshold voltage substantially remains unchanged virtually, must be done many times, so that the efficiency of writing might be reduced greatly. If the minimum write voltage pulse width can be trimmed, then the differences in characteristic between memory cells due to process variations can be rendered uniform or optimized between semiconductor integrated circuit chips like flash memory chips. Namely, the amounts of shifts of threshold voltages of memory cells are considered to subtly differ from each other due to the process variations or the like even if the write voltages are the same. Allowing adjustments to the difference in such characteristic in an inspection process, such as a wafer process of a semiconductor integrated circuit like a flash memory chip, is important to make high-speed write possible.
Incidentally, a trimming means for trimming or adjusting the minimum value of the pulse-shaped voltage or the rate of gradual increase in pulse-shaped voltage can be adopted according to the form of the memory cell array.
A semiconductor integrated circuit, such as a flash memory device, can be applied to a data processing system used to constitute a digital still camera. Namely, the data processing system includes an image sensing means, the semiconductor integrated circuit, and a mode control means for providing instructions for allowing the semiconductor integrated circuit to sequentially store image data obtained by the image sensing means in a first operating mode and for causing the semiconductor integrated circuit to rewrite the image data stored in the semiconductor integrated circuit in the first operating mode to multivalued data in a second operating mode, using a period in which an imaging process of the image sensing means is brought to a halt.
A semiconductor integrated circuit, such as a flash memory device, also can be applied to a data processing system for constituting a PC card. Namely, the data processing system for constituting the PC card includes the semiconductor integrated circuit, like a flash memory, and a mode control means for setting a write operation for the semiconductor integrated circuit as a first operating mode upon supply of an external power source to the PC card and allowing the semiconductor integrated circuit to rewrite data written into the semiconductor integrated circuit in the first operating mode to multivalued data in a second operating mode in response to the cutoff of the supply of the external power source to the PC card.
This type of data processing system is capable of implementing the writing of data into each of the non-volatile memory cells of a semiconductor integrated circuit, like a flash memory, at high speed and is capable of improving the reliability of retention of the data stored therein.
While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description, taken in connection with the accompanying drawings, in which:
FIG. 1 is a block diagram showing one embodiment of a flash memory having a coarse write mode and a high-accuracy write mode;
FIGS. 2(a) to 2(d) are diagrams for describing a first write characteristic and a second write characteristic;
FIG. 3 is a flowchart for describing examples of write operations in a first write mode and a second write mode;
FIGS. 4(a) and 4(b) are flowcharts for describing one example of a rewrite operation;
FIG. 5 is a block diagram showing another flash memory having a coarse write mode and a high-accuracy write mode;
FIGS. 6(a) to 6(d) are diagrams for describing a first write characteristic and a second write characteristic of the flash memory shown in FIG. 5;
FIG. 7 is a block diagram illustrating a further flash memory having means for setting conditions for specifying a first write mode and a second write mode;
FIG. 8 is a diagram for describing one example of operation switching conditions in FIG. 7;
FIG. 9 is a block diagram showing a still further flash memory in which a first write mode and a second write mode are identical in write voltage pulse width to each other, whereas write voltages are set as fixed voltages different from each other between the first write mode and the second write mode;
FIGS. 10(a) to 10(f) are diagrams for describing write characteristics related to the flash memory shown in FIG. 9;
FIG. 11 is a block diagram showing a still further flash memory in which high-accuracy writing placed in a second write mode is defined as multivalue writing;
FIGS. 12(a) and 12(b) are diagrams for describing examples of threshold voltage distributions of memory cells at binary writing and multivalue writing;
FIGS. 13(a) to 13(c) are diagrams for describing one example of a rewrite operation of binary-written data into multivalued data;
FIG. 14 is a diagram for describing another way of converting binary data into multivalued data;
FIG. 15 is diagram for describing an initial state of each memory cell placed under a rewrite operation of its stored information from binary to multivalue;
FIG. 16 is a diagram for describing the state of each memory cell at first-stage writing, which is under a rewrite operation of its stored information from binary to multivalue;
FIG. 17 is a diagram for describing the state of each memory cell at second-stage writing, which is under a rewrite operation of its stored information from binary to multivalue;
FIG. 18 is a diagram for describing the state of each memory cell at third-stage writing, which is under a rewrite operation of its stored information from binary to multivalue;
FIG. 19 is a diagram for describing the state of each memory cell at completion of a write operation, which is under a rewrite operation of its stored information from binary to multivalue;
FIG. 20 is a diagram showing a still further flash memory in which coarse write-dedicated memory mats in the first write mode are physically separated from high-accuracy write-dedicated (including multivalue write) memory mats in the second write mode;
FIG. 21 is a diagram illustrating a still further flash memory having memory mats shared for coarse writing and high-accuracy writing;
FIG. 22 is a diagram for describing an example in which data written in a first write mode (coarse write) and data written in a second write mode (high-accuracy write) are mixed into each memory mat;
FIG. 23 is a flowchart for describing one example of a write operation at the time that the configuration shown in FIG. 22 is adopted;
FIG. 24 is a flowchart for describing one example of a read operation at the time that the configuration shown in FIG. 22 is adopted;
FIG. 25 is a flowchart for describing one example of a rewrite operation at the time that the configuration shown in FIG. 22 is adopted;
FIGS. 26(a) and 26(b) are diagrams for describing comparisons between threshold voltage distributions at the time that a write level (corresponding to a threshold voltage of each memory cell in a written state) is set to 1/2 of Vcc and above 1/2 of Vcc;
FIG. 27 is a diagram for describing an erase level and a write level set to above 1/2 of Vcc and the amount of change in threshold voltage per write voltage pulse;
FIGS. 28(a) to 28(d) are diagrams for describing the difference in write meaning between an AND memory cell and a NAND memory cell;
FIGS. 29(a) to 29(f) are diagrams for describing the correlation between erase and write levels of each memory cell and a threshold voltage (Vthi) thereof at irradiation of ultraviolet rays by being divided into the AND memory cell structure and NAND memory cell structure shown in FIG. 28;
FIG. 30 is a block diagram showing a still further flash memory capable of trimming the minimum write voltage pulse widths and the magnitudes of changes in write voltage pulse width;
FIGS. 31(a) and 31(b) are diagrams for describing trimming of the minimum write voltage pulse widths to be subjected to trimming in FIG. 30;
FIGS. 32(a) and 32(b) are diagrams for describing trimming of the magnitudes of the changes in write voltage pulse width to be subjected to another trimming in FIG. 30;
FIG. 33 is a block diagram illustrating a still further flash memory capable of trimming the absolute values of the minimum voltages and the magnitudes of changes in write voltages under a system for varying the write voltages;
FIGS. 34(a) and 34(b) are diagrams for describing trimming of the minimum write voltage values to be subjected to one trimming in FIG. 33;
FIGS. 35(a) and 35(b) are diagrams for describing trimming of gradually-increased widths of write voltage values to be subjected to another trimming in FIG. 33;
FIG. 36 is a block diagram showing a still further flash memory provided with means capable of changing gradually-increased widths or the like of threshold voltages in the course of their increasing;
FIGS. 37(a) to 37(c) are diagrams for describing one example of the technique of changing each gradually-increased width or the like of the threshold voltage in the course of its increasing in FIG. 36;
FIG. 38 is a block diagram showing one example of a pulse train generating means (pulse generator) for application of a write voltage;
FIG. 39 is a block diagram illustrating one example of a trimming means;
FIG. 40 is a block diagram showing one example of an address generator included in the trimming means;
FIG. 41 is a circuit diagram illustrating one example of a trimming circuit included in the address generator;
FIG. 42 is a diagram for explaining one example of a counter unit constituting each of the pulse generator and the address generator;
FIGS. 43(a) to 43(c) are diagrams for describing the basic principle of the technique of changing threshold voltages every write voltage pulses;
FIG. 44 is a circuit diagram showing one example of a circuit for trimming a power circuit;
FIGS. 45(a) to 45(c) are diagrams for describing a digital still camera to which a flash memory having a coarse write mode and a high-precision write mode is applied;
FIG. 46 is a flowchart for describing one example of a rewrite operation employed in the digital still camera shown in FIG. 45;
FIG. 47 is another flowchart for describing a rewrite operation employed in the digital still camera shown in FIG. 45;
FIG. 48 is a block diagram showing one example of a memory card to which flash memories having coarse write and high-accuracy write modes are applied;
FIG. 49 is another block diagram illustrating a memory card to which the flash memories having the coarse write and high-accuracy modes are applied;
FIG. 50 is a further block diagram depicting a memory card to which the flash memories having the coarse write and high-accuracy write modes are applied;
FIG. 51 is a block diagram showing a computer system to which the flash memories having the coarse write and high-accuracy write modes are applied;
FIG. 52 is a block diagram showing one example of a file memory system to which the flash memories having the coarse write and high-accuracy write modes are applied;
FIG. 53 is a circuit diagram illustrating a configuration of a flash memory with a sense latch and a precharge circuit defined as principal;
FIG. 54 is a circuit diagram showing the details of a memory mat and one example of its X-system selection circuit;
FIG. 55 is a diagram illustrating one example of a layout configuration of an AND memory cell;
FIG. 56 is a diagram depicting one example of a layout configuration of a NAND memory cell;
FIG. 57 is a diagram showing one example of a layout configuration of a NOR memory cell;
FIG. 58 is a diagram illustrating one example of a layout configuration of a DINOR memory cell;
FIG. 59 is a diagram for describing states of voltages to be applied to each memory cell according to a memory operation;
FIG. 60 is a general block diagram of a still further flash memory;
FIG. 61 is a block diagram showing a still further flash memory for supporting both binary wring and multivalue writing;
FIG. 62 is a circuit diagram illustrating, in detail as an example, parts of a memory cell array and a sense latch shown in FIG. 61;
FIG. 63 is a diagram for describing the relationship between write verify voltages and threshold voltages at quaternary writing with respect to one memory cell;
FIG. 64 is a diagram for describing one example of voltages applied to each word line at writing;
FIG. 65 is a diagram for describing the correspondence of four memory cells and quaternary data written therein to explain one example of quaternary data writing;
FIG. 66 is a diagram for describing threshold voltages of four memory cells at the time that the four memory cells are all kept in an erased state as a first stage for obtaining the written state shown in FIG. 64;
FIG. 67 is a diagram for describing changes in threshold voltages of four memory cells, which are obtained by .left brkt-top.write 1.right brkt-bot. after the four memory cells are kept in an erased state as a second stage for acquiring the written state shown in FIG. 64;
FIG. 68 is a diagram for describing changes in threshold voltages of memory cells, which are obtained by .left brkt-top.write 2.right brkt-bot. as a third stage for obtaining the written state shown in FIG. 64;
FIG. 69 is a diagram for describing changes in threshold voltages of memory cells, which are obtained by .left brkt-top.write 3.right brkt-bot. as a fourth stage for obtaining the written state shown in FIG. 64;
FIG. 70 is a diagram for describing, as a write voltage application mode, one example of voltage waveforms at the time that write pulse widths are gradually increased;
FIG. 71 is a diagram for describing, as a write voltage application mode, one example of voltage waveforms at the time that write pulse widths are gradually increased;
FIG. 72 is a logic circuit diagram showing one example of a circuit for separating written data into even-numbered and odd-numbered bits;
FIG. 73 is a timing chart for describing one example of the operation of the circuit shown in FIG. 72;
FIG. 74 is a block diagram illustrating the manner in which the memory cell array, the sense latch circuit, the write conversion circuit and the read conversion circuit shown in FIG. 61 are electrically connected to one another;
FIG. 75 is a logic circuit diagram showing one example of a write data synthesis circuit for generating data for .left brkt-top.write 1.right brkt-bot. to .left brkt-top.write 3.right brkt-bot. from the data separated into the even-numbered and odd-numbered bits by the circuit shown in FIG. 72;
FIGS. 76(A) to (C) are diagrams for describing examples of results synthesized by the write data synthesis circuit shown in FIG. 75 in association with .left brkt-top.write 1.right brkt-bot. to .left brkt-top.write 3.right brkt-bot.;
FIG. 77 is a diagram for describing the relationship between word line potentials and threshold voltages of memory cells at the time of reading of the memory cells with data written therein in quaternary form;
FIG. 78 is a waveform diagram for describing examples of voltages applied to read word lines;
FIG. 79 is a diagram for describing the correspondence of four memory cells and data written therein in quaternary form to explain one example of the reading of quaternary data;
FIG. 80 is a diagram for describing binary data obtained by .left brkt-top.read 1.right brkt-bot. with respect to the memory cells shown in FIG. 79;
FIG. 81 is a diagram for describing binary data obtained by .left brkt-top.read 2.right brkt-bot. with respect to the memory cells shown in FIG. 79;
FIG. 82 is a diagram for describing binary data obtained by .left brkt-top.read 3.right brkt-bot. with respect to the memory cells shown in FIG. 79;
FIG. 83 is a logic circuit diagram showing one example of a read data synthesis circuit;
FIG. 84 is a diagram for describing examples of results outputted from the read data synthesis circuit;
FIG. 85 is a circuit diagram showing examples of circuits for respectively alternately outputting high-order and low-order bits, based on outputs produced from the read data synthesis circuit; and
FIG. 86 is a timing chart for describing examples of the operations of the circuits shown in FIG. 85.
Prior to the description of the characteristic features of individual flash memories according to embodiments of the present invention, the configuration of each flash memory will first be described diagrammatically in order of .left brkt-top.the configuration of the flash memory with a sense latch as the central figure.right brkt-bot., .left brkt-top.an AND memory cell array.right brkt-bot., .left brkt-top.the mode of application of voltages to memory cells.right brkt-bot., and .left brkt-top.a chip configuration of the flash memory.right brkt-bot..
[1.1. Configuration of flash memory with sense latch as the central figure]
FIG. 53 shows the configuration of a flash memory with a sense latch and a precharge circuit defined as principal elements. Reference numerals 1 and 2 indicate memory mats, respectively. The memory mats 1 and 2 have a plurality of electrically erasable and programmable or electrically reprogrammable memory cells MCs (one being typically shown in the drawing) respectively. One memory cell comprises one electrically reprogrammable transistor (memory cell transistor) having a control gate, a floating gate, a source and a drain. Although a layout of the structure of each memory cell MC is not limited to a particular types a so-called AND type will be described as an example. In the AND-type construction, a plurality of the memory cell transistors are arranged in parallel through their diffusion or diffused layers (semiconductor regions) constituting sources and drains common to them. Each diffused layer constituting the drain is electrically connected to a bit line BLU through a select transistor 10, whereas each diffused layer constituting the source is electrically connected to a source line 12 through a select transistor 11. The AND-type memory cell structure will be described in detail later. SiS indicates a switch control signal used for the select transistor 11 and SiD indicates a switch control signal used for the select transistor 10. WL indicates a word line electrically connected to a corresponding control gate of each memory cell MC.
In FIG. 53, the bit lines BLU and BLD included in the individual memory mats are shown as typical ones, respectively. Correspondingly, one sense latch 3 shared between the left and right bit lines BLU and BLD is typically illustrated. Although not restricted in particular, a structure related to the left and right bit lines BLU and BLD corresponding to one sense latch 3 is defined as a mirror symmetric structure with the sense latch 3 as the center. Reference numerals 4 and 5 indicate precharge circuits connected to the bit lines BLU and BLD respectively.
The sense latch 3 is made up of a static latch composed of one pair of CMOS inverters, i.e., a circuit in which an input terminal of one CMOS inverter is mutually connected to an output terminal of the other CMOS inverter. The output of one CMOS inverter is electrically connected to its corresponding bit line BLU through the precharge circuit 4, whereas the output of the other CMOS inverter is electrically connected to its corresponding bit line BLD through the precharge circuit 5. Power supplies to activate the sense latch 3 are defined as SLP and SLN. The sense latch 3 latches written data supplied from column select gate transistors 6 and 7 therein or latches initial data according to the states of set MOS transistors 43 and 53 in the event of a read or verity operation. Further, the sense latch 3 performs a sense operation or the like according to the states of the left and right bit lines BLU and BLD.
The precharge circuit 4 (5) has a transfer MOS transistor 40 (50) interposed in the course of a signal transmission path for connecting the bit line BLU (BLD) and the sense latch 3 to each other. A feedback MOS transistor 41 (51) whose gate is electrically connected to an input/output terminal of the sense latch 3 with the MOS transistor 40 (50) interposed between the bit line and the sense latch 3, and a MOS transistor 42 (52) whose source is electrically connected to the bit line BLU (BLD) with the MOS transistor 40 (50) interposed therebetween are placed in series. The drain of the feedback MOS transistor 41 (51) is supplied with a voltage UPC.
When the MOS transistor 40 (50) is in an off state, the MOS transistor 41 (51) is by-switch controlled according to the level of the input/output terminal of the sense latch 3. The MOS transistor 42 (52) is by-conductance controlled according to the level of a signal PCU (PCD) so as to supply a level corresponding to it to the bit line BLU (BLD) based on the voltage UPC.
The precharge circuits 4 and 5 respectively precharge the levels on the bit lines BLU and BLD to desirable levels prior to read, erase verify and program or write verify operations. MOS transistors 4A and 5A are transistors for supplying a reference level for the sense latch 3 to the bit lines BLU and BLD.
Referring to FIG. 53, reference numerals 8 and 9 indicate MOS transistors for determining a written or erased state. The gates of the MOS transistors 8 and 9 are electrically connected to their corresponding bit lines, whereas the sources thereof are respectively connected to a ground potential. The structure related to the bit lines BLU and BLD with one sense latch 3 typically shown in FIG. 53 provided as the center actually exists in large numbers. The drains of the transistors 8 provided on the left side of FIG. 53 with the sense latch 3 interposed between the bit lines are all commonly connected to each other. Further, each of the drains thereof produces a current ECU corresponding to the state (level) of the left-side bit line typified by the bit line BLU. Similarly, the drains of the transistors 9 provided on the right side of FIG. 53 with the sense latch 3 interposed therebetween are all commonly connected to each other. Further, each of the drains thereof generates a current ECD corresponding to the state (level) of the right-side bit line typified by the bit line BLD. Although not shown in the drawing in particular, a current sense-type amplifier is provided which, based on a change in current ECU (ECD), detects whether all the bit lines BLU (BLD) on the left (right) side of the sense latch 3 are brought to the same state. This amplifier is used to detect whether all the memory cells subjected to the erase verify operation or write verify operation are brought to a predetermined threshold voltage.
Incidentally, P channel MOS transistors are shown in the drawings attached to the present specification as distinguished from N channel MOS transistors by arrows affixed on basic gates of the former transistors.
FIG. 54 shows the details of the memory mat 1 and an example of an X-system selection circuit thereof. For example, the memory mat 1 is divided into a plurality of blocks with 128 word lines WL(0) through WL(127) defined as one unit. In the respective blocks, select MOS transistors 11 are by-switch controlled by a common control signal SiS and select MOS transistors 10 are by-switch controlled by a common select signal SiD. Although not shown in the drawing, the memory mat 2 is configured in the same manner as described above. The X-system selection circuit comprises a main decoder 17, a gate decoder 18 and a sub decoder 19. The sub decoder 19 is provided for each of the memory mats 1 and 2 and has drivers DRV provided in one-to-one correspondence with the word lines. Power supplies to activate or operate the drivers DRV are supplied from the main decoder 17 in block units. The main decoder 17 supplies the operating power supply to the driver DRV corresponding to one block exclusively in accordance with an address signal supplied thereto. At the same time, the main decoder 17 controls the select MOS transistors 11 and 10 in each block associated with the driver DRV to supply the operating power supply thereto to an on state. The gate decoder 18 supplies a signal for selecting one word line in each block in accordance with an address signal supplied thereto to its corresponding driver of the sub decoder 19. The X-system selection circuit selects one block and is capable of driving one word line in the selected block to a select level. The driven level at that time is determined according to the operating power supply of each output circuit in the main decoder 17. An X-system selection circuit of the memory mat 2 is configured in the same manner as described above.
Either one of the X-system selection circuits for the memory mats 1 and 2 is exclusively selected and operated. Either one of the main decoder 17 for the memory mat 1 and the main decoder 17 for the memory mat 2 can be activated in accordance with, for example, the least significant bit or the most significant bit of an address signal supplied from the outside.
[1-2. AND memory cell array]
FIG. 55 shows an example of a layout configuration of the aforementioned AND memory cell. The memory cell shown in the same drawing has a structure formed in accordance with a process, using metal interconnection layers corresponding to two layers. Memory cells MC and select MOS transistors 10 and 11 are respectively formed at positions where longitudinally-extending diffused layers arranged in parallel and transversely-extending control gates made of polysilicon or the like intersect. Each memory cell MC of a flash memory is defined as an N channel MOS transistor formed on a P-type substrate. The memory cell MC is capable of holding information therein according to the presence or absence of an electrical charge in each floating gate. When, for example, the electrical charge is introduced into the floating gate, the threshold voltage of each memory cell increases. No memory current flows by increasing the threshold voltage to above a voltage value applied to each control gate. Further, the discharge of the electrical charge from the floating gate allows a reduction in threshold voltage of each memory cell. The memory current flows by setting the threshold voltage so as to be lower than the voltage value applied to the control gate. For example, the state of a current flow and the state of a non-current flow can be assigned to a "0" information holding state (e.g., written state) and a "1" information holding state (e.g., erased state) respectively. This is set from the standpoint of definition. Even if the reverse definition is given, no problem occurs.
Although the memory cells of the flash memory described as an illustrative example in the present specification are AND types, the memory cell structure is not limited to this and may adopt or take other structures, such as a NAND type as shown in FIG. 56, a NOR type as shown in FIG. 57, a DINOR type as shown in FIG. 58, etc. Even in the case of any other structure, the memory cells in the flash memory are basically identical in configuration to each other. However, when the memory cells are disposed in array form as shown in FIGS. 55 through 58, their characteristics are exhibited. Since the NOR type needs contacts with the bit lines (metal interconnection layers) of all memories, it is difficult to reduce its occupied area. However, since the NAND type, DINOR type and AND type may place contacts with bit lines of every block, their occupied areas can be reduced.
[1-3. Mode for application of voltage to memory cell]
FIG. 59 shows examples of states of voltages to be applied to each memory cell according to a memory operation. The memory operation is roughly divided into read, program or write and erase operations. The terms program or write verify and erase verify are substantially identical to read. Vg indicates a voltage (control gate voltage) applied to a control gate, Vd indicates a voltage (drain voltage) applied to a drain, and Vs indicates a voltage (source voltage) applied to a source.
In the event of a read operation, a read potential (Vcc) is applied to the control gate of each memory cell. Thus, data stored in each memory cell is determined depending on whether a current flows in the memory cell by the application of the read potential to the control gate. The read operation will be explained in accordance with the construction shown in FIG. 53. When it is desired to perform reading on each memory cell MC included in the memory mat 1 (MATU), for example, the set MOS transistor 53 on the non-selected memory mat 2 (MATD) side is turned on to activate the sense latch 3, thereby latching a high level into the bit line BLU side of the sense latch 3. Further, RPCU is controlled to 1V+Vth so as to precharge the bit line BLU to 1V. On the non-selected memory mat 2 side on the other hand, RPCD is controlled to 0.5V+Vth so as to precharge the bit line BLD to 0.5V, which is defined as a reference level for a sense operation of the sense latch 3. After the selecting operation of the corresponding word line, the transfer MOS transistors 40 and 50 are turned on. At this time, the sense latch 3 senses whether the level of the bit line BLU is higher or lower than 0.5V and latches therein data read from the memory cell MC.
In the event of an erase operation, a positive voltage (12V) is applied to the control gate of each memory cell and a negative voltage (-4V) is applied between the drain and source thereof. It is thus possible to inject an electrical charge into the floating gate by the tunnel effect. As a result, the threshold voltage of the memory cell MC increases. For example, the erase operation is performed until the above state of application of the voltage is executed intermittently and the threshold voltage of the memory cell exceeds a word line potential for the erase verify. In the construction shown in FIG. 54, the erase operation is performed in word line units, for example. The same drain and source voltages are respectively applied to the memory cells in the block including the word lines, which are subjected to the erasing, through the select MOS transistors 10 and 11. Accordingly, Vg=0V and Vd=Vs=-4V are applied to the non-selected memory cells included in the selected block. Since the select MOS transistors 10 and 11 in the non-selected block are kept in an off state, the drain and source of each memory cell included in the non-selected block is brought to a floating state, i.e., it is rendered open so that the control gate voltage is brought to 0V. The erase verify operation is substantially identical to the read operation except that the word line voltage for the verity operation is simply different from that of the read operation.
In the event of a write operation, a negative potential (-10V) is applied to the control gate of each memory cell, a positive potential (4V) is supplied to the drain thereof and the source thereof is brought to a floating state. 0V is applied to the drain of a memory cell to be written and the drain of a memory cell to be non-written, which shares the use of the word line. Thus, the electrical charge is discharged only from the memory cell whose drain is supplied with the positive voltage. As a result, the threshold voltage of the memory cell decreases. The write operation is executed until the threshold voltage of a desired memory cell is lower than or equal to a word line potential for the write verify operation. The write operation will be explained in accordance with the construction shown in FIG. 53. After the written data inputted from the column select gates 6 and 7 have been latched in the sense latch 3, PCU and PCD are controlled to a high level, so that the bit line (e.g., BLU) connected to the input/output nodes on the high level side of the sense latch 3 is precharged to a high level. Further, when the transfer MOS transistors 40 and 50 are turned on, the bit line BLU precharged to the high level is supplied with a write drain voltage from the sense latch 3. The select MOS transistors 10 for connecting the bit lines to the drains of the memory cells MC are all in a cut-off state on the write non-selected mat side by the signal SiD. Thus, the threshold voltage of each memory cell supplied with the write voltage through the bit line, of the memory cells connected to the control gates each supplied with the write voltage on the write selected mat side, is reduced. The subsequent write verify operation is also performed in the same manner as the read operation.
[1-4. Chip configuration of flash memory]
FIG. 60 is a block diagram showing the overall configuration of the flash memory referred to above. The invention is not limited to the flash memory shown in the drawing in particular, which is formed on a single semiconductor substrate like monocrystal silicon by a known semiconductor integrated circuit manufacturing technique.
Referring to FIG. 60, MATU constitutes the memory mat 1 and MATD constitutes the memory mat 2. In order to distribute the load capacity of one word line to the individual memory mats 1 and 2, the word line disposed at the same address is divided into two to which sub decoders 19 are assigned respectively. Although the invention is not restricted in particular, the flash memory is defined as a flash memory effective for application to a disc-device compatible ATA file memory. Each word line located at the same address has memory cells of (2048+128)×2 bits, which corresponds to a sector of 512 bytes and a sector management area of 16 bytes. Of these, the 16-byte area is used for redundancy.
In FIG. 60, reference numeral 60 indicates a column-system circuit. The column-system circuit 60 is defined as a circuit block including the column-system circuit shown in FIG. 53 having the sense latch 3, precharge circuits 4 and 5, column select gates 6 and 7, etc., and a column decoder for by-switch controlling the column select gates. The column select gates 6 and 7 interface to eight pairs of common data lines 61 and the column decoder controls continuity or conduction between the eight pairs of common data lines 61 and bit lines BLU and BLD in accordance with a column address signal or the like. The common data lines 61 are respectively electrically connected to main amplifiers (MA) 63 and input/output buffers 64 through an input/output switching circuit 62. Each of the input/output buffer 64 interfaces to the outside through an external connecting electrode (I/O) like a bonding pad.
The input/output buffer 64 is shared between the input and output of memory data, the input of address data and the input of command data. Data to be written into each memory cell is supplied to its corresponding pair of common data lines 61 through the input/output switching circuit 62. Data read from each memory mat is supplied via the input/output switching circuit 62 to the corresponding main amplifier 63 where it is amplified, followed by its supply to a corresponding input/output buffer 64.
The address data supplied to the input/output buffer 64 is supplied to an address counter 65. Further, the address data is supplied to a main decoder 17, a gate decoder and the column decoder and the like through an address generator 66. In the address counter 65, although the invention is not restricted in particular, initial values are preset as the address data and successively subjected to an incrementing or the like according to operating modes given to the flash memory by commands. Each address subjected to incrementing or the like is outputted from the address generator 66. Each of the memory mats 1 and 2 has spare bits placed in 16-byte form at the data lines. A save-system circuit 68 replaces an address having a defective bit by a redundant address in accordance with a programmed state of a redundant fuse circuit 67 and supplies or inputs it to the address generator 66, whereby the defective bit is replaced by a corresponding spare bit. The address generator 66 forms or produces an internal complementary address signal in response to its input and assigns it to the main decoder 17, the gate decoder 18 and the column decoder or the like.
Reference numeral 86 indicates a status register and test-system circuit, which is capable of outputting an internal state of the flash memory to the outside through the corresponding input/output buffer 64 and outputting a ready/busy status to the outside through a buffer 87.
A data input/output control circuit 70 supplied with a serial clock signal SC from the outside synchronizes inputs and outputs transferred between the corresponding main amplifiers 63, the input/output switching circuit 62 and the address counter 65, and the corresponding input/output buffer 64 with the serial clock signal SC.
External control signals are supplied to a control signal input buffer 71. The external control signals include a write enable signal WEB for providing instructions for the input of information to the flash memory, a chip enable signal CEB for providing instructions for the operation of the flash memory, an output enable signal OEB for providing instructions for the output of information from the flash memory, a signal CED for providing instructions as to whether information to be supplied to the flash memory is a command or data, and a reset signal RESB. An internal operation of the flash memory is synchronized with a clock signal outputted from a clock generator 72.
Commands supplied from the input/output buffers 64 are supplied to a command decoder 73. The commands are ones related to a read, high-precision or -accuracy program or a write and coarse program or write, and erase, etc. Contents instructed by the program and erase commands also include verify. Internal control based on the commands is divided into a so-called microprogram control system and a control system similar to this. Namely, a ROM 75 has a control code (state information) series for defining processes corresponding to the commands, for every command. The result of decoding of each command by a command decoder 73 is defined as the leading address within the ROM 75 having the control code series associated with the command. When the result of decoding of the command is supplied to the ROM 75, a control code at the head of the control code series associated with the command is read from the ROM 75. A ROM decoder 76 decodes the read control code and supplies an operation control signal to a writeerase determination circuit 80, a direct-system control circuit 81 and a power control circuit 82. A ROM control-system circuit 74 specifies second and later control codes of the control code series, based on a ROM address for the leading control code. When the division of the order of execution of the control codes into conditions is taken into consideration, the control code may be set so as to hold a ROM address corresponding to the next control code in a manner similar to the microprogram.
The power control circuit 82 controls the supply of an operating power source or supply to various circuits necessary for the read, program and erase operations. The operating power source is formed by a reference voltage generating circuit 85 for generating a reference voltage, based on a band gap or the like of silicon, for example, a charge pump circuit 84 for generating a power of -10V or so, using the reference voltage produced from the reference voltage generating circuit 85, and a power switching circuit 83 for performing switching between power supplies to activate various circuits such as the main decoders, etc. according to the read, erase and program operations, for example. The writeerase determination circuit 80 is a circuit for determining based on ECU and ECD described in FIG. 53 whether the program or write operation or erase operation is completed. The result of the determination is supplied to the ROM control-system circuit 74 where it is reflected on the contents of control in a control step next to a series of write operations or erase operations. The direct-system control circuit 81 controls word line selecting timing and column selecting timing.
Operations implemented by supplying the control information decoded by the ROM decoder 76 to the writeerase determination circuit 80, the direct-system control circuit 81 and the power control circuit 82 or the like include control operations for carrying out a write or program operation, a rewrite operation, etc. according to operating modes to be described below. This control may be implemented by hard-wired logic.
Flash memories having several characteristic contents will next be explained with the above-described flash memory whose schematic configuration has been made apparent, as the basis.
[2. Coarse write mode and high-accuracy write mode]
A flash memory FMRY1 shown in FIG. 1 has a coarse program or write mode and a high-accuracy write mode. Namely, the flash memory FMRY1 has operating modes different from each other in the amount of change in threshold voltage per pulse of a write pulse or write pulse train.
At the time of the write operation, the above-described write voltage is applied to a memory cell to be written. However, since the threshold voltage of a memory cell placed in a written state is determined with comparatively high accuracy or a variation in the threshold voltage of the memory cell kept in the written state is less reduced, the write voltage is applied to a selected word line for each time (high-level cycle or period) defined by the write pulse until the threshold voltage of the memory cell reaches a predetermined threshold voltage. As a matter of course, verify is performed each time the write voltage is applied to the word line. When the value of a write word line voltage is fixed and supplied to the corresponding word line as shown in FIG. 43(a), the write pulse width is rendered long in sequence so that the amount of change in the threshold voltage of the memory cell is approximately constant by one writing. When the write pulse width is fixed as shown in FIG. 43(b), the write word line voltage increases in sequence. Both the write voltage and the write pulse width may be varied as shown in FIG. 43(c).
In FIG. 43(a), the word line voltage V is defined as -13V, and the pulse width is changed to 800 ns at T1, 960 ns at T2 and 1152 ns at T3. In FIG. 43(b), the pulse width T is defined as 800 ns and the word line voltage is changed to -9V at V1, -11V at V2 and -13V at V3. In FIG. 43(c), the pulse widths T1 through T3 change as illustrated in FIG. 43(a) and the word line voltages V1 through V3 change as shown in FIG. 43(b).
For example, the flash memory FMRY1 shown in FIG. 1 is intended to fix each write word line voltage so as to correspond to FIG. 43(a), for example and to increase each write pulse width (time) in sequence. Therefore, the flash memory FMRY1 has a first pulse train generating circuit 100 for application of the write voltage, which is used for a first write mode (coarse write) in which the amount of change in threshold voltage of each memory cell per write pulse is ΔVth1 (0.4V), and a second pulse train generating circuit for application of the write voltage, which is used for a second write mode (high-accuracy write) in which the amount of change in threshold voltage is ΔVth2 (0.2V). The operation for verifying the threshold voltage is done between the write pulse and the write pulse.
FIGS. 2(a) and 2(b) show a first write characteristic and a second write characteristic respectively. In the present specification, the scales of time axes are all defined as log. As described above, the write pulse widths are respectively rendered longer as the write operation proceeds.
FIGS. 2(c) and 2(d) respectively show threshold voltage distributions of each memory cell MC at the first writing and the second writing.
When the threshold voltage of the memory cell ranges from Vt1 (5V) to Vt2 (3.3V) in FIG. 2(c), the memory cell is kept in an erased state. On the other hand, when the threshold voltage of the memory cell ranges from Vt3 (2V) to Vt4 (1.4V), the memory cell is brought to a written state. When the threshold voltage of the memory cell ranges from Vt5 (4.8V) to Vt6 (3.1V), the memory cell is in an erased state. On the other hand, when the threshold voltage thereof ranges from Vt7 (1.8V) to Vt8 (1.4V), the memory cell is placed in a written state.
Now consider where the difference (cell window) between the minimum threshold voltage Vt2 or Vt6 at the erased state and the maximum threshold voltage Vt3 or Vt7 at the written state is fixed. In this case, the number of pulses required to change the threshold voltage of the memory cell MC at ΔVth1 is fewer than that at ΔVth2. Therefore, the number of times that the verify operation is performed when the first pulse train generating circuit 100 for the application of the write voltage (the amount of change in threshold voltage: ΔVth1) is used, is smaller than when the second pulse train generating circuit 101 for the application of the write voltage (the amount of change in threshold voltage: ΔVth2) is used. A write or program time results in the sum of the time required to vary the threshold voltage of each memory cell itself and an overhead time such as the time required to perform verify. Thus, since the overhead time is short if the number of times that the verify operation is performed is few, the write time becomes short.
Although not shown in the drawing in particular, each of the first and second pulse train generating circuits 100 and 101 uses a carrier-transfer type binary counter, which is capable of controlling the width of each pulse according to the time required to bring the result of counting of data preset thereto to the whole bit "1". At this time, the first and second pulse train generating circuits 100 and 101 may be constructed of separate hardware respectively. However, when it is unnecessary to perform the first write and the second write in parallel, the use of such a binary counter can be shared between the two. Decreasing widths of preset data successively set according to the operating modes may be controlled so as to differ from each other. If its configuration is placed in correspondence with the configuration shown in FIG. 60, then each of the preset data is outputted from the ROM decoder 76. The value of each preset data is determined according to the first write mode or the second write mode judged by decoding the command with the command decoder 73. The binary counter is included in the power control circuit 82. In accordance with a write pulse produced therefrom, the power switching circuit 83 supplies a write word line voltage to the X-system selection circuit for each time defined by the write pulse.
The flash memory FMRY1 includes a first verify voltage generating circuit 102 used upon writing by the first pulse train generating circuit (also called "first pulse train generating means") for the application of the write voltage, and a second verify voltage generating circuit 103 used upon writing by the second pulse train generating circuit (also called "second pulse train generating means") for the application of the write voltage. In order to utilize either one of the two circuits, a switching circuit 104 controls the switching between switches S1 and S2 according to whether a command is used to specify the first write mode or the second write mode. The write voltage generating circuit connected to the X-system selection circuit by either one of the switches S1 and S2 supplies a word line drive voltage to the X-system selection circuit according to the operating modes.
Further, the flash memory FMRY1 has an erase voltage generating circuit 107 for applying an erase voltage in an erase mode and an erase verify voltage generating circuit 108 for verifying whether erasing has been done. These circuits are electrically connected to the X-system selection circuit when a switch S3 is turned ON by the switching circuit 104.
When the amount of change in threshold voltage is ΔVth1, the threshold voltage distribution at the written state ranges from Vt3 to Vt4 as shown in FIGS. 2(c) and 2(d). This is because, since this range becomes larger than the range from Vt7 to Vt8 indicative of the threshold voltage distribution at the written state, it is advisable to divide the verify voltage into a verify voltage used for the first write and a verify voltage used for the second write. The verify voltage might not be divided according to the characteristic of each memory cell MC or the cell window voltage.
Particularly,when the verify voltage is classified according to the first write and the second write as described above, it is desirable to set the verify voltage at writing to Vt3 (first verify voltage)>Vt7 (second verify voltage) for purposes of avoiding its depletion. If the present configuration is associated with the configuration shown in FIG. 60, then such first and second verify voltages are formed or produced by the charge pump circuit 84. Whether either one of the first and second write verify voltages should be used, is controlled by the power switching circuit 83 in accordance with instructions given from the ROM decoder 76 on the basis of the result of decoding of either a first write command or a second write command.
Although the invention is not restricted in particular, erase operations are also carried out so that the threshold voltage of each memory cell is raised in a stepwise form using an erase pulse train. However, the amount of change in threshold voltage per pulse in the erase pulse train at this time is not selected as in the case of the write operating modes. For the erase operation at the first write mode, an erase verify potential like Vt2 is supplied to the corresponding word line. Further, for the erase operation at the second write mode, an erase verify potential like Vt6 is supplied to the corresponding word line. Since the normal writing is done in the first write mode and the subsequent rewriting is done in the second write mode, such control is made possible. Namely, in order to rewrite each memory cell on the same word line, the memory cell on the word line needs to be kept in an erased state once. At this time, the erase verify potential is changed to control its threshold voltage distribution to a range from Vt5 to Vt6.
As is understood from the above description, an electric field between a floating gate at the retention of information and a semiconductor substrate is low and the information holding time is long when the writing is done through the second write mode. In other words, it can be said that the performance of retention of stored information or its retention period is excellent when the writing is done through the second write mode.
Word line selection levels at a read operation may be used in common in consideration of the width of the cell window, the difference between Vt3 and Vt7, the difference between Vt2 and Vt6, etc. When memory locations or areas, to which the first write mode and the second write mode are applied, are being physically divided into desired areas, the word line selection levels at the read operation may be made different from each other most suitably every memory areas.
FIGS. 3(a) and 3(b) are flowcharts for explaining examples of the write operations in the first and second write modes. Namely, when a write command is input, the command decoder 73 decodes the input command and determines based on the result of decoding whether either one of the first and second write modes has been used. An increment (Δt1, Δt2) of a write pulse time and a verify voltage (Vt3, Vt7) applied to a word line are determined according to a signal decoded by the ROM decoder 76. In the first write mode, the increment of the writ pulse time is set to Δt1 and the verify voltage is set to Vt3. In the second write mode, the increment of the write pulse time is set to Δt2 and the verify voltage is set to Vt7. The verify voltages Vt3 and Vt7 are illustrated as described in FIGS. 2(c) and 2(d). The increments Δt1 and Δt2 of the write pulse time are set so as to satisfy Δt1>Δt2. The amount of change in threshold voltage during a first write pulse cycle or period in the first write mode is set so as to be larger than that in the second write mode. Other operations are the same between the first and second write operations. As is apparent from this description, it will be understood that even if there are two types of write mode, the physical circuit scale due to the provision of the two types of write modes is increased very little. With respect to the increments of the write pulse time, as described above, the counter values that will cause the increments, may be varied according to the write modes. Further, the verify voltage can be selectively controlled by turning on and off the switches S1 and S2 for respectively selecting one of the voltages at a plurality of voltage output nodes of one voltage generating circuit. Alternatively, the verify voltage may be controlled by varying the voltage itself generated from the voltage generating circuit.
As described above, the write operation in the first write mode is faster than that in the second write mode but the second write mode is superior to the first write mode in reliability (data holding period) of written data. When this is taken into consideration, the flash memory FMRY1 shown in FIG. 1 has a control means (rewrite control means) 105 for rewriting data written by the first pulse train generating circuit 100 for the application of the write voltage, using the second pulse train generating circuit 101 for the application of the write voltage. Namely, the data is rewritten in the second write mode capable of narrowing the distribution of the threshold voltage after the data has been written in the first write mode in a short write time. With respect to the rewriting, the data is first read from the memory cell MC and then inverted and stored in the sense latch 3, whereby the rewriting may be done based on the data in the second write mode.
FIGS. 4(a) and 4(b) are flowcharts for describing one example of the rewrite operation. For the first write mode, the written data is loaded and latched in the sense latch 3. The initial write pulse width is defined as t1. The verify voltage is defined as Vt3. The pulse width is increased
Δt1 by Δt1 until the verify is determined to be OK. While the write pulse is being updated, the write or program and verify operations are repeated. in the relationship between the threshold voltage of the memory cell MC and the write time expressed in log, Δt1 is set so that the amount ΔVth1 of change in threshold voltage becomes constant per one write pulse. Thus, a high-speed write operation can be completed.
The rewrite mode is an operating mode for rewriting data written in the first write mode in the second write mode. In the rewrite mode, the data written in the first write mode is read into the sense latch 3. This is identical to the normal read operation. Since data amplified by and latched in the sense latch 3 after the normal read operation assumes a voltage that works in reverse for writing, it is necessary to invert the data. The initial write pulse width is set to t1. The verify voltage is set to Vt7. The pulse width is increased Δt2 by Δt2 and the write pulse is repeatedly applied until the verify is determined to be OK. In the relationship between the threshold voltage of the memory cell and the write time expressed in log, Δt2 is set so that the amount ΔVth2 of change in threshold voltage becomes constant per one write pulse. Since Vt3>Vt7 and ΔVth1>ΔVth2, the second writing is slower than the first writing in speed. However, the electric field at the retention of data is small, the time required to hold the data becomes long and the reliability of retention of the written data is improved.
The switching circuit 104, the switches S1, S2 and S3, the reprogram control circuit 106 and the rewrite control circuit 105 shown in FIG. 1 are composed of the ROM control-system circuit 74, the ROM 75, the ROM decoder 76, the writeerase determination circuit 80, the power switching circuit 83 and the power control circuit 82 or the like. Further, the erase voltage generating circuit 107 and the erase verify voltage generating circuit 108 is composed of the charge pump circuit 84.
FIG. 5 is a block diagram showing a flash memory of a type for fixing each write pulse width and successively raising write word line voltages on an absolute value basis to thereby perform writing, which applies the first write mode and the second write mode thereto.
The flash memory FMRY2 shown in FIG. 5 has also a coarse write mode (first write mode) and a high-precision write mode (second write mode), which are defined as operating modes different from each other in the amount of change in threshold voltage per pulse in a write pulse or write pulse train. FIG. 5 is different from FIG. 1 in that writing is done by fixing write pulse widths and successively raising write word line voltages on an absolute value basis as shown in FIG. 43(b). Therefore, the flash memory FMRY2 shown in FIG. 5 is provided with a first write voltage train generating circuit 120 used for first write (coarse write) in which the amount of change in threshold voltage of a memory cell per one write pulse is defined as ΔVth1, and a second write voltage train generating circuit (high-accuracy write) 121 used for second write (high-accuracy write) in which the amount of change in threshold voltage is defined as ΔVth2.
FIGS. 6(a) and 6(b) show a first write characteristic and a second write characteristic respectively. As described above, the individual write pulse widths (write times) are constant and each write voltage gradually increases as the write operation progresses.
FIGS. 6(c) and 6(d) show threshold voltage distributions of each memory cell at the time of the first write and the second write respectively.
In the same manner as in FIG. 1, the flash memory FMRY2 has also a first verify voltage generating circuit 102 used upon the write operation by the first pulse train generating circuit, and a second verify voltage generating circuit 103 used upon the write operation by the second pulse train generating circuit. They are switched by a switching circuit 104 according to a write mode specified by a command in the same manner as described above.
If an increase in absolute value of the write voltage is changed in place of the change in increment of each write pulse time in the flowcharts described in FIGS. 3(a), 3(b) and 4(a), 4(b), then the flash memory FMRY2 is capable of performing the same control as described above. Since the correspondence of the configuration of FIG. 5 and the configuration of FIG. 60 is similar to FIG. 1, its description will be omitted.
FIG. 7 is a block diagram showing a flash memory FMRY3 having means for setting conditions for specifying a first write mode and a second write mode. Namely, a mode of ΔVth1 (coarse and first write mode) and a mode of ΔVth2 (high-accuracy and second write mode) may be used by switching under specific conditions in place of the method of first coarsely writing data in the first write mode and thereafter rewriting it in the second write mode with high accuracy when the flash memory FMRY3 has the first write mode and the second write mode, as typified by the rewrite mode described in FIG. 4. The conditions are set to a switching condition setting means 130. Referring to FIG. 12(b), for example, a region ranging from V+9 to V+10 in voltage is defined as an erased state in a multivalue mode to be described later. In doing so, the writing of data into a region ranging from V+5 to V+6 in voltage is done in the first write mode. The writing of data into regions ranging from V+7 to V+8 in voltage and V+11 to V+12 in voltage is carried out in the second write mode.
FIG. 8 show switching conditions in a binary data write mode by way of example. Up to the number of reprogrammings corresponding to ten thousands or so, in which the degree of degradation in characteristic of a memory cell MC, for example, is considered not to be so developed, top priority is assigned to a write operation as the first write mode and the subsequent write operation is set as the second write mode in consideration of the influence of the degradation in characteristic of each memory cell. To this end, the switching condition setting means 130 sets the number of reprogrammings at the time of the execution of switching. At this time, the number of times that the reprogramming is done, is stored in, for example, a management region assigned in a memory mat. A switching circuit 104 regularly determines through a timer or the like whether the number of reprogrammings exceeds a set condition. If the number of reprogrammings is found to have exceeded it, then the switching circuit 104 switches the write mode from the first write mode to the second write mode when the write mode is specified or designated from the outside. The write mode may be switched according to a data holding period using the timer or the like. Further, storage areas such as a block, a sector (e.g., storage area for each word line), etc. can be set as designated or specified conditions. The conditions can be given by memory addresses in these areas. In this case, the switching circuit compares a written address with the set condition address to thereby select either first write or second write. In order to set each address, a fuse program circuit can be adopted for the switching condition setting circuit 130. Alternatively, the conditions can be set according to a chip unit of the flash memory. For example, a chip specified by the first write mode performs writing in the first write mode when the write operation is directed from the outside. As the switching condition switching means 130 in this case, a type such as an aluminum master slice condition-set according to a change in wiring pattern mask in a manufacturing process is efficient.
FIG. 9 shows a flash memory in which a first write mode and a second write mode are identical in write voltage pulse width to each other, whereas write voltages are defined as fixed voltages different from each other between the first write mode and the second write mode. Namely, the flash memory is provided with a pulse train generating circuit 140 shared between the first write mode and the second write mode, a first write voltage generating circuit 141, and a second write voltage generating circuit 142. A constant first write voltage VA outputted from the first write voltage generating circuit 141 and a second write voltage VA generated from the second write voltage generating circuit 142 are selected by a switching circuit 143 through switches S1 and S2. The selected write voltage is supplied to the pulse train generating circuit 140. The pulse train generating circuit 140 outputs a given voltage pulse train to an X-system selection circuit as a write voltage.
In the first write mode, the absolute value of the write voltage is represented as VB, whereas in the second write mode, the absolute value of the write voltage is represented as VA (VA>VB).
Now consider write characteristics at this time in which as shown in FIGS. 10(a) and 10(b), the inclination of a change in threshold voltage with respect to a write time (log scale) remains unchanged as K1 for the two. Since VB>VA at this time, the amount of change in threshold voltage per first write pulse in the first write mode becomes larger than that in the second write mode. Thus, the first write mode is smaller than the second write mode in the number of times that the write pulse up to the intended threshold voltage is applied. Namely, the write operation can be speeded up.
Now consider where,as shown in FIGS. 10(c) and 10(d), the inclination of change in threshold voltage with respect to the write time (log scale) in the first write mode becomes larger than that in the second write mode (K2>K1). In practice, the inclination is generally considered to virtually lead to such a case in terms of a physical characteristic of the memory cell MC. When the write voltage is VB, the inclination results in K2 in the first write mode, whereas the inclination at the time that the write voltage is VA, is represented as K1 different from K2 in the second write mode. When K1>K2 and VB>VA, the change in threshold voltage per first write pulse voltage in the first write mode becomes greater than that in the second write mode. Further, the amount of change in threshold voltage per one write pulse voltage is brought to ΔVth2 at VB, which is greater than ΔVth1 at VA. Therefore, the first write mode is smaller than the second write mode in the number of times that the write pulse up to the intended threshold voltage is applied. Namely, the write operation can be speeded up.
Threshold voltage distributions shown in FIGS. 10(e) and 10(f), which are obtained by the configuration of FIG. 9 have the same tendency as those by the configuration of FIG. 1.
In the configuration shown in FIG. 9, the first write voltage generating circuit 141 and the second write voltage generating circuit 142 are implemented by the charge pump circuit 84 employed in the configuration shown in FIG. 60. The switching circuit 143 and the pulse train generating circuit 140 can be constructed of the power switching circuit 83 and the power control circuit 82, and the command decoder 73, the ROM control circuit 74, the ROM 75 and the ROM decoder 76 for controlling the two circuits 83 and 82.
When writing is carried out in the form in which each write voltage is gradually increased with the write pulse widths as fixed as described in FIGS. 5 and 6(a) to 6(d), although its illustration is omitted, write voltage trains can be made identical to one another in the first and second write modes and pulse voltage widths can be rendered different from each other in the first and second write modes. In this case, the tendency of the write operation is similar to that in FIG. 10.
FIG. 11 shows one example of a flash memory of a type wherein the high-accuracy write in the second write mode is set as multivalue write. FIGS. 12(a) and 12(b) illustrate threshold distributions of each memory cell at binary write and multivalue write.
In the flash memory FMRY5 shown in FIG. 11, a first pulse train generating circuit 150 for application of a write voltage generates a write pulse voltage for coarsely writing data in the same manner as the first write mode described in FIGS. 1 and 2. Data to be written based on the write pulse voltage is defined as binary in the same manner as that already described in FIG. 1 or the like. At this time, an erase level ranges from Vt1 to Vt2 and a write level ranges from Vt3 to Vt4. A second pulse train generating circuit 151 for application of a write voltage generates a write pulse voltage for writing data with high accuracy in the same manner as the second write mode described in FIGS. 1 and 2. Data to be written in this case is defined as a multivalue, e.g., four values or quaternary. In FIG. 11, multivalued data buffers 152 and 153 are provided at ends of bit lines for purposes of multivalue writing. In a threshold voltage distribution of a multivalue-written memory cell, an erase level falls within a range from Vt5 to Vt6 and a write level is defined as three values, which fall within ranges from Vt7 to Vt8, Vt9 to Vt10 and Vt11 to Vt12 respectively.
A first verify voltage generating circuit 154 generates a verify voltage for the binary write in a first write mode. A second verify voltage generating circuit 155 generates a verify voltage for the multivalue write in the second write mode.
When a binary write command is supplied to the flash memory FMRY5, the flash memory FMRY5 is brought to the first write mode. Upon the binary write, the write pulse voltage outputted from the first pulse train generating circuit 150 is selected by a selection/control circuit 156. On the other hand, when a multivalue write command is supplied thereto, the flash memory FMRY5 is brought to the second write mode. Upon the multivalue write, the write pulse voltage outputted from the second pulse train generating circuit 151 is selected by the selection/control circuit 156. A selection/control circuit 157 selects a verify voltage outputted from the first verify voltage generating circuit 154 upon the binary write in the first write mode. Upon the multivalue write in the second write mode, the selection/control circuit 157 selects a verify voltage outputted from the second verify voltage generating circuit 155.
There may be cases in which Vt2 in the binary write mode is equal to Vt6 in the multivalue write mode and Vt3 is equal to Vt7. The binary write mode is defined as a first write mode for coarsely writing data. To make rough or coarse writing possible, only Vt3 to Vt4 may be provided within Vt7 to Vt12 in the multivalue mode. Since the multivalue mode needs to narrow a threshold voltage distribution, it is necessary to reduce the amount of change in threshold voltage per pulse in a write pulse or write pulse train. Although the write operation is slow, the storage capacity is obtained in double form.
The details of the multivalue write will be described later. However, when data stored in one memory cell is defined as four values or quaternary, for example, two bits indicative of binary data constitute quaternary data stored in one memory cell. Thus, upon writing, 2-bit data is decoded and whether the writing should be continued with the objective of determining which level of Vt7, Vt9 and Vt11 should be selected, is controlled in accordance with the result of decoding of the data. Correspondingly, one write verify voltage is also selected from, for example, Vt7, Vt9 and Vt11 in accordance with the result of decoding. Upon reading, a word line level is switched to voltages (Vr3, Vr2 and Vr1) between Vt6 to Vt7, Vt8 to Vt9 and Vt10 to Vt11. Read data obtained based on the respective voltages are encoded and converted into 2-bit data represented in binary form, respectively. The multivalued data buffers 152 and 153 serve as latch circuits for saving the previous read data upon reading one memory cell three times. Their control is done by a reprogram control circuit 159A and both decoding and encoding are carried out by a data conversion circuit 158.
Further, either the multivalue write or the binary write can arbitrarily be specified by a command as described above. The rewrite control circuit 159B is also capable of selecting the operation of rewriting the data first written at high speed in binary form into multivalue form. Upon writing binary data, written data is latched in a sense latch array. Namely, the multivalued data buffers 152 and 153 are not used upon writing the binary data. Upon writing multivalued data, written data are stored in the sense latch array and the multivalued data buffers 152 and 153 respectively.
FIGS. 13(a) to 13(c) show examples of the operating of rewriting the data written in binary form into multivalue form. For example, the binary data stored in a memory cell on a word line WL1 is read and temporarily held in the buffer 152. Next, the data is read from a memory cell on a word line WL2 and then the read data is held in the other buffer 153. Thus, when the 2-bit data represented in binary form are respectively latched in the data buffers 152 and 153, the 2-bit data are decoded by the corresponding data conversion circuit 158 to generate data to be written for quaternary writing, followed by supply to the sense latch. Thereafter, the decoded information is stored in a predetermined memory cell on a word line WL3 under the control of the reprogram control circuit 159A, i.e., its data is written therein as one logical value of four values. It is natural that write non-selection might be done depending on the result of the 2-bit decoding.
FIG. 14 shows another example of the conversion of binary data into multivalued data. In FIGS. 13(a) to 13(c), the 2 bits held in the two adjacent memory cells on the same word line were converted into the quaternary data. In FIG. 14, data in a buffer 153 are arranged behind all the data stored in a buffer 152. Next, each data string is separated or partitioned two by two from the beginning and the individual partitioned 2 bits are successively converted into quaternary data respectively.
FIGS. 15 through 19 respectively show the procedures for the operations of writing 2-bit binary data as tour values or quaternary data. Four values "01", "11", "10" and "00" indicative of quaternary data are respectively shown in the respective drawings. Threshold voltages of memory cells corresponding to the four values are associated with states of "01", "11", "10" and "00" respectively. As show n in FIG. 15, the memory cells with the quaternary data written therein are first kept in an erased state. Namely, they are kept in the state "00". Data written into sense latches SL1 through SL4 with respect to the four values "01", "11", "10" and "00" are defined as "1", "1", "1" and "0" as illustrated in FIG. 16, respectively. The data "1" latched in the corresponding sense latch allows the execution of writing and the data "0" allows the non-execution of writing. The write operations are divided into a first write shown in FIG. 16, a second write shown in FIG. 17 and a third write shown in FIG. 18. A series of first to third writes proceed until the data written into the corresponding sense latch results in "0". In the first through third writes, only verify voltages are different from one another and the control over the application of write pulse voltages is the same.
When the first write (verify voltage=Vt7) shown in FIG. 16 is performed, the threshold voltage of a memory cell to be written is brought to the state "01". Accordingly, a sense latch of a memory cell corresponding to quaternary data "01" is inverted to "0" and hence the writing of "01" is completed. Namely, the first write results in a write operation for obtaining a threshold state of "01" from the erased state.
When the second write (verify voltage=Vt9) shown in FIG. 17 is done subsequent to the first write, the threshold voltage of a memory cell to be written is brought to the state "11". Accordingly, a sense latch of a memory cell corresponding to quaternary data "11" is inverted to "0" and hence the writing of "11" is completed. Namely, the second write results in a write operation for obtaining a threshold state of "11" by being performed subsequent to the first write.
When the third write (verify voltage=Vt11) shown in FIG. 18 is done subsequent to the second write, the threshold voltage of a memory cell to be written is brought to the state "10". Accordingly, a sense latch of a memory cell corresponding to quaternary data "10" is inverted to "0" and hence the writing of "10" is terminated. Namely, the third write results in a write operation for obtaining a threshold state of "10" by being performed subsequent to the first write and the second write.
In a flash memory FMRY6 shown in FIG. 20, memory mats 1A and 2A dedicated to coarse write in the first write mode are physically distinguished from memory mats 1B and 2B dedicated to high-accuracy write (inclusive of multivalue write) in the second write mode. A sense latch array for the memory mats 1A and 2A is separated from a sense latch array for the memory mats 1B and 2B.
A flash memory FMRY7 shown in FIG. 21 is different from the configuration shown in FIG. 13 in that a sense latch array is shared between memory mats 1A and 2A dedicated to the coarse write and memory mats 1B and 2B dedicated to the high-accuracy write. Incidentally, the individual configurations and functions shown in FIGS. 20 and 21 are basically identical to those in the above description, and their detailed description will therefore be omitted.
In the configurations shown in FIGS. 20 and 21, a first pulse train generating circuit 100 for application of a write voltage and a first verify voltage generating circuit 102 are used for writing made to the memory mats 1A and 2A. Further, a second pulse train generating circuit 101 for application of a write voltage and a second verify voltage generating circuit 103 are used for writing made to the memory mats 1B and 2B.
Memory cell structures about a tunnel film thickness of each memory cell MC, the thickness of an interlayer insulator, the size of a floating gate, etc. can be individualized so as to be optimized for the memory mats 1A and 2A dedicated to the coarse write and the memory mats 1B and 2B dedicated to the high-accuracy write.
FIG. 22 shows an example in which data written in a first write mode (coarse write) and data written in a second write mode (high-accuracy write) are mixed into each memory mat. In order to mix data coarsely written in the first write mode into data written with high accuracy in the second write mode for each group of memory cells (hereinafter called "sector") in the memory mats 1 and 2, for example, a portion of the sector is defined as a management region 160 and information for identifying either the data written in the first write mode or the data written in the second write mode is written into this region 160. Referring to FIG. 22, MR1 through MRn and MC1 through MCm are represented as one sector. Of these, MC1 through MCm are defined as the management region corresponding to them. The identification information is assigned to bits suitable for MC1 through MCm. Another region for storing sector management information is assigned to the management region 160. In FIG. 22, a word line WL21 for the management region 160 is separated from a word line WL11 for a portion (normal region) 161 of the sector, which is other than the management region 160. This is intended to allow, for example, the erasing of sector data by inverting valid bits indicative of the effectiveness of the sector data in the management region 160. They may be disposed on the same word line according to a system for managing the sector data. Although other configurations of the flash memory are not shown in FIG. 22, the circuits shown in FIG. 1, for example are provided in FIG. 22 in addition to the above.
FIG. 23 is a flowchart for describing the write operation at the time that the configuration of FIG. 22 is adopted. When the written data is loaded into the corresponding sense latch upon writing, either the write voltage pulse for the first write mode or the write voltage pulse (inclusive of the multivalue write) for the second write mode, each having been described in the examples shown thus far, is selected depending on whether a written command corresponds to the first write mode (coarse write) or the second write mode (high-accuracy write including multivalue writing). If the command is found to be the first write mode, then, for example, "1" is written into the management region of the corresponding sector. If the command is found to be the second write mode, then, e.g., "0" is written into the management region of the corresponding sector. It is desirable that in order to make a decision as to either data in the first write mode or data in the second write mode after the reading of the data in the management region to be described later at this time, the erasing of the management region and the write threshold voltage distribution are the same even if the data is written into the normal region in either the first write mode or the second write mode. Therefore, X-system selection circuits are provided separately for the management region 160 and the normal region 161 in FIG. 22. Thus, since a word line voltage at verify with respect to the management region 160 can be set separately from a word line voltage at verify with respect to the normal region 161, the uniform erasing and writing of data from and into each memory cell in the management region 160 can be achieved regardless of whether the normal region is written in the first write mode or the second write mode.
FIG. 24 shows a flowchart for describing the read operation at the time that the configuration of FIG. 22 is adopted. When the data is read from the normal region 161, the sector management information is first supplied from the management region 160 of the corresponding sector to the writeerase determination circuit 80 through the column-system circuit 60 shown in FIG. 60. When the writeerase determination circuit 80 judges the selected information included in the supplied sector management information to be "1", the normal region of the corresponding sector holds the data written in the first write mode (coarse write) therein. Therefore, the ROM decoder 76 outputs a control signal to the power control circuit 82 based on the result of decision by the writeerase determination circuit 80 so as to select a first read word line voltage, whereby the data is read from the data region (normal region) 161. On the other hand, if the information is found to be "0", then a second read word line voltage is selected to read the data written in the second write mode (high-accuracy write including the multivalue write) from the normal region of the sector, whereby the data is read from the data region (normal region) 161.
FIG. 25 shows a flowchart for describing one example of the rewrite operation at the time that the configuration shown in FIG. 22 is adopted. A description will now be made of the case in which addresses from an address k to an address m are defined as objects to be rewritten. The address n is set as k (n=k) and data in a management region at the address n is read. When the data is found to be "1", data in a sector corresponding to the address has led to being written in the first write mode (coarse write). In this case, the data is read from the normal region 161 of the corresponding sector and a second word line voltage is selected to rewrite the data into the original data storage area in the second write mode (including high-accuracy write by multivalues). On the other hand, if the data is found to be "0", then the data is already written in the second write mode (including high-accuracy write by multivalues) and hence the object to be rewritten proceeds to the next address. The above operation is repeated until the intended final address is reached.
[3. Coarse write]
The various flash memories described above had the two coarse and high-accuracy write modes. Several examples of flash memories for carrying out high-speed write while paying attention to the execution of the coarse write will next be explained. Namely, the flash memories to be described have the coarse write mode alone.
A threshold voltage distribution shown in FIG. 26(a) is obtained from a flash memory wherein a write level (equivalent to a verify word line voltage at writing) is defined as, for example, 1.5V with respect to a power source voltage Vcc of, for example, 3.3V and the threshold voltage of a memory cell per