Title:
Digital feedback relay controller
United States Patent 3922587
Abstract:
System for accurately controlling the closure time of relays by storing the operating characteristics of the individual relays and using the data to determine the necessary activation time.
Application Number:
05/518085
Publication Date:
11/25/1975
Filing Date:
10/25/1974
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Export Citation:
Assignee:
RCA Corporation (New York, NY)
Primary Class:
Other Classes:
361/186
International Classes:
G01R31/327; H01H47/00
Field of Search:
340/172.5,173FF 317/123,137,DIG.6
Other References:
"Adaptor for Time Measurement of Relay Operation, Paslawski - Przeglad, Telekom Vol. 43 No. 6, 1970..
Primary Examiner:
Miller J. D.
Assistant Examiner:
Moose Jr., Harry E.
Attorney, Agent or Firm:
Norton, Edward Wright Carl J. M.
Claims:
What is claimed is
1. A system for controlling the closure of a plurality of relays comprising the combination of:
2. The invention claimed in claim 1 wherein said storage means includes:
3. The invention claimed in claim 2 wherein said pull-in time signal generating means includes:
4. The invention claimed in claim 3 wherein said drop-out time signal generating means includes:
5. The invention claimed in claim 2 wherein said relay control means includes:
6. The invention claimed in claim 5 wherein said relay control means further includes period counter means responsive to said timing signals and to said operating characteristics signals for inhibiting the activation of a relay.
7. The invention claimed in claim 6 including
8. The invention claimed in claim 6 wherein said pull-in counter and said period counter are also responsive to said relay indication means for varying the operation times of at least one of said plurality of relays.
9. A method of controlling the closure of a plurality of relays comprising the steps of: storing electrical signals representing the operating characteristics of each of said relays; selecting one of said relays to be operated; extracting the stored electrical signals representing the operating characteristics of the selected relay; and activating the selected relay for a desired period of time controlled by the operating characteristics signals of the selected relay.
1. A system for controlling the closure of a plurality of relays comprising the combination of:
2. The invention claimed in claim 1 wherein said storage means includes:
3. The invention claimed in claim 2 wherein said pull-in time signal generating means includes:
4. The invention claimed in claim 3 wherein said drop-out time signal generating means includes:
5. The invention claimed in claim 2 wherein said relay control means includes:
6. The invention claimed in claim 5 wherein said relay control means further includes period counter means responsive to said timing signals and to said operating characteristics signals for inhibiting the activation of a relay.
7. The invention claimed in claim 6 including
8. The invention claimed in claim 6 wherein said pull-in counter and said period counter are also responsive to said relay indication means for varying the operation times of at least one of said plurality of relays.
9. A method of controlling the closure of a plurality of relays comprising the steps of: storing electrical signals representing the operating characteristics of each of said relays; selecting one of said relays to be operated; extracting the stored electrical signals representing the operating characteristics of the selected relay; and activating the selected relay for a desired period of time controlled by the operating characteristics signals of the selected relay.
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to relay closure control systems where closure time must be accurate.
2. Description of the Prior Art
Relay networks, where the closure time of the relay must be within given tolerances, usually involve the selection of relays for the desired characteristics or the use of expensive relays designed to very close tolerances. Resistor-capacitor networks are sometimes provided with adjustments to permit the closure time to be adjusted. Closure adjustments can also be made mechanically by adjusting the pole-armature gap while activating the relay with a suitable read-out device to indicate the closure time. Such systems require a large amount of maintenance and must be continually checked as the relays age and wear causes changes in the closure time. Large systems, typically having hundreds of such relays, therefore require excessive maintenance.
This invention relates to an electronically controlled feedback system for controlling relay closures.
BRIEF SUMMARY OF THE INVENTION
System and method for controlling the closure of a plurality of electrically operated relays by storing signals that represent the operating characteristics of each relay is disclosed. When a relay is selected to be activated, its characteristics' signals are recovered from storage and used to determine the activation time required for a desired closure time. In one embodiment, the characteristics are stored as counts at a given frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an embodiment of the invention.
FIG. 2 is an illustration of an input system.
FIG. 3 is a schematic of an input system.
FIG. 4 is a table illustrating an input coding scheme.
FIGS. 5(a) and 5(b) are logic diagrams of an embodiment of a computer.
FIG. 6 is a timing diagram showing waveforms at various points in the computer.
FIG. 7 is a logic diagram of a data store suitable for use in the computer.
FIG. 8 is a logic diagram of an arithmetic unit suitable for use in the computer.
FIG. 9 is a logic diagram of a relay controller embodiment.
FIG. 10 is a schematic showing relay connections.
DETAILED DESCRIPTION OF THE EMBODIMENT
The block diagram of FIG. 1 illustrates the relation of the major components of a system according to the invention. An input system 2 provides data signals to a computer 5 signifying a sequence of relays to be operated. The output signals from the computer 5 are coupled to a relay controller 9 which is coupled to a relay bank 10. The relay bank 10 also provides input signals to the computer 5 by means of a return line.
For purposes of illustration, a certain sequence of numbers and control signals will be considered. The sequence of relays to be closed will represent 10 numbers which can be used for operating a telephone switching system. The number signals will be preceeded by a signal called FRONT and followed by a signal called START. The purpose of the FRONT signal is to initialize the switching system to which the relay output lines are coupled. The signal START indicates that all the numbers have been entered.
The input system 2 in FIG. 1 is shown in more detail in FIG. 2. It can be a keyboard with the digit keys 0 through 9 and function keys I, F, S and R. The F key activates the front relay and the S key activates the start relay. The R key provides a reset signal to the computer to permit a sequence to be interrupted and to reset the controls for a new number. The I key causes the computer 5 in FIG. 1 to initialize the data banks storing the operating characteristics of the relays. This will be explained in greater detail below.
The output signals from the input system 2 as shown in FIG. 2 are conducted by a seven line cable for purposes of illustration. Four of the lines carry signals indicating the key encoding, two of the lines carry the complement of two of the encoding lines, and the seventh line indicates that a key has been activated.
The circuit of FIG. 3 shows the details of one possible embodiment of the input system 2. All the switches have one contact coupled to a voltage bus. The other contact of each switch is coupled to one or more logic OR gates for encoding. For example, the keys 1, 3, 5, 7, 9, S, or I activate an OR gate 31. The output signal from the OR gate 31 represents a binary weight of 2 0 . An OR gate 32 is activated by the keys 2, 3, 6, 7, F, S, R, or I and its output signal represents a binary weight of 2 1 . An inverter 33 complements the value of the output signal from the OR gate 32. Similar OR gate encoding is used for producing signals K4 and K8 representing binary weights of 2 2 and 2 3 , respectively. Another OR gate 34 is coupled to the output signals from the encoding OR gates and to the zero key to provide a signal that indicates that a key has been pressed. A delay element 35 is provided to allow key bounce and static to subside before the signal is transmitted to the computer.
A typical encoding scheme is summarized in FIG. 4. The keys 0 through 9 are encoded into BCD or binary coded decimal. The F key is encoded as a binary 10; the S key, as a binary 11; the R key, as a binary 14, and the I key, as a binary 15. The complement of K4 is also provided by an inverter as in the case for the K2 signal.
The computer 5 (FIG. 1) can be a general purpose, stored-program, digital computer. A program can be provided so the computer can perform the functions which are described below in more detail for the operation of the computer. Computers have input/output bus lines to which the input system 2, the relay controller 9, and the feedback lines from the relay bank 10 can be connected. The program can accept and store the sequence of numbers provided by the input system, manipulate the operating characteristics of the relays, and provide signals to the relay controller 9 to cause the relays in the relay bank 10 to operate in the proper sequence and for the proper lengths of time.
The initialization operation sequences all the relays in the relay bank 10. The feedback lines to the computer 5 indicate that a relay has been activated. By using an internal clock, the computer can calculate the time that it takes a relay to pull in, i.e., the time required for the contacts to close after an electrical activation signal has been provided, by counting the number of clock pulses that occur between the transmission of the activation signal to the relay controller 9 and the return signal from the relay bank 10 indicating that a relay has been operated. By timing the period between the removal of the activation signal and a return signal indicating that no relay is closed, the drop out time can be measured. The drop out time is the time interval between the removal of an activation signal and the separation of the relay contacts. By performing this measurement for each relay, the closure time can be adjusted by the computer in one of several ways.
For purposes of illustration, the following control will be used. Each relay must operate during a specific period of time and the closure time must be a specific period of time. The closure time will be hereinafter referred as the width and the period of time during which the width will occur will be referred to as the period. The width can be controlled by a counter which is responsive to a known frequency so that a given count at a given frequency will equal the desired time period. The width count, therefore, refers to the value which would be set into a counter which would be operated to designate the width. Similarly, a period count is the count value at the known frequency during which the selected relay must operate and during which no other relay can operate. Each count, that is the width count and the period count, can be divided into a fixed and a variable portion. The fixed portion can be adjusted so that any variation due to the operating characteristics of a relay can be compensated for in the variable count. Therefore, the period count will be considered as a fixed count plus the count required for the pull-in time. Similarly, the width count will be considered as a fixed count plus the count for the pull-in time minus the count for the drop-out time. Variations of the desired timing and the times measured can be varied within the scope of the invention herein described. The remainder of the detailed description of the embodiment will be based on the above description of the timing measurements.
FIGS. 5a and 5b illustrate a computer of a fixed logic design which can be used for the computer 5 shown in FIG. 1. The description of the logic configuration shown in FIGS. 5a and 5b, describing the steps required to practice the invention, will enable a person of ordinary skill in the art to program a general purpose, stored program, digital computer to perform the same operations.
In FIG. 5b, an oscillator 510 produces a timing output signal labelled TPA, and an inverter 511 produces its complement, TBB. The output signal from the oscillator 510 also triggers a modulo-11 counter 514, the output signals from which are decoded by a decoder 516 into eleven timing pulses BT0-BT10. These timing signals are the lowest stratus in the timing hierarchy of the system. The oscillator 510, counter 514, and the decoder 516 are well known in the art, requiring no further explanation of their operation.
A complete sequence of the timing signals BT0-BT10 define a machine cycle. Each machine cycle is identified by a unique combination of the output signals from four control flip-flops 51-54 shown in FIG. 5a, which comprise the sequence control logic of the computer 5 (FIG. 1). The control flip-flops 51-54 are implemented as J-K flip-flops and are triggered by the first timing pulse, BT0. The operation of J-K flip-flops are well known in the art; see, for example, U.S. Pat. No. 3,588,545. Therefore, the first timing pulse, BT0, of a timing cycle will adjust the conditions of the control flip-flops 51-54 to define a particular machine state. During its operation, the computer uses 11 machine states, each of which will be explained in detail.
The first machine state, state 0, is an idle or hold-off state in which the machine waits for a key to be pressed. State 0 is defined by all the flip-flops 51-54 in the reset condition.
The seven wire cable from the input system 2 (FIG. 1) is shown as a cable 55 in FIG. 5a. The activation of the R key is detected by an AND gate 56; the I key, by an AND gate 57; the F key, by an AND gate 58; and the S key, by an AND gate 59. The AND gate 59 is also controlled by the D flip-flop 54 being reset.
The key pressed signal KP, indicating that a key has been activated, is coupled to the clock input of a D flip-flop 512, the D input signal of which is a continuous logical one. Therefore, the leading edge of the key pressed signal will set the flip-flop 512, which will be reset via a direct reset terminal as explained below.
The information signals from the keyboard via the cable 55 are also applied to a number store 515 which can be implemented by four parallel, 12-bit shift registers. Each of the encoded key bit signals furnishes the input signal to one of the shift registers, which are all shifted concurrently by the output signal from an AND gate 517. The output signals from the number store 515 are identified as NS8, NS4, NS2, and NS1.
When a key is pressed, the flip-flop 512 will be set. The next BT0 timing signal will set the A flip-flop 51 indicating that the computer is in machine state 1. The A flip-flop 51 is set via an AND gate 518 through an OR gate 519. The other flip-flops 52-54 do not change so that the machine state 1 is defined by the A flip-flop 51 being set and the B, C, and D flip-flops 52-54 being reset. Machine state 1 enables an AND gate 520 which, via an OR gate 521, primes an AND gate 522, which, when enabled by the timing signal BT1, resets the flip-flop 512.
The first key in a sequence must be an I key, and R key, or a F key. The F signal indicates the start of a number sequence which is to be stored in the number store 515. The R key resets the computer. The I key starts the initiation routine.
The R key signal is detected by the AND gate 56 which generates a reset signal via an AND gate 523 (FIG. 5b) during the timing pulses BT2-BT9 of state 1. The R signal also resets the A flip-flop 51 via an AND gate 524 and the OR gate 525 at the next BTO timing signal. The AND gate 524 is enabled by the B flip-flop 52 and the C flip-flop 53 being reset and by the output signal from an OR gate 526, which is enabled by the R signal from the AND gate 56 (FIG. 5a). Therefore, pressing the reset key resets the computer and returns it to the machine state 0.
When the I key is pressed, the computer goes from machine state 1 to machine state 13, defined by the A, C, and D flip-flops 51, 53, and 54 set and the B flip-flop 52 reset. The I key is recognized by the AND gate 57, the output signal from which is coupled to an AND gate 527 to set the C flip-flop 53 by the next BT0 timing signals. The output signal from the AND gate 57 is also coupled to an AND gate 528, which via an OR gate 529, sets the D flip-flop 54. The A flip-flop 51 remains set.
An AND gate 531 (FIG. 5b) is activated during the machine state 13 and its output signal enables four AND gates 532-535. The other input signal to the AND gates 532-535 are the output signals from a four-stage relay number counter 536. The counter 536 is reset during the machine state 0 via an AND gate 537 and an OR gate 538. The latter is also enabled by the output signal from the general reset AND gate 523. The relay number counter 536 is a ripple binary counter which is well known in the art with the output signal RN1 being the least significant bit and RN8, the most significant bit. Therefore, during the first occurrence of the machine state 13, the output signals from the relay number counter 536 indicates a relay number 0 which signals, via the AND gates 532-535 and four OR gates 539-542, are applied to a four-line bus.
The four-line bus is coupled to an address decoder 543 which activates a word line to a data store 506. The four-line bus is also coupled to four AND gates 544-547, the output signals from which are coupled to and OR gate 548. The other inputs signals to the AND gates 544-547 are the timing signals BT6 through BT9 so that the output signal from the OR gate 548 is the relay number in serial format. The output signal from the OR gate 548 is coupled to a bus C via an AND gate 549 and an OR gate 550 during the machine state 13. A bit signal is also produced from the OR gate 548 by the BT2 timing signal.
From machine state 13, the computer goes to a machine state 15 which is identified by all the control flip-flops 51-54 (FIG. 5a) set. The machine state 15 is entered by setting the B flip-flop 52 via an AND gate 551 and an OR gate 552.
During the machine state 15, a pull-in time counter 553 (FIG. 5b) is activated by an AND gate 554 to count clock pulses which originate in the relay controller. The period of the clock pulses is not greater than the desired timing error in the relay activation. For example, if the relays are to be timed to an accuracy of 1 millisecond, the clock frequency will be not less than 1 kilohertz. The frequency of the timing clock 510 is typically 1 megahertz.
The machine remains in the machince state 15 until and indication is received from the relay bank that a relay has closed, indicated by an RR signal from a flip-flop composed of two cross-coupled NAND gates 555 and 556. The signals from the relay bank will be described in greater detail below.
When the RR signal from the output of the NAND gate 556 indicates that a relay contact has closed, the computer goes to a machine state 7 by resetting the D flip-flop 54 (FIG. 5a) via an AND gate 557 and an OR gate 558. Resetting the D flip-flop disables the AND gate 554 and enables the AND gate 559 which operates the drop-out counter 560. When all relay contacts are open as indicated by a high signal from the NAND gate 555, the computer goes from the mchine state 7 to a machine state 5 by resetting the B flip-flop via an AND gate 561 and an OR gate 580 (FIG. 5a). In the machine state 5, the pull-in counter 553 and the drop-out counter 560 (FIG. 5b) contain count values which indicate the pull-in and drop-out times, respectively. During the machine state 5, these counter values are stored in the data store 506 via the AND gate 562. The details of the operation of the data store are described below.
During the machine state 5, the relay number in the counter 536 is advanced to the next number in sequence via an AND gate 563 which also resets the counters 533 and 560 via the OR gate 564. If the relay previously tested was not the last relay as indicated by a signal from the decoder 543, the computer returns to the machine state 13 by setting the D flip-flop 54 via the AND gate 565 and the OR gate 529. The above described sequence is repeated for each relay until the last relay is detected by the decoder 543, at which time the computer returns to the machine state 0 from machine state 5 by resetting the C flip-flop 53 via the AND gate 566 and by resetting the A flip-flop 51 via the AND gate 567.
Summarizing the operation of the computer when the I key is activated, the data store 506, which stores eight bits for each relay, stores a pull-in count from the counter 553 and a drop-out count from the counter 560 by activating each relay in turn and counting the number of clock pulses until the relay pulls in and by activating the relay and counting the number of clock pulses until the relay drops out. Pushing the initiation key automatically tests all the relays by sequencing the relay number counter 536 and cycling through the appropriate machine states.
Returning to the condition where the computer is in the machine state 1, an F key signal causes the computer to go to the machine state 2, which is identified by the D flip-flop 54, the C flip-flop 53, and the A flip-flop 51 being reset and the B flip-flop 52 being set. The A flip-flop 51 is reset via the AND gate 524 and the OR gate 525. The B flip-flop 52 is set via an AND gate 568 and the OR gate 552. In the machine state 1, the B flip-flop 54 and the C flip-flop 53 were already reset.
In the machine state 2, the exclusive OR gate 530 is activated by the B flip-flop 52 being set and the D flip-flop 54 being reset. The AND gate 517 is enabled by the A flip-flop being reset and the output signal from the exclusive OR gate 530 at time BT 10. The output signal from the AND gate 517 shifts the four parallel shift registers of the number store 515 to store the binary signals representing the key that was pressed. The signals representing the key are coupled to the number store 515 via the cable 55 as previously described.
If the key pressed was not the S button, which indicates that all numbers of a group have been entered, the computer goes to machine state 3 which is identified by the A flip-flop 51 and the B flip-flop 52 being set and the C flip-flop 53 and D flip-flop 54 being reset. The A flip-flop 57 is set by means of an AND gate 569 through the OR gate 519. Machine state 3 is a hold-off state in which the computer idles until another key is pressed.
The signal indicating that another key has been pressed returns the computer to the machine state 2 by resetting the A flip-flop 51 via an AND gate 570 and the OR gate 525 to the reset terminal and via the AND gate 518 or the AND gate 569 via the OR gate 519 to the set terminal; with both input signals activated, the A flip-flop 51 will be triggered to its opposite state, i.e., reset. Again, in machine state 2, the signals representing the activated key are stored in the number store 515 by the action of the AND gate 517 and the Exclusive OR gate 530. The flip-flop 512 (FIG. 5a) is reset via an AND gate 590 through the OR gate 521 and the AND gate 522. The above sequence of steps continues until the S key has been activated and its signals stored.
In the machine state 2, when the S key is pressed, the AND gate 59 is activated by the signals from the keyboard and the output reset signal from the D flip-flop 54. The output signal from the AND gate 59 is coupled to an input terminal of an OR gate 571. The complement of the output signal from the OR gate 571 is provided by an inverter 572.
After the signals representing the S key have been stored in the number store 515, the computer goes to machine state 11 identified by the A flip-flop 51, the B flip-flop 52, and the D flip-flop 54 being set and the C flip-flop 53 being reset. The A flip-flop 51 is set via the AND gate 569 and the OR gate 519. The D flip-flop 54 is set via an AND gate 573 through the OR gate 529. The other two control flip-flops are in the correct condition from the machine state 2.
In the machine state 11, the relay number is transmitted serially to the controller. An AND gate 574 (FIG. 5b) is activated to enable four AND gates 575-578 to pass the number represented by the signals from the output terminals of the number store 515 to the OR gates 539-542 and to the bus C at the output terminal of the OR gate 550 via the AND gates 544-547, the OR gate 548 and the AND gate 549 as has been previously described.
From the machine state 11, the computer goes to machine state 8 identified by the D flip-flop 54 being set and the A flip-flop 51, the B flip-flop 52, and the C flip-flop 53 being reset. The B flip-flop 52 is reset via the AND gate 574 (FIG. 5b) through the OR gate 580. The A flip-flop 51 is reset via an AND gate 581 through the OR gate 525.
During the machine state 8, the data signals indicating the relay characteristics are gated to the controller from the data store 506 (FIG. 5b) by an AND gate 591 via an arithmetic unit 508. The address to the data store 506 is provided to the decoder 543 via the AND gate 574, the AND gates 575-578, and the OR gates 539-542. The output signals from the arithmetic unit 508 will be described in more detail below. The output signals from the arithmetic unit 508 provide the input signals to eight parallel AND gates 583 each of which is enabled by a different one of the timing signals BT2 through BT9. The output signals from the AND gate network 583 are serially combined by an OR gate 584 and coupled to the bus C via an AND gate 585 and the OR gate 550 during the machine state 8.
From the machine state 8, the computer goes to machine state 10 if the S symbol signals have not been transmitted to the controller. Machine state 10 is identified by the D flip-flop 54 and the B flip-flop 52 being set and the C flip-flop 53 and the A flip-flop 51 being reset. The B flip-flop 52 is set via an AND gate 586. The input signals to the AND gate 586 are the set output signals from the D flip-flop 54 and the output signal from the inverter 572. The S signal will be detected by an AND gate 587 from the output signals from the number store 515, one of which signals is inverted by an inverter 588. The function of the machine state 10 is to idle the computer until a ready signal is received from the controller that the next number is to be transmitted. The ready signal returned from the controller causes the computer to return the machine state 11 by setting the A flip-flop 51 via an AND gate 589.
In the machine state 8, after an S signal has been sent to the controller, the computer returns to the machine state 0 by resetting the D flip-flop 54 via an AND gate 592.
During the machine state 1, the controller is enabled by an output signal from an AND gate 593 (FIG. 5b). During the machine state 11, the output signal from an AND gate 594 is transmitted to the controller to indicate that the data on the bus represent a relay number. The timing signals BT2 through BT9 are applied to the input terminals of an OR gate 595 and transmitted as a timing level to the controller.
An embodiment of the controller is illustrated by the logic diagram of FIG. 9. An eight bit shift register 91 is coupled to the bus C for receiving the signals indicating the relay number. The data bits from the bus C are shifted into the shift register 91 by the output signal from an AND gate 92.
Another eight bit shift register 93 receives the data specifying the relays operating characteristics. It is controlled by the output signal from an AND gate 94. The signal from the AND gate 597 (FIG. 5b) is applied to the AND gate 92 via an OR gate 95 and to the AND gate 94 to indicate that information is on the bus. The output signal from the AND gate 594 (FIG. 5b) is applied to the AND gate 92 to indicate that the data on the bus are a relay number. Its complement from the inverter 598 (FIG. 5b) is applied to the AND gate 94 to indicate that the relay characteristics data are on the bus. The output signal from the OR gate 595 is also applied to the AND gates 92 and 94 to indicate the time that the data is on the bus. The gates are enabled by the output signal from the oscillator 510 (FIG. 5b).
The relay numbers comprise four binary signals which are the last four bits that are transmitted on the bus. The time pulse input signal BT2 to the OR gate 548 causes the leading bit to be a one which primes the D input terminal of a flip-flop 96. The following BT10 time signal sets the flip-flop 96 indicating that the relay number has been loaded.
During the initiation phase, the control signals described above are not transmitted to the controller from the computer. Instead, the output signal from the AND gate 593 (FIG. 5b) is applied to enable the decoder 97 via an OR gate 98. When enabled, the encoder 97 produces an output signal that activates the relay whose binary representation signals are stored in the shift register 91. During the initiation phase, the AND gate 92 is enabled by the output from the AND gate 531 (FIG. 5b) via the OR gate 95.
A flip-flop 99 is primed by an OR gate 910. Initially, the flip-flop 99 is set by the F signal, from the first relay to be activated, from the decoder 97. An AND gate 911 is enabled by the setting of the flip-flops 96 and 99 after the relay characteristics have been shifted into the shift register 93. The output signal from the AND gate 911 loads four counters 912-915. The counter 912 is a variable counter which depends on the most significant four bits of the relay characteristics in the shift register 93. The counter 912 operates in conjunction with a fixed counter 913 which produces an output signal at the completion of the fixed plus variable count. The output signal from the counters 912 and 913 is inverted by an inverter 916 to produce an enabling signal to the decoder 97 via the OR gate 98. The counters 912 and 913 determine the closure time of the relay being activated.
The counter 914 is a variable counter whose interval depends on the least significant four bits in the shift register 93 and the counter 914 operates in conjunction with the fixed interval counter 915. The output signal from the counter 915 is inverted by an inverter 917.
The counters 912 and 913 are enabled by the output signal from the inverter 916 and the counters 914 and 915 are enabled by the output signal from the inverter 917. Enabling the counters by the inverter output signals prevents the counters from over-running, i.e., once an output signal is produced, the counters are stopped until they are reset. The output signal from the inverter 916 provides a signal to the OR gate 98 to enable the encoder 97 and thus activate the selected relay until the counters 912 and 913 have completed their count. At the end of their count, the output signals from the inverter 916 disables the decoder by removing the enabling signal from the OR gate 98. This causes the relays to open.
The counters 914 and 915 continue to count until the end of the desired period at which time the output signal from the counter 915 primes the ready flip-flop 99. As previously described, the set output signal from the flip-flop 96 causes the computer to go to the machine state 11 to transmit the next relay number and its associated characteristics.
Clock signals to the counters 912-915 in FIG. 9 and to counters 553 and 560 in FIG. 5b are provided by a resettable clock 918. The clock circuit 918 can be synchronized with the output from the oscillator 510 and can be reset by the output signal from the AND gate 911. The reset signal can be used to control a flip-flop which inhibits the output from the clock circuit 918 and the clock circuit can be a count down counter which divides the frequency of the oscillator 510 by some suitable integer to produce the desired clock width as described above.
The fixed interval counters 913 and 915 are coupled to reference voltages to set the desired fixed interval. The interval for various relays may be changed by appropriate gating at the input to the fixed counters 913 and 915. For example, the values loaded in the counters 913 and 915 are different when the F relay is activated from those when the remaining relays are activated by coupling the output signal from an inverter 919 to the most significant bit of each of the counters 913 and 915.
Two of the relays in the relay bank 10 of FIG. 1 are illustrated in FIG. 10. The appropriate output signal from the encoder 97 is coupled to a driver circuit 101 or 102. The driver circuits provide the required current to operate the relay. Each relay has a set of normally opened contacts 103 which provide the output signals from the relay bank. A second set of transfer contacts 104 is provided to furnish the return signals to the computer, more specifically, to the NAND gates 555 and 556 in FIG. 5b.
FIG. 6 is an illustration of the timing signals at various points in the logic described above. FIG. 6a is the output signal from the oscillator 510 and FIG. 6b is the complemented signal from the inverter 511. FIG. 6c is the output signal from the AND gate 597 during the appropriate machine states. FIG. 6d is the timing signal BT1 from the decoder 516. FIG. 6e is the output signal from the OR gate 595. FIG. 6f shows the relationship of the signal BT0 from the output of the decoder 516. FIG. 6g represents the output signal from the AND gate 594 during the appropriate machine states.
The details of the data store 506 of FIG. 5b are shown in FIG. 7. The input lines from the counters 560 and 553 are coupled to the D input terminals of a plurality of flip-flops, such as a typical flip-flop 71. A Write signal from the AND gate 562 is coupled to a plurality of AND gates such as an AND gate 72, which produces a signal that clocks the D flip-flop 71. The other input to the AND gate 72 is a word line output signal from the address decoder 543. Each row of storage flip-flops in the data store is controlled by a separate word line. Each column is controlled by a separate input line and produces a separate output signal. Only one word line is activated at a time and determines the row in which the input data are stored or from which the data are read. The read signal from the AND gate 591 is coupled to a plurality of AND gates such as an AND gate 73. The other input to the read AND gates are the word line for the corresponding rows. The output signal of the AND gate 73 enables a second plurality of AND gates such as an AND gate 74 which produces a signal on the output line depending on the data stored in the corresponding flip-flop.
The output lines from the data store 506 (FIG. 5b) are coupled to an arithmetic unit 508 which is shown in more detail in FIG. 8. The most significant four bits from the data store 506 represent the pull-in time count and are gated directly to the most significant four output signal lines of the arithmetic unit 508. The least significant four bits represent the drop-out time and are coupled to a plurality of subtracter circuits such as a subtracter 81. The other input signal to the subtracter is the corresponding bit of the pull-in count value so that the output bits from the subtracter circuits represent the difference of the pull-in count minus the drop-out count. To insure a positive result, a bit value having a binary weight of 2 3 is added to the pull-in time by means of an adder 82. The adder 82 is similar to the subtracter 81 except that the inverter 83 is omitted. The input signals to the adder 82 are the most significant bit of the pull-in count and a signal representing a constant binary one. The subtracter 81 is cascaded with the subtracter 84 which in turn is cascaded to the subtracter 85. The subtracter 85 is cascaded with the subtracter 86 which is cascaded with the subtracter 87. The subtracter 86 receives the binary bit with the weight of 2 3 from the pull-in counter to which one is added by the adder 82. The adder 82 furnishes a carry signal to the subtracter 87 to provide an overflow indication. The output signal from the subtracter 87 is not used in the embodiment of the invention described in FIG. 5a but can be used to test for an illegal condition, i.e., the drop-out count is greater than the pull-in count plus eight.
The embodiment described shows how the operating characteristics of a plurality of relays can be determined and stored as electrical signals and used to control the closure time of the relays to a desired degree of accuracy. It has been shown how the closure time can be changed for each relay and how error checks can be made for certain out-of-limit characteristics. Various modifications to the system and circuits described and illustrated to explain the concepts and modes of practicing the invention might be made by those of ordinary skill in the art within the principles and scope of the invention as expressed in the appended claims.
1. Field of the Invention
This invention relates to relay closure control systems where closure time must be accurate.
2. Description of the Prior Art
Relay networks, where the closure time of the relay must be within given tolerances, usually involve the selection of relays for the desired characteristics or the use of expensive relays designed to very close tolerances. Resistor-capacitor networks are sometimes provided with adjustments to permit the closure time to be adjusted. Closure adjustments can also be made mechanically by adjusting the pole-armature gap while activating the relay with a suitable read-out device to indicate the closure time. Such systems require a large amount of maintenance and must be continually checked as the relays age and wear causes changes in the closure time. Large systems, typically having hundreds of such relays, therefore require excessive maintenance.
This invention relates to an electronically controlled feedback system for controlling relay closures.
BRIEF SUMMARY OF THE INVENTION
System and method for controlling the closure of a plurality of electrically operated relays by storing signals that represent the operating characteristics of each relay is disclosed. When a relay is selected to be activated, its characteristics' signals are recovered from storage and used to determine the activation time required for a desired closure time. In one embodiment, the characteristics are stored as counts at a given frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an embodiment of the invention.
FIG. 2 is an illustration of an input system.
FIG. 3 is a schematic of an input system.
FIG. 4 is a table illustrating an input coding scheme.
FIGS. 5(a) and 5(b) are logic diagrams of an embodiment of a computer.
FIG. 6 is a timing diagram showing waveforms at various points in the computer.
FIG. 7 is a logic diagram of a data store suitable for use in the computer.
FIG. 8 is a logic diagram of an arithmetic unit suitable for use in the computer.
FIG. 9 is a logic diagram of a relay controller embodiment.
FIG. 10 is a schematic showing relay connections.
DETAILED DESCRIPTION OF THE EMBODIMENT
The block diagram of FIG. 1 illustrates the relation of the major components of a system according to the invention. An input system 2 provides data signals to a computer 5 signifying a sequence of relays to be operated. The output signals from the computer 5 are coupled to a relay controller 9 which is coupled to a relay bank 10. The relay bank 10 also provides input signals to the computer 5 by means of a return line.
For purposes of illustration, a certain sequence of numbers and control signals will be considered. The sequence of relays to be closed will represent 10 numbers which can be used for operating a telephone switching system. The number signals will be preceeded by a signal called FRONT and followed by a signal called START. The purpose of the FRONT signal is to initialize the switching system to which the relay output lines are coupled. The signal START indicates that all the numbers have been entered.
The input system 2 in FIG. 1 is shown in more detail in FIG. 2. It can be a keyboard with the digit keys 0 through 9 and function keys I, F, S and R. The F key activates the front relay and the S key activates the start relay. The R key provides a reset signal to the computer to permit a sequence to be interrupted and to reset the controls for a new number. The I key causes the computer 5 in FIG. 1 to initialize the data banks storing the operating characteristics of the relays. This will be explained in greater detail below.
The output signals from the input system 2 as shown in FIG. 2 are conducted by a seven line cable for purposes of illustration. Four of the lines carry signals indicating the key encoding, two of the lines carry the complement of two of the encoding lines, and the seventh line indicates that a key has been activated.
The circuit of FIG. 3 shows the details of one possible embodiment of the input system 2. All the switches have one contact coupled to a voltage bus. The other contact of each switch is coupled to one or more logic OR gates for encoding. For example, the keys 1, 3, 5, 7, 9, S, or I activate an OR gate 31. The output signal from the OR gate 31 represents a binary weight of 2 0 . An OR gate 32 is activated by the keys 2, 3, 6, 7, F, S, R, or I and its output signal represents a binary weight of 2 1 . An inverter 33 complements the value of the output signal from the OR gate 32. Similar OR gate encoding is used for producing signals K4 and K8 representing binary weights of 2 2 and 2 3 , respectively. Another OR gate 34 is coupled to the output signals from the encoding OR gates and to the zero key to provide a signal that indicates that a key has been pressed. A delay element 35 is provided to allow key bounce and static to subside before the signal is transmitted to the computer.
A typical encoding scheme is summarized in FIG. 4. The keys 0 through 9 are encoded into BCD or binary coded decimal. The F key is encoded as a binary 10; the S key, as a binary 11; the R key, as a binary 14, and the I key, as a binary 15. The complement of K4 is also provided by an inverter as in the case for the K2 signal.
The computer 5 (FIG. 1) can be a general purpose, stored-program, digital computer. A program can be provided so the computer can perform the functions which are described below in more detail for the operation of the computer. Computers have input/output bus lines to which the input system 2, the relay controller 9, and the feedback lines from the relay bank 10 can be connected. The program can accept and store the sequence of numbers provided by the input system, manipulate the operating characteristics of the relays, and provide signals to the relay controller 9 to cause the relays in the relay bank 10 to operate in the proper sequence and for the proper lengths of time.
The initialization operation sequences all the relays in the relay bank 10. The feedback lines to the computer 5 indicate that a relay has been activated. By using an internal clock, the computer can calculate the time that it takes a relay to pull in, i.e., the time required for the contacts to close after an electrical activation signal has been provided, by counting the number of clock pulses that occur between the transmission of the activation signal to the relay controller 9 and the return signal from the relay bank 10 indicating that a relay has been operated. By timing the period between the removal of the activation signal and a return signal indicating that no relay is closed, the drop out time can be measured. The drop out time is the time interval between the removal of an activation signal and the separation of the relay contacts. By performing this measurement for each relay, the closure time can be adjusted by the computer in one of several ways.
For purposes of illustration, the following control will be used. Each relay must operate during a specific period of time and the closure time must be a specific period of time. The closure time will be hereinafter referred as the width and the period of time during which the width will occur will be referred to as the period. The width can be controlled by a counter which is responsive to a known frequency so that a given count at a given frequency will equal the desired time period. The width count, therefore, refers to the value which would be set into a counter which would be operated to designate the width. Similarly, a period count is the count value at the known frequency during which the selected relay must operate and during which no other relay can operate. Each count, that is the width count and the period count, can be divided into a fixed and a variable portion. The fixed portion can be adjusted so that any variation due to the operating characteristics of a relay can be compensated for in the variable count. Therefore, the period count will be considered as a fixed count plus the count required for the pull-in time. Similarly, the width count will be considered as a fixed count plus the count for the pull-in time minus the count for the drop-out time. Variations of the desired timing and the times measured can be varied within the scope of the invention herein described. The remainder of the detailed description of the embodiment will be based on the above description of the timing measurements.
FIGS. 5a and 5b illustrate a computer of a fixed logic design which can be used for the computer 5 shown in FIG. 1. The description of the logic configuration shown in FIGS. 5a and 5b, describing the steps required to practice the invention, will enable a person of ordinary skill in the art to program a general purpose, stored program, digital computer to perform the same operations.
In FIG. 5b, an oscillator 510 produces a timing output signal labelled TPA, and an inverter 511 produces its complement, TBB. The output signal from the oscillator 510 also triggers a modulo-11 counter 514, the output signals from which are decoded by a decoder 516 into eleven timing pulses BT0-BT10. These timing signals are the lowest stratus in the timing hierarchy of the system. The oscillator 510, counter 514, and the decoder 516 are well known in the art, requiring no further explanation of their operation.
A complete sequence of the timing signals BT0-BT10 define a machine cycle. Each machine cycle is identified by a unique combination of the output signals from four control flip-flops 51-54 shown in FIG. 5a, which comprise the sequence control logic of the computer 5 (FIG. 1). The control flip-flops 51-54 are implemented as J-K flip-flops and are triggered by the first timing pulse, BT0. The operation of J-K flip-flops are well known in the art; see, for example, U.S. Pat. No. 3,588,545. Therefore, the first timing pulse, BT0, of a timing cycle will adjust the conditions of the control flip-flops 51-54 to define a particular machine state. During its operation, the computer uses 11 machine states, each of which will be explained in detail.
The first machine state, state 0, is an idle or hold-off state in which the machine waits for a key to be pressed. State 0 is defined by all the flip-flops 51-54 in the reset condition.
The seven wire cable from the input system 2 (FIG. 1) is shown as a cable 55 in FIG. 5a. The activation of the R key is detected by an AND gate 56; the I key, by an AND gate 57; the F key, by an AND gate 58; and the S key, by an AND gate 59. The AND gate 59 is also controlled by the D flip-flop 54 being reset.
The key pressed signal KP, indicating that a key has been activated, is coupled to the clock input of a D flip-flop 512, the D input signal of which is a continuous logical one. Therefore, the leading edge of the key pressed signal will set the flip-flop 512, which will be reset via a direct reset terminal as explained below.
The information signals from the keyboard via the cable 55 are also applied to a number store 515 which can be implemented by four parallel, 12-bit shift registers. Each of the encoded key bit signals furnishes the input signal to one of the shift registers, which are all shifted concurrently by the output signal from an AND gate 517. The output signals from the number store 515 are identified as NS8, NS4, NS2, and NS1.
When a key is pressed, the flip-flop 512 will be set. The next BT0 timing signal will set the A flip-flop 51 indicating that the computer is in machine state 1. The A flip-flop 51 is set via an AND gate 518 through an OR gate 519. The other flip-flops 52-54 do not change so that the machine state 1 is defined by the A flip-flop 51 being set and the B, C, and D flip-flops 52-54 being reset. Machine state 1 enables an AND gate 520 which, via an OR gate 521, primes an AND gate 522, which, when enabled by the timing signal BT1, resets the flip-flop 512.
The first key in a sequence must be an I key, and R key, or a F key. The F signal indicates the start of a number sequence which is to be stored in the number store 515. The R key resets the computer. The I key starts the initiation routine.
The R key signal is detected by the AND gate 56 which generates a reset signal via an AND gate 523 (FIG. 5b) during the timing pulses BT2-BT9 of state 1. The R signal also resets the A flip-flop 51 via an AND gate 524 and the OR gate 525 at the next BTO timing signal. The AND gate 524 is enabled by the B flip-flop 52 and the C flip-flop 53 being reset and by the output signal from an OR gate 526, which is enabled by the R signal from the AND gate 56 (FIG. 5a). Therefore, pressing the reset key resets the computer and returns it to the machine state 0.
When the I key is pressed, the computer goes from machine state 1 to machine state 13, defined by the A, C, and D flip-flops 51, 53, and 54 set and the B flip-flop 52 reset. The I key is recognized by the AND gate 57, the output signal from which is coupled to an AND gate 527 to set the C flip-flop 53 by the next BT0 timing signals. The output signal from the AND gate 57 is also coupled to an AND gate 528, which via an OR gate 529, sets the D flip-flop 54. The A flip-flop 51 remains set.
An AND gate 531 (FIG. 5b) is activated during the machine state 13 and its output signal enables four AND gates 532-535. The other input signal to the AND gates 532-535 are the output signals from a four-stage relay number counter 536. The counter 536 is reset during the machine state 0 via an AND gate 537 and an OR gate 538. The latter is also enabled by the output signal from the general reset AND gate 523. The relay number counter 536 is a ripple binary counter which is well known in the art with the output signal RN1 being the least significant bit and RN8, the most significant bit. Therefore, during the first occurrence of the machine state 13, the output signals from the relay number counter 536 indicates a relay number 0 which signals, via the AND gates 532-535 and four OR gates 539-542, are applied to a four-line bus.
The four-line bus is coupled to an address decoder 543 which activates a word line to a data store 506. The four-line bus is also coupled to four AND gates 544-547, the output signals from which are coupled to and OR gate 548. The other inputs signals to the AND gates 544-547 are the timing signals BT6 through BT9 so that the output signal from the OR gate 548 is the relay number in serial format. The output signal from the OR gate 548 is coupled to a bus C via an AND gate 549 and an OR gate 550 during the machine state 13. A bit signal is also produced from the OR gate 548 by the BT2 timing signal.
From machine state 13, the computer goes to a machine state 15 which is identified by all the control flip-flops 51-54 (FIG. 5a) set. The machine state 15 is entered by setting the B flip-flop 52 via an AND gate 551 and an OR gate 552.
During the machine state 15, a pull-in time counter 553 (FIG. 5b) is activated by an AND gate 554 to count clock pulses which originate in the relay controller. The period of the clock pulses is not greater than the desired timing error in the relay activation. For example, if the relays are to be timed to an accuracy of 1 millisecond, the clock frequency will be not less than 1 kilohertz. The frequency of the timing clock 510 is typically 1 megahertz.
The machine remains in the machince state 15 until and indication is received from the relay bank that a relay has closed, indicated by an RR signal from a flip-flop composed of two cross-coupled NAND gates 555 and 556. The signals from the relay bank will be described in greater detail below.
When the RR signal from the output of the NAND gate 556 indicates that a relay contact has closed, the computer goes to a machine state 7 by resetting the D flip-flop 54 (FIG. 5a) via an AND gate 557 and an OR gate 558. Resetting the D flip-flop disables the AND gate 554 and enables the AND gate 559 which operates the drop-out counter 560. When all relay contacts are open as indicated by a high signal from the NAND gate 555, the computer goes from the mchine state 7 to a machine state 5 by resetting the B flip-flop via an AND gate 561 and an OR gate 580 (FIG. 5a). In the machine state 5, the pull-in counter 553 and the drop-out counter 560 (FIG. 5b) contain count values which indicate the pull-in and drop-out times, respectively. During the machine state 5, these counter values are stored in the data store 506 via the AND gate 562. The details of the operation of the data store are described below.
During the machine state 5, the relay number in the counter 536 is advanced to the next number in sequence via an AND gate 563 which also resets the counters 533 and 560 via the OR gate 564. If the relay previously tested was not the last relay as indicated by a signal from the decoder 543, the computer returns to the machine state 13 by setting the D flip-flop 54 via the AND gate 565 and the OR gate 529. The above described sequence is repeated for each relay until the last relay is detected by the decoder 543, at which time the computer returns to the machine state 0 from machine state 5 by resetting the C flip-flop 53 via the AND gate 566 and by resetting the A flip-flop 51 via the AND gate 567.
Summarizing the operation of the computer when the I key is activated, the data store 506, which stores eight bits for each relay, stores a pull-in count from the counter 553 and a drop-out count from the counter 560 by activating each relay in turn and counting the number of clock pulses until the relay pulls in and by activating the relay and counting the number of clock pulses until the relay drops out. Pushing the initiation key automatically tests all the relays by sequencing the relay number counter 536 and cycling through the appropriate machine states.
Returning to the condition where the computer is in the machine state 1, an F key signal causes the computer to go to the machine state 2, which is identified by the D flip-flop 54, the C flip-flop 53, and the A flip-flop 51 being reset and the B flip-flop 52 being set. The A flip-flop 51 is reset via the AND gate 524 and the OR gate 525. The B flip-flop 52 is set via an AND gate 568 and the OR gate 552. In the machine state 1, the B flip-flop 54 and the C flip-flop 53 were already reset.
In the machine state 2, the exclusive OR gate 530 is activated by the B flip-flop 52 being set and the D flip-flop 54 being reset. The AND gate 517 is enabled by the A flip-flop being reset and the output signal from the exclusive OR gate 530 at time BT 10. The output signal from the AND gate 517 shifts the four parallel shift registers of the number store 515 to store the binary signals representing the key that was pressed. The signals representing the key are coupled to the number store 515 via the cable 55 as previously described.
If the key pressed was not the S button, which indicates that all numbers of a group have been entered, the computer goes to machine state 3 which is identified by the A flip-flop 51 and the B flip-flop 52 being set and the C flip-flop 53 and D flip-flop 54 being reset. The A flip-flop 57 is set by means of an AND gate 569 through the OR gate 519. Machine state 3 is a hold-off state in which the computer idles until another key is pressed.
The signal indicating that another key has been pressed returns the computer to the machine state 2 by resetting the A flip-flop 51 via an AND gate 570 and the OR gate 525 to the reset terminal and via the AND gate 518 or the AND gate 569 via the OR gate 519 to the set terminal; with both input signals activated, the A flip-flop 51 will be triggered to its opposite state, i.e., reset. Again, in machine state 2, the signals representing the activated key are stored in the number store 515 by the action of the AND gate 517 and the Exclusive OR gate 530. The flip-flop 512 (FIG. 5a) is reset via an AND gate 590 through the OR gate 521 and the AND gate 522. The above sequence of steps continues until the S key has been activated and its signals stored.
In the machine state 2, when the S key is pressed, the AND gate 59 is activated by the signals from the keyboard and the output reset signal from the D flip-flop 54. The output signal from the AND gate 59 is coupled to an input terminal of an OR gate 571. The complement of the output signal from the OR gate 571 is provided by an inverter 572.
After the signals representing the S key have been stored in the number store 515, the computer goes to machine state 11 identified by the A flip-flop 51, the B flip-flop 52, and the D flip-flop 54 being set and the C flip-flop 53 being reset. The A flip-flop 51 is set via the AND gate 569 and the OR gate 519. The D flip-flop 54 is set via an AND gate 573 through the OR gate 529. The other two control flip-flops are in the correct condition from the machine state 2.
In the machine state 11, the relay number is transmitted serially to the controller. An AND gate 574 (FIG. 5b) is activated to enable four AND gates 575-578 to pass the number represented by the signals from the output terminals of the number store 515 to the OR gates 539-542 and to the bus C at the output terminal of the OR gate 550 via the AND gates 544-547, the OR gate 548 and the AND gate 549 as has been previously described.
From the machine state 11, the computer goes to machine state 8 identified by the D flip-flop 54 being set and the A flip-flop 51, the B flip-flop 52, and the C flip-flop 53 being reset. The B flip-flop 52 is reset via the AND gate 574 (FIG. 5b) through the OR gate 580. The A flip-flop 51 is reset via an AND gate 581 through the OR gate 525.
During the machine state 8, the data signals indicating the relay characteristics are gated to the controller from the data store 506 (FIG. 5b) by an AND gate 591 via an arithmetic unit 508. The address to the data store 506 is provided to the decoder 543 via the AND gate 574, the AND gates 575-578, and the OR gates 539-542. The output signals from the arithmetic unit 508 will be described in more detail below. The output signals from the arithmetic unit 508 provide the input signals to eight parallel AND gates 583 each of which is enabled by a different one of the timing signals BT2 through BT9. The output signals from the AND gate network 583 are serially combined by an OR gate 584 and coupled to the bus C via an AND gate 585 and the OR gate 550 during the machine state 8.
From the machine state 8, the computer goes to machine state 10 if the S symbol signals have not been transmitted to the controller. Machine state 10 is identified by the D flip-flop 54 and the B flip-flop 52 being set and the C flip-flop 53 and the A flip-flop 51 being reset. The B flip-flop 52 is set via an AND gate 586. The input signals to the AND gate 586 are the set output signals from the D flip-flop 54 and the output signal from the inverter 572. The S signal will be detected by an AND gate 587 from the output signals from the number store 515, one of which signals is inverted by an inverter 588. The function of the machine state 10 is to idle the computer until a ready signal is received from the controller that the next number is to be transmitted. The ready signal returned from the controller causes the computer to return the machine state 11 by setting the A flip-flop 51 via an AND gate 589.
In the machine state 8, after an S signal has been sent to the controller, the computer returns to the machine state 0 by resetting the D flip-flop 54 via an AND gate 592.
During the machine state 1, the controller is enabled by an output signal from an AND gate 593 (FIG. 5b). During the machine state 11, the output signal from an AND gate 594 is transmitted to the controller to indicate that the data on the bus represent a relay number. The timing signals BT2 through BT9 are applied to the input terminals of an OR gate 595 and transmitted as a timing level to the controller.
An embodiment of the controller is illustrated by the logic diagram of FIG. 9. An eight bit shift register 91 is coupled to the bus C for receiving the signals indicating the relay number. The data bits from the bus C are shifted into the shift register 91 by the output signal from an AND gate 92.
Another eight bit shift register 93 receives the data specifying the relays operating characteristics. It is controlled by the output signal from an AND gate 94. The signal from the AND gate 597 (FIG. 5b) is applied to the AND gate 92 via an OR gate 95 and to the AND gate 94 to indicate that information is on the bus. The output signal from the AND gate 594 (FIG. 5b) is applied to the AND gate 92 to indicate that the data on the bus are a relay number. Its complement from the inverter 598 (FIG. 5b) is applied to the AND gate 94 to indicate that the relay characteristics data are on the bus. The output signal from the OR gate 595 is also applied to the AND gates 92 and 94 to indicate the time that the data is on the bus. The gates are enabled by the output signal from the oscillator 510 (FIG. 5b).
The relay numbers comprise four binary signals which are the last four bits that are transmitted on the bus. The time pulse input signal BT2 to the OR gate 548 causes the leading bit to be a one which primes the D input terminal of a flip-flop 96. The following BT10 time signal sets the flip-flop 96 indicating that the relay number has been loaded.
During the initiation phase, the control signals described above are not transmitted to the controller from the computer. Instead, the output signal from the AND gate 593 (FIG. 5b) is applied to enable the decoder 97 via an OR gate 98. When enabled, the encoder 97 produces an output signal that activates the relay whose binary representation signals are stored in the shift register 91. During the initiation phase, the AND gate 92 is enabled by the output from the AND gate 531 (FIG. 5b) via the OR gate 95.
A flip-flop 99 is primed by an OR gate 910. Initially, the flip-flop 99 is set by the F signal, from the first relay to be activated, from the decoder 97. An AND gate 911 is enabled by the setting of the flip-flops 96 and 99 after the relay characteristics have been shifted into the shift register 93. The output signal from the AND gate 911 loads four counters 912-915. The counter 912 is a variable counter which depends on the most significant four bits of the relay characteristics in the shift register 93. The counter 912 operates in conjunction with a fixed counter 913 which produces an output signal at the completion of the fixed plus variable count. The output signal from the counters 912 and 913 is inverted by an inverter 916 to produce an enabling signal to the decoder 97 via the OR gate 98. The counters 912 and 913 determine the closure time of the relay being activated.
The counter 914 is a variable counter whose interval depends on the least significant four bits in the shift register 93 and the counter 914 operates in conjunction with the fixed interval counter 915. The output signal from the counter 915 is inverted by an inverter 917.
The counters 912 and 913 are enabled by the output signal from the inverter 916 and the counters 914 and 915 are enabled by the output signal from the inverter 917. Enabling the counters by the inverter output signals prevents the counters from over-running, i.e., once an output signal is produced, the counters are stopped until they are reset. The output signal from the inverter 916 provides a signal to the OR gate 98 to enable the encoder 97 and thus activate the selected relay until the counters 912 and 913 have completed their count. At the end of their count, the output signals from the inverter 916 disables the decoder by removing the enabling signal from the OR gate 98. This causes the relays to open.
The counters 914 and 915 continue to count until the end of the desired period at which time the output signal from the counter 915 primes the ready flip-flop 99. As previously described, the set output signal from the flip-flop 96 causes the computer to go to the machine state 11 to transmit the next relay number and its associated characteristics.
Clock signals to the counters 912-915 in FIG. 9 and to counters 553 and 560 in FIG. 5b are provided by a resettable clock 918. The clock circuit 918 can be synchronized with the output from the oscillator 510 and can be reset by the output signal from the AND gate 911. The reset signal can be used to control a flip-flop which inhibits the output from the clock circuit 918 and the clock circuit can be a count down counter which divides the frequency of the oscillator 510 by some suitable integer to produce the desired clock width as described above.
The fixed interval counters 913 and 915 are coupled to reference voltages to set the desired fixed interval. The interval for various relays may be changed by appropriate gating at the input to the fixed counters 913 and 915. For example, the values loaded in the counters 913 and 915 are different when the F relay is activated from those when the remaining relays are activated by coupling the output signal from an inverter 919 to the most significant bit of each of the counters 913 and 915.
Two of the relays in the relay bank 10 of FIG. 1 are illustrated in FIG. 10. The appropriate output signal from the encoder 97 is coupled to a driver circuit 101 or 102. The driver circuits provide the required current to operate the relay. Each relay has a set of normally opened contacts 103 which provide the output signals from the relay bank. A second set of transfer contacts 104 is provided to furnish the return signals to the computer, more specifically, to the NAND gates 555 and 556 in FIG. 5b.
FIG. 6 is an illustration of the timing signals at various points in the logic described above. FIG. 6a is the output signal from the oscillator 510 and FIG. 6b is the complemented signal from the inverter 511. FIG. 6c is the output signal from the AND gate 597 during the appropriate machine states. FIG. 6d is the timing signal BT1 from the decoder 516. FIG. 6e is the output signal from the OR gate 595. FIG. 6f shows the relationship of the signal BT0 from the output of the decoder 516. FIG. 6g represents the output signal from the AND gate 594 during the appropriate machine states.
The details of the data store 506 of FIG. 5b are shown in FIG. 7. The input lines from the counters 560 and 553 are coupled to the D input terminals of a plurality of flip-flops, such as a typical flip-flop 71. A Write signal from the AND gate 562 is coupled to a plurality of AND gates such as an AND gate 72, which produces a signal that clocks the D flip-flop 71. The other input to the AND gate 72 is a word line output signal from the address decoder 543. Each row of storage flip-flops in the data store is controlled by a separate word line. Each column is controlled by a separate input line and produces a separate output signal. Only one word line is activated at a time and determines the row in which the input data are stored or from which the data are read. The read signal from the AND gate 591 is coupled to a plurality of AND gates such as an AND gate 73. The other input to the read AND gates are the word line for the corresponding rows. The output signal of the AND gate 73 enables a second plurality of AND gates such as an AND gate 74 which produces a signal on the output line depending on the data stored in the corresponding flip-flop.
The output lines from the data store 506 (FIG. 5b) are coupled to an arithmetic unit 508 which is shown in more detail in FIG. 8. The most significant four bits from the data store 506 represent the pull-in time count and are gated directly to the most significant four output signal lines of the arithmetic unit 508. The least significant four bits represent the drop-out time and are coupled to a plurality of subtracter circuits such as a subtracter 81. The other input signal to the subtracter is the corresponding bit of the pull-in count value so that the output bits from the subtracter circuits represent the difference of the pull-in count minus the drop-out count. To insure a positive result, a bit value having a binary weight of 2 3 is added to the pull-in time by means of an adder 82. The adder 82 is similar to the subtracter 81 except that the inverter 83 is omitted. The input signals to the adder 82 are the most significant bit of the pull-in count and a signal representing a constant binary one. The subtracter 81 is cascaded with the subtracter 84 which in turn is cascaded to the subtracter 85. The subtracter 85 is cascaded with the subtracter 86 which is cascaded with the subtracter 87. The subtracter 86 receives the binary bit with the weight of 2 3 from the pull-in counter to which one is added by the adder 82. The adder 82 furnishes a carry signal to the subtracter 87 to provide an overflow indication. The output signal from the subtracter 87 is not used in the embodiment of the invention described in FIG. 5a but can be used to test for an illegal condition, i.e., the drop-out count is greater than the pull-in count plus eight.
The embodiment described shows how the operating characteristics of a plurality of relays can be determined and stored as electrical signals and used to control the closure time of the relays to a desired degree of accuracy. It has been shown how the closure time can be changed for each relay and how error checks can be made for certain out-of-limit characteristics. Various modifications to the system and circuits described and illustrated to explain the concepts and modes of practicing the invention might be made by those of ordinary skill in the art within the principles and scope of the invention as expressed in the appended claims.