Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to controlling the harmonic content of musical sounds generated by a computor organ in response to the magnitude of the amplitude envelope of that sound, and also relates to controlling the sound loudness as a function of the fundamental frequency of the note being generated.
2. Related Applications
This application is related to the inventor's copending U.S. application, Ser. No. 225,883 filed Feb. 14, 1972, entitled COMPUTOR ORGAN, now U.S. Pat. No. 3,809,786.
3. Description of the Prior Art
Both listening tests and analysis of orchestral instruments have established that a desirable musical tonal quality is obtained by increasing the harmonic content as the magnitude of the amplitude envelope is increased, and by decreasing the harmonic content as the envelope amplitude is decreased. Such modulation of the harmonic content also is advantageous for generation of unusual synthesized tones.
FIG. 1 shows an amplitude envelope 10 typical of a synthesized musical tone. During the initial portion 11 of the attack, the amplitude increases from zero(at time T 0 )to a maximum amplitude at time T 1 . Thereafter, during the time period T 1 through T 2 the envelope amplitude 12 decreases to a "sustain" value 13 which is maintained until the beginning of the decay at time T 3 . In a keyboard instrument, this decay 14 begins when the key is released and ends at time T 4 when the envelope amplitude drops to zero.
In accordance with the present invention, the harmonic content of the generated tone is proportional to the amplitude of the envelope 10. By way of example, the left hand ordinant of FIG. 1 shows a relative amplitude scale ranging from 0 to 127. The right hand ordinant indicates the maximum number of harmonic components contained in the generated tone for each corresponding envelope amplitude. In the example, these range from a single Fourier component when the envelope amplitude is less than 7, to a maximum harmonic content of 16 Fourier components when the envelope amplitude is between 120 and 127. A principal object of the present invention is to provide means for implementing such harmonic modulation in a computer organ.
Another object of the present invention is to provide loudness scaling to compensate for the unequal sensitivity of the ear to sound intensities at different audible frequencies. It is well known that human hearing is less sensitive at low frequencies than at high frequencies. In particular, the response of the ear is about 20 db to 30 db less sensitive at frequencies of about 60 Hz (near the note C 3 ) that it is at frequencies of about 1,000 Hz (near the note C 5 ).
To overcome this frequency dependent average hearing loss, pipe organs and the better electronic organs provide sounds of scaled intensity so that the listener perceives substantially constant loudness throughout the entire musical scale. In pipe organs, such amplitude regulation is accomplished by adjusting the air flow to each individual pipe until the listener senses the same relative loudness. In electronic organs which use individual oscillators to generate the different notes, amplitude scaling is obtained by adjustment of each oscillator output level. An alternative technique is to use a bass-boost filter in the audio signal line from the electronic organ to its associated power amplifier. Typically, such a bass-boost filter will amplify the note C 2 by about 20 to 30 db, and will be scaled to have approximately unity gain for all notes above about E 3 .
A problem associated with the bass-boost filter technique is that of unequal harmonic accentuation. For example, if the note C 2 is played, the fundamental may be accentuated by 20 to 30 db, while the second harmonic will be accentuated by only 10 db and the third harmonic will remain substantially unaltered in amplitude. Thus the tonal quality of the note C 2 will be distinctly different from that of C 3 or of any note higher than C 2 . Moreover, the very prominent boost of the fundamental with respect to the harmonic overtones results in an undesirable "boomy" effect for the low notes, and particularly for the pedal tones.
Thus another object of the present invention is to provide a means for scaling the loudness of tones generated by a computor organ without affecting the relative harmonic content thereof. This permits generation of tones having the same apparent loudness and similar tonal quality throughout the entire musical range.
SUMMARY OF THE INVENTION
These and other objectives are achieved in a COMPUTER ORGAN of the type described in the above-mentioned patent U.S. Pat. No. 3,809,768. In such an instrument, musical notes are produced by computing in real time the amplitudes X o (qR) at successive sample points qR of a musical waveshape, and converting these amplitudes to notes as the computations are carried out. Each sample point amplitude is computed during a regular time interval t x according to the relationship: ##EQU1## where q is an integer incremented each time interval t x , the value n=1, 2,3. . . W represents the order of the Fourier component being evaluated, and C n is a coefficient establishing the relative amplitude of the n th component. The period of the computed wave-shape, and hence the fundamental frequency of the generated note, is established by a frequency number R selected by the instrument keyboard switches.
The amplitude of the envelope 10 (FIG. 1) of the generated tone is established by the scale factor S(t) which is time dependent. In the embodiments described herein, the scale factors S(t) are supplied from attack and decay scale factor memories that are appropriately accessed during the attack and decay periods of each generated note.
In accordance with the present invention, the harmonic content of each generated tone is modulated in response to the envelope amplitude. Specifically, the number of Fourier components included in each waveshape sample point amplitude computation is proportional to the scale factor S(t) value that establishes the envelope amplitude at the time the sample point amplitude X o (qR) is evaluated. Appropriate circuitry is used to obtain a value n max that is fractionally proportional to S(t), and which establishes the highest order Fourier component included in the waveshape amplitude computation. In this manner, the generated tone will include only Fourier components of order less than or equal to n max . Harmonic modulation is achieved. When the envelope amplitude is low, only low order Fourier components are present in the spectrum of the generated note. When the envelope amplitude is greater, more Fourier components are present.
In an illustrative embodiment, the highest order Fourier component is given by: ##EQU2## where k is a constant and the brackets indicate that n max is to have the value of the integer next larger than the quotient. By way of example, wherein the value S(t) can range from 0 to 127, and where k=8, the value n max will range between 0 and 16. This corresponds to the illustration of FIG. 1. If S(t)=83, the quotient within the brackets will be 10.375, so that the highest order Fourier component included in the amplitude computation will be n max = 11. Of course, the invention is not limited either to the specific numerical examples just given, or even to the implementation of equation 2. Other relationships between envelope amplitude and maximum Fourier component order may be employed.
To obtain equal apparent loudness for all generated notes, the present invention employs fundamental-frequency-dependent amplitude scaling circuitry. The octave or half-octave of the selected note is ascertained from the accessed frequency number R. The computed sample point amplitude X o (qR) then is scaled by an amount established by the relative sensitivity of the human ear to the fundamental frequency of the generated note.
For example, if the selected note is C 2 , The computed waveshape sample point amplitude may be multiplied by 8, to achieve a boost of 18 db. This readily can be achieved by left-shifting the value X o (qR) by three bit positions in a shift register. Alternatively, the individual harmonic components C n may be scaled appropriately by an amount dependent on the octave or half-octave containing the note being generated.
BRIEF DESCRIPTION OF THE DRAWINGS
A detailed description of the invention will be made with reference to the accompanying drawings, wherein like numerals designate corresponding parts in the several figures.
FIG. 1 is a graph showing a typical amplitude envelope of a musical tone. The ordinate scales indicate harmonic content as a function of envelope amplitude in accordance with the present invention.
FIG. 2 is a graph like FIG. 1 but showing a different form of amplitude envelope.
FIG. 3 is an electrical block diagram of a computor organ incorporating both harmonic modulation and voice scaling in accordance with the present invention.
FIG. 4 is an electrical schematic diagram showing illustrative circuitry for limiting the number of Fourier components included in each waveshape amplitude computation as a functional of envelope amplitude.
FIG. 5 is an electrical schematic diagram of circuitry for obtaining the attack, sustain and decay scale factors S(t).
FIG. 6 is an electrical schematic diagram of circuitry for achieving loudness scaling as a function of the fundamental frequency of the note being generated.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following detailed description is of the best presently contemplated modes of carrying out the invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention since the scope of the invention best is defined by the appended claims.
Operational characteristics attributed to forms of the invention first described also shall be attributed to form later described, unless such characteristics obviously are inapplicable or unless specific exception is made.
Harmonic modulation and voice scaling both are incorporated in the computor organ 20 of FIG. 3. Each time one of the keyboard switches 21 is depressed, the instrument 20 produces a corresponding note via a sound system 22. The amplitude envelope of the produced sound is established by a set of scale factors S(t) supplied via an OR gate 23 to a line 24. During the attack and sustain periods, the values S(t) are accessed from a scale factor memory 25 controlled by appropriate attack/decay control logic 26 shown in detail in FIG. 5. During the decay period, which begins when the keyboard switch 21 is released, the scale factors S(t) are accessed from a decay scale factor memory 27.
During note production, the constituent Fourier components are calculated individually as described below. The maximum number n max of such components included in each waveshape amplitude computation is established by a divider circuit 30, an illustrative embodiment of which is detailed in FIG. 4. The circuit 30 receives the current scale factor value S(t) from the line 24 and performs the calculation of equation 2. The output of the circuit 30, on a line 31, is a signal designating the value n max . A comparator 32 compares the order n of the Fourier component presently being evaluated with the highest order specified by the signal on the line 31. If n > n max , the comparator 32 provides an inhibit signal on line 33 which prevents this Fourier component from being included in the amplitude computation. In this manner, the generated tone will include only Fourier components having an order less than or equal to n max . That is, the harmonic content of the generated tone will be fractionally proportional to the envelope amplitude.
In the instrument 20, successive waveshape sample point amplitudes X o (qR) are computed in real time in accordance with equation 1. The fundamental frequency of the generated tone is established by a frequency number R accessed from a frequency number memory 35 (FIG. 3) in response to selection of a keyboard switch 21. The frequency number designates both the note and the octave of the selected tone. Appropriate loudness scaling logic 36, described in detail in conjuction with FIG. 6, establishes a loudness scale factor L(R) that is proportional to the relative response of the human ear to the frequency of the selected note. Each calculated sample point amplitude X o (qR) is multiplied by the loudness scale factor in a multiplier 37 prior to reproduction by the sound system 22. Alternatively, each harmonic coefficient C n may be multiplied by the loudness scale factor in a scaler 38 shown in phantom in FIG. 6. In either case, the result is that all notes produced by the instrument 10 will have equal apparent loudness.
In the computor organ 20 (FIG. 3) the individual Fourier components F (n) are individually evaluated during successive calculation time intervals t cpl through t cp16 . At each such interval the corresponding value n is present on a line 40. A clock 41 supplies pulses at intervals t cp to a counter 42 of modulo W. The contents of the counter 42 designates the order n and provides the signals on the line 40. A computation interval t x timing pulse is provided on a line 43 by slightly delaying the counter 42 reset pulse (which occurs at time t cp16 ) in a delay circuit 44.
The Fourier components are summed in an accumulator 45. Thus at the end of each computation time interval t x the contents of the accumulator 45 represents the waveshape amplitude X o (qR) for the current sample point qR. Occurrence of the t x pulse transfers the contents of the accumulator 45 via the multiplier 37 and a gate 46 to a digital-to-analog converter 47. The accumulator 45 then is cleared in preparation for summing of the Fourier components associated with the next sample point, computation of which begins immediately.
The digital-to-analog converter 47 supplies to the sound system 22 a voltage corresponding to the waveshape amplitude just computed. Since these computations are carried out in real time, the analog voltage supplied from the converter 47 comprises a musical waveshape having a fundamental frequency established by the frequency number R then being supplied from the memory 35 via a line 48.
At the beginning of each computation interval t x , the frequency number R, provided via a gate 49, is added to the previous contents of a note interval adder 50. Thus the contents of the adder 50, supplied via a line 51, represents the value (qR) designating the waveshape sample point currently being evaluated. Preferably the note interval adder 50 is of modulo 2W, where W is the highest order Fourier component evaluated by the instrument 20. Each calculation timing pulse t cp is supplied via a line 52 to a gate 53. This gate 53 provides the value qR to a harmonic interval adder 54 which is cleared at the end of each amplitude computation interval t x . Thus the contents of the harmonic interval adder 54 is incremented by the value (qR) at each calculation interval t cp1 through t cp16 , so that the contents of the adder 54 represents the quantity (nqR). This value is available on a line 55.
An address decoder 56 accesses from a sinusoid table 57 the value sinπ/WnqR corresponding to the argument nqR received via the line 55. The sinusoid table 57 may comprise a read only memory storing values of sinπ/W φ for 0 ≤ φ ≤ W/2 at intervals of D, where D is called the resolution constant of the memory. With this arrangement, the value sinπ/WqR will be supplied on a line 58 during the first calculation interval t cp1 . During the next interval t cp2 , the value sinπ/W2qR will be present on the line 58. Thus in general, the value sinπ/WnqR will be provided from the sinusoid table 57 for the particular n th order component specified by the contents of the counter 42.
A set of harmonic coefficients C n is stored in a harmonic coefficient memory 60. As each sinusoid value is supplied on the line 58, the harmonic coefficient C n for the corresponding n th order component is accessed from the memory 60 by a memory address control circuit 61 which receives the value n from the line 40. The accessed value C n is supplied via a line 63 to a harmonic coefficient scaler 64 where it is multiplied by the value S(t) present on the line 24. The product S(t)C n , provided via a line 65, is multiplied by the value sinπ/WnqR on the line 58 in a harmonic amplitude multiplier 66. The output of the multiplier 66, corresponding to the value: ##EQU3## of the Fourier component presently being evaluated, is supplied via a line 67 to the accumulator 45. In this manner, consecutive sets of Fourier components are evaluated during consecutive computation intervals t x . Accumulation of these components, and conversion to an analog waveshape by the converter 47 results in the desired tone production.
Shown in FIG. 4 is illustrative circuitry for modulating the harmonic content of the generated tone as a function of envelope amplitude. In this embodiment, the amplitude scale factors S(t) are provided on the line 24 in the form of 7-bit binary numbers corresponding to a relative amplitude scale having a range from 0 to 127. Individual bits of each binary scale factor are provided in parallel on the lines 24-1 (most significant bit) through 24-7 (least significant bit).
In the circuit 30, each scale factor S(t) is divided by the constant k=8. This is accomplished merely by dropping the three least significant bits contained on the lines 24-5 through 24-7. This is equivalent to performing a right-shift of three bit positions to accomplish division by 2 3 =8. The signal on the lines 24-1 through 24-4 then represents the quantity S(t)/8. An adder circuit 70 adds one (i.e., binary 0001) to this quantity. As a result, the 4-bit binary signal present on the output 31 (consisting of the bit-lines 31-1 through 31-4) represents the quantity n max given by equation 2 above, for k=8.
By way of example, if S(t)=83, the lines 24-1 through 24-7 will contain the binary value 1010011. Thus the output lines 31-1 through 31-4 will contain the binary value 1011 corresponding to decimal 11. In other words, with a signal of relative amplitude 83, the highest order Fourier component to be included in the amplitude computation is n max =11.
As noted above, the order n of the Fourier component presently being evaluated is established by the counter 42. Advantageously this counter is of modulo W=16 and may be implemented using a standard integrated circuit such as the Signetics type SIG 8281 16-state binary counter. The counter 42 provides a 4-bit binary output on the line 40-1 through 40-4 which designates the order n of the Fourier component presently being evaluated.
The comparator 32 likewise may comprise a conventional integrated circuit such as the Signetics type SIG 8269. This circuit compares the inputs on the lines 31 and 40 and provides an inhibit signal on the line 33 when n > n max . The scale factors S(t) on the line 24 are provided to the circuit 30 via a switch 69 when that switch is set to the position 69a.
In an alternative embodiment, operative when the switch 69 is set to the position 69b, the circuit 30 may be replaced by a memory 68 (FIG.4) which stores values of n max . A memory access decoder 68a receives the current scale factor S(t) from the line 24 and accesses from the memorry 68 the corresponding value n max . The stored n max values are a design choice, but could be those shown along the right ordinate of FIG. 1 for corresponding relative amplitudes given on the left ordinate. The memory 68 and its associated decoder may be implemented using a conventional read-only memory such as the Signetics type SIG 8223.
The harmonic coefficient memory 60 and its associated memory access control 61 together may be implemented using a conventional integrated circuit read only memory such as the Signetic type SIG 8223. This circuit includes a storage array which may be user programmed to contain a desired set of harmonic coefficients C n . For example, the stored values may correspond to those set forth in Table I below for a diapason voice.
TABLE ______________________________________ DIAPASON Coefficient (Relative (Decibel Amplitude) Equivalent) ______________________________________ C 1 127 0 db C 2 71 -5 C 3 90 -3 C 4 36 -11 C 5 23 -15 C 6 25 -14 C 7 8 -24 C 8 8 -24 C 9 4 -31 C 10 4 -31 C 11 2 -38 C 12 2 -38 C 13 2 -38 C 14 1 -42 C 15 1 -42 C 16 1 -42 ______________________________________
The same integrated circuit includes access control circuitry which accepts binary address information. Thus, the binary signal on the line 40 may be provided directly to this control circuit 61 to cause access from the memory 60 of the harmonic coefficient C n corresponding to the value of n present on the line 40. Further, the same integrated circuit includes an inhibit or "chip enable" input. The comparator output line 33 is connected to this input. As a result, whenever n > n max , readout from the harmonic coefficient memory 60 is inhibited, and no C n output is provided to the line 63. As a result, the output of the harmonic coefficient scaler 64 is 0. Thus the higher order Fourier components are eliminated from the amplitude computation, exactly as desired.
Although not illustrated, the inhibit signal on the line 33 could be used to inhibit a gate in the line 63, and in this manner prevent the value C n from being supplied to the scaler 64. The scaler 64 itself may comprise a conventional multiplier circuit, or may be implemented using a standard integrated circuit scaler such as the Signetics type SIG 8243.
FIG. 5 shows illustrative circuitry for providing envelope amplitude scale factors S(t) during the attack, sustain and decay periods of note production. In this embodiment, the lengths of the attack and decay periods correspond to a fixed number of cycles of the note being generated. For example, the duration (T 1 -T 0 ) of the initial attack 11 (FIG. 1) may correspond to 16 quarter-cycles of the fundamental frequency of the generated note. Similarly, the attack portion 12 may have a time duration (T 2 -T 1 ) for 48 quarter cycles, and the decay 14 may have a time duration (T 4 -T 3 ) of 32 quarter-cycles.
In the embodiment of FIG. 5, the attack and decay durations are established in conjunction with the note interval adder 50. This adder 50, of modulo 2W, resets at the beginning of each cycle of the note being generated. For example, if the computor organ 20 is configured to evaluate up to W=16 Fourier components, sufficient for accurate synthesis of most pipe organ tones, the adder 52 will reset each time its contents just exceeds 2W=32. Thus a signal obtained on a line 72 each time the adder 50 resets (upon reaching a count of 32) will indicate the start of a new cycle of the generated tone.
Similarly, an output on a line 73, obtained when the adder 50 reaches a count of 16, will indicate completion of the first half of each cycle. The lines 72 and 73 are connected to an OR-gate 74 to provide on a line 75 a signal which occurs each one-half cycle of the generated tone. Similarly, a signal that occurs each quarter cycle of the generated note is obtained on a line 76 by combining via an OR gate 77 signals obtained each time that the adder 50 reaches a count of 8, 16, 24 or 32.
The following tables II and III are helpful in understanding the manner in which the adder 50 operates to identify the current waveshape sample point (gR) and to reset at the end of each cycle of the generated tone. Thus Table II lists typical values of the frequency numbers R stored in the memory 35. Each frequency number R is directly proportional to the fundamental frequency of the associated note, and inversely proportional to the number of sample points at which the generated waveshape amplitude X o (qR) is evaluated during each cycle of the generated tone.
TABLE II ______________________________________ NOTE FREQUENCY R Number of Sample (Hz) Points per Cycle ______________________________________ C 7 2093.00 1.0000 32.00 B 6 1975.53 0.9443 33.90 A 6 1864.66 0.8913 35.92 A 6 1760.00 0.8412 38.06 G 6 1661.22 0.7940 40.32 G 6 1567.98 0.7494 42.72 F 6 1479.98 0.7073 45.26 F 6 1396.91 0.6676 47.95 E 6 1318.51 0.6301 50.80 D 6 1244.51 0.5947 53.82 D 6 1174.66 0.5613 57.02 C 6 1108.73 0.5298 60.41 C 6 1046.50 0.5000 64.00 ______________________________________ Table III lists the contents (qR) of the note interval adder 50 at successive computation intervals t x during production of three different notes. For example, during generation of the note C 7 , the adder 50 is incremented by the amount R=1.0000 at each computation interval t x . Thus exactly 32 such intervals are required for production of the note. Quarter-cycle pulses will occur on the line 76 (FIG. 5) at the intervals t x =8, 16, 24 and 32.
Similarly, during production of the note G 6 the adder 50 will be incremented by the value R=0.7494 at each computation interval. Slightly more than 42 such intervals t x are required for generation of one cycle at the fundamental frequency of this note. Thus, quarter-cycle signals will be present on the line 76 at computation intervals t x =11, 22, 33 and 43.
During attack and decay, the scale factors S(t) may be updated each full, half, or quarter cycle of the note being generated. This selection is made by means of a switch 78 (FIG. 5) which connects the corresponding line 72, 75 or 76 to a scale factor timing line 79.
During the attack and sustain periods, the scale factors S(t) are provided from the memory 25. In the embodiment of FIG. 5, this memory 25 contains a plurality of storage locations 25-1 through 25-p each of which contains a separate value S(t). During the initial attack portions 11 and 12 (FIG. 1), these stored scale factors are accessed successively under the control of a parallel load shift register 81 having a corresponding plurality of positions 81-1 through 81-p. Only one of these positions contains a binary 1 bit. The storage location in the memory 25 corresponding to the register position containing that 1 bit provides the scale factor S(t) to a line 82 and thence via an enabled AND gate 83 and the OR gate 23 to the line 24.
TABLE III ______________________________________ COMPUTATION qR INTERVAl t x A 6 G 6 C 7 ______________________________________ 1 0.8913 0.7497 1.0000 2 1.7826 1.4988 2.0000 3 2.6739 2.2482 3 4 3.5652 2.9976 4 5 4.4565 3.7470 5 6 5.3478 4.4964 6 -- -- -- -- 11 9.8043 8.2434 11 -- -- -- -- 22 19.6086 16.4868 22 -- -- -- -- 31 27.6303 23.2314 31.0000 32 28.5216 23.9808 0.0000 33 29.4129 24.7302 1.0000 34 30.3042 25.4796 2 35 31.1955 26.2290 3 36 0.0868 26.9784 4 37 0.9781 27.7278 5 38 1.8694 28.4772 6 39 2.7607 29.2266 7 40 3.6520 29.9760 8 41 4.5433 30.7254 9 42 5.4346 31.4748 10 43 6.3259 0.2242 11 44 7.2172 0.9736 12 45 8.1085 1.7230 13.0000 ______________________________________
Such readout of the attack-sustain scale factor memory 25 is initiated each time that a keyboard switch 21 is closed. For example, if the note C 7 is selected by closing the corresponding switch 84, a signal is supplied via a line 85 and an OR gate 86 to a one-shot multivibrator 87. This produces a "key depressed" pulse on a line 88 which initiates readout of the memory 25.
Specifically, the "key depressed" pulse is provided to the "load" input of the shift register 81 to cause entry of a binary 1 bit into the position 81-1, and to cause binary 0 bits to be entered into all other positions of the register 81. The "key depressed" pulse also sets a flip-flop 89 to the 1 state so as to enable an AND gate 90. Accordingly, the quarter, half or full cycle pulses on the line 79 are fed via the AND gate 90 to the "shift" input of the register 81. As a result, the single binary 1 bit contained in that register is advanced from location to location as each pulse occurs on the line 79. Successive scale factors S(t) thus are accessed from the memory 25 at a rate proportional to generation of successive cycles of the selected note.
Advantageously, the memory positions 21-1 through 21-i contain scale factors S(t) appropriate for generating the attack section 11 (FIG. 1) of the amplitude envelope 10. The positions 25-(i+) through 25-p contain the necessary scale factors for producing the attack portion 12 of decreasing amplitude. The end of the attack, corresponding to the time T 2 in FIG. 1, occurs when the single 1 bit in the register 81 reaches the position 81-p. At that time, a signal is provided via a line 92 to the reset (R) input of the flip-flop 89. This resets the flip-flop 89 to the 0 state, thereby disabling the AND gate 90 so that no more shift pulses are provided to the register 81.
The final attack scale factor S(t) contained in the memory location 25-p continues to be supplied via the line 24 until the selected keyboard switch 21 is released. That is, the scale factor in the storage location 25-p establishes the amplitude of the envelope 10 (FIG. 1) during the sustain period 13.
An alternative amplitude envelope configuration 10' is shown in FIG. 2. Here the attack has only an increasing amplitude portion 11' ending at a time T 1 '. The sustain begins immediately with an amplitude equal to the final, maximum amplitude achieved during the attack. The decay 14' begins at the time T 3 ' when the keyboard switch is released. Harmonic modulation, achieved in accordance with the present invention, with an amplitude envelope like that of FIG. 2 may be called "incomplete" as compared with the "complete" harmonic modulation employing an amplitude envelope like that of FIG. 1.
Incomplete harmonic modulation also is implemented by the control logic 26 of FIG. 5, by transferring a switch 93a, 93b from the C or complete position to the I or incomplete position. When this is done, accessing of the attack-sustain scale factor memory 25 terminates when the single 1 bit in the register 81 reaches the position 81-i. At that time, a signal is supplied via a line 94 and the switch 93a to the reset input of the flip-flop 89. As a result, the AND gate 90 is disabled so that shifting of the register 81 is terminated. The maximum amplitude scale factor stored in the memory location 25-i continues to be supplied to the line 24 during the sustain period 13' (FIG. 2).
Decay begins when the selected keyboard switch 21 is released. To facilitate continued tone production during the decay period, the frequency number memory 35 is accessed in response to a set of flip-flop 96 each associated with a corresponding keyboard switch 21. Thus the switches 84, 97 and 98, for the notes C 7 , D 1 and C 1 , are connected to the set (S) inputs of respective flip-flops 96-1, 96-q and 96-r.
Thus e.g., when the switch 84 is closed, the flip-flop 96-1 is set, and a signal is provided via a line 99 to cause access from the memory 35 of the frequency number R associated with the note C 7 . When the keyboard switch 84 is released, the flip-flop 96-1 is not immediately reset. As a result, the signal on the line 99 remains high so that the selected frequency number continues to be accessed from the memory 35 during the decay period. However, opening of the switch 84 causes the output of the OR gate 86 to go low. As a result, an inverter 101 provides a high output that triggers a one-shot multivibrator 102. This in turn produces a "start of decay" signal on a line 103. This signal causes amplitude scale factors S(t) to be supplied to the line 24 from the decay scale factor memory 27.
To this end, the start of decay signal sets a flip-flop 104 to the 1 state. This disables the AND gate 83 to prevent scale factors from the memory 25 from reaching the line 24. The 1 output from the flip-flop 104 is supplied via a line 105 to enable an AND gate 106 to open a path for scale factors S(t) from the decay scale factor memory 27 via a line 107 and the OR gate 23 to the line 24.
The start of decay signal on the line 103 also is fed to the load input of a parallel load shift register 108 that is used to access the decay scale factor memory 27. Like the register 81, the shift register 108 includes a plurality of locations 108-1 through 108-k corresponding respectively to the storage locations 27-1 through 27-k in the memory 27.
At the start of decay, a single binary 1 bit is loaded into the shift register 108 via a line 109 and the switch 93b. For complete harmonic modulation (FIG. 1), the 1 bit is loaded into the position 108-j. In this instance, the memory storage position 27-j preferably contains a scale factor S(t) having a value equal to or very close to that stored in the attack-sustain scale factor memory position 25-i. For incomplete harmonic modulation like that of FIG. 2, the 1 bit is loaded into register position 108-1. Preferably the scale factor contained in the corresponding memory position 27-1 is equal to or very near the value stored in the attack-sustain memory position 26-p. The 1 output from the flip-flop 104 also enables an AND gate 110 which feeds the quarter, half or whole cycle pulses from the line 79 to the shift input of the register 108. Accordingly, decay scale factors S(t) are successively accessed from the memory 27 as the single 1 bit is shifted through the register 108. This results in decreasing amplitude of the generated tone, along the decay curve 14 (FIG. 1) or 14' (FIG. 2).
In either case, the decay ends when the single 1 bit reaches the final location 108-k. At this time, a end of decay signal occurs on a line 111. This signal resets all of the flip-flops 96, to terminate access of the selected frequency number from the memory 35, and hence to terminate note production. Further, the end of decay signal resets the flip-flop 104 to the 0 state. This disables the AND gate 106 and enables the AND gate 83. This insures that attack scale factors from the memory 25 will be supplied to the line 24 when the next keyboard switch 21 is depressed.
Illustrative amplitude scale factors S(t) for complete and incomplete attack and for decay are listed in Table IV below.
TABLE IV ______________________________________ Quarter S(t) Cycle of ATTACK DECAY Generated Relative Decibel Relative Decibel Tone Amplitude Equivalent Amplitude Equivalent Complete Attack ______________________________________ 1 0.0031 -50 0.5007 -6 2 0.0997 --20 0.3976 -8 3 0.2234 -13 0.3157 -10 4 1.0000 0 0.1255 -18 5 0.8911 -1 0.0560 -25 6 0.7941 -2 0.0223 -33 7 0.7076 -3 0.0031 -50 8 0.6305 -4 9 0.5619 -5 10 0.5007 -6 11 0.5007 -6 12 0.5007 -6 Incomplete Attack 1 0.0031 -50 2 0.0997 -20 3 0.2234 -13 4 0.5007 -6 ______________________________________
FIG. 6 shows illustrative circuitry for controlling the loudness of the generated musical tones to compensate for decreasing sensitivity of the human ear at low frequencies. In this embodiment, the loudness may be increased in steps of 6 db for each half-octave below the note F 3 . Each increase of 3 db doubles the loudness.
To this end, the loudness scaling logic 36 includes a memory 115 that stores a set of loudness scale factors L(R) which establish the relative increase in loudness for the generated note. Typically, these loudness scale factors L(R) may have the values listed below in Table V.
TABLE V ______________________________________ Frequency Octave L(R) Increase in Note Number (R) Code Loudness ______________________________________ C 2 .03125 010 0 8 18 db F 2 .0417 E 2 .0442 010 1 4 12 db B 2 .0590 C 3 .0625 100 0 2 6 db F 3 .0834 F 3 .0884 100 1 0 0 db C 7 1.0000 ______________________________________
In the foregoing table, the scale factors L(R) are listed in decimal value for each corresponding half octave. For example, the scale factor L(R) for the lower half of the second octave (containing the notes C 2 through F 2 ) has the decimal value 8. Each computed waveshape sample point amplitude X o (qR) provided on a line 116 from the accumulator 45 is multiplied by this value L(R) in the multiplier 37. The augmented amplitude value L(R)X o (qR) is provided from the multiplier 37 via the gate 46 to the digital to analog converter 47. As a result, the tone produced by the sound system 22 will be increased in amplitude by 18 db.
Scale factors L(R) are supplied to the multiplier 37 via a switch 114 set to position 114a and a line 117 from the memory 115. This memory is accessed by a control circuit 118 that receives octave information via a line 119 from the frequency number memory 35. Advantageously, the memory 35 stores both the frequency number R and an associated octave code. As indicated in Table V above, the octave code stored in the memory section 35a may be a 4-bit binary number of which the first three bits indicate the octave and the final bit designates the half octave of the selected note. For example, for the note C 2 the octave code 010 0 indicates that the note is contained in the lower half of the second octave.
With the foregoing arrangement, the memory 115 and associated access control 118 together may be implemented using a conventional integrated circuit read only memory such as the Signetics type SIG 8223. The octave-indicating binary code on the line 119 may be supplied directly to the address input of this device. The memory itself may contain appropriate loudness scale factors L(R) such as those listed in Table V.
In a binary implementation, the multiplier 37 simply may comprise a shift register in which the waveshape amplitude X o (qR) is left shifted a number of positions designated by the value L(R). A left shift of one position corresponds to multiplication by two and hence results in an increase in loudness of 6 db. In such implementation, the scale factors L(R) stored in the memory 115 may designate the number of positions that the amplitude X o (qR) is to be left shifted. For example, if an increase in loudness of 18 db is desired, the memory 115 may store a number indicating a left shift of three bit positions, corresponding to multiplication by decimal 8.
As an alternative, operative when the switch 114 is set to the position 114b, the multiplier 37 may be eliminated and the loudness scale factors L(R) used to scale each individual harmonic coefficient C n provided on the line 63. To this end, the scale factors L(R) from the memory 115 are supplied to a scaler 38 (FIG.6) inserted in the line 63. Scaled harmonic coefficients L(R)C n thus are supplied to the harmonic coefficient scaler 64 instead of the stored harmonic coefficient C n itself. The desired loudness augmentation is achieved. The scaler 38 may comprise a conventional multiplier circuit, a binary shift register, or an integrated circuit scaler such as the Signetics type 8243.
As an alternative to storing a separate octave code in the memory 35, the scale factor memory 115 may be accessed in response to the frequency number R itself. To accomplish this, a switch 120 is closed and the accessed frequency number R is supplied via the line 48 to a decoder circuit 121. This decoder 121 ascertains directly from the value R itself the octave or half octave of the selected note. For example, as indicated by Table V above, notes having frequency numbers between 0.03125 and 0.0417 are contained in the lower half of the second octave. The decoder 121 provides corresponding octave information via a line 122 to control 118 which accesses the appropriate loudness scale factor from the memory 115. In this manner, loudness adjustment is achieved to compensate for decreasing response of the human ear to notes of low frequency. The various components of the basic computor organ are conventional circuits well known in the digital computer art. For example, the frequency number memory 35 may comprise an integrated circuit read-only memory such as the Signetics type SIG 8223 or the Texas Instruments type TI SN5488A. The note interval adder 50 and the harmonic interval adder 54 each may comprise an accumulating adder of the type shown in Section 1.11 of the textbook "Computer Logic" by Ivan Flores, Prentice-Hall, 1960. Such adders may be implemented using conventional integrated circuits such as the Signetics type SIG 8260 arithmetic logic element, type SIG 8268 gated full adder or Texas Instruments type TI SN5483 full adder. The sinusoid table 57 and its associated decoder 56 may be implemented using a Texas Instruments integrated circuit type TI TMS4405 sinusoid table and addressing circuitry. The multipliers 37 and 66 may be impleneted as shown on page 28 of the Signetics "Digital 8000 Series TTl/MSI" catalog, copyright 1971, using type SIG 8202 buffer registers and type 8260 arithmetic elements.