05/508723

09/02/1975

09/23/1974

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Polaroid Corporation (Cambridge, MA)

396/244

396/256

G03B7/091; G03B7/08

354/29,50,51,6R,234

Matthews, Samuel S.

Adams Jr., Russell E.

Thornton, David R.

This is a continuation of application Ser. No. 362,664, filed May 22, 1973, now abandoned.

I claim

1. Apparatus for controlling an exposure control mechanism of a variety including a stepper motor unit having a first input for receiving a directional sense signal and a second input for receiving drive pulses to effect movement of said mechanism to provide control of the passage of light through an optical path, comprising:

2. The apparatus of claim 1 in which said drive control means is operative to drive said stepper motor at one pulse frequency in the presence of said first directional sense signal, to detect said exposure control circuit means output signal at a predetermined multiple of said one pulse frequency and respond to said signal detection to drive said stepper motor in the presence of said second directional sense signal.

3. The apparatus of claim 1 in which said drive control means includes:

4. The apparatus of claim 1 in which said synchronizing means includes bistable means initially actuable to commence an exposure control cycle of said apparatus and deriving a select stable output state in coincidence with said initial actuation and the presence of a pulse at said drive frequency for actuating said drive control means in synchronism with said pulse train drive frequency.

5. The apparatus of claim 1 in which said directional control means includes bistable means having a first stable output state providing said first directional sense signal and a second stable output state providing said second directional sense signal.

6. An exposure control system of a variety including an exposure mechanism movable from a first terminal position toward a second terminal position to define progressively varying apertural values over an optical path and subsequently movable into said first position to block said path, the improvement comprising:

7. The exposure control system of claim 6 including:

8. The exposure control system of claim 6 in which said drive control means includes:

9. The exposure control system of claim 8 including delay means responsive to said divider network means derivation of said subsequent energizing pulse train for selectively delaying the presence of said subsequent energizing pulse train at said phase control means.

10. The exposure control system of claim 9 in which:

11. The exposure control system of claim 6 in which:

12. The exposure control system of claim 11 in which said phase control means includes:

13. The exposure control system of claim 12 wherein said directional control means and said exposure cycle identification means respective output conditions R' and G₃ are synchronous to said output, K_a.

14. In an exposure control apparatus of a variety including an exposure mechanism movable in a first direction to uncover an optical path and subsequently movable in a reverse direction to terminate an interval of exposure, the improvement comprising:

15. The exposure control apparatus of claim 14 in which said operational cycle logic means is operative to respond to said exposure evaluation means signal at a time within said terminal pulse interval coinciding with a sampling frequency interval representing a select multiple of said given frequency.

16. The exposure control apparatus of claim 14 in which said operational cycle logic means includes:

17. The exposure control apparatus of claim 16 in which said divider network means is operative to generate said subsequent energizing pulse train in response to said coincidence means detection of said exposure evaluation signal.

18. A photographic exposure control system comprising:

19. The system of claim 18 wherein said driving means includes a stepper motor.

20. A photographic exposure control system for a camera, the camera having means for mounting photographic film material at a given focal plane, a lens for directing image-carrying rays from a scene along a given optical path to the camera focal plane, and selectively operable means for initiating an exposure cycle, said system comprising:

21. The system of claim 20 wherein said blade means is mounted for displacement between said one terminal position and a second terminal position wherein it defines a maximum aperture value, and said system additionally including means, responsive to energization of said motor to displace said blade means to said second terminal position, for terminating the energizing of said motor so as to minimize power consumption when said blade means reaches said second terminal position.

22. The system of claim 20 wherein said means responsive to the location of said blade means in said one terminal position includes switch means configured to be engaged by said blade means when said blade means is in its said one terminal position and providing a first output signal when said blade means is located in said one terminal position and a second output signal when said blade means is located in other than said one terminal position, said means for generating said first predetermined sequence of pulses is responsive to the exposure initiating means in the presence of said first output signal and for generating said second predetermined sequence is responsive to said scene evaluation in the presence of said second output signal.

23. An exposure control system of a variety including an exposure mechanism actuatable in response to an exposure initiation signal and an input pulse train to define changing aperture values unblocking an exposure path to initiate an exposure interval and then actuatable in response to an exposure termination signal to block the exposure path to terminate the exposure interval, and means deriving a time dependent evaluation signal corresponding with an exposure evaluation of a scene, said system comprising:

BACKGROUND

Conventional shutter mechanisms are designed to utilize the advantageous characteristics of springs to derive both the opening and closing movement of shutter blades or the like. Such springs provide both desirable consistency of dynamic performance as well as relatively high output force in consequence of their correspondingly high stored energy characteristics. To operate the shutters, power is required and, in most applications, that power is delivered to the springs by an energy storing cocking procedure through a hand-driven device. Such devices may be present as a crank lever or a strong mechanical linkage connecting a film wind lever with the shutter mechanism. The mechanisms of such cameras are relatively simple inasmuch as the mechanical paths transferring forces are relatively short. Should the shutter use electronic exposure controls, such controls need only perform a function latching cocked elements, a function requiring relatively low power levels.

As the photographic industry sought to design miniature or compact, but fully automated cameras, a need was developed for a shutter device which would remain accurate while operating without the energy otherwise supplied from a hand-loaded spring-driven system. The energy to be supplied to such cameras would be derived from a battery and this battery necessarily is of very limited capacity in consequence of the space limitations of a compact camera. The design of a low power level demand shutter becomes even more complex where the camera is called upon not only to automatically regulate an interval of exposure, but to provide a programmed automatic dual parameter (exposure interval and aperture) control while functioning within the complex photographic cycle required of an automatic single lens reflex form of camera which serves the additional function of providing a self-processing feature following each exposure. The drive or motive power available for the shutter must be generated from an electromagnetically actuated device such as tractive electromagnet or the like, usually operating in conjunction with relatively weak springs. Further, inasmuch as reflex mode conversion is automated, some form of motive means is required to cause the automatic camera to carry out optical mode changes and additionally, to drive an automatic film processing station. As a consequence, in the course of a single photographic cycle, a current consumption or energy consumption profile may be developed which represents a critical power consuming characteristic. Where analog forms of electronic control systems are utilized in conjunction with such power consumption profiles, their sensitivity may be adversely effected. For instance, requisite trigger threshold buildups providing needed delays and the like may be difficult to realize where vagaries in battery output levels are witnessed.

One such compact but fully automated photographic camera incorporating both a single lens reflex operational cycle as well as automatic film processing, is described in U.S. Pat. No. 3,714,874. A photographic cycle of this camera requires that its shutter remain normally open, defining full aperture width for purposes of viewing and focusing. With the commencement of a photographic cycle, the shutter is required to fully close and remain closed while the optical path thereof converts to an exposure mode orientation. Following such conversion, the shutter is required to carry out a two parameter exposure regulation, following which the shutter remains closed as the components thereof are automatically driven to alter the optical path to its initial viewing-focusing mode orientation. While this optical path conversion is carried out, a processing station is motor driven to both remove and process an exposed film unit. When optical path conversion as well as processing is completed, the shutter is called upon to reassume its fully open condition exhibiting maximum aperture width and then to automatically turn off to conserve battery power.

Inasmuch as the above-described automatic camera necessarily utilizes a series of electro-mechanical interfaces between moving components and its control circuitry, its control circuit should be immune from the mechanical inconsistencies normally realized with typical switching operations. Such immunity would permit the cycle of the camera to progress from one operational event to another without the disruptive electrical noise effects encountered with such phenomena as "switch bounce", i.e., multiple closures of the contacts of a mechanical switch resulting from its actuation during a cycle. Such effects are particularly damaging where they are incurred during the light evaluating phase or exposure phase of operation of an automatic photographic cycle.

SUMMARY

The present invention is addressed to a photographic system and apparatus incorporating a pulse logic control system operating in conjunction with a stepper motor driven shutter or exposure mechanism. Through the use of this pulse logic control in concert with a step form of shutter drive, resultant camera control electronics are available which permit an enhanced conservation of the demands made upon a self-contained electrical power supply. The control circuitry is more immune to electrical noise and the like and is less sensitive to variations in power supply output as often may be experienced in the course of normal camera usage.

The invention further features a more discrete control over the operational events constituting both the exposure cycle and full operational cycle of an automatic camera. For instance, the variably timed events constituting an interval of exposure regulation are controlled in conjunction with principal clock pulse frequencies. As a consequence, more precise aperture values are defined and it follows that the anticipation feature required with a dual directional shutter system of a variety deriving dual exposure parameter control is more accurately established. As an example, in one preferred arrangement of the instant inventive system, an anticipatory delay of the consistently definable interval of one predetermined pulse width is provided.

As another aspect and object of the invention, an exposure control system of a variety utilizing a stepper motor driven from a train of energizing pulses is arranged to incorporate a monitor arrangement which responds to the introduction of a given number of these pulses to the motor which corresponds with exposure mechanism or shutter blade movement from one terminal position to another. When the monitor arrangement counts this number of pulses required for terminal movement, a phase control operates to interrupt motor energization, thereby rendering the motor de-energized at a "hold" event during a photographic cycle. This hold event may occur at such time as a maximum aperture width is defined or when a camera optical path is fully blocked to permit the carrying out of other operational cycle events such as optical path conversion or film unit processing. Since the shutter drive motor is inactivated, the energy demand profile for a cycle of the automatic control is suppressed to provide a desired energy conservation.

Another feature of the invention provides a phase control arrangement for energizing a stepper motor driven exposure mechanism which is operative in the presence of the shutter opening directional signal and an initial energizing or clock pulse train to energize the motor to move the exposure mechanism toward an open or terminal position. This phase control arrangement is further operative in response to a reversing directional signal in the presence of a scene evaluating signal as well as to a subsequent energizing or clock pulse train to actuate the motor to move the exposure mechanism into its closed or initial terminal position. Should an exposure interval requiring an interval timing extending beyond the attainment of a maximum aperture width be required, the phase control arrangement is operative to interrupt the energizing clock pulse train when the exposure mechanism reaches an orientation representing a terminal aperture position. However, the energizing pulse train is introduced subsequently in the presence of an exposure evaluating signal to re-energize the motor to move in a reverse direction.

Another object and feature of the invention is to provide a digital technique for detecting the presence of an exposure evaluating signal at a point in time intermediate the commencement and end of a clock pulse signal. Such a feature is provided through a coincidence arrangement in which the output of an exposure evaluating network is sampled at a frequency higher than the clock frequency of the system. Preferably, this sampling frequency is selected as a multiple of the clock frequency. As a consequence, highly accurate aperture definition is provided by the system. Through appropriate gating, the energizing clock pulses utilized in terminating an exposure interval are readjusted in time to accommodate for this vernier detecting or sampling feature of the digital control network. In a preferred arrangement, a basic output pulse generator serves to establish the noted multiple frequency and the energizing pulse train or clock frequencies are derived through a divider network arrangement selectively activated during an exposure cycle in response to the noted detection.

Another feature and object of the invention provides a photographic control system wherein digital logic is utilized to overcome the ambiguities which may be present in consequence of the mechanical actuation of switches within the system. In particular, a bistable multivibrator arrangement responsive to switch actuation is utilized to generate a stable output actuating signal such that any logic information represented by such switch actuation is accepted by the digital circuit in isolation from extraneous switch actuations which might occur in consequence of bounce characteristics or the like.

Another object of the invention is to provide mechanical switch synchronization within the system through the use of a first bistable multivibrator arrangement having an input responsive to initial mechanical actuation of a switch. This first multivibrator arrangement has a unique stable output condition which serves as an actuating signal for introduction into the digital control logic of the circuit. A second bistable multivibrator arrangement responsive to the earlier unique stable output actuating signal as well as to the earlier described clock pulse train serves to introduce the actuating signal to the circuit in synchronism with the clock pulse train. As a consequence, highly predictable performance and accuracy are achieved within the system.

Other objects of the invention will in part be obvious and will in part appear hereinafter.

The invention accordingly comprises the apparatus and system possessing the construction, combination of elements and arrangement of parts which are exemplified by the following detailed disclosure.

For a fuller understanding of the nature and objects of the invention, reference should be had to the following detailed description taken in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a front sectional view of an exposure control mechanism of a photographic camera which may utilize the system and apparatus of the instant invention;

FIG. 2 is another view of the exposure housing of FIG. 1 showing the components thereof as they are oriented during a different portion of a photographic cycle;

FIG. 3 is a partial side sectional view of the exposure housing of FIG. 1;

FIG. 4 is a schematic diagram of a control logic circuit for use with the exposure mechanism of FIG. 1;

FIG. 5 is a pulse diagram illustrating the pulse digital logic of the circuit of FIG. 4;

FIG. 6 is a flow chart elaborating upon the operational logic of the circuit of FIG. 4 as it operates in the exposure phase of a photographic cycle;

FIGS. 7, 7A provide an operational logic chart showing the operation of the circuit of FIG. 4 as it performs in conjunction with the full photographic cycle of a fully automated single lens reflex camera utilizing the exposure mechanism of FIG. 1; and

FIG. 8 is an energization state diagram illustrating features of the cycle described in FIG. 7.

DETAILED DESCRIPTION

Referring to FIG. 1, the general structure of an exposure housing suited for use, for instance, with the compact automatic single lens reflex camera described earlier and with the control logic system of the instant invention is revealed at 10. Housing 10 is formed having a rear casting 12 serving as a principal support for the components therewithin. More particularly, the center and one side portion of rear casting 12 serve to support a compound mounting fixture including an exposure mechanism mounting plate 14 which, in turn, supports a lens mounting bracket 16 at the center of housing 10. Bracket 16 serves to support an externally geared bezel 18 which is rotatable to focus the taking or objective lens 20 of the camera. Focusing movement of lens bezel 18 is provided from a hand-manipulated, externally geared focusing wheel shown in outline form at 22. Focusing wheel 22 is interconnected with the geared periphery of bezel 18 through an idler gear 24.

The rearward portion of lens mounting bracket 16 also serves to support two coacting exposure mechanism or shutter elements or blades 26 and 28. Blades 26 and 28, respectively, are formed having tapered aperture openings 30 and 32 which symmetrically overlap about the center of taking lens 20 to define a variation of aperture values. The requisite mutual, synchronous and corresponding movement of blades 26 and 28 is realized by virtue of their mutual geared interconnection with a drive pinion 34. Note in this regard that blade 26 is formed having a rack extension 36, the geared teeth within which are meshed with those of pinion 34, while blade 28 has a rack extension 38, the gear teeth within which are meshed with pinion 34 on an opposite side thereof from extension 36.

The opposite sides of blades 26 and 28, respectively, are formed having extensions 40 and 42 designed to move within a light sensing station depicted generally at 44. Extensions 40 and 42, respectively, are formed having tapered secondary openings 46 and 48 which move in mutual symmetry to define a progressively varying secondary opening 50 (FIG. 2) before the light detecting elements of the exposure control circuit. Light sensing station 44 further includes an entrance optical assembly including a lens 52 having a field of view corresponding with that of taking lens 20 and a bracket 54 supporting lens 52. Bracket 52, in turn, is fixed to rear casting 12.

Rotational drive is imparted to the pinion 34 from a stepper motor 60, the output shaft 62 of which is fixedly journaled within pinion 34. As is shown in FIG. 3, motor 60 is of relatively thin dimension and is supported upon mounting plate 14 of the compound mounting fixture. To assure proper enmeshment between pinion 34 and rack extensions 36 and 38, guide pins 64 and 68 are provided and are shown extending from a rearward portion of bracket 14. As is apparent from the structure described, when motor 60 is selectively energized from an energizing pulse or clock train and receives an appropriate directional signal, it is capable of driving blades 26 and 28 from an orientation fully blocking the optical path toward open orientations such that openings 30 and 32 may serve to define a progressive variation of aperture values until full aperture opening is reached.

To define an interval of exposure, motor 60 is energized from a pulse train and receives a directional sense signal to cause pinion 34 to rotate in an appropriate direction opening the shutter blades until a sufficient exposure value has been reached. This evaluation may be performed at light sensing station 44 or through a range responsive flash control circuit or the like. When an appropriate signal has been reached, energizing drive pulses in the presence of a reversing drive signal are generated to rotate pinion 34 in an opposite sense to cause the exposure mechanism to reassume a closed or light blocking orientation as shown in FIG. 1. Other selective energizations and directional commands to motor 60 can be provided to open or secure the optical path defined at lens 20 where the mechanism is utilized for single lens reflex applications or the like. However, in the initial description to follow, emphasis is placed upon the operation of the mechanism wherein motor 60 drives blades 26 and 28 from a fully closed toward an open orientation, thence the motor is reversed to close the blades to terminate an interval of exposure.

Stepper motors as at 60 generally are motive devices which respond directly to a pulse of specified length and amplitude to provide a motive drive output. The position of the motor shaft 62 is directly proportionate to the number of these excitation or drive pulses applied. Rotational direction for the output of shaft 62 is controlled by electrical shading. Depending upon the use contemplated, the motors generally are designed utilizing multiple coils forming multiple stators, each of which is bifilar wound to allow 4 to 8 stator phases. The rotors usually are formed in permanent magnet fashion having a plurality of pole points. A more comprehensive description of stepper motors as they are used in conjunction with exposure mechanisms is provided in a copending application for U.S. patent entitled "Non-Cocking Springless Shutter Developing Two Parameter Exposure Regulation" by I. Erlichman, Ser. No. 362,926 filed of even date herewith and assigned in common with the parent application on May 22, 1973. In that application, a stepper motor having a step angle of about 71/2° operating to drive exposure mechanism blades between their terminal positions under about a 20 pulse energization each direction is described as being adequate for the purpose at hand. When combined with a vernier form of control, such exposure control derives a resolution amounting to about 1/12 of an F/stop, a resolution considered highly desirable in automatic exposure control schemes.

In the discourse to follow, the control logic circuit for operating the exposure mechanism of the invention is described as it performs in the course of a conventional exposure interval. Following such description, this operation is described as it is carried out in conjunction with the full photographic cycle of a fully automated single lens reflex camera.

For purposes of clarity in the description to follow, Boolean enumeration is utilized to describe the pulse logic of the circuit diagrams. For instance, a "low" signal is considered to be one having a potential essentially at ground and is represented by a logical "0". Conversely, a "high" signal is considered positive and is depicted by a logical "1". Additionally, the circuit will be seen to utilize bistable multivibrators in the form of J-K flip-flops. Generally, a J-K flip-flop is a complementing flip-flop having two added control signals, arbitrarily designated J and K that serve to limit the conditions under which the flip-flop will change to the 1 and 0 states, respectively. While several forms of such logic devices are available for the instant purpose, the particular flip-flops shown in the drawings are ones whose outputs in time change on the negative transition of clock inputs. The P or preset input, representing a d.c. set input to given flip-flop will cause its corresponding Q output to be a logical "1" where such P input is ground. A d.c. reset input to a given such flip-flop will cause its Q output to be a logic "0" when that input is at ground potential. Of course, this output is in complement with its corresponding Q output. To further facilitate the description to follow, the "Q" output of any flip-flop will be designated by the label of the particular flip-flop, while the not Q or "Q" output of a given flip-flop is designated by the label prime of that flip-flop. It will be understood, however, that alternate forms of flip-flops as well as such designations may be utilized to derive an equivalent form of logic circuit. In same regard, it will be seen that the circuit of FIG. 4 utilizes NAND logic elements. It should be understood that other logic criteria, for instance "AND" logic may be utilized in the design of such logic circuits.

Concerning the particular output logic of each of the J-K flip-flops, the Q output of such flip-flop will switch from the 0 state to the 1 state when J is 1 at the time of a clock or actuating pulse, although, if the flip-flop is already in the 1 state, that is "reset", the binary value of J will not affect the flip-flop. Analogously, the flip-flop will switch from the 1 state at its Q terminal to a 0 state, while its Q will transition to 1 at such time that the K input is 1. When both the J and K terminals are "0", clock or actuating pulses will have no effect on the flip-flop.

Referring now to FIG. 4 and, in reference thereto to FIGS. 5 and 6, the control arrangement of the invention is revealed. Motor 60, as described in connection with FIGS. 1-3, is represented in FIG. 4 by a block 60'. A motor directional control circuit is shown at 65, connected to motor 60 along line 67 and a motor drive network is shown at 68 connected to motor 60 by line 70.

The exposure phase of a photographic cycle is initiated by an appropriate signal generated from a cycle control function of the camera as depicted by block 72. It should be understood that for simple photographic cycles such signal may be generated from the manual closure of a switch or the like. Cycle control 72 initially supplies a signal along line 74 to a reset function shown at block 76. Reset block 76 presents a transient "low" or 0 pulse designated "Z" along lines 78, 80 and 82 to all flip-flops within the circuit. This reset event is depicted at block 84 in FIG. 6 and is represented at "Z" in the pulse diagram of FIG. 5. The input and output conditions of all flip-flops within the circuit being thus aligned to commence a photographic cycle, cycle control 72 then imparts start and energization signals from along lines 86 and 88 to a start function 90 and main pulse generator. The start function is shown in appropriate sequence at 94 in FIG. 6 and additionally is represented by the curve aligned with the label "START" on the pulse diagram of FIG. 5. When so activated, pulse generator 92 delivers a pulse train along line 96. This pulse train, having the highest selected frequency, f ₀ , of the control circuit is simultaneously introduced along lines 98 and 100 to the clock input terminals C of respective J-K flip-flops K _b and K _a . The Q output terminal of flip-flop K _b is connected along lines 102 and 104, respectively, to the J and K input terminals of flip-flop K _a . Accordingly, it will be recognized that flip-flops K _b and K _a are coupled in divider network fashion. Looking additionally to FIG. 5, it may be seen that the consequent Q output at line 102 of flip-flop K _b represents a divide by two pulse train frequency of the clock pulse at line 96. By virtue of its interconnection with flip-flop K _b , the resultant Q output of flip-flop K _a at line 106 is a pulse train representing divide by four submultiple of the pulse generator frequency, f ₀ . This pulse train designated K _a , as shown in FIG. 5, represents the opening phase clock input to the circuit. The frequency of this clock train may be represented as f ₁ .

Returning to starting function 90, and looking to the corresponding pulse curve in FIG. 5, as the output thereof at line 108 alters from a high value to a low and then transitions to a high or 1, the preset terminal of a J-K flip-flop G ₁ causes the Q output thereof to transition to a high. This high Q value is stable and is present at line 110. The G ₁ flip-flop is present in the circuit to stabilize the actuating signal deriving from starting network 90. For instance, should such network be formed utilizing, for the present purpose, a switch having an undesirable bounce characteristic, once an initial actuation or closure of the switch is recognized, the stable output Q at line 110 will remain stable at the noted high value. Accordingly, the circuit becomes immune from vagaries otherwise encountered with ambiguous switch performance.

The G ₁ output at line 110 is introduced to the J terminal of a J-K flip-flop G ₂ . The corresponding clock input C of flip-flop G ₂ is coupled from along line 110 to the opening phase clock pulse train K _a emanating from distribution line 106. As shown at the appropriate curve in FIG. 5, with the presence of a negative transitioning, clock pulse K _a at clock input "C" of flip-flop G ₂ causes it to toggle to produce a high at its output terminal Q and a corresponding low at its output Q. Flip-flop G ₂ serves the function of synchronizing the starting or actuating signal from block 90 with the opening phase clock pulse train K _a . Such synchronization permits highly accurate timing of all operational events to take place from this starting point in time. This clock synchronization feature is represented functionally in FIG. 6 at block 114.

The not Q or Q terminal of flip-flop G ₂ is coupled along line 116 to the clock input terminal C of a third J-K flip-flop G ₃ . Accordingly, flip-flop G ₃ toggles to produce a high value at its output Q which is introduced along lines 118 and 120. Represented as G ₃ , this high value signal is utilized as an exposure mode signal, the purpose of which is to provide a consistent and continuing recognition that an exposure cycle is underway. The G ₃ development of this logic information is represented at function block 122 in FIG. 6. As additionally shown in that figure, the output from flip-flop G ₃ serves to activate a light evaluating circuit as shown at block 124. The figure further shows that an opening phase motor directional logic signal is generated as illustrated at function block 126 and a step limit monitor arrangement is activated as shown at block 128.

Returning to FIG. 4, the noted exposure evaluating function includes, inter alia, a light sensing network 134 coupled to line 120 through 136 and to ground through line 138. Network 134 may assume a variety of configurations, however, a configuration described and claimed in U.S. Pat. No. 3,620,143 by J. P. Burgarella is particularly appropriate. This form of network utilizes a photovoltaic light sensing device operating in a current mode in conjunction with an operational amplifier having an input circuit which includes a capacitive feedback path. The output of network 134 is present at line 140 and is introduced to a trigger circuit 142. Coupled to line 120 through line 144 and to ground through line 146, circuit 142 has a normally not conducting input stage and a normally conducting output stage which function to rapidly reverse their conducting senses upon the appearance of a threshold voltage value at line 140 of a predetermined level. The output of trigger circuit 142 is present at line 148 and is identified in the pulse chart of FIG. 5 as "ST _o ". Note in the latter figure that output ST _o remains low during the opening or initial phase of an exposure interval.

Turning now to the opening phase motor directional logic signal as is described in connection with function block 126 of FIG. 6, with the development of the initial low or "Z" signal at output lines 78 and 80 of reset network 76, a directional logic J-K flip-flop R is reset by virtue of its connection through line 150 to line 180. The resultant state of its output "Q" is "low" at connected output lines 152 and 154. Line 154, in turn, is connected to motor directional control network 65 through line 156. The complementing Q output of flip-flop R is now high and is introduced to motor directional control network 65 from lines 160, 162 and 164. Represented for descriptional purposes as "R'" this signal is also introduced to one input terminal of a NAND gate 158 which represents a component of a phase control feature of the circuit.

The step limit monitor feature of the circuit as described at block 128 in FIG. 6, includes paired decade counters designated "M" and "N". Being of conventional design, these counters are reset, respectively, through lines 170 and 172 which, in turn, are coupled between reset line 80 and the R _D terminals thereof. The latter reset terminals are common to all four bits A-D and a low at the reset input produces a low or 0 at all four of the noted bits. A counting operation is performed by the counters on the falling or negative-going edge of an input clock pulse. Bit terminal "A" of counter M is connected along line 174 to one input terminal of a NAND gate 176, while the C ₂ clock pulse input thereof is connected along line 178 in common with line 174. The D bit terminal of counter M is connected along lines 180 and 182 to the clock input C ₁ of counter N and to another terminal input of gate 176. A parallel entry line 184 serves to provide the same input to a third terminal of gate 176 from line 182. The fourth input to NAND gate 176 is provided from the A bit terminal of counter N through lines 186 and 188. Line 188 additionally couples clock input C ₂ of counter N in common with this signal. Thus interconnected, counters M and N, operating in conjunction with NAND gate 176, serve to provide a twenty pulse or step counting feature in response to clock impulses from a pulse train identified as K _Z introduced to clock input "C ₁ " of counter M through line 190. As discussed earlier, the twenty step or pulse count provided by the counter network is selected in accordance with the number of step pulses required to move exposure mechanism blades 26 and 28 from one terminal position, for instance fully closed as shown in FIG. 1, to a complementing fully open position. Of course, the number of pulses selected for this operation is a matter of design choice, depending upon the apertural value resolution desired. The output states of bits A-D of counter N as well as output terminal A of counter N are represented, respectively, in the pulse chart of FIG. 5 as M _A - M _D and N _A .

With the introduction of appropriate opening phase logic to NAND gate 158, monitoring and motor drive is permitted to take place. Looking momentarily to FIG. 6, the motor drive function is represented at block 190, while the counting operation takes place as represented at block 192. Returning to FIG. 4, NAND gate 158 serves to pass opening clock pulses K _a , as are present at output lines 106 and parallel input line 194, only in the presence of signal G ₃ , presented from line 120 through line 196 to gate 158, and directional signal R' inserted to gate 158 from line 154. More particularly, NAND gate 158 will pass clock pulses K _a in the presence of the Boolean expression: G ₃ R'K _a , where G ₃ and R' are synchronous to K _a .

The output of gate 158 is directed along line 200 to gate 202, whereupon it passes to input line 190 of counter M. As noted earlier, the signal passing from gate 202 is arbitrarily designated as K _Z . The energizing pulse train at line 190 is simultaneously introduced along line 204 to drive network 68 of motor 60'. When combined with the earlier directional signal from J-K flip-flop R, the pulse train introduced to network 70 causes motor 60' to be energized in a directional sense causing blades 26 and 28 to move toward orientations defining variable aperture values over lens 20. Looking to FIG. 5, the energizing pulse train during opening phase performance is represented in the initial portion of pulse line "K _Z ".

Returning momentarily to FIGS. 1 and 2, a switch S ₁ is revealed to be mounted within an upper corner of housing 10 upon rear casting 12 thereof. Switch S ₁ is formed having an insulative base 210 from which extend two resilient contact members 212 and 214. Mounted in cantilever fashion, contacts 212 and 214 are normally open, contact leaf 214 being biased outwardly from contact with leaf 212. When blades 26 and 28 are in the fully closed orientation of FIG. 1, extension 36 of blade 26 serves to but against leaf 214 to effect closure of switch S ₁ . However, when motor 60 is energized and blades 26 and 28 are driven from pinion 34, contact leaf 214 separates from contact 212. Accordingly, switch S ₁ serves a monitoring feature informing the control circuit that blades 26 and 28 have, indeed, moved from their closed terminal orientations. Conversely, when blades or elements 26 and 28 resume their fully blocking position, leaves 212 and 214 will have resumed contact to inform the circuit that an exposure interval is completed or that the optical path of the photographic apparatus is blocked and secured. Looking momentarily to FIG. 6, the opening phase monitor signal to which this opening actuation of switch S ₁ contributes is represented at function block 216.

Returning to FIG. 4, switch S ₁ is seen to be coupled between line 218 and ground. Line 218, in turn, leads to one input of a NAND gate 220. The opposite input at line 162 extends through line 160 to the Q output of J-K flip-flop R. Accordingly, the signal at line 162 is R' during the opening phase of an exposure interval. The resultant low signal at output line 224 is introduced to the preset or P terminal of a J-K flip-flop designated "H ₁ ". The resultant "Q" output at line 226 transitions to a logical 1 or high. Looking to FIG. 5, it may be seen in conjunction with the logical curves S ₁ and H ₁ that H ₁ assumes a stable state in immediate response to the opening of switch S ₁ . Here again, the control circuit becomes immune from any subsequent switch bounce or the like occasioned in the mechanical actuation of switch S ₁ . Line 226 is connected to the J input of another J-K flip-flop designated "H ₂ ", while the Q terminal of flip-flop H ₁ is connected to the K terminal of flip-flop H ₂ through line 228. The clock input terminal C of flip-flop H ₂ is coupled along line 230 to the K _Z output at line 190 carrying the energizing pulse train or clock train to motor drive network 68. Accordingly, the Q output of flip-fop H ₁ at line 226 is, in effect, "anded" with the energizing drive or clock pulses of the system. As shown in FIG. 5, the Q output terminal at line 232 of flip-flop H ₂ assumes a stable high state which is witnessed at the clock input terminal C of another J-K flip-flop designated H ₃ . The Q output terminal of flip-flop H ₃ , connected with line 234, remains low as shown in the corresponding pulse diagram of FIG. 5, throughout the opening phase of an exposure interval. Note that flip-flops H ₂ and H ₃ are initially reset from lines 82 and 236.

Returning to FIGS. 1, 2 and 6, as blades 26 and 28 are driven to define progressively widening aperture values over the taking optical path of housing 10, secondary openings 46 and 48 of those blades simultaneously insert brightness level and aperture value information to light sensing network 134. Either of two control conditions may obtain during this opening phase. For instance, as shown at function block 240, the threshold level of trigger 142 may be reached to cause its output at line 148, designated "ST _o " to assume a high value. Such high value will cause a motor reversal and exposure termination. On the other hand, blades 26 and 28 of the mechanism may be driven to their full open aperture orientation before such high signal is reached. In this event, the monitoring function of the circuit will evolve a step limit signal as represented at block 242. For purposes of clarity in the discussion to follow, the latter condition in which a full aperture opening is achieved before an "ST _o " high signal is reached at line 148 is described in detail.

As energizing pulse train K _Z at line 190 is fed both to motor drive network 68 and to clock input C ₁ of counters M and N, counters M and N will commence cumulative counting until such time as twenty pulses are recorded. The pulsing technique wherein this value of twenty is achieved is shown in FIG. 5 in connection with pulse curves M _A - M _D and N _A . As shown in these curves, at such time as a twentieth step is witnessed by the monitoring feature, the M _A output at line 174, the M _D output at lines 182 and 184 and the N _A output at line 188 will transition to a low or logical 0 value. With this transition, the output of NAND gate 176 at line 244 transitions to a logical 1 or high state and is introduced to NAND gate 246. The opposite input to gate 246 derives from the output at line 148 of trigger circuit 142. This output is directed through an inverter 248, thence to line 250 and the input side of gate 246. Inasmuch as output line 148 is high in the course of exposure evaluation, its value is inverted at 248 to a low which signal is delivered through line 250. The resultant output at line 252 of gate 246, therefore, is high or a logical 1. This high signal, designated for descriptive purposes as "X ₁ ", is introduced to the J input terminal of flip-flop R. As a consequence, directional flip-flop R toggles in synchronism with a negative-going clock or drive pulse deriving from lines 254 and 106. The consequent signal at the Q output terminal line 152 is high and is represented as "R".

Simultaneously with the development of the high or R signal, the previously derived R' signal from flip-flop R alters to a complementing "low" value. In response to this alteration, gate 158 acts to block the passage of clock or drive pulses K _a from entering drive network 68 through line 204. Motor 60 stops. However, the directional sense for causing motor 60 to operate in reverse to cause blades 26 and 28 to move in a direction closing the optical path of housing 10 is established. Note in FIG. 5 that the drive or clock pulse train K _Z has been interrupted. Further, it may be observed that the inputs from flip-flop R to motor directional control 65 have altered in complimentary fashion, the input at line 156 being high and the input at line 164 being low. An important aspect of this reversing signal resides in the presence of a reversing input to motor directional control 65 before any energizing pulses for reversing motor 60 are capable of being delivered.

When light sensing network 134 determines that an exposure terminating phase of the exposure interval should be undertaken, its input at line 140 to trigger 142 reaches a predetermined threshold value and the output at line 148 of trigger 142 rapidly converts to a low state. The resultant output of NAND gate 246, designated X ₁ , at line 252 remains low, however, the low value at line 148 is witnessed through line 256 at the "J" input terminal of a J-K flip-flop designated "ST _x ". This low signal at line 256 is represented in FIG. 5 as "ST _o " and, for illustrative purposes, is seen to occur at a point in time representing about 1/4 of a clock or drive pulse width, f ₁ . This somewhat rapid reaction of flip-flop ST _x represents a vernier response aspect of the invention. Note that the clock input terminal C of flip-flop ST _x is connected through line 96 to pulse generator 92. Accordingly, the output of flip-flop ST _x is synchronized with pulse generator frequency, f ₀ . With the presence of a negative-going pulse at frequency, f ₀ , and a high signal at line 256, flip-flop ST _x toggles to produce a high at its Q output terminal on line 258. The output at line 258 then is introduced to a divider network including J-K flip-flops K ₁ and K ₂ which serve to re-develop clock or energizing drive frequency, f ₁ , at a point in time substantially synchronous with the development of signal ST _o .

Flip-flop K ₁ of the divider network, as designated at 260, is arranged such that its J and K terminals are connected, respectively, with the Q terminal of flip-flop ST _x through lines 258 and 262. Thus connected, the Q output terminal of flip-flop K ₁ at line 264 represents a "divide by two" value of pulse generator frequency, f ₀ , as synchronized at flip-flop ST _x . Line 264, in turn, is coupled with the J input of J-K flip-flop K ₂ . The clock input C of flip-flop K ₂ is coupled through line 266 to pulse generator 92 output line 96. Accordingly, flip-flop K ₂ again divides the input frequency thereof by two and derives a reversing energizing pulse train at its Q output on line 268. Line 268 is directed to the input of a reversing NAND gate 270. It may be noted that J-K flip-flops ST _x , K ₁ and K ₂ may be cleared or reset from reset network 76, respectively, through lines 272, 274 and 80. Looking to FIG. 5, the performance of divider circuit 60 is revealed in connection with the pulse diagrams labeled "K ₁ " and "K ₂ ".

Returning to FIG. 6, the operation of the control circuit to the present stage may be reviewed. Following the development of the step limit signal as described in connection with function block 242, the resultant input signal to flip-flop R is synchronized with clock pulses K _a as shown at function block 276. Upon these signals being effectively "anded", flip-flop R toggles to derive a closing phase directional logic signal, R, as depicted by block 278. Simultaneously, the R' signal at gate 158 is removed to, in turn, inhibit the drive pulse train K _Z at line 190. As a consequence, motor 60 is halted as shown at function block 280. Also, the R' signal at gate 220 is removed, however, signal H ₁ remains stable. The monitoring feature of the circuit is enabled to monitor the closing phase of the exposure interval as shown at function block 282. Looking to FIG. 4, this is carried out by asserting a high or R signal along line 154 to gate 284.

Returning to FIG. 6, the vernier detection feature derived from flip-flop ST _x is revealed at function block 286. It will be apparent that should the exposure termination signal shown at block 240 occur before the step limit signal depicted at block 242, the function of synchronizing as described at block 276, the development of the closing phase directional logic shown at function block 278, as well as the resultant stopping of the motor as described in connection with block 280 and enabling of the closing phase monitor as shown at block 282 will immediately take place. Additionally, the vernier detection feature as shown at block 286 will occur in response to the synchronization of the R signal as described in connection with block 276. The exposure interval cycle now continues in common to both conditions, i.e., the development of an exposure termination signal either before or after the development of a step limit signal to which the system is accommodated.

Because the mechanism representing blades 26 and 28 as well as the drive components of motor 60 should evidence some inertial or mass accelerative characteristics, whether of trace value or otherwise, the system of the invention imposes a deliberate delay of predetermined interval. This interval is selected as representing the interval of one pulsewidth at frequency f ₁ . The selection of such a fixed interval permits simplified design of turn-around anticipation for the drive system of the mechanism. For instance, this anticipation design parameter is incorporated within the contour design of secondary photocell sweep openings 46 and 48 (FIGS. 1 and 2). The delay function is represented in FIG. 6 at block 286.

Returning to FIG. 4, the one pulsewidth delay feature is derived from another J-K flip-flop designated K ₃ . Clock input C of flip-flop K ₃ is connected to the Q output line 268 of flip-flop K ₂ from along line 288, while its K input terminal is coupled to ground through line 290 and its reset terminal, C _L , is connected to line 80. The Q output terminal of flip-flop K ₃ is connected with line 292 and the resultant signal thereupon, designated "K ₃ " is directed to an input of NAND gate 270. Gate 270 will pass energizing or clock drive pulses "K ₂ " at such time as positive-going K ₂ and K ₃ pulses are synchronously received, as revealed in FIG. 5 astride the appropriate signal designation. Expressed in Boolean logic, this pulse train is passed under the conditions G ₃ K _x R, where: K _x = K ₂ K ₃ . From gate 270, the pulse train is directed along line 294 and through a NOR gate 202 to evolve pulse train signal K _Z at line 190. It may be noted, therefore, that the signal K _Z , expressed in Boolean logic, presents the equation: K _Z = G ₃ K _a R' + G ₃ K _x R.

Looking again to FIG. 6, with the development of the K _Z signal for reversing exposure mechanism blade motion, the counting function again ensues as depicted at block 296 and motor 60 is driven as depicted in function block 297.

Referring to FIG. 4, as in the opening phase of the exposure interval, an energizing pulse train, K ₂ , or K _Z , is introduced along line 204 to drive network 68 to energize motor 60. Simultaneously, paired counters M and N monitor the number of pulses delivered to motor 60 and when that number reaches the predetermined twenty required for termination of motor energization, the condition sense of the signals at lines 174, 182 and 188 serve to evolve a high value at line 244 extending from gate 176 which, in turn, is directed to the input side of gate 246. When this signal at line 244 is combined with the high signal at line 250, gate 246 output X ₁ transitions from a low to a high level.

Looking to FIGS. 1, 2 and 6, as exposure mechanism blades 26 and 28 approach their closed orientations, extension 36 of blade 26 again contacts resilient leaf 214 of switch S ₁ and urges it into contact with leaf 212. Closure of switch S ₁ provides a low signal at line 218 which is introduced through an inverter 302 and combined with the high signal, R, at line 154 at NAND gate 284. The resultant high signal at line 304 is introduced to the clear or reset terminal, C _L , of J-K flip-flop H ₁ . As in the earlier case, and as shown at block 306, flip-flop H ₁ serves the function of accommodating for any bounce or similar vagary occasioned with the opening or closing of switch S ₁ . The output of flip-flop H ₁ toggles to exhibit a high value at its Q output terminal at line 228. This output is "anded" with the K _Z clock input at flip-flop H ₂ , as introduced from line 230. Thus synchronized with the clock or drive pulse train K _Z , the Q terminal output of flip-flop H 2 transitions to a low at line 232. As a consequence, flip-flop H ₃ toggles such that the Q output thereof at line 234 reverts to a "low" state. This low value is transmitted along line 234 to logic gate 310, thence along line 312 to logic gate 314 and thence along line 316 to the reset or clear terminal C _L of J-K flip-flop G ₃ . Inasmuch as flip-flop G ₃ controls the delivery of driving pulses to motor 60, the resetting of this flip-flop causes motor drive termination as depicted at block 318 in FIG. 6. In consequence, the high output at line 118 of flip-flop G ₃ transitions to a low to remove all pulse gating at AND gates 270 and 158. With the termination of this G ₃ exposure mode signal, an exposure interval is terminated as depicted in FIG. 6 at block 320.

The discussion now turns to operation of the stepper motor driven exposure mechanism and the above-described exposure control circuit as it is operated in conjunction with a fully automated single lens reflex camera. As described earlier, such a camera must cause blades 26 and 28 to define a fully open aperture for purposes of viewing and focusing. Following the assertion of power to the camera, blades 26 and 28 are required to fully close and remain so closed until such time as the optical path of the camera is converted from a viewing orientation to an exposure orientation. Once this orientation is achieved, the camera carries out the exposure cycle described above (See U.S. Pat. No. 3,714,879). At the termination of that cycle, the exposure mechanism blades remain closed until the optical path components of the camera reassume their viewing-focusing orientation. At such time as such orientations are achieved, motor 60 again drives blades 26 and 28 to their fully open condition.

Looking to FIG. 7, the condition of the automatic reflex camera at such time as viewing and focusing are carried out is represented at block 326. Following appropriate focusing and viewing, the operator applies power to the control system at cycle control function 72. As depicted at block 328 and beside the "reset" label of the energization chart of FIG. 8, cycle control 72 then activates reset function 76. As a consequence, the logic input and output sense of all flip-flops and counters within the circuit are aligned in identical fashion as at the beginning of an exposure cycle.

Immediately following the activation of reset function 76, as shown at block 330, and at the energization trace labeled "preset" in FIG. 8, cycle control 72 activates a preset network 332 from line 334. The output of network 332, present at line 336, converts from a high value or state to a low state which signal condition is transferred to the present input terminal, P, of flip-flop R. The same signal simultaneously is delivered to preset terminal, P, of flip-flop ST _x through line 338. This is a D-C set input which causes the Q output of both flip-flops to assume a logic 1 or high condition. As depicted at block 340 in FIG. 7, the presetting of flip-flop R causes the development of an "R" signal condition at NAND gate 270. This signal condition will permit gate 270 to transmit pulses generated from divider network 260. As shown in FIG. 8, cycle control 72 then activates start network 90 to cause the circuit to commence to carry out an operational cycle in dependence upon the directional logic inserted at NAND gate 270. This start function is represented in FIG. 7 at block 342. The earlier described presetting of flip-flop ST _x causes its Q output at line 258 to assume a high condition which, in turn, activates divider network 260 to develop energizing drive pulse train K ₂ in identical fashion as disclosed in connection with FIG. 6.

The activation of start network 90 having developed an appropriate earlier discussed signal G ₃ , pulse train K ₂ is passed by gate 270 and is introduced through gate 202 and line 204 to drive network 68. Simultaneously, counters M and N commence to monitor the number of pulses delivered from line 190 as depicted at block 344 in FIG. 7. The appropriate high signal value being present at line 152, motor directional control 65 causes motor 60 to operate in a direction closing blades 26 and 28. The motor drive operation is depicted in FIG. 7 at block 346, while the counting or monitoring function is depicted therein at block 348. As a predetermined or twentieth pulse is received by motor 60, extension 36 of blade 26 (FIG. 1) makes contact with leaf 214 of switch S ₁ . In consequence, flip-flop H ₁ is reset from line 304 as discussed in connection with block 300 of FIG. 6. The outputs of flip-flop H ₁ toggle in complement, line 226 assuming a low state. This input is "anded" with pulse train K _Z at flip-flop H ₂ and introduced to flip-flop H ₃ as described in connection with FIG. 6. As a consequence, reset network 76 is reactivated, as depicted in FIG. 8. In FIG. 7, the development of the S ₁ shutter closing signal is shown at block 350, the clock synchronization feature of H ₁ is depicted at block 352, while the activation of reset network 76 is depicted at block 354.

As discussed earlier in connection with block 318 of FIG. 6 and as shown at block 356 in FIG. 7, motor 60 is stopped and is in a non-powered state. During the resultant closed or optical path blocking orientation, the exposure chamber of the automatic camera is secured and the optical path components thereof are reoriented to assume exposure mode positions as indicated by block 358.

As shown in FIG. 8 in connection with the start network operational curve and as shown at block 360 in FIG. 7, cycle control 72 reactivates start network 90 at the conclusion of optical path conversion to cause the circuit to carry out a conventional exposure cycle. This cycle has been discussed in connection with FIGS. 4, 5 and 6 and is depicted in FIG. 7 as block 362. At the conclusion of an exposure interval, optical path conversion again is carried out as depicted at block 364 in FIG. 7A. When the components of the camera have reassumed their viewing-focusing orientations, cycle control 72 initially activates reset network 76 as shown at block 366 in FIG. 7A and at the corresponding energization curve of FIG. 8. This reset function is the same as that carried out at the commencement of an exposure cycle as discussed above.

Following the resetting operation, starting network 90 is again activated as shown at block 368 and at the appropriately labeled energization diagram of FIG. 8. Simultaneously, cycle control 72, operating along line 370, disables light sensitive network 134. This can be carried out, for instance, by shunting the capacitive feedback of the earlier described light sensing circuit 134. This operational event is depicted under appropriate label in FIG. 8 and at block 372 in FIG. 7A. As in a conventional exposure cycle, the activation of start network 90 causes the development of an opening phase directional logic signal, R', as depicted at block 374. Simultaneously, the step limit monitor feature including counters N and M are activated as shown at block 376 and as described earlier in conjunction with block 128 of FIG. 6. As a consequence, motor 60 is driven as depicted at block 378; blades 26 and 28 are moved toward orientations defining progressively opening or widening apertures and counters M and N monitor the number of pulses in the drive pulse train K _Z as depicted at block 380. The latter counting procedure was discussed in connection with block 192 of FIG. 6. As a terminal count is reached at counters M and N, a step limit signal is developed, as described above, at line 252 and is introduced to the J input terminal of flip-flop R. This signal is synchronized or "anded" with pulse train K _a , as depicted at block 384, and discussed earlier in connection with block 276 of FIG. 6. As a consequence, flip-flop R toggles to produce an R output, thereby causing NAND gate 158 to terminate the passage of pulse train K _a to line 200. Development of this additional logic signal is shown in FIG. 7A at block 386. With the blocking of energizing pulses K _Z , motor 60 stops, as depicted at block 388 in FIG. 7A and the reflex camera has reassumed its viewing-focusing mode, blades 26 and 28 now defining an aperture opening of maximum width. Cycle control 72 then removes power from the system.

Since certain changes may be made in the above-described apparatus and system without departing from the scope of the invention herein involved, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.