Electronic amusement machine
United States Patent 3889956

This specification discloses an electronic amusement game that is adapted to play a form of card game. The machine has a face bearing card representations capable of illumination during use of the machine. Illumination of the card representations is achieved by a function control circuit causing a memory, containing bits corresponding to each card representation to be scanned and a memory bit set when a vacant address in the memory is sensed. The machine has a display cancellation facility which is operable to cancel a display of the last memory bit set at the discretion of the player within a predetermined time and furthermore includes circuitry for detecting display of certain combinations of card representations for providing a free game or actuation of a disc pay-out facility. In an alternative form the memory is addressed by means of a programmed read only memory.

Application Number:
Publication Date:
Filing Date:
Primary Class:
Other Classes:
International Classes:
A63F1/00; G06F19/00; (IPC1-7): A63F1/00
Field of Search:
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US Patent References:
3375352Bowling scorer utilizing semiconductor elements1968-03-26House et al.
3357703Combined clock and chance device1967-12-12Hurley
2786680Racing games1957-03-26Northrop et al.

Primary Examiner:
Pinkham, Richard C.
Assistant Examiner:
Kramer, Arnold W.
Attorney, Agent or Firm:
Cushman, Darby & Cushman
I claim

1. An electronically controlled amusement apparatus adapted to play card games comprising:

2. An apparatus as in claim 1 wherein said bits setting means includes:

3. An apparatus as in claim 2 wherein said logic means includes:

4. An apparatus as in claim 3 wherein said addressing means includes:

5. An apparatus as in claim 3 wherein said further circuit means includes:

6. An apparatus as in claim 5 further including:

7. An apparatus as in claim 2 wherein said bits setting means includes:

8. Apparatus as in claim 7 further including:

9. Apparatus as in claim 8 further including:

10. Apparatus as in claim 7 further including:

11. Apparatus as in claim 10 further including means connected to said lamps for sequentially illuminating said lamps when said first start flip-flop is in said second condition.

12. Apparatus according to claim 10, further comprising an audio tone generator circuit which is actuated for a predetermined period after the game is started, said generator circuit comprising an audio tone generator and an audio amplifier for driving a loudspeaker, said tone generator including an oscillator whose output is varied by switching different values of resistance to earth into said oscillator circuit by means of a multivibrator circuit running at a preset frequency.

13. Apparatus as in claim 2 further including:

14. Apparatus according to claim 1, wherein said memory comprises a plurality of pairs of cross-coupled gates each of which form a flip flop constituting a bit of said memory.


This invention relates to an electronic amusement machine.

Many different forms of amusement machine are known, including recreational machines such as pin ball machines, and poker machines. it is the object of the invention to provide an electronic machine capable of being used to play various forms of card games and other games, in recreational modes.


The invention provides an electronic amusement machine comprising a face having a number of displays capable of illumination during use of the machine, a memory containing bits corresponding to the displays on the face, means for addressing said memory in a random manner or in programmed manner resembling random addressing to set one bit in said memory, and circuit means connected to said memory bits for illuminating the display corresponding to said set bit.

In one form of the invention the machine may include circuitry to detect one or more combinations of displays to restart the machine to provide a free game, or to actuate a disc pay-out mechanism.

The addressing means may include a first pulse generator and means driven thereby for creating an address adapted to scan the bits of said memory at a predetermined rate, a second pulse generator for creating a pulse that causes the first pulse generator to stop and causes the memory bit being addressed at that time to be set. The timing circuits of the pulse generators are connected to a varying amplitude voltage and this prevents their running in any recognisable set relationship providing random setting of the memory bits.

Alternatively, the addressing means may include a read only memory (ROM) programmed with a predetermined large number of memory bit addresses, said ROM being stepped from one address to another in accordance with the desired operation of the machine to cause the setting of the memory bit whose address is read from the ROM. Each bit of the memory may comprise a cross-coupled gate forming a flip flop. Each gate may be a NAND gate.


In the drawings:

FIG. 1 is a simplified functional block diagram of one form of amusement machine embodying the invention;

FIG. 2 is a detailed circuit diagram of the machine of FIG. 1, the figure being on three sheets marked FIG. 2(A), 2(B) and 2(C) which are arranged so as to be read in conjunction with each other by aligning the similarly coded wires on the respective sheets; and

FIG. 3 is a simplified functional block diagram of an alternative form of part of a machine embodying the invention.


A general description of the machine and its function will first of all be given with reference to FIG. 1. The machine is enclosed in a housing, not shown in the drawings, which has a translucent front face bearing representations of twenty different playing cards capable of illumination as described below. The front also includes illuminatable signs such as a, `game on` sign a `game off` sign and a `free game` sign and a descriptive sign showing what type of game the machine plays. In the present example, the machine plays a type of poker game. The housing includes a disc slot and supports a start button and a display cancel button, both of which are illuminated when operable.

The machine includes a power supply 1 which is connected directly or indirectly to the various components of the machine. For the sake of convenience it is shown as an isolated block and its connections will be clear from consideration of FIG. 2. A disc detector 2 includes means for detecting the insertion of a disc for activating the power supply 1 and for causing the machine to be placed in the game on condition.

The disc detector 2 is connected to function control circuitry 3 which controls the various sequences of the machine, as will be described in more detail in relation to FIG. 2. As FIG. 1 shows, the function control arrangement 3 is connected directly or indirectly to all the other components of the machine.

Two pulse generators 4 and 5 are connected with the function control unit 3 and cause it to control an address generator 6, which in turn activates a display set decoder 7 connected to a display memory 8. A display illumination control circuit 9 is connected with the memory 8 and is activated in accordance with the state of the memory 8 to illuminate a selected number of representations on the face of the machine. In the present example, five displays are possible, but this may be varied depending on the type of game the machine is required to play. The number of displays is controlled by a display counter which scans the 20 displays, and when the count reaches five, the counter causes the machine to go into the game off state, unless a free game situation obtains. The pulse generators 4 and 5 operate so that the address generator 6 is inhibited in random manner and the decoder 7 randomly sets one position in the display memory. Thus, the sequence of the displays is always different making it impossible for the player to anticipate the course of the game.

A display cancel counter 10 is connected to a display cancel decoder 11 to control the number of display cancellations that are available to the player, in the present example ten. The cancel decoder, operates, when activated by the display cancel button, to cancel the last state set in the display memory 8 and to extinguish the lamp illuminating the corresponding representation on the face.

The machine also includes a free game detector 12 connected to the display memory 8 to detect whenever one or more combinations of displays is present on the face. In the present example two combinations of four displays activate the free game detector to set the machine in the game start condition again. It will be appreciated that the detector 12 may also be used to activate a disc payout mechanism.

As an additional feature, the machine includes an audio generator 13 adapted to operate a loud speaker to create a wavering sound which accompanies a sequential momentary lighting of all the displays on the face shortly after the disc is inserted. The lighting and audio effects are intended to give the impression that the cards are being shuffled prior to the start of the game.

Referring now to the three parts of FIG. 2, this circuit diagram represents one way of realising the necessary functions to be performed by the blocks described in FIG. 1. However, as will be appreciated by the person skilled in the art to whom this specification is directed, many other ways of effecting the necessary functions may be utilized. Component values are excluded as unnecessary for a proper understanding of the machine. The various components making up all the blocks of FIG. 1, with the exception of function control 3, have been outlined and allotted the same reference number as in FIG. 1. The unoutlined components collectively constitute the function control arrangement 3. Furthermore, in accordance with accepted practice, points that are connected in common are labelled with similar reference letters.

The sheet marked FIG. 2(c) shows at the top thereof a typical power supply for the machine, comprising a power transformer 11 connected via a fuse to a mains AC supply. The transformer 11 has two secondary windings, one of which is rectified using a diode bridge 12 to provide a lamp power supply rail L. A game off lamp 13 and a game on lamp 14 are arranged to be connected via the contacts R1 of a relay R/2 to L. The other secondary is also rectified using a diode bridge 15 and filter capacitors, and this rectified voltage is fed to a voltage regulator V which provides a logic power supply rail S which is nominally about +5V. Game name display lamps 16 and 17 are connected to S via relay contacts R2. The associated circuitry causes the lamps 16 and 17 to be illuminated alternately at about two second intervals while the machine is connected to the mains supply but not in use.

The disc detector 2 (FIG. 2(C)) includes a micro switch 21 mounted on the disc acceptor of the machine. The active terminal of the switch is connected to the input of a flip flop 22, the output of which is connected to the base of a transistor 23 which is connected to drive the relay R/2.

The function control circuitry 3 (Parts A and B of FIG. 2) includes the start button 30 which is inhibited until the flip flop 22 in the disc detector 2 is put into its active state by the insertion of a disc. When start button 30 is pressed a signal is gated to two flip flops 31 and 32 to set these in their other states. Flip flop 31 is connected to circuitry for scanning the memory 8 so as to cause sequential momentary lighting of the display lamps connected to circuit 9, and to a five second time delay circuit 33. The buffered output of flip flop 31 is connected to the audio generator and to the input of timer 33. Flip flop 32 is connected to the start button lamp 34 and to the pulse generator 5 to turn the lamp off and to start generator 5 when the button is pressed. After time out of delay circuit 33, the function control circuitry controls the action of pulse generator 4, the address generator 6, the display set decoder 7 and the display cancel decoder 11 to perform the functions described briefly above and in more detail below.

The pulse generator 4 generates a 1ms square wave pulse every 1/15 second (centre frequency 15 Hz) while pulse generator 5 generates a pulse each 5 seconds. The pulses from generator 4 are fed to the address generator 6 to enable the outputs of the decoder 7 to be addressed sequentially at the frequency of the generator 4. The pulse generated by generator 5 is fed to a flip flop 35 where it is stored until a vacant decoder address is sensed. The timing circuits of both generators are powered by the lamp supply rail L. This supply is a pulsating DC voltage as already mentioned which has its amplitude varied depending on the number of lamps 90 that have been illuminated by the illumination circuit 9. The pulsating and varying amplitude nature of the DC voltage substantially prevents the two generators 4 and 5 running in a set relationship at any one time and this ensures that the selection of the memory position, as described in more detail below, is of a random nature.

The address generator 6 (FIG. 2(A)) comprises a four bit binary number generator 60 and one bit 61 of a further four bit generator 36, the other three bits of which form part of the function controller 3. The generators 60 and 61 are reset each time the twenty memory positions have been scanned.

The binary address A,B,C,D, E generated by generator 6 is fed to the display set decoder 7, the display cancel decoder 11 and to a multiplexer circuit 37 forming part of the function controller 3. The display set decoder 7 comprises a first integrated circuit 70 which handles the setting of sixteen of the twenty displays, and a second integrated circuit 71 that handles the remaining four displays. The decoder outputs 72 are connected directly to one input of one of the gates 80 forming each bit of the memory 8 and these outputs are controlled by the fifth address bit E and the set display strobe created by the function controller 3.

The display memory 8 comprises 20 memory bits each consisting of a two input NAND gate 80 and a three input NAND gate 81 connected in a cross-coupled relationship. For convenience, only the first and last bits are shown. One input to each gate 81 is commoned to the function controller 3, while the output of each gate 80 is connected to the display illumination circuit 9. The outputs M1 to M20 of each bit are connected to the inputs of the multiplexer circuit 37, similarly labelled. The multiplexer monitors the set output of the display memory 8 and is connected via gates as shown to a card counter forming part of generator 36. This counter is reset each time the 20 memory positions have been scanned, and when the count reaches five, generator 36 outputs a signal that resets flip flop 32 and also resets flip flop 22 to turn off relay R/2 unless the free game detector 12 prevents this.

The display illumination circuit 9 comprises 20 long-life filament lamps 90, one behind each card representation on the face of the machine. Each lamp 90 is driven by its own transistor 91, connected, through a resistor 92, to the outputs of the gates 80 of the memory bits.

The display cancel counter 10 includes the cancel button 100, a counter 101 and circuitry 102 for illuminating the cancel button 100. The counter 101 receives a signal each time the cancel button 100 is pressed while in its active state. When the count reaches ten, an inhibit is placed on the cancel button to prevent this facility being used any further. The cancel button is activated when a flip flop 38 is set by multiplexer 37 sensing a vacant display bit in memory 8, whenever flip flop 35 is in the set state. The setting of flip flop 38 illuminates the lamp in circuit 102 and also starts a 3 second timer 39. During this time, the button 100 may be pressed to cancel the last display, otherwise, at the time out period, an inhibit is placed on the button 100 and the lamp in circuit 102 extinguished. The number at which the cancel button is inhibited may be made more or less than ten.

Display cancellation is achieved by the display cancel decoder 11 adapted to receive a reset strobe generated by pressing the cancel button 100 while in its active state. The decoder 11 comprises two integrated circuits 111, 112 similar to circuits 70 and 71 of the set decoder. The outputs 113 from the circuits 111, 112 are connected to the second input terminals of the gates 81 in the memory 8. The outputs are controlled by the fifth address bit E and by the reset strobe.

The free game detector 12 includes two gates 120, 121, each of which is connected to four of the multiplexer inputs MI-M20. In the example, gate 120 is connected to the inputs connected to the memory bits corresponding to the four aces, while gate 121 is connected to the inputs corresponding to the four tens. It will be appreciated that other combinations of more or less than four cards may be applied to the gates 120, 121. Whenever either of these combinations is sensed by the gates, a flip flop 123 is set to illuminate free game lamp 124. In addition, the card counter is blocked to prevent the machine going into its game off state, and the flip flop 32 is set to illuminate lamp 34 in the start button and put the machine into the ready state. The flip flop 123 is reset after the start button is pressed.

The audio generator 13 comprises a tone generator 130 and an audio amplifier 131 to which a loudspeaker 132 is connected. The tone generator 130 is a simple resistance capacitance oscillator in which the audio frequency output is changed by varying the resistance to earth. Two different resistors are alternatively switched into and out of the oscillator circuit by means of a multivibrator circuit which runs at about 12Hz. In this way, the audio tone produced by the oscillator is switched between about 400 Hz and 600 Hz every 1/12 seconds. The chopped audio tone is fed via an output control circuit to the audio amplifier 131 which changes the voltage waveform to a current waveform sufficient to drive the loudspeaker 132.

For completeness of description, an example of the operation of the machine will now be described. On insertion of a disc, the microswitch 21 is closed, setting flip flop 22 and activating the relay R/2. This puts contacts R1 and R2 into the alternative position shown in the diagram to illuminate game on lamp 14 and to disconnect the flashing game sign lamps 16 and 17. The setting of flip flop 22 also removes the inhibit from start button 30. When the start button is pressed, flip flops 31 and 32 are set to initiate the timer 33 and also causing the sequential momentary lighting of lamps 90 and generation of the audio tone effect described for about five seconds, and to turn off start button lamp 34 and start the pulse generator 5. Within a few seconds of time-out of the sequential lighting and audio tone effects, the pulse generator 5 sets flip flop 35 and when the address of generator 6, which is scanning the memory 8 at the same frequency as that of pulse generator 4, detects a free memory bit, the flip flop 38 is set to halt the pulse generator 4, strobe the set decoder 7 to illuminate the lamp 90 corresponding to the memory bit, start timer 39 and illuminate cancel button 100. If the cancel button 100 is not pressed before time out of timer 39, the illuminated display is retained. If the button is pressed, the counter 101 is stepped on one count and a strobe is applied to the display cancel decoder 11 causing the set memory bit to be reset. A further pulse from the generator 5 is again stored in flip flop 35 until a free memory bit is again detected. This procedure may be repeated for a maximum of ten cancellations and until five cards are displayed whereupon the counter of generator 36 resets flip flops 32 and 22, unless a free game situation is detected, and the relay R/2 is turned off, which illuminates the game off lamp 13 and the flashing game sign lamps 16 and 17. The displays that have been retained during the game remain illuminated until a disc is inserted to set the machine in the game on state.

Referring now to FIG. 3, this self-explanatory block diagram shows an alternative form of display selection. The read only memory ROM may be programmed with between 2,500 and 5,000 display addresses in any desired order making it virtually impossible for a player to determine the order. The ROM may be mounted in a socket so that it may be removed at regular intervals and exchanged for a differently programmed ROM.

Pulse generator 1, the 5 bit address generator, the 20 bit set decoder and the 20 bit display memory may be identical to components 4, 6, 7 and 8 of the first embodiment, although the only purpose served by generator 1 and the address generator is to scan the memory for creating the momentary lighting (shuffling) effect.

The pulse generator 2 creates the pulses necessary to increment the ROM address generator which steps the ROM through its programmed display addresses in response to a function control unit (not shown). The ROM is connected to the set decoder via a control circuit that acts as a change over circuit after the sequential lighting effect is finished. As each address in the ROM is transmitted to the decoder, the corresponding bit in the display memory is set to illuminate the display as in the previous embodiment. The display cancel facility (not shown) also operates as in the first embodiment. Thus, operation of this form of the invention is the same as the first embodiment except for the above.