05/327145

02/18/1975

01/26/1973

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Princeton Applied Research Corporation (Princeton, NJ)

708/813

327/552, 327/356, 327/3

G06G7/161; G06G7/19; G06G7/00; G06G7/19; G06G7/16

235/181,194 328/127,160,133,134,167 329/50 307/232

3424990	SYNCHRONOUS DEMODULATING MEANS	January 1968	Escobosa
3428794	TIME CORRELATION COMPUTERS	February 1969	Norsworthy
3517879	DIGITAL SIGNAL CROSS-CORRELATOR	June 1970	Conway
3550023	REMODULATOR FILTER	December 1970	Vivian
3553723		January 1971	Ohnsorg
3614407	METHOD OF MULTIPLICATION OF ELECTRIC SIGNALS AND ITS APPLICATION TO RADAR OR LIKE SYSTEMS	October 1971	Fournier
3746851	MULTIPLIER, DIVIDER AND WATTMETER USING A SWITCHING CIRCUIT AND A PULSE-WIDTH AND FREQUENCY MODULATOR	July 1973	Gilbert
3774125	BAND REJECTION FILTER USING TANDEM COMMUTATING CAPACITOR UNITS	November 1973	Condon

Korn & Korn, (Textbook), Electronics Analog Computers, Multipliers and Function Generators, McGraw-Hill 1956, pages 270-275..

Gruber, Felix D.

Bain, Gilfillain & Rhodes

1. The signal correlation process with improved dynamic range for providing an indication of the time average of the product of two arbitrary signals, which process utilizes an electronic multiplier whose output signal will include DC drift and offset due to circuit imperfections in said multiplier comprising the steps of:

2. The process according to claim 1 wherein said repetitive polarity

3. The process according to claim 1 wherein said repetitive polarity

4. The process according to claim 3 wherein said predetermined polarity reversing signal is a square wave signal and wherein said predetermined

5. The process according to claim 4 wherein said square wave signals are

6. The process according to claim 1 wherein said synchronous filtering of said output signal of said electronic multiplier comprises the steps of:

7. The process according to claim 6 wherein said rotating capacitor square wave filter includes said resistor R connected in series with said capacitor C and wherein said output signal of said electronic multiplier is a voltage signal and is applied across the series connection of said

8. The process according to claim 6 wherein said rotating capacitor square wave filter includes said resistor R connected in parallel with said capacitor C and wherein said output signal of said electronic multiplier is a current signal and is applied across the parallel connection of said

9. The process according to claim 6 wherein said rotating capacitor square wave filter includes an operational amplifier connected as an inverting summing amplifier and wherein said capacitor C and resistor R are connected in parallel in the feedback network of said inverting summing amplifier and wherein said output signal of said electronic multiplier is applied to the input of said inverting summing amplifier and wherein said AC output signal appears at the output of said inverting summing

10. The process according to claim 1 wherein said synchronous rectification is accomplished by feeding said AC output signal and a predetermined signal in phase with and at the same frequency of said predetermined product signal into a switching type phase reversing multiplier wherein said signals are multiplied and whereby the output signal of said

11. The process according to claim 1 including the additional step of amplifying said AC output signal subsequent to said synchronous filtering

12. The process according to claim 1 including the additional step of passing said AC output signal through a high pass filter to further remove any DC and low frequency signals included in said AC output signal, said additional step being accomplished subsequent to said synchronous

13. The process according to claim 1 including the additional steps of amplifying said AC output signal and passing said amplified AC output signal through a high pass filter to further remove any DC and low frequency signals included in said AC output signal, said additional steps being accomplished subsequent to said synchronous filtering and prior to

14. The process according to claim 1 wherein said multiplication of said one signal repetitively reversed in polarity times the other is accomplished by phase reversal modulation and wherein one of said arbitrary signals assumes only the values of +1 or -1 and wherein said one arbitrary signal is the arbitrary signal which is multiplied with said

15. The process according to claim 1 wherein said multiplication of said one signal repetitively reversed in polarity times the other is accomplished by phase reversal modulation and wherein one of said arbitrary signals assumes only the values +1 or -1 and wherein the other of said arbitrary signals is the arbitrary signal which is multiplied with

16. The signal correlation process with improved dynamic range for providing an indication proportional to the exponentially weighted time average of characteristic time T of the product of two arbitrary signals A and B, i.e. <A × B>_T which process utilizes an electronic multiplier whose output signal will include DC drift and offset due to circuit imperfections in the electronic multiplier, comprising the steps of:

17. The process according to claim 16 wherein said repetitive polarity

18. The process according to claim 16 wherein said repetitive polarity

19. The process according to claim 16 wherein said predetermined square wave signal and said predetermined square wave product signal are

20. The process according to claim 16 wherein said rotating capacitor square wave filter includes said resistor R connected in series with said capacitor C and wherein said output signal of said electronic multiplier is a voltage signal and is applied across the series connection of said

21. The process according to claim 16 wherein said rotating capacitor square wave filter includes said resistor R connected in parallel with said capacitor C and wherein said output signal of said electronic multiplier is a current signal and is applied across the parallel

22. The process according to claim 16 wherein said rotating capacitor square wave filter includes an operational amplifier connected as an inverting summing amplifier and wherein said capacitor C and resistor R are connected in parallel in the feedback network of said inverting summing amplifier and wherein said output signal of said electronic multiplier is applied to the input of said inverting summing amplifier and wherein substantially only said predetermined square wave product signal

23. The process according to claim 16 wherein said synchronous rectification is accomplished by feeding said AC output signal and a second predetermined square wave signal in phase with and at the same frequency f_i of said predetermined square wave product signal into a switching type phase reversing multiplier wherein said signals are multiplied and whereby the output signal of said switching type hase

24. The process according to claim 16 including the additional step of amplifying said AC output signal subsequent to said synchronous filtering

25. The process according to claim 16 including the additional step of passing said AC output signal through a high pass filter to further remove any DC and low frequency signals included in said AC output signal, said additional step being accomplished subsequent to said synchronous

26. The process according to claim 16 including the additional steps of amplifying said AC output signal and passing said amplified AC output signal through a high pass filter to further remove any DC and low frequency signal included in said AC output signal, said additional steps being accomplished subsequent to said synchronous filtering and prior to

27. The process according to claim 16 wherein said multiplication of said signal B repetitively reversed in polarity times arbitrary signal A is accomplished by phase-reversal modulation and wherein arbitrary signal B

28. The process according to claim 16 wherein said multiplication of said signal B repetitively reversed in polarity times arbitrary signal A is accomplished by phase-reversal modulationand wherein arbitrary signal A

29. Signal correlator apparatus with improved dynamic range for providing an indication of the time average of the product of two arbitrary signals, which apparatus utilizes an electronic multiplier whose output signal will include DC drift and offset due to circuit imperfections in said multiplier, comprising:

30. Apparatus according to claim 29 wherein said additional multiplier means are multiplier means for providing said one signal repetitively

31. Apparatus according to claim 29 wherein said additional multiplier

32. Apparatus according to claim 31 wherein said electronic multiplier is a

33. Apparatus according to claim 31 wherein said electronic multiplier is a

34. Apparatus according to claim 33 wherein said logic multiplier is an

35. Apparatus according to claim 31 wherein said additional multiplier means further includes means for generating a square wave signal which

36. Apparatus according to claim 35 wherein said means for generating said square wave signal are means for generating a symmetrical square wave

37. Apparatus according to claim 29 wherein said synchronous filter means for filtering said output signal of said electronic multiplier comprises:

38. Apparatus according to claim 37 wherein said rotating capacitor square wave filter includes said resistor R connected in series with said capacitor C and wherein said output signal of said electronic multiplier is a voltage signal and is applied across the series connection of said

39. Apparatus according to claim 37 wherein said rotating capacitor square wave filter includes said resistor R connected in parallel with said capacitor C and wherein said output signal of said electronic multiplier is a current signal and is applied across the parallel connection of said

40. Apparatus according to claim 37 wherein said rotating capacitor square wave filter includes an operational amplifier connected as an inverting summing amplifier and wherein said capacitor C and resistor R are connected in parallel in the feedback network of said inverting summing amplifier and wherein said output signal of said electronic multiplier is applied to the input of said inverting summing amplifier and wherein substantially only said predetermined product signal appears at the output

41. Apparatus according to claim 29 wherein said synchronous rectifying means includes a signal generator for providing a predetermined square wave signal in phase with and at the same frequency of said predetermined product signal and a switching type phase reversing multiplier for receiving said AC output signal and said predetermined square wave signal

42. Apparatus according to claim 29 further including amplifying means connected intermediate said synchronous filtering means and said synchronous rectifying means and for amplifying said AC output signal.

43. Apparatus according to claim 29 further including a high pass filter connected intermediate said synchronous filtering means and said synchronous rectifying means and for further filtering said AC output signal by further removing any DC and low frequency signals included in

44. Apparatus according to claim 29 further including amplifying means and a high pass filter connected intermediate said synchronous filtering means and said synchronous rectifying means and for amplifying and further filtering said AC output signal to further remove any DC and low frequency

45. Signal correlator apparatus with improved dynamic range for providing an indication proportional to the exponentially weighted time average of characteristic time T of the product of two arbitrary signals A and B, i.e. <A × B>_T which apparatus utilizes an electronic multiplier whose output signal will include DC drift and offset due to circuit imperfections in the electronic multiplier, comprising:

46. Apparatus according to claim 45 wherein said additional multiplier means are multiplier means for providing said signal B repetitively

47. Apparatus according to claim 45 wherein said additional multiplier

48. Apparatus according to claim 47 wherein said electronic multiplier is a

49. Apparatus according to claim 47 wherein said electronic multiplier is a

50. Apparatus according to claim 49 wherein said logic multiplier is an

51. Apparatus according to claim 47 wherein said additional multiplier means further include a square wave generator for generating said

52. Apparatus according to claim 51 wherein said square wave generator is

53. Apparatus according to claim 45 wherein said rotating capacitor square wave filter includes said resistor R connected in series with said capacitor C and wherein said output signal of said electronic multiplier is a voltage signal and is applied across the series connection of said

54. Apparatus according to claim 45 wherein said rotating capacitor square wave filter includes said resistor R connected in parallel with said capacitor C and wherein said output signal of said electronic multiplier is a current signal and is applied across the parallel connection of said

55. Apparatus according to claim 45 wherein said rotating capacitor square wave filter includes an operational amplifier connected as an inverting summing amplifier and wherein said capacitor C and resistor R are connected in parallel in the feedback network of said inverting summing amplifier and wherein said output signal of said electronic multiplier is applied to the input of said inverting summing amplifier and wherein substantially only said predetermined square wave product signal appears

56. Apparatus according to claim 45 wherein said synchronous rectifying means include a square wave signal generator for providing a second predetermined square wave signal in phase with and at the same frequency f_i of said predetermined square wave product signal and a switching type phase reversing multiplier for receiving said AC output signal and said second predetermined square wave signal and for multiplying said

57. Apparatus according to claim 45 further including amplifying means connected intermediate said synchronous filtering means and said synchronous rectifying means and for amplifying said AC output signal.

58. Apparatus according to claim 45 further including a high pass filter connected intermediate said synchronous filtering means and said synchronous rectifying means and for further filtering said AC output signal by further removing any DC and low frequency signals included in

59. Apparatus according to claim 45 further including amplifying means and a high pass filter connected intermediate said synchronous filtering means and said synchronous rectifying means and for amplifying and further filtering said AC output signal to further remove any DC and low frequency

60. Apparatus according to claim 45 wherein said electronic multiplier is a

61. Apparatus according to claim 45 wherein said electronic multiplier is a switching type phase reversing modulator.

CROSS REFERENCE TO RELATED APPLICATIONS

This invention is related to the invention of U.S. Pat. No. 3,793,599, issued Feb. 19, 1974 and assigned to the same assignee as the present invention.

BACKGROUND OF THE INVENTION

The present invention relates generally to the novel signal correlators for producing the time average of the product of any two arbitrary time varying or stationary electric signals A(t) and B(t) (referred to hereinafter as A and B), the time average of the product being written <A × b> _T , the symbol <> _T indicating the exponentially weighted time average with characteristic time T.

Prior art signal correlators have limited dynamic range due to their use of electronic multipliers whose output signal includes, inherently, DC drift and offset due to circuit imperfections in the electronic multipliers, such DC drift and offset being due to the sensitivity of the electronic multiplier components to temperature, humidity and very large signals. Such DC drift and offset, as known to those skilled in the art, severely limits the dynamic range of the signal correlators and hence places a floor on the minimum value of <A × B> _T that can be decerned in prior art signal correlators.

By "dynamic range" is meant, with regard to any two-part input device whose output reading is a measure of the correlation of two input signals applied to the two input ports, the ratio of:

1. that output reading of the device (even though the device may be incapable of producing such output reading) which would correspond to input signals applied to each input port with each signal having an amplitude verging on overload and wherein in fact such signals are fully correlated,

to

2. that output reading of the device which would correspond to input signals applied to each input port with each signal having an amplitude verging on overload and wherein in fact such signals are completely uncorrelated.

SUMMARY

The signal correlator of the present invention has improved dynamic range due to the utilization of novel signal multiplication techniques and novel square wave filtering techniques.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of typical prior art electronic signal multiplication process and apparatus;

FIG. 2 is a diagrammatic presentation of the process of an apparatus for electronically multiplying arbitrary signals in accordance with the present invention;

FIGS. 3 and 4, are diagrammatic presentations of process of and apparatus for electronically multiplying arbitrary signals in accordance with the present invention wherein one of the arbitrary signals assumes only the logic values of +1 or -1;

FIGS. 5-8 illustrate various embodiments of rotating capacitor square wave filters;

FIG. 9 illustrates a cascade of rotating capacitor square wave filters;

FIG. 10 illustrates a manner in which a DC indication of amplitude of a filtered square wave signal can be provided; and

FIGS. 11 and 12 illustrate various utilizations of the rotating capacitor square wave filter of the present invention; and

FIGS. 13 and 14 are signal correlators according to the present invention.

DESCRIPTION OF THE INVENTION

Referring to the prior art and to FIG. 1, arbitrary signals A and B are fed into and electronically multiplied by an electronic multiplier M1 to provide the signal product (A × B) in the output signal of the electronic multiplier M1, however, as noted above, due to circuit imperfections in the electronic multiplier M1 the output signal of the electronic multiplier will also include DC drift and offset adversely affecting the signal product (A × B). As is known to those skilled in the art, the output signal of the electronic multiplier M1 may be fed into indicating means for providing an indication of the signal product (A × B), or the time average of the signal product, e.g. the DC amplifier and low-pass filter and DC indicating means shown in FIG. 1; alternatively, the output signal of the electronic multiplier M1 may be fed into signal product (A × B) utilization means, e.g. a servo motor. As noted above, the DC drift and offset inherently present in the output signal of the electronic multiplier M1 will adversely affect both the indication of the signal product (A × B) or the utilization of the signal product (A × B).

Referring now to FIG. 2 and to the process of and apparatus for electronically multiplying arbitrary signals in accordance with the present invention, there are shown an electronic multiplier M1, which may be for example any one of several four-quadrant linear electronic multipliers known to the art; an electronic multiplier or modulator M2, which may be for example any one of several switching type phase reversing multipliers known to the art; a polarity reversing signal generator 9, which may be for example any one of several square wave signal generators known to the art; and signal product indicating or utilization means 12, which may be for example an AC servo motor or an RC high pass filter and synchronous rectifier.

More particularly, prior to electronically multiplying the arbitrary signals A and B in the electronic multiplier M1, either one of the arbitrary signals, e.g., arbitrary signal B, is fed into the switching type phase reversing electronic multiplier M2 where it is multiplied by the predetermined polarity reversing signals S which signal S, as shown in FIG. 2, is also fed into the electronic multiplier M2. The effect of feeding arbitrary signal B and polarity reversing signal S into the electronic multiplier M2 is to provide at the output of the electronic multiplier M2 arbitrary signal B repetitively reversed in polarity in accordance with the sign of the predetermined polarity reversing signal S; signal B repetitively reversed in polarity in accordance with the sign of polarity reversing signal S being represented by the symbolization B S.

Signal B repetitively reversed in polarity and signal A are fed into electronic multiplier M1 where they are electronically multiplied to provide the product of the signals in the form of a predetermined product signal repetitively reversed in polarity in accordance with the sign of the polarity reversing signal S; this product signal is designated by the symbolization (A × B) S. The output signal of the electronic multiplier M1 will be comprised of the product signal (A × B) S and the DC drift and offset which will be present in the output signal of the electronic multiplier M1 due to circuit imperfections in the electronic multiplier M1; the output signal of the electronic multiplier including the product signal (A × B) S and DC drift and offset is shown graphically in the upper righthand portion of FIG. 2. In accordance with the teaching of the present invention, it will be understood that the peak-to-peak amplitude of the product signal (A × B) S will be proportional substantially only to the actual product of the signals (A × B) and will be substantially independent of the DC drift and offset present in the output signal of the electronic multiplier M1.

The output signal of the electronic multiplier M1 shown in the upper-right hand portion of FIG. 2 has utility directly, for example, such signal may be used to directly drive an AC servo motor whose reference winding is driven in accordance with the polarity reversing signal S whereupon the output torque of the AC servo motor will be proportional directly to the signal product (A × B) and will be substantially independent of the DC drift and offset; alternately, the output signal of the electronic multiplier M1 may be passed through an RC high pass filter and fed into a synchronous rectifier driven in accordance with the polarity reversing signal S to provide a DC signal which will be the product (A × B) substantially without the DC offset and drift. It will be understood by those skilled in the art that such AC servo motor and RC high pass filter and synchronous rectifier are merely two specific examples of the signal product indicating or utilization means 12 shown in FIG. 2, and that many other signal product indicating or utilization means may directly utilize the output signal of the electronic multiplier M1.

It will be understood by those skilled in the signal multiplication art, that in accordance with the present invention, the repetitive polarity reversal of signal B as taught with regard to FIG. 2 may be done either periodically or aperiodically in accordance with the periodicity characteristic of the polarity reversing signal S. Further, it will be understood that the polarity reversing signal S may be, for example, a square wave signal which may be either symmetrical or non-symmetrical.

Further, it will be understood that the product signal (A × B) S will be repetitively polarity reversed periodically or aperiodically in accordance with the periodicity characteristic of the polarity reversing signal S, and, where the polarity reversing signal S is a square wave signal, the product signal (A × B) S will be either a symmetrical or non-symmetrical signal in accordance with the symmetrical or non-symmetrical characteristic of the square wave polarity reversing signal S.

A still more specific understanding of the present invention may be provided by a description of a specific embodiment of the diagrammatic presentation shown in FIG. 2 wherein the polarity reversing signal S was a symmetrical square wave signal of arbitrary frequency f ₁ (arbitrary in the sense that it is not related to the frequency of either arbitrary signal A not necessarily B), and wherein the electronic multiplier M1 was a four-quadrant electronic multiplier, and wherein the electronic multiplier M2 was a phase-reversing switching type modulator or multiplier. In such specific embodiment, arbitrary signal B will have its polarity repetitively reversed at the frequency f ₁ , i.e. the arbitrary frequency of the polarity reversing signal S, and in this instance the output of the electronic multiplier M2 may be represented by the symbolization B f _i which represents symbolically arbitrary signal B repetitively polarity reversed at frequency f _i . Consequently, the output signal of the four-quadrant linear electronic multiplier M1 will also be repetitively polarity reversed at the frequency f _i , and hence, the output product signal of electronic multiplier M1 may be represented by the symbolization (A × B) f _i which symbol represents the product (A × B) repetitively polarity reversed at frequency f _i . In such instance, a frequency translation has been effected with the information of interest, product of signal A times B, (A × B), appearing at the frequency f _i and odd harmonics thereof. DC drift and offset present in the output of electronic multiplier M1 due to the circuit imperfections therein will still appear, of course, in its output signal but such DC drift and offset will not have been translated to the new frequencies, f _i , 3f _i , 5f _i , (2n + 1)f _i , . . . . What has in effect been accomplished is similar to what happens in superhetrodyne circuits, except that in the present case there are no image responses and the "intermediate frequency" is not a single frequency but instead is a multiplicity of frequencies (2n + 1)f _i , wherein n is the sequence of non-negative integers.

It will be understood by those skilled in the art that wherein in the practice of the present invention the polarity reversing signal S is a square wave signal of frequency f _i , the signal product indicating or utilization means 12, such as for example the above-noted AC servo motor and RC high pass filter and synchronous rectifier, would be driven or operated at the frequency f _i , i.e. the frequency of the polarity reversing signal S.

A still further understanding of arbitrary signal multiplication in accordance with the present invention is presented as follows: two arbitrary signals are multiplied in an electronic multiplier to obtain their product independent of DC drift and offset present in the output signal in the electronic multiplier due to circuit imperfections in the electronic multiplier by (i) multiplying the signals in an electronic multiplier to obtain a first product; (ii) reversing the polarity of one of the signals and multiplying the signal of reversed polarity times the other signal in the electronic multiplier to obtain a second product; (iii) subtracting the second product from the first product to obtain their difference; and (iv) taking one half of the difference whereby the product of the signals is provided independent of the DC drift and offset. It will be understood by those skilled in the art that such signal multiplication may be accomplished in an electronic multiplier such as a linear multiplier as shown in FIG. 2, that the subtraction of the second product from the first product may be performed electronically in any one of several signal subtracting circuits, or manually, and that one half of the difference of the product may be accomplished electronically in any one of several electronic circuits such as for example any one of several signal averaging circuits, or such one half difference may be accomplished manually. Referring now to FIGS. 3 and 4, there are shown further embodiments of arbitrary signal multiplication in accordance with the present invention which further embodiments are particularly useful wherein one of the arbitrary signals is a square wave signal at arbitrary frequency f _r which assumes only values of +1 or -1, a situation commonly found in signal multiplication situations, e.g. signal multiplication situations as are present in phase sensitive detectors, lock-in amplifiers, vector voltmeters, etc.

In the embodiments of FIGS. 3 and 4, the linear multiplier M1 of FIG. 2 is replaced with a switching type phase reversing multiplier or modulator M3 (FIG. 3) and M6 (FIG. 4), such switching type phase reversing modulators or multipliers being less expensive and having inherently greater dynamic range than linear multipliers.

In the embodiment of FIG. 3, square wave signal B of arbitrary frequency f _r and the polarity reversing signal S are fed into a suitable logic multiplier M4 (e.g. an "exclusive-or circuit" known to the logic signal multiplication art) to provide signal B repetitively polarity reversed in accordance with the sign of the predetermined polarity reversing signal S. Signal B, repetitively polarity reversed, and signal A are then fed into the switching type phase reversing multiplier or modulator M3 to provide the product (A × B) in the form of the product signal (A × B) S as shown graphically in the upper righthand portion of FIG. 2. As with the output signal of the linear multiplier M1 of FIG. 2, the output signal of switching type phase reversing modulator M3 will include both the product signal (A × B) S and the DC drift and offset inherent in the output signal of multiplier M3 due to circuit imperfections therein; the output signal of the switching type phase reversing modulator M3 being the same as shown graphically in the upper righthand portion of FIG. 2 for the output signal of linear multiplier M1 of FIG. 2.

Referring now specifically to FIG. 4, in the embodiment of FIG. 4, arbitrary signal A and the polarity reversing signal S are fed into the switching type phase reversing modulator M5 to provide signal A repetitively polarity reversed in accordance with the sign of the polarity reversing signal S. Signal A, repetitively polarity reversed, and signal B, the square wave signal of arbitrary frequency f _r assuming only logic values +1 or -1, are fed into the switching type phase reversing modulator M6 to provide the product (A × B) in the form of the product signal (A × B) S repetitively polarity reversed in accordance with the sign of the polarity reversing signal S; similarly, with regard to the embodiments of FIGS. 2 and 3, the output signal of the switching type phase reversing modulator M6 will include the product signal (A × B) S and the DC drift and offset and the peak-to-peak amplitude of the product signal (A × B) will be proportional substantially only to the actual product (A × B) and will be substantially independent of the DC drift and offset.

It will be understood by those skilled in the art that other than the specific differences taught with regard to the embodiments of FIGS. 3 and 4, the embodiments shown in FIGS. 3 and 4 operate the same as the embodiments shown and described in FIG. 2 with regard to the multiplication of the signals A and B, and that the signal product indication or utilization with regard to the embodiments of FIGS. 3 and 4 is the same as that taught with regard to the embodiment of FIG. 2.

Referring generally to FIGS. 5-8, there are shown various apparatus for practicing the processes of the present invention for filtering a square wave signal out of a composite signal including the square wave signal and other unwanted signals such as other AC signals, DC, noise, etc. Still further generally, it will be noted that each apparatus includes a capacitor C and an electrically associated resistor R which will be treated in detail below.

With regard to the apparatus of FIG. 5, such apparatus is provided with an input and output as shown and includes resistor R connected in series with capacitor C which is connected to terminals T1 and T2 through a double pole double throw (DDT) switch which upon being operated alternately reverses the connection of the capacitor C to the terminals T1 and T2l such apparatus being disclosed in the prior art by Y. Sun, Network Functions of Quadrature N-Path Filters, IEEE Trans. Circuit Theory, Vol. CT-17, pp. 594-600, Novemeber 1970, and such apparatus being disclosed as having a small response at zero frequency and a response peak at the frequency fs, the frequency at which the DPDT switch is operated. However, and in accordance with the teachings of the present invention, it has been discovered that the apparatus of FIG. 5 is unexpectedly useful for filtering a square wave signal of frequency f _i out of a composite signal including the square wave signal and other signals, and it has been further discovered that such apparatus has, in fact, ideal characteristics as a matched, narrow band filter for filtering a symmetrical, zero median square wave signal at frequency f _i out of such composite signal.

Referring now to FIG. 6, the symbolization of the DPDT switch is replaced by a symbolization ##SPC1##

that more graphically illustrates the action of the capacitor C having its connection to the terminals T1 and T2 reversed or commutated. Capacitor C may thus be visualized or understood as being commutated, reversed or switched at a frequency f _i between the terminals T1 and T2 with the switching operation being considered to be instantaneous. Such capacitor being referred to hereinafter as a "rotating capacitor" of frequency f _i , the capacitor being carried through a full cycle of reversal or rotation in a time = 1/i f _i . However, it will be further understood that the expression "rotating capacitor" is also used to include such embodiments as the capacitor C of FIG. 5 and well as any other embodiment of such capacitor C for having its connection to a pair of terminals, such as terminals T1 and T2 reversed. The reversal of the connection of the rotating capacitor C at frequency f _i may be accomplished mechanically such as by the DPDT switch of FIG. 5, by a motor, or electrically such as by solid state switches operated at frequency f _i ; such reversing means not being shown in FIGS. 6 and 7.

Shown in FIG. 7 is an embodiment wherein the resistor R is electrically associated with the rotating capacitor C by being connected in parallel with the rotating capacitor; the means for reversing or commutating the capacitor C not being shown.

The apparatus of FIGS. 5 and 6, wherein resistor R is connected in series with rotating capacitor C, are for receiving the composite signal in the form of a voltage signal; and, the apparatus of FIG. 7 is for receiving the composite signal in the form of a current signal.

Referring now to FIG. 8 there is shown novel apparatus utilizing the rotating capacitor and which novel apparatus is particularly useful in practicing the filtering processes of the present invention. Shown in FIG. 8 is an operational amplifier A, which may be any one of several suitable operational amplifiers known to the art, an input resistor R1 and an amplifier feed-back network including resistor R and rotating capacitor C connected in parallel as shown in FIG. 8. The operational amplifier A is connected as an inverting summing amplifier and is provided with inputs and outputs as shown. Also shown schematically in FIG. 8 are suitable means for reversing or commutating rotating capacitor C at frequency f _i , such as for example, a suitable solid state switch or switches referred to above.

It will be further understood by those skilled in the art that the apparatus included in the dash rectangular outline shown in FIGS. 5-8, and given general numerical designation 10, is referred to hereinafter as a "rotating capacitor square wave signal filter."

Referring now specifically to the practice of the processes of the present invention as may be practiced by each of the rotating capacitor square wave signal filters of FIGS. 5-8 for filtering a zero median value square wave signal having known transitions, i.e., a zero median value square wave signal of known phase and frequency and which known frequency will be referred to as frequency f _i , out of a composite signal including such square wave signal and other signals, such as other AC signals, other AC signals and DC, noise, etc., such composite signal is applied to the input of such rotating capacitor square wave signal filter and the connection of the rotating capacitor C is repetitively reversed to the terminals T1 and T2 in synchronism with the transitions of the square wave signal to be filtered, i.e., the rotating capacitor C has its connection to the terminals T1 and T2 reversed in phase with and at the frequency f _i of the square wave signal to be filtered out of the composite signal. The rotating capacitor C and its electrically associated resistor R are chosen such that their RC time constant is much greater than the period of the square wave signal to be filtered, hence, substantially only the median value square wave signal will appear or be provided across the output of the rotating capacitor square wave signal filters; the other signals of the composite signal, in particular DC, being rejected or attenuated and substantially not passing through said rotating capacitor square wave filter. More particularly, in the rotating capacitor square wave filters 10 of FIGS. 5-7, the filtered square wave signal will appear across the terminals T1 and T2 to which the output of the filters is connected, and in the rotating capacitor square wave filter 10 of FIG. 8 the filtered square wave signal will appear across the output of the inverting summing amplifier.

Referring again specifically to FIG. 8, the filtered square wave signal provided at the output of the inverting summing amplifier will be amplified by a factor equal to the resistor ratio, R/R1. The "band-width" of the rotating capacitor square wave filter of FIG. 8 is proportional to 1/RC, and is best described as a synchronous matched filter for zero median value square waves, especially, symmetrical square waves of zero median value.

It will be understood further with regard to the practice of the above-described processes of the present invention as practiced by the rotating capacitor square wave signal filters of FIG. 5-8 that where the zero median value square wave signal to be filtered is a symmetrical square wave and where the other signals of said composite signal are other AC signals and/or DC signals, substantially only the symmetrical square wave signal appears or is provided at the output of the filter; that where the zero median value square wave signal is a non-symmetrical square wave signal and where the other signals of the composite signal are other AC signals, substantially only the non-symmetrical square wave signal appears or is provided at the output of the filter; and that where the zero median value square wave signal is a non-symmetrical square wave and the other signals are other AC signals and DC signal, substantially only said non-symmetrical square wave signal and portions of said DC signal appear or are provided at the output of the filter.

In accordance with the further teachings of the present invention, it has been found that sharper response characteristics can be achieved by cascading two or more rotating capacitor square wave filters 10, operated in synchronism at frequency f _i , as illustrated in FIG. 9.

APPLICATIONS OF ROTATING CAPACITOR SQUARE WAVE FILTERS

It will be understood by those skilled in the art that the above-described rotating capacitor square wave filters will have numerous applications in instrumentation and communication electronic circuitry.

For example, the measurement of small amplitude square wave signals of known frequency and phase in the presence of large amplitude noise can be accomplished advantageously by combining the rotating capacitor square wave filter 10, of FIGS. 5-8 with a synchronous rectifier or detector such as a switching type phase reversing multiplier or demodulator M1 as shown in FIG. 10, the rotating capacitor square wave filter 10 of FIG. 8 being actually shown in FIG. 9, however, it will be understood that the rotating capacitor square wave filters 10 of FIGS. 5-7 could also be combined with the multiplier M1 of FIG. 10. The multiplier M1, or synchronous rectifier or demodulator, is operated in synchronism with the transitions of the filtered square wave signal and the reversing of the rotating capacitor C. More specifically, the multiplier M1 may receive the filtered square wave signal and a square wave signal in phase with and at the frequency f _i of the filtered square wave signal, which may be provided by a suitable square wave generator 14 (which generator may also be used to operate the means for reversing or commutating the rotating capacitor C as shown), and the phase-reversing switching type multiplier M1 will multiply or synchronously rectify or demodulate, the received square wave signals and provide a DC signal which will be proportional to the amplitude of the filtered square wave signal. Such DC signal may be indicated by suitable DC indicating means such as the DC meter shown. With regard to such DC signal being "proportional" to the magnitude of the filtered square wave signal, if the gain of the filter, e.g. the ratio of R/R1, is one, the DC signal will be equal to, or substantially equal to, one-half of the peak-to-peak amplitude of the filtered square wave signal of zero median value.

It will be further understood by those skilled in the art that the apparatus of FIG. 10 will be optimally responsive to symmetrical square wave synchronous with the frequency f _i . The response to input noise and off-frequency (not f _i ) coherent signals can be made arbitrarily small by reducing the bandwidth (1/RC) of the rotating capacitor square wave filter, i.e. by increasing the RC time constant. Because the signals of interest at point Q in FIG. 9 are zero median square wave signals of frequency f _i , and have been bandwidth limited to an arbitrary degree by the rotating capacitor square wave filter 10, the utility of the circuit of FIG. 10 may be advantageously enhanced by the addition of AC amplification means, such as a suitable AC amplifier A1, and/or suitable high pass filtering means C2-R2 such as shown in FIG. 11, wherein such AC amplifier and/or high pass filter are connected intermediate the output of the rotating capacitor square wave filter 10 and the synchronous rectifier or phase reversing switching type multiplier M1. The high pass filter, C2-R2, further removes any DC and low frequency signals included in the filtered composite signal prior to synchronous rectification by the multiplier M1, and prevents DC drifts and offsets from the operational amplifier A and AC amplifier A1 from being converted into square waves at the frequency f _i by the multiplier, modulator, or synchronous rectifier, M1.

It will be further understood by those skilled in the art that the apparatus or circuit of FIG. 11 is particularly useful for band limiting, detecting and measuring the amplitude of a small square wave signal in the presence of large noise. Further, because of the noise-rejecting properties of the rotating capacitor square wave filter 10, the dynamic range requirements on the additional amplification means, e.g. AC amplifier A1, are greatly reduced.

A further application of the rotating capacitor filter 10 is in a carrier-type DC and low frequency amplifier as shown in FIG. 12. The circuit of FIG. 12 is the same as that shown in FIG. 11 except that a phase reversing switching type modulator, or multiplier, M2 has been added prior to the input of the rotating capacitor square wave filter 10.

The apparatus or circuit of FIG. 12 has been found to be particularly useful in amplifying only the, or substantially only the, DC and low frequency signals found in a composite signal including such DC and low frequency signals and high frequency signals. Such composite signal is applied to the input of the circuit whereupon the composite signal is modulated by modulator M2 by being repetitively reversed in polarity in accordance with the sign of a square wave signal of frequency f _i wherein the frequency f _i is less than the period of the low frequency signals. The composite signal is then fed into the rotating capacitor square wave filter 10 and the balance of the circuit operates and functions as taught above with regard to the application circuit shown in FIG. 11.

The RC time constant is made much greater than the period of the square wave signal f _i and is made less than the period of the low frequency signals to be amplified. The frequency response of the circuit of FIG. 12 is flat from DC out to a frequency f _c = 1/2πRC where it will begin to fall off at approximately 6 db. per octave. There are no spurious responses for input frequencies at or near frequency f _i , nor for any frequency whatsoever.

SIGNAL CORRELATOR OF IMPROVED DYNAMIC RANGE

The signal correlator of improved dynamic range is provided by the unique combinations of the signal multiplication processes and apparatus taught above with regard to FIGS. 1-4, and the square wave filtering processes and apparatus taught above with regard to FIGS. 5-12, as illustrated by way of specific example in FIG. 13.

The signal multiplication section 14, depending upon whether the signals A and B are both arbitrary, or whether one of the signals assumes only the value +1 or -1 otherwise arbitrary, may be any one of the signal multiplication circuits of FIGS. 2-4, with the embodiment of FIG. 2 being shown specifically in FIG. 13; such circuits operating as taught above. Similarly, the square wave filtering section 10 may be any one of the embodiments 10 of FIGS. 5-9, with such circuits operating as taught above. Similarly, the balance of the signal correlator shown in FIG. 13 may be the same as the balance of the circuit of FIG. 11 after the initial square wave filter portion, and will operate in the same manner to provide the DC signal indication or output.

The output of the signal correlator of FIG. 13 will be a DC voltage proportional to the exponentially weighted time average of the product of the arbitrary input signals A and B, with the averaging time T equal to the time constant RC of the rotating capacitor C and its electrically associated resistor R.

A hybrid analogue-digital circuit for accomplishing the square wave filtering and synchronous detection means is shown in FIG. 14. It is similar to that described in the literature by Morris and Johnston, E. D. Morris and Harold S. Johnston, Digital Phase Sensitive Detector, RSI 39, p. 620 (1968). The novel signal multiplication technique is combined with a voltage to frequency converter and an up/down counter, operated at frequency f _i , to accomplish the detection of the square wave from the multiplier M1.

It will be understood by those skilled in the art that many modifications may be made in the present invention without departing from the spirit and scope thereof.