Title:
PROGRAMMABLE CALCULATOR
United States Patent 3859635


Abstract:
A modular read-write and read-only memory unit capable of employing both direct and indirect decimal and symbolic addressing, a central processing unit capable of performing both serial binary and parallel binary-coded-decimal direct and indirect memory register arithmetic, and an input-output control unit capable of bidirectionally transferring information between the central processing unit and a number of input and output units are controlled by a microprocessor included in the central processing unit. The input and output units include a keyboard input unit with a section capable of being defined by plug-in read-only memory modules and stored programs added by the user, a magnetic card reading and recording unit capable of bidirectionally transferring information between an external magnetic card and the calculator, and a solid state output display unit capable of displaying three lines of numeric information. An output printer unit capable of printing out every alphabetic and numeric character and many other symbols individually and in messages may also be included with the other input and output units. The memory, central processing, input-output control, input, and output units are employed to provide an adaptable programmable calculator that may be operated manually by the user from the keyboard input unit or automatically by a program stored in the memory unit. This calculator may also be employed to load programs into the memory unit from the keyboard input unit, to separately transfer either data or programs bidirectionally between the memory unit and an external magnetic card, to code programs stored in the memory unit as being secure when they are transferred to an external magnetic card and thereby prevent users of the calculator from re-transferring them to an external magnetic card or obtaining any indication of the individual program steps once they are reloaded into the calculator, to edit programs stored in the memory unit and to print out keystroke logs, program lists, labels, and messages. The read-write memory available to the user may be expanded by the addition of program storage memory modules or by the alteration of the data storage memory control.



Inventors:
Watson, Robert E. (Loveland, CO)
Walden, Jack M. (Loveland, CO)
Near, Charles W. (Loveland, CO)
Application Number:
05/153437
Publication Date:
01/07/1975
Filing Date:
06/15/1971
Assignee:
WATSON; ROBERT E.
WALDEN; JACK M.
NEAR; CHARLES W.
Primary Class:
International Classes:
G06F15/02; (IPC1-7): G06F15/02
Field of Search:
340/172.5
View Patent Images:



Other References:

Burroughs Series L2000 Electronic Billing Computer - Jan. 1969. .
Burroughs TC500 Operation and Programming Manual - Feb. 1969, pages 5, 56, 57, 6, 61..
Primary Examiner:
Shaw, Gareth D.
Assistant Examiner:
Nusbaum, Mark Edward
Attorney, Agent or Firm:
Griffin, Roland I.
Claims:
We claim

1. An electronic desk type calculator, portable calculator, or the like including an input unit for entering information into the calculator, a basic first memory unit into which information may be written and from which information may be read, a basic second memory unit for storing routines and/or subroutines to be executed by the calculator in performing selected functions, plug-in adaptor means for enabling the user to removably plug one or more additional second memory units for storing routines and/or subroutines to be executed by the calculator in performing additional selected functions into the calculator to increase the number of functions that may be performed by the calculator, processing means responsive to information from the input unit or the basic first memory unit and to operating states within the calculator itself for selectively executing one or more of the routine and/or subroutines stored in the basic second memory unit to perform one or more of the selected functions employing information from one or both of the input and basic first memory units, said processing means being further responsive to information from the input unit or the basic first memory unit and to operating states within the calculator itself when an additional second memory unit is plugged into the calculator for selectively executing one or more of the routines and/or subroutines stored in that additional second memory unit to perform one or more of the additional selected functions employing information from one or both of the input and basic first memory units, and an output unit for providing an output indication of the results of the selected and additional selected functions performed by the calculator.

2. An electronic calculator as in claim 1 wherein said basic first memory unit comprises a first section for storing data and a separate second section for storing program steps, and said first and second sections of the basic first memory unit may be separately internally expanded to increase the data and program-step storage capacity of the basic first memory unit.

3. An electronic calculator as in claim 1 wherein said basic first memory unit is a read-write memory, and each of said basic and additional second memory units is a read-only memory.

4. An electronic calculator as in claim 1 wherein said calculator includes one or more receptacles into said calculator and additional second memory units include electrical connection means for electrically connecting the calculator and each of the additional second memory units plugged into one of the receptacles in the calculator, said plug-in adaptor means including the receptacles in the calculator and the electrical connection means, and said processing means includes means for detecting either the presence or the absence of each additional second memory unit plugged into one of the receptacles in the calculator.

5. An electronic calculator as in claim 4 wherein said processing means includes addressing means coupled to the basic first and second memory units and to the electrical connection means for addressing the basic first and second memory units and each of the additional second memory units plugged into one of the receptacles in the calculator, and accessing means coupled to the basic first and second memory units and to the electrical connection means for accessing the basic first and second memory units and each of the additional second memory units plugged into one of the receptacles in the calculator.

6. An electronic calculator as in claim 5 wherein said electrical connection means comprises an electrical connector on each of the additional second memory units and a mating electrical connector in each of the receptacles in the calculator, said addressing means comprises a memory address register and a first bus system for coupling the memory address register to the basic first and second memory units and to the electrical connector in each of the receptacles in the calculator, and said accessing means comprises a memory access register and a second bus system for coupling the memory access register to the basic first and second memory units and to the electrical connector in each of the receptacles in the calculator.

7. An electronic calculator as in claim 6 wherein said basic first memory unit is a read-write memory, and each of said basic and additional second memory units is a read-only memory.

8. An electronic calculator as in claim 6 wherein said input unit is a keyboard input unit including a first plurality of keys for enabling the user to manually initiate the basic functions that may be performed by the calculator without an additional second memory unit, and a second plurality of keys employed alone or with one or more of the first plurality of keys for enabling the user to manually initiate the added functions that may be performed by the calculator when each of the additional second memory units is plugged into one of the receptacles in the calculator.

9. An electronic calculator as in claim 8 wherein said basic first memory unit is a read-write memory, and each of said basic and additional second memory units is a read-only memory.

10. An electronic calculator as in claim 8 including a keyboard overlay for designating the added functions that may be initiated by the second plurality of keys when one of the additional second memory units is plugged into one of the receptacles in the calculator.

11. An electronic calculator as in claim 1 wherein said input unit is a keyboard input unit including a first plurality of keys for enabling the user to manually initiate the basic functions that may be performed by the calculator without an additional second memory unit, and a second plurality of keys employed alone or with one or more of the first plurality of keys for enabling the user to manually initiate the added functions that may be performed by the calculator when each of the additional second memory units is plugged into one of the receptacles in the calculator.

12. An electronic calculator as in claim 11 including a keyboard overlay for designating the added functions that may be initiated by the second plurality of keys when one of the additional second memory units is plugged into one of the receptacles in the calculator.

13. An electronic caluclator as in claim 1 wherein said calculator includes adaptor means for accommodating one or more additional first memory units to internally expand the storage capacity of the basic first memory unit.

14. An electronic calculator as in claim 13 wherein said basic first memory unit includes a first section for storing data and a separate second section for storing program steps, and said adaptor means is operable for accommodating the additional first memory units to separately, internally expand the data and program-step storage capacity of the first and second sections of the basic first memory unit.

15. An electronic calculator as in claim 14 wherein said processing means includes addressing means coupled to the basic first and second memory units and to the adaptor means for addressing the basic first and second memory units and each added first memory unit, and accessing means coupled to the basic first and second memory units and to the adaptor means for accessing the basic first and second memory units and each added first memory unit.

16. An electronic calculator as in claim 15 wherein said addressing means comprises a memory address register and a first bus system for coupling the memory address register to the basic first and second memory units and to one or more electrical connectors of the adaptor means, and said accessing means comprises a memory access register and a second bus system for coupling the memory access register to the basic first and second memory units and to the electrical connectors of the adaptor means.

17. An electronic calculator as in claim 16 wherein said basic first memory unit is a read-write memory, and each of said basic and additional second memory units is a read-only memory.

Description:
BACKGROUND OF THE INVENTION

This invention relates generally to calculators and improvements therein and more particularly to programmable calculators that may be controlled both manually from the keyboard input unit and automatically by a stored program loaded into the calculator from the keyboard input unit or an external record member.

Conventional programmable calculators generally have less capability and flexibility than is required to meet the needs of many users. For example, they typically cannot be readily expanded and adapted by the user to separately increase the amount of program and data storage memory or to perform special keyboard functions oriented toward the environment of the user. They also typically cannot perform indirectly addressed numeric data register transfers and arithmetic without utilizing available working registers for addresses rather than data. This seriously limits their ability to efficiently perform complex operations such as file manipulations or matrix arithmetic. Moreover, they typically have a very limited capability for performing direct arithmetic between working and storage memory registers and little or no capability for performing indirect arithmetic between working and storage memory registers.

In some conventional programmable calculators a program stored within the calculator can be recorded onto an external magnetic record member and can later be reloaded back into the calculator from the magnetic record member. However, data and programs stored within these calculators typically cannot be separately recorded onto an external magnetic record member and later separately reloaded back into the calculator therefrom. Moreover, these calculators have no provision for making a program secure when it is recorded onto an external magnetic record member. Any user may therefore re-record the program or obtain an indication of the individual program steps once the program is reloaded into the calculator.

Conventional programmable calculators with self-contained output printer units typically have a very limited alpha capability of only a few selected characters confined to certain columns of the printer. They are therefore typically unable to print out both a numeric and a distinct mnemonic representation of every program step of every program stored within the calculator. Furthermore, they are typically unable to print out labels for inputs to and outputs from the calculator or messages informing the user how to run programs with which he may be unfamiliar. Such features would be very helpful to the user both in editing programs and in simplifying their use.

In some conventional programmable calculators a program stored within the calculator may be edited by single stepping forward through the program while viewing an output display representing the last-encountered program step and its associated address and, in one case, also the presently-encountered program step and its associated address. However, these calculators typically cannot single step backward through the program or display the next program step to be encountered and its associated address. Moreover, they typically have no provision for inserting program steps into the program without reloading portions of the program and no provision for finding every occurrence of any designated program step. Such features would also be very helpful to the user in editing programs.

Conventional computer systems have or may be programmed to have much more capability than conventional programmable calculators. However, they are larger, more expensive, and less efficient in calculating elementary mathematical functions than conventional programmable calculators. Moreover, a skilled programmer is typically required to utilize them. Due to these factors, conventional computer systems are best suited for handling large amounts of data or making highly iterative or very complex mathematical calculations.

SUMMARY OF THE INVENTION

The principal object of this invention is to provide an improved programmable calculator that has more capability and flexibility than conventional programmable calculators and that is smaller, less expensive, more efficient in calculating elementary mathematical functions, and easier to utilize than conventional computer systems.

Another object of this invention is to provide a programmable calculator in which the amount of program and data storage memory available to the user may be separately expanded and in which additional program and data storage memory made available to the user is automatically accommodated by the calculator and the user informed when he has exceeded the capacity of either the program or data storage memory.

Another object of this invention is to provide a programmable calculator in which the functions performed by the calculator may be readily expanded by the user and oriented toward the environment of the user and in which the added functions are automatically accommodated by the calculator.

Another object of this invention is to provide a programmable calculator in which the user may define keyboard functions to be performed by the calculator and may protect them from subsequently being inadvertently altered or destroyed.

Another object of this invention is to provide a programmable calculator capable of employing extensive indirect addressing to permit efficient manipulation of files and matrix operations.

Another object of this invention is to provide a programmable calculator in which the user may employ either absolute or symbolic addressing and in which program jumps or subroutine calls may be made to absolute or symbolic addresses.

Another object of this invention is to provide a programmable calculator capable of performing both direct and indirect storage, recall, and exchange between working and storage memory registers.

Another object of this invention is to provide a programmable calculator capable of performing both direct and indirect arithmetic bidirectionally between working and storage memory registers.

Another object of this invention is to provide a programmable calculator capable of performing serial binary arithmetic, parallel-by-digit binary-coded-decimal arithmetic, and logic operations.

Another object of this invention is to provide a programmable calculator in which either programs or data stored within the calculator may be separately recorded on an external magnetic record member and, subsequently, separately reloaded back into the calculator therefrom.

Another object of this invention is to provide a programmable calculator in which the user may designate any program stored within the calculator as being secure when it is recorded onto an external magnetic record member for subsequent re-entry into the calculator and in which the user is prevented from re-recording any secure program or obtaining any indication of its individual program steps once it is reloaded into the calculator.

Another object of this invention is to provide a programmable calculator capable of printing out every alphabetic and numeric character and many other symbols individually and in messages.

Another object of this invention is to provide a programmable calculator capable of printing out both a numeric and a mnemonic representation of each keyboard entry in a key-log listing.

Another object of this invention is to provide a programmable calculator capable of printing out a numeric representation of each numeric keyboard entry and calculated numeric result and a mark distinguishing each numeric keyboard entry from each calculated numeric result.

Another object of this invention is to provide a programmable calculator capable of printing out both a numeric and mnemonic representation of each step in a program stored within the calculator and a numeric indication of the address of each program step in a program listing.

Another object of this invention is to provide a programmable calculator capable of editing programs stored within the calculator more efficiently than conventional programmable calculators.

Another object of this invention is to provide a programmable calculator in which the user may single step either forward or backward through an internally stored program in a program entering mode to check the program and may single step forward through the program in a program-controlled operating mode to check the program execution.

Another object of this invention is to provide a programmable calculator in which the last program step encountered, the program step presently encountered, and the next program step to be encountered, while single stepping either forward or backward through a program stored within the calculator, may be displayed.

Another object of this invention is to provide a programmable calculator in which the user may insert program steps and automatically locate every occurrence of a designated program step in a program stored within the calculator.

Other and incidental objects of this invention will become apparent from a reading of this specification and an inspection of the accompanying drawings.

These objects are accomplished according to the illustrated preferred embodiment of this invention by employing a keyboard input unit, a magnetic card reading and recording unit, a solid state output display unit, an output printer unit, an input-output control unit, a memory unit and a central processing unit to provide an adaptable programmable calculator having manual operating, automatic operating, program entering, magnetic card reading, magnetic card recording, and alphameric printing modes. The keyboard input unit includes a group of data keys for entering numeric data into the calculator, a group of control keys for controlling the various modes and operations of the calculator and the format of the output display, and a group of definable keys for controlling additional functions that may be added by the user. All of the data keys and nearly all of the control keys may also be employed for programming the calculator, many of the control keys being provided solely for this purpose. The keyboard input unit also includes a group of indicator lights for informing the user of the status of the calculator. These indicator lights and all of the keys are mounted on a front panel of a housing for the calculator.

The magnetic card reading and recording unit includes a reading and recording head, a drive mechanism for driving a magnetic card from an input receptacle in the front panel of the calculator housing past the reading and recording head to an output receptacle in the front panel, and reading and recording drive circuits coupled to the reading and recording head for bidirectionally transferring information between the magnetic card and the calculator as determined by the control keys of the keyboard input unit. It also includes a pair of detectors and an associated control circuit for disabling the recording drive circuit whenever a notch is detected in the leading edge of the magnetic card to prevent information recorded on the magnetic card from being inadvertently destroyed. Such a notch may be provided in any magnetic card the user desires to protect by simply pushing out a perforated portion thereof.

The solid state output display unit includes three rows of light emitting diode arrays and associated drive circuits for selectively displaying three separate lines of numeric information. Numeric data may be displayed in either a fixed or a floating point format as determined by the control keys of the keyboard input unit.

The output printer unit includes a stationary thermal printing head with a row of resistive heating elements, a drive circuit for selectively energizing each heating element, and a stepping mechanism for driving a strip of thermal-sensitive recording paper past the stationary thermal printing head in seven steps for each line of alphameric information to be printed out. Every alphabetic and numeric character and many other symbols may be printed out individually or in messages as determined by the control keys of the keyboard input unit or by a program stored within the calculator.

The input-output unit includes a 16-bit universal shift register serving as an input-output register into which information may be transferred serially from the central processing unit or in parallel from the keyboard input and magnetic card reading and recording units and from which information may be transferred serially to the central processing unit or in parallel to the keyboard indicator lights and to the solid state output display, magnetic card reading and recording, and output printer units. It also includes control logic responsive to the central processing unit for controlling the transfer of information between these units. The input-output control unit may also be employed to perform the same functions between the central processing unit and peripheral units including, for example, a digitizer, a marked card reader, an X-Y plotter, a magnetic tape unit, and a typewriter. A plurality of peripheral units may be connected at the same time to the input-output control unit by simply plugging interface modules associated with the selected peripheral units into receptacles provided therefore in a rear panel of the calculator housing.

The memory unit may employ both direct and indirect decimal and symbolic addressing. It includes a modular random-access read-write memory having a program storage section for storing a plurality of program steps and having a separate data storage section including a plurality of working registers, a plurality of associated display registers, and a plurality of storage registers for manipulating and storing data. These program and data storage sections of the read-write memory may be separately expanded without increasing the overall dimensions of the calculator by the addition of program storage modules or by the alteration of the data storage memory control. Additional read-write memory made available to the user is automatically accommodated by the calculator, and the user is automatically informed when the program or data storage capacity of the read-write memory has been exceeded.

The memory unit also includes a modular read-only memory in which routines and subroutines of basic instructions for performing the various functions of the calculator are stored. These routines and subroutines of the read-only memory may be expanded and adapted by the user to perform additional functions oriented toward the specific needs of the user. This is accomplished by simply plugging additional read-only memory modules into receptacles provided therefor in the top panel of the calculator housing. Added read-only memory modules are automatically accommodated by the calculator and may be associated with the definable keys of the keyboard input unit or employed to expand the operations associated with other keys. An overlay is employed with each added read-only memory module associated with the definable keys of the keyboard input unit to identify the additional functions that may then be performed by the calculator.

Plug-in read-only memory modules including, for example, an alpha module, a mathematics module, a statistics module, a definable functions module, and a typewriter module may be added to the read-only memory. The alpha module enables the calculator to print out every alphabetic character individually or in messages. It employs addressing enabling it to redefine most of the keys of the keyboard input unit so that it may be employed at the same time as other plug-in read-only memory modules. The mathematics module enables the calculator to perform trigonometric functions, coordinate transformations, vector arithmetic, and many other mathematical functions. Similarly, the statistics module enables the calculator to perform random number generations, accumulations of sums, sums of products and sums of squares for up to five variables, linear and multiple linear regressions, and many other statistical functions. It also permits the use of a correct key, included among the definable keys of the keyboard input unit, to automatically delete data from a statistical analysis. The definable functions module enables the user to store programs of his own choosing in the program storage section of the read-write memory, associate them with some of the definable keys of the keyboard input unit, and protect them from subsequently being inadvertently altered or destroyed. It also permits the use of an insert key and a find key, included among the definable keys of the keyboard input unit, to insert program steps in a program stored in the read-write memory and to find evey occurrence of any designated program step in the stored program. The typewriter module enables the calculator to control the entire keyboard of a properly interfaced typewriter.

The memory unit further includes a pair of recirculating 16-bit serial shift registers. One of these registers serves as a memory address register for serially receiving information from an arithmetic-logic unit included in the central processing unit, for parallel addressing any memory location designated by the received information, and for serially transferring the received information back to the arithmetic-logic unit. The other of these registers serves as a memory access register for serially receiving information from the arithmetic-logic unit, for writing information in parallel into any addressed memory location, for reading information in parallel from any addressed memory location, and for serially transferring information to the arithmetic-logic unit. It also serves as a four-bit parallel shift register for transferring four bits of binary-coded-decimal information in parallel to the arithmetic-logic unit.

The central processing unit includes four recirculating 16-bit serial shift registers, a four-bit serial shift register, the arithmetic logic unit, a programmable clock, and a microprocessor. Two of these 16-bit serial shift registers serve as accumulator registers for serially receiving information from and serially transferring information to the arithmetic-logic unit. The accumulator register employed is designated by a control flip-flop. One of the accumulator registers also serves as a four-bit parallel shift register for receiving four bits of binary-coded-decimal information in parallel from and transferring four bits of such information in parallel to the arithmetic-logic unit. The two remaining 16-bit serial shift registers serve as a program counter register and a qualifier register, respectively. They are also employed for serially receiving information from and serially transferring information to the arithmetic-logic unit. The four-bit serial shift register serves as an extend register for serially receiving information from either the memory access register or the arithmetic-logic unit and for serially transferring information to the arithmetic-logic unit.

The arithmetic-logic unit is employed for performing one-bit serial binary arithmetic, four-bit parallel binary-coded-decimal arithmetic, and logic operations. It may also be controlled by the microprocessor to perform bi-directional direct and indirect arithmetic between any of a plurality of the working registers and any of the storage registers of the data storage section of the read-write memory.

The programmable clock is employed to supply a variable number of shift clock pulses to the arithmetic-logic unit and to the serial shift registers of the input-output, memory, and central processing units. It is also employed to supply clock control signals to the input-output control logic and to the microprocessor.

The microprocessor includes a read-only memory in which a plurality of microinstructions and codes are stored. These microinstructions and codes are employed to perform the basic instructions of the calculator. They include a plurality of coded and non-coded microinstructions for transferring control to the input-output control logic, for controlling the addressing and accessing of the memory unit, and for controlling the operation of the two accumulator registers, the program counter register, the extend register and the arithmetic-logic unit. They also include a plurality of clock codes for controlling the operation of the programmable clock, a plurality of qualifier selection codes for selecting qualifiers and serving as primary address codes for addressing the read-only memory of the microprocessor, and a plurality of secondary address codes for addressing the read-only memory of the microprocessor. In response to a control signal from a power supply provided for the calculator, control signals for the programmable clock, and qualifier-control signals from the central-processing and input-output control units, the microprocessor issues the microinstructions and codes stored in the read-only memory of the microprocessor as required to process either binary or binary-coded-decimal information entered into or stored in the calculator.

In the manual operating mode, the calculator is controlled by keycodes sequentially entered into the calculator from the keyboard input unit by the user. The solid state output display unit displays a numeric representation of the contents of three of the working registers and their associated display registers. These working registers and their associated display registers may contain the last-entered numeric operand and two previously entered or calculated numeric operands or results or three previously entered or calculated numeric operands or results. The output printer unit may be controlled by the user to selectively print out a numeric representation of any numeric data entered into the calculator from the keyboard input unit, a numeric representation of any result calculated by the calculator, and a mark distinguishing numeric data entries from calculated numeric results. If the alpha read-only memory module is plugged into the calculator, the output printer unit may also be controlled by the user to print out labels for inputs to and outputs from the calculator and any other alphabetic information that may be desired.

When the calculator is in the manual operating mode, it may also be operated in a key-log alphameric printing mode. The output printer unit then prints out a numeric representation of each keycode as it is entered by the user. If the alpha read-only memory module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each such keycode.

In the automatic operating mode, the calculator is controlled by automatically obtaining keycodes stored as steps of a program in the program storage section of the read-write memory. During automatic operation of the calculator, data may be obtained from the memory unit as designated by the program or may be entered from the keyboard input unit by the user while the operation of the calculator is stopped for data either by the program or by the user. The solid state output display unit displays the final contents of the three registers and their associated display registers. This may include the final calculated numeric result and two previously entered or calculated numeric operands or results or three previously entered or calculated numeric operands or results. The output printer unit prints out calculated numeric results and other numeric information designated by the program. If the alpha read-only memory module is plugged into the calculator, the output printer unit also prints out any alphabetic information designated by the program.

When the calculator is in the automatic operating mode, the user may also employ a step program control key of the keyboard input unit to single step forward through the program being executed. This enables the user to check the execution of the program step by step in order to determine whether the program, as entered into the calculator, does in fact carry out the desired sequence of operations.

In the program entering mode, keycodes are sequentially entered by the user into the calculator from the keyboard input unit and are stored as steps of a program in the program storage section of the read-write memory. The program may include sequences of program steps that will be intrepreted, when the program is executed, as alphabetic information to be printed out by the output printer unit if the alpha read-only memory module is plugged into the calculator. This alphabetic information may include labels for inputs to and outputs from the calculator, alphabetic messages for facilitating the use of the program and the operation of the calculator, or any other alphabetic information that may be desired. While the user is entering a program into the calculator in the program entering mode, the solid state output display unit displays a numeric representation of the last-entered program step and its associated address and the addresses of the next two program steps to be entered and the present contents of those addresses.

In the program entering mode, the user may also employ the step program control key and a back step control key of the keyboard input unit, to single step either forward or backward through any sequence of program steps stored in the program storage section of the read-write memory. While the user is single stepping forward or backward through a sequence of program steps, the solid state output display unit displays a numeric representation of the last-encountered program step, the program step presently encountered, the next program step to be encountered, and the addresses of these program steps. If the definable functions read-only memory module is plugged into the calculator, the user may also employ the insert and find keys described above by switching to the manual operating mode. These features greatly facilitate the editing of programs stored in the program storage section of the read-write memory.

When the calculator is in the program entering mode, it may also be operated in a key-log alphameric printing mode. The output printer unit then prints out a numeric representation of each program step and its associated address as it is entered into the calculator from the keyboard input unit by the user. If the read-only memory module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each such program step.

When the calculator is in the program entering mode, it may also be operated in a list alphameric printing mode. The output printer unit then prints out a numeric representation of every program step then stored in the program storage section of the read-write memory and a numeric representation of the addresses of those program steps. If the alpha read-only memory module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each such program step.

In the magnetic card reading mode, the magnetic card reading and recording unit may be employed by the user to separately load either data or programs into the calculator from one or more external magnetic cards. Data and programs so loaded are separately stored in the data storage and program storage sections of the read-write memory.

In the magnetic card recording mode, the magnetic card reading and recording unit may be employed by the user to separately record either data or programs, separately stored in the data storage and program storage sections of the read-write memory, onto one or more external magnetic cards. Programs stored in the program storage section of the read-write memory may be coded by the user as being secure when they are recorded onto one or more external magnetic cards. The calculator detects such programs when they are reloaded into the calculator and prevents the user from re-recording them or obtaining any listing or other indication of the individual program steps.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a front perspective view of an adaptable programmable calculator according to the preferred embodiment of this invention.

FIG. 2 is a rear perspective view of the adaptable programmable calculator of FIG. 1.

FIGS. 3A-B are simplified block diagrams of the adaptable programmable calculator of FIGS. 1 and 2.

FIG. 4 is a memory map of the memory unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 5 is a detailed memory map of the dedicated portion of the data storage section of the read-write memory employed in the memory unit of FIGS. 3A-B and 4.

FIG. 6 is a detailed memory map of the dedicated portion of the program storage section of the read-write memory employed in the memory unit of FIGS. 3A-B and 4.

FIGS. 7A-C are simplified operational logic flow charts illustrating the operation of the microprocessor employed in the central processing unit of FIGS. 3A-B.

FIG. 7' is a figure map showing how the operational flow charts of FIGS. 7A-C fit together.

FIG. 8 is a plan view of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B showing how the keyboard input unit may be redefined by an alpha plug-in read-only memory module that may also be employed in the adaptable programmable calculator.

FIG. 9 is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B and the overlay associated with a definable functions plug-in read-only memory module that may be employed in the adaptable programmable calculator.

FIG. 10 is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B and the overlay associated with a mathematics plug-in read-only memory module that may be employed in the adaptable programmable calculator.

FIG. 11 is a plan view of the definable keys of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B and the overlay associated with a statistics plug-in read-only memory module that may be employed in the adaptable programmable calculator.

FIG. 12 is a plan view of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B showing how the keyboard input unit may be redefined by a typewriter plug-in read-only memory module that may also be employed in the adaptable programmable calculator.

FIG. 13 is a simplified flow chart of the overall control sequence employed for keycode processing in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 14 is a flow chart of the display routine of FIG. 13.

FIGS. 15 A-C are flow charts of the display list building routine of FIG. 14.

FIG. 16 is a map of the output bit assignment for The seven-segment display employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 17 is a map of the display list built in the read-write memory of FIGS. 3A-B, 4, and 5.

FIG. 18 is a map of the internal structure of the display list of FIG. 17.

FIGS. 19A-B are flow charts of the monitor routine employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 20A-B are flow charts of the interpreter routine of FIG. 13.

FIGS. 21 A-D are flow charts of the program mode key, run mode key, floating-point display key, and fixed-point display key processing routines, respectively, of FIG. 13.

FIG. 22 is a map of the status word register of FIG. 5 illustrating how it is employed by some of the routines of FIGS. 21A-D.

FIG. 23 is a flow chart of the back step key processing routine of FIG. 13.

FIG. 24 is a flow chart of the clear key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 25 is a flow chart of the end key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 26 is a flow chart of the stop key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 27 is a flow chart of the integer x key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 28 is a flow chart of the pi key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 29 dis a flow chart of the clear x key processing routine selectable by the interpreter of FIG. 13.

FIGS. 30A-B are simplified flow charts of the number entry processing routine selectable by the interpreter of FIG. 13.

FIGS. 31A-C are flow charts of portions of the magnitude processing portions of the number entry routine of FIGS. 30A-B.

FIGS. 32A-B are flow charts of exponent processing portions of the number entry routine of FIGS. 30A-B.

FIG. 33 is a flow chart of the change-sign processing portion of the number entry routine of FIGS. 30A-B.

FIG. 34 is a flow chart of the termination portion of the number entry routine of FIGS. 30A-B.

FIG. 35 is a flow chart of the up-key processing routine selectable by the interpreter of FIGS. 13.

FIG. 36 is a flow chart of the down-key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 37 is a flow chart of the roll-up key processing routine selectable by the interpreter routine of FIG. 13.

FIGS. 38A-B are simplified flow charts of the register transfer and register arithmetic routines selectable by the interpreter routine of FIG. 13.

FIGS. 39A-B are flow charts of the register transfer and automatic address termination routine employed in connection with the register transfer arithmetic key processing routine of FIGS. 38A-B.

FIG. 40 is a flow chart of the indirect-key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 41 is a flow chart of the a- and b-register transfer key processing routines selectable by the interpreter routine of FIG. 13.

FIG. 42 is a flow chart of the indirect address computation routine employed in connection with the indirect-key processing routine of FIG. 40.

FIG. 43 is a flow chart of the decimal address jump and automatic address termination routine employed in connection with the go-to and if key processing routines selectable by the interpreter routine of FIG. 13.

FIG. 44 is a flow chart of the label-key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 45 is a flow chart of the if key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 46 is a flow chart of the subroutine/return key processing routine selectable by the interpreter routine of FIG. 13.

FIGS. 47A-C are flow charts of the floating point add and subtract key processing routines selectable by the interpreter routine of FIG. 13.

FIG. 48 is a flow chart of the floating point multiply key processing routine selectable by the interpreter routine of FIG. 13.

FIGS. 49A-B are flow charts of the floating point division key processing routine of FIG. 13.

FIGS. 50A-C are flow charts of the floating point square root key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 51 is a flow chart of the store routine of FIG. 13.

FIG. 52 is a flow chart of the rounding routine employed in connection with several of the routines selectable by the interpreter routine of FIG. 13.

FIG. 53 is a flow chart of the x-squared key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 54 is a flow chart of the reciprocal-x key processing routine selectable by the interpreter routine of FIG. 13.

FIGS. 55A-B are flow charts of the basic format key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 56 is a flow chart of a search routine that may be employed in connection with the basic format key processing routine of FIGS. 55-B.

FIG. 57 is a memory map illustrating the use of the search routine of FIG. 56.

FIGS. 58A-B are flow charts of a plotter routine employed in connection with the basic format key processing routine of FIGS. 55A-B.

FIG. 59 is a map of a memory register employed in connection with the plotter routine of FIGS. 58A-B.

FIG. 60 is a flow chart of the program-step recording portion of the record key processing routine of FIG. 13.

FIG. 61 is a flow chart of the program-step loading portion of the load key processing routine of FIG. 13.

FIG. 62 is a memory map of the program storage section of the read-write memory of FIGS. 3A-B and 4-6 illustrating how a secure program is destroyed by an unsecure program.

FIG. 63 is a flow chart of the format recording portion of the record key processing routine of FIG. 13.

FIG. 64 is a flow chart of the data recording portion of the record key processing routione of FIG. 13.

FIG. 65 is a flow chart of the data loading portion of the load key processing routine of FIG. 13.

FIG. 66 is a flow chart showing how a plug-in read-only memory module employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B can obtain keycodes from a program stored in the program storage section of the read-write memory of FIGS. 3A-B and 4.

FIGS. 67A-C show how the print routine accesses code information stored in tables in the data storage section of the read-write memory of FIGS. 3A-B and 4.

FIGS. 68A-B are memory maps of a directive table and a code table respectively, in an alpha plug-in read-only memory module that may be employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 69 is a flow chart showing how the printer code is accessed by an alpha plug-in read-only memory module employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 70A-B are flow charts of the typewriter format routine employed in connection with the format key processing routine selectable by the interpreter routine of FIG. 13.

FIG. 71 is a memory map of a typewriter mnemonic table in a typewriter plug-in read-only memory module that may be employed in the adaptable programmable calculator of FIGS. 1, 2, and 1, 2, and B.

FIG. 72 is a flow chart of a typewriter list routine that may be performed when the typewriter read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 73 is a flow chart of a typewriter print routine that may be performed when the typewriter read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 74 is a flow chart of a typewriter alpha routine that may be performed when the typewriter read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 75 is a flow chart of a definable keycode entry routine employed when the definable functions read-only memory module is plugged into the calculator.

FIG. 76 is a flow chart of a protect key processing routine that may be performed when the definable functions read-only memory module is plugged into the calculator.

FIG. 77 is a flow chart of a memory search routine that may be performed when the definable functions read-only memory module is plugged into the calculator.

FIGS. 78A-B are flow charts of a definable function calls routine that may be performed when the definable functions read-only memory module is plugged into the calculator.

FIG. 79 is a directive table of the function calls that may be performed by the definable function calls routine of FIGS. 78A-B.

FIG. 80 is a flow chart of a definable function return routine employed with the definable function calls routine of FIGS. 78A-B.

FIG. 81 is a flow chart of a turn-off-the-function light subroutine employed by the definable function return routine of FIG. 80.

FIG. 82 is a flow chart of a function stack checking subroutine employed by the definable function calls routine and the definable function return routine of FIGS. 78A-B and 80, respectively.

FIG. 83 is a flow chart of a delete-protect routine that may be performed when the definable functions read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 84 is a flow chart of a turn-off-the-delete-light subroutine employed by the delete-protect routine of FIG. 83.

FIG. 85 is a flow chart of an empty-the-function-stack subroutine employed by the delete-protect routine of FIG. 83.

FIG. 86 is a flow chart of a find routine that may be performed when the definable functions read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 87 is a flow chart of a get-the-next-key subroutoine employed by the find routine of FIG. 86.

FIG. 88 is a flow chart of a memory compactor routine that may be performed when the definable functions read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1,2,and 3A-B

FIG. 89 is a memory map illustrating the use of the memory compactor subroutine of FIGS. 88.

FIGS. 90A-C are flow charts of a delete routine that may be performed when the definable functions read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 91A-B are flow charts of an insert routine that may be performed when the definable functions read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 92 is a flow chart of an address calculating subroutine employed by the insert routine of FIGS. 91A-B.

FIGS. 93A-B are flow charts of a tangent x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 94A-B are flow charts of an arctangent x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 95A-B are flow charts of an e-to-the-x-power that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 96 is a flow chart of a natural logarithm x routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 97 is a flow chart of a subroutine employed by the tangent x and the e-to-the-x-power routines of FIGS. 93A-B and 95A-B, respectively.

FIG. 98A-B are flow charts of a subroutine employed by the tangent x and arctangent x routines of FIGS. 93A-B and 94A-B, respectively.

FIGS. 99A-B are flow charts of a subroutine employed by the e-to-the-x-power and natural logarithm x routines of FIGS. 95A-B and 96, respectively.

FIG. 100 is a flow chart of a subroutine employed by the arctangent x and natural logarithm x routines of FIGS. 94A-B and 96, respectively.

FIG. 101 is a flow chart of sine and cosine routines that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 102 is a flow chart of a table f(x) routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 103 is a flow chart of an arc routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 104 is a flow chart of an arcsine routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 105 is a flow chart of an arccosine routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 106 is a flow chart of a conversion to polar coordinates routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 107 is a flow chart of a conversion to rectangular coordinates routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 108 is a flow chart of a 10-to-the-x-power routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 109 is a flow chart of an absolute value y routine that may be performed when the mathematics read-only memory module is plugged into the adaptable progammable calculator of FIGS. 1, 2, and 3A-B.

FIG. 110 is a flow chart of an x-to-the-y-power routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 111 is a flow chart of a logarithm-to-the-base-10 routine that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 112 is a flow chart of a routine for converting degrees, minutes, and seconds to degrees that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 113 is a flow chart of a routine for converting degrees to degrees, minutes, and seconds that may be performed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 114 is a flow chart of a subroutine employed by the routine of FIG. 113 for converting degrees to degrees, minutes, and seconds.

FIG. 115 is a flow chart of an x factorial routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 116 is a flow chart of a recall routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 117 is a flow chart of an accumulate plus routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 118 is a flow chart of an accumulate minus routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 119A-B are flow charts of a rounding routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 120 is a flow chart of a scale routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 121 is a flow chart of a subroutine employed by the scale routine of FIG. 120.

FIG. 122 is a flow chart of a clear routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 123 is a flow chart of a definable f(x) routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 124 is a flow chart of a do-loop routine that may be employed when the mathematics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 125A-B are flow charts of a summation routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 126 is a flow chart of a correct routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 127 is a flow chart of a t-pair routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 128 is a flow chart of an x-squared routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 129 is a flow chart of a mean value routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 130 is a flow chart of a maximum/minimum routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 131 is a flow chart of a variance routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 132 is a flow chart of an initialize routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 133 is a flow chart of a regression routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 134 is a flow chart of a variables routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 135 is a flow chart of an r2 -correlation routine that may be performed when the statistics read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 136 is a block diagram of the microprocessor of FIGS. 3A-B.

FIGS. 137A-D are detailed schematic diagrams of the microprocessor of FIGS. 34A-B and 136.

FIG. 137' is a figure map showing how the detailed schematic diagrams of FIGS. 137A-D fit together.

FIGS. 138A-H are detailed flow charts illustrating the operation of the microprocessor of FIGS. 3A-B, 136, and 137A-D.

FIG. 138' is a figure map showing how the detailed flow charts of FIGS. 138A-D fit together.

FIG. 138" is a figure map showing how the detailed flow charts of FIGS. 138E-H fit together.

FIG. 138I shows the macro-instruction coding table, the used data format, and the used address and constants for the micro-processor of FIGS. 3A-B and 136.

FIG. 138J is an instruction table for the micro-processor of FIGS. 3A-B and 136.

FIG. 139 is a block diagram of the programmable clock of FIGS. 3A-B.

FIGS. 140A-C are detailed schematic diagrams of the programmable clock of FIGS. 3A-B and 139 and of a portion of the input-output control unit of FIG. 3A-B.

FIG. 140' is a figure map showing how the detailed schematic diagrams of FIGS. 149A-C fit together.

FIG. 141 is a waveform diagram illustrating the operation of the programmable clock of FIGS. 3A-B 139, and 140A-C.

FIGS. 142A-D are detailed schematic diagrams of the shift register and arithmetic logic units of FIGS. 3A-B.

FIG. 142' is a figure map showing how the detailed schematic diagrams of FIGS. 142A-D fit together.

FIG. 143 is a block diagram of the arithmetic-logic unit of FIGS. 3A-B.

FIG. 144 is a table of the function code assignments of the arithmetic-logic unit of FIGS. 142A-D and 143.

FIG. 145 is a table of integrated circuits that may be employed to construct the ALU of FIGS. 142A-D and 143.

FIG. 146 is a block diagram of the memory unit of FIGS. 3A-B.

FIG. 147 is a table of mnemonics used in the memory unit of FIG. 3.

FIG. 148 is a schematic diagram of the read-write memory of FIGS. 3A-B 4, and 146.

FIG. 149 is a schematic diagram of one of the add-on read-write memory modules of FIG. 146 that may be plugged into the calculator to increase the amount of program storage memory available to the user.

FIG. 150 is a schematic diagram of the other add-on read-write memory module of FIG. 146 that may be plugged into the calculator to further increase the amount of program storage memory available to the user.

FIG. 151 is a schematic diagram of the read-only memory of FIGS. 3A-B 4, and 146.

FIG. 152 is a schematic diagram of the add-on read-only memory modules of FIG. 146 that may be pluged into the calculator to increase the number of functions available to the user.

FIG. 153 is a block diagram of one of the read-only memory chips of FIGS. 151-152.

FIGS. 154A-D are schematic diagrams of one of the read-only memory chips of FIGS. 151-152.

FIG. 154' is a figure map showing how the detailed schematic diagrams of FIGS. 154A-D fit together.

FIG. 155 is a memory map of the memory unit of FIGS 3A-B and 4 illustrating how it is partitioned into the read-only and read-write memory chips of FIGS. 148-153 and 154A-D.

FIG. 156 is a flow chart illustrating how the row numbers of the lists stored in the read-only memory chips are computed.

FIG. 157 is a table of bit mumbers of actual bits used in connection with the flow chart of FIG. 156.

FIGS. 158A-D are detailed schematic diagrams of the memory address register of FIGS. 3A-B and 146.

FIG. 158' is a figure map showing how the detailed schematic diagrams of FIGS. 158A-D fit together.

FIGS. 159A-D are detailed schematic diagrams of the control circuitry of FIGS. 3 and 146.

FIG. 159' is a figure map showing how the detailed schematic diagrams of FIGS. 159A-D fit together.

FIG. 160 is a waveform diagram illustrating the operation of the control circuitry of FIGS. 159A-D.

FIGS. 161A-D are detailed schematic diagrams of the memory access register of FIGS. 3A-B and 146.

FIG. 161' is a figure map showing how the detailed schematic diagrams of FIGS. 161A-D fit together.

FIGS. 162A-D are detailed schematic diagrams of the input-output register and gating control circuits employed in the input-output control unit of FIG. 3.

FIG. 162' is a figure map showing how the detailed schematic diagrams of FIGS. 162A-D fit together.

FIG. 163 is a schematic diagram of the source and and relationship of the input-output party lines connected to the peripheral interface module receptacles of FIG. 2.

FIG. 164 is a waveform diagram illustrating the operation of the control section of the input-output control unit FIGS. 3A-B and 140A-C.

FIG. 165 is a flow chart illustrating the operation of the control section of the input-output control unit of FIGS. 3A-B and 140A-C.

FIG. 166 is a schematic diagram of the address code decoding for the output section of the interface modules employed with the input-output control unit of FIGS. 3A-B.

FIG. 167 is a chart listing and defining all of the input-output lines of the input-output control unit of FIGS. 3A-B.

FIG. 168 is a waveform diagram of some of the output signals employed by the input-output control unit and associated interface modules of FIGS. 3A-B.

FIG. 169 is a waveform diagram of some of the input signals employed by the input-output control unit and associated interface modules of FIGS. 3A-B.

FIG. 170 is a waveform diagram illustrating the operation of the interrupt mode of operation of the input-output control unit of FIGS. 3A-B.

FIG. 171 is a schematic diagram of logic that may be used to interface an output peripheral to the input-output control unit of FIGS. 3A-B.

FIG. 172 is a schematic diagram of logic that may be used to interface an input peripheral to the input-output control unit of FIGS. 3A-B.

FIG. 173 is a schematic diagram of logic that may be used to interface an interrupting peripheral to the input-output control unit of FIGS. 3A-B.

FIGS. 174A-D are detailed schematic diagrams of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 174' is a figure map showing how the detailed schematic diagrams of FIGS. 174A-D fit together.

FIG. 175 is a schematic diagram of one of the transformer pairs employed in the keyboard input of FIGS. 174A-D.

FIG. 176 is a pictorial view of a transformer employed in the keyboard input unit of FIG. 3.

FIG. 177 is a schematic diagram of the transformer of FIG. 176.

FIG. 178 is a schematic diagram of a portion of the keyboard input unit of FIGS. 174A-D.

FIG. 179 illustrates the required polarities for the drive and sense lines employed in the keyboard input unit of FIG. 3 and 176.

FIG. 180 is a block diagram of the magnetic card reading and recording unit employed in the calculator of FIGS. 1, 2, and 3A-B.

FIGS. 181A-G are schematic diagrams of the magnetic card reading and recording unit of FIG.180.

FIG. 181' is a figure map showing how the detailed schematic diagrams of FIGS. 181A-G fit together.

FIG. 182 is a block diagram illustrating how the magnetic card reading and recording unit of FIGS. 180 and 181A-G interacts with the calculator of FIGS. 1, 2, and 3A-B.

FIG. 183 is a block diagram of the output display unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIGS. 184A-B are detailed schematic diagrams of the output display unit of FIG. 183.

FIG. 184' is a figure map showing how the detailed schematic diagrams of FIGS. 184A-B fit together.

FIG. 185 is a block diagram of the output printer unit employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 186 is a cross-sectional view taken along the line A--A in FIG. 185.

FIGS. 187A-B are detailed schematic diagrams of the thermal printing head, isolation diodes, four group drivers, and one-of-10 decoder of FIG. 185.

FIG. 187' is a figure map showing how the detailed schematic diagrams of FIGS. 187A-B fit together.

FIG. 188 is a partial plan view of the thermal printing head of FIG. 185.

FIGS. 189A-D are a detailed schematic diagrams of the 20 dot drivers the internal 10-bit shift register, the motor drivers, the motor drive control circuit, and the printer timing circuit of the motor drivers of FIG. 185.

FIG. 190 is a figure map showing how the detailed schematic diagrams of FIGS. 189A-D fit together.

FIGS. 191A-B are detailed schematic diagrams of the motor drivers of FIG. 185.

FIG. 191' is a figure map showing how the detailed schematic diagrams of FIGS. 191A-B fit together.

FIG. 192 illustrates how the output printer unit of FIGS. 185-191 prints out each character.

FIG. 193 is a flow chart illustrating the printing operation of the output printer unit of FIGS. 186, 187A-B, 188, 189A-D, and 191A-B.

FIG. 194 is a block diagram of the power supply system employed in the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 195 is a detailed schematic of the 5 volt power supply of FIG. 194.

FIG. 196 is detailed schematic diagram of the 16, 20, and 24 volt power supplies of FIG. 194.

FIGS. 197A-B are detailed schematic diagrams of the positive and negative 12 volt power supplies of FIG. 194.

FIG. 198 is a schematic diagram of an alternative ripple signal circuit that may be employed in the power supply of FIG. 195.

FIGS. 199A-B are block diagrams of an interface module that may be employed to interface a typewriter to the adaptable programmable calculator of FIGS. 1, 2, and 3A-B.

FIG. 199' is a figure map showing how the block diagrams of FIGS. 199A-B fit together.

FIGS. 200A-C are schematic diagrams of the interface module of FIGS. 199A-B.

FIG. 200' is a figure map showing how the schematic diagrams of FIGS. 200A-C fit together.

DESCRIPTION OF THE PREFERRED EMBODIMENT

GENERAL DESCRIPTION

Referring to FIGS. 1 and 2, there is shown an adaptable programmable calculator 10 including both a keyboard input unit 12 for entering information into and controlling the operation of the calculator and a magnetic card reading and recording unit 14 for recording information stored within the calculator onto one or more external magnetic cards 16 and for subsequently loading the information recorded on these and other similar magnetic cards back into the calculator. The calculator also includes a solid state output display unit 18 for displaying three lines of numeric information stored within the calculator and a group of indicator lights 19, serving as part of the keyboard input unit, for indicating the status of the calculator. It may also include an output printer unit 20 for printing out alphameric information on a strip of thermal-sensitive recording paper 22. All of these input and output units are mounted within a single calculator housing 24 adjacent to a curved front panel 26 thereof.

As shown in FIG. 2, a plurality of peripheral input and output units 28 including, for example, a digitizer, a marked card reader, an X-Y plotter, and a typewriter may be connected to the calculator at the same time by simply inserting interface modules 30 associated with the selected peripheral units into any of four receptacles 32 provided therefor in a rear panel 34 of the calculator housing. As each interface module 30 is inserted into one of these receptacles, a spring-loaded door 38 at the entrance of the receptacle swings down allowing passage of the interface module. Once the interface module is fully inserted, a printed-circuit terminal board 40 contained within the interface module plugs into a mating edge connector mounted inside the calculator. If any of the selected peripheral units require AC line power, their power cords may be plugged into any of three AC power outlets 42 provided therefor at the rear panel of calculator housing 24.

Referring to the simplified block diagram shown in FIGS. 3A-B, it may be seen that the calculator also includes an input-output control unit 44 (hereinafter referred to as the I/O control unit) for controlling the transfer of information to and from the input and output units, a memory unit 46 for storing and manipulating information entered into the calculator and for storing routines and subroutines of basic instructions performed by the calculator, and a central processing unit 48 (hereinafter referred to as the CPU) for controlling the execution of the routines and subroutines of basic instructions stored in the memory unit as required to process information entered into or stored within the calculator. The calculator also includes a bus system comprising an S-bus 50, a T-bus 52, and an R-bus 54 for transferring information from the memory and I/O control units to the CPU, from the CPU to the memory and I/O control units, and between different portions of the CPU. It further comprises a power supply for supplying DC power to the calculator and peripheral units employed therewith and for issuing a control signal POP when power is supplied to the calculator.

The I/O control unit 44 includes an input-output register 56 (hereinafter referred to as the I/0 register), associated I/0 gating control circuitry 58, and input-output control logic 60 (hereinafter referred to as the I/0 control). I/0 register 56 comprises a universal 16-bit shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from keyboard input unit 12, magnetic card reading and recording unit 14, and peripheral input untis 28 such as the marked card reader via twelve input party lines 62. Information may also be transferred from I/0 register 56 either bit-serially to CPU 48 via S-bus 50 or in parallel to magnetic card reading and recording unit 14, solid state output display unit 18, indicator lights 19, output printer unit 20, and peripheral output units 28 such as the X-Y plotter or the typewriter via 16 output party lines 64.

I/0 gating control circuitry 58 includes control circuits for controlling the transfer of information into and out of I/0 register 56 in response to selected I/0 qualifier control signals from CPU 48 and selected I/0 control instructions from I/0 control 60. It also includes an interrupt control circuit 65, a peripheral control circuit 66, a magnetic card control circuit 67, a printer control circuit 68, a display control circuit 69, and an indicator control circuit 70 for variously controlling the input and output units and issuing control signals QFG and EBT to I/0 control 60 via two output lines 71 and 72. These last mentioned control circuits variously perform their control functions in response to control signal POP from the power supply, I/0 qualifier control signals from CPU 48, I/0 control instructions from I/0 control 60, and control signals from keyboard input unit 12. Interrupt control circuit 65 initiates the transfer of information into I/0 register 56 from keyboard input unit 12 or interrupting peripheral input units 28 such as the marked card reader and issues a qualifier control signal QNR to CPU 48 via output lines 73. Peripheral control circuit 66 enables interface modules 30 plugged into the calculator to respond to information from I/0 register 56, control associated peripheral units 28, transfer information to and/or receive information from associated peripheral units 28, and in some cases initiate the transfer of information to I/0 register 56 from the interface modules themselves. Magnetic card control circuit 67 enables magnetic card reading and recording unit 14 to respond to information in I/0 register 56 and either read information into I/0 register 56 from a magnetic card 16 or record information onto a magnetic card 16 from I/0 register 56. Printer control circuit 68, display control circuit 69, and indicator control circuit 70 enable output display unit 18, output printer unit 20, and indicator lights 19, respectively, to respond to information from I/0 register 56.

When a basic I/0 instruction obtained from memory unit 46 is to be executed, CPU 48 transfers control to I/0 control 60 by issuing a pair of I/0 microinstructions PTR and XTR thereto. In response to these I/0 microinstructions from CPU 48, control signal POP from the power supply, control signals QFG and EBT from I/0 gating control circuitry 58, and I/0 qualifier and clock control signals from CPU 48, I/0 control 60 selectively issues one or more I/0 control instructions to gating control circuitry 58 as required to execute the basic I/0 instruction designated by CPU 48 and issues control signals TTX, XTR, QRD, and SCB to CPU 48 via output lines 74-77. The I/0 qualifier control signals issued to I/0 control 60 and gating control circuitry 58 by CPU 48 are derived from the basic I/0 instruction to be executed. Those qualifier control signals issued to I/0 control 60 designate the specific I/0 control instructions to be issued by I/0 control 60, while those issued to gating control circuitry 58 designate selected control circuits to be employed in executing the basic I/0 instruction.

Memory unit 46 includes a modular random-access read-write memory 78 (hereinafter referred to as the RWM), a modular read-only memory 80 (hereinafter referred to as the ROM), a memory address register 82 (hereinafter referred to as the M-register), a memory access register 84 (hereinafter referred to as the T-register), and control circuitry 85 for these memories and registers RWM 78 and ROM 80 comprise MOS-type semiconductor memories. As shown in the memory map of FIG. 4, they are organized into eight 1,024-word pages. The basic RWM 78 contains a data storage section 86 of 512 16-bit words extending from address 1000 to address 1777 on page 0 and a separate program storage section 88 of 512 six-bit words extending from address 12000 to address 12777 on page 5. All addresses on the memory map are represented in octal form.

Data storage section 86 contains 49 four-word storage registers available to the user (as user addresses 000-048) for manipulating and storing data, 60 additional four-word storage registers that may be made available to the user (as user addresses 049-108) for the same purpose, and 76 words dedicated for use by CPU 48. The 60 additional four-word storage registers may be made available to the user by altering a control routine in the ROM section 80. This is accomplished by removing a top panel 90 of the calculator housing shown in FIG. 1, removing a printed circuit board containing the control routine to be altered, and substituting another printed circuit board containing the altered control routine. Additional data storage modules made available to the user are automatically accommodated by the calculator.

As shown in the more detailed memory map of FIG. 5, the dedicated portion of data storage section 86 includes 12 words (addresses 1750-1753, 1740-1743, and 1760-1763) employed as "X", "Y", and "Z" four-word working registers available to the user and 8 words (addresses 1764-1773) employed as a and b four-word storage registers available to the user. It also includes eight words (addresses 1744-1747 and 1754-1757) employed as "AR1" and "AR2" four-word working registers for performing binary-coded-decimal arithmetic; 12 words (addresses 1664-1677) employed as three ("T1'", "T2', and "T3'") or more temporary storage registers in connection with a definable section 91 of keyboard input unit 12 (see FIG. 1); 16 words (addresses 1720-1737) employed as four ("T1", "T2", "T3", and "T4") or more temporary storage registers in connection with the remaining sections of the keyboard input unit; seven words (addresses 1711-1717) employed as a variable-length "system subroutine stack" for storing return addresses required by programs stored in ROM 80 and as temporary storage for housekeeping information required by CPU 48; one word (address 1777) employed as a "system stack pointer"; five words (addresses 1702-1706) employed as a "user subroutine stack" for storing return addresses required by programs entered into program storage section 88 of RWM 78 by the user; one word (address 1710 employed as a "user stack pointer"; one word (address 1701) employed as a "user program counter" for program steps entered into program storage section 88 by the user; one word (address 1707) employed as an "address of user 0000" register for storing the first address available to the user in program storage section 88; one word (address 1700) employed as a "microprocessor store" register for storing housekeeping information required by CPU 48; one word (address 1774) employed as an "interrupt store" register for storing information displaced from CPU 48 by some keyboard entries; one word (address 1775) employed as an "input buffer" register for storing keyboard information awaiting entry into CPU 48, and one word (address 1776) employed as a "status word" register for storing information regarding the present state of the calculator.

As shown in the memory map of FIG. 4, program storage section 88 of RWM 78 contains 500 one-word program step registers available to the user (as user addresses 0000-0499) for storing programs and 12 words dedicated for use by CPU 48. An additional 1,536 one-word program-step registers may be made available to the user (as user addresses 0500-2035) in steps of 512 words (addresses 13000-13777) and 1,024 words (addresses 14000 to 15777). This is accomplished by removing top panel 90 of the calculator housing shown in FIG. 1 and plugging additional program storage modules into the calculator. Added program storage modules are automatically accommodated by the calculator.

As shown in the more detailed memory map of FIG. 6, the dedicated portion of program storage section 88 includes one word (address 12013) employed as a "security word" register for storing a code designating a program stored in program storage section 88 as being secure. It also includes one word (address 12000) employed as an "execution flag " register for storing information indicating whether CPU 48 is being controlled by a program stored in the program storage section or by the keyboard input unit; two words (addresses 12001-12002) employed as "normalize flag" and "print flag" registers for storing information about numeric data being processed by CPU 48; three words (addresses 12003-12005) employed as "temporary display" registers for storing housekeeping information about the character position, decimal position, and register location of numeric information being displayed by the output display unit; one word (address 12006) employed as a "print code buffer" register for storing housekeeping information about alphameric information being printed out by the output printer unit; and four words (addresses 12007-12012) available for other uses.

As shown in the memory map of FIG. 4, the basic ROM 80 contains 2,048 16-bit words extending from address 0000 to address 0777 on page 0, from address 4000 to address 5777 on page 2, and from address 16000 to address 16777 on page 7. Routines and subroutines of basic instructions for performing the basic functions of the calculator and constants employed by these routines and subroutines are stored in these portions of ROM 80. An additional 3,072 16-bit words of ROM may also be added on pages 1, 3, and 4 in steps of 512 and 1,024 words. This is accomplished by simply inserting plug-in ROM modules 92 into receptacles 94 provided therefor in top panel 90 of the calculator housing as illustrated in FIG. 1 by the partially-inserted plug-in ROM module on the left. As each plug-in ROM module 92 is inserted into one of these receptacles a spring-loaded door 95 at the entrance of the receptacle swings down allowing passage of the plug-in ROM module. Once the plug-in ROM module is fully inserted as illustrated by the plug-in ROM module on the right, a printed circuit terminal board 96 contained within the plug-in ROM module plugs into a mating edge connector mounted inside the calculator. A handle 98 pivotally mounted at the top end of each plug-in ROM module 92 facilitates removal of the plug-in ROM module once it has been fully inserted into one of the receptacles 94.

Routines and subroutines of basic instructions (and any needed constants) for enabling the calculator to perform many additional functions are stored in each plug-in ROM module 92. The user himself may therefore quickly and simply adapt the calculator to perform many additional functions oriented toward his specific needs by simply plugging ROM modules of his own choosing into the calculator. Added plug-in ROM modules are automatically accommodated by the calculator and associated with definable section 91 of keyboard input unit 12 or employed to expand the functions performed by this and other sections of the keyboard input unit.

Referring again to FIGS. 3A-B, M-register 82 of the memory unit comprises a recirculating 16-bit serial shift register into which information may be transferred bit-serially from CPU 48 via T-bus 52 and out of which information may be transferred bit-serially to CPU 48 via S-bus 50. Information shifted into M-register 82 may be employed to address any word in RWM 78 or ROM 80 via 15 output lines 106.

T-register 84 of the memory unit comprises a recirculating 16-bit serial shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from any addressed word in RWM 78 and ROM 80 via 16 parallel input lines 108. Information may be transferred from T-register 104 either bit-serially to CPU 48 via S-bus 50 or in parallel to any addressed word in RWM 78 via 16 parallel output lines 110. The four least significant parallel of information contained in T-register 104 may comprise binary-coded-decimal information and may be transferred from the T-register in parallel to CPU 48 via three parallel output lines 112 taken with S-bus 50.

The control circuitry 85 of the memory unit controls these transfers of information into and out of M-register 82 and T-register 84, controls the addressing and accessing of RWM 78 and ROM 80, and refreshes RWM 78. It performs these functions in response to memory microinstructions, memory clock pulses, and shift clock pulses from CPU 48.

CPU 48 includes a register unit 114, an arithmetic-logic unit 116 (hereinafter referred to as the ALU), a programmable clock 118, and a microprocessor 120. Register unit 114 comprises four recirculating 16-bit shift registers 122, 124, 126, and 128 and one four-bit shift register 130. Shift registers 122 and 124 serve as 16-bit serial accumulator registers (hereinafter referred to as the A-register and the B-register, respectively) into which information may be transferred bit-serially from ALU 116 via T-bus 52 and out of which information may be transferred bit-serially to ALU 116 via R-bus 54. The four least significant bit positions of A-register 122 also serve as a four-bit parallel accumulator register into which four bits of binary-coded-decimal information may be transferred in parallel from ALU 116 via four parallel input lines 132 and out of which four bits of binary-coded-decimal information may also be transferred in parallel to ALU 116 via three parallel output lines 134 taken with R-bus 54.

Shift register 126 serves as a 16-bit system program counter (hereinafter referred to as the P-register) into which information may be transferred bit-serially from ALU 116 via T-bus 52 and out of which information may be transferred bit-serially to ALU 116 via R-bus 54. Information contained in the least significant bit position of P-register 126 may also be transferred as a qualifier control signal QPO to microprocessor 120 via output line 135.

Shift register 128 serves as a sixteen-bit qualifier register (hereinafter referred to as the Q-register) into which information may be transferred bit-serially from ALU 116 via T-bus 52 and out of which information may be transferred bit-serially to ALU 116 via R-bus 54. Information contained in the five least-significant bit positions of Q-register 28 is transferred to I/0 gating control circuitry 58 as five one-bit I/0 qualifier control signals Q00-Q04 via five parallel output lines 136, and information contained in the six next-least significant bit positions of the Q-register is transferred to I/0 control 60 as six one-bit I/0 qualifier control signals Q05-Q10 via six parallel output lines 138. Similarly, information contained in the seven least-significant, the ninth and eleventh least-significant, and the most significant bit positions of Q-register 128 and information derived from the thirteenth, fourteenth, and fifteenth bit positions of the Q-register may be transferred to microprocessor 120 as 11 one-bit microprocessor qualifier control signals Q00-Q06, Q08, Q10, Q15, and QMR via 11 output lines 140. Information contained in the twelfth through the fifteenth least-significant bit positions of Q-register 128 may be transferred to microprocessor 120 as a four-bit primary address code via four parallel output lines 142.

Shift register 130 serves as a four-bit serial extend register (hereinafter referred to as the E-register) into which information may be transferred bit-serially either from ALU 116 via T-bus 52 or from the least-significant bit position of T-register 84 via input line 144. Information may also be transferred out of E-register 130 to ALU 116 via R-bus 54.

Register unit 114 also includes control circuitry 146 for controlling the transfer of parallel binary-coded-decimal information into and out of A-register 122 and the transfer of serial binary information into and out of A-register 122, B-register 124, P-register 126, Q-register 128, and E-register 130. This is accomplished in response to register microinstructions from microprocessor 120, control signals TTX and XTR from I/0 control 60, and shift clock control pulses from programmable clock 118. Control circuitry 146 includes a flip-flop 148 (hereinafter referred to as the A/B flip-flop) for enabling the transfer of information into and out of either the A-register 122 or the B-register 124 as determined by the state of the A/B flip-flop. The state of A/B flip-flop 148 is initially determined by information Q11 transferred to the A/B flip-flop from the twelfth least-significant bit position of Q-register 128 but may be subsequently complemented one or more times by microinstruction CAB from microprocessor 120.

ALU 116 may perform either one-bit serial binary arithmetic on data received from T-register 84 or M-register 82 via S-bus 50 and/or from any register of register unit 114 via R-bus 54 or four-bit parallel binary-coded-decimal arithmetic on data received from T-register 84 via output lines 112 taken with S-bus 50 and/or from A-register 122 via output lines 134 taken with R-bus 54. It may also perform logic operations on data received from memory unit 46 and/or register unit 114 via any of these lines. The arithmetic and logic operations performed are designated by ALU microinstructions from microprocessor 120 and are carried out in response to these microinstructions, shift clock control pulses from programmable clock 118, and control signal SCB from I/0 control 60. Information is also transferred from ALU 116 to A-register 122 via output lines 132 or to I/0 register 56, M-register 82, T-register 84, or any register of register unit 114 via T-bus 52 in response to microinstructions and control signals applied to these registers. If a carry results while ALU 116 is performing either one-bit serial binary arithmetic or four-bit parallel binary-coded-decimal arithmetic, the ALU issues a corresponding qualifier control signal QBC and QDC to microprocessor 120 via one of two output lines 152 and 154.

Programmable clock 118 includes a crystal-controlled system clock 156, a clock decoder and generator 158, and a control gate 160. System clock 156 issues regularly recurring clock pulses to clock decoder and generator 158 via output line 162. In response to these regularly recurring clock pulses from system clock 156 and to four-bit clock codes from microprocessor 120, clock decoder and generator 158 issues trains of n shift clock pulses to ALU 116, M-register 82, T-register 82, and all of the registers of register unit 114 via output line 164. These trains of n shift clock pulses are employed for shifting a corresponding number of bits of serial information into or out of any of these registers or for shifting a carry bit in the ALU. The number n of pulses in each of these trains may vary from one to 16 as determined by the number of bits of serial information required during each operation to be performed. In response to a control signal CCO from microprocessor 120, control gate 160 prevents any shift clock pulses from being applied to the ALU or any of these registers. Upon completion of each train of n shift clock pulses, clock decoder and generator 158 issues a ROM clock pulse to microprocessor 120 via output line 166 and an I/0 clock pulse to I/0 control 60 via output line 168. In response to the regularly recurring clock signal from system clock 56, clock decoder and generator 158 also issues correspondingly regularly recurring memory clock pulses to memory unit 46 via output line 170.

Microprocessor 120 selectively issues two I/0 microinstructions to I/0 control 60 via two output lines 172, six memory microinstructions to memory unit 46 via six output lines 174, 13 register microinstructions to register unit 114 via 13 output lines 176, and five ALU microinstructions to ALU 116 via five output lines 178. It also issues a four-bit clock code associated with each of these microinstructions to clock decoder 158 via four output lines 180. These microinstructions and associated clock codes are issued as determined by the control signal POP from the power supply, the 11 microprocessor qualifier control signals from Q-register 128, the four-bit primary address codes from Q-register 128, and the five microprocessor qualifier control signals from I/0 control 60, interrupt control 65, ALU 116, and P-register 126.

As shown in the simplified flow chart of FIG. 7, microprocessor 120 executes a hardware diagnostic routine (stored within the microprocessor itself) in response to the control signal POP. Upon completion of this diagnostic routine, ALU 116 issues the qualifier control signal QBC indicating whether or not the diagnostic routine was successful, microprocessor 120 thereupon responds to this qualifier control signal by entering the basic machine operating loop and issuing microinstructions causing a 16-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to Q-register 128. Microprocessor 120 thereupon sequentially responds to one or more additional qualifier control signals by issuing microinstructions and associated clock codes for executing the instruction then contained in Q-register 128 and causing another 16-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to the Q-register. When an instruction requiring multiple branching is contained in Q-register 128, microprocessor 120 issues a pair of microinstructions UTR and XTR causing the microprocessor to respond to a four-bit primary address code from the Q-register by issuing additional microinstructions and associated clock codes for executing the instruction contained in the Q-register.

As illustrated by the basic machine operating loop shown in the flow chart of FIG. 7, microprocessor 120 initially responds to the qualifier control signal QNR either by issuing microinstructions and associated clock codes for interrupting the basic machine operating loop and executing an I/0 service routine or by issuing microinstructions and associated clock codes for loading A/B flip-flop 148 with the information Q11 contained in Q-register 128. The manner in which microprocessor 120 responds is determined by the condition of the qualifier control signal QNR, which in turn indicates whether or not the basic machine operating loop should be interrupted.

Assuming the basic machine operating loop is not to be interrupted, microprocessor 120 loads the information Q11 into A/B flip-flop 148 and responds to the qualifier control signal QMR either by issuing microinstructions for transferring an address portion of the instruction contained in Q-register 128 from T-register 84 into M-register 82 or by responding to another qualifier control signal Q15. Again, the manner in which microprocessor 120 responds is determined by the condition of the qualifier control signal QMR, which in turn indicates whether or not the instruction contained in Q-register 128 is a memory reference instruction.

Assuming the instruction contained in Q-register 128 is a memory reference instruction, microprocessor 120 transfers the required address information into the M-register 82 and responds to qualifier control signal Q10 either by issuing microinstructions and associated clock codes to select the base page of the memory (i.e. page 0) or by issuing microinstructions and associated clock codes to select the current page of the memory (i.e. the page from which the instruction contained in Q-register 128 was obtained). In either case, the microprocessor then issues microinstructions as required to read data from the preset page of the memory at the address designated by the address information last transferred into M-register 82. Upon completion of this operation, microprocessor 120 responds to qualifier control signal Q15 by issuing additional microinstructions and associated clock codes to execute an indirect memory access operation if the condition of this qualifier control signal indicates that the address information contained in M-register 82 is indirect.

Assuming the address information contained in M-register 82 is direct (or upon completion of the indirect memory access operation), microprocessor 120 issues microinstructions and associated clock codes causing the microprocessor itself to respond to a four-bit primary address code from the Q-register. The microprocessor responds by issuing additional microinstructions and associated clock codes for executing whichever one of 10 possible memory reference instructions is contained in Q-register 128 and designated by the four-bit primary address code. Following execution of the designated memory reference instruction, microprocessor 120 issues microinstructions and associated clock codes causing another 16-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to Q-register 128 thereby beginning another cycle of the basic machine operating loop.

As illustrated by other possible paths of the basic machine operating loop shown in FIG. 7, microprocessor 120 sequentially responds to other qualifier control signals when other types of instructions are contained in Q-register 128. For example, when an I/0 instruction is contained in Q-register 128, microprocessor 120 sequentially responds to qualifier control signals QNR, QMR, Q15, Q10, and QRD by issuing microinstructions and associated clock codes to execute the I/0 instruction. It should be noted that the microprocessor qualifier control signals not shown in the simplified flow chart of FIG. 7 are variously contained within those flow chart blocks requiring decisions as will hereinafter become apparent.

KEY OPERATIONS

A11 operations performed by the calculator may be controlled or initiated by the keyboard input unit and/or by keycodes entered into the calculator from the keyboard input unit, the magnetic card reading and recording unit, or peripheral input units such as the marked card reader and stored as program steps in the program storage section of the RWM. The calculator responds to keycodes in basically the same manner whether obtaining them from the keyboard input unit or from the program storage section of the RWM. An operational description of the keyboard input unit is therefore now given with specific reference to FIGS. 1 and 8, except as otherwise indicated.

Line Switch

An on-off line switch 182, which may be considered as part of the keyboard input unit, controls the application of power to the calculator and hence initiation of the control signal POP from the power supply. The indicator lights 19 serve as a pilot light since at least two of them are always turned on while power is applied to the calculator.

As shown in FIG. 2, the calculator may be operated at 230, 200, 115, or 100 volts ± 10% as determined by a pair of line voltage selector switches mounted at rear panel 34 of the calculator housing and at a line frequency within the range of 48 to 66 Hertz. The calculator is provided with a 6-amp fuse and either a 1-amp fuse for operation at a line voltage of 200 or 230 volts ± 10% or a 2-amp fuse for operation at a line voltage of 100 or 115 volts ± 10%. It is also provided with a three-conductor power cable 184 which, when plugged into an appropriate AC power outlet, grounds the calculator housing. The maximum power consumption of the calculator is 150 voltamps. No more than a total of 610 voltamps may be drawn from AC power outlets 42 provided for peripheral units 28.

Mode Keys (RUN, PRGM, KEY LOG)

When the calculator is first turned on, it is automatically initialized and placed in a manual operating mode. If the calculator is switched to some other operating mode, it may subsequently be placed in the manual operating mode again by simply depressing the RUN mode key. In the manual operating mode, operation of the calculator is manually controlled by the user from the keyboard input unit. During this mode the output display unit displays a decimal numeric representation of the contents of the x-, y-, and z-registers (or of associated memory registers in which the actual or intended contents of the x-, y-, and z-registers are temporarily stored and, for simplicity of description, are then considered to be the contents of the x-, y-, and z-registers). The contents of the x-, y-, and z-registers are displayed adjacent to the corresponding register designators "keyboard x", "accumulator y", and "temporary z", respectively, in the display window. Depression of the RUN mode key also conditions the calculator for operation in an automatic operating mode, a first key-log printing mode, a program-list printing mode, a magnetic card reading mode, and a magnetic card recording mode as determined by other keys hereinafter explained. A run indicator light 19 positioned immediately below the RUN mode key is turned on when the calculator is operating in any of the RUN modes.

The PRGM mode key is depressed to place the calculator in a program entering mode. In this mode keycodes sequentially entered by the user from the keyboard input unit are stored as program steps in successive program-step registers of the program storage section of the RWM as specified by the user program counter. As described above, 500 program-step registers (user addresses 0000-0499) are available, and 1536 additional program-step registers (user addresses (0500-2035) may be made available, to the user for this purpose. The program step register into which each program step is to be stored and from which each program step is to be obtained in any program-related operation is always specified by the user program counter. Thus, before entering a program or subprogram into the calculator, the user program counter must be set to the address of the program step register into which it is desired to store the initial program step of the program or subprogram to be entered (this address is hereinafter referred to as the desired starting address nnnn of the program). This may be accomplished, when the calculator is in a keyboard-controlled run mode, by depressing the GO TO key followed by the decimal-digit keys 0-9 specifying the desired starting address nnnn of the program. If the desired starting address is 0000, this may also be accomplished, when the calculator is in the manual operating mode by simply depressing the END key.

Once the user program counter is set to the desired starting address nnnn, the user may proceed to enter the program or subprogram by sequentially performing basically the same key operations that he would normally perform in the manual operating mode. Thus no special language need be learned to program the calculator. During the program entering mode the output display unit displays a decimal numeric representation of the last-entered program step and its associated address and the addresses of the next two program steps to be entered and the present contents of those addresses.

Depression of the PRGM mode key also conditions the calculator for operation in a second key-log printing mode and the program-list printing mode as determined by other keys hereinafter explained. A program mode indicator light 19 positioned immediately below the PRGM mode key is turned on when the calculator is operating in any of the PRGM modes.

The KEY LOG mode key is depressed, when the calculator is in the manual operating mode, to place the calculator in the first key-log printing mode. In this mode, the output printer unit prints out an octal numeric representation of each keyboard operation as it is performed by the user. This provides a permanent record of all keyboard operations (including regular data print-out operations), as illustrated by the following example:

Keyboard entry Key log ______________________________________ 1 01 2 02 ↑ 27 3 03 4 04 + 33 5 05 ÷ 35 PRINT SPACE 45 5.00000 ______________________________________

If the alpha ROM module enabling the calculator to print out every alphabetic character and many symbols individually or in messages is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each keyboard operation as it is performed by the user. This is illustrated by the following example:

Keyboard entry Key log ______________________________________ 1 1 01 2 2 02 ↑ UP 27 3 3 03 4 4 04 + + 33 5 5 05 ÷ DIV 35 PRINT SPACE PNT 45 5.00000 ______________________________________

In the first key-log printing mode the output display unit displays the same information as during the manual operating mode.

The KEY LOG mode key is depressed, when the calculator is in the program entering mode, to place the calculator in the second key-log printing mode. In this mode the output printer unit prints out an octal numeric representation of each keycode as it is entered into the calculator from the keyboard input unit and a decimal numeric representation of the address at which each such keycode is stored as a program step in the program step in the program storage section of the RWM. This provides a permanent record of all keyboard-entered program steps, as illustrated by the following example:

Keyboard entry Key log ______________________________________ CLEAR 0000 --------- 20 1 0001 --------- 01 2 0002 --------- 02 ↑ 0003 --------- 27 3 0004 --------- 03 4 0005 --------- 04 + 0006 --------- 33 5 0007 --------- 05 0008 --------- 30 PRINT SPACE 0009 --------- 45 STOP 0010 --------- 41 END 0011--------- 46 ______________________________________

If the alpha ROM module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each keyboard-entered program step. This is illustrated by the following example:

Keyboard entry Key log ______________________________________ CLEAR 0000-- CLR 20 1 0001-- 1 01 2 0002-- 2 02 ↑ 0003-- UP 27 3 0004-- 3 03 4 0005-- 4 04 + 0006-- + 33 5 0007-- 5 05 ⇋ 0008-- XEY 30 PRINT 0009-- PNT 45 STOP 0010-- STP 41 END 0011-- END 46 ______________________________________

In the second key-log printing mode the output display unit displays the same information as during the program entering mode.

The KEY LOG mode key is a toggling on-off key (i.e. repeated depressions of the key alternately switch the calculator in and out of either the first or the second key-log printing mode). A key-log indicator light 19 positioned immediately below the KEY LOG mode key is turned on when the calculator is operating in either key-log printing mode.

Program Keys (LIST, LOAD, RECORD)

The LIST program key is depressed, when the calculator is in the manual operating mode, first key-log printing mode, second key-log printing mode, or program entering mode, to place the calculator in the program-list printing mode. In this mode, the output printer unit prints out an octal numeric representation of keycodes then stored as program steps in the program storage section of the RWM and a decimal numeric representation of the addresses of these program steps. These program steps and addresses are printed out in a list beginning with the address initially specified by the user program counter and ending with the address specified by the user program counter when an END program step is encountered or the STOP key is depressed. The user may select the starting address nnnn of the list by depressing to GO TO key followed by the decimal digit keys (0-9) designating the desired starting address nnnn, or simply by depressing the END key if the starting address is 0000. Similarily, the user may terminate the list at any time by depressing the STOP key. When the program-list operation is terminated either by an END program step or by depression of the STOP key, the calculator reverts to its original manual operating, first or second key-log printing, or program entering mode. If the program-list operation is terminated by an END program step, the user program counter specifies the address of the END program step. However, if the program-list operation is terminated by depression of the STOP key, the user program counter specifies the address of the next program step to have been encountered had the STOP key not been depressed.

The list printed out by the output printer unit serves as a permanent record of a sequence of program steps stored as a program, subprogram, or part thereof in the program storage section of the RWM and the address of these program steps. A typical list is illustrated by the right- and left-hand columns of numbers printed out on the strip of thermal-sensitive recording paper 22. If the alpha ROM module is plugged into the calculator, the output printer unit also prints out a mnemonic representation of each of these program steps. This is illustrated by the central column of alphameric characters printed out on the same strip of thermal-sensitive recording paper.

The LOAD program key is depressed, when the calculator is in the manual operating mode or the first key-log printing mode, to place the calculator in the magnetic card reading mode. During this mode, program steps recorded on one or more external magnetic cards 16 are read by the magnetic card reading and recording unit and stored in the program storage section of the RWM. In order to properly accomplish this program loading operation:

1. The user program counter is set to the desired starting address nnnn of the program storage section to be loaded. This may be accomplished by depressing the GO TO key followed by those decimal degit keys designating the desired starting address nnnn, or simply by depressing the END key if the desired starting address is 0000.

2. A recorded magnetic card 16 inserted into an input receptable 186 of the magnetic card reading and recording unit with the first side 187 to be read placed in the operative reading and recording position as shown in FIG. 1.

3. The LOAD key is depressed, thereby causing the magnetic card reading and recording unit to begin reading the first recorded side of the magnetic card and turning on an INSERT CARD indicator light 19 positioned immediately below and between the LOAD and RECORD program keys. This program reading operation will terminate and the INSERT CARD indicator light will turn off when an END (i.e. terminating) program step is read. The calculator will thereupon revert to the original manual operating or first key-log printing mode with the user program counter specifying the address of the END program step. In any case, the magnetic card will be partially ejected at an output receptacle 188 of the magnetic card reading and recording unit after each reading pass has been completed.

4. If the INSERT CARD indicator light remains on and the magnetic card reading and recording unit continues to run, the partially ejected magnetic card is retrieved from output receptacle 188, turned around, and the same magnetic card (or another magnetic card, as appropriate) inserted into input receptacle 186 with the next side 189 to be read placed in the operative reading and recording position. The magnetic card reading and recording unit thereupon begins reading this next recorded side. This program reading operation is repeated, if necessary, until it is terminated by reading an END program step. If desired, program reading operation may also be terminated by depressing the STOP key. The calculator will thereupon also revert to the original manual operating or first key-log printing mode, but with the user program counter specifying the address of the next program step to have been read and loaded into the program storage section of the RWM had the program reading operation not been so terminated.

When the program reading operation is terminated by an END program step, the user program counter is left specifying the address of this END program step so that additional program steps, subprograms, and programs may be chain-loaded into the calculator without extra effort by simply repeating steps 2, 3, and 4 above. The first additional program step will over-write the last encountered END program step thereby leaving only a final END program step at the completion of the composite program. Similarly, when the program reading operation is terminated by depressing the STOP key, the user program counter is also left specifying the address of the next program step to have been read so that additional program steps, subprograms, and programs may also be chain-loaded by simply repeating steps 2, 3, and 4 above.

The RECORD program key is depressed, when the calculator is in the manual operating mode or the first key-log printing mode, to place the calculator in the magnetic card recording mode. During this mode program steps stored in the program storage section of the RWM are recorded on one or more external magnetic cards by the magnetic card reading and recording unit. In order to properly accomplish this program recording operation:

1. The user program counter is set to the starting address nnnn of the stored program to be recorded. This may be accomplished by depressing the GO TO key followed by the decimal digit keys designating the required address nnnn, or simply by depressing the END key if the starting address is 0000.

2. A magnetic card 16 is inserted into input receptacle 186 of the magnetic card reading and recording unit with the first side 187 of the card to be recorded placed in the operative reading and recording position as shown.

3. The RECORD program key is depressed, thereby causing the magnetic card reading and recording unit to begin recording the stored program onto the first side of the magnetic card and turning on the INSERT CARD indicator light 19. This program recording operation will terminate and the INSERT CARD indicator light turn off when an END program step is recorded. The calculator will thereupon revert to the original manual operating or first key-log printing mode with the user program counter specifying the address of the END program step. In any case, the magnetic card will be partially ejected at output receptacle 188 of the magnetic card reading and recording unit after each recording pass has been completed.

4. If the INSERT CARD indicator light remains on, and the magnetic card reading and recording unit continues to run, the partially ejected card is retrieved from output receptacle 188, turned around, and the same magnetic card (or another magnetic card, as appropriate) inserted into input receptacle 186 with the next side 189 to be recorded placed in the operative reading and recording position. The magnetic card reading and recording unit thereupon begins recording on this next side. This program recording operation is repeated, if necessary, until it is terminated by recording an END program step. If no END program step is encountered, the calculator will continue to request more magnetic card recording passes until 2,036 program steps are recorded, regardless of the actual amount of program storage memory installed in the calculator. If desired, the recording operation can be terminated at any time by depressing the STOP key. The calculator will thereupon also revert to the original manual operating or first key-log printing mode but with the user program counter left specifying the address of the next program step to have been recorded had the recording operation not been so terminated.

Once the program is recorded on one or both sides of one or more magnetic cards 16, it may be protected against undesired erasures by punching out a perforated portion 190 at the leading edge of each side on which it is recorded. If a protected (notched) magnetic card is inserted into input receptacle 186 of the magnetic card reading and recording unit and the RECORD key depressed, the STATUS (error) indicator light 19 will turn on and will remain on while the magnetic card reading and recording unit drives the magnetic card to output receptacle 188, whereupon the STATUS light will be extinguished. Nothing will be recorded on the protected magnetic card during this recording pass nor will there be any impairment of the calculator itself or the information previously recorded on the protected magnetic card. The calculator and the magnetic card unit will simply continue to wait for a nonprotected magnetic card to be inserted into input receptacle 186 for the magnetic card reading and recording unit.

Automatic Operating Mode Control Keys (CONTINUE, STOP, END, PAUSE)

The CONTINUE key is depressed, when the calculator is in the manual operating mode or the first key-log printing mode, to start the automatic execution of a program or subprogram stored within the program storage section of the RWM. Automatic execution begins at the address specified by the user program counter. Thus, in order to execute a desired program or subprogram stored within the program storage section of the RWM:

1. The user program counter is set to the starting address nnnn of the desired program or subprogram. This is accomplished by depressing the GO TO key followed by those decimal digit keys designating the starting address nnnn of the desired program. If the starting address is 0000, this may be accomplished by simply depressing the END key.

2. The CONTINUE key is depressed, when the calculator is in the manual operating mode or the first key-log printing mode, to place the calculator in the automatic operating mode and begin automatic execution of the stored program or subprogram at the address nnnn specified by the user program counter. Automatic execution will continue until a STOP or END program step is encountered or a STOP key is depressed as described below.

The STOP key is depressed, when the calculator is in the automatic operating mode, to halt the automatic execution of a stored program or subprogram immediately after completion of the program step then being executed. Automatic execution of a stored program or subprogram is similarly halted when a STOP program step is encountered. In either case the calculator will thereupon revert to the original manual operating or first key-log printing mode with the program counter specifying the address of the next program step to be encountered. The user may then operate the calculator in the manual operating mode to enter data required by the program being executed or to perform other calculations. So long as the user does not depress the GO TO or END key or perform some other operation altering the last setting of the user program counter, he may resume automatic operation of the calculator at any time by simply depressing the CONTINUE key again.

As described above, the STOP key may also be depressed, when the calculator is in the program-list printing mode, the magnetic card reading mode, or the magnetic card recording mode to halt the program-list printing operation, the magnetic card reading operation or the magnetic card recording operations, respectively. In each of these cases the calculator will revert to the mode it was in immediately prior to the halted operation with the user program counter specifying the address of the next program step to have been printed, read, or recorded had the STOP key not been depressed.

The END key is depressed, when the calculator is in the manual operating mode, to set the user program counter to address 0000 in the program storage section of the RWM (this is equivalent to depressing the GO TO, 0, 0, 0, and 0 keys). An END program step terminates the automatic execution of a stored program by the calculator and resets the user program counter to the first available address 0000 in the program storage section of the RWM. The calculator thereupon reverts to the original manual operating or first key-log printing mode, from which automatic operation was initiated. Automatic execution may then be resumed by depressing the CONTINUE key, if the desired starting address is 0000 or by repeating steps 1 and 2 described above in connection with the CONTINUE key if the desired starting address is not 0000. An END program step also clears any subroutine return-address to which return has not by then been made. As described above, it also terminates the program listing, magnetic card reading, and magnetic card recording operations.

The PAUSE key is typically used only as a program step. Automatic execution of a stored program or subprogram is automatically halted for a 1/4 second pause interval whenever a PAUSE program step is encountered or the PAUSE key is depressed. This enables partial results of a calculation to be displayed by the output display unit during automatic execution of the stored program or subprogram. Successive PAUSE program steps may be employed to increase the duration of the pause interval by 1/4 second increments. Automatic execution of the stored program or subprogram automatically resumes after the pause interval.

A PAUSE program step may also be used as a conditional step, permitting the user to stop the automatic operation of the calculator immediately after execution of any PAUSE program step. This is accomplished by simply depressing any key (other than STOP) during automatic execution of the program until the PAUSE program step has been executed. In other words, a PAUSE program step immediately followed by depression of any key other than STOP has the same effect as depressing STOP, with the advantage that automatic execution of a stored program or subprogram may thereby be precisely halted at one or more predetermined program steps if the user so desires. Automatic execution of the stored program may then be resumed by depressing the CONTINUE key.

Decimal Display Keys (FLOAT, FIX () )

These keys are employed to control the format of numbers displayed by the output display unit when the calculator is in the manual operating and first key-log printing modes. Either a fixed or a floating decimal point format may be used. A fixed point indicator light 19 positioned immediately below the FIX () key is turned on when the fixed decimal point format is being used. Similarly, a floating point indicator light positioned immediately below the FLOAT key is turned on when the floating decimal point format is being used.

In the fixed decimal point format, numbers appear in the form in which they are most commonly written. The decimal point is fixed in its correct position. In the floating decimal point format, numbers appear in a normalized form with the decimal point located immediately after the most significant non-zero digit of the normalized number. Each normalized number is followed by an exponent comprising a positive or negative power of 10 and representing the number of digit places that, and the direction in which, the decimal point must be moved to express the normalized number in the fixed decimal point format. The following examples illustrate the relationship between numbers expressed in both the fixed and floating decimal point formats.

______________________________________ FIXED DECIMAL FLOATING DECIMAL POINT FORMAT POINT FORMAT ______________________________________ 1234.5 = 1.2345 × 103 0.0012345 = 1.2345 × 10-3 -1.2345 = -1.2345 × 100 ______________________________________

When the calculator is turned on and automatically initialized, the output display unit displays numbers in the floating decimal point format. If the output display is switched to the fixed decimal point format, it may subsequently be switched back to the floating decimal point format by simply depressing the FLOAT key. Every number displayed in the floating decimal point format includes the sign (if negative) and 10 most significant digits of the normalized number followed by the sign (if negative) of the exponent and two exponent digits. This is illustrated by the following examples:

NUMBERS TO FLOATING DECIMAL BE DISPLAYED POINT DISPLAY ______________________________________ 1234.5 1.234500000 03 0.0012345 1.234500000 -03 -1.2345 -1.234500000 00 ______________________________________

The output display may be changed to the fixed decimal point format by depressing the FIX () key followed by a decimal digit key designating the desired number n (0-9) of digits to be displayed to the right of the decimal point. Less significant digits are not displayed, and the least significant digit to be displayed is rounded up if the nondisplayed next least significant digit is five or greater. This is illustrated by the following examples for different values of n:

NUMBERS TO VALUES FIXED DECIMAL BE DISPLAYED OF n POINT DISPLAY ______________________________________ 123.456784 2 123.46 -6.703256 2 -6.70 123.456784 5 123.45678 -6.703256 5 -6.70326 123.456784 0 123. -6.703256 0 -7. ______________________________________

If the FIX () key is depressed but not followed by a decimal digit key, the calculator will automatically treat the next key depressed as being the 0 key (i.e., n will thereupon equal 0 as in the last example).

Numbers of up to (and including) 10 significant digits and their signs (if negative) may be displayed in the fixed decimal point format. Thus, (10-n) digits may be displayed to the left of the decimal point. If a number to be displayed has more than (10-n) digits to the left of the decimal point (i.e. is too large for the selected value of n), the display of that number (not the whole display) overflows and thereupon reverts to the floating decimal point format. This is illustrated by the fixed decimal point display of FIG. 1 wherein the numbers contained in the x and y registers have overflowed and are therefore displayed in the floating decimal point format. It is also illustrated by the following example:

NUMBER TO VALUE ACTUAL BE DISPLAYED OF n NUMBER DISPLAYED ______________________________________ 1234567.89 5 1.23456789 06 ______________________________________

If the first non-zero digit of a number to be displayed is more than n digits to the right of the decimal point (i.e. is too small for the selected value of n), the display of that number (not the whole display) underflows. In this case only zeros will be displayed. This is illustrated by the following example:

NUMBER TO VALUE ACTUAL BE DISPLAYED OF n NUMBER DISPLAYED ______________________________________ 0.0000012 3 0.000 ______________________________________

Regardless of the way in which numbers are displayed, the calculator always stores all numbers and performs all calculations in the floating decimal point format. Furthermore, regardless of the number of digits entered or displayed, each number is stored with 12 significant digits, their associated sign, a two-digit exponent, and its associated sign. Up to (and including) 10 significant digits, their associated sign, the two-digit exponent, and its associated sign can be displayed (however, no sign is displayed for positive numbers or exponents). The remaining two digits (called guard digits) are not displayed. They are employed to maintain greater than 10-place accuracy during calculations and also to automatically round the tenth displayed digit.

The calculator has a dynamic range of from ±10-98 to ±9.999999999(99) × 1098. Whenever this range is exceeded during a calculation the STATUS indicator light 19 turns on.

Numeric Data Entry Keys (0-9), ., ENTER EXP, CHG SIGN, π)

The decimal digit keys 0-9 are depressed to enter numbers into the x-register. Numbers are entered serially, the last digit entered becoming the least significant digit. For example, the number 1325 is entered by sequentially depressing the decimal digit keys 1, 3, 2, and 5. A number entered into the x-register is terminated as soon as any non-data-entry key is depressed. Another number entered into the x-register will automatically replace a terminated number, but will become a part of any non-terminated number.

The decimal point (.) key is depressed to enter the decimal point into the x-register. For example, the number 1.234 is entered by sequentially depressing the 1, ., 2, 3, and 4 keys. Regardless of the display format, it is not necessary to use the decimal point key when entering integers. If the decimal point key is not used, the decimal point will be assumed to have followed the last-entered digit. When the fixed decimal point display format is used, the calculator automatically positions the decimal point. Similarly, when the floating decimal point display format is used the calculator automatically corrects the exponent according to the position of the decimal point.

The ENTER EXP key is depressed followed by one or two decimal digit keys to enter a one- or two-digit exponent (power of 10) into the x-register, the last digit entered becoming the least significant digit. If a third digit is entered, it will terminate entry of the exponent and begin a new numeric data entry. A non-terminated number in the x-register may be multiplied directly by successive powers of ten by simply entering successive exponents. For example, the product of 8.3 × 102 × 1014 may be obtained by sequentially depressing the 8, ., 3, ENTER EXP, 2, ENTER EXP, 1, and 4 keys. If the ENTER EXP key is depressed as the first key of a numeric data entry (i.e. before any of the decimal digit keys have been depressed or following a terminated number), the number 1 is entered into the x-register. For example, the number 1 × 1016 may be entered by depressing the ENTER EXP, 1, and 6 keys.

The CHG SIGN key is depressed to change the sign of any terminated or unterminated number in the x-register. If the CHG SIGN key is depressed as the first key of a numeric data entry, it changes the sign of the number then in the x-register (whatever the sign may be) and, once that number is replaced by the first digit of the new data entry, it prefaces the new data entry with a negative sign. This is illustrated by the following example:

______________________________________ KEYS DEPRESSED CONTENTS OF x-REGISTER ______________________________________ -123.45 CHG SIGN 123.45 6 -6. 7 -67. ______________________________________

The CHG SIGN key is also depressed immediately following the ENTER EXP key (or the last-entered digit of the exponent) to enter negative exponents into the x-register. For example, the number 8.3 × 10-2 × 104 × 10-12 may be entered by sequentially depressing the keys 8, ., 3, ENTER EXP, CHG SIGN, 2, ENTER EXP, 4, ENTER EXP, CHG SIGN, 1, and 2 keys and the number 1 × 10-16 may be entered by depressing the ENTER EXP, 1, 6, and CHG SIGN keys.

The π key is depressed to enter the value of π (i.e. 3.14159265360) into the x-register.

Clear keys (CLEAR x, CLEAR)

The CLEAR x key clears (i.e. sets to zero) the x-register. It does not affect any other registers.

The CLEAR key clears the x-, y-, and z- (working) registers, clears the a- and b- (data storage) registers, and clears (or resets) the flag, which can be set by the SET FLAG key as hereinafter explained. It does not affect any other registers.

When the calculator is switched on, all of the working, program, and data storage registers of the RWM are automatically cleared. Any terminated numbers subsequently stored in them will automatically be cleared and replaced by any new data entry.

Working Register Control Keys (↑, ↑, ROLL ↑, x y)

The working register control keys are used to reposition the contents of the x-, y-, and z-registers. They do not affect any other registers.

When the ↑ key is depressed, the contents of the y-register shift to the z-register and the contents of the x-register appear in both the x- and y-registers. The contents of the z-register are lost.

When the ↑ key is depressed, the contents of the y-register shift to the x-register and the contents of the z-register appear in both the y- and z-registers. The contents of the x-register are lost.

When the ROLL ↑ key is depressed, the contents of the x-register shift to the y-register, the contents of the y-register shift to the z-register, and the contents of the z-register shift to the x-register. No information is lost.

The x y key is depressed to exchange the contents of the x- and y-registers. The contents of the z-register are unaffected by this operation.

Arithmetic Keys (+, -, ×) ÷)

These four keys are used to perform working register arithmetic operations in which the contents of the x- and y-registers are employed as operands. The results of these arithmetic operations are stored in the y-register and the contents of the x-register remain unchanged by the arithmetic operations performed. These four keys do not affect any other registers.

The + key is depressed to add the number in the x-register to the number in the y-register, the sum appearing in the y-register.

The - key is depressed to subtract the number in the x-register from the number in the y-register, the difference appearing in the y-register.

The × is depressed to multiply the number in the y-register by the number in the x-register, the product appearing in the y-register.

The ÷ key is depressed to divide the number in the y-register by the number in the x-register, the quotient appearing in the y-register.

The use of these keys and the working register control keys is illustrated by the following method of computing

[(3 × 4) + (8 - 9)]/[(8 × 2) - 6] = 1.1 :

KEYS CONTENTS OF CONTENTS OF CONTENTS OF DEPRESSED x-REGISTER y-REGISTER z-REGISTER ______________________________________ CLEAR 0 0 0 3 3 0 0 ↑ 3 3 0 4 4 3 0 × 4 12 0 ROLL↑ 0 4 12 8 8 4 12 ⇋ 4 8 12 9 9 8 12 - 9 -1 12 ↑ -1 12 12 + -1 11 12 ROLL↑ 12 -1 11 8 8 -1 11 ⇋ -1 8 11 2 2 8 11 × 2 16 11 6 6 16 11 - 6 10 11 ↑ 10 11 11 ÷ 10 1.1 11 ______________________________________

The answer, appearing in the y-register, is underlined.

Unary Function Keys (√x, x2, 1/x, int x, CHG SIGN)

These five keys are used to perform unary functions in which the contents of the x-register are employed as the argument. The results of the unary functions performed are placed in the x-register. These five keys do not affect any other registers.

The √x key is depressed to calculate the square root of the number in the x-register. If the number is negative, the square root of its absolute value is calculated and the STATUS indicator light 19 turned on. The STATUS indicator light remains on until the next key is depressed.

The x2 key is depressed to calculate the square of the number in the x-register. If the number is greater than √10 × 1049, the number 9.99999999999 × 1098 is placed in the x-register and the STATUS indicator light 19 turned on. The STATUS indicator light remains on until the next key is depressed.

The 1/x key is depressed to calculate the reciprocal of the number in the x-register. For example, 1/9.8 may be calculated by sequentially depressing the 9, ., 8, and 1/x keys.

The int x key is depressed to truncate the fractional part of the number in the x-register. It does not affect the sign of the integer part of the number. For example, if the number -5.9 is contained in the x-register when the int x key is depressed, the number -5.0 will remain.

The CHG SIGN key has already been described above in connection with the numeric data entry keys.

Data-Storage and Register-Transfer Keys (a, b, x➝(), y➝(), x➝(), y (), INDIRECT)

These keys are variously used to perform direct data storage and recall, direct storage-register arithmetic, indirect data storage and recall, and indirect storage-register arithmetic operations. As illustrated below, the a and b keys are depressed following any of the remaining five keys of this group to specify the a- and b-registers, respectively. The a and b keys may also be used to directly recall the contents of the a- and b-registers, respectively, to the x-register without changing the contents of the a- and b-registers themselves. Either of these functions of the a and b keys may be performed in response to a single keystroke thereof. For example, the contents of the b-register may be directly recalled to the x-register by simply depressing the b key alone. As noted above the contents of the b-register itself will remain unchanged by this recall operation.

The x➝(), y➝(), x➝(), and y () keys are used to control the transfer of numeric data from the x- and y-registers to the a- and b-registers and 49 additional storage registers available to the user (at user addresses 000-048) in the data storage section of the RWM and from these storage registers to the x- and y-registers. If the 60 optional storage registers included in the data storage section of the RWM (at user addresses 049-108) are made available to the user, these same four keys may also be used to control the transfer of numeric data from the x- and y-registers to these optional storage registers and from them to the x- and y-registers.

The specific storage register to or from which numeric data is transferred by these four keys is specified by the key or keys depressed immediately following them. Accordingly, the a key is used to specify the a-register, the b key to specify the b-register, and the decimal digit keys 0-9 to selectively specify any of the available storage registers at user addresses 000-108 of the data storage section of the RWM. For simplicity of description, the available storage registers at user addresses 000-108 will hereinafter be referred to by their addresses (i.e. the storage register at any available address nnn will be referred to as register nnn). If a non-existant or nonavailable storage register is designated, the STATUS indicator light is turned on, no data transfer or arithmetic operation is performed, and the operation of the calculator halts. (If such a register is designated while the calculator is automatically executing a stored program, the program-counter specifies the program step immediately following the improper operation.)

The x➝() key is depresssed followed by the a key, the b key, or decimal digit keys n, n, n to directly store the contents of the x-register in the a-register, the b-register, or register nnn respectively. In any case, the contents of the x-register remain unchanged by this operation. For example, π may be stored directly in the b register by sequentially depressing the π, x➝(), and b keys. Similarly, π may be stored directly in register 027, by sequentially depressing the π, x➝ (), 0, 2, and 7 keys. In each of these examples, π will also remain in the x-register.

The y➝() key is depressed followed by the a key, the b key, or decimal digit keys n, n, n to directly store the contents of the y-register in the a-register, the b-register, or register nnn, respectively. In any case, the contents of the y-register remain unchanged by this operation. For example, a number contained in the y-register may be stored directly in register 000, without changing the contents of the y-register, by sequentially depressing the y➝(), 0, 0, and 0 keys.

The x➝() key is depressed followed by the a key, the b key, or decimal digit keys n, n, n, to directly recall the contents of the a-register, the b-register, or register nnn, respectively, to the x-register. In any case, the contents of the recalled register remain unchanged by this operation. For example, the contents of register 012 may be recalled to the x-register, without changing the contents of register 012, by sequentially depressing the x➝(), 0, 1, and 2 keys. Recall from the a- or b-register to the x-register may be accomplished in the same manner as described above, by simply depressing the a or b key alone.

The y () key is depressed followed by the a key, the b key, or decimal digit keys n, n, n, to exchange the contents of the y-register with the contents of the a-register, the b-register, or register nnn, respectively. For example, a number in the y-register may be exchanged with a number in register 048 by depressing the y (), 0, 4, and 8 keys.

The direct storage and recall operations performed by the x➝(), y➝(), x➝(), and y () keys may be conveniently summarized by employing the following notation:

x➝() a y➝() b x➝() nnn y⇋()

In this notation each pair of braces implies that any one of the enclosed group of key operations or storage registers may be selected. The order of the successive pairs of braces from left to right specifies the key-sequence required to perform the selected key operation with the selected storage register. Thus, any of the key operations enclosed in the left-hand pair of braces may be employed with any of the storage registers enclosed in the righthand pair of braces by first depressing the key performing the selected key operation and then depressing the key or keys designating the selected storage register. The usefullness of these direct storage and recall operations is illustrated by the following method of multiplying a series of numbers n1, n2, etc. by a constant K, where n1 = 3, n2 = 11.2, etc. and K = 1.684:

CONTENTS CONTENTS CONTENTS KEYS OF OF OF DEPRESSED x-REGISTER y-REGISTER a -REGISTER ______________________________________ CLEAR 0 0 0 1, 0, 6, 8, 4, 1.684 0 0 y⇋(), a 1.684 0 1.684 3 3 0 1,684 ↑ 3 3 1,684 a 1.684 3 1.684 × 1.684 5.0520 1.684 1, 1, ., 2 11.2 5.0520 1.684 ↑ 11.2 11.2 1.684 a 1.684 11.2 1.684 × 1.684 18.8608 1.684 ______________________________________

The answers, appearing in the y-register, are underlined.

The x➝(), y➝(), x➝(), and y () keys may also be employed with the +, -, ×, and ÷ arithmetic keys to perform direct register-arithmetic operations in which the contents of the x-register or the y-register are employed as one operand and the contents of the a-register, the b-register, or register nnn are employed as the other operand. These direct register-arithmetic operations may be summarized as follows by using the above-described notation:

x➝() + a y➝() - b x➝() × nnn y⇋() ÷

Thus, the x➝() key may be employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the x-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the selected storage register without recalling the contents of the selected storage register and without changing the contents of the x-register. For example, the contents of the x-register may be subtracted from the contents of the b-register by sequentially depressing the x➝(), -, and b keys. The difference is stored in the b-register, and the contents of the x-register remain unchanged by the operation. Similarly, the contents of register 042 may be divided by the contents of the x-register by sequentially depressing the x➝(), ÷, 0, 4, and 2 keys. The quotient is stored in register 042, and the contents of the x-register itself remain unchanged by the operation.

The y➝() key may be similarly employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the y-register and any of the storage registers enclosed by the third pair of braces and store the result in the selected storage register without recalling the contents of the selected storage register and without changing the contents of the y-register. For example, the contents of the y-register may be added to the contents of the a-register by sequentially depressing the y➝(), +, and a keys. The sum is stored in the a-register, and the contents of the y-register remain unchanged by the operation. Similarly, the contents of register 038 may be multiplied by the contents of the y-register by sequentially depressing the y➝(), x, 0, 3, and 8 keys. The product is stored in register 038, and the contents of the y-register remain unchanged by the operation.

The x➝() key may be employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the x-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the x-register without changing the contents of the selected storage register. For example, the contents of the a-register may be added to the contents of the x-register by sequentially depressing the x➝(), +, and a keys. The sum is stored in the x-register, and the contents of the a-register remain unchanged by the operation. Similarly, the contents of the x-register may be multiplied by the contents of register 022 by sequentially depressing the x➝(), x, 0, 2, and 2 keys. The product is stored in the x-register, and the contents of register 022 remain unchanged by the operation.

The y () key may be employed to directly perform any of the arithmetic operations enclosed by the second pair of braces upon the contents of the y-register and the contents of any of the storage registers enclosed by the third pair of braces and store the result in the y-register without changing the contents of the selected storage register (i.e. the y () may be used as though it were a y➝() key in performing register-arithmetic operations).

For example, the contents of the b-register may be subtracted from the contents of the y-register by sequentially depressing the y (), -, and b keys. The difference is stored in the y-register, and the contents of the b-register remain unchanged by the operation. Similarly, the contents of the y-register may be divided by the contents of regiters 039, by sequentially depressing the y (), ÷, 0, 3, and 3 keys. The quotient is stored in the y-register, and the contents of register 039 remains unchanged by the operation.

The INDIRECT key is used with the above-described data-storage and register-transfer keys to perform indirect data-storage and recall and indirect register-arithmetic operations, in which the contents of a directly-addressed register (e.g. the a-register, the b-register or any of the registers nnn) are employed as the address of an indirectly-addressed storage register (e.g. any of the other storage registers nnn) to be used in these operations. When indirectly addressing any of the storage registers 000 through 048 or 108, care must be taken to insure that the directly-addressed register contains the proper address nnn of the indirectly addressed-register nnn. The indirect address used is the absolute value of the integer part of the contents of the directly addressed register. Thus, 1.732 will be treated as the address of register 001, -6.99 as the address of register 006, 0.999 as the address of register 000, and 106.75 as the address of register 106. Since the storage registers may only contain numeric data, the a- and b-registers may not be used as the indirectly-addressed registers in these operations.

The indirect data storage and recall operations may be summarized as follows by again using the above-described notation without braces for the INDIRECT key:

{x ➝() a {y➝() INDIRECT b {x➝() nnn {y⇋()

Thus, the x➝() and y➝() keys may be employed with the INDIRECT key to indirectly store the contents of the x- and y-registers, respectively in any storage register nnn designated by the contents of any of the other data storage registers. Moreover, this may be accomplished without changing the contents of the x- and y-registers or of the directly addressed storage register. For example, the contents of the x-register may be indirectly stored in the storage register designated by the contents of the a-register by sequentially depressing the x➝(), INDIRECT, and a keys. The contents of the x-register and the a-register remain unchanged by this operation. Similarly, the contents of the y-register may be indirectly stored in the storage register designated by the contents of register 022 by sequentially depressing y➝(), INDIRECT, 0, 2, and 2 keys. The contents of the y-register and register 022 remain unchanged by this operation.

The x➝() key may be similarly employed with the INDIRECT key to indirectly recall to the x-register the contents of any storage register nnn designated by the contents of any of the other storage registers. This is accomplished without changing the contents of either the directly- or indirectly-addressed storage register. For example, the contents of the register nnn designated by the contents of the b-register may be indirectly recalled to the x-register by sequentially depressing the x➝(), INDIRECT, and b keys. The contents of the b-register and of the indirectly-addressed register remain unchanged by this operation.

The y () key may be employed with the INDIRECT key to indirectly exchange the contents of the y-register with the contents of any storage register nnn designated by the contents of any of the other storage registers. This is accomplished without changing the contents of the directly-addressed storage register. For example, the contents of the y-register may be indirectly exchanged with the contents of the register designated by register 041 by sequentially depressing the y (), INDIRECT, 0, 4, and 1 keys. The contents of register 041 remain unchanged by this operation.

The indirect register-arithmetic operations may be summarized as follows:

{x➝() + a {y➝() - INDIRECT b {x➝() × nnn {y⇋() ÷

In connection with the indirect register arithmetic operations it should be noted that the INDIRECT key may also be depressed immediately after the selected arithmetic key. Thus, the indirect register-arithmetic operations may also be summarized as follows:

{ x➝() + a {y➝() - INDIRECT b {x➝() × nnn {y⇋() ÷

Thus, any of the x ➝(), y➝(), x➝(), and y () keys may be employed with the INDIRECT key and any of the arithmetic keys to indirectly perform register-arithmetic operations employing the contents of either the x- or the y-register as one operand and the contents of any of the storage registers nnn designated by the contents of any of the other storage registers as the other operand. In the case of the x➝() and y➝() keys, the results of these operations are stored in the indirectly addressed storage register nnn, and the contents of the x- and y-registers and the directly-addressed registers are not changed. Similarly, in the case of the x➝() and y () keys, the results of these operations are stored in the x- and y-registers, respectively, and the contents of the directly and indirectly addressed registers are not changed.

For example, the contents of the x-register may be added to the contents of the register nnn designated by the contents of the a-register by sequentially depressing the x➝(), INDIRECT, +, and a keys. The sum is stored in the indirectly-addressed register nnn, and the contents of the x-register and the a-register remain unchanged by this operation. Similarly, the contents of the storage register nnn designated by the contents of register 014 may be multiplied by the contents of the y-register by sequentially depressing the y➝(), x, INDIRECT, 0, 1, and 4 keys. The product is stored in the indirectly-addressed storage register nnn, and the contents of the y-register and register 014 remain unchanged by the operation. Similarly, the contents of the register nnn designated by the contents of the b-register may be subtracted from the contents of the x-register by sequentially depressing the x➝(), INDIRECT, -, and b keys. The difference is stored in the x-register, and the contents of the b -register and the indirectly-addressed register remain unchanged by the operation. As a last example, the contents of the y-register may be divided by the contents of the register nnn designated by the contents of register 008 by sequentially depressing the y (), INDIRECT, ÷, 0, 0, and 8 keys. The quotient is stored in the y-register, and the contents of register 008 and the indirectly-addressed register nnn remain unchanged by this operation.

Multiple-level indirect addressing may be performed to any desired level in the above described indirect data storage and recall and indirect register arithmetic operations by sequentially depressing the INDIRECT key once for each desired level. Multiple-level indirect data storage and recall may be summarized as follows:

{x➝() a {y➝() INDIRECT ....INDIRECT b {x➝() nnn {y⇋()

Thus, for example, the contents of the x-register may be indirectly stored in the contents of register 017 designated by the contents of register 003 in turn designated by the contents of the a-register by sequentially depressing the x➝(), INDIRECT, INDIRECT, and a keys. The contents of the x-register, the a-register, and register 003 remain unchanged by this operation. Similarly, the contents of register 046 designated by the contents of register 031 in turn designated by the contents of register 000 in turn designated by the contents of register 025 may be exchanged with the contents of the y-register by sequentially depressing the y (), INDIRECT, INDIRECT, INDIRECT, 0, 2, and 5 keys. The contents of registers 025, 000 and 031, remain unchanged by this operation.

Multiple level indirect register-arithmetic may be similarly summarized as follows:

{x➝() + a {y➝() - INDIRECT...INDIRECT b {x➝() × nnn {y⇋() ÷ OR {x➝() + a {y➝() - INDIRECT...INDIRECT b {x➝() × nnn {y⇋() ÷

Thus, assuming, for example, that the 60 optional storage registers 049-108 are available to the user, the contents of the y-register may be subtracted from the contents of register 108 designated by the contents of register 082, in turn designated by the contents of register 049 by sequentially depressing the y➝(), INDIRECT, INDIRECT, -, 0, 4, and 9 keys. The difference is stored in register 108 and the contents of the y-register, register 049, and register 082 remain unchanged by this operation. Similarly, the contents of the x-register may be divided by the contents of register 106 designated by the contents of register 056 in turn designated by the contents of the b-register by sequentially depressing the x➝(), ÷, INDIRECT, INDIRECT, INDIRECT, and b keys. The results are stored in the x-register, and the contents of the b-register and registers 003, 056, and 106 remain unchanged by this operation.

Numeric Address Termination

As described above, each of the available numerically-addressed storage registers 000 through 048 or 108 employed in the foregoing data-storage and register-transfer operations is properly addressed by selectively depressing the decimal digit keys to specify its three-digit address. Upon entry of the third digit, the numeric address is automatically terminated. Any immediately following digit entries are therefore not intrepreted as part of the numeric address, but rather as the beginning of a new data entry. Thus, for example, if the x➝(), 1, 0, 3, 2, and 5 keys are sequentially depressed, the contents of the x-register are stored in register 103, and the number 25 is entered into the x-register. Similarly, if the y➝(), +, 0, 0, 2, 1, and + keys are sequentially depressed, the contents of the y-register are added to the contents of register 002, and the number 1 is entered into the x-register and thereupon added to the contents of the y-register.

A numeric address may also be terminated, without entering leading zeros of the address, by depressing any non-numeric key except the STEP PRGM key or, if the calculator is in the manual operating or first key-log printing mode, the CONTINUE key. However, most of the terminating key entries that may be used will also be executed. For example, if the x➝(), 2, and + keys are sequentially depressed, the contents of the x-register are stored in storage register 002 and also added to the contents of the y-register. Similarly, if the y➝(), +, 3, 8, and a keys are sequentially depressed, the contents of the y-register are added to the contents of register 038, and the contents of the a-register are recalled to the x-register.

When the calculator is in the manual operating or first key-log printing mode, the STOP key may be used to terminate a numeric address if a no-operation address-terminating key entry is desired. For example, by simply depressing the x➝(), 3, and STOP keys the contents of the x-register may be stored in register 003 without performing any other operation. Similarly, when formulating or entering a program by which the calculator is to be controlled in the automatic operating mode, a CONTINUE program step may be employed to terminate a numeric address if a no-operation address-terminating program step is desired. For example, if the program steps y➝(), x, 2, 9, CONTINUE, and 3 are sequentially encountered when the calculator is in the automatic operating mode, the contents of register 29 are multiplied by the contents of the y-register, and the product is stored in register 29. No operation is performed by the CONTINUE program step, and the next program step 3 is stored in the x-register as the beginning of a new data entry.

Since every numeric storage register except optional registers 100-108 may be uniquely specified by less than three digits, these abbreviated address-termination features permit significant reductions in the number of key-operations and program steps required to perform many calculations. Moreover, these same address termination features may be used in connection with the four-digit numeric addresses of the program storage section of the RWM to achieve still further reductions in the number of key-operations and program-steps required to perform many calculations.

Program-Control Keys (GO TO, IF x<y, IF x=y, IF x>y, IF FLAG,

SET FLAG, LABEL, SUB/RETURN)

All of the previously-described keys except the FLOAT, FIX(), RUN, PRGM, KEY LOG, LIST, LOAD, and RECORD keys may be employed both for controlling the operation of the calculator during the manual operating and first key-log printing modes and for entering program steps into the calculator during the program entering and second key-log printing modes. When the calculator is in the manual operating mode, the user may continuously observe the output display of the contents of the x-, y-, and z-registers and, in accordance with his observations, make his own decisions about what to do next at any stage of the calculation. However, this is not possible when the calculator is executing a stored program at high speed in the automatic operating mode. The above eight program-control keys have therefore been provided to permit the calculator itself to test calculated quantities and make decisions based on those tests during the automatic execution of an internally-stored program. These eight keys may be used to permit unconditional branching (or transfers), conditional branching (or transfers), symbolic or labelled branching, storage of "yes-no" information is a flag and conditional branching based on that "yes-no" information at a later stage in the execution of a program, and unconditional or conditional branches to pre-defined program routines with return to the main program sequence upon completion.

Branching instructions in a program cause the user program counter to specify an address other than the next sequential address in the program storage section of the RWM, whereupon execution of the program continues sequentially from the new address. If a branch is conditional, the calculator makes a decision, based upon a specified condition, whether or not to branch. However, if the branch is unconditional, the calculator has no option, and must branch to the address specified in the program (e.g. by a GO TO program step followed by a numeric address nnnn).

The GO TO key is depressed followed by decimal digit keys specifying a selected four-digit address nnnn in the program storage section of the RWM to set the user program counter to the selected address nnnn. When this sequence of keycodes is encountered as a sequence of program steps, an unconditional branch is made to the address indicated and the program step stored at that address is executed. Execution of the program then automatically continues to run from that address.

For simplicity of description the terms "keys" and "program steps" will hereinafter be used synonomously since the remaining keys of this group are used almost exclusively to enter keycodes into the calculator as program steps during the program entering mode of the calculator. All of the program steps so entered are automatically executed during the automatic operating mode of the calculator.

The four IF keys are used for conditional branching. The IF x<y, IF x=y, and IF x>y keys compare the numeric values contained in the x- and y-registers to determine if the number in x is less than the number in y, equal to the number in y, or greater than the number in y respectively. The IF FLAG key tests the condition (yes-no) of the flag, which is controlled by the SET FLAG key hereinafter explained. There can be only two possible results to each test made by each of these four keys. The condition tested is either "met" (YES) or "not met" (NO).

When the condition tested is met (YES), the next program step following the IF is automatically executed. However, when the condition tested is not met (NO), the calculator automatically skips (ignores) the next four program steps and continues execution at the fifth program step following the IF.

If the program steps immediately following the IF constitute a numeric address nnnn and the condition tested is met (YES), an automatic branch is made to that address nnnn. The program step stored at address nnnn is thereupon executed, and automatic execution of the program continued from there. If the program steps immediately following the IF constitute operations (e.g. +, ↑, etc.) then no branch occurs and the operations are executed.

When an IF program step (other than IF FLAG) is encountered, the two numbers in the x- and y-registers are automatically rounded before the test is made. In each register, the tenth digit of the number is rounded according to the value of the guard digits; the guard digits are then set equal to zero. Thus the numbers to be tested actually have the same values as would appear in a floating point display with all 10 significant digits displayed. After the test has been made, the numbers in the x- and y-registers retain their rounded values. This means that the actual values of the number in the x- and y-registers may be different after the test than before. If the resulting slight loss in accuracy is undesirable, the numbers in the x- and y-registers can be stored in the data-storage section of the RWM before the IF test is made and can be recalled and substituted for the rounded numbers after the IF test is completed.

The use of the IF x>y and IF x<y keys is illustrated by employing the following sequence of program steps beginning with an IF x>y program step and including a three-step conditional routine for taking the absolute value of the contents of the y-register:

IF x >y { x⇋y } conditional 4-step conditional routine for │y│ CHG SIGN sequence x⇋ y CONTINUE ↑

If the contents of the x-register are greater in value than the contents of the y-register (i.e. condition met), then every program step in this sequence is executed and the absolute value of the contents of the y-register is calculated. As described above CONTINUE is a no-operation program step. It is used in this and the following examples to fill in the fourth program step to be skipped if the test condition is not met. If the contents of the x-register are equal to or greater in value than than contents of the y-register (i.e. the condition is not met), then the four program steps immediately following the IF x>y program step are skipped and execution continues beginning with the ↑ program step. In this case the absolute value of the contents of the y-register is not calculated.

The use of the IF x=y key is illustrated by employing the following sequence of program steps: IF x=y 2 3 4-step conditional sequence CONTINUE CONTINUE +

if the contents of the x-register equal the contents of the y-register in value (i.e. condition met), then every program step in this sequence is executed. This results in an automatic branch to execute the program step stored at user address 0023. However, if the contents of the x-register do not equal the contents of the y-register in value (i.e. condition not met), the four program steps immediately following the IF x=y program step are skipped and execution continues beginning with the + program step.

The use of the IF FLAG key is illustrated by the following sequence of program steps: IF FLAG 4 1 4-step conditional sequence CONTINUE } CONTINUE SET FLAG

If the flag controlled by the SET FLAG key has been set (i.e. condition met), then every program step in this sequence is executed. This results in an automatic branch to execute the program step stored at user address 0041. However, if the flag controlled by the SET FLAG key has not been set (i.e. condition not met), then the four program steps immediately following the IF FLAG program step are skipped and execution continues beginning at the SET FLAG program step by setting the flag.

The SET FLAG key establishes the condition to be tested by the IF FLAG key. The YES condition is established when a SET FLAG keycode is encountered either as a program step or as a keyboard entry. The NO condition is established by clearing the flag. This occurs automatically whenever the calculator is switched on or whenever a CLEAR or IF FLAG key-code is encountered either as a program step or as a keyboard entry. If the flag condition must be retained for use later, the program must include a SET FLAG program step in the sequence of program steps executed following the flag-clearing program step. The flag enables the user to select the conditions which will determine whether a conditional branch (or operation) is to be made.

The LABEL key allows relocatable symbolic addresses to be used within a program. A LABEL key immediately followed by any other programmable key (e.g. LABEL, π) except the END key serves as a symbolic address that may be inserted in a program immediately before any program step a user may wish to relocate independently of its absolute (numeric) address. This symbolic address is relocated by a search command comprising a GO TO key immediately followed by the symbolic address itself (e.g. GO TO, LABEL, π). In response to this search command, the user program counter is reset to the first user available address 0000 in the program storage section of the RWM and is sequentially incremented in a search operation until the symbolic address (e.g. LABEL, π) is found. The user program counter then specifies the next address which is the program step designated by the symbolic address.

If the search command came from the keyboard, the calculator waits for the next key to be depressed. However, if the search command came from the program, then execution automatically continues at the program step designated by the symbolic address. The keys of the symbolic address itself serve as no-operation codes and are ignored during execution of the program. This may be illustrated by the following sequence of program steps.

______________________________________ PROGRAM ADDRESS STEP ______________________________________ 0098 0099 GO TO 0100 LABEL 0101 ÷ 0102 etc. . . . . . . . . 0362 0363 LABEL 0364 ÷ 0365 ↑ 0366 etc. ______________________________________

The search for the symbolic address "LABEL, ÷" is initiated immediately after address 0101 is designated by the user program counter and starts at address 0000. When the symbolic address is found, program execution continues with the ↑ program step at address 0365. The ÷ program, step 0101 and 0364, serving as part of the symbolic address are not executed.

A specific symbolic address cannot be used to specify more than one location at any one time. If it is, only the first (lowest order numeric address) specified will be valid (i.e. the point of transfer). Any number of different labels can be used at one time, limited to the number of keys available to follow the LABEL key.

If transfer to an undefined symbolic address occurs, the calculator will search all of program memory, and if the symbolic address is not found, will stop with the STATUS indicator light on. The program-counter will specify the next following program steps.

Branching to a symbolic addresss offers considerable advantages over branching to an absolute address. Programs with symbolic addresses can be stored anywhere in the program storage section of the RWM and can be easily moved and relocated because there are no absolute addresses to be changed. Also, any time a program is to be corrected (i.e. program steps changed, added or deleted), any absolute addresses must be checked in case they themselves must now be changed as a result of the corrections. This may entail substantial bookkeeping by the user. If symbolic addresses are used instead of absolute addresses, the corrections will not affect the symbolic addresses.

The main disadvantage of using symbolic addresses is that a search takes considerably more time (depending upon the location of the label in memory) than does a branch to an absolute address. Usually, this will have no significance because, in this case, "time" constitutes only a few thousandths of a second. Even if time is a significant factor, the user may still take advantage of symbolic addresses by writing his original program with symbolic addresses and once the program has been completely debugged, changing the symbolic addresses to the appropriate absolute addresses.

The SUB/RETURN key is used to transfer to (i.e. call) a subroutine (subprogram) and return from the subroutine to the point in the calling program where the transfer was initiated. Subroutines may be nested upto a depth of five. An attempt to nest to a depth of more than five is an error, stopping execution of the program and turning on the STATUS indicator light. Both the automatic initialization occuring at turn-on and the END key (given either as a program step or a keyboard entry) automatically reset the nesting to a depth of zero so that all five depths are then available. A GO TO key followed by a SUB/RETURN key and either an absolute numeric or symbolic labelled address may be used in the calling program to (unconditionally) call a subroutine. The address used specifies the starting address of the subroutine. If a symbolic address is used, the first two program steps of the subroutine must also be the same symbolic address. An IF key followed by GO TO and SUB/RETURN keys and either an absolute numeric or symbolic labelled starting address may also be used in the calling program to conditionally call a subroutine. Execution of the steps of the subroutine starts automatically as soon as the subroutine is called. A SUB/RETURN key must be included as the last step to be executed in the subroutine. The RETURN causes a branch to the "return-address" in the calling program. The return address is always the address immediately following the last step used to call the subroutine. Execution of the calling program then continues automatically, starting at the return address.

Any number of subroutines may be called individually during a program. However, it is also possible to use more than one subroutine at one time. One subroutine can call a second subroutine which, in turn, can call a third subroutine, and so on. This multiple-calling is known as "nesting". The calculator can remember (store) from one to five return-addresses at a time so that the subroutines may be nested up to a depth of five. Returns are made on a "last-in, first-out" basis, the return always being made to the last return-address stored. As soon as the return is made, that return-address is forgotton (erased from storage) so that the previous address now becomes the "last" one. Thus the returning order is always the opposite of the calling order.

A program written as a subroutine may also be used as a "stand-alone" program. This is accomplished by depressing the END key to erase any return-addresses currently stored in the calculator and by not using the SUB/RETURN key when addressing the memory before the program is run.

Special Function Keys (FMT, PRINT/SPACE, PAPER)

The FMT (format) key is used to initiate special operations not otherwise defined and implemented by the other basic keys of the calculator. It is always used with other keys and, in effect, serves to re-define these other keys to implement the desired special operations. Several of these special operations associated with the FMT key are defined as part of the basic calculator. Others have been defined as part of associated plug-in ROM modules and are available only when the associated ROM modules are plugged into the calculator.

The command-sequences FMT, ↑ and FMT, ↑ are used to operate the X-Y plotter peripheral unit. They are part of the basic calculator. The X-Y plotter-input commands are PEN ↑, PEN ↑, and x and y coordinates to which the pen-carriage is to be moved. The x and y coordinates are specified by decimal numbers in the range 0000 to 9999. The corresponding actual pen range of physical movement is determined by adjustments on the plotter itself. The FMT, ↑ command-sequence causes the pen to be raised and the contents of the x- and y-registers to be fed to the plotter as the x and y coordinates to which the pen is to be moved. The FMT, ↑ command-sequence lowers the pen and transmits the x-y coordinates. Note that for both commands the pen is raised or lowered first and the pen carriage is then moved. The x-y coordinates in the x- and y-registers must be pre-scaled by the user in the range 0000 to 9999. If these limits are violated, the following events occur:

1. If the contents of the x- and/or y-registers are less than 0000 (i.e. negative), 0000 is sent to the plotter, the pen is raised, moved, and lowered.

2. If the contents of the x- and/or y-registers are greater than 9999, 9999 is sent to the plotter, the pen is raised, moved, and lowered.

The result is to plot a series of dots along the boundary of the plot. The raising and lowering of the pen is a visual and audible warning to the user that he is plotting out-of-bounds.

The basic calculator includes provision for recording a user-program in the program storage section of the RWM as a secure program. This provision is completely distinct from a protected recording obtained by physically notching the magnetic card. A secure program is, by definition a program which can be executed only. It cannot be listed, recorded, looked at in the program mode, edited, or changed in any way. It is a program which can only be executed in the automatic operating mode at high speed by using the CONTINUE key (or step-by-step using the STEP PRGM key hereinafter explained).

Any program entered by the user from the keyboard input unit into the program storage section of the RWM, or any non-secure program loaded from a magnetic card, can be recorded as a secure program. This is accomplished in the same manner as described above in connection with the RECORD key except that the keys FMT and RECORD are sequentially depressed in the named order to initiate the recording operation. The program thereupon recorded on the magnetic card or cards is a secure program. The original program also remains in the program storage section of the RWM as a non-secure program, and can be recorded again, either as a secure or nonsecure program. It should be noted that once recording of a secure program has begun, it must be completed by continuing to insert cards until recording is terminated by an END program step. If the recording process is interrupted by depression of the STOP key, the recording will be terminated but the original program stored in the program storage section of the RWM then becomes a secure program and can only be executed -- no further recordings can be made.

If a program stored in the program storage section of the RWM is a secure program (either by loading a program recorded as a secure program or by the STOP default outlined above) the following conditions prevail:

1. If the PRGM key is depressed, the entire program memory is cleared.

2. If LIST or RECORD are depressed, they are ignored, so that no listing or recording of the program can be made. These actions do not destroy the program -- they are just ignored.

3. Since the program is destroyed by switching to the PRGM mode, the program cannot be changed or edited in any way.

Loading of a secure program is no different from loading a non-secure program -- the same procedure holds. Several secure programs may be chain-loaded. If a non-secure program is loaded into the calculator when a secure program is already stored therein, the program storage section of the RWM is cleared of the secure program in all areas not loaded by the non-secure program so that no trace of the secure program remains after loading the non-secure program. Thus, a non-secure program may not be chain-loaded after a secure program. However, the reverse can be done -- a secure program can be chain-loaded to a non-secure program but the composite program is then secure.

The command sequence FMT, GO TO is used to implement automatic or program-controlled loading of magnetic program cards. The effect of FMT GO TO is the same as the following sequence: GO TO, 0 LOAD, GO TO, 0, and CONTINUE. This may be used to load a program from the keyboard, with automatic initiation of execution, or it may be used in a program to "link" programs. If the magnetic card reading and recording unit is not loaded with a magnetic card, the INSERT CARD indicator light will come on indicating to the user that magnetic card should be inserted. The LOAD routine operates in the same manner as described above in connection with the LOAD key and is terminated by an END program step on the magnetic card.

The command sequence FMT, x➝ causes the contents of the available numeric-addressed data-registers in the data storage section of the RWM to be recorded on a magnetic card. The INSERT CARD indicator light comes on, and the recording continues, pass-after-pass, card-after-card until all registers are recorded, at which time the magnetic card reading and recording unit stops and the INSERT CARD indicator light goes out. If the FMT, x➝ command sequence was executed from a stored-program, the program will return to execution at the keycode immediately following the x➝ command. Recording may be terminated after any card by depressing the STOP key if the FMT x➝ command sequence came from a stored program, execution may then be resumed by depressing the CONTINUE key.

The command sequence FMT x➝ causes the loading of the available numeric-addressed datal registers in the data storage section of the RWM from one or more magnetic data cards. These registers are loaded card-after-card until all the registers are loaded. The INSERT CARD light remains on, and the card unit continues to run until all are loaded. The loading may be terminated by a STOP key. If the FMT, x➝ command sequence is executed from a stored program, executive resumes after a completed data load.

The PRINT/SPACE key causes the contents of the x-register to be printed in the same format as it is displayed (i.e. FIX (), n, or FLOAT). If additional PRINT/SPACE commands follow immediately, they will cause the printer to space (print a blank line). If the PRINT/SPACE command follows immediately after a numeric entry to x (from the keyboard or from a sequence of digit-keys in a program) the numeric printout is followed by an * (asterisk) indicating that this was a data entry and not a computed result.

The PAPER key is depressed to space the strip of thermal-sensitive paper used by the output printer unit. It continues to drive the paper upward until it is released.

Program Checking and Editing Keys (STEP/PRGM, BACK/STEP)

The STEP PRGM key is not programmable and is used, from the keyboard only, to single-step programs. When the calculator is in the manual operating mode the STEP PRGM key single-steps program execution. Each time STEP PRGM is depressed the program counter is incremented by one so that one program step is executed. When the calculator is in the program mode the STEP PRGM key enables the program steps stored in the program storage section of the RWM to be viewed. Each time the STEP PRGM key is depressed, the program counter is incremented by one, so that the address and program step displayed in the y-register shifts to the z-register, those in the x-register shift to the y-register and the next higher address and program step appears in the x-register.

The BACK STEP key is not programmable and is used to decrement the user program counter by one each time it is pressed. This backs up the output display (i.e. does just the opposite of the STEP PRGM key). It should only be used in the program mode. If the STEP PRGM and BACK STEP keys are depressed alternately, the same program step will be executed repeatedly. This key is extremely useful in editing and checking programs and when used with the PRGM STEP key permits the user to advance either forward or backward through a stored program one step at a time.

Definable and Redefinable Keys

The half keys A-O comprising the group of definable keys 91 enable the calculator to be tailored to the special needs of the user. Operation of these keys is defined by the various plug-in ROM modules 92 that may be used with the calculator. Without these ROM modules the definable keys 91 serve no function and accidently depressing them, or encountering them in the execution of a stored program, will result in a completely non-destructive no-operation.

The plug-in ROM modules 92 include the alpha ROM module mentioned above, a definable functions ROM module, a mathematics ROM module, a statistics ROM module, and a typewriter ROM module. Both the alpha ROM module and the typewriter ROM module redefine nearly all of the keys of the keyboard as well as defining the definable keys 91 themselves. The definable functions ROM module, the mathematics ROM module, and the statistics ROM module each uniquely define the definable keys alone and may each be used at the same time as the alpha ROM module or the typewriter ROM module.

A different overlay 192 is associated with each of the definable functions, mathematics, and statistics ROM modules and is employed with the definable keys 91 to identify the functions performed thereby when its associated ROM module is plugged into the calculator. Each of these overlays 192 comprises a thin metal template that fits over the definable keys 91 and latches into a recess around them. The graphics on these templates visually complete the key shapes and indicate the key function. A small tab positioned just above the nameplate releases each template, which then pops up enough to grasp. Three holes 196 near the top edge of each template allow direct viewing of three light-emitting diode indicator light used to indicate various operating conditions associated with the routines implemented by the ROM module. When the overly and its associated ROM module are not in use they may be secured together by a pair of tabs 198 provided on the ROM module.

A description of the additional key operations that may be provided by the plug-in ROM modules will now be given.

Alpha ROM Module

The Alpha ROM module redefines the keyboard input unit as indicated by the letters printed on the tops of the definable keys 91 and the letters and symbols printed on the front sides of most of the other keys to provide an "alpha keyboard" (see FIG. 8) containing 54 character-entry keys, five operational keys, and 16 "non-essential" keys (these non-essential keys are either inoperative or duplicate other keys during the alpha mode). During the alpha mode, the key-log feature is deactivated (thus, any keys pressed are not logged).

The 54 character-entry include all of the English alphabetic characters A-Z, all of the decimal numbers 0-9, and all of the following symbols , √, / (printed by the ÷ key), x, -, +, π, ➝, ,,,., =, $, ?, (, ), %, ", and π. Depressing any of these keys during the alpha mode, will cause the alphameric character or symbol indicated thereby to be printed out in line-printer fashion. The output printer unit operates as a line printer in that each character is not immediately printed out, but rather an entire line (16 characters) is first stored and then printed out. The print-out occurs as the 16th character is entered.

The five operational keys include the FMT key, the STOP key, a SPACE key (normally the CONTINUE key), a CLEAR/RETURN key (normally the CLEAR key), and a PAPER key.

During the alpha mode, the following operational keys are depressed to perform various printing operations. Depressing the FMT key twice redefines the keyboard to the alpha mode, after which character keys may be depressed. After the last character is entered, depressing the FMT key causes a line print, a line feed, and returns the keyboard to normal operation. (The output display is blanked during the alpha mode, although the contents of the x-, y-, and z-registers remain unchanged.) For example, the alphabet may be printed by sequentially depressing the RUN, STOP, FMT, FMT, A through Z, and FMT keys.

Depressing the SPACE key inserts a blank space in the printed line (similar in operation to the space bar on the typewriter).

Depressing the CLEAR/RETURN key causes a line print and advances the printer to the next line (i.e. like a typewriter carriage-return and line feed operation). The alpha mode remains set after this instruction. Successive CLEAR instructions will cause the printer to advance, without printing, one line for each instruction.

Depressing the STOP key terminates the alpha mode without a line print or line feed. Any characters entered but not printed will be erased when STOP is pressed. This instruction is not programmable and should not be used while programming alpha messages.

The PAPER key is a manual paper advance control. This operation is not programmable.

The 16 "non-essential" keys include the ↑, x y, ↑, PRINT/SPACE, SUB/RETURN, END, BACK/STEP, STEP/PRGM, FLOAT, FIX (), RUN, PRGM, KEY LOG, LIST, LOAD, and RECORD keys. These keys are not essential for alpha printing operations. The non-essential keys which are programmable duplicate the SPACE key, while most of the non-programmable keys are "locked out" (i.e. not operational) during alpha printing operations. Pressing BACK STEP or STEP PRGM will cause 1 or 0, respectively, to be printed.

Definable Functions ROM Module

When the definable functions ROM module is plugged into the calculator, the user may employ the definable keys 91 to perform the redefined functions indentified by the associated overlay shown in FIG. 9. These functions include:

a. Defining special subroutines that can be called by a single key;

b. Protecting such subroutines against accidental erasure;

c. Deleting one, or more, of such subroutines when desired; and

d. Deleting, inserting, or searching for keycodes in any stored program.

a. Defining a Function

A user definable function can be any sequence of program steps, beginning with the key DEFINE F (i), where F(i) represents one of the keys F1 thru F9. The execution of such sequence of program steps must be terminated with the F-RET key in the same manner as the SUB/RET key in the case of subroutines.

Example:

The following is a function which puts π in x, y, and z.

______________________________________ Program Step Key ______________________________________ 0000 DEFINE 0001 F1 0002 π 0003 ↑ 0004 ↑ 0005 F-RET ______________________________________

The above function is identified by the key F1. To execute this function simple press the F1 key in RUN mode or insert F1 in a program at the place you want it executed.

Example:

The following is a call on F1 from another program (the program here happens to be another function F2).

______________________________________ Program Step Key ______________________________________ 0000 DEFINE 0001 F2 0002 CLR 0003 F1 0004 F-RET ______________________________________

Notice that we have assigned the same program step numbers to both the functions F1 and F2. Every function definition is assumed to start at program step 0000. All GO TO commands when present in a function are coded accordingly. This allows the user to define functions and delete them in a way independent of where they actually reside in the calculator memory. The key DEFINE in both of the above functions serves to mark the start of the definition of a function in the calculator memory. This key is treated as an error if it is pressed during RUN mode. The key DEFINE is also treated as an error if the user attempts to execute it in a program.

Example:

Program Step Key ______________________________________ 0000 DEFINE 0001 F3 0002 CLR 0003 DEFINE ➝ 0004 F2 ______________________________________

The DEFINE at program step 0003 will be treated as an error when encountered during the execution of F3. The user here forgot to terminate the execution of F3 with F-RET. This error will cause the calculator to stop execution and turn on the STATUS light.

b. Protecting User Defined Functions

The protection feature allows the user to designate areas of memory to be a part of the calculator's executive system.

i. Protecting A Single Function

Assume that you have just entered the definition of the function F1 in memory (the same F1 discussed earlier). After entering the last keystroke in the definition, namely F-RET, the program counter (y display) will point to program step 0006. Location 0005 which contains F-RET will be displayed in the z-register. Switch to the RUN mode. Press PROTECT. The light on the top of the PROTECT key (option 2 light) .................. will come on. The definition of F1 is now protected up to and including the F-RET key. If you switch back to PROGRAM mode, whatever was in program step 0006 before will appear now to be at program step 0000. All the program steps used in defining F1 became "invisible". For all purposes these program steps are now a part of the calculator system. You can still execute F1 by pressing the corresponding key in RUN mode, or by calling on it from another program or function.

ii. Protecting Several User Defined Functions

Assume now that both the functions F1 and F2, described earlier, are to be protected. After protecting F1 switch to the PROGRAM mode and enter the definition of F2, namely:

Program Step Key ______________________________________ 0000 DEFINE 0001 F2 0002 CLR 0003 F1 0004 F-RET ______________________________________

After entering the definition of F2 switch to the RUN mode. Press DELETE PROTECT. The protect light indicator (option 2) will go off. Press PROTECT. Both the definitions of F1 and F2 are protected.

iii. Effect of Protection on User Memory

When protecting a certain number of keystrokes the calculator subtracts that number from the total number of program steps available in user memory. The user can compute the number of program steps available at any time as follows. In RUN mode, press END, DELETE, PROTECT, switch to the PROGRAM mode and read the program step number in the y display, assume this number is p. The number of program steps available to the user are given by the simple formula:

Available Program Steps = n - p

The variable n in the above formula is 500, 1012 or 2036 according to the amount of user memory purchased.

After finding the value of p, as illustrated above, you can switch back to the RUN mode and press PROTECT again to re-establish the protection.

c. Deleting User Defined Functions

To delete a given function simply press the DELETE key followed by the name of the function to be deleted. The DELETE key only applies to the unprotected area of user memory. This prevents accidental erasure of protected functions. Pressing the DELETE key causes the Insert/Delete light to come on (option 1) indicating that a memory modification operation is to be performed. If after pressing the DELETE key you find that you did not want to delete after all, you can press the CLEAR key to abort the delete option. Pressing the CLEAR key at this time will cause the Insert/Delete light to go off. If the function to be deleted does not exist the error light will come on and the delete operation will be aborted. The DELETE key must be pressed while the calculator is in RUN mode. The DELETE key may be followed by a function name (F1 thru F9), CLEAR, or a digit. Other keys following the DELETE key will turn on the error light and abort the delete operation. If encountered during the execution of a stored program the DELETE key will cause the calculator to stop execution and turn on the error indicator.

Deleting the last function in memory

the delete operation is designed to delete a portion of user memory which starts with the DEFINE of the function to be deleted and ending with the keystroke prior to the DEFINE of the next function in memory, or END. To illustrate, consider the following memory map.

______________________________________ Program Step Key ______________________________________ 0000 DEFINE ➝ 0001 F1 0002 CLR 0003 F-RET ➝ 0004 DEFINE 0005 F2 0006 EEX 0007 1 0008 0009 IF X=Y 0010 F-RET 0011 CONT 0012 CONT 0013 CONT 0014 GO TO 0015 4 0016 END 0017 ... ______________________________________

When pressing DELETE F1 the calculator will delete the memory portion delimited by the two arrows in the memory map. After deletion the DEFINE at program step 0004 will move to program step 0000. The following keystrokes will move accordingly. Since the last function in a user memory is not likely to be followed by another DEFINE it is advisable to terminate that function with the keystroke END as shown in the memory map (program step 0016). If the last function in memory is not terminated with END then by deleting that function the user will also delete that portion of memory which follows that function and terminates with an END. When deleting the last function in memory, the delete operation does not delete the END key. Thus deleting F2 from the memory map shown earlier will result in the following memory map.

______________________________________ Program Step Key ______________________________________ 0000 DEFINE 0001 F1 0002 CLR 0003 F-RET 0004 END ______________________________________

The keystroke END becomes now the terminator to the definition of F1.

d. General Editing Capabilities

In addition to deleting functions the user of the definable function block is offered the capability of deleting, inserting, and searching for individual keystrokes in memory. This feature is discussed next.

i. Deleting Individual Keystrokes

If the DELETE key is followed by a 4 digit address* the calculator will delete the keystroke contained in that address and move all the following keystrokes accordingly.

Example:

Consider the memory map:

Program Step Key ______________________________________ 0000 CLR 0001 GO TO 0002 0 ➝ 0003 5 0004 END 0005 1 0006 ... ______________________________________

To delete the keystroke at program step 0002 press the DELETE key in RUN mode, (Insert/Delete light will come on), followed by the keys 0 0 0 2. The resulting memory map will be:

Program Step Key ______________________________________ 0000 CLR 0001 GO TO 0002 5 0003 END 0004 1 0005 ... 0006 ... ______________________________________

Notice that the keystroke previously at 0003 is now at program step 0002. All the keystrokes following the deleted key up to the last keystroke in memory have been moved accordingly.

Automatic address termination and aborting a delete:

in the above example we used a 4 digit address to specify the keystroke to be deleted. The user can use a 3, 2, or one digit address if such an address is terminated by a non-numeric key other than CLEAR. The following delete commands are equivalent to that given in the last example:

DELETE 2 STOP DELETE 02 STOP DELETE 002 STOP

To abort a delete command before it is executed press the CLEAR key. The Insert/Delete light (option 1) will go off and the delete command will be cancelled. The CLEAR key can be pressed immediately after the DELETE key or during the entry of the address digits. Notice that the fourth digit in an address terminates that address. This digit signals to the calculator that the delete operation is to be performed. A CLEAR key following the fourth digit of an address will have no effect on a delete operation. After performing a delete operation the calculator switches off the Insert/Delete light. If the delete address is bigger than 2035 the status light will come on and the delete operation will be aborted. This number represents the maximum available program steps in the calculator.

ii. Inserting Individual Keystrokes

The definable function block also offers the user the capability of inserting key codes at any arbitrary program step.

Example:

Consider the following memory map:

Program Step Key ______________________________________ 0000 CLR 0001 GO TO ➝ 0002 9 0003 END 0004 ... ______________________________________

To insert a keystroke before the key at program step 0002, press INSERT in RUN MODE, (the Insert/Delete light will come on), followed by 0 0 0 2. Switch to PROGRAM mode. The y display will point to program step 0002. At this location you will find that a CONTINUE (Code 47) has been inserted. The keystrokes originally at 0002 has now been moved to step 0003. All the keystrokes which follow this keystroke have been moved accordingly. To put a new keystroke at 0002, simply press the new key while you are still in PROGRAM mode. The key pressed will replace the CONTINUE inserted earlier by the calculator. Without replacing the CONTINUE at step 0002 the new memory map is as shown below:

Program Step Key ______________________________________ 0000 CLR 0001 GO TO 0002 CONT 0003 9 0004 END 0005 ... ______________________________________

The address in an INSERT command may . . . . . . . be automatically terminated in the same manner described earlier in connection with DELETE. The insert operation can also be aborted in the same fashion.

Notice that the insert operation effects the content of all the program steps following the one designated in that operation.

iii. Searching for a Given Keystroke in Memory:

The ability to search for a given keystroke in memory is provided by the FIND key. By pressing the FIND key, in RUN mode, followed by any other key on the keyboard the user commands the calculator to search for that key in memory starting at the current program counter value. If the key asked for is not found, the status light will come on. However if the key is found: the calculator will automatically switch to PROGRAM mode, and the Z register will contain the program step at which the key was found.

Example:

Consider protecting a function definition area in memory. This area is terminated with the key END. Reset the program counter to 0000 by pressing GO TO 0 or END, in RUN mode. Now press FIND END, the z-register will now contain the terminating END in the function area. Press RUN PROTECT. The function area is now protected up to and including that terminating END.

Programming hints:

the definable functions can be nested five levels deep, irrespective of regular subroutine nesting. A higher nesting value will cause the calculator to stop execution and turn on the status light.

The light on top of the F-RET key (option 3) when lit indicates that the user is executing a sequence of keystrokes in a function definition. If you press STOP while this light is on you may stop the calculator in the middle of a function. To reinitialize program execution press DELETE, F-RET in RUN mode, the F-RET light will go off and the program counter adjusted to the value it had when the function area of memory was called.

Calling on a non-existant function from a stored program will cause the calculator to stop execution and turn on the status light. The program counter at this time will point to the program step which contains the name of the function called.

Mathematics ROM Module

When the mathematics ROM module is plugged into the calculator at the left-hand receptacle 94, the user may employ the definable keys 91 to perform the additional functions indicated by the mathematics overlay shown in FIG. 10. All of these additional functions are programmable. Any mathematically illegal functions performed either from the keyboard input unit or a stored program will turn on the STATUS light.

The units to be used in problems involving trigonometric functions or vector arithmetic are selected according to the procedure listed in Table A. The units specified by the appropriate indicator light above the definable key block.

Table A ______________________________________ Specifying Units To Specify: Press: Indication: ______________________________________ DEGREES TABLE N 1 Deg Rad Grad RADIANS TABLE N 2 Deg Rad Grad GRADS TABLE N 3 Deg Rad Grad ______________________________________

It should be noted that the setting of degrees, radians, and grads (360 degrees = 400 grads) is programmable.

Trigonometric functions of angles from 0° up to 5760° can be calculated at full accuracy; however, inverse trigonometric functions are calculated only for the principal values of the functions:

θ = sin-1 x; -90° ≤ θ ≤ + 90°

θ = cos-1 x; 0° ≤ θ ≤ + 180°

θ = tan-1 x; -90° ≤ θ ≤ + 90°

For instance: cos 150° = cos 210° = cos 510° = (etc.) = -.866

But: cos-1 .866 = 150°.

The sin x key is depressed to calculate the Sine of the contents of the x-register and insert the result in the x-register.

The cos x key is depressed to calculate the Cosine of the contents of the x-register and insert the result in the x-register.

The tan x key is depressed to calculate the Tangent of the contents of the x-register and insert the result in the x-register.

The arc key is depressed followed by a trigonometric key to calculate the inverse trigonometric function of the contents of the x-register and insert the result in the x-register.

For example, the sin-1 0.5 may be calculated by sequentially depressing the TABLE N, 1, ., 5, arc, and sin x keys. Depression of the TABLE N and 1 keys selected the units (degrees) per Table A above.

The following logarithmic and exponential functions may all be performed by employing one or two keystroke operations.

The TABLE N and 4 keys are sequentially depressed in the order named to calculate the logarithm (to base 10) of the contents of the x-register and display the result in the x-register.

The TABLE N and 5 keys are sequentially depressed in the order named to raise 10 to the power indicated by the contents of the x-register and display the result in the x-register (i.e. 10x). For example, the number 0.69897 may be raised to the power indicated by the contents of the x-register by sequentially depressing the ., 6, 9, 8, 9, 7, TABLE N, and 5 keys.

The ln x key is depressed to calculate the logarithm (to base e, i.e. natural logarithm) of the contents of the x-register and display the result in the x-register (i.e. ln x). For example, the 5 √23 may be calculated by sequentially depressing the 2, 3, ln x, ↑, 5, ÷, ↑, and ex keys.

The ex key is depressed to raise e (i.e. 2.718....) to the power indicated by the contents of the x-register and display the result in the x-register (i.e. ex).

The xy key is depressed to raise the contents of the x-register to the power indicated by the contents of the y-register. The result is displayed in the x-register, and the contents of the y-register remain unchanged.

The following keys provide capability for performing complex and vector arithmetic with a single keystroke operation.

The TO POLAR key is depressed to convert rectangular coordinates (consisting of x and y components in the x- and y-registers, respectively) to polar coordinates (θ = tan-1 (y/x), R = √x2 +y2). When converting from rectangular (cartesian) to polar coordinates, the calculated angle θ will be within the range of -180°≤ θ ≤180°. The final display is:

temporary z accumulator y (Angle θ) keyboard x (Radius R)

For example, the coordinates 4, 3 (x, y) may be converted to polar form by sequentially depressing the TABLE N, 1 (these keys select the units, i.e. degrees), 3, ↑, 4, and TO POLAR keys.

The TO RECTANGULAR key is depressed to convert polar coordinates, when the radius (R) and the angle (θ) are in the x- and y-registers, respectively, to rectangular coordinates (y = R Sin θ, x = R Cos θ). The final display is:

temporary z accumulator y (y component) keyboard x (x component)

For example, the polar coordinates R = 8, θ = 120° (or -240°) may be converted to rectangular form by sequentially depressing the TABLE N, 1, 1, 2, 0, ↑, 8, and TO RECTANGULAR keys. The final display is:

temporary z accumulator y 6.928 keyboard x -4.000

The ACCUMULATE +, ACCUMULATE -, and RECALL keys are storage and recall keys associated with the a- and b-data storage registers. These keys provide complete capabilities for vector addition and subtraction.

The ACCUMULATE + key is depressed to simultaneously add the contents of the x- and a-registers together and the contents of the y- and b-registers together. The sums are entered in the a- and b-registers, respectively, while the x- and y-registers remain unchanged.

The ACCUMULATE - key is depressed so simultaneously subtract the contents of the x-register from the contents of the a-register and the contents of the y-register from the contents of the b-register. The remainders are entered into the a- and b-registers, respectively, while the contents of the x- and y-registers remain unchanged.

The TABLE N key permits access to 10 more ROM functions than there are definable keys. A list of these functions is given in Table B below. The TABLE N key may be followed by any key. If this key is different from a numeric or FMT, no operation is performed.

Table B ______________________________________ TABLE N FUNCTION ______________________________________ 1 SET DEGREES SETS ARGUMENT 2 SET RADIANS } UNITS FOR TRIGONO- 3 SET GRADS METRIC FUNCTIONS 4 Log10 x 5 10x 6 DEGR, MIN, SEC ➝DECIMAL DEGREES 7 DECIMAL DEGREES ➝DEGR, MIN, SEC 8 X! 9 ROUND FMT AUTOMATIC PLOTTER SCALING ______________________________________

The first five functions of the TABLE N key have already been explained above. However, this key may also be used to perform any of the next five functions (namely, angle conversion, calculation X!, rounding a number to a specified power of 10, and plotter scaling) not previously described above.

The TABLE N and 6 keys are sequentially depressed in the order named to convert an angle expressed in degrees, minutes and seconds to decimal degrees. The angle must be entered into the calculator as follows:

DISPLAY ______________________________________ temporary z ➝ (Degrees) accumulator y ➝ (Minutes) keyboard x ➝ (Seconds) ______________________________________

The result in decimal degrees, appears in the x-register, while the y- and z-registers are cleared. This is illustrated as follows:

temporary z -- 0 accumulator y -- 0 keyboard x --DECIMAL DEGREES

The TABLE N and 7 keys are sequentially depressed in the order named to convert an angle expressed in decimal degrees to degrees, minutes and seconds. The angle to be converted must be entered into the x-register, and the resultant angle appears as in the previous display. However, the contents of the y- and z-registers need not be zero for the instruction TABLE N, 7.

The TABLE N and 8 keys are sequentially depressed in the order named to replace the contents of the x-register with X! (where x 0 ≤ │x│ ≤ 69).

The TABLE N and 9 keys are sequentially depressed in the order named to round the contents of the y-register to the power of 10 indicated by the integer value of the contents of the x-register. The rounded number appears in the x-register, while the y-register remains unchanged. For example, the number 5610.0 may be rounded to 102 (or nearest 100), by sequentially depressing the 5, 6, 1, 0, and ↑ followed by the 2, TABLE N, and 9 keys.

DISPLAY ______________________________________ accumulator y 5610.000 keyboard x 5600.000 (y rounded) ______________________________________

Similarly, the contents of the y-register may be rounded to another power (104) by sequentially depressing the 4, TABLE N, and 9 keys.

DISPLAY ______________________________________ accumulator y 5610.000 keyboard x 10000.000 (y rounded) ______________________________________

A fractional number may be rounded by inserting a negative number into the x-register. For example, the number 0.005 may be rounded to the 10-2 or nearest 1/100 by sequentially depressing the ., 0, 0, 5, ↑, CHG SIGN, 2, TABLE N, and 9 keys.

DISPLAY ______________________________________ accumulator y 0.005 keyboard x 0.010 (y rounded) ______________________________________

A problem usually encountered when writing a calculator/plotter program is that of scaling the available problem variables to coordinates which the plotter can use. The plotter scaling feature to be described, simplifies this typical plotting problem. The TABLE N, FMT, and ↑ or ↑ keys are sequentially depressed in the order named to replace the plotter problem variables, which are entered in corresponding x- and y-registers, with scaled coordinates. The user variable maxima and minima for this scaling operation are stored in user data storage registers 001-004. The foregoing sequence of keys controls the plotter (using the scaled variables) in the same manner as FMT, ↑, or ↑ described above.

The DEFINABLE f () key is used to label and "call" an often used (or favorite) function which is programmed as a subroutine in the calculator. The definable function may be executed at any time from the keyboard by depressing the DEFINABLE key, or it may be called in a program by inserting the DEFINABLE (key) instruction. The definable function is programmed similar to a LABEL subroutine, while the function is executed as a normal subroutine; except it may be called with only one keystroke or program step.

When the DEFINABLE f () key is depressed the program counter searches for a subroutine labeled DEFINE f (), executes, and returns. This key can be used both in keyboard and program control. A user written subroutine to be called by the DEFINABLE f () key can be stored anywhere in the program memory, its first program steps must be LABEL, DEFINABLE f (); its last step must be SUB/RETURN. There are no restrictions on the operations this subroutine may perform. It is illustrated by the following example:

LABEL ______________________________________ DEFINABLE f ( ) ↑ ex x⇋y CHG SIGN ex + 2 ÷ (SUB/RETURN) ______________________________________

Whenever the key DEFINABLE f () is called either in RUN or PROGRAM mode, the hyperbolic cosine of the number in the x-register is computed and placed in the y-register by this subroutine.

The TABLE N and CLEAR x keys are depressed to clear all numerical storage registers without affecting the a- and b-registers or the x-, y- and z-registers.

A programmed subroutine may be repeated m number of times by inserting the following keys at the end of the subroutine: TABLE N, SUB RETURN, and n, where n may be any key from 0 to 9 indicating a data storage register that contains m, and m is equal to the absolute integer value of the contents of the n-register. After the subroutine has been repeated n times, the program exits the subroutine and resumes normal program operation at the program step following the subroutine "calling instructions". The iterative subroutine feature may be added to a LABEL subroutine, but when the LABEL subroutine is called (during a program) the call instructions must cntain six program steps. The following partial program shows how to call the LABEL π iterative subroutine.

Iterative "LABEL" Subroutine ______________________________________ STEP KEY (KEY/CODE) COMMENT ______________________________________ 0400 0401 CONTINUE 47 Subroutine 0402 CONTINUE 47 CALLS 0403 GO TO 44 Instructions 0404 (SUB/RETURN) 77 0405 LABEL 31 (6 keys) 0406 π 56} Return from 0407 ÷ 35 Subroutine ______________________________________

Statistics ROM Module

The primary function of the statistics ROM module is to carry out the summations of variables, cross-products, and squares needed as fundamental quantities in a variety of statistical analyses. These summations are generated in the general data storage user registers, and the user must be careful to avoid any operations which might destroy or alter the contents of these registers. The number of registers used is dependent on the number of variables treated -- as defined by the user.

The registers used are:

n ➝ 0 Σ x ➝ 1 Σ x2 ➝ 2 1-variable; x Σ y ➝ 3 Σxy ➝ 4 Σ y2 ➝ 5 2-variable; x, y Σ z ➝ 6 Σxz ➝ 7 Σyz ➝ 8 Σ z2 ➝ 9 3-variable; x, y, z Σ a ➝ 10 Σxa ➝ 11 Σya ➝ 12 Σza ➝ 13 Σ a2 ➝ 14 4-variable; x, y, z, a Σ b ➝ 15 Σxb ➝ 16 Σyb ➝ 17 Σzb ➝ 18 Σab ➝ 19 Σ b2 ➝ 20 5-variables; x, y, z, a, b

These are graphically summarized in an easy-to-recall form in this table:

1 x y z a b ______________________________________ 1 0 1 3 6 10 15 x 1 2 4 7 11 16 y 2 5 8 12 17 z 3 9 13 18 a 4 14 19 b 5 20 ______________________________________

In addition to the user-registers 0 ➝ 20 utilized as shown above, registers 21➝27 are used for collection of maximum/minimum values, for the "seed" of the pseudo-random number generator. This is shown below:

xmin ➝ 21 xmax ➝ 22 ymin ➝ 23 ymax ➝ 24 zmin ➝ 25 zmax ➝ 26 RN ➝ 27

any registers not used in a specific sequence are available. For example, if 2 - variable operations are set up, only registers 0➝5 are in use, and 6➝20 are free for other purposes.

When the statistis ROM module is plugged into the calculator, the user may employ the definable keys 91 to perform the additional functions indicated by the statistics overlay shown in FIG. 11. All of these additional functions are programmable and will hereinafter be described key-by-key.

The VARIABLES K key is used to define the number of variables to be treated, 1 to 5. It must be followed immediately by a digit key, 1 to 5. If any other key is depressed after this key, the STATUS light will be turned on, and the calculator will halt in the display mode. The VARIABLE key and the erroneous key following it are ignored -- there is no other action.

If a correct digit key follows, one or more of the indicator lights will come on, to signal the number of variables selected. The pattern is:

1-variable 1-light 2-variable 2-light 3-variable 3-light 4-variable 1 and 3-lights 5-variable 2 and 3-lights

The definition of the number of variables affects subsequent use of the Σ key, MAX/MIN key, and the INITIALIZE and CORRECT keys used in conjunction with it. The number of variables remains unchanged until the VARIABLES key is used to change it, which may be done at any time.

Σ

This key is used to accumulate the data summations of variables, cross-products, and squares as outlined previously. The number of summations is determined by the VARIABLES key described above. That is, the contents of the registers utilized are:

1-variable x 2-variable x, y 3-variable x, y, z 4-variable x, y, z, a 5-variable x, y, z, a, b

If the summation key (Σ) is depressed without a previous definition of the number of variables (VARIABALES key followed by digit 1➝5), the number of variables is set at three. It will remain at this setting unless changed by use of VARIABLES

The Σ key generates the summations, and leaves the contents of x, y, z, a, and b unchanged.

The INITIALIZE and CORRECT keys work in conjunction with the summation key. They must precede the Σ key.

When the sequence INITIALIZE - Σ is used, all registers (defined by the number of variables set) involved in the summations are cleared to zero. This sequence should always be used before the start of a series of summations on a set of data -- otherwise any previous contents of the registers are included in the summations.

If, after depressing the Σ key, it is discovered that the contents of x, y, z, a, or b were erroneous, the user may remove the erroneous data from the summation by depressing CORRECT - Σ keys in that sequence. This will remove all variables, cross-products, and squares of that data from the summation. The user may then correct the data and reenter it by depressing the Σ key. Since x, y, z, a, and b are unchanged by the use of Σ (or CORRECT - Σ ) this is most conveniently done when the erroneous data is still intact - i.e., immediately after Σ . However, if the erroneous data is not discovered until later, the user must reenter the erroneous data in x through b (only x and y if 2 - variable, etc.), use CORRECT - Σ, and then correct the erroneous data and enter it with the Σ key.

The user must be careful not to do any operations during a summation-sequence on data which will alter the contents of any user-registers involved in the summation. However, the contents of any of the summation-registers may be recalled and used at any time, so long as they are not altered.

Once a data-sequence has been entered by use of the Σ key, the summations are available for any desired statistical analysis. For user convenience, four commonly used statistical processes are implemented, to be performed by a single keystroke. The function of these four keys will follow.

The MEAN key computes (from the collected summations) the arithmetic mean of up to three variables; x, y, and z. If four or five variables are set, the MEAN key operates on only three, and does not form the other two means (on a and b).

For various variable settings, the following computations are made, and appear in the x, y, z registers:

1-variable z φ.φ y φ.φ x x=(Σx/n)= ((1)/(0))

where (1) means "contents of register - 1".

______________________________________ 2-variable z φ.φ y y=(Σy/n)=((3)/(0)) x x 3-variable z z=(Σz/n)= ((6)/(0)) y y x x ______________________________________

These computations are carried out and the results appear in x, y, z as shown, without changing the contents of any of the summation registers.

The VARIANCE key computes (from the collected summations) the variance of up to three variables, x, y, and z. If four or five variables are set, the VARIANCE key operates on only three, and does not form the vaiance of a or b.

The following computations are performed: ##SPC1##

The results appear in the x, y, z registers in the pattern

______________________________________ 1-variable 2-variable 3-variable ______________________________________ z- φ.φ φ.φ z2 y- φ.φ y2 y2 x- x2 x2 x 2 ______________________________________

The contents of all summation-registers used in these computations remain unchanged.

The REGRESSION key performs linear regression (least-squares curve fitting) using the accumulated summations. The computations and results are controlled by the variable-setting, as outlined below.

Variable - 1: The regression of a single variable on itself is not performed. If REGRESSION is depressed with VARIABLES - 1 set, the STATUS light is turned on, and the calculator halts in the display mode. There will be no other action - the contents of x, y, z, and all summation -- registers will be unchanged.

Variable - 2: The regression of the dependent variable on one independent variable is performed for the equation:

y = a0 + a1 x

The results are placed in x, y, z in the pattern:

z φ.φ y a0 x a1

The contents of all summation-registers used in the computation remain unchanged.

Variable - 3: The regression of the dependent variable on two independent is performed for the equation:

z = a0 + a1 x + a2 y

The results are placed in x, y, z in the pattern:

z a0 y a2 x a1

The contents of all summation-registers used in the computation remain unchanged.

Variable 4 - and Variable - 5: This situation is treated as Variable - 3. Four - and 5 - variable regression may be performed by user-programming. All summations required are generated by the Σ key when variables are set at 4 or 5.

r2

The r2 key generates the correlation coefficient (a measure of goodness-of-fit) for the linear regressions performed by the REGRESSION key. The computations performed are controlled by the variable setting.

Variable - 1: No computations are performed--the key is ignored.

Variable - 2: The correlation coefficient of the linear regression for:

y = a0 + a1 x

is computed.

The computations performed are best described by introduction of a subsidiary quantity:

μxi xj = Σxi xj -[(Σ xi)(Σ xj)/n]

The correlation-coefficient for variable - 2 is then defined to be:

r2 = (μxy)2 /μxxμyy

This result is placed in register x, and y and z are cleared.

Variable - 3: The correlation-coefficient of the linear regression for:

z = ao + a1 x + a2 y

is computed. This is:

r2 =(a1 μxz + a2 μyz)/μzz

The result is placed in register x, and y and z are cleared.

The MAX/MIN key is used to collect the maximum and minimum values of the variables x, y, and z. Since these values are stored in registers 21 through 26, they do not affect the summation registers (Σ key). Thus, MAX/MIN information may be collected on the same data on which summation information is being collected.

The MAX/MIN storage registers 21 through 26 are initialized by the key-sequence INITIALIZE - MAX/MIN. This results in loading the registers with:

(21), (23), (25) (x, y, z)min = 1099 (22), (24), (26) ( x, y, z)max = -1099

All six registers are initialized without regard to the variable-number setting.

When MAX/MIN is depressed, the contents of x(1-variable), xand y (2-variable) or x, y, and z (3,4, or 5-variable) are compared to the stored contents of the max/min registers. If the new value is less than the contents of the associated "min" register, the new value is substituted-- if not, the register is left unchanged. The maximums are handled correspondingly Thus, at any time the max/min registers contain the max/min of the input data since the last initialization. This data is not displayed--the user must recall it, as needed, from the appropriate register.

The CORRECT key does not work in association with the MAX/MIN key, since any previous values changed are lost irretrievably by the MAX/MIN operation.

The t key collects summations necessary to compute a t-statistic on data in x and y, and computes and displays the statistic. The overall action is quite different from the Σ key, which collects summations only, and leaves the original data unchanged. In contrast, the t key collects needed summations, computes and presents the t-statistic, and destroys the data just entered.

Further, the t-summations are stored in registers 0,1, and 2 which are the same registers used by the Σ key. Therefore, use of the Σ andt key canot be intermixed.

The summations accumulated are:

n ➝ 0 Σ(x2 -y) = ΣD ➝ 1 Σ(x - y)2 = ΣD2 ➝ 2

These are accumulated with each depression of the t key. The three registers may be cleared for starting a new data-sequence by the key-sequence INITIALIZE - t.

If an error is made in data entry and the erroneous data is included in the summations by depression of the t key, it is convenient to have a means for removing the erroneous data. However, the data has been destroyed in order to present the t-statistic which is computed after each key depression. When the user discovers the data error, he may reenter the erroneous data in x and y. Then, depression of CORRECT - t will remove the data from the summation. He may then reenter the correct data and include it by depressing the t key.

The computations performed from the summations are:

D = ΣD/n = [Σ(x - y)]/n ##SPC2##

D is placed in the z - register, n in y, and t in x.

X2

the X2 key accumulates the summations and then computes and presents the chi-squared statistic at each depression of the key. It's general operation is the same as the t key in that:

1. Summations are accumulated in 0 and 1 so that use of X2 and Σ cannot be mixed.

2. The presentation of results after each key depression destroys the data entry in x and y. Correction for erroneous data can be accomplished by reentering the bad data and then depressing CORRECT - X2.

3. the registers used (0 and 1) are cleared by depressing INITIALIZE - X2.

The summations accumulated are:

n➝0

Σ(x - y)2 /y➝1

In the normal context for use of chi-square the "observed"value is in x, the "expected" value in y.

The RANDOM key causes the computation of a sequence of pseudo-random numbers, uniformly distributed in the interval 0≥RN≥1. The method used is congruential products. It is necessary for the user to provide a "seed" for the sequence before using the RANDOM key. A given seed will produce the same sequence of pseudo-random numbers each time it is used.

The seed should be stored by the user into register 27. After each depression of RANDOM, the newly-generated pseudo-random will be stored in register 27 as a new seed, and the number will also be presented in the x- register. They y and z registers remain unchanged.

The initial seed provided by the user should be selected with certain rules in mind in order to obtain acceptable pseudo-random number properties. They are:

1. Enter a decimal fraction consisting of 12 digits (i.e., enter a complete number including guarddigits, even though they cannot be seen).

2. The number should be odd.

3. The number should not be evenly divisible by 5.

The LOG10 x, LOGe x, and ex keys provide the specified mathematical function on the argument in x, and the result is left in the x-register. No other registers are changed.

Typewriter ROM Module

When the typewriter ROM module is plugged into the calculator, the keyboard input unit is redefined as shown in FIG. 12 so that the entire keyboard of a properly interfaced tyewriter such as the Facit Model 3841 (hereinafter referred to as the Model 61) may be completely cntrolled by the calculator. The Model 61 is capable of performing three basic operations:

1. Type data contained in the calculator's xregister.

2. Type alphameric messages and control typewriter functions.

3. List programs contained in the calculator memory.

These operations are accomplished by calculator instructions given either from the keyboard or as program steps in a proper sequence. In this section, these instruction sequences will be described. Numerous examples are provided so that the user will be able to manually key the instruction sequences and observe the results. In normal operation, the instruction sequences would be placed in a program.

Table C provides, in brief form, the instruction sequences used to operate the Model 61. The table is not provided to teach typewriter operation; rather, it is provided for quick reference once the instruction sequences are understood.

All of the Model 61 instruction sequences presented in this section can be reduced into component parts consisting of one or more calculator instructions. For example, all of the Model 61 instruction sequences contain the two calculator instructions FMT and 2.

The instructions FMT and 2 service the special purpose of redefining the following calculator instructions so that they will be understood only by the typewriter. The two instructins, when thought of as a component part of an instruction sequence, can be considered as "the typewriter address". Although these two instructions will be shown as part of each of the following instruction sequences, their meaning will not be explained again.

TABLE C ______________________________________ COMMAND SET Instruction Sequence: Typing a Number ______________________________________ Types the number in the x-register in a notation and location specified by the last w.d. instruction. 1. FMT 2 PRINT 2. FMT 2 w.d. w specifies field width (location). The number will be right justified in the field. At turn-on, the calculator assumes a w of 20. 3. FMT 2 w.d. PRINT d specifies the number of digits to the right of the decimal point or specifies floating point. ______________________________________

Alphanumeric Typing

Fmt 2 fmt message FMT

Allows the user to type labels and headings. Also allows control of all keyboard functions except margin setting. Messages may include print instructions. Calculator keyboard has two modes, shifted and unshifted (see keyboard diagram on the back page).

Listing A Program

Fmt 2 list

Lists the contents of the calculator's memory beginning with the present location of the program counter and continuing until an end statement is encountered in the memory or stop on the calculator keyboard is pressed. The listing includes address location, key code, and key mnemonic.

All commands are available on program or manual request.

The instruction sequence FMT, 2, w.d, PRINT allows the user to type the data contained in the calculator's x-register. In this sequence, the notation (fixed or floating point) of the typed data can be specified. In addition, the location where the data will be typed on the typewriter platen may also be specified. This instruction sequence consists of the following component parts:

Fmt 2 -- typewriter address.

w.d. -- Specifies the location and notation of the typed data.

Print -- causes the data point to be typed.

The instruction sequence is initiated with the typewriter address and is terminated by the PRINT instruction. The component parts of the instruction sequence have the following meaning for the typewriter.

w.d. -- This component of the instruction sequence allows the location and notation of the typed data to be specified. The w part of the component specifies the location; the d part specifies the notation. The decimal point in the component delimits the two parts. Although a w cannot be given without also giving a d, they are best explained separately.

w specifies the field width (w) in which the data is to be typed. The left side of the field is defined by the location of the typewriter carriage when the data is typed. The right side of the field is defined by the value of w. For example, if the typewriter carriage were sitting 10 spaces from the left margin setting and w was specified as twenty, then after the data has been typed the carriage will be located 30 spaces from the left margin setting.

Any data typed in a field will automatically be typed in the right most spaces (right justified) of the field. The following drawing illustrates the number 123.45 right justified in a field of ten. ##SPC3##

The field must be large enough to contain the typed data, including the decimal point and any signs that may be present in the data point. If, for one example, the data point were the digit one, a w of one would be large enough to contain the data point; however, if the data point were a negative one, a field width of two would be required. If the field is not large enough to contain the data point, the data will not be typed; instead, the entire field would be filled with asterisks to notify you that the data point could not be fitted into the specified field width.

W may be specified as any number between 1 and 63 (inclusive). Since the data point is always right justified in the field, you will use w to place the data point at the desired location on the typewriter platen. Do not, however, set w so large that the data, when typed, exceeds the right margin setting. If the right margin is exceeded, the program will be stopped at the memory location following the PRINT instruction (explained later) that exceeded the right margin setting and the STATUS lamp will be lit.

When a w instruction is given, the value is automatically stored in the calculator. A w instruction, once given, need not be given again in a program and may be used any number of times when succeeding FMT, 2, PRINT (explained later) instruction sequences.

The value selected for w is lost when the calculator is switched OFF. When the calculator is switched ON a w of 20 is automatically stored.

The d part of the w.d. component allows the user to control the mode of the calculator display from a program and, therefore, the notation (fixed or floating point) of the typed data.

In this instruction sequence, when the data in the calculator's x-register is typed, it will be typed as it is displayed in the x-register. In order to provide the capability of specifying the notation (fixed or floating point) of the typed data, this instruction sequence is capable of controlling the format of the calculator display. This is provided by the d part of the w.d component.

The following table shows the relationship between d and the notation of the typed data.

______________________________________ d Typed Notation ______________________________________ φ decimal part and decimal point are suppressed 1 one digit to the right of the decimal point is typed. 2 two digits to the right of the decimal point are typed. . . 9 nine digits to the right of the decimal point are typed. . │➝ (decimal point) the data will be typed in floating point notation. ______________________________________

A data point in the calculator's x-register will always contain a decimal point; however, if the data point is displayed with no digits to the right of the decimal point (e.g., 10.), the data, when typed, will be typed without the decimal point.

The d part of the w.d component is most easily thought of as a programmable FIX () - FLOAT instruction. It has the same effect as those keys on the calculator display. Also, all of the rules of operation concerning overflow and underflow applicable to the FIX () and FLOAT keys apply equally to d.

In the case of overflow, if the calculator display contains nine digits to the right of the decimal point and a data point containing two digits to the left of the decimal point is entered in the x-register, the register will overflow and display the data point in floating point notation. Exactly the same situation can occur with d. If you specify a d of nine and the data point in the x-register overflows, then the data point will be typed in floating point notation.

There is a potential problem in the interaction between w and d that the operator should be aware of. For example, assume that w has been set for two and d has been specified as zero. If the data point in the x-register overflows and an attempt is made to type the data point, the field width of two will not be large enough to contain the data point in floating notation and two asterisks will be typed.

Whereas an overflow condition which exceeds the field width will cause asterisks to be typed, an underflow condition will not. In an underflow condition, the data point in the x-register has become so small that the d specification does not allow the data point to be displayed with enough accuracy. Like the overflow condition, the data point is, in essence, not typed. For example, assume the value of the data point in the x-register were 1.23 × 10-11 and dwere specified as zero. When the data point is typed it will be typed as zero.

The operator should be aware of the range in which the typed data will lie and set the w.d specification so that neither underflow or overflow occur. If the range is likely to be very great, the field width and d should be set so that the data point is typed in floating point notation (16 . . ).

Because dis essentially stored by changing the format of the calculator display, the value for d remains unchanged until the display format is changed. This can be done by giving another d instruction or by manually pressing the FLOAT or FIX () keys. If, for example, you specify a d of two, stop the program and press FLOAT, then, when the data is typed it will be typed in floating point notation.

The PRINT component of this instruction sequence causes the typewriter to type the data contained in the calculator's x-register. The data will be typed in the location and notation specified by the last w.d component given.

When a FMT, 2, w.d, PRINT instruction sequence has been executed, the instruction sequence will automatically be terminated and the typewriter address reset. This means that if you wished to type the same data twice, the entire instruction sequence (less w.d, explained later) must be given again.

In order to provide maximum programming flexibility, certain component parts of the FMT, 2, w.d, PRINT instruction sequence may, optionally, be omitted from the instruction sequence. The following variations of the sequence are allowable:

Fmt, 2, w.d, PRINT -- Type the data in the

x-register in a specified location and notation.

Fmt, 2, w.d -- Establish a field width (w) and

notation (d) which will be used later in the program by one or more FMT, 2, PRINT instruction sequences.

Fmt, 2, print -- type the data in the x-register

in a location and notation stored earlier in the program.

The FMT, 2, w.d instruction sequence allows you to save program steps by specifying w and d only once in a program and reusing them any number of times with succeeding FMT, 2, PRINT instruction sequences.

The PRINT instruction in these sequences will automatically terminate the instruction sequence and reset the typewriter address. In the case of the FMT, 2, w.d instruction sequence, the instruction sequence is not terminated; however, the next calculator instruction, in addition to performing its normal function will terminate the sequence.

The use of the FMT, 2, w.d, PRINT instruction sequence is illustrated by the following example:

A piece of paper 81/2 inches or wider is placed in the typewriter and the margin stops, paper guide and carriage set as shown below:

Left Margin Right Margin ➝Stop ➝Stop 1 2 3 6 7 0 0 0 0 . . . 0 0 Paper Guide 1 2 3 4 Paper Bail's 0 0 0 0 0 . . . Graduated Typing Scale 1 2 3 4 0 0 0 0 0 . . . Card Holder

The number 1,000 is keyed into the calculator's x-register, and floating point display is selected.

______________________________________ DISPLAY: 1.000000000 03 ➝X PRESS: FMT, 2 1 3 . 2 DISPLAY: 1000.00 ➝X ______________________________________

The w (13) was stored and the d(2) changed the display. The instruction sequence is not terminated, however, and a PRINT instruction may be added:

PRESS: PRINT TYPE-OUT: w = 13, d = 2 1000.00 1 1 2 3 4 0 0 3 0 0 0 ...

The red pointer mark on the CARD HOLDER points to 13 on the PAPER BAIL'S graduated typing scale, not 14 as one might expect. That is because the scale starts at zero, not one.

The PRINT instruction has terminated the instruction sequence. To type the data again will require another instruction sequence:

PRESS: FMT, 2, PRINT TYPE-OUT: w = 13, d = 2 1000.00 1000.00 1 2 2 3 4 0 0 0 6 0 0 . . .

The FMT, 2, PRINT instruction sequence has used the w and d stored in the preceding FMT, 2, w.d instruction sequence. The type-out is right-justified on the twenty-sixth space as the left side of the field is defined by the location of the carriage when the data is typed.

It should be noted that a FMT, 2, w.d PRINT instruction sequence does not contain the capability of a carriage return/line feed instruction. This capability does exist, however, as explained below.

A FMT, 2, w.d instruction sequence is terminated by the next calculator instruction given. In addition to terminating the FMT, 2, w.d instruction sequence, the instruction will be performed in its normal manner.

______________________________________ PRESS: FMT, 2 1 3 . . ↑ DISPLAY: 1.000000000 03 ➝ X, Y ______________________________________

This instruction sequence has specified floating point notation; however, this display can be manually overridden with the FIX () - FLOAT keys:

PRESS: FIX ( ) 2 DISPLAY: 1000.00 ➝ X PRESS: FMT, 2, and PRINT TYPE-OUT: w = 13, d = 2 1000.00 1000.00 1000.00 1 2 3 34 0 0 0 0 90 . . .

Data in the calculator's x-register can be typed without a decimal point. THis is done by specifying a dof zero:

PRESS: FMT, 2, 4, ., 0, and PRINT TYPE-OUT: w = 4, d = 0 1000.00 1000.00 1000.001000 1 2 3 4 4 0 0 0 0 0 3

The data point just typed was typed in a field width of four, just large enough to contain the data. Spaces between this data type-out and the one previously typed could have been provided by specifying a larger field width, w.

Asterisks will be typed across a field that is not large enough to contain the data.

PRESS: FMT, 2, 3, ., 0, and PRINT TYPE-OUT: w = 3, d = 0 1000.00 1000.00 1000.001000*** 1 2 3 4 4 5 0 0 0 0 0 6 0 . . . .

The FMT, 2, FMT, MESSAGE, FMT instruction sequence allows labels and headings to be typed for data. With this instruction sequence, the user can control both characters on each typewriter key and control all typewriter functions directly from the calculator, either by stored program step or manually, from the calculator keyboard.

The instruction sequence consists of the following component parts:

FMT 2 -- Typewriter address FMT -- Established the TYPING - MESSAGES instruction sequence. -MESSAGE -- Your label or heading

Other calculator instructions which terminate this instruction sequence are:

LOAD STOP * STEP FLOAT PRGM RUN KEYLOG RECORD END * BACK STEP FIX ( ) PRGM LIST Programmable instructions.

In the MESSAGE component of this instruction sequence, one programmable calculator instruction will control one typewriter key. Which character on the typewriter key will be typed or which typewriter function will be performed, will depend on the mode of the calculator keyboard when the instruction is given. In the MESSAGE component of this sequence, the calculator can be in one of two modes, unshifted or shifted.

When the instructions FMT, 2, FMT are given, the calculator keyboard will automatically be in the unshifted mode. In this mode of operation, the calculator instructions and the typewriter character typed or function performed have the correspondence shown by the characters and symbols included within the keys of FIG. 12.

The unshifted calculator keyboard can control the typewriter's numbers and capital alphabet. In addition, the functions TAB CLEAR, TAB, CR/LF (Carriage return/Line feed), SPACE, BLACK RIBBON may also be performed. The FMT instruction and the blank keys shown in the diagram will terminate the instruction sequence. Three instructions (PRINT, TAB and SHIFT) available on the unshifted calculator keyboard require special mention.

A PRINT instruction placed in a MESSAGE will cause the data in the calculator's x-register to be typed. The data will be typed in the location and notation specified by the last w.d given. A w.d may not be placed in a MESSAGE; however, they are stored when they are given and automatically recalled and used with a PRINT instruction placed in a MESSAGE.

A TYPING MESSAGES instruction sequence will not affect the contents of the calculator's display registers. Therefore, data can be placed in the x-register and typed with a PRINT instruction placed in this instruction sequence.

Giving a TAB instruction will cause the typewriter carriage to move either to the next tab set or to the right margin setting. If the carriage is less than two spaces from a tab setting and a TAB instruction is given, then that tab setting will be ignored by the typewriter and the carriage will move to the next tab setting or right margin setting.

The SHIFT instruction allows one to change the mode of the calculator's keyboard. If the calculator keyboard were unshifted and a SHIFT instruction was given, then the calculator keyboard would be in the shifted mode. In the shifted mode of operation, the calculator instructions and the typewriter character typed or the function performed have the correspondence shown by the characters and symbols printed below the keys of FIG. 12.

The shifted calculator keyboard can control the typewriter's small letter alphabet and the symbols above the numbers and in addition, the functions TAB CLEAR ALL (CLEAR ALL TABS), TAB SET, CR/LF, SPACE, BACK SPACE. The FMT instruction and the blank keys shown in the diagram will terminate the instruction sequence. The operation of the PRINT and SHIFT instructions on the shifted calculator keyboard are the same as on the unshifted keyboard. The two instructions that require special mention on the shifted calculator keyboard are the CR/LF instruction and the RED RIBBON instruction.

The CR/LF instruction will cause the typewriter to perform a carriage return and line feed. In addition, this instruction will cause the calculator keyboard to become unshifted.

A RED RIBBON instruction will cause the typewriter to type in red. Once red ribbon is selected, only two things can reset the red ribbon, they are, giving a BLACK RIBBON instruction (available on the calculator's unshifted keyboard) or switching the calculator interface OFF. Terminating the TYPING MESSAGES instruction sequence wil not reset a RED RIBBON instruction.

The MESSAGE component of a TYPING MESSAGES instruction sequence may be any number of program steps (limited only by the size of the calculator memory). However, a typewritten line must not be allowed to exceed the right margin setting. If the right margin setting is exceeded, the program will stop at the second memory location following the instruction that exceeded the right margin setting and the STATUS lamp will light.

(It should be noted that if the right margin setting is exceeded in a typing data instruction sequence, the program will stop at the memory location immediately following the PRINT instruction that exceeded the right margin setting.)

Because of the two things an operator must keep track of, an example of TYPING MESSAGES is potentially confusing. For example, if the instruction A were placed in a MESSAGE, the operator could not easily predict whether the character typed would be A or a, further, the color would be unknown. Which character and which color would, of course, depend on whether the calculator keyboard were shifted or unshifted and the status of the ribbon color. The following format makes keeping track of these two things easier and, therefore, helps clarify the examples. ##SPC4##

The format is essentially the standard programming pad format with five additional columns: B, R, S, U and PROG INST. Mark the B and R column so that you will know the status of the ribbon color, red or black. In the S and U columns, you can mark the mode of the calculator keyboard when the instruction is given -- S for shifted, U for unshifted. In the PROG INST column you can record the typewriter instruction that, considering the mode of the calculator keyboard, corresponds to the instruction in the KEY column. In the following examples, the PROG INST column will not be used except for typewriter instruction sequences.

To type messages the typewriter's LEFT MARGIN STOP and PAPER GUIDE are set to zero. The typewriter carriage is positioned against the LEFT MARGIN STOP. A piece of paper 81/2 inches or wider is placed in the typewriter and the RIGHT MARGIN STOP set to 70. The number 123.45 is keyed into the calculator's x-register and a display mode of FIX (), 3 selected. In this example, the MESSAGE "The value is" will be typed followed by the data just entered into the calculator's x-register. This is accomplished by keying in the following instructions: ##SPC5##

TYPE-OUT: The value is 123.45

Steps 0000-0004

The FMT 2 w.d instruction sequence established a field of seven with two digits to the right of the decimal point. The data point (123.45) requires a field width of six; setting the width to seven will ensure that there will be a space between the data and the last character typed.

Steps 0008-0009

The BLK RIBBON instruction in step 0008 will ensure that the MESSAGE in this example is typed in black. Prior to that time the status of the ribbon color was unknown; therefore, neither the B or R column was filled in.

The CR/LF instruction in step 0009 will ensure the MESSAGE is typed against the LEFT MARGIN STOP.

The next example performs the same type of operation with the instruction sequences used in a slightly different manner. In this example the TYPING MESSAGES instruction sequence will be used to type the message "123.45 squared =" in black and then set the red ribbon. Next a TYPING DATA instruction sequence is used to set a field width of ten with four digits to the right of the decimal point, and type the data contained in the x-register.

If the number 123.45 is not still in the x-register from the last example, it is entered into the x-register and the following calculator keys are depressed in the order given: ##SPC6##

In the last example, a BLK RIBBON instruction was given. Since then, the ribbon color has not been changed. Therefore, in step 0003, the B column can be filled in even though a BLK RIBBON instruction was not given.

At step 0024 a RED RIBBON instruction is given so that the data in the x-register will be typed in red. Remember, the red ribbon can be reset to black ribbon by two things only, giving a BLK RIBBON instruction or turning the typewriter interface OFF.

TYPE-OUT: 123.45 Squared = 15239.9025

It may be noted that there is no space in the type-out between the "=" and the data. That can be corrected in two ways:

1. Setting the w specification to 11.

2. Inserting a SPACE instruction immediately following the "=" instruction.

The instruction sequence FMT, 2, LIST allows the user to list a program contained in the calculator memory. The listing will be typed in a column format with each line consisting of the memory location, the mnemonic of the instruction stored in the location and the key code of the instruction. The listing will begin at the location of the program counter when this instruction sequence is given and will continue until either an END instruction is given or STOP on the calculator keyboard is pressed.

(It should be noted that if the ribbon color status is red, the listing will be typed in red.)

This may be illustrated by entering a typewriter exerciser program into the memory of the calculator and then:

PRESS: END FMT 2 LIST TYPE-OUT: ______________________________________ --27--UP --36-- * --25--DN 0003--FMT---42 --02-- 2 0028--SFL---54 0029--S/R---77 0030--PNT---45 0031--CLR---20 0032--S/R---77 0033--END---46 ______________________________________

KEY CODES AND MNEMONICS

All of the keys of the keyboard input unit and their associated octal keycodes and mnemonics are listed in Table D below. Every key has only one keycode and only one mnemonic (if it has a mnemonic), regardless of how many different functions it may be used to perform. The keycodes for the FLOAT, FIX (), RUN, PRGM, KEY LOG, LIST, LOAD, RECORD, BACK STEP, AND STEP PRGM keys are applied to the CPU in seven-bit binary form. Since these keycodes are used only to control the mode of the calculator, are not programmable, and are never printed out by the output printer unit, they have no associated mnemonic. All of the remaining keycodes are applied to the CPU in six-bit binary form, are programmable, and have a mnemonic that may be printed out by the output printer unit.

TABLE D ______________________________________ KEY MNE- KEY MNE- KEY CODE MONIC KEY CODE MONIC ______________________________________ 0 00 0 GO TO 44 GTO 1 01 1 PRINT 45 PNT SPACE 2 02 2 END 46 END 3 03 3 CONTINUE 47 CNT 4 04 4 IF x=y 50 X=Y 5 05 5 LABEL 51 LBL 6 06 6 IF x<y 52 X<Y 7 07 7 IF x>y 53 X>Y 8 10 8 SET FLAG 54 SFL 9 11 9 K 55 K x2 12 XSG π 56 π 13 a PAUSE 57 PSE 14 b E 60 E G 15 G C 61 C F 16 F A 62 A 1/x 17 1/X D 63 D CLEAR 20 CLR int x 64 INT . 21 . I 65 I ROLL ↑ 22 RUP B 66 B x➝() 23 XTO x➝() 67 XFR y⇋() 24 UE M 70 M ↑ 25 DN 0 71 O ENTER EXP 26 EEX L 72 L ↑ 27 UP N 73 N x÷y 30 XEY H 74 H INDIRECT 31 IND J 75 J CHG SIGN 32 CHS √x 76 √ + 33 + SUB 77 S/R RETURN - 34 - RECORD 102 ÷ 35 DIV LOAD 103 × 36 x LIST 104 CLEAR x 37 CLX KEY LOG 105 y➝() 40 YTO PRGM 106 STOP 41 STP RUN 107 FMT 42 FMT FIX () 110 IF FLAG 43 IFG FLOAT 110 ______________________________________

PROCESSING KEYCODES

The manner in which keycodes entered into the CPU from the keyboard input unit or from the program storage section of the memory unit are processed is shown and described in the keycode processing flow chart of FIG. 13. Once the calculator is turned on, it operates in the display routine until a key is depressed. If a FLOAT, FIX (), RUN, PRGM, KEY LOG, LIST, LOAD, RECORD, BACK STEP, or STEP PRGM key (each having a seven-bit keycode) is depressed, the calculator operates in a director routine to determine which of these keys was depressed and thereupon selects the routine for performing the function required by that key. Upon completion of the selected routine, the calculator reverts to operation in the display routine.

If any other key (each having a six-bit keycode), except the CONTINUE key, is depressed and the PRGM key has not been depressed or has been followed by the RUN key, the calculator operates in the interpreter routine to determine which six-bit keycode it has received and to select the appropriate routine for performing the function required by that six-bit keycode. Unpon completion of the selected routine the calculator reverts to operation in the display routine.

If the CONTINUE key is depressed and the PRGM key has not been depressed or has been followed by the RUN key, the calculator operates in a fetch routine to sequentially fetch keycodes, as designated by the user program counter, from the program storage section of the RWM. Each fetched keycode is interpreted and the routine for performing the function required thereby selected in the same manner as if the fetched keycode had been received from the keyboard input unit. However, upon completion of the selected routine the calculator reverts to the fetch routine unless the fetched keycode was a STOP, END, or PAUSE (if the execution of the PAUSE is immediately followed by depression of a key), in which cases the calculator reverts to operation in the display routine.

If any key having a six-bit keycode is depressed and the PRGM key has been depressed and has not been followed by the RUN key, the calculator operates in a store routine to store the six-bit keycode received from the keyboard input unit as a program step in the program storage section of the RWM. Upon completion of this storage operation the calculator reverts to operation in the display routine.

If the KEY LOG key has been depressed and has not been followed by the RUN key or the PRGM key, the calculator also prints out each six-bit keycode received from the keyboard input unit in any of the above-mentioned cases.

The display routine, the director routine, the interpreter routine, the routines for performing the various functions required by the six-bit and seven-bit keycodes, and other routines used by the calculator are shown and described in FIGS. 14-135.

BASIC INSTRUCTION SET

Every routine and subroutine of the calculator comprises a sequence of one or more of 71 basic 16 -bit instructions listed below these 71are all implemented serially by the micro-processor in a time period which varies according to the specific instruction, to whether or not it is indirect, and to whether or not the skip condition has been met.

Upon completion of the execution of each instruction, the program counter (P register) has been incremented by one except for instructions JMP, JSM, and the skip instructions in which the skip condition has been met. The M-register is left with contents identical to the P-register. The contents of the addressed memory location and the A and B registers are left unchanged unless specified otherwise.

Memory Reference Group

The 14 memory reference instructions refer to a specific address in memory determined by the address field -m>, by the ZERO/CURRENT page bit, and by the DIRECT/INDIRECT bit. Page addressing and indirect addressing are both described in detail in the reference manuals for the Hewlett-Packard Model 2116 computer (hereinafter referred to as the HP 2116).

The address field <m> is a 10 bit field consisting of bits 0 through 9. The ZERO/CURRENT page bit is bit 10 and the DIRECT/INDIRECT bit is bit 15, except for reference to the A or B register in which case bit 8 becomes the DIRECT/INDIRECT bit. An indirect reference is denoted by a <, I> following the address <m>.

REGISTER REFERENCE OF A OR B REGISTER: If the location <A> or <B> is used in place of <m> for any memory reference instruction, the instruction will treat the contents of A or B exactly as it would the contents of location <m>. See the note below on the special restriction for direct register reference of A or B.

______________________________________ ADA m, I Add to A. The contents of the addressed memory location m are added (binary add) to contents of the A register, and the sum remains in the A register. If carry occurs from bit 15, the E register is loaded with 0001, otherwise E is left unchanged. ADB m, I Add to B. Otherwise identical to ADA. CPA m, I Compare to A and skip if unequal. The contents of the addressed memory location are compared with the contents of the A register. If the two 16-bit words are different, the next instruction is skipped; that is, the P and M registers are advanced by two instead of one. Otherwise, the next instruction will be executed in normal sequence. CPB m, I Compare to B and skip is unequal. Otherwise identical to CPA. LDA m, I Load into A. The A register is loaded with the contents of the addressed memory location. LDB m, I Load into B. The B register is loaded with the contents of the addressed memory location. STA m, I Store A. The contents of the A register are stored into the addressed memory location. The previous contents of the addressed memory location are lost. STB m, I Store B. Otherwise identical to STA. IOR m, I "Inclusive OR" to A. The contents of the addressed location are combined with the contents of the A register as an "INCLUSIVE OR" logic operation. TSZ m, I Increment and Skip if Zero. The ISZ instruction adds ONE to the contents of the addressed memory location. If the result of this operation is ZERO, the next instruction is skipped; that is, the P and M registers are advanced by TWO instead of ONE. The incremental value is written back into the addressed memory location. Use of ISZ with the A or B register is limited to indirect reference; see footnote on restrictions. AND m, Logical "AND" to A. The contents of the addressed location are combined with the contents of the A register as an "AND" logic operation. DSZ m, I Decrement and Skip if Zero. The DSZ instruction subtracts ONE from the contents of the addressed memory location. If the result of this operation is zero, the next instruction is skipped. The decremented value is written back into the addressed memory location. Use of DSZ with the A or B register is limited to indirect reference; see footnote on restrictions. JSM m, I Jump to Subroutine. The JSM instruction permits jumping to a subroutine in either ROM or R/W memory. The contents of the P register is stored at the address contained in location 1777 (stack pointer). The contents of the stack pointer is incremented by one, and both M and P are loaded with the referenced memory location. JMP m, I Jump. This instruction transfers control to the contents of the addressed location. That is, the referenced memory location is loaded into both M and P registers, effecting a jump to that location. ______________________________________

Shift-Rotate Group

The eight shift-rotate instructions all contain a 4 bit variable shift field <n> which permits a shift of one through 16 bits; that is 1 ≤ n > 16. If <n> is omitted, the shift will be treated as a one bit shift. The shift code appearing in bits 8,7,6,5 is the binary code for n-1, except for SAL and SBL, in which cases the complementary code for n-1 is used.

______________________________________ AAR n Arithmetic right shift of A. The A register is shifted right n places with the sign bit (bit 15) filling all vacated bit positions. That is, the n+1 most significant bits become equal to the sign bit. ABR n Arithmetic right shift of B. Otherwise identical to AAR. SAR n Shift A right. The A register is shifted right n places with all vacated bit positions cleared. That is, the n most significant bits become equal to zero. SBR n Shift B right. Otherwise identical to SAR. SAL n Shift A left. The A register is shifted left n places with the n least significant bits equal to zero. SBL n Shift B left. Otherwise identical to SAL. RAR n Rotate A right. The A register is rotated right n places, with bit 0 rotated around to bit 15. RBR n Rotate B right. Otherwise identical to RAR. ______________________________________

Alter-Skip Group

The 16 alter-skip instructions all contain a 5-bit variable skip field <n> which, upon meeting the skip condition, permits a relative branch to any one of 32 locations. Bits 9, 8, 7, 6, 5 are coded for positive or negative relative branching in which the number <n> is the number to be added to the current address, (skip in forward direction), and the number <-n> is the number to be subtracted from the current address, (skip in negative direction). If <n> is omitted, it will be interpreted as a ONE.

______________________________________ <n>=0 CODE=00000 REPEAT SAME INSTRUCTION <n>=1 CODE=00001 DO NEXT INSTRUCTION <n>=2 CODE=00010 SKIP ONE INSTRUCTION <n>=15 CODE=01111 ADD 15 TO ADDRESS <n>=-1 CODE=11111 DO PREVIOUS INSTRUCTION <n>=-16 CODE=10000 SUBTRACT 16 FROM ADDRESS <n>=nothing CODE=00001 DO NEXT INSTRUCTION ______________________________________

The alter bits consist of bits 10 and bits 4. The letter <s> following the instruction places a ONE in bit 10 which causes the tested bit to be set after the test. Similarly the letter <c> will place a ONE in bit 4 to clear the test bit. If both a set and clear bit are given, the set will take precedence. Alter bits do not apply to SZA, SZB, SIA, and SIB.

__________________________________________________________________________ SZA n Skip if A zero. If all 16 bits of the A register are zero, skip to location defined by n. SZB n Skip if B zero. Otherwise identical to SZA. RZA n Skip if A not zero. This is a "Reverse Sense" skip of SZA. RZB n Skip if B not zero. Otherwise identical to RZA. SIA n Skip if A zero; then increment A. The A register is tested for zero, then incremented by one. If all 16 bits of A were zero before incrementing, skip to location defined by n. SIB n Skip if B zero; then increment B. Otherwise identical to SIA. RIA n Skip if A not zero; then increment A. This is a "Reverse Sense" skip of SIA. RIB n Skip if B not zero; then increment B. Otherwise identical to RIA. SLA n, S/C Skip if Least Significant bit of A is zero. If the least significant bit (bit 0) of the A register is zero, skip to location defined by n. If either S or C is present, the test bit is altered accordingly after test. SLB n, S/C Skip if Least Significant bit of B is zero. Other- wise identical to SLA. SAM n, S/C Skip if A is Minus. If the sign bit (bit 15) of the A register is a ONE, skip to location defined by n. If either S or C is present, bit 15 is altered after the test. SBM n, S/C Skip if B is Minus. Otherwise identical to SAM. SAP n, S/C Skip if A is Positive. If the sign bit (bit 15) of the A register is a ZERO, skip to location defined by n. If either S or C is present, bit 15 is altered after the test. SBP n, S/C Skip if B is Positive. Otherwise identical to SAP. SES n, S/C Skip if Least Significant bit of E is Set. If bit 0 of the E register is a ONE, skip to location defined by n. If either S or C is present, the entire E register is set or cleared respectively. SEC n, S/C Skip if Least Significant bit of E is Clear. If bit 0 of the E register is a ZERO, skip to location defined by n. If either S or C is present, the entire E register is set or cleared respectively. __________________________________________________________________________

Complement Execute-DMA Group.

These seven instructions include complement operations and several special-purpose instructions chosen to speed up printing and extended memory operations.

______________________________________ CMA Complement A. The A register is replaced by its One's complement. CMB Complement B. The B register is replaced by its One's complement. TCA Two's Complement A. The A register is replaced by its One's Complement and incremented by one. TCB Two's complement B. The B register is replaced by its One's Complement and incremented by one. EXA Execute A. The contents of the A register are treated as the current instruction, and executed in the normal manner. The A register is left unchanged unless the instruction code causes A to be altered. EXB Execute B. Otherwise identical to EXA. DMA Direct Memory Access. The DMA control in Extended Memory is enabled by setting the indirect bit in M and giving a WTM instruction. The next ROM clock transfers A M and the following two cycles transfer B M. ROM clock then remains inhibited until released by DMA ______________________________________ control.

Note: Special Restriction for Direct Register Reference of A or B

For the five register reference instructions which involve a write operation during execution, a register reference to A or B must be restricted to an INDIRECT reference. These instructions are STA, STB, ISZ, DSZ, and JSM. A DIRECT register reference to A or B with these instructions may result in program modification. (This is different from the hp 2116 in which a memory reference to the A or B register is treated as a reference to locations O or 1 respectively.) A reference to location 0 or 1 will actually refer to locations 0 or 1 in Read Only Memory.

Input/Output Group (IOG)

The 11 IOG instructions, when given with a select code, are used for the purpose of checking flags, setting or clearing flag and control flip-flops, and transferring data between the A/B registers and the I/O register.

______________________________________ STF <SC> Set the flag. Set the flag flip-flop of the channel indicated by select code <SC>. CLF <SC> Clear the flag flip-flop of the channel indicated by select code <SC>. SFC <SC> Skip if flag clear. If the flag flip-flop is clear in the channel indicated by <SC>, skip the next instruction. SFS <SC> H/C Skip if flag set. If the flag flip-flop is set in the channel indicated by <SC>, skip the next instruction. H/C indicates if the flag flip-flop should be held or cleared after executing SFS. CLC <SC> H/C Clear control. Clear the control flip-flop in the channel indicated by <SC>. H/C indicates if the flag flip-flop should be held or cleared after executing CLC. STC <SC> H/C Set Control. Set the control flip-flop in the channel indicated by <SC>. H/C indicates if the flag flip-flop should be held or cleared after executing STC. OT* <SC> H/C Output A or B. Sixteen bits from the A/B register are output to the I/O register. H/C allows holding or clearing the flag flop after execution of OT*. The different select codes allow different functions to take place after loading the I/O register. SC=00 Data from the A or B register is output eight bits at a time for each OT* instruction given. The A or B register is rotated right eight bits. SC=01 The I/O register is loaded with 16 bits from the A/B registers. SC=02 Data from the A/B register is output one bit at a time for each OT* instruction for the purpose of giving data to the Magnetic Card Reader. The I/O register is unchanged. SC=04 The I/O register is loaded with 16 bits from the A/B register and the control flip flop for the printer is then set. SC=08 The I/O register is loaded with 16 bits from the A/B register and the control flip flop for the display is then set. SC=16 The I/O register is loaded with 16 bits from the A/B register and then data in the I/O register is transferred to the switch latches. LI* <01> H/C Load into A or B. Load 16 bits of data into the A/B register from the I/O register. H/C allows holding or clearing the flag flop after L1* has been executed. LI* <00> The least significant 8 bits of the I/O register are loaded into the most significant locations in the A or B register. MI* <01> H/C Merge into A or B. Merge 16 bits of data into the A/B register from the I/O register by "inclusive or". H/C allows holding or clearing the flag flop after M1* has been executed. MI* <00> The least significant 8 bits of the I/O register are combined by inclusive OR with the least significant 8 bits of the A or B register, and rotated to the most significant bit locations of the A or B register. ______________________________________

Mac instruction Group

A total of 16 MAC instructions are available for operation

a. with the whole floating-point data (like transfer, shifts, etc), or

b. with two floating-point data words to speed up digit and word loops in arithmetic routines.

______________________________________ NOTE: <AO-3 > means: contents of A-register bit 0 to 3 AR 1 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1744 to 1747 (octal) AR 2 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1754 to - 1757 (octal) Di means: mantissas i-th decimal digit; most significant digit is D1 least significant digit is D12 decimal point is located between D1 and D2 Every operation with mantissa means BCD-coded decimal operation. RET Return 16-bit-number stored at highest occupied address in stack is transferred to P- and M-registers. Stack pointer (=next free address in stack) is decremented by one. <A>, <B>, <E> unchanged. MOV Move overflow The Contents of E-register is transferred to A0-3. Rest of A-register and E-register are filled by zeros. <B> unchanged. CLR Clear a floating-point data register in R/W memory on location <A> ZERO➝<A>, <A>+1, <A>+2, <A>+3 <A>, >B>, <E> unchanged XFR Floating-point data transfer in R/W memory from location <A> to location <B> Routine starts with exponent word transfer. Data on location <A> is unchanged. <E> unchanged. MRX AR1 mantissa is shifted to right n-times. Exponent word remains unchanged. <BO-3 > = n (binary coded) 1st shift: <A0-3 >➝D1 ; Di ➝D.sub .i+1 ; D12 is lost jth shift: θ ➝ D1 ; Di ➝Di+ 1 ; D12 is lost nth shift: θ ➝ D1 ; Di ➝Di+ 1 ; D12 ➝ A0-3 θ ➝ E, A4-15 each shift: <B0-3 > - 1 ➝ B0-3 <B4-15 > unchanged MRY AR2 mantissa is shifted to right n-times. Otherwise identical to MRX MLS AR2 mantissa is shifted to left once. Exponent word remains unchanged. θ ➝ D12 ; Di ➝ Di-1 ; D1 ➝ A0-3 <B> unchanged DRS AR1 mantissa is shifted to right once Exponent word remains unchanged θ ➝ D1 ; Di ➝ Di+1 ; D12 ➝ A0-3 ZERO ➝ E and A4-15 <B> unchanged DLS AR1 mantissa is shifted to left once. Exponent word remains unchanged. <A0-3 > ➝ D12 ; Di ➝ Di.su b.-1 ; Di ➝ A0-3 θ ➝ E, A4-15 <B> unchanged FXA Fixed-point addition Mantissas in pseudo-registers AR2 and AR1 are added together and result is placed into AR2. Both exponent words remain unchanged. When overflow occurs "0001" is set into E-reg., in opposite case <E> will be zero. <AR2> + <AR1> + DC ➝ AR2 DC = θ if <E> was 0000 before routine execution DC = 1 if <E> was 1111 before routine execution <B>, <AR1> unchanged FMP Fast multiply Mantissas in pseudo-registers AR2 and AR1 are added together <B0-3 >-times and result is placed into AR2. Total decimal overflow is placed to A0-3. Both ex- ponent words remain unchanged. <AR2> + <AR1> * <B0-3 >+DC ➝ AR2 DC = 0 if <E> was 0000 before routine execution DC = 1 if <E> was 1111 before routine execution ZERO ➝ E, A4-15 <AR1> unchanged FDV Fast divide Mantissas in pseudo-registers AR2 and AR1 are added together so many times until first decimal overflow occurs. Result is placed into AR2. Both exponent words remain unchanged. Each addition without overflow causes +1 increment of <B>. 1st addition: <AR2> + <AR1> = DC ➝ AR2 DC = 0 if <E> was 0000 before routine execution DC = 1 if <E> was 1111 before routine execution next additions: <AR2>+ <AR1> ➝ AR2 ZERO ➝ E <AR1> unchanged CMX 10's complement of AR1 mantissa is placed back to AR1, and ZERO is set into E-register. Exponent word remains unchanged <B> unchanged CMY 10's complement of AR2 mantissa. Otherwise identical to CMY MDI Mantissa decimal increment. Mantissa on location <A> is incremented by decimal ONE on D12 level, result is placed back into the same location, and zero is set into E-reg. Exponent word is unchanged. When overflow occurs, result mantissa will be 1,000 0000 0000 (dec) and 0001 (bin) will be set into E-reg. <B> unchanged. NRM Normalization Mantissa in pseudo-register AR2 is rotated to the left to get D1 ≠0. Number of these 4-bit left shifts is stored in B0-3 in binary form (<B4-15 >=0) when <B0-3 >=0,1,2, ..., 11 (dec) ➝, <E>=0000 When <B0-3 >=12 (dec)➝mantissa is zero, and <E>= 0001 Exponent word remains unchanged <A>unchanged. ______________________________________

The binary codes of all of the above instructions are listed in the following coding table, where * implies the A or B register, D/I means direct/indirect, A/B means A register/B register, Z/C means zero page (base page) (current page, H/S means hold test bit/set test bit, and H/C means hold test bit/clear test bit. D/I, A/B, Z/C, H/S, and H/C are all coded as 0/1.

CODING TABLE __________________________________________________________________________ GROUP OCTAL INSTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 __________________________________________________________________________ 0 MEMORY 0---- AD* D/I 0 0 A/B Z/C ➝ MEMORY ADDRESS ➝ REFERENCE 1---- CP* D/I 0 0 1 A/B Z/C GROUP 2---- LD* D/I 0 1 0 A/B Z/C 3---- ST* D/I 0 1 1 A/B Z/C 4---- IOR D/I 1 0 0 0 Z/C 4---- ISZ D/I 1 0 0 1 Z/C 5---- AND D/I 1 0 1 0 Z/C 5---- DSZ D/I 1 0 1 1 Z/C 6---- JSM D/I 1 1 0 0 Z/C 6---- JMP D/I 1 1 0 1 Z/C SHIFT- 07---0 A*R 0 1 1 A/B -- ➝ SHIFT ➝ 0 0 0 0 ROTATE 07---2 S*R 0 1 1 A/B -- 0 0 1 0 CODE GROUP 07---4 0 1 0 0 S*L 0 1 1 A/B -- 07---6 0 1 1 0 R*R 0 1 1 A/B -- ALTER- 07---0 SZ* 0 1 1 A/B O ➝ SKIP ➝ 0 1 0 0 0 SKIP 07---0 RZ* 0 1 1 A/B 1 CODE 0 1 0 0 0 GROUP 07---0 SI* 0 1 1 A/B 0 1 1 0 0 0 07---0 RI* 0 1 1 A/B 1 1 1 0 0 0 07---1 SL* 0 1 1 A/B H/S H/C 1 0 0 1 07---2 S*M 0 1 1 A/B H/S H/C 1 0 1 0 07---3 S*P 0 1 1 A/B H/S H/C 1 0 1 1 07---4 SES 0 1 1 A/B H/S H/C 1 1 0 0 07---5 SEC 0 1 1 1 A/B H/S H/C 1 1 0 1 REGISTER 07--17 ADA 0 1 1 A/B -- D/I 0 0 0 0 1 1 1 1 REFERENCE 07--37 ADB 0 1 1 A/B -- D/I 0 0 0 1 1 1 1 1 GROUP 07--57 CPA 0 1 1 A/B -- D/I 0 0 1 0 1 1 1 1 07--77 CPB 0 1 1 A/B -- D/I 0 0 1 1 1 1 1 1 07--17 LDA 0 1 1 A/B -- D/I 0 1 0 0 1 1 1 1 07--37 LDB 0 1 1 A/B -- D/I 0 1 0 1 1 1 1 1 07-557 STA 0 1 1 A/B -- 1 0 1 1 0 1 1 1 1 07-577 STB 0 1 1 AB-- 1 0 1 1 1 1 1 1 1 0--17 IOR 0 1 1 A/B -- D/I 1 0 0 0 1 1 1 1 07-637 ISZ 0 1 1 A/B -- 1 1 0 0 1 1 1 1 1 07--57 AND 0 1 1 A/B -- D/I 1 0 1 0 1 1 1 1 07-677 DSZ 0 1 1 A/B -- 1 1 0 1 1 1 1 1 1 07-717 JSM 0 1 1 A/B -- 1 1 1 0 0 1 1 1 1 07--37 JMP 0 1 1 A/B -- D/I 1 1 0 1 1 1 1 1 COMP 07-016 EX* 0 1 1 A/B 0 0 1 1 1 0 EXECUTE 070036 DMA 0 1 1 0 0 1 1 1 1 0 DMA 07-056 CM* 0 1 1 A/B 1 0 1 1 1 0 07-076 TC* 0 1 1 A/B 1 1 1 1 1 0 INPUT 1727-- 1 0 1 1 1 1 1 1 1 1 ➝ SELECT ➝ OUTPUT 1737-- 1 1 1 1 1 1 1 1 1 1 CODE GROUP 17-7-- 1 H/C 1 1 1 0 1 1 1 17-5-- 1 H/C 1 0 1 0 1 1 1 17-5-- 1 H/C 1 0 1 1 1 1 1 17-6-- STC 1 1 1 1 1 H/C 1 1 0 0 17-1-- OT* 1 1 1 A/B 1 H/C 0 0 1 1 17-2-- LI* 1 1 1 A/B 1 H/C 0 1 0 1 17-0-- MI* 1 1 1 A/B 1 H/C 0 0 0 1 MAC 170402 RET 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 GROUP 170002 MOV 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 170000 CLR 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 170004 XFR 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 174430 MRX 1 1 1 1 0 0 1 0 0 0 1 1 0 0 0 174470 MRY 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 171400 MLS 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 170410 DRS 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 175400 DLS 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 170560 FXA 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 171460 FMP 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 170420 FDV 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 174400 CMX 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 170400 CMY 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 170540 MDI 1 1 1 0 0 0 1 0 1 1 0 0 0 0 0 171450 NRM 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 __________________________________________________________________________

DETAILED LISTING OF ROUTINES AND SUBROUTINES OF BASIC INSTRUCTIONS

A complete listing of all of the routines and subroutines of basic instructions employed by the calculator and of all of the constants employed by these routines and subroutines is given below. All of these routines, subroutines, and constants are stored either in the basic ROM or in the plug-in ROM modules employed therewith. Each page of each different group of routines, subroutines, and constants is numbered at the top left-hand corner of the page, and each line of each page is separately numbered in the first column from the left-hand side of the page. This facilitates reference to different parts of the listing. Descriptive headings are also provided throughout the listing to identify routines, subroutines, groups of constants, different portions of the ROM, the plug-in ROM modules, etc. Each instruction of each routine or subroutine and each constant stored in the ROM or plug-in ROM modules is represented in octal form by six digits in the third column from the left-hand side of the page, and the address of the ROM location in which each such instruction or constant is stored is represented in octal form by five digits in the second column from the left-hand side of the page.

Mnemonic labels serving as symbolic addresses or names are given in the fourth column from the left-hand side of the page for most of the constants and many of the instructions to facilitate references to these constants and instructions and associated instructions. The mnemonic code of each basic instruction and of each pseudo instruction is given in the fifth column from the left-hand side of the page. As noted above, each basic instruction is employed as a step in a routine or subroutine of one or more basic instructions and therefore has an address in the ROM. Psuedo instructions such as ORG, EQU, etc. which appear (and are recognizable as not being one of the 71 basic machine instructions listed above) are used for control of the Assembler, which translates the symbolic/mnemonic coding of the fourth, fifth, and sixth columns into the address and contents of ROM registers which appear in the second and third columns. (See chapter 4 of the Hewlett-Packard "Assembler Programmer's Reference Manual" of April, 1970.) They are not employed as steps in the routines and subroutines performed by the calculator and therefore have no addresses in the ROM. Mnemonic operand codes are given in the sixth column from the left-hand side of the page, and descriptive comments are given to the right of the sixth column. The format, assembly, and use of the listing is explained in greater detail in the above-mentioned Hewlett-Packard "Assembler Programmer's Reference Manual". ##SPC7## ##SPC8## ##SPC9## ##SPC10## ##SPC11## ##SPC12## ##SPC13## ##SPC14## ##SPC15## ##SPC16## ##SPC17## ##SPC18## ##SPC19## ##SPC20## ##SPC21## ##SPC22## ##SPC23## ##SPC24## ##SPC25## ##SPC26## ##SPC27## ##SPC28## ##SPC29## ##SPC30## ##SPC31## ##SPC32## ##SPC33## ##SPC34## ##SPC35## ##SPC36## ##SPC37## ##SPC38## ##SPC39## ##SPC40## ##SPC41## ##SPC42## ##SPC43## ##SPC44## ##SPC45## ##SPC46## ##SPC47## ##SPC48## ##SPC49## ##SPC50## ##SPC51## ##SPC52## ##SPC53## ##SPC54## ##SPC55## ##SPC56## ##SPC57## ##SPC58## ##SPC59## ##SPC60## ##SPC61## ##SPC62## ##SPC63## ##SPC64## ##SPC65## ##SPC66## ##SPC67## ##SPC68## ##SPC69## ##SPC70## ##SPC71## ##SPC72## ##SPC73## ##SPC74## ##SPC75## ##SPC76## ##SPC77## ##SPC78## ##SPC79## ##SPC80## ##SPC81## ##SPC82## ##SPC83## ##SPC84## ##SPC85## ##SPC86## ##SPC87## ##SPC88## ##SPC89## ##SPC90## ##SPC91## ##SPC92## ##SPC93## ##SPC94## ##SPC95## ##SPC96## ##SPC97## ##SPC98## ##SPC99## ##SPC100## ##SPC101## ##SPC102## ##SPC103## ##SPC104## ##SPC105## ##SPC106## ##SPC107## ##SPC108## ##SPC109## ##SPC110## ##SPC111## ##SPC112## ##SPC113## ##SPC114## ##SPC115## ##SPC116## ##SPC117## ##SPC118## ##SPC119## ##SPC120## ##SPC121## ##SPC122## ##SPC123## ##SPC124## ##SPC125## ##SPC126## ##SPC127## ##SPC128## ##SPC129## ##SPC130## ##SPC131## ##SPC132## ##SPC133## ##SPC134## ##SPC135## ##SPC136## ##SPC137## ##SPC138## ##SPC139## ##SPC140## ##SPC141## ##SPC142## ##SPC143## ##SPC144## ##SPC145## ##SPC146## ##SPC147## ##SPC148## ##SPC149## ##SPC150## ##SPC151## ##SPC152## ##SPC153## ##SPC154## ##SPC155## ##SPC156## ##SPC157## ##SPC158## ##SPC159## ##SPC160## ##SPC161## ##SPC162## ##SPC163## ##SPC164## ##SPC165## ##SPC166## ##SPC167## ##SPC168## ##SPC169## ##SPC170## ##SPC171## ##SPC172## ##SPC173## ##SPC174## ##SPC175## ##SPC176## ##SPC177## ##SPC178## ##SPC179## ##SPC180## ##SPC181## ##SPC182## ##SPC183## ##SPC184## ##SPC185## ##SPC186## ##SPC187## ##SPC188## ##SPC189## ##SPC190## ##SPC191## ##SPC192## ##SPC193## ##SPC194## ##SPC195## ##SPC196## ##SPC197## ##SPC198## ##SPC199## ##SPC200## ##SPC201## ##SPC202## ##SPC203## ##SPC204## ##SPC205## ##SPC206## ##SPC207## ##SPC208## ##SPC209## ##SPC210## ##SPC211## ##SPC212## ##SPC213## ##SPC214##

MICROPROCESSOR

All of the above-listed routines and subroutines of basic instructions are implemented by the basic computing system shown in FIGS. 3A-B. Central control of this system is achieved by microprocessor 120. As shown in the block diagram of FIG. 136 and in the detailed schematic diagram of FIGS. 137A-D, the microprocessor comprises a bipolar ROM 200 including seven ROM chips organized into 256 words of 28 bits. Eight J-K flip-flops contain the ROM address; (i.e. a 4-bit primary address and a 4-bit secondary address). A single chip 16-bit data selector permits any one of 16 different qualifier lines to be tested with a 4-bit qualifier code. This 4-bit qualifier code ROM chip serves a dual function in that it provides a complementing code to the 4 primary address flip-flops as well as selecting the proper qualifier to be tested. If branching in any ROM state is desired, the microinstruction BRC must also be given. BRC occurring with a QN (qualifier not met) signal from the data selector will cause the least significant bit of the address code to be inhibited to the secondary address flip-flop, thus causing the address to "branch" according to the state of the qualifier.

An additional feature of this ROM organization is the IQN microinstruction (inhibit if qualifier not met). When the IQN is given and the qualifier selected by the qualifier code is not met, the signal CCO (clock code zero) goes low. This inhibits all shift clock pulses from the clock decoder which in effect prevents execution of microinstructions in that ROM state.

To minimize the ROM word length, two three-to-eight-line decoders are used to expand 3 R-code outputs and 3 X-code outputs into a total of 14 microinstructions. Also the SCO and SCI outputs from ROM No. 5 are decoded in the Memory. The ALU code outputs, AC0, AC1, and AC2 are treated as address inputs to the ALU ROM and therefore need no decoding.

The microprocessor is responsible for the following:

1. Issuing a four-bit clock code to the clock decoder during each ROM state.

2. Issuing microinstructions to the memory, including the read and write microinstructions.

3. Issuing microinstructions to the shift registers for gating serial data into or out of the proper registers.

4. Issuing a four-bit ALU code to the Arith Logic Unit to select the proper binary or BCD arithmetic function.

5. Performing logical decisions (branching) based on the states of 16 qualifier inputs to the microprocessor.

6. Issuing next address information to the ROM address flip-flops in the microprocessor.

7. Transferring control to the input/output controller via the I/O strobe for execution of input or output instructions.

The full set of 28 ROM outputs with their associated microinstructions, the list of 16 qualifiers and assigned codes, and the microprocessor mnemonics are contained in the following tables:

MICRO-INSTRUCTION SET __________________________________________________________________________ TABLE POSITIVE NEGATIVE TRUE ➝ TRUE ➝ OUTPUTS ➝ __________________________________________________________________________ CONTROL ROM DECODED μ-INSTRUCTION FUNCTION FIELD OUTPUT OUTPUT __________________________________________________________________________ GENERAL 1. IQN INHIBIT SHIFT CLOCK IF QUALIFIER NOT MET. 2. BRC BRANCH: INHIBITS SOO IF QUALIFIER NOT MET. 3. TTT T BUS ➝ T REG 4. TTM T BUS ➝ M REG - 5. XTR A/B REG ➝ R BUS Decoded In Memory SC1 SC0 S-CODE 6. SC1 ZTS 0 O ZERO ➝ S BUS 7. SC0 MTS 0 1 M REG ➝ S BUS TTS 1 0 T REG ➝ S BUS UTS 1 1 ONE ➝ S BUS Decoded In Microprocesser RC2 RC1 RC0 R-CODE 8. RC2 UTR 0 0 0 ONE ➝ R BUS 9. RC1 PTR 0 0 1 P REG ➝ R BUS 10. RC0 TRE 0 1 0 T REG ➝ E REG ➝ R BUS WTM. ZTR 0 1 1 STORE CONTENTS T REG ➝ MEMORY TQ6. ZTR 1 0 0 T BUS ➝ Q REG (BIT 6) QTR 1 0 1 Q REG ➝ R BUS RDM. ZTR 1 1 0 READ MEMORY <M> ➝ T REG ZTR 1 1 1 ZERO ➝ R BUS Decoded In Microprocessor XC2 XC1 XC0 X-CODE 11. XC2 TTQ 0 0 0 T BUS ➝ Q REG 12. XC1 QAB 0 0 1 Q REG (BIT 11) ➝ AB FLIP-FLOP 13. XC0 BCD 0 1 0 BCD ARITHMETIC MODE OF ALU TBE 0 1 1 T BUS ➝ E REG ➝ R BUS CAB 1 0 0 COMPLEMENT THE AB FLIP-FLOP TTP 1 0 1 T BUS ➝ P REG TTX 1 1 0 T BUS ➝ A/B REG NOP 1 1 1 NONE OF THE ABOVE Decoded In ALU AC2 AC1 AC0 ALU 14. AC2 XOR 0 0 0 EXCLUSIVE OR ...... R + ➝ T BUS 15. AC1 AND 0 0 1 LOGICAL AND ..... R . S ➝ T BUS 16. AC0 IOR 0 1 0 INCLUSIVE OR .... R + S ➝ T BUS ZTT 0 1 1 ZERO ➝ T BUS ZTT. CBC 1 0 0 ZERO ➝ T BUS, CLEAR BINARY CARRY IOR. CBC 1 0 1 INCLUSIVE OR, CLEAR BINARY CARRY IOR. SBC 1 1 0 INCLUSIVE OR, SET BINARY CARRY ADD 1 1 1 BINARY ADD CONTROL ROM FUNCTION FIELD OUTPUT CLOCK 17. CC1 This 4-bit code initializes a presettable 18. CC2 down counter to generate any number - 19. CC4 of shift clocks from 1 through 16. - 20. CC8 Shift is inhibited by IQN if QUALIFIER not met. QUALIFIER 21. QC3 This 4-bit code performs two functions: - 22. QC2 (1.) Addressing the data selector to select - 23. QC1 one of sixteen QUALIFIER inputs, - 24. QC0 (2.) Provides complement code to PRIMARY Flip-Flops. SECONDARY 25. SO3 This 4-bit code provides complement -ADDRESS 26. SO2 code to the SECONDARY Flip-Flops. - 27. SO1 If BRC is given and QUALIFIER is not - 28. SO0 met, the SO0 bit is inhibited. SPECIAL MICRO-INSTRUCTIONS TQR = UTR . XTR ..... TRANSFERS Q14. Q11 ➝ PO4 Q-REGISTER TO PRIMARY ADDRESS Q12 ➝ PO5 as shown Q13 ➝ PO6 Q14 ➝ PO7 IOS = PTR . XTR ........INITIATES - a) TRANSFER OF CONTROL TO I/O IF Q10 = 1 b) SETS "SINGLE SERVICE" FF IN I/O VIA SRA IF Q10 = 0 SPECIAL OPERATIONS BCD SUM ➝ A<0-3> = BCD . UTR . ROM CLOCK CLEAR DECIMAL CARRY = QAB . ROM CLOCK SET DECIMAL CARRY = UTR . BCD . ROM CLOCK DECIMAL ADD = BCD . ZTT ...... T.sup..not >.0-3> + A<0-3> ➝ Q<0-3> 10's COMPLEMENT W/DECIMAL ADD = BCD . ADD ...... ...... T<0-3> + A <0-3> ➝ Q<0-3> __________________________________________________________________________

QUALIFIER SET TABLE __________________________________________________________________________ QUALIFIER CODE QC3 QC2 QC1 QCO MNEMONIC FUNCTION __________________________________________________________________________ 0 0 0 0 QOO SHIFT/SKIP ONE BIT 0 0 0 1 Q01 SHIFT/SKIP TWO BITS 0 0 1 0 QO2 SHIFT/SKIP FOUR BITS 0 0 1 1 Q03 SHIFT/SKIP EIGHT BITS 0 1 0 0 Q04 FAST SQUARE ROOT QUALIFIER 0 1 0 1 Q05 SET BIT IN A/S GROUP; FDV QUALIFIER 0 1 1 0 Q06 T-BUS QUALIFIER VIA TQ6 0 1 1 1 QBC BINARY CARRY FROM ALU 1 0 0 0 QPO P-REGISTER, BIT O, FOR BCD COUNTING 1 0 0 1 Q15 INDIRECT ADDRESS, CLEAR BIT IN A/S GROUP 1 0 1 0 QMR MEMORY REFERENCE QUALIFIER 1 0 1 1 Q10 CURRENT PAGE QUALIFIER FXA QUALIFIER 1 1 0 0 QNR NON-SERVICE REQUEST QUALIFIER 1 1 0 1 Q08 FMP QUALIFIER 1 1 1 0 QDC DECIMAL CARRY FROM ALU 1 1 1 1 * QRD ROM DISABLE (NORMALLY ZERO) __________________________________________________________________________ POP WILL PRESET ROM ADDRESS FLIP-FLOPS AT TURN-ON * QRD MAY BE USED WITH IQN TO INSURE ZERO SHIFT EXCEPT WHEN IN I/O LOOP

MICROPROCESSOR MNEMONICS ______________________________________ Clock Signals ______________________________________ MCK Memory Clock SCK Shift Clock XTC External Clock RCF ROM Clock for Flip Flops RCA ROM Clock for Address Flip Flops IIC Inhibit Internal Clock INH Inhibit Clock IPS Inhibit ROM Clock (Also primary and secondary Flip Flop) CC8 } CC4 Clock Code: Binary Code that CC2 programs the number of CC1 shift clocks CCφ Inhibits Shift Clocks Address Mnemonics POP Power on Preset IQN Inhibit if Qualifier not met BRC Branch Q-Register TQR Transfer Q11, Q12, Q13, Q14 to primary addr. Flip Flops TTQ T-Bus to Q-Register QTR Q-Register to R-Bus Q10} Q9 Q8 Q7 Q6 Q5 Bits 1φ- φ of Q-Register Q4 Q3 Q2 Q1 Qφ-Data Qualifiers QPφ Bit φ of P-Register QRD Qualifier ROM Disable (I/O Interupt) QNR Qualifier No Request (Keyboard Interupt) QDC Decimal Carry QBC Binary Carry Memory SCφ S-Bus Code SCI TTT T-Bus to T-Register TTM T-Bus to M-Register RDM Read Memory WTM Write Memory A, B, P, E-Registers QAB Q-Register to AB Flip Flop AB = φ A-Register Operation AB = φ B-Register Operation TTX (ROM) T-Bus to A or B Register (Originates at ROM Decoder) XTR A or B Register to R-Bus TTP T-Bus to P-Register PTR P-Registers to R-Bus TBE T-Bus to E-Register to R-Bus TRE T-Register to E-Register UTR Units to R-Bus AC2} AC1 Arithmetic Codes for Arithmetic ACφ Logic Unit BCD Decimal Arithmetic SDR Disables ROMs For Single Step Tester Operation ______________________________________

Each of the ROM chips of FIGS. 136 and 137A-D is organized into 256 words of 4 bits each constructed in accordance with the following table, where each L represents a low (or 0) state and each H represents a high or (1) state: ##SPC215## ##SPC216## ##SPC217## ##SPC218## ##SPC219## ##SPC220## ##SPC221##

Each of the 71 basic instructions employed by the calculator is implemented by one or more of the above-described microinstructions and associated control signals issued by the microprocessor. The manner in which this is accomplished is shown and described in detail in the flow charts of FIGS. 138A-H. Each rectangular box of these flow charts represents a state of ROM 200 of the microprocessor and includes the mnemonic of the microinstructions and control signals stored in that ROM state. The number at the upper right-hand corner of each of these rectangular boxes represents the number of shift clock pulses required by the microinstructions of that ROM state. A simplified overview of these detailed flow charts is shown in FIG. 7.

PROGRAMMABLE CLOCK

Given a computing system organized to process binary data serially and under control of microinstructions stored in ROM 200 as shown in FIGS. 3A-B and 136, the implementation of a general purpose instruction set requires that some number of bits be shifted into or out of the storage registers. Depending on the operation being performed, the number of bits may vary from zero to n, where n is the number of bits in a single machine word.

If each clock period of the ROM clock corresponds to a one bit shift, a count loop must be employed to provide the desired number of shifts. A rather large number of such count loops would exist in order to implement an entire instruction set. An alternative method is to provide additional hardware which permits assignment of the desired number of shifts in a single state of ROM 200. Such an arrangement requires a variable cycle time for each state of ROM 200, but results in a very substantive saving in total number of ROM states.

To implement a variable number of shift clocks in a single state of the microprocessor, two separate clocks are required. The shift clock is applied to the data storage registers in the memory, the shift register block, the arithmetic logic unit and the input/output block. The ROM clock is applied to the ROM address flip-flops in the microprocessor, and occurs once for each state in the microprogram. The number of shift clock pulses that occur in any given ROM state is determined by a 4-bit clock code sent to the clock decoder from the microprocessor.

If no shift clocks are desired, a separated signal CC0 from the microprocessor inhibits the shift clock output, independent of the clock code issued in that state. In this way, any number of shifts between and including zero and 16 may be implemented with a 4-bit clock code and an inhibit signal.

This inhibit signal offers an additional powerful feature when gated by the qualifier test logic in the microprocessor as shown in FIG. 136. The qualifier test logic including a 4-bit qualifier code from ROM 3 that selects one of 16 qualifier inputs to the data selector. The data selector output QN (qualifier not met) will be high if the selected qualifier input was low. By using the QN signal to gate the inhibit microinstruction, IQN, the shift clock will be inhibited only when the qualifier is not met. Thus all microinstructions requiring shift clocks that are issued in a given ROM state may be either executed or inhibited, depending on the logical state of the qualifier under test.

The ROM clock is applied to the eight J-K flip-flops which address the 256 word microprocessor ROM. During any given state, the complementing (J-K) inputs to the four primary address flip-flops are set up by the qualifier code or q-register code. the four secondary address flip-flop inputs are determined by the ROM 4 outputs, the BRC microinstruction, and the data selector output QN. Where ROM clock goes low, the negative edge-triggered flip-flops will cause transition of the ROM address to the next ROM state.

As shown in the block diagram of FIG. 139 and the detailed schematic diagram of FIGS. 140A-C, a crystal controlled system clock output is inverted to generate memory clock, MCK. This signal is again inverted to clock a D flip-flop having an output (control clock), which will go low if the end-of-count signal (borrow) from the down counter has occurred at the D input. The ROM clock will also go low at this time, initiating a new ROM state in the microprocessor. Control clock will normally remain low for one system clock period, and in turn generates a load signal which is delayed a half period from control clock by means of a second D flip-flop. The 4-bit clock code from the microprocessor is preset into the counter while the load signal is low.

As the load signal goes high, ROM clock also goes high, completing the fixed interval portion of ROM clock and shift clock as shown in FIG. 141. A series of clock pulses are now gated onto shift clock, SCK, until the preset counter has counted down to zero, causing control clock to again go low, completing the ROM cycle.

The inhibit signal, INH, from memory may lengthen the normal fixed interval of ROM clock by clearing the D flip-flop and holding control clock low. This may occur during memory refresh or external test operations. In this situation, the counter remains preset and the correct number of shifts will be generated when the inhibit goes away.

SHIFT REGISTER UNIT

As shown in the detailed schematic diagrams of FIGS. 137A-D and 142A-D, A-register 122, B-register 124, P-register 126, Q-register 128, and E-register 130 comprise bipolar status registers, the contents of which are recirculated when data is output to the R-bus or the S-bus. Full control of these registers in use and type of operations performed is maintained by the microinstructions from the from the microprocessor. The number of bits to be shifted in any one ROM state of the microprocessor is determined by the number of shift clocks from the clock decoder. This shift clock appears at the shift clock input of each shift register that is enabled by the microprocessor during that ROM cycle.

ARITHMETIC LOGIC UNIT

The development of complex and read-only memory arrays on a single chip have made possible a hardware implementation of central processing units (CPUs) and arithmetic logic units (ALUs) with far fewer components than were previously possible. In this application, two bipolar read-only memory chips are combined with carry flip-flops and adapted to perform 1-bit binary logic and arithmetic operations as well as 4-bit binary coded decimal (BCD) arithmetic operations. The two bipolar read-only memory chips may comprise, for example. Hewlett-Packard 16-pin dual-in-line packaged bipolar ROMs organized into 256 words by 4-bits and of the same type as shown and described in U.S. Pat. App. Ser. No. 12,262 filed Feb. 18, 1970 by John C. Barrett et al. and assigned to the same assignee as this patent application.

The binary/BCD Arithmetic Logic Unit consists of five integrated circuits connected as shown in the block diagram of FIG. 143 and the detailed schematic diagram of FIGS. 142A-D. Specifically, the packages consist of two 1024-bit ROMs, a dual D-type flip-flop and two quad two-input NAND gates. The function code input BCD selects between the binary mode and BCD mode of operation.

In the binary mode, the function code inputs AC0, AC1, and AC2 select the desired logical function or arithmetic operation as given in FIG. 144. The binary input data enters ROM No. 1 on the carry, S-bus and R-bus input lines, and the binary result appears on the T-bus and binary carry output lines. ROM No. 2 is not used in the binary mode.

In the BCD mode of operation, the two function code lines AC0 and AC1 are disabled from the Micro-processor and these two lines carry the TO2 and TO3 bits of BCD data from the T-Register. The ALU function code line AC2 is used to select the desired BCD operation. If AC2 is low, the 4-bit output Σ0, Σ1, Σ1, Σ3 will be the BCD sum of the two BCD data inputs. If AC2 is high and decimal carry has been set, the 4-bit output Σ0, Σ1, Σ2, Σ3 will be the BCD Tens Complement of the BCD data from the T-Register. In the BCD mode, the binary carry output will be disabled and the decimal carry output will be enabled to ROM No. 1.

Although only one-fourth of the available registers in ROM No. 1 are required for the eight binary operations, the concept of adding a second 1024-bit ROM to perform the BCD operations grew from several basic concepts:

1. The least significant BCD sum bit, Σ0, is always identical to the binary sum bit; therefore, only three additional outputs, Σ1, Σ2, and Σ3 need be generated. For BCD complement operations, the decimal carry flip-flop defines whether or not the least significant bit should be complemented.

2. In forming the "nine's complement" of the T-Register BCD data in ROM No. 1, it can be seen that for 8421 code the second least significant bit TO1 is the same before and after forming the complement. Thus only two bits, TO2 and TO3 need be complemented prior to input into ROM No. 2. The ten's complement with add is then found by presetting decimal carry and performing a BCD sum of the three most significant digits in ROM No. 2.

3. With only eight ROM inputs available, some sharing of inputs is required for ROM No. 1. During binary operations, all four function codes and only one bit of T-Register data is required. During BCD operations, all four bits of T-Register data and only two function codes are required. Use of two NAND gates in wire-OR connection with the open collector function codes AC0 and AC1 permits sharing of the two inputs.

This arrangement left one input still available to ROM No. 2. By programming this input to always make output DCI true, the micro-instruction UTR can serve two purposes--placing units on the R-bus and also set decimal carry if BCD is true. When BCD is false, clock is inhibited to decimal carry. This feature permits saving decimal carry information during all binary operations. Similarly, binary carry is saved during the four binary operations AND, IOR, XOR, and ZTT by connecting AC2 such that when AC2 is false the shift clock is inhibited to the binary carry flip-flop.

In summary, the mode select input BCD performs the following functions:

1. Addresses the proper 128 word set of word lines in ROM No. 1.

2. Enables the TO2 and TO3 data lines to ROM No. 1 only in BCD mode.

3. Enables clock to decimal carry flip-flop only in BCD mode.

4. Selects binary carry or decimal carry into ROM No. 1 as appropriate.

5. Transfers outputs Σ0, Σ1, Σ2, Σ3 to A-Register only in BCD mode.

The remaining three ALU function codes select the proper set of word lines in ROM No. 1 to perform the eight binary functions listed in FIG. 144. In addition, the AC2 input performs the following functions.

1. Enables clock to binary carry flip-flop only during the four carry-related binary functions and the BCD comp/add function.

2. In the BCD mode, AC2 causes BCD data bit TO0, TO2 and TO3 to convert the nine's complement form.

The ALU has a total of 15 inputs which include eight data inputs, two clock inputs and five microinstructions. Four data output lines are required, and two additional output lines from carry flip-flops are available as qualifier inputs to the microprocessor. The ALU and shift register mnemonics are listed in the following table:

SHIFT REGISTERS & ALU BOARD MNEMONICS ______________________________________ TRE T-Register to E-Register to R-Bus TOφ Bit φ of T-Register TBE T-Bus to E-Register to R-Bus TTX - TEST T-Bus to A/B-Register from Tester TTX - I/O T-Bus to A/B-Register from I/O (Board No. 12) TTX - ROM T-Bus to A/B-Register from μ-Processor (Board No. 13) TTX Logical "OR" of Three TTX Signals AB Status of AB-Flip-Flop AB = O A-Reg. Operation AB = 1 B-Reg. Operation XTR A/B Register to R-Bus UTR Logical "1" to R-Bus TQR Q-Register to Primary Address Flip-Flops AB Complement of AB TTP T-Bus to P-Register SCK Shift Clock QPφ Qualifier, Bit φ of P-Register PTR P-Register to R-Bus QOφ Q-Register Bit φ QTR Q-Register to R-Bus RCK ROM Clock QAB Q-Register to AB-Flip-Flop, also clears decimal carry. SCB Set Binary Carry QDC Qualifier, Decimal Carry BCD Decimal Arithmetic AC2 ALU Operation Code QBC Qualifier, Binary Carry S-BUS Data Bus AC1 ALU Operation Code ACφ ALU Operation Code TO2 Bit 2 of T-Register TO3 Bit 3 of T-Register SDR Signal to Disable ROMs TO1 Bit 1 of T-Register T-BUS Data Bus ALU Arithmetic Logic Unit ______________________________________ () Indicates Negative True Signal

FIG. 145 lists five dual-in-line integrated circuits that may be employed in the ALU. The following table gives an example of how the two ALU ROM chips shown in FIGS. 142A-D and 143 can be constructed to implement the above described ALU functions (in this table each 1 represents a low state and each 0 represents a high state): ##SPC222## ##SPC223##

MEMORY UNIT

The calculator uses an all semiconductor memory system. Peripheral circuitry is bipolar and the memory consists of n-channel MOS read only memory (ROM) and p-channel MOS read/write memory (RWM).

Addressing and physical layout of the memory module is done so that the number of words can be increased from 3K in the basic machine to 7.5K in the largest machine. The smallest increment of memory that can be added in 512 words. Provisions have been made to contain all add-on RWM within the memory module. Add-on ROM is external to the memory module, behind the display.

The basic machine contains 3K words of memory, organized into 2K × 16 ROM, 512 × 16 and 512 × 6 RWM. The 16 bit RWM words are divided into 109 user registers (four words) and 76 words for processor use. The 6 bit RWM words are program steps. The largest machine contains 5K words of ROM and 2.5K words of RWM, of which 512 words are 16 bit.

Read/Write Memory

As shown in FIGS. 146-150 memory is made up of 1024 × 1, dynamic, Read/write memory chips (Intel 1103). These devices are P-channel, MOS using silicon gate technology. To maintain the contents of memory, the device must be refreshed every 2 ms. This is accomplished by performing a read cycle at a given address. On each chip are 32 refresh amplifiers so that each read cycle, 32 cells get refreshed. The entire chip is then refreshed by cycling through the lower 5 address bits and reading each distinct address. The refresh period is 20 μs at least every 2 ms.

Logic levels on all input lines to the RWM chips are 0 to + 16v. This includes the three clock lines (chip select, Y-enable or write, and precharge), 10 address lines, and input data. The output data, however, is a current of 600 μa or more into 1K ohms or less. This low level output is "wire-or able" with other chips to build larger systems.

Read Only Memory

As shown in FIG. 146, 147, 151, and 152 ROM chips are 4096 bit, n-channel MOS arranged 512 × 8. The devices are static and consume no power when not enabled. Data is retrieved from the ROMs by pulling the chip enable line from 0 to + 12v (turning the chip on), addressing the desired cells (0 or 4v levels) and selecting which output devices are to be enabled (4v or 0v). The output levels are sufficient to drive one TTL gate directly, and can be "wire-or/ed" for large systems.

As further shown in FIGS. 153 and 154 A-D, each ROM chip comprises six input buffers. These input buffers generate both the input and its complement. On the basis of the 64 possible combinations of the 6-inputs I0 -I5, one of the 64 lines in the decoder is selected. The selected line enables one of the vertical lines in the 64 × 64 bit storage array. For example, let I0 - I5 = 0 and I6 - I8 be "don't cares". This means line X00 (octal) is selected.

The two 8 out of 32 select decoders must choose 16 lines from the 64 horizontal lines selected by the vertical line X00- (The 8 out of 32 select decoder is actually a 2 out of 8 decoder repeated 4 times in each of the section A - B.) The output from four MOS FET's a, b, c, and d are wire or/ed. MOS devices a', b', c', and d' are also connected similarly. If I6 and I7 = 0, horizontal lines 1XX, 2XX, 3XX, 5XX, 6XX, 7XX are grounded in each of the four sections A-B. This insures that MOS FET's b, c, d, b', c', and d' are non-conductive. This allows signals on lines 0XX and 4XX to pass into the output sections through transistors a and a'.

The output section contains the output buffer, 1 out of 2 decoder, and the output drivers s. The output butter provides a stage of gain and "wire or's" four lines from the storage array. The 1 our of 2 decoder clamps the gates of 2 of the 4 output drivers in each section A-B by enabling either line I8 or its complement (I8). This disables 1 of 2 signals coming from the output buffer. The output drivers then can be tied together with line (e) for a 512 × 8 organization.

Each of the above-listed constants and routines and subroutines of basic instructions employed by the calculator is stored in these ROM chips. This is accomplished by partitioning the 0 to 16,777 octal addresses of the memory map of FIG. 4 into 51210 × 810 blocks which is the capacity of each 4096-bit ROM chip. These blocks are represented in the memory map of FIG. 155. The next step is the inversion of the 8 bits (if the input was 1, it is now a 0) and complimenting of the address (i.e. once the octal addresses 0 - 16,777 are partitioned into 512 × 8 blocks, only the last 3 octal digits are important). For this reason, address 7778 goes to 000,7768 goes to 001, ......., and 000 goes to 7778.

The 16 bits of each constant and basic instruction are stored in the 51210 × 810 ROM chips by organizing the ROM chips into 64 × 64 bit matrices and computing the row and column numbers of each bit of each matrix by operating on each address and the particular bit (15 through 8, or 7 through 0). The column number is computed by subtracting the last two digits of the address from 1008. For example, the column number of address 000 = 1008 - 008 = 100 = 6410 and the column number of address 777 = 1008 - 778 = 1. The computation of the row number (referred to as IR in the flowchart of FIG. 156) can best be described by referring to the flowchart of FIG. 156 and the associated table of FIG. 157. Once the row and column numbers are found it is a simple matter of storing in that location of the matrix that particular bit (i.e., a 1 or a 0). A 0 is stored at a designated location by forming a metal gate to complete a MOS FET device at that location, and a 1 is stored at a designated location by leaving off the metal gate so that a MOS FET device is not formed at that location.

M-register

As shown in FIGS. 146, 147, and 158 A-D included on the M-Register board is the 16 bit Address or M-Register, all chip enable decoding and buffering, and address buffers for both ROM and RWM. The register uses four, four bit, serial in and out, parallel in and out shift Registers. Upon receipt of a TTT instruction from the microprocessor, serial data from the T-Bus is accepted into the M-register. Nothing is done with this data until either a read or write instruction is received, then one of two decoders are enabled. These chip Enable decoders uniquely decode which block of 512 words, either ROM or RMW, is being addressed. If ROM is being addressed, the signal is inverted and amplified to +12v. For RWM the Chip Enable enables a gate, which allows a 16 Volt clock signal to reach the enabled RWM chips. The clock wave-form is generated on the control card.

The dynamic characteristic of the RWM chips, requires that all chips be enabled simultaneously during a refresh cycle, to refresh the entire read/write memory. The buffer circuits in the output of the Chip Enable decoders allow the chip select clock to reach all of the RWM chips during refresh but only those being accessed, during a read or write cycle.

Open collector nand gates with resistor pull-ups are used as buffers for the ROM address lines. Using the open collector gates, the address lines can be pulled above the required 4v level. The nand gates are enabled during a memory cycle so that the ROM address lines are inhibited at a 5v level. The RWM address lines must pull from 0v to + 16v. High voltage, open collector, inverters with discrete transistor pull-ups are used as buffers for the 5 most significant bits. The 5 least significant address bits are bussed to the control card where they are used in part of the refresh circuitry.

Control

A memory cycle consists of a read or write instruction from the processor accompanied by 12 clock pulses from the shift clock. As shown in FIGS. 146, 147, 159 A-D, and 160 control uses these pulses and instructions to generate the clocks required by the RWM chips. A synchronous 4 bit counter (SN74193) is used to count clock pulses and the 4 outputs are decoded by a 1 of 16 decoder (SN74154) to generate J and K input to flip-flops. The outputs from the flip-flops are then buffered to become the required clock signals (Precharge, Y-enable, chip select).

Refreshing the read/write memory is also taken care of by the control card. An astable multivibrator with a repetition rate of 500 hz. minimum generates a signal which allows a refresh cycle to occur. A flip-flop generates the actual signal (REF), but only if the astable multivibrator signal is high, there is no read or write cycle in progress and the processor signal, CCT, is high. CCT goes high between processor instructions, thus it is known that nothing is going to be interrupted when REF is generated. REF is then buffered by an open collector inverter and given to the processor as INH. INH halts the machine and the refresh cycle begins.

The same counter used for a memory cycle, is used during refresh to again generate the necessary clocks (Precharge and chip select). When the counter returns to state 0 and REF is present, a second counter is advanced one count. This second counter provides the refresh addresses which go to the RWM only if REF is present. When this counter returns to state 0, it causes REF and INH to return to preset conditions and the machine continues normal operation.

A further function of the control card is to make the 1024X1 memory chips appear to the processor like 512 × 2 chips. This is done by accessing the RWM twice during each memory cycle. Hence, half-way through each refresh or memory cycle a flip-flop changes state to generate one address bit. The M-register thus provides only 9 address bits and the control card 1 bit, independent of the M-register.

Other signals generated on the control card, direct the flow of data in the T-register.

T-register

Data to and from the memory is temporarily stored in the T-register. As shown in FIGS. 146, 147, and 161 A-D four 4-bit, serial in and out, parallel in and out shift registers make up the actual T-register. The registers have a mode control (TMC) which when low, allows serial data flow and when high, allows parallel data flow.

Serial data enters the T-register in the presence of a TTT instruction. Data is serially transmitted to the S-bus during a TTS instruction, and simultaneously recirculated into the T-register to prevent loss of data.

Parallel data is accepted from either ROM or RWM during a read cycle. The ROM data is buffered by nand gates and the RWM by sense amplifiers followed by the same nand gates. Multiplexing the RWM means that only one-half the data bits are transmitted between RWM and the R-register during each half of the memory cycle. The first half of the read cycle, the odd bits are loaded into the T-register. To complete the transfer these bits must be shifted right one place and the odd bits again loaded from the RWM. This is done by allowing the odd bits to appear as data at the input of the even bits. When new data is clocked into the T-register during the second half of the read cycle, the even inputs are also clocked in, filling the T-register. This isn't done with ROM since all ROM is transferred 16 bits parallel.

Data is written into memory in a manner similar to the way data is read from RWM. The bits are 16v levels, after buffering, and are written by the odd bits followed by the even bits. The nand gates between the T-register and the 16v buffers are gates from the control card to handle the write multiplexing.

INPUT-OUTPUT CONTROL UNIT

The input-output control unit allows the calculator to communicate with the internal input, input-output, and output units and with external peripheral devices. As shown in FIGS. 140 A-C and 162 A-D, the input-output control unit is contained on two printed circuit boards; the "Control and System Clock" board and the "I/O Register and Gate Interface" board. A third board, shown in FIG. 163, is an I/O motherboard providing room for connecting four external interface cards to the calculator.

The internal input, input-output, and ouput units are distinguished from peripheral devices by the fact that the I/O language set addresses them directly. Hence each I/O instruction contains an internal peripheral address as part of its makeup. The five internal directly-addressable input, input-output, and output units are the I/O register, the magnetic card reader, the output printer, the x-, y-, and z- register display, and the keyboard mode lights.

The external peripheral devices are indirectly addressable and are connected via cable to an interface card which is plugged into the I/O motherboard at the rear of the calculator. The term indirectly addressable is defined here to mean the external peripheral devices are addressed by lines leading from the four most significant bits in the I/O register, thereby requiring an address word to be loaded into the directly addressable I/O register.

I/o control and system clock section

the function of the I/O Control and System Clock Section is to provide control to the I/O Register and Gate Interface Section. This is accomplished by use of an I/O instruction set stored in the main memory of the calculator.

The microprocessor causes instructions from the memory unit to be loaded into the T-Register and then to be transferred to the Q-Register. The microprocessor determines the type of instruction and causes the proper execution of the instruction. If the instruction is an I/O type, control is transferred by the microprocessor to the I/O Control and System Clock Section.

The microprocessor remains in a two state waiting loop while the I/O Control section is active. Time in the wait loop is between 0.72 μ seconds and 6.5 μ seconds.

Bits 5 through 10 from the Q-Register are connected to the I/O Control section and remain constant during an I/O instruction execution time. Bits 5 through 8 representing the I/O instruction code are gated to the I/O address flip flops and entered on each clock time while the I/O is inactive. The four outputs of the address flip flops are connected to the address input of a 1 of 16 decoder and represent the starting state address of the I/O instruction to be executed. When the I/O Control Section is enabled, the input gates passing bits 5 through 8 to the I/O address flip flops are closed and the 1 of 16 decoder enabled. This allows the starting state I/O micro instructions to come from the 1 of 16 decoder. The next state address coming from the closed input gates will be the exit state (1111=178) unless modified by reopening the gates to let the original starting state code through or by modifying the output of one or more of the input gates using a "wire or" connection coming from the 1 of 16 decoder output. This address is sent to the I/O address flip flops inputs and clocked in on the leading edge of the first half clock cycle. The first half clock cycle turns off the 1 of 16 decoder and the address changes. The second half clock cycle enables the 1 of 16 decoder, allowing the next state micro instruction to appear. (See FIG. 164 for the timing described above.) The process continues until the exit state is encountered. On the exit state, the I/O Control is disabled and control is returned to the microprocessor.

The I/O instructions involving the transfer of data between the I/O and the CPU (OT, LI, MI), require 16 passes through the same state (1 pass for each of 16 bits). This is achieved by checking the output of a 16 bit down counter and then decrementing after each pass through the state. If the counter indicates 0 has not been reached, it causes the starting state address to be reloaded into the address flip flops by opening the input gates. When 16 passes have been indicated by the counter, the input gates are not allowed to open; however, the next state (1111) is modified by the output of the 1 of 16 decoder through a wire-or connection on the 2cd bit to give state 1101. This address is input to the I/O address flip flops as in the preceeding paragraph.

The above-described operation of the I/O control section is also illustrated and further described in the flow chart of FIG. 165.

Bit 9 is called a hold/clear bit. It allows a clear flag (CLF) to take place or not to take place after execution of the other I/O instructions. (STF excepted)

Bit 10 is used in conjunction with the micro instructions PTR and XTR to give control to the I/O.

The I/O control and programmable clock mnemonics are given in the following table:

I/O CONTROL BOARD MNEMONICS ______________________________________ CCφ Clock Code Zero CC1 do. One CC2 do. Two CC4 do. Four CC8 do. Eight CCT Control Clock to Tester CEM Call Extended Memory CLC Clear Control CLF Clear Flag DRC Data Register Clock EBT Eight Bit Transfer EOW End of Word IIC Inhibit Internal OSC INH Inhibit Clock IPS Inhibit Primary/Secondary ITS Input to S-Bus MCK Memory Clock POP Power On Pulse PTR P-Reg to R-Bus QFG Qualifier Flag Q5 do. Five Q6 do. Six Q7 do. Seven Q8 do. Eight Q9 do. Nine Q10 do. Ten QRD do. ROM Disable RCA ROM Clock Address RCF ROM Clock Flip Flop SCB Set Carry Bit SCK Shift Clock SCT Shift Clock to Tester SRA Service Request Acknowledge STC Set Control STF Set Flag TCK Tester Clock TTO T-Bus to Output TTX T-Bus to A/B Reg. XTO External OSC XTR A/B Reg. to R-Bus ______________________________________ Note: () indicates negative true signal

I/o register and gate interface section

as shown in FIGS. 162 A-D, the directly addressable I/O Register (address 01) is a 16 bit universal (Parallel in/out, Serial in/out) register that is connected to the calculator processor by the serial-in S-Bus and the serial-out T-Bus. Information is passed non-inverted from the A or B registers bit serial to the I/O Register with the I/O instruction OTX 01. Sixteen lines connected to the parallel outputs of the I/O Register provide data out to the internal input, imput-output, and output units and to the external output interfaces. (NOTE: each I/O unit or interface may place only 1 TTL load on the output lines.)

Parallel entry to the I/O Register is through 12 party lines connected to the 12 least significant parallel inputs. The input lines are negative true with all input interfaces tying to the lines through open collectors. Care must be taken to insure there is no disturbance to the lines while an interface is inactive. Input information is passed inverted to the A or B Register Bit serial with the I/O instructions LIX 01 or MIX 01. (The inversion puts positive true information into the A or B register.)

Input information is entered into the I/O Register in three ways:

a. Service Request.

Entry by the service request method is controlled by a service inhibit flip flop. When the service inhibit flip flop has been cleared with the I/O instruction CLF 01, a service request may be initiated by returning the SSI (Service Strobe Input) party line to ground through an open collector on the interface. This signal causes the parallel inputs to be strobed into the I/O Register and sends a request for service (QNR) to the microprocessor. The microprocessor prior to receiving a request for service would have been cycling through various instruction paths and checking for a service request after execution of each instruction. Upon receipt of a request for service, the processor interrupts the sequence of instructions it was doing and loads an address into the M-Register which contains the starting address of the service routine. At the same time a signal, SRA (Service Request Acknowledge), turns off the service inhibit flip flop and also sets the single service flip flop which permits only one service interrupt to the processor per service strobe input. The single service flip flop is reset when the service strobe is removed. All lines from an interface using the service request method for entering information are inhibited when the Service Inhibit flip flop is set.

b. Return of Channel Flag After Command was Given to an External Peripheral Device.

This method implies the calculator must control the peripheral. That is to say the calculator transmits the indirect address and control enable (CEO) from the "I/O Register and gate interface" section to the interface with the expectation of information being returned by the peripheral through the interface to the I/O Register. Because of this expectation, only limited instructions may be performed by the calculator while waiting. The Service Request method must be inhibited during this wait so that input information is not destroyed by another peripheral using Service Request.

When a controlled peripheral responds, its flag and data are processed at the interface. The signal CFI (Channel Flag In) causes the loading of parallel data from the interface into the I/O register and clears the control enable flip flop so that the CEO signal is removed from the interface. The calculator can interrogate the Control Enable flip flop with the instructions SFS 01 or SFC 01 to determine when data has been loaded in.

c. Giving the I/O Instruction STF 01.

The instruction STF 01 as described in a sets the service inhibit flip flop inhibiting the service request mode of entry. The STF 01 instruction also causes a parallel load of the input lines into the I/O Register.

The I/O Register is used to transfer data and control between the calculator and the directly addressable magnetic card reader (address 02). To record information on a card, the control word and data is transferred from the A Register to the I/O Register. The I/O instruction STC02 clocks this information via MLS into a latch located at the card reader. The strobe bit for the recorded data is output to the I/O Register from the B Register. The I/O instruction STF02 clocks the strobe latch located at the card reader via MCR. The I/O instruction STF01 loads status from the card reader into the I/O Register (see 1-C). This status is transferred to the A or B Register where it is processed.

To enter information from the magnetic card reader a control word is transferred from the A-Register to the card reader latch as above. When a strobe is encountered from the card, the card reader sends a signal, MFL, to the I/O Register and gate interface section, which sets the magnetic card flag flip flop. The I/O instruction SFS02 is used to determine the state of the magnetic card flag flip flop. When the flip flop is set, data is loaded into the I/O Register with the I/O instruction STF01.

The directly-addressable output printer (address 04) requires 26 bits of parallel information from the calculator. Sixteen bits come from the I/O Register and 10 bits come from a register at the printer. A 16 bit word with "don't cares" in the least 6 significant bits is transferred to the I/O Register with the I/O instruction OTX 01. A second 16 bit word is transferred to the I/O Register with the instruction OTX 04. The 10 valid printer bits already in the I/O Register overflow into the 10 bit printer register. The significance of the address 04 in the OTX instruction is that it allows the microinstruction EOW (End of Word) to set the printer enable flip flop after the 16th bit has been transferred. At the end of the printers response it returns a signal (PTF) to the printer enable flip flop clearing it. The printer enable flip flop can also be cleared with the I/O instruction CLF 04. The state of the printer enable flip flop is checked with the I/O instructions SFC 04 or SFS 04.

The directly-addressable output display (address 08) recieves information from the I/O Register. A 16 bit word is transferred to the I/O Register with the instruction OTX 08. The address 08 allows the display enable flip flop to be set with the micro-instruction EOW after the 16th bit has been transferred. The display enable flip flop sends a signal DEN to the display indicating information is ready in the I/O Register. The display enable flip flop is cleared with the I/O instruction CLF 08.

The directly-addressable keyboard indicator lights (address 16) are used to indicate the mode for various keys. The lights are driven from a latch or series of latches which get information from the I/O Register. Information is transferred to the I/O Register with the I/O instruction OTX 16. After the 16th bit has been transferred, the microinstruction EOW and address 16 send a signal KLS which strobes the information from the I/O Register into the keyboard lights latch.

The keyboard does not have an address. It transfers information to the CPU through the I/O Register using the Service Request method described in a above. The keyboard is disabled while the service inhibit flip flop is set except for the stop key which when depressed sends the signal STP which is processed independent of the service inhibit flip flop.

All external peripheral interfaces are indirectly addressed from the four most significant bits in the I/O Register. Thus to communicate with an external peripheral, an address (0000 excluded) must be loaded into the I/O Register. Data and status will be loaded at the same time if the peripheral is to act as a receiver. If the peripheral is to act as a transmitter, only the address and status need be loaded. Next, the I/O instruction STC 01 sets the Control Enable Out flip flop. This flip flop sends a signal CEO to all external interface slots. The CEO signal and the decoded (from the 4 bit address) address allow the interface to command the peripheral. After the peripheral has responded, information given back to the interface by the peripheral is processed to the I/O Register in the manner described under b, "Return of Channel Flag After Command was Given to an External Peripheral Device".

The I/O Register and gating control circuit mnemonics are given in the following table:

I/O REGISTER AND GATE BOARD ______________________________________ CEC Control Enable Out CFI Channel Flag In CLF Clear Flag COφ, 1,2,3 Code Out DEN Display Enable DIφ, 1,2,3,4,5,6,7 Data In DOφ, 1,2,3,4,5,6,7 Data Out DRC Data Register Clock EBT Eight Bit Transfer EOW End of Word IOD I/O Data KLS Key Lights Strobe MCR Mag Card Reset MFL Mag Flag MLS Mag Latch Strobe PEN Printer Enable POP Power On Pulse PTF Printer Flag Qφ Qualifier Bit φ Q1 do. 1 Q2 do. 2 Q3 do. 3 Q4 do. 4 QFG do. Flag QNR do. Not Request SIH Service Inhibit SIφ, 1,2,3 Status In SOφ, 1,2,3 Status Out SRA Service Request Acknowledge SSI Service Strobe In STC Set Control STP Stop STF Set Flag T-Bus T-Bus TTO T Bus to Output ______________________________________ NOTE: () indicates negative true signal

As shown in FIG. 166, when addressing a peripheral device, bits loaded into the four most significant locations in the I/O register from the CPU constitute the peripheral address code. As part of the output party line system the address code is routed to all I/O interface slots. Each I/O interface card decodes the four line address code to a unique single line for use on that particular I/O card. The binary codes 10 through 15 have been reserved for dedicated peripheral addresses which are used by dedicated keys (from the keyboard) and dedicated I/O drivers. Binary codes 1 through 9 are for general use. Code 0 is a non-addressing code and is used in operations that do not involve addressing a specific peripheral. The following table summarizes the address code assignments:

ADDRESS CODE ASSIGNMENTS ______________________________________ ADD- 4-BIT ASSIGNED PERIPHERAL RESS CODE ______________________________________ 15 HHHH TYPEWRITER 14 HHHL PLOTTER 13 HHLH 12 HHLL KEYBOARD & KEYBOARD-LIKE PERIPHERALS 11 HLHH 10 HLHL 9 HLLH GENERAL USE; ONE OF NINE SELECTABLE 8 HLLL do. 7 LHHH do. 6 LHHL do. 5 LHLH do. 4 LHLL do. 3 LLHH do. 2 LLHL do. 1 LLLH do. φ LLLL USED ON INTERRUPT I/O INTERFACE CARDS WHEN THE INTERRUPT BECOMES ENABLED ______________________________________

The general usage codes (1-9) are decoded outputs from a four line to 1 of 10 decoder (SN 7442 for example). It is intended that the codes 1 through 9 be jumper selectable. This would allow the user to select a code for his system peripherals or allow him to use more than one of the same peripheral by selecting different address codes.

Since the I/O register is used to communicate with the internal input, input-output, and output units as well as peripheral devices, a given peripheral's address code will appear randomly in the I/O register address field with there being no intention of expecting the peripheral to respond: Therefore, a second piece of information is necessary for the I/O interface card to form a unique signal which will indicate to the peripheral to respond. This second piece of information is control information and is described hereinafter.

The I/O interface cards contain TTL compatible logic for manipulating control and data from the calculator and/or the peripheral. All I/O interface cards which are intended to be used with the calculator must provide storage either on the I/O interface card or in the peripheral. Thus data being transferred from the calculator to the I/O card must be stored at the instant the peripheral is requested to respond. Likewise data coming from a peripheral must be stored until the calculator accepts it. This requirement is important and must be considered on all compatible interface cards.

The calculator can supply up to 100 ma. maximum at +5 volts to each I/O interface card. Power exceeding this absolute maximum must be supplied by the peripheral.

The following table lists the pin assignments for all I/O lines at the plug-in slots on the calculator back plane, as viewed from the rear of the calculator, left to right.

______________________________________ EXTERNAL I/O INTERFACE PIN ASSIGNMENTS ______________________________________ 1 A 2 +5 B +5 3 USED C USED 4 USED D 10/20 5 USED E USED 6 DI φ F DO φ 7 DO 1 H DO 2 8 DI 3 J DO 3 9 DI 2 K DI 1 10 DO 4 L DI 4 11 DO 5 M DI 5 12 DO 6 N DI 6 13 DO 7 P DI 7 14 SO φ R SI φ 15 SO 1 S SI 1 16 SO 2 T SI 2 17 SO 3 U SI 3 18 CO φ V CO 1 19 CO 2 W CO 3 20 SSI X SIH 21 CEO Y CFI 22 Z STP ______________________________________

FIG. 167 lists all I/O lines with brief definitions and specifications and FIG. 163 shows the source and relative relationship of the I/O lines. The output address data lines (Co O-3) transmit the address code along the party lines to all interface slots. These lines will go high and low according to information being shifted in or out of the I/O Register. At anytime a peripheral is addressed the lines will become steady 1 instruction time (8 μs) before control information is passed to the I/O interface card or before data or status is taken from the I/O interface card or before data or status is taken from the I/O interface card and will remain constant until the control information is removed. After the control information is removed, the state of the I/O lines become unpredictable until the next addressing takes place. Address data coming to the I/O interface card is positive true and each interface may place 1 TTL load on each address line.

The output data lines (DO 0-7) output data from the A or B accumulator in 8 bit bytes from the eight least significant locations in the I/O register to all interface card slots. The logic state is positive true (Data = 1 = High). Each interface card may place 1 standard TTL load on each data line.

The output data status lines (SO 0-3) output status data from the A or B accumulator and are driven from the next four locations above the data out positions in the I/O register. (DO positions = 0 thru 7; SO positions = 8 thru 11.) These lines are used for sending additional information to a peripheral. The logic state is positive true. One standard TTL load may be placed on each output data status line. (Special drivers, fast data transfer, and interrupt do not make use of SO 3.)

The input data lines (DI 0-7) transmit input data in 8 bit bytes to the eight least significant bit positions of the I/O register (locations 0 thru 7) from the I/O interface card. Each "Data In" line has a 1K pull up resistor to +5 volts and under the party line system must be driven low for a logical 1 from open collector gates on each addressed I/O interface card. The logic state is negative true.

The input data status lines (SI 0-3) receive information from the I/O interface cards and transmit it to locations 8 through 11 in the I/O register. Each line has a 1K pull us resistor to +5 volts. These lines are used to provide additional information to the calculator about the state of a peripheral. The logic state is negative true.

The negative true "Device Ready" output line (CEO) transmits a control signal, which when combined with an address code will initiate a peripheral response on the addressed I/O interface card. Device Ready is controlled by the I/O interface driver and therefore may look different depending upon the driver. For example, when the calculator wishes to transmit data to the I/O interface card or to initiate a peripheral response prior to receiving data from the peripheral, the calculator causes the Device Ready output lines to go low and stay low until the peripheral response is over and the calculator receives the signal "Device Request" (CFI) from the I/O interface card. The Device Ready flip-flop always receives a clear signal whenever the I/O reister completes a parallel load.

The Device Request party line CFI when driven low from an open collector gate on the I/O interface card will cause the loading to parallel input information into the 12 least significant locations of the I/O register. The active state of the line is low (negative true).

The peripheral flag, indicating to the I/O interface card the peripheral has received data/control or is ready to input data, is gated through an open collector nand gate onto the Device Request (CFI) party line. The open collector gate is enabled by the I/O interface card's address and Device Ready (CEO). The Device Request line is pulled up inside the calculator by a 1K resistor to +5 volts.

The Device Request (CFI) signal must stay low until Device Ready (CEO) has been cleared (goes high). At this time data transfer has terminated and peripheral's flag and control must be cleared in preparation for the next pass. Since a parallel load in the I/O register causes the Device Ready flip-flop to receive a clear signal, when a Device Request (CFI) is entered, a parallel load takes place and afterward Device Ready (CEO) is cleared. The calculator uses Device Request in its general mode of data transfer.

The Half Status output line (STP) is a line that goes low when the STOP key on the calculator is depressed. It will stay low for the duration of the key depression. One standard TTL load may be placed on this line by each I/O interface card.

The prevent Interrupt output line (SIH), when low indicates to the I/O interface card that a request for service must not be given to the calculator. One standard TTL load may be placed on this line by each I/O interface card.

The Service Request (Lo) lines (SSI), when driven low, causes the loading of parallel input information into the 12 least significant locations of the I/O register and causes a CPU interrupt for service. The peripheral's request for service is gated with the Prevent Interrupt (SIH) line onto the Service Request party line through an open collector nand gate. A 1K pull-up resistor to +5 volts is connected to the line inside the calculator.

The line 10/20 is used on the I/O interface card to differentiate between the present calculator and other calculators, thereby permitting the use of compatible I/O interface cards. It is grounded in the case of the present calculator and open in the case of others.

The general format for all data transfer consists of 8 bit parallel bytes (this calculator, like the Hewlett-Packard model 9100 calculator uses a 7 bit field). Other data formats are handled by specially developed drivers, such as the ROM plug-in module employed for driving the typewriter.

The state of a peripheral is generally checked before attempting an output. This is done by first inhibiting the interrupt system. The address of the I/O interface card is shifted into the I/O register. The decoded address code enables the open collector gates on the I/O interface card. The status of the peripheral is passed to the Status In lines and loaded into the I/O register with an I/O instruction issued by the calculator. The I/O register information is transferred to the A or B accumulator and processed. If the peripheral is ready, the output data word consisting of the address code, output status (if necessary) and the eight bit data byte is formed in the A or B accumulator. The output data word is transferred to the I/O register after which the Device Ready (CEO) flip-flop is set. The I/O interface card receives the data, address code and Device Ready and a peripheral response is initiated. The calculator interrogates the state of the Device Ready flip-flop to determine when the I/O interface card has received the information and the peripheral response is done. The peripheral I/O interface card signals the calculator it is done by transmitting the Device Request (CIF) signal to the calculator. The output waveforms are shown in FIG. 168.

Before inputing data from an I/O interface card it is necessary to determine if the peripheral has responded and is ready to input data. After a peripheral response has been initiated, as described previously, the calculator waits for the Device Request (CFI) which loads the data into the I/O Register and clears the Device Ready (CEO). The calculator checks the state of Device Ready and when it goes false (CEO = HIGH), the calculator knows data is present in the I/O Register and proceeds to shift it into the A or B accumulators for processing. The input waveforms are shown in FIG. 169.

When blocks of data are to be transferred between a peripheral and the calculator, the interrupt is turned off, and transfer rates as high as 100,000 bits/sec may be possible. Before either input or output of a block of data can start, it is necessary for the calculator to check the status of the peripheral to see if it is turned on and ready. Register will remain unchanged during the block transfer. A single I/O instruction shifts the 8 bit byte of data from the eight least significant locations in A or B to the eight data locations in the I/O Register; gives Device Ready (CEO) goes low) 120 ns after the shift is completed; and shifts the 8 most significant bits in A or B to the eight least significant locations in A or B in preparation for the next transfer. (Note the Address and status field in the I/O Register are not disturbed in the shifting). Device Ready stays true (low) until the peripheral has received the data and is ready for more. The I/O interface card then returns Device Request (CFI) to the calculator. The receiving of Device Request by the calculator causes loading of the parallel input party lines into the input status and input data locations of the I/O Register, and clears the Device Ready signal (CEO) goes high). The logic sense of Device Ready is observed by the calculator and when it goes false (CEO = High) the CPU proceeds to output the next eight bit byte of data.

If the output I/O interface card is not returning information on the input lines all input lines will be high when the loading, described in the preceding paragraph, takes place. Therefore, if at the beginning the code in the output status field is being used by the I/O interface card and must remain something other than all high it will be necessary for the I/O interface card to receive the output status from the calculator and return it back to the status inputs so that when Device Request occurs the status field does not get changed in the I/O Register.

Input: After determining if the peripheral is ready to start transferring a block of data the calculator turns off the interrupt and shifts the address code into the I/O Register. (The Address code remains unchanged during the block transfer.) The Device Ready is given (CEO = Low) to the calculator when the 8 bit data byte is ready for input. The Device Request signal causes the input data and status to be loaded into the I/O Register and causes Device Ready to go false (CEO = High). The calculator by checking when Device Ready goes false knows the data has been loaded. A single I/O instruction shifts the 8 bit data byte from the I/O Register into the eight most significant locations in the A or B accumulators (shifting the previous information in A or B 8 places to the right) and causes Device Ready to go true (CEO = Low) 120 ns after the last bit has been shifted into A or B. As before if output status is to be retained on the I/O interface card it must be returned to the I/O Register upon each input data transfer. Wave forms illustrating high speed operations resemble the wave forms for the calculator in FIGS. 8 and 9.

The interrupt system is controlled by the Service Inhibit flip-flop. An interrupting peripheral is allowed to request service for input from the processor anytime the Prevent Interrupt line is disabled (SIH = High). The calculator allows only those peripherals which use the calculator key-codes to interrupt, and these must be user controlled such that only one interrupt at a time is taking place. Data (keycodes) is loaded into the I/O Register at the instant the Service Request is given by the I/O interface card (SSI = Low) if Prevent Interrupt is disabled (SIH = High) or if Prevent Interrupt having been enabled (SIH = Low) goes high while Service Request is being given. At the same time a qualifier is routed to the CPU indicating a request for service is active. Recognizing the request for service the CPU branches to the service routine which enables Prevent Interrupt (SIH = Low) and loads the starting address for the software service routine into the M-Register. After servicing the interrupt entry the Prevent Interrupt is disabled (SIH = High) and the next interrupt allowed to take place. The interrupt waveforms are shown in FIG. 170.

The following table lists the general I/O instruction set and the associated codes:

__________________________________________________________________________ I/O INSTRUCTION SET NAME INSTRUCTION INSTRUCTION CODE EXECUTION TIME 13 15 14 13 12 11/ 10 9 8 7 6 5 4 3 2 1 0 __________________________________________________________________________ STF 9 μs H H H H -- H L H H H H SELECT CD CLF 9 μs H H H H -- H H H H H H do. SFC 9 μs H H H H -- H H/C H H H L do. SFS 9 μs H H H H -- H H/C H L H L do. CLC 9 μs H H H H -- H H/C H L H H do. STC 9 μs H H H H -- H H/C H H L L do. OT* 15 μs H H H H A/B H H/C L L H H do. LI* 15 μs H H H H A/B H H/C L H L H do. MI* 15 μs H H H H A/B H H/C L L L H do. __________________________________________________________________________

The following describes the function of each I/O instruction with the five allowable select codes.

__________________________________________________________________________ STF <SC> Set the flag. STF is a 240 ns positive true pulse which accomplishes the follow- ing with the various select codes. STF φφ Not used by the calculator. STF φ1 a. Sets the Service Inhibit flip-flop to the true state (SIH=Low; in- terrupt not allowed). b. Causes parallel input data and status to be loaded into the I/O Register. STF φ2 Generates a 240 ns positive true MCR pulse for the magnetic card reader. STF φ4, φ8, 16 Not used by the calculator. CLF <SC> Clear the flag. CLF is a 240 ns positive true pulse which accomplishes the follow- ing with the various select codes. CLF φφ Not used by the calculator CLF φ1 a. Clears the Service Inhibit flip-flop to the false state. (SIH=High; interrupt allowed.) b. Loads address locations in I/O Re- gister with φ's. (φ=Low) c. Clears Device Ready flip-flop (CEO= High). CLF φ2 Clears magnetic card reader flag flip- flop. CLF φ4 Clears Printer Enable flip-flop (PEN= Low). - CLF φ8 Clears Display Enable flip-flop (DEN= High). - CLF 16 Generates a 240 ns positive true KLS pulse. SFC <SC> H/C Skip if flag clear. SFC is a 240 ns positive true pulse which accomplishes the following with the various select codes. If C is given a 240 ns CLF pulse is given after SFC. SFC φφ Causes the next instruction to be skipped if the STOP key has not been depressed. SFC φ1 Causes the next instruction to be skipped if Device Ready is true (CEO=Low). SFC φ2 Causes the next instruction to be skipped if the magnetic card reader flag flip- flop is clear. SFC φ4 Causes the next instruction to be skipped if the printer enable flip-flop is clear. (PEN=Low). SFS <SC> H/C Skip is flag set. SFS is a 240 ns positive true pulse which accomplishes the following with the various codes. If C is given then a 240 ns CLF Pulse is issued after SFS. SFS φφ Causes the next instruction to be skipped if the STOP key is depressed. SFS φ1 Causes the next instruction to be skipped if Device Ready is false (CEO=High). SFS φ2 Causes the next instruction to be skipped if the magnetic card reader flag flip-flop is set. SFS φ4 Causes the next instruction to be skipped if the printer enable flip-flop is set (PEN=High). CLC <SC> H/C Clear Control. CLC is a 240 ns negative true pulse and is not used by the calculator. If C is given then a 240 ns positive true CLF pulse is given after CLC. STC <SC> H/C Set the Control. STC is a 240 ns posi- tive true pulse which accomplishes the following with the various select codes. If C is given a 240 ns CLF pulse is issued after STC. STC φφ Not used by the calculator. STC φ1 Sets the Device Ready flip-flop (CEO= Low). STC φ2 Generates a 240 ns positive true MLS pulse for the magnetic card reader. STC φ4, φ8, 16 Not used by the calculator. OTX <SC> H/C Output A or B causes data bits from A or B to be shifted to the I/O Register and accomplishes the following with the various select codes. If C if given, a 240 ns CLF pulse is given after OTX is executed. OTX φ φ The 8 least significant bits in the A or B register are shifted non-inverted to the 8 least significant locations in the I/O Register, and 120 ns after the 8th shift the Device Ready flip-flop is set (CEO=Low). The 8 most significant bits are shifted right 8 places and the least 8 significant bits are recirculated to the 8 most significant locations in the A or B registers. The 8 most signi- ficant bits in the I/O Register are un- touched. OTX φ1 Sixteen bits from the A or B re- gister are shifted non-inverted to the I/O Register. The data in A or B recirculates. OTX φ2 Not used by the calculator OTX φ4 Same as OTX φ1 and in addition, 120 ns after the 16th bit has been shifted the printer enable flip-flop is set. OTX 08 Same as OTX φ1 and in addition, 120 ns after the 16th bit has been shifted the display enable flip-flop is set. OTX 16 Same as OTX φ1 and in addition, 120 ns after the 16th bit has been shifted the 240 ns KLS signal is generated. LIX <SC> H/C Load into A or B. Loads data bits from the I/O Register into the A or B Registers and accomplishes the following with the various select codes. If C is given, a 240 ns CLF pulse is given after LIX is executed. LIX φφ The eight least significant bits in the I/O Register are shifted inverted to the eight most significant locations of A or B, and 120 ns after the 8th shift the Device Ready flip-flop is set (CEO=Low). A or B is shifted right eight places as the I/O Register data comes in. The 8 most significant bits in the I/O Register are untouched. LIX φ1 The 16 bits of the I/O register are trans- ferred inverted to the A or B register. Data in the I/O Register is lost. LIX φ2, φ4, φ8, 16 Not used by the calculator. MIX <SC> H/C Merge into A or B. Merges data from the I/O Register into A or B registers and accomplishes the following with various select codes. If C is given, a 240 ns CLF pulse is given after MIX is executed. MIX φφ The eight least significant bits in the I/O register are merged with the eight least significant bits of the A or B register and shifted to the 8 most signi- ficant locations of A or B; 120 ns after the merge takes place the Device Ready flip-flop is set (CEO=Low). A or B shifts right 8 places as the data is merged and shifted to the most significant locations. The 8 most significant bits of the I/O Register are untouched. MIX φ1 The 16 bits of the I/O Register are merged with the 16 bits of the A or B register and contained in the A or B register. __________________________________________________________________________

MIX 02, 04, 08, 16 Not used by the calculator.

Examples of various drivers which transfer data are given below:

Example 1: Typical Subroutine to Get Status of I/O Device.

Calling Sequence:

LDB Select Code JSM Stat ______________________________________ Stat STF 1 Turn off the interrupt system. OTB 1 Load I/O Register with select code. STF 1 Load I/O Register with status of I/O device. LIA 1 Loan A Register with status information. CLF 1 Turn on interrupt. RET Return. ______________________________________

Example 2: Typical Subroutine to Output an 8 bit character.

Calling Sequence:

OTA 1 Output 16 bits to the I/O Register. STC 1 SFS 1 Loop until I/O flag is set by the JMP *-1 output device. CLF 1

Example 3: High speed output where the calculator is faster than

output device

Calling Sequence:

ST* I -(Number of 16 bit words to be output)+1 ST* J Address of first word in the array. LDB SC Select Code JSM OUT2 OUT2 JSM STAT Get status of output device RAR 9 and position it.

Example 4A: Typical subroutine to input an 8 character.

Calling sequence is:

LDB Select code JSM In ... Return is made with the data in the A Register. ______________________________________ In STF 1 Turn off interrupt system OTB 1 Load I/O Register with the select code STC 1, C Pulse the flag & turn interrupt system on JSM STAT Get status off the input device RAR 9 and position it. SAP *-2, C If device is busy then continue to SAR 7 loop else position data bits RET Return. SAP OUT2 If device is busy, continue to loop STF 1 Turn off interrupt system. OTB 1 Output select code LDB 1 B➝Counter for number of words to be output LDA J, I Load next data word SEC *+1, C E➝φ OTA φ Output 8 bits from A SFS 1 Loop until device sets JMP *-1 flag. SEC *-3, S If E=φ and E➝J then loop to output last 8 bits ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished. CLF 1 Turn on interrupt system RET Return ______________________________________

Example 3B: If the output device is faster than the calculator then

fewer instructions can be used.

. . . OTAφ Output first 8 bits OTAφ Output second 8 bits. . . .

Example 5A: High speed input where the calculator is faster than

the input device.

Calling sequence:

ST* I (Number of 16 bit words to be input)+1 ST* J Address LDB SC Select code JSM In2 In 2 JSM STAT Get status of input device RAR 9 and position it. SAP In2 If device is busy, continue to loop STF 1 Turn off interrupt system OTB 1 Output select code STC 1 Command device to read LDB I R➝Counter for number of words to be input SEC *+1, C E➝φ SFS 1 Loop until input JMP *-1 device sets flag LIA φ Load 8 bits from I/O Register SEC *-3, S If E=φ and E➝1 then loop to input last 8 bits STA J, I Save data word in array ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished. CLF 1 Turn on interrupt system RET Return

Example 5B: If the input device is faster than the calculator then

the number of instructions can be reduced.

. . . LIA φ Input first 8 bits LIA φ Input second 8 bits . . .

All output I/O interface cards which are to be fully interchangeable with both the present and other calculators must have storage either on the I/O interface card or in the peripheral to which information is being transmitted. FIG. 171 illustrates the logic used to interface an X-Y plotter which has storage on the I/O interface card.

Blocks A and B are the storage latches which store information coming from the I/O register. When the output of gate C goes high, data is latched; when low, the outputs of the latch track the inputs. Gates D decode the Address code (14 = 1110) and pass it positive true to gate E. Device Ready (CEO) is also passed positive true to gate (E). Gates (H) are open collector and pass status and Device Request (CFI) onto the input party lines. An example of a 9810A output would be: Output the address 14 which enables status gates H and see if the power is on. If on, output address, status, and data to gates A, B, and D. The output of C is low allowing data and status to pass. Next give Device Ready (CEO = Low) this enables flip-flop G, clocks flip-flop F which causes A and B to latch, and sends control to the peripheral. The peripheral acknowledges receipt of control by returning FLAG (FLAG = High) in a busy state this continues to keep A and B latched and clears control flip-flop F. When the peripheral is done acting, the FLAG is returned to the not busy state (FLAG = Low) which clocks flip-flop G and causes output at C to go low enabling A and B. The output of G drives the CFI gate which has been enabled from E and CFI goes low. CFI is received by the calculator which responds by returning CEO high. This causes the output of E to go low, clearing flip-flop G and returning CFI high. This completes one output cycle.

All input I/O interface cards which are to be fully interchangeable with both the present and other calculators must have storage either on the I/O interface card or in the peripheral from which information is being received. FIG. 172 illustrates the logic required on a general purpose interface card with storage.

Block A is used to store information coming from the peripheral. B stores status coming from the I/O register which may be needed by the peripheral. The output tracks the input whenever the enable on the latch is low. Block C decodes the address code into one of 10 addresses which are jumper selectable. An example of a calculator input would be as follows. The address code would be decoded by C. The calculator would load status through the open collector input status gates D. If the peripheral is on and ready, the address code and output status (if necessary) would be sent to B and C. The decoded address is passed, positive true, to gate E. The enable at B is low so that status is passed to the peripheral. The Device Ready is given (CEO = Low) and comes to E positive true. The output of E clocks flip-flop F through gate H. The output of F gives control to the peripheral and also enables A to receive data. The peripheral responds in a busy state (FLAG = High). When data is ready to be input the FLAG is driven low. Data is latched when the FLAG goes low in A. Also when FLAG goes low, G, having been enabled by the output of H, is clocked driving J from its Q output. I is enabled by the output of H and so CFI is driven low. Data is loaded into the I/O register from open collector gates I and CEO driven high as a result of the calculator receiving CFI. This clears flip-flop G and disables the input gates I completing an input cycle.

FIG. 173 illustrates the logic required, on an I/O interface board, to input using the interrupt.

A power preset circuit, block A, will be necessary on this card to prevent an interrupt when the peripheral power is turned off or on. This can usually be done by sensing the peripherals' +5 volts and presetting when the voltage drops below 3 to 4 volts.

The calculator must be in a display routine such that the Prevent Interrupt is false (SIH = High) before an interrupt can take place. This enables the flip-flop B to be clocked from the peripheral FLAG. The clock inputs to E and F have been high enabling the storage latches prior to the receipt of FLAG. FLAG clocks B causing E and F to latch, enabling open collector gates H through gates I and J, and drives gate G which sends Service Interrupt (SSI = Low) to the calculator. The calculator responds by loading the data into the I/O register and returning Prevent Interrupt true (SIH = Low). This clears (B). Prevent Interrupt is returned false after the entry has been processed and the cycle is complete.

KEYBOARD INPUT UNIT

The keyboard input unit is shown in FIGS. 174A-D and 175. It includes a contactless keyboard of the type shown and described in U.S. Patent application Ser. No. 74,949 entitled NONCONTACTING KEYBOARD, filed on Sep. 24, 1970, issued as U.S. Pat. No. 3,668,697 on June 6, 1972, and assigned to the same assignee as this patent application. The contactless keyboard is made up of an array of printed circuit transformers. Each transformer has its secondary and primary interlaced in a spiral coil as shown in FIGS. 176-177. The secondaries of all the coils are tied in series to form the sense line. The primaries of the coils are arranged in separate pairs. Each coil is connected in series, with opposite polarity, to its pair as shown in FIG. 178. Every pair has a drive and sink line, which is being selected and driven by the scanner.

Centered above each coil is a metal disc at the end of the key shaft. When a key is depressed the disc proximates the coil. The disc acts like a shorted turn and reduces the coupling of the coil, and unbalances the pair. This unbalance is amplified by the comparator, when it is greater than the on bias. The comparator triggers the one shot, which turns off the scanner and lowers the on bias. The scanner remains at its present state, which corresponds to the drive and sink line of the key depressed. This state is the keycode of the key pressed. When the key is released a spring retracks the key and disc. When the unbalance is less than the new bias, the comparator turns off and the scanner starts again ready for a new key. The two bias levels give the key mechanical hysteresis.

When two keys are depressed the first one down will be entered, and as long as a key is down no other key can be entered. An exception is when the other key is its pair. In this case the two keys will cancel each other. When the first key is released, the second one will be entered. When the first key is released, while more than one other key is down, the next key to be entered will be the next in the scan sequence, not necessarily the second key down.

For the keyboard to work each pair of primary coils must be balanced. To balance a pair of coils the following rules should be used when laying out the printed circuit board:

1. Sense lines must run in pairs. The closer the better. They should be thin traces.

2. The sense windings of a pair of coils can be anywhere on the sense line. For best results they should be close.

3. Drive lines should be in pairs when possible. Drive clamp and source lines should be grouped together well away from the sense lines. When a drive line crosses a sense line it should be at right angles.

4. Connect to spiral so to add a turn (or part of a turn) not to subtract. Try to duplicate additional turns on a spiral pair. Connect to spiral at a right angle, from a distance.

5. For a pair of spirals separated by some distance, run the common connection away from the sense line and in the drive grouping.

6. Check each pair of spirals for errors in drive or sense polarity. This can cause either an incorrect code (least digit), or a constant full output. One method to check for proper polarity is to assign current direction for both drive and sense. Then at each spiral check for proper polarity. This is illustrated in FIG. 179.

MAGNETIC CARD READING AND RECORDING UNIT

The magnetic card reading and recording unit is shown in the block diagram of FIG. 180 and in the detailed schematic diagram of FIGS. 181A-G. The manner in which it interacts with the calculator and operates to record and load secure and unsecure programs and to separately record and load data is shown and described in the block diagram of FIG. 182, the flow charts of FIGS. 60-61 and 63-65, and in the memory map of FIG. 62.

Operation of the card reader is largely automatic. It is only necessary to specify the type of operation and the limits desired. These commands are entered via the calculator keyboard. The calculator then determines the necessary commands required to cause the magnetic card reader to perform the desired operation.

Several modes of operation are possible. Programs can be recorded on magnetic cards and loaded back into the calculator. Similarly, program and data information can be recorded and loaded, or data alone. Very long programs or blocks of data can be stored on several cards. The information is loaded back into the calculator by inserting the cards into the reader in the same sequence as they were recorded. The proper linking of the information stored on the cards is automatically performed by the calculator.

Information is stored on the magnetic card in 3 bit bytes. Three tracks record the information and a fourth track provides a timing mark. Two bytes form six bit words in the calculator. The card reader automatically begins and terminates the recording, irrespective of the length of card used. Different card lengths can be mixed together without affecting the operation of the reader. Cards may be interchanged from one calculator to another.

No mechanical switches are used in the card reader. The only moving part is the card drive motor and capstan. The mechanical assembly and electronics assembly are modular and can be replaced as separate and independent units in the calculator.

OUTPUT DISPLAY UNIT

As shown in FIGS. 183 and 184A-B, the output display unit includes three 15-character rows of seven-segment light-emitting diode arrays. Each array requires an anode driver for each of its seven segments and one for the decimal point. The cathodes are common to all the diodes in one character. Respective anodes for the characters of a register are tied together to one driver. A series PNP transistor enables one of three sets of eight anode drivers each. The cathodes of a column of three characters are tied together to one of 15 cathode drivers.

The data required to operate the display is as follows:

1. Four bits to determine the column to be enabled.

2. One of three bits to determine the register.

3. Eight bits to determine the diodes of a character to be lighted.

4. A line to enable the display when the data is present.

The duty cycle is less than 1/45 requiring pulses of more current than a character could stand continuously. A retriggerable one shot is fired at every display enable pulse and will disable the column drivers after 1/2 ms. if the machine hangs up.

OUTPUT PRINTER UNIT

Several methods have been described for producing printed characters by thermal means (see particularly U.S. Pat. No. 3,161,457 issued to H. Schroeder et al.) but they typically employ a rectangular matrix of resistors to form an entire character at once. Commercial versions of this sort of printer are marketed by National Cash Register and Texas Instruments. As described in Schroeder's patent, a matrix five elements wide and seven elements high is typically employed.

The output printer unit employed in this calculator is constructed as shown in FIGS. 185, 186, 187A-B, 188, 189A-D, and 191A-B. It includes a row of print elements distributed linearly across a printing head, as shown in FIG. 188, to print a 16-character line. Each print element is an electrical resistor, of a size and shape intended to produce a dot on thermally-sensitive paper moved at right angles to the line of print elements. Dots are formed in the conventional manner by pulsing the resistor element with a pulse of electrical current, which raises its temperature by joule heating.

Each of the 16 characters of each line is formed in a 5 × 7 dot matrix. For example, as illustrated in FIG. 192 the letter A is produced by printing the darkened dots in the top row and then stepping down to the next row, etc.

Each line of print contains 16 5 × 7 matrices. The matrices are made of seven rows of 80 dots spaced in five dot groups to produce 16 characters. The printer produces each line of print by printing the top row of all 16 characters and then stepping down to print row 2 until all seven rows are printed. Three blank steps are then added to produce the space between lines.

Each of the seven rows of printing contains 80 dots (five for each of the 16 characters) which may or may not be printed. This requires that 80 information bits be supplied for each row printed. To accomplsih this, each row is split into four groups of 20 dots (four characters). (Since the I/O Register of the calculator is only 16 bits long an extra 10 bit shift register is contained in the printer hardware.) Each group of 20 bits is transmitted to the printer along with the group number by the I/O Register and is printed when the printer enable signal is given. The printer then prints that group of dots and returns a printer flag signal to the calculator. The next group of information is then supplied until all 28 groups have been printed. The three step commands are then given to provide the space between lines.

The printer requires the following information to print any group of dots:

1. Dots to be printed,

2. group number, and

3. Printer enable.

As shown and described in the flow chart of FIG. 193, this information is transmitted to the printer through the calculator I/O register. Since the total number of information bits needed is greater than the I/O registers length, two 16 bit words are transmitted to the printer. The first 16 bit word contains the dot patterns for characters 1 and 2 as shown in the following table:

CONTENT OF I/O REGISTER AFTER FIRST LOADING ##SPC224##

Character 1 is contained in bits SO2-SO0 and DO7, DO6 with the left dot in bit SO2 and the right dot in DO6. Character 2 is contained in bit CO3-CO0 and SO3 with the left dot in CO3 and the right dot in SO3. When the I/O Register is loaded with the second 16 bit word these bits will appear in the internal 10 bit shift register. The second 16 bit word contains the dot pattern for characters 3 and 4 and the group number as shown in the following table:

I/O REGISTER AFTER SECOND LOADING ##SPC225##

Character 3 is contained in bits SO2-SO0 and DO7, DO6 with the left dot in SO2 and the right dot in DO6. Character 4 is contained in bits CO3-CO0 and SO3 with the left dot in CO3 and the right dot in SO3. The group number is contained in bits DO0 and DO2. Groups are numbered as follows:

GROUP PRINTED CHARACTERS D01 D00 From Left to Right ______________________________________ 1 1, 2, 3, 4 0 0 2 5, 6, 7, 8 0 1 3 9, 10, 11, 12 1 0 4 13, 14, 15, 16 1 1 ______________________________________

When group 4 is detected the printer automatically steps to the next line. The time interval between printer enable and the return of printer flag is extended to allow the system to physically move. The printing speed is given in the following table:

Group 1 8 ms Group 2 8 ms Group 3 8 ms Group 4 18 ms Row 1 42 ms Row 2 42 ms Row 3 42 ms Row 4 42 ms Row 5 42 ms Row 6 42 ms Row 7 42 ms Space 18 ms Space 18 ms Space 18 ms Total Time to Print 1 line 348 ms Lines per second 2.87 ms

As shown in FIGS. 185-186, paper is loaded into the ooutput printer unit by lifting the wire bucket cover 220 and placing a roll of paper 222 with the free end into the paper bucket formed by the front and rear bucket halves, 224 and 226 respectively. The only care needed by the operator is to be sure that the paper uprolls forward from the bottom. The wire bucket cover performs a dual function of keeping the free end of the paper in the bucket while loading and after the paper is loaded prevents the free end from reloading itself through the mechanism.

The weight of the paper then stretches the rubber belts 228 and the roll of paper rolls forward until it rests against the paper guide 230. The paper rolls forward due to the "downhill" slope of the belt from the top of the rear idler pulley 232 to the bottom of the paper guide. With the roll of paper in the position described above the belts moving forward the free end of the paper is constrained by the belts, paper guide and roll to move below the paper guide and between it and the belts.

The belts are driven by the drive pulley 234 which is in turn driven by a gear set from the platen 236. The platen is driven by the motor 238 via a belt and gear set. The diameter and speed of the platen is such that its surface speed is approximately 5% faster than that of the belts to insure that the paper is always under tension after loading is completed. The drive and rear idler pulleys are crowned so that the belts will be self-centering. The front idler pulley 270 is flat and serves to keep the lower portion of the belt out of the bucket area.

The print head 242 is pressed against the paper and platen by means of a spring, hence it is necessary to remove the print head from the platen while loading paper. This is accomplished by the head lifter and paper deflector 244 such that when it is rotated on its axis it cams the print head off the platen and positions a small plate in the path of the paper which guides the paper up and between the platen and print head.

The paper is guided through the mechanism while loading and while the printer is working by edge guiding the paper. Ordinarily paper does not lend itself well to edge guiding due to its very low compressive strength. To overcome this the paper is bent around the convex bottom surface of the paper guide and the belt, which is under tension, is very near the edge thereby preventing the paper from buckling. The relationship of the paper, paper guide and belts can be seen by looking at Section AA of Figure 186.

When selecting materials for the various parts of the loading mechanism it is important to be sure that the coefficients of friction between the various parts are compatible. The C.F. between the paper and paper guide should be low relative to the C.F. between the paper and belts in order that the belts can drive the paper through the mechanism. Similarly, the C.F. between the paper and platen should be high relative to the C.F. between print head and paper in order that the paper can be driven through while printing. In addition, the drag introduced by the belt and paper guide due to the paper moving faster than the belt while printing must not be so great as to tear the paper or impose an impossible load on the motor.

The right half of top panel 90 of the calculator housing is hinged at the back and provided with a handle 246 at the front so that it may readily be raised by the user and stopped at an oblique upright position to expose and facilitate replenishment of the supply of thermal-sensitive paper for the output printer unit and also to serve as a music stand for holding operating or program-running instructions or any other material the user desired. A transparent plastic retainer is mounted on the underside of the hinged right half of the top panel 90 to hold such material.

POWER SUPPLY

The power supply system employed in the caluclator is constructed as shown in FIGS. 194-196 and 197A-B. As shown in FIG. 194, a centertapped transformer secondary is connected to terminals 2-3, 2-1, 2-2, and 2-4. The AC voltage from the transformer is rectified by diodes CR1 and CR2 and filtered by capacitor C1. The output of this rectifier/filter circuit is nominally 18 volts DC at 2.7 amps with a 2 volt peak to peak ripple.

Q1 and Q2 serve as a switch to connect the 5 volt output bus to the 18 volt unregulated supply through inductors L1 and L2. CR3 serves to clamp the input of L1 to ground when Q1 and Q2 are switched off. Current flow in L1 and L2 are substantially constant and equal to the load current.

Loss in high current transistor Q2 is minimized because Q2 can be completely saturated. Loss in driver transistor Q1 is minimized because Q1 can also be saturated. Resistor R7 limits the maximum drive current to Q2. Losses in R7 can be minimized by proper positioning of the tap on L1 consistent with transistor parameters and circuit requirements.

IC1 is a linear differential amplifier integrated circuit to drive Q1 and Q2. Any differential amplifier with sufficient voltage capability and bandwidth will work. Since the amplifier employed is linear, R7 and R4 have been included in the circuit to provide sufficient hysteresis for reliable switching. This hysteresis stabilizes the switching frequency and thus stabilizes the switching losses.

Because hysteresis has been added to the circuit, a significant ripple signal (at the switching frequency) must be present on the feedback signal to the amplifier. This need for a ripple signal limits the amount of capacity that can appear between the output of L1 and ground. L2 serves to isolate this point from the rest of the system. The amount of capacity that can appear between the output of L2 and ground is essentially unlimited and significantly reduces power supply ripple, and greatly improves response to load transients.

The second winding of L2 is a path for the feedback from the remote sensing. The required ripple signal is added to the feedback signal by transformer action in L2. Another possible configuration is shown in FIG. 198.

The power supply also includes an overvoltage crowbar circuit (Qr, CR4, and R9) and a short circuit shut-down circuit (using Q5). In the event that the +5 volt bus is grounded, or the crowbar is triggered, Q5 saturates and locks IC1 off.

The resistor R8 makes a current generator of IC1. Resistors R5 and R6 discharge the bases of Q1 and Q2 respectively. IC2 and its associated components generate a "power on pulse" to initialize the instrument. IC1 is referenced and powered from an external +12 volt supply. Powering the IC from +12 rather than the unregulated +18 reduces power dissipation in IC1.

The +24 volt supply of FIG. 196 is referenced by the +16 volt supply with the amplifier common returning to +12 volts to minimize power loss and voltage stress in IC1 of FIG. 196. The +12 volt supply of FIG. 197A references the +12, + 5, and +16 supplies directly. The +12 amplifier IC1 of FIG. 197A may be biased either from the unregulated supply for the +12 volt supply or from the operating +16 volt supply. Diodes CR5 and CR6 determine the appropriate source. This provides a greater power supply margin for the +12 volt supply. Similarly the +16 volt amplifier is biased from the +20 to give that supply greater margin.

All supplies except the +20 volt supply are current limited. The +24 volt supply is current limited at a value greater than the rating of its series fuse. If a short circuit occurs in the +24 volt supply, it will current limit until the fuse opens. The average current from this supply is 1.1 amps with transients to 2 amps. The current limit is set to 2.5 amps. There is not sufficient thermal capacity available to allow Q1 of FIG. 196 to carry sustained short circuit current so the fuse has been included to protect the various power supply components. All supplies except the +20 volt supply are crowbar protected against over-voltage.

TYPEWRITER INTERFACE

This interface couples the Facit-Odhner model 3841 output typewriter to the calculator.

The unit mounts directly on the back of the typewriter. Communications with the calculator are made through about 5 feet of cable which is terminated by the I/O plug containing a board for buffering and some logic.

Referring to FIGS. 199A-B and 200A-C, characters from the calculator appear on the data lines as ASCII codes. These codes are recoded by a ROM into the six bit Facit typewriter code for the 46 type bars, and one bit for upper case shift. Functions such as space, tab, line feed, etc. are recoded for easy recognition in the interface since each function must be driven by a separate line. A data latch after the ROM holds codes for processing. If new data arrives during this processing, the two codes are compared to determine if they both drive the same type bar and if they are both numbers. Non-repeating numbers can be typed at 14.5 characters per second, otherwise typing speed is 12 characters per second (reduce these speeds 17% for 50HZ operation). Codes in the latch are gated to the program solenoids or the function solenoids by the control logic.

To understand the coding, notice that two blocks of codes on the Facit typewriter code map are empty. If all function codes are put in these blocks, they can be identified by control logic by testing for (6.4). Each function code puts a 1 on one of five lines and this line opens the correct solenoid gate. Bit 8 is used to discriminate between two sets of function gates. In the case of a program solenoid code, bit 8 identifies numerals.

The control clock is provided by a sync. pulse which is generated in the typewriter by a vaned wheel attached to the end of the main drive shaft. The vanes interrupt a light beam. When a type cycle is initiated, a modulo 8 counter counts sync. pulses and the count is decoded by a 1 or 8 decoder. At each of the eight states, combinational logic can enable solenoid gates, set or clear flag flip-flops or change the counter to state zero, or state 6, or inhibit the counter.