Title:
REMOTE STATION ADDRESSING SYSTEM
United States Patent 3854122
Abstract:
A remote staton is disclosed for use in a supervisory system capable of effecting both monitoring and controlling functions. The station includes transmitter and receiver sequencers for both transmitting and receiving coded instructions and responses. Each received message is decoded by the receiver sequencer and the correct field point addressed, while the message is verified, and a response encoded and transmitted.
US Patent References:
/3045210.html
Langley - July 1962 - 3045210
INTEGRATED PARAMETER DISPLAY OF GALVANOMETER READING
Blizard - December 1970 - 3548378
CONTROL AND SUPERVISION SYSTEM HAVING DATA STORAGE
Schoenwitz - November 1971 - 3622994
/3045210.html
Langley - July 1962 - 3045210
INTEGRATED PARAMETER DISPLAY OF GALVANOMETER READING
Blizard - December 1970 - 3548378
CONTROL AND SUPERVISION SYSTEM HAVING DATA STORAGE
Schoenwitz - November 1971 - 3622994
Application Number:
05/314305
Publication Date:
12/10/1974
Filing Date:
12/12/1972
View Patent Images:
Export Citation:
Assignee:
Robertshaw Controls Company (Richmond, VA)
Primary Class:
Other Classes:
340/870.130, 340/3.540, 340/3.800, 340/870.220
International Classes:
G08C25/00; H04Q9/14; H04Q9/00
Field of Search:
340/150,151,152,408,409,222,163
Primary Examiner:
Pitts, Harold I.
Attorney, Agent or Firm:
O'brien, Anthony A.
Claims:
What is claimed is
1. A remote station for use in a supervisory system to control and monitor a plurality of remote field points in response to messages from a central station having address and verifying portions, said remote station comprising
2. A remote station according to claim 1 wherein said remote field points include analog sensors,
3. A remote station according to claim 2 wherein said control panel means immediately supplies operating signals to said analog to digital and multiplexer unit to begin analog to digital conversion upon receipt of the address portions of the messages whereby digital responses representative of conditions sensed by said analog sensors are immediately formed when said address portions are received for supply to said transmitter sequencer means when said receiver sequencer means verifies said address portions.
4. A remote station according to claim 3 wherein said remote field points include control points,
5. A remote station according to claim 4 further comprising
6. A remote station according to claim 5 wherein said remote field points include status points,
1. A remote station for use in a supervisory system to control and monitor a plurality of remote field points in response to messages from a central station having address and verifying portions, said remote station comprising
2. A remote station according to claim 1 wherein said remote field points include analog sensors,
3. A remote station according to claim 2 wherein said control panel means immediately supplies operating signals to said analog to digital and multiplexer unit to begin analog to digital conversion upon receipt of the address portions of the messages whereby digital responses representative of conditions sensed by said analog sensors are immediately formed when said address portions are received for supply to said transmitter sequencer means when said receiver sequencer means verifies said address portions.
4. A remote station according to claim 3 wherein said remote field points include control points,
5. A remote station according to claim 4 further comprising
6. A remote station according to claim 5 wherein said remote field points include status points,
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a remote station for use in supervisory systems and in particular to a station which will verify an incoming message and control a plurality of analog, status or control points.
2. Description of the Prior Art
The current trend in supervisory systems for monitoring and controlling a wide variety of things, such as commercial and industrial processes and environmental control of buildings and complexes, has been to centralize the control and provide a plurality of remote stations for carrying out the monitoring and controlling functions in order to reduce the number of personnel required as well as to achieve overall and continuous control. The functions carried out by such remote stations include temperature and humidity control, air flow, light and electrical power.
Many of the known remote stations have been capable of providing only one type of control or handling one type of point, namely status, analog or control, and have either been unable to verify the incoming message or have required extensive and expensive equipment to provide verification of the message. They have also required far greater time periods to response with analog information than with status information.
SUMMARY OF THE INVENTION
The present supervisory system remote control station is characterized by a receiver sequencer connected to receive and verify messages from a central station, a control panel connected between the receiver sequencer and a plurality of field points including analog sensors, control points and status points, an address and decode unit connected to the receiver sequencer and adapted to enable the addressed field point, and a transmitter sequencer connected to the field points and adapted to transmit a return message to the central control station of the system.
It is therefore an object of the present invention to construct a remote station for a supervisory system which station is capable of verifying the incoming message and controlling a plurality of field points which may include control, status and analog points.
It is also an object of the present invention to construct a remote station for a supervisory system in which reporting from analog points will require no more time than for control of control points or reporting from status points.
It is also an object of the present invention to construct a supervisory system remote station having up to 64 field points which may include, for example, resistance temperature detectors (RTD), pressure transducers, controller motors, and set point motors, with each field point being addressed by a separate address number and all remote points being constantly sequentially addressed so that an alarm will be received or an instruction for starting or stopping a control function transmitted within one sequence, some alarms being initially inhibited to allow start-stop conditions to stablize before indicating an alarm status.
A further object of the present invention is to construct a supervisory system remote control station provided with up to 64 field points of which a maximum of 32 of the field points may be analog and multiplexed to the input of an anlog to digital converter, but in which all 64 points may be status or control points.
The means for accomplishing the foregoing and other objects of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a timing waveform chart showing the form of the message used in the present invention;
FIG. 2 is a schematic diagram of a supervisory system remote station according to the present invention;
FIG. 3 is a schematic diagram of a control panel of the remote station according to the present invention, as shown in FIG. 2;
FIG. 4 is a schematic diagram of a synchronous divide by 5 counter according to the present invention, as shown in FIG. 3;
FIG. 5 is a schematic diagram of a synchronous divide by 4 counter according to the present invention, as shown in FIG. 3;
FIG. 6 is a schematic diagram of the analog to digital converter multiplexer according to the present invention, as shown in FIG. 2;
FIG. 7 is a schematic diagram of the start-stop control unit according to the present invention, as shown in FIG. 2; and
FIG. 8 is a schematic diagram of the address and decoder unit according to the present invention, as shown in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In any system dealing with data transmission, the selection of code and code format is very important since much of the speed and accuracy of the system depends upon the code. The present remote station is intended for use in a supervisory system utilizing a code known as a biphase Manchester code. An abbreviated message of eight bits as shown in FIG. 1 broken down as a three bit synchronization code, a three bit address, and a two bit instruction. Of course the length of the actual message transmitted would be determined by the specifications of the related system to include an adequate number of bits for a synchronization code and the address and function instruction of a double word message. This abbreviated message is also shown in binary form, as a biphase code, and in inverted form, as the negative level. Positive and negative pulses are generated by each positive and negative going transition of the binary code and the transition of the binary code and the transitions appearing in the center of each message bit are used to generate a window in which the next message bit (transition) must fall in order to generate the next successive window. Thus both timing and synchronization of the incoming message are provided.
A remote station is schematically shown in FIG. 2 having a transceiver 10 connected by a cable 12 to a central station (not shown) and connected to a transmitter sequencer 14 and a receiver sequencer 16, with the former sequencer being connected to inhibit the latter when a message is being transmitted. A remote panel control 18 is connected to both sequencers as well as to an address and decode unit 20, an analog to digital and multiplexer unit 22, a start-stop control 24, and a status unit 26. The size and number of each of these units is determined by number and type of field points connected to the remote station. The maximum number of field points contemplated as 64, of which up to 32 points can be analog. The address and decode unit 20 has inputs connected to the receiver sequencer 16 and remote panel control 18, and has outputs connected to the analog to digital and multiplexer unit 22, start-stop control 24, and status unit 26. The analog to digital and multiplexer unit 22 is connected to receive an input from analog signal condition unit 28 which has a plurality of inputs from sensors 30, and an output connected to the transmitter sequencer 14. The start-stop control 24 is connected to control relays 32 which in turn control load relays 34. A plurality of control points 36, for example motors, are connected to be controlled by the load relays 34. The status unit 26 is connected to a plurality of status points 38 and to the transmitter sequencer 14. An intercom 40 is connected to an intercom (not shown) of the central control station (also not shown) via cable 42 and to the receiver sequencer 16 and address line of the address and decoder unit 20.
The control panel 18 is shown in more detail in FIG. 3 and includes a clockpulse generator 44, which has been shown as a 10 MHz crystal oscillator. The clockpulse generator has outputs connected through NAND gate 46 to a window generator (not shown) of the receiver sequencer 16, through NAND gate 48 and inverter 50 to the clockpulse input CP of a synchronizer formed by J-K flip flop 52, through NAND gate 54 and inverter 56 to the clockpulse input CP of J-K flip flop 58 and through NAND gate 60 and inverter 62 to the input of the divide by five counter 64. The output of inverter 56 is also fed through NAND gate 66 and inverter 68 to the clockpulse input Cp of J-K flip flop 70.
A message count pulse, representing the end of the first word of a double word message, is fed from receiver sequencer 16 to terminal 72 and through inverter 74 to the J input and through inverter 76 to the K input of synchronizer flip flop 52. A reset pulse, also originating in the receiver sequencer 16, is fed to terminal 78 and through NOR gate 80 and inverter 82 to the reset inputs C D of J-K flip flops 52, and 58 and 70.
The output of synchronizer J-K flip flop 52 is connected as an input of NAND gate 48 and the Q output is connected as an input to NAND gate 54 which also receives an input from the Q output of J-K flip flop 58. NAND gate 66 receives inputs from the panel address and decode unit 20 through terminal 84 and from the receiver sequencer 16 through terminal 86 and inverter 88. The output of NAND gate 66 is connected through inverter 90 to the analog to digitial and multiplexer unit 22 by terminal 92. The output of the divide by 5 counter 64 is fed to the transmitter sequencer 14, as a 2 MHz clockpulse, through inverter 94 to a terminal 96 and to the input of the divide by 4 counter 98 and as one input to NAND gate 100. The Q A and Q B outputs of counter 98 are also fed to NAND gate 100 and the output therefrom is fed to the analog to digital and multiplex unit 22, as a 0.5 MHz clockpulse, through inverter 102 to terminal 104 and through inverter 106 to 0-9 counter 108 which has outputs connected to an analog to digital decoder (not shown). Outputs from the counter 108 are also fed to NAND gate 110 and inverter 112. The output of gate 110 is fed through inverter 114 and NAND gates 116 and 118 to enable the transmitter sequencer 14. The output of inverter 112 is connected to an input of NAND gate 120, the output of which is fed through NAND gate 122 and output terminal 124 as the control strobe to the address and decode unit 20. The output is also taken from NAND gate 110 and fed as a status strobe through NAND gate 126 to terminal 128 connected to the status unit 26.
A reset pulse from NOR gate 80 is fed through inverter 130 to 0-9 counter 108 and through inverter 132 to counters 64 and 98. The reset unit 134 also feeds a power or reset pulse through NAND gate 136 and terminal 138 to the start-stop control 24 any time power is reestablished after power loss.
The synchronous divide by five counter 64 is shown in detail in FIG. 4 and comprises three J-K flip flops 140, 142 and 144 each connected to receive a clockpulse from the output of inverter 62. The J and K inputs of flip flop 140 are connected to the Q output of flip flop 144 and the Q output of flip flop 140 is connected to the J and K inputs of flip flop 142 as well as to NAND gate 146 which receives a second input from the Q output of flip flop 142. The output of gate 146 is connected through inverter 148 to the J input of flip flop 144. The Q output of flip flop 144 is tied to its K input and also forms the counter output.
The synchronous divide by four counter 98 is shown in detail in FIG. 5 and comprises J-K flip flops 150 and 152. The J and K inputs of flip flop 150 are tied to a 1 input and the Q output is connected to the J and K inputs of flip flop 152 and as the QA input to NAND gate 100. The Q output of flip flop 152 is connected as the Q B input to NAND gate 100.
The analog to digital and multiplexer unit 22 is shown in FIG. 6 and includes four multiplexers 154, 156, 158, and 160 each having eight analog inputs, three point address inputs and an enable input. Input terminal 162 is connected through AND gate 164 to the enable input of multiplexer 154, through inverter 166 to AND gate 168 to the enable input of multiplexer 156, through NOR gates 170 and 172 to the enable input of multiplexer 158, and through NOR gate 174 to the enable input of multiplexer 160. The terminal 167 is directly connected to gates 164, 168, 172 and 174. The outputs of multiplexers 154 and 156 are connected to comparator 178 which also receives a reference input from ladder network 180. The output of the comparator 178 is fed through NAND gate 182, inverters 184, 186 and 188 to an analog to digital converter 190. The multiplexer output is taken from terminal 192 while an input is connected to terminal 194.
The start-stop control 24 is shown in FIG. 7 and includes four J-K flops 196, 198, 200 and 202 receiving clockpulse inputs from the address and decode unit 20 through AND gates 204, 206, 208, and 210, respectively. AND gates 212, 214, 216 and 218 are connected to the J inputs of the flip flops 196, 198, 200 and 202, respectively, and their K inputs are tied together to the output of AND gate 220. A control strobe from the remote panel control 18 is fed through AND gate 222 to the inputs of AND gates 204, 206, 208, and 210. The Q outputs of the J-K flip flops 196, 198, 200, and 202 are respectively connected to inverters 224, 226, 228 and 230, light emitting diodes 232, 234, 236 and 238, and the relay drivers 240, 242, 244, and 246 of the control relays 32. A power on reset pulse is fed to the J-K flip flops 196, 198, 200 and 202 from terminal 248 through inverter 150.
The address and decode unit 20 is shown in detail in FIG. 8 and simply comprises a series of registers 252 connected to output registers 254 and 256 having address line outputs each of which includes an NAND gate.
The operation of the present remote station will be described generally with reference to FIG. 2 and to a biphase Manchester code exemplary message formed by three synchronization bits and a double word body, each word having 16 bits.
The central control station (not shown) is arranged to sequentially contact each field point located at each remote station, by transmitting a message, including a synchronizing code and a single multi bit word which is repeated once, to the remote station. The message is fed from a sequencing counter (not shown) which advances counts representing the addresses of all the field points in the supervisory system. The message is sent over line 12 to transceiver 10 at the remote station. The message is fed from the transceiver to receiver sequencer 16 as positive and negative pulses and positive and negative levels. The sequencer first determines that the synchronization code is correct and then begins to examine the message body. If the address portion of the message begins with a 1 this is sent to the remote panel control 18 to inhibit the remote station since this address is reserved for the central control station as it would be the most frequently used address. If the message is addressed to the remote station, the first bit of the first word of the message is sent to panel contro 18 and the remaining 15 bits of the first word are fed to address and decode unit 20 (as a 12 bit address and three bit control, the three control bits also being fed to intercom 40). At a count of 16, the end of the first word, the remote panel control starts counters 64 and 98 in the remote panel control 18 to produce an analog to digital clockpulse which is sent to analog to digital and multiplexer unit 22 to start the analog to digital conversion. The receiver sequencer 16 compares the first 16 bit word received to the second 16 bit word, which operates as a verifying portion of the message, as it is received and, if they are not identical, sends an error signal to inhibit the remote panel control 18 so that the message received will be ignored. If the remote panel is not addressed by the incoming message, as determined by the address and decode unit 20, then no action takes place. Likewise if the incoming message is preceeded by a 1 this is the central control address and all the remote stations will ignore the message, as discussed above.
The 16 bits of the first word at the address and decode unit 20 will be decoded and, according to the address contents of the word, will enable the remote control panel 18 and the addressed point at analog to digital multiplexer unit 22, start-stop control 24 or status unit 26. However, no further action will take place at the addressed point unless the station has been addressed and the received message verified. The control bits will also be decoded to produce the inputs to the start-stop control unit for turning on or off the point addressed, usually by actuating a register or flip flop associated with that point. When the second word or verifying portion of the message is received and compared, the instruction will be carried out to obtain a readout from status points 38 or to effect the desired control at points 36, assuming that the proper panel address has been received. When there is a readout from status points 38, this readout is fed through the status unit 26 to the transmitter sequencer 14 for transmission to the central control station.
Assuming that an analog point is addressed, after receiving the first 16 bit word, the output from the addressed sensor point 30 is sent to analog to digital converter 22 and conversion is made of the analog input. After the second word has been received, the binary output from the multiplexer 22 is fed to transmitter sequencer 14 where it forms part of the message from the remote station. However, in case of an error in the incoming message, transmitter sequencer 14 is not enabled, and no message will be sent.
Assuming a correct message has been received, when the reply message is transmitted, the receiver sequencer 16 is inhibited by the transmitter sequencer 14 and the outgoing message is fed to the remote station transceiver 10 and on the cable 12.
In the case of power failure at the remote station, when power is restored all of the flip-flops at the remote station are reset to insure that no start-stop control point will be in any position but off.
Inasmuch as the present invention is subject to a variety of modifications and changes in details, it is intended that all matter contained in the foregoing description and shown in the accompanying drawings shall be considered as illustrative and not in a limiting sense.
1. Field of the Invention
The present invention relates to a remote station for use in supervisory systems and in particular to a station which will verify an incoming message and control a plurality of analog, status or control points.
2. Description of the Prior Art
The current trend in supervisory systems for monitoring and controlling a wide variety of things, such as commercial and industrial processes and environmental control of buildings and complexes, has been to centralize the control and provide a plurality of remote stations for carrying out the monitoring and controlling functions in order to reduce the number of personnel required as well as to achieve overall and continuous control. The functions carried out by such remote stations include temperature and humidity control, air flow, light and electrical power.
Many of the known remote stations have been capable of providing only one type of control or handling one type of point, namely status, analog or control, and have either been unable to verify the incoming message or have required extensive and expensive equipment to provide verification of the message. They have also required far greater time periods to response with analog information than with status information.
SUMMARY OF THE INVENTION
The present supervisory system remote control station is characterized by a receiver sequencer connected to receive and verify messages from a central station, a control panel connected between the receiver sequencer and a plurality of field points including analog sensors, control points and status points, an address and decode unit connected to the receiver sequencer and adapted to enable the addressed field point, and a transmitter sequencer connected to the field points and adapted to transmit a return message to the central control station of the system.
It is therefore an object of the present invention to construct a remote station for a supervisory system which station is capable of verifying the incoming message and controlling a plurality of field points which may include control, status and analog points.
It is also an object of the present invention to construct a remote station for a supervisory system in which reporting from analog points will require no more time than for control of control points or reporting from status points.
It is also an object of the present invention to construct a supervisory system remote station having up to 64 field points which may include, for example, resistance temperature detectors (RTD), pressure transducers, controller motors, and set point motors, with each field point being addressed by a separate address number and all remote points being constantly sequentially addressed so that an alarm will be received or an instruction for starting or stopping a control function transmitted within one sequence, some alarms being initially inhibited to allow start-stop conditions to stablize before indicating an alarm status.
A further object of the present invention is to construct a supervisory system remote control station provided with up to 64 field points of which a maximum of 32 of the field points may be analog and multiplexed to the input of an anlog to digital converter, but in which all 64 points may be status or control points.
The means for accomplishing the foregoing and other objects of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a timing waveform chart showing the form of the message used in the present invention;
FIG. 2 is a schematic diagram of a supervisory system remote station according to the present invention;
FIG. 3 is a schematic diagram of a control panel of the remote station according to the present invention, as shown in FIG. 2;
FIG. 4 is a schematic diagram of a synchronous divide by 5 counter according to the present invention, as shown in FIG. 3;
FIG. 5 is a schematic diagram of a synchronous divide by 4 counter according to the present invention, as shown in FIG. 3;
FIG. 6 is a schematic diagram of the analog to digital converter multiplexer according to the present invention, as shown in FIG. 2;
FIG. 7 is a schematic diagram of the start-stop control unit according to the present invention, as shown in FIG. 2; and
FIG. 8 is a schematic diagram of the address and decoder unit according to the present invention, as shown in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In any system dealing with data transmission, the selection of code and code format is very important since much of the speed and accuracy of the system depends upon the code. The present remote station is intended for use in a supervisory system utilizing a code known as a biphase Manchester code. An abbreviated message of eight bits as shown in FIG. 1 broken down as a three bit synchronization code, a three bit address, and a two bit instruction. Of course the length of the actual message transmitted would be determined by the specifications of the related system to include an adequate number of bits for a synchronization code and the address and function instruction of a double word message. This abbreviated message is also shown in binary form, as a biphase code, and in inverted form, as the negative level. Positive and negative pulses are generated by each positive and negative going transition of the binary code and the transition of the binary code and the transitions appearing in the center of each message bit are used to generate a window in which the next message bit (transition) must fall in order to generate the next successive window. Thus both timing and synchronization of the incoming message are provided.
A remote station is schematically shown in FIG. 2 having a transceiver 10 connected by a cable 12 to a central station (not shown) and connected to a transmitter sequencer 14 and a receiver sequencer 16, with the former sequencer being connected to inhibit the latter when a message is being transmitted. A remote panel control 18 is connected to both sequencers as well as to an address and decode unit 20, an analog to digital and multiplexer unit 22, a start-stop control 24, and a status unit 26. The size and number of each of these units is determined by number and type of field points connected to the remote station. The maximum number of field points contemplated as 64, of which up to 32 points can be analog. The address and decode unit 20 has inputs connected to the receiver sequencer 16 and remote panel control 18, and has outputs connected to the analog to digital and multiplexer unit 22, start-stop control 24, and status unit 26. The analog to digital and multiplexer unit 22 is connected to receive an input from analog signal condition unit 28 which has a plurality of inputs from sensors 30, and an output connected to the transmitter sequencer 14. The start-stop control 24 is connected to control relays 32 which in turn control load relays 34. A plurality of control points 36, for example motors, are connected to be controlled by the load relays 34. The status unit 26 is connected to a plurality of status points 38 and to the transmitter sequencer 14. An intercom 40 is connected to an intercom (not shown) of the central control station (also not shown) via cable 42 and to the receiver sequencer 16 and address line of the address and decoder unit 20.
The control panel 18 is shown in more detail in FIG. 3 and includes a clockpulse generator 44, which has been shown as a 10 MHz crystal oscillator. The clockpulse generator has outputs connected through NAND gate 46 to a window generator (not shown) of the receiver sequencer 16, through NAND gate 48 and inverter 50 to the clockpulse input CP of a synchronizer formed by J-K flip flop 52, through NAND gate 54 and inverter 56 to the clockpulse input CP of J-K flip flop 58 and through NAND gate 60 and inverter 62 to the input of the divide by five counter 64. The output of inverter 56 is also fed through NAND gate 66 and inverter 68 to the clockpulse input Cp of J-K flip flop 70.
A message count pulse, representing the end of the first word of a double word message, is fed from receiver sequencer 16 to terminal 72 and through inverter 74 to the J input and through inverter 76 to the K input of synchronizer flip flop 52. A reset pulse, also originating in the receiver sequencer 16, is fed to terminal 78 and through NOR gate 80 and inverter 82 to the reset inputs C D of J-K flip flops 52, and 58 and 70.
The output of synchronizer J-K flip flop 52 is connected as an input of NAND gate 48 and the Q output is connected as an input to NAND gate 54 which also receives an input from the Q output of J-K flip flop 58. NAND gate 66 receives inputs from the panel address and decode unit 20 through terminal 84 and from the receiver sequencer 16 through terminal 86 and inverter 88. The output of NAND gate 66 is connected through inverter 90 to the analog to digitial and multiplexer unit 22 by terminal 92. The output of the divide by 5 counter 64 is fed to the transmitter sequencer 14, as a 2 MHz clockpulse, through inverter 94 to a terminal 96 and to the input of the divide by 4 counter 98 and as one input to NAND gate 100. The Q A and Q B outputs of counter 98 are also fed to NAND gate 100 and the output therefrom is fed to the analog to digital and multiplex unit 22, as a 0.5 MHz clockpulse, through inverter 102 to terminal 104 and through inverter 106 to 0-9 counter 108 which has outputs connected to an analog to digital decoder (not shown). Outputs from the counter 108 are also fed to NAND gate 110 and inverter 112. The output of gate 110 is fed through inverter 114 and NAND gates 116 and 118 to enable the transmitter sequencer 14. The output of inverter 112 is connected to an input of NAND gate 120, the output of which is fed through NAND gate 122 and output terminal 124 as the control strobe to the address and decode unit 20. The output is also taken from NAND gate 110 and fed as a status strobe through NAND gate 126 to terminal 128 connected to the status unit 26.
A reset pulse from NOR gate 80 is fed through inverter 130 to 0-9 counter 108 and through inverter 132 to counters 64 and 98. The reset unit 134 also feeds a power or reset pulse through NAND gate 136 and terminal 138 to the start-stop control 24 any time power is reestablished after power loss.
The synchronous divide by five counter 64 is shown in detail in FIG. 4 and comprises three J-K flip flops 140, 142 and 144 each connected to receive a clockpulse from the output of inverter 62. The J and K inputs of flip flop 140 are connected to the Q output of flip flop 144 and the Q output of flip flop 140 is connected to the J and K inputs of flip flop 142 as well as to NAND gate 146 which receives a second input from the Q output of flip flop 142. The output of gate 146 is connected through inverter 148 to the J input of flip flop 144. The Q output of flip flop 144 is tied to its K input and also forms the counter output.
The synchronous divide by four counter 98 is shown in detail in FIG. 5 and comprises J-K flip flops 150 and 152. The J and K inputs of flip flop 150 are tied to a 1 input and the Q output is connected to the J and K inputs of flip flop 152 and as the QA input to NAND gate 100. The Q output of flip flop 152 is connected as the Q B input to NAND gate 100.
The analog to digital and multiplexer unit 22 is shown in FIG. 6 and includes four multiplexers 154, 156, 158, and 160 each having eight analog inputs, three point address inputs and an enable input. Input terminal 162 is connected through AND gate 164 to the enable input of multiplexer 154, through inverter 166 to AND gate 168 to the enable input of multiplexer 156, through NOR gates 170 and 172 to the enable input of multiplexer 158, and through NOR gate 174 to the enable input of multiplexer 160. The terminal 167 is directly connected to gates 164, 168, 172 and 174. The outputs of multiplexers 154 and 156 are connected to comparator 178 which also receives a reference input from ladder network 180. The output of the comparator 178 is fed through NAND gate 182, inverters 184, 186 and 188 to an analog to digital converter 190. The multiplexer output is taken from terminal 192 while an input is connected to terminal 194.
The start-stop control 24 is shown in FIG. 7 and includes four J-K flops 196, 198, 200 and 202 receiving clockpulse inputs from the address and decode unit 20 through AND gates 204, 206, 208, and 210, respectively. AND gates 212, 214, 216 and 218 are connected to the J inputs of the flip flops 196, 198, 200 and 202, respectively, and their K inputs are tied together to the output of AND gate 220. A control strobe from the remote panel control 18 is fed through AND gate 222 to the inputs of AND gates 204, 206, 208, and 210. The Q outputs of the J-K flip flops 196, 198, 200, and 202 are respectively connected to inverters 224, 226, 228 and 230, light emitting diodes 232, 234, 236 and 238, and the relay drivers 240, 242, 244, and 246 of the control relays 32. A power on reset pulse is fed to the J-K flip flops 196, 198, 200 and 202 from terminal 248 through inverter 150.
The address and decode unit 20 is shown in detail in FIG. 8 and simply comprises a series of registers 252 connected to output registers 254 and 256 having address line outputs each of which includes an NAND gate.
The operation of the present remote station will be described generally with reference to FIG. 2 and to a biphase Manchester code exemplary message formed by three synchronization bits and a double word body, each word having 16 bits.
The central control station (not shown) is arranged to sequentially contact each field point located at each remote station, by transmitting a message, including a synchronizing code and a single multi bit word which is repeated once, to the remote station. The message is fed from a sequencing counter (not shown) which advances counts representing the addresses of all the field points in the supervisory system. The message is sent over line 12 to transceiver 10 at the remote station. The message is fed from the transceiver to receiver sequencer 16 as positive and negative pulses and positive and negative levels. The sequencer first determines that the synchronization code is correct and then begins to examine the message body. If the address portion of the message begins with a 1 this is sent to the remote panel control 18 to inhibit the remote station since this address is reserved for the central control station as it would be the most frequently used address. If the message is addressed to the remote station, the first bit of the first word of the message is sent to panel contro 18 and the remaining 15 bits of the first word are fed to address and decode unit 20 (as a 12 bit address and three bit control, the three control bits also being fed to intercom 40). At a count of 16, the end of the first word, the remote panel control starts counters 64 and 98 in the remote panel control 18 to produce an analog to digital clockpulse which is sent to analog to digital and multiplexer unit 22 to start the analog to digital conversion. The receiver sequencer 16 compares the first 16 bit word received to the second 16 bit word, which operates as a verifying portion of the message, as it is received and, if they are not identical, sends an error signal to inhibit the remote panel control 18 so that the message received will be ignored. If the remote panel is not addressed by the incoming message, as determined by the address and decode unit 20, then no action takes place. Likewise if the incoming message is preceeded by a 1 this is the central control address and all the remote stations will ignore the message, as discussed above.
The 16 bits of the first word at the address and decode unit 20 will be decoded and, according to the address contents of the word, will enable the remote control panel 18 and the addressed point at analog to digital multiplexer unit 22, start-stop control 24 or status unit 26. However, no further action will take place at the addressed point unless the station has been addressed and the received message verified. The control bits will also be decoded to produce the inputs to the start-stop control unit for turning on or off the point addressed, usually by actuating a register or flip flop associated with that point. When the second word or verifying portion of the message is received and compared, the instruction will be carried out to obtain a readout from status points 38 or to effect the desired control at points 36, assuming that the proper panel address has been received. When there is a readout from status points 38, this readout is fed through the status unit 26 to the transmitter sequencer 14 for transmission to the central control station.
Assuming that an analog point is addressed, after receiving the first 16 bit word, the output from the addressed sensor point 30 is sent to analog to digital converter 22 and conversion is made of the analog input. After the second word has been received, the binary output from the multiplexer 22 is fed to transmitter sequencer 14 where it forms part of the message from the remote station. However, in case of an error in the incoming message, transmitter sequencer 14 is not enabled, and no message will be sent.
Assuming a correct message has been received, when the reply message is transmitted, the receiver sequencer 16 is inhibited by the transmitter sequencer 14 and the outgoing message is fed to the remote station transceiver 10 and on the cable 12.
In the case of power failure at the remote station, when power is restored all of the flip-flops at the remote station are reset to insure that no start-stop control point will be in any position but off.
Inasmuch as the present invention is subject to a variety of modifications and changes in details, it is intended that all matter contained in the foregoing description and shown in the accompanying drawings shall be considered as illustrative and not in a limiting sense.