Olander Jr., Emil Edward (Fort Collins, CO)
James, Rex L. (Loveland, CO)
Larson, Ivar W. (Loveland, CO)
Covington, Wayne F. (Loveland, CO)
Walden, Jack M. (Loveland, CO)
Watson, Robert E. (Loveland, CO)
Yockey, Francis J. (Loveland, CO)
Wenninger Jr., Fred (Loveland, CO)
Russell, Homer C. (Berthoud, CO)

05/212581

10/01/1974

12/27/1971

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Hewlett-Packard Company (Palo Alto, CA)

708/130

714/E11.212, 708/138, 708/136, 708/164

G06F11/36; G06F15/02; G06F7/38

235/156,159,160,164 340/172.5

3588841		June 1971	Ragen
3720820	CALCULATOR WITH A HIERARCHY CONTROL SYSTEM	March 1973	Cochran
3760171	PROGRAMMABLE CALCULATORS HAVING DISPLAY MEANS AND MULTIPLE MEMORIES	September 1973	Wang et al.

Morrison, Malcolm A.

Malzahn, David H.

Griffin, Roland I.

1. An electronic calculator comprising:

2. An electronic calculator as in claim 1 wherein said output means comprises alphameric display means for displaying each line of one or more

3. An electronic calculator as in claim 2 wherein said alphameric display means is capable of displaying every English alphabetic and Arabic numeric

4. An electronic calculator as in claim 3 wherein said output means further comprises alphameric printing means capable of printing every English alphabetic and Arabic numeric character and many other symbols individually and in messages.

BACKGROUND OF THE INVENTION

This invention relates generally to calculators and improvements therein and more particularly to programmable calculators that may be controlled both manually from the keyboard input unit and automatically by a stored program loaded into the calculator from the keyboard input unit of an external record member.

Computational problems may be solved manually, with the aid of a calculator (a dedicated computational keyboard-driven machine that may be either programmable or nonprogrammable), or a general purpose computer. Manual solution of computational problems is often very slow, so slow in many cases as to be an impractical, expensive, and ineffective use of the human resource, particularly where there are other alternatives for solution of the computational problems.

Nonprogrammable calculators may be employed to solve many relatively simple computational problems more efficiently than they could be solved by manual methods. However, the keyboard operations or language employed by these calculators is typically trivial in structure, thereby requiring many keyboard operations to solve more general arithmetic problems. Programmable calculators may be employed to solve many additional computational problems at rates hundreds of times faster than manual methods. However, the keyboard language employed by these calculators is also typically relatively simple in structure, thereby again requiring many keyboard operations to solve more general arithmetic problems.

Another basic problem with nearly all of the keyboard languages employed by conventional programmable and nonprogrammable calculators is that they allow the characteristics of the hardware of the calculator to show through to the user. Thus, the user must generally work with data movement at the hardware level, for example, by making sure that data is in certain storage registers before specifying the operations to be performed with the data and by performing other such "housekeeping" functions.

In the past both programmable and nonprogrammable calculators have generally had very limited memories thereby severely limiting the size of the computational problems they could be employed to solve. Because of these limitations, the relatively simple structure of the keyboard languages employed by these calculators and the "housekeeping" requirements associated with their languages have not heretofore been serious shortcomings. However, with advances in technology the cost of memories has decreased to a point where larger memories could be economically included in programmable calculators. These larger memories have allowed larger and larger problems to be handled by programmable calculators. As a result the shortcomings of conventional calculator languages have become more critical thereby creating the need for higher level keyboard languages.

In addition to the foregiong shortcomings, conventional programmable calculators generally have less capability and flexibility than is required to meet the needs of many users. For example, they typically cannot be readily expanded and adapted by the user to increase the amount of program and data storage memory or to perform many special keyboard functions oriented toward the environment of the user.

In some conventional programmable calculators a program stored within the calculator can be recorded onto an external magnetic record member and can later be reloaded back into the calculator from the magnetic record member. However, data and programs stored within these calculators typically cannot be separately recorded onto an external magnetic record member and later separately reloaded back into the calculator therefrom. Moreover, these calculators typically have no provision for making a program secure when it is recorded onto an external magnetic record member. Any user may therefore re-record the program or obtain an indication of the individual program steps once the program is reloaded into the calculator.

Conventional programmable calculators with self-contained output display units typically have little or no alpha capability and typically can only display the contents of one or more selected registers. They are therefore typically unable to display a line of one or more alphameric statements or an alphabetic message such as might be used, for example, to inform the user how to run programs with which he may be unfamiliar. Such features would be very helpful to the user both in editing programs and in simplifying their use.

Similarly, conventional programmable calculators with self-contained output printer units typically have a very limited alpha capability of only a few selected characters confined to certain columns of the printer. They are therefore typically unable to print out a distinct mnemonic representation of every program step of every program stored within the calculator. Furthermore, they are typically unable to print out labels for inputs to and outputs from the calculator or messages informing the user how to run programs with which he may be unfamiliar. Such features would also be very helpful to the user both in editing programs and in simplifying their use.

In order to efficiently employ a programmable calculator to solve many non-trivial computational problems, the user must be given operator instructions that, when followed, will provide a printed listing of computed results. Since conventional calculators typically do not include both a self-contained volatile output display unit and a self-contained output printer unit, each of which has an alpha capability, the operator instructions are presented either as numbers on the volatile output display unit or as alphameric messages scattered within the printed listing of computed results. The presentation of operator instructions as numbers by the volatile output display unit is undesirable because the user must then either memorize or look up the operator instructions corresponding to the numbers displayed. Similarly, the presentation of operator instructions scattered throughout the printed listing of computed results is also undesirable.

Conventional programmable calculators typically have little or no capability for editing keyboard entries or programs stored within the calculator. For example, they typically have no provision for deleting, replacing, and inserting information included in or omitted from a keyboard entry or internally-stored program on a character-by-character or line-by-line basis. As another example, they typically have no provision for directing recalling any line of an internally-stored program of one or more lines of alphameric statements. Such features would be very heloful to the user in editing programs.

Conventional computers typically have or may be programmed to have much more capability than conventional programmable calculators. For many computational problems the computer provides little or no economical improvement over manual methods of solution because of the difficulty of the interfacing problem between the user and the machine. This interfacing problem appears as a slow turn around time in batch processing or in a long learning period for the user due to the general-purpose nature of the computer. A skilled programmer is typically required to utilize a computer. Due to these factors, conventional computers are best suited for handling large amounts of data or solving highly iterative or very complex computational problems.

SUMMARY OF THE INVENTION

The principal object of this invention is to provide an improved programmable calculator that has more capability and flexibility than conventional programmable calculators, that is smaller, less expensive and more efficient in calculating elementary mathematical functions than conventional computer systems, and that is easier to utilize than conventional programmable calculators or computer systems.

Another object of this invention is to provide a programmable calculator employing a directly usable high-level keyboard language that completely eliminates most of the operator "housekeeping" requirements typically associated with the languages of conventional programmable calculators and computers.

Another object of this invention is to provide a programmable calculator in which the amount of program and data storage memory available to the user may be expended and in which additional program and data storage memory made available to the user is automatically accommodated by the calculator and the user informed when the capacity of the program and data storage memory has been exceeded.

Another object of this invention is to provide a programmable calculator in which the functions performed by the calculator may be readily expanded by the user and oriented toward the environment of the user and in which the added functions are automatically accommodated by the calculator.

Another object of this invention is to provide a programmable calculator in which the user may define and store within the calculator additional keyboard functions to be performed by the calculator, may associate each such defined keyboard function with a separate definable key of a keyboard input unit, and may cause each such defined keyboard function to be executed and/or stored as part of a program, either by itself or as part of an arithmetic expression, by depressing an execute key or a store key, respectively of the keyboard input unit following depression of the associated definable key and one or more other keys required to enter the parameters of the defined keyboard function into the calculator.

Another object of this invention is to provide a programmable calculator in which the user may define and store within the calculator subroutines to be performed by the calculator, may associate each such defined subroutine with a calling sequence that may or may not include a separate associated definable key of a keyboard input unit and that may or may not include parameters for the defined subroutine, may cause each such calling sequence to be executed and/or stored as part of a program by depressing an execute key or a store key, respectively, of the keyboard input unit immediately following the calling sequence, and may cause each such defined subroutine associated with a calling sequence to be executed by executing the associated calling sequence.

Another object of this invention is to provide a programmable calculator in which the user may define and store within the calculator subroutines to be performed by the calculator, may associate each such defined subroutine that does not have parameters with a separate definable key of a keyboard input unit, and may cause each such parameterless defined subroutine associated with a definable key to be executed immediately upon depression of the associated definable key.

Another object of this invention is to provide a programmable calculator in which each subrouting defined, stored within the calculator, and associated with a separate definable key of a keyboard input unit by the user is given a sequence of line numbers independent of the line numbers of any other function, subroutine, or program that may also be stored within the calculator.

Another object of this invention is to provide a programmable calculator in which each subroutine and additional keyboard function defined, stored within the calculator, and associated with a separate definable key of a keyboard input unit by the user is automatically protected from being inadvertently altered or destroyed by the user.

Another object of this invention is to provide a programmable calculator in which the parameters specified for keyboard functions and for subroutines and additional keyboard functions defined by the user and stored within the calculator may include input data comprising numerics, register designations, and arithmetic expressions and may also include output register designations.

Another object of this invention is to provide a programmable calculator in which subroutines defined, stored within the calculator, and associated with a separate definable key of a keyboard input unit by the user may include both local and global variables.

Another object of this invention is to provide a programmable calculator in which data storage registers may be addressed directly by the computed integral value of an arithmetic expression that may in turn incorporate the contents of one or more similarly addressed data storage registers and in which this capability may be used both to fetch and store information and to permit efficient manipulation of files and matrix operations.

Another object of this invention is to provide a programmable calculator in which the user may designate any program stored within the calculator as being secure when it is recorded onto an external magnetic record member for subsequent re-entry into the calculator, in which the user is prevented from re-recording any secure program or obtaining any indication of its individual program steps once it is reloaded into the calculator, and in which a magnetic record member including a secure program may also include nonsecure data.

Another object of this invention is to provide a programmable calculator capable of printing out every alphabetic and numeric character and many other symbols individually and in messages.

Another object of this invention is to provide a programmable calculator capable of providing an alphameric display of every alphabetic and numeric character and many other symbols individually and in messages.

Another object of this invention is to provide a programmable calculator in which questions may be asked and operator instructions or other messages given by an alphameric display and the answers or output data printed with labels and without the questions, operator instructions, or messages by an alphameric printer.

Another object of this invention is to provide a programmable calculator capable of printing out a numeric representation of each numeric keyboard entry and calculated numeric result and distinguishing each printed-out numeric keyboard entry from each printed-out calculated numeric result.

Another object of this invention is to provide a programmable calculator in which programs stored within the calculator may be edited more efficiently than in conventional programmable calculators.

Another object of this invention is to provide a programmable calculator in which the user may enter a line of one or more alphameric statements into the calculator from a keyboard, may visually observe an alphameric display of part or all of the line both while it is being entered and after it has been entered to check for errors therein, and upon determining that the entered line is error free may selectively cause it to be immediately executed by the calculator and/or stored as a program or a portion of a program within the calculator.

Another object of this invention is to provide a programmable calculator in which the user may selectively and nondestructively recall any line or one or more alphameric statements stored as a program or a portion of a program within the calculator and may visually observe an alphameric display of any part or all of the recalled line to check for errors therein.

Another object of this invention is to provide a programmable calculator in which the user may selectively and nondestructively recall any line of one or more alphameric statements stored within a program memory of the calculator, may visually observe an alphameric display or any part or all of the recalled line to check for errors therein, may edit the recalled line without altering the program stored within the program memory, and may thereafter store the edited recalled line in the program memory in place of the corresponding unedited line stored therein.

Another object of this invention is to provide a programmable calculator in which the user may employ a forward key and a back key of a keyboard to single step either forward or backward through a line of one or more alphameric statements entered into the calculator from the keyboard or recalled from a program stored within the calculator and may visually observe an alphameric display of part or all of the entered or recalled line up to and including as the last character of the display the last character to which the calculator has been single stepped.

Another object of this invention is to provide a programmable calculator in which the user may employ a forward key and a back key of a keyboard to single step either forward or backward through a line of one or more alphameric statements recalled from a program stored within the calculator and upon reaching either the back or the front end of the recalled line to automatically recall the next succeeding or preceeding line, respectively, of the program.

Another object of this invention is to provide a programmable calculator in which the user may visually observe any part or all of a line of one or more alphameric characters entered into the calculator from a keyboard or recalled from a program stored within the calculator and may either selectively delete or replace incorrect or undesired portions of the observed line or selectively insert corrected or previously omitted portions of the observed line from the keyboard on a character-by-character or line-by-line basis.

Another object of this invention is to provide a programmable calculator in which upon detection of a syntactical error in a line of one or more alphameric statements being entered into the calculator depression of any key that is not useful in determining, removing, or correcting the error is prevented from having any effect upon the calculator and execution of any line being executed by the calculator is arrested and prevented from continuing until the error is removed or corrected.

Another object of this invention is to provide a programmable calculator in which syntactical errors in a line of one or more alphameric statements being entered into the calculator from a keyboard are automatically detected and immediately indicated to the user as they occur.

Another object of this invention is to provide a programmable calculator in which semantical errors in any line of one or more alphameric statements entered into the calculator from a keyboard or stored within the calculator as part of a program are automatically detected when the entered or stored line is being executed and in which each such error is indicated to the user and, in the case of an error occurring in a line stored as part of a program, the number of the line in the program at which the error occurs is also indicated to the user.

Another object of this invention is to provide a programmable calculator in which syntactical and semantical errors are indicated by alphameric messages and may be determined with the aid of an error table listing each such alphameric message and the possible errors that may have produced that alphameric message.

Another object of this invention is to provide a programmable calculator in which upon detection of a syntactical error in a line of one or more alphameric statements being entered from a keyboard the user may depress a forward key of the keyboard to single step the calculator to the erroneous keyboard entry and to obtain an alphameric display of all or part of the line being entered up to and including the erroneous keyboard entry.

Another object of this invention is to provide a programmable calculator in which upon detection of a syntactical error in a line of alphameric statements being entered from a keyboard the user may depress a back key of the keyboard to single step the calculator to the keyboard entry immediately preceding the erroneous keyboard entry and to obtain an alphameric display of all or part of the line being entered up to but not including the erroneous keyboard entry.

Another object of this invention is to provide a programmable calculator in which upon detection of a semantical error in a line of one or more alphameric statements being executed by the calculator the user may depress a recall key of a keyboard to obtain an alphameric display of all or part of the line in which the error occurred.

Another object of this invention is to provide a programmable calculator in which the user may sequentially depress a recall key of a keyboard to step line-by-line through a plurality of lines of alphameric statements stored as a program or a portion of a program within the calculator and to obtain an alphameric display of all or part of each line while it is recalled.

Another object of this invention is to provide a programmable calculator in which the user may include a trace command in a program of one or more lines of alphameric statements stored in a program memory of the calculator or may enter the trace command from a keyboard at any time before or during the execution of the program to obtain an alphameric print-out of the number of each line executed by the calculator, the value of each numerical assignment made therein, and each print command included therein and in which the user may include a normal command in the program at any point following the trace command or may enter the normal command from the keyboard at any time following a trace command to terminate the trace command.

Another object of this invention is to provide a programmable calculator in which the user may execute a trace command to obtain an alphameric keylog listing of each line of one or more alphameric statements as that line is being executed by the calculator or stored as part of a program within the calculator and, in the case of a line being stored as part of a program within the calculator, also the number of that line.

Another object of this invention is to provide a programmable calculator in which the user may obtain an alphameric program listing of the number and content of each line of one or more alphameric statements stored as part of any program, defined function, or subroutine within a program memory of the calculator.

Another object of this invention is to provide a programmable calculator in which the user may obtain directly or as part of any program listing an alphameric print out of the number of nondedicated data storage registers currently remaining available to the user.

Another object of this invention is to provide a programmable calculator in which every printed program listing is automatically spaced above a paper cutter.

Another object of this invention is to provide a programmable calculator having a DISPLAY key which permits the user to manually or programmably display the results of an arithmetic expression, an alphameric message, or the contents of any data register either singly or as a string and without altering any data register.

Another object of this invention is to provide a programmable calculator having a DISPLAY key which can be used as a programmable pause key by displaying the results of an arithmetic expression, an alphameric message, the contents of any data register, or any combination thereof momentarily without altering any data register.

Another object of this invention is to provide a programmable calculator in which either alpha or numeric information may be displayed without altering any data register.

Another object of this invention is to provide a programmable calculator having FIXED N and FLOAT N keys which allow the user to manually or programmably designate fixed point or floating point notation for displayed data, N being a parameter indicating the number of display digits to the right of the decimal point.

Another object of this invention is to provide a programmable calculator in which the user may change a programmed data display notation designation during program execution from fixed point to floating point or vice versa by depressing a single key.

Another object of this invention is to provide a programmable calculator which, through the use of a single program statement, stops execution of the program and allows the user to enter one or more pieces of data, after which the data is automatically stored in a register or registers specified in the program statement.

Another object of this invention is to provide a programmable calculator which, upon stopping for the entry of data, can display either a register designator or an alphameric message associated therewith.

Another object of this invention is to provide a programmable calculator which, upon stopping program execution for the entry of data, sets a flag if the user calls for continuation of the program without entering data, thus permitting termination of the entry of successive pieces of data, the exact number of which is unknown at the time of writing the program.

Another object of this invention is to provide a programmable calculator in which the execution sequence of a stored program may include unconditional branching to absolute, symbolically labeled, relative, and computed relative lines of the stored program.

Another object of this invention is to provide a programmable calculator in which the execution sequence of a stored program may include subroutine calls to absolute, symbolically labeled, and relative lines of the stored program.

Another object of this invention is to provide a programmable calculator in which, at the user's option, the execution of a stored program involving any unconditional branching except computed relative branching may be accelerated over the normal program execution rate.

Another object of this invention is to provide a programmable calculator in which the execution of an unconditional uncomputed branch statement in a program does not occur until other statements contained on the same line have been executed, thereby facilitating multiple conditional branching.

Another object of this invention is to provide a programmable calculator in which a multiplicity of flags are available to the user as boolean variables in constructing any program statement.

Another object of this invention is to provide a programmable calculator in which, upon encountering a mathematically illegal expression or an arithmetic overflow or underflow condition during execution of a program, a flag is set, an error message appears in the display, and program execution is halted, and in which, in the above situation, the user may suppress the error message and program halt by presetting another flag.

Another object of this invention is to provide a programmable calculator in which a flag is provided for use as a boolean variable in constructing program statements and which may be set manually during program execution by depressing a single key.

Another object of this invention is to provide a programmable calculator in which a magnetic card reading and recording unit is provided for transferring programs, data or a combination thereof between the calculator and an external magentic card.

Another object of this invention is to provide a programmable calculator in which LOAD and RECORD keys for controlling a magnetic card reading and recording unit are programmable.

Another object of this invention is to provide a programmable calculator in which programs transferred therefrom to an external magnetic card contain an indication of the plug-in ROM module configuration of the calculator and in which an error message is displayed if the user attempts to read a card which was previously recorded from a calculator having an incompatible plug-in ROM module configuration.

Another object of this invention is to provide a programmable calculator in which a display message asking for additional magnetic cards is automatically provided in the instance wherein a particularly large program or data block to be transferred between magnetic cards and the calculator requires more than one card.

Another object of this invention is to provide a programmable calculator in which the programmable relational operators =, ≠, ≤, and > are available to the user for inclusion in any statement to the calculator for the purpose of providing a boolean test of the relationship of any two numeric constants, register contents, or arithmetic expression results.

Another object of this invention is to provide a programmable calculator in which a plurality of dedicated data registers having fixed labels and memory locations may by single keystrokes be called into a displayed algebraic expression and whose contents are manipulated and the result displayed according to the algebraic expression and in response to depression of an EXECUTE key.

Another object of this invention is to provide a programmable calculator in which the mnemonics associated with various sequential key actuations appear in a multicharacter alphameric display and in which the displayed mnemonics automatically scroll to the left and off the display as additional keys are depressed after the display becomes full.

Another object of this invention is to provide a programmable calculator in which a displayed string of mnemonic characters may be scrolled left or right one character with each actuation of one of two keys.

Another object of this invention is to provide a programmable calculator in which the special characters "space" and " " are used to indicate the beginning and end, respectively, of a stored program line when displayed.

Another object of this invention is to provide a programmable calculator whose display may be cleared independently of any data and/or program storage registers.

Another object of this invention is to provide a programmable calculator in which a display unit is included for displaying the mnemonics of keys as they are depressed and for displaying numeric or alphameric results of keyboard or program calculations.

Another object of this invention is to provide a programmable calculator in which the alpha character "E" is used to designate exponent digits when displaying numbers in floating point notation.

Another object of this invention is to provide a programmable calculator in which all memory, including basic read-only memory, plug-in read-only memory modules, system and user read-write memory, and optional read-write memory is addressed through a common address register technique, thereby allowing either read-write memory or read-only memory to be used interchangeably for read-only memory, and further allowing microprocessor language instructions to be loaded into the user read-write memory as an ordinary sub-routine for accessing by a keyboard-compiled program.

Another object of this invention is to provide a programmable calculator having a magnetic card reading and recording unit for loading any keyboard-compiled program or any microprocessor language program into the user section of the calculator read-write memory.

Another object of this invention is to provide a programmable calculator in which no new instructions are required for accessing any expansion of read-write memory.

Another object of this invention is to provide a programmable calculator in which a programmable SPACE N key is provided for spacing the paper on the internal printer N spaces, N being a parameter.

Another object of this invention is to provide a programmable calculator in which selected keyboard keys may perform dual functions by either depressing the key one time or two times.

Another object of this invention is to provide a programmable calculator in which user registers and programs are protected from each other even though they may interchangeably use the same area.

Another object of this invention is to provide a programmable calculator in which the input/output structure allows external peripheral units to interrupt the calculator central processing unit.

Another object of this invention is to provide a programmable calculator in which the input/output structure allows external memory devices to communicate directly with the internal memory without involving the central processing unit.

Another object of this invention is to provide a programmable calculator in which an error message is displayed if the user attempts to print information on the output printer unit if its paper supply has been exhausted.

Another object of this invention is to provide a programmable calculator in which, after programmably loading a program from an external magnetic card, execution resumes automatically from either line zero or from the first line of the program just loaded.

Another object of this invention is to provide a programmable calculator in which a MINUS key performs either subtraction or unary minus, as the context of the statement requires.

Another object of this invention is to provide a programmable calculator having implied multiply capability, that is, multiplication without the use of the multiplicative operator.

Another object of this invention is to provide a programmable calculator in which a priority of operation exists as each algebraic statement line is executed, the priority being from highest to lowest as follows: functions, exponentiation, implied multiply, unary minus, multiply and divide, add and subtract, and the relational operations <, ≥, =, ≠.

Another object of this invention is to provide a programmable calculator in which an assignment operator may be used any number of times in one statement to store intermediate results.

Another object of this invention is to provide a programmable calculator in which arguments of keyboard functions, including those relating to a plug-in ROM module, may be numeric constants, registers or arithmetic expressions.

Another object of this invention is to provide a programmable calculator in which a keyboard function provides for raising the number ten to any power.

Another object of this invention is to provide a programmable calculator in which functions related to a user definable functions plug-in ROM module may be assigned their own mnemonics by the user, and, in addition, they may be assigned to any keys not being used by other plug-in ROM modules.

Other and incidental objects of this invention will become apparent from a reading of this specification and an inspection of the accompanying drawings.

These objects are accomplished according to the illustrated preferred embodiment of this invention by employing a keyboard input unit, a magnetic card reading and recording unit, a solid state output display unit, an output printer unit, an input-output control unit, a memory unit, and a central processing unit to provide an adaptable programmable calculator having manual operating, automatic operating, program entering, magnetic card reading, magnetic card recording, and alphameric printing modes. The keyboard input unit includes a group of data keys for entering numeric data into the calculator, a group of control keys for controlling the various modes and operations of the calculator and the format of the output display, and a group of definable keys for controlling additional functions that may be added by the user. All of the data keys and nearly all of the control keys may also be employed for programming the calculator, many of the control keys being provided solely for this purpose.

The magnetic card reading and recording unit includes a reading and recording head, a drive mechanism for driving a magnetic card from an input receptacle in the front panel of the calculator housing past the reading and recording head to an output receptacle in the front panel, and reading and recording drive circuits coupled to the reading and recording head for bidirectionally transferring information between the magnetic card and the calculator as determined by the control keys of the keyboard input unit. It also includes a pair of detectors and an associated control circuit for disabling the recording drive circuit whenever a notch is detected in the leading edge of the magnetic card to prevent information recorded on the magnetic card from being inadvertently destroyed. Such a notch may be provided in any magnetic card the user desires to protect by simply pushing out a perforated portion thereof.

The output printer unit includes a stationary thermal printing head with a row of resistive heating elements, a drive circuit for selectively energizing each heating element, and a stepping mechanism for driving a strip of thermally sensitive recording paper past the stationary thermal printing head in seven steps for each line of alphameric information to be printed out. Every alphabetic and numeric character and many other symbols may be printed out individually or in messages as determined by the control keys of the keyboard input unit or by a program stored within the calculator.

The input-output control unit includes a sixteen-bit universal shift register serving as an input-output register into which information may be transferred serially from the central processing unit or in parallel from the keyboard input and magnetic card reading and recording units and from which information may be transferred serially to the central processing unit or in parallel to the solid state output display, magnetic card reading and recording, and output printer units. It also includes control logic responsive to the central processing unit for controlling the transfer of information between these units. The input-output control unit may also be employed to perform the same functions between the central processing unit and peripheral units including, for example, a digitizer, a marked card reader, an X-Y plotter, a magnetic tape unit, a disc, and a typewriter. A plurality of peripheral units may be connected at the same time to the input-output control unit by simply plugging interface modules associated with the selected peripheral units into receptacles provided therefore in a rear panel of the calculator housing.

The memory unit includes a modular random-access read-write memory having a dedicated system area and a separate user area for storing program steps and/or data. The user portion of the read-write memory may be expanded without increasing the overall dimensions of the calculator by the addition of a program storage module. Additional read-write memory made available to the user is automatically accommodated by the calculator, and the user is automatically informed when the storage capacity of the read-write memory has been exceeded.

The memory unit also includes a modular read-only memory in which routines and subroutines of basic instructions for performing the various functions of the calculator are stored. These routines and subroutines of the read-only memory may be expanded and adapted by the user to perform additional functions oriented toward the specific needs of the user. This is accomplished by simply plugging additional read-only memory modules into receptacles provided therefor in the top panel of the calculator housing. Added read-only memory modules are automatically accommodated by the calculator and may be associated with the definable keys of the keyboard input unit or employed to expand the operations associated with other keys. An overlay is employed with each added read-only memory module associated with the definable keys of the keyboard input unit to identify the additional functions that may then be performed by the calculator.

Plug-in read-only memory modules include, for example, a trigonometric module, a peripheral control module, and a definable functions module. The trigonometric module enables the calculator to perform trigonometric functions, logarithmic functions, and many other mathematical functions. The definable functions module enables the user to store subprograms of his own choosing in the program storage section of the read-write memory, associate them with some of the definable keys of the keyboard input unit, and protect them from subsequently being inadvertently altered or destroyed. These subprograms may have their own line numbering sequence and may be any of three types: an immediate execute type wherein the subprogram may be run upon depressing a DEFINE key; a subroutine utilizing parameters; a function having parameters that may be employed as any other keyboard function.

The memory unit further includes a pair of recirculating sixteen-bit serial shift registers. One of these registers serves as a memory address register for serially receiving information from an arithmetic-logic unit included in the central processing unit, for parallel addressing any memory location designated by the received information, and for serially transferring the received information back to the arithmetic-logic unit. The other of these registers serves as a memory access register for serially receiving information from the arithmetic-logic unit, for writing information in parallel into any addressed memory location, for reading information in parallel from any addressed memory location, and for serially transferring information to the arithmetic logic unit. It also serves as a four-bit parallel shift register for transferring four bits of binary-coded-decimal information in parallel to the arithmetic-logic unit.

The central processing unit includes four recirculating sixteen-bit serial shift registers, a four-bit serial shift register, the arithmetic logic unit, a programmable clock, and a microprocessor. Two of these sixteen-bit serial shift registers serve as accumulator registers for serially receiving information from and serially transferring information to the arithmetic logic unit. The accumulator register employed is designated by a control flip-flop. One of the accumulator registers also serves as a four-bit parallel shift register for receiving four bits of binary-coded-decimal information in parallel from and transferring four bits of such information in parallel to the arithmetic logic unit. The two remaining sixteen-bit serial shift registers serve as a program counter register and a qualifier register, respectively. They are also employed for serially receiving information from and serially transferring information to the arithmetic-logic unit. The four-bit serial shift register serves as an extend register for serially receiving information from either the memory access register or the arithmetic-logic unit and for serially transferring information to the arithmetic-logic unit.

The arithmetic-logic unit is employed for performing one-bit serial binary arithmetic, four-bit parallel binary-coded-decimal arithmetic, and logic operations. It may also be controlled by the microprocessor to perform bidirectional direct and indirect arithmetic between any of a plurality of the working registers and any of the storage registers of the data storage section of the read-write memory.

The programmable clock is employed to supply a variable number of shift clock pulses to the arithmetic logic unit and to the serial shift registers of the input-output, memory, and central processing units. It is also employed to supply clock control signals to the input-output control logic and to the microprocessor.

The microprocessor includes a read-only memory in which a plurality of microinstructions and codes are stored. These microinstructions and codes are employed to perform the basic instructions of the calculator. They include a plurality of coded and non-coded microinstructions for transferring control to the input-output control logic, for controlling the addressing and accessing of the memory unit, for controlling the operation of the two accumulator registers, the program counter register, the extend register and the arithmetic logic unit. They also include a plurality of clock codes for controlling the operation of the programmable clock, a plurality of qualifier selection codes for selecting qualifiers and serving as primary address codes for addressing the read-only memory of the microprocessor, and a plurality of secondary address codes for addressing the read-only memory of the microprocessor. In response to a control signal from a power supply provided for the calcultor, control signals for the programmable clock, and qualifier control signals from the central processing and input-output control units, the microprocessor issues the microinstructions and codes stored in the read-only memory of the microprocessor as required to process either binary or binary-coded-decimal information entered into or stored in the calculator.

In the keyboard mode, the calculator is controlled by keycodes sequentially entered into the calculator from the keyboard input unit by the user. The solid state output display unit displays either the mnemonic representation of the keys as they are depressed or a numeric representation of output data or alphameric user instructions or program results. The output printer unit may be controlled by the user to selectively print out a numeric representation of any numeric data entered into the calculator from the keyboard input unit, a numeric represenation of any result calculated by the calculator, or a program listing on a line-by-line basis of the mnemonic representation of the keys entered. The output printer unit may also be controlled by the user to print out labels for inputs to and outputs from the calculator and any other alphameric information that may be desired.

When the calculator is in the keyboard mode, it may also be operated in a trace alphameric printing mode. The output printer unit then prints out a mnemonic representation of each program line as it is entered by the user.

In the program running mode, the calculator is controlled by automatically obtaining compiled keycodes stored as steps of a program in the user storage section of the read-write memory. During automatic operation of the calculator, data may be obtained from the memory unit as designated by the program or may be entered from the keyboard input unit by the user while the operation of the calculator is stopped for data either by the program or by the user.

When the calculator is in the program running mode, the user may also employ a TRACE key to check the execution of the program line by line in order to determine whether the program, as entered into the calculator, does in fact carry out the desired sequence of operations.

In the program entering mode, keycodes are sequentially entered by the user into the calculator from the keyboard input unit and are compiled into Polish notation and stored as steps of a program in the user storage section of the read-write memory.

In the magnetic card reading mode, the magnetic card reading and recording unit may be employed by the user to separately load either data or programs into the calculator from one or more external magnetic cards.

In the magnetic card recording mode, the magnetic card reading and recording unit may be employed by the user to separately record either data or programs stored in the user section of the read-write memory onto one or more external magnetic cards. Programs may be coded by the user as being secure when they are recorded onto one or more external magnetic cards. The calculator detects such programs when they are reloaded into the calculator and prevents the user from re-recording them or obtaining any listing or other indication of the individual program steps.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a front perspective view of an adaptable programmable calculator according to the preferred embodiment of this invention.

FIG. 2 is a rear perspective view of the adaptable programmable calculator of FIG. 1.

FIGS. 3A-B are a simplified block diagram of the adaptable programmable calculator of FIGS. 1 and 2.

FIGS. 4A-B are a memory map of the memory unit employed in the adaptable programmable calculator of FIGS. 1-3B.

FIG. 4' is a diagram showing the arrangement of FIGS. 4A-B.

FIG. 5 is a detailed memory map of the dedicated portion of the data storage section of the read-write memory employed in the memory unit of FIGS. 3A-B and 4A-B.

FIG. 6 is a simplified operational logic flow chart illustrating the operation of the microprocessor employed in the central processing unit of FIGS. 3A-B.

FIG. 7 is a plan view of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1-3B showing how the keyboard input unit may be redefined by an alpha, plug-in, read-only memory module that may also be employed in the adaptable programmable calculator.

FIGS. 8A-C are perspective views of the trigonometric, plug-in, read-only memory module that may be employed in the adaptable programmable calculator, of FIGS. 1-3B and a plan view of the keyboard overlay associated therewith.

FIGS. 9A-C are perspective views of the peripheral-control, plug-in, read-only memory module that may be employed in the adaptable programmable calculator of FIGS. 1-3B and a plan view of the keyboard overlay associated therewith.

FIGS. 10A-E are perspective views of the user-definable-functions, plug-in, read-only memory module that may be employed in the adaptable programmable calculator of FIGS. 1-3B and plan views of the keyboard overlays associated therewith.

FIG. 11 is a plan view of the keyboard employed in the adaptable programmable calculator of FIGS. 1-3B showing the key definitions relating to a format or write statement when using the adaptable programmable calculator in conjunction with a Facit typewriter peripheral unit.

FIG. 12 is another plan view of the keyboard employed in the adaptable programmable calculator of FIGS. 1-3B showing the key definitions relating to a format or write statement when using the adaptable programmable calculator in conjunction with a teletype peripheral unit.

FIGS. 13A-B are an operational firmware block diagram for the adaptable programmable calculator of FIGS. 1-3B.

FIG. 13' is a diagram showing the arrangement of FIGS. 13A-B.

FIGS. 14A-C are a simplified flow chart of the overall control sequence employed for keycode processing in the adaptable programmable calculator of FIGS. 1-3B.

FIG. 14' is a diagram showing the arrangement of FIGS. 14A-C.

FIGS. 15A-C are flow charts of the floating point add and subtract key processing routines selectable by the interpreter routines of FIGS. 13A-B.

FIG. 16 is a flow chart of the floating point multiply key processing routine selectable by the interpreter routines of FIGS. 13A-B.

FIGS. 17A-B are flow charts of the floating point division key processing routine selectable by the interpreter routines of FIGS. 13A-B.

FIGS. 18A-C are flow charts of the floating point square root key processing routine selectable by the interpreter routines of FIGS. 13A-B.

FIG. 19 is a flow chart of the store routine selectable by the interpreter routines of FIGS. 13A-B.

FIG. 20 is a flow chart of the rounding routine employed in connection with several of the routines selectable by the interpreter routines of FIGS. 13A-B.

FIGS. 21A-B are flow charts of a tangent X routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIGS. 22A-B are flow charts of an arctangent x routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIGS. 23A-B are flow charts of an e ^x routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIG. 24 is a flow chart of a natural logarithm x routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIG. 25 is a flow chart of a subroutine employed by the tangent x and the e ^x routines of FIGS. 21A-B and 23A-B, respectively.

FIGS. 26A-B are flow charts of a subroutine employed by the tangent x and arctangent x routines of FIGS. 21A-B and 22A-B, respectively.

FIGS. 27A-B are flow charts of a subroutine employed by the e ^x and natural logarithm x routines of FIGS. 23A-B and 24, respectively.

FIG. 28 is a flow chart of a subroutine employed by the arctangent x and natural logarithm x routines of FIGS. 22A-B and 24, respectively.

FIG. 29 is a flow chart of sine and cosine routines that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIG. 30 is a flow chart of an arcsine routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIG. 31 is a flow chart of an arccosine routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIG. 32 is a flow chart of an x to the y power routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIG. 33 is a flow chart of a logarithm to the base ten routine that may be performed when the trigonometric, read-only memory module is plugged into the adaptable programmable calculator of FIGS. 1-3B.

FIG. 34 is a block diagram of the microprocessor of FIGS. 3A-B.

FIGS. 35A-D are a detailed schematic diagram of the microprocessor of FIGS. 3A-B and 34.

FIG. 35' is a diagram showing the arrangement of FIGS. 35A-D.

FIGS. 36A-H are detailed flow charts illustrating the operation of the microprocessor of FIGS. 3A-B, 34, and 35A-D.

FIGS. 36' and 36" are diagrams showing the arrangement of FIGS. 36A-H.

FIG. 37 is a block diagram of the programmable clock of FIGS. 3A-B.

FIGS. 38A-C are a detailed schematic diagram of the programmable clock of FIGS. 3A-B and 37 and of a control section of the input-output control unit of FIGS. 3A-B.

FIG. 38' is a diagram showing the arrangement of FIGS. 38A-C.

FIG. 39 is a waveform diagram illustrating the operation of the programmable clock of FIGS. 3A-B, 37, and 38A-C.

FIGS. 40A-D are a detailed schematic diagram of the shift register and arithmetic logic units of FIGS. 3A-B.

FIG. 40' is a diagram showing the arrangement of FIGS. 40A-D.

FIG. 41 is a block diagram of the arithmetic logic unit of FIGS. 3A-B.

FIG. 42 is a block diagram of the memory unit of FIGS. 3A-B.

FIGS. 43A-B are a schematic diagram of the read-write memory of FIGS. 3A-B, 4A-B, and 42.

FIG. 43' is a diagram showing the arrangement of FIGS. 43A-B.

FIGS. 44A-B are a schematic diagram of the optional add-on read-write memory of FIGS. 3A-B, 4A-B, and 42.

FIG. 44' is a diagram showing the arrangement of FIGS. 44A-B.

FIGS. 45A-B are a schematic diagram of the read-only memory of FIGS. 3A-B, 4A-B, and 42.

FIG. 45' is a diagram showing the arrangement of FIGS. 45A-B.

FIG. 46 is a schematic diagram of the optional, add-on, read-only memory modules of FIGS. 1, 4A-B, and 42 that may be plugged into the calculator to increase the number of functions available to the user.

FIG. 47 is a block diagram of one of the read-only memory chips of FIGS. 45A-B and 46.

FIGS. 48A-D are a schematic diagram of one of the read-only memory chips of FIGS. 45A-B and 46.

FIG. 48' is a diagram showing the arrangement of FIGS. 48A-D.

FIG. 49 is a memory map of the memory unit of FIGS. 3A-B and 4A-B illustrating how it is partitioned into the read-only and read-write memory chips of FIGS. 43A-B through 48A-D.

FIG. 50 is a flow chart illustrating how the row members of the lists stored in the read-only memory chips are computed.

FIG. 51 is a table of bit numbers and actual bits used in connection with the flow chart of FIG. 50.

FIGS. 52A-D are a detailed schematic diagram of the memory address register of FIGS. 3A-B and 42.

FIG. 52' is a diagram showing the arrangement of FIGS. 52A-D.

FIGS. 53A-D are a detailed schematic diagram of the control circuitry of FIGS. 3A-B and 42.

FIG. 53' is a diagram showing the arrangement of FIGS. 53A-D.

FIG. 54 is a waveform diagram illustrating the operation of the control circuitry of FIGS. 53A-D.

FIGS. 55A-D are a detailed schematic diagram of the memory access register of FIGS. 3A-B and 42.

FIG. 55' is a diagram showing the arrangement of FIGS. 55A-D.

FIGS. 56A-D are a detailed schematic diagram of the input-output register and gating control circuits employed in the input-output control unit of FIGS. 3A-B.

FIG. 56' is a diagram showing the arrangement of FIGS. 56A-D.

FIG. 57 is a schematic diagram of the source and relationship of the input-output party lines connected to the peripheral interface module receiving receptacles of FIG. 2.

FIG. 58 is a waveform diagram illustrating the operation of the control section of the input-output control unit of FIG. 3A-B and 38A-C.

FIG. 59 is a flow chart illustrating the operation of the control section of the input-output control unit of FIGS. 3A-B and 38A-C.

FIG. 60 is a schematic diagram of the address decoder for decoding the output selection portion of the interface modules employed with the input-output control unit of FIGS. 3A-B.

FIG. 61 is a waveform diagram of some of the input signals employed by the input-output control unit and associated interface modules of FIGS. 3A-B.

FIG. 62 is a waveform diagram of some of the output signals employed by the input-output control unit and associated interface modules of FIG. 3A-B.

FIG. 63 is a waveform diagram of some of the high speed input signals employed by the input-output control unit and associated interface modules of FIGS. 3A-B.

FIG. 64 is a waveform diagram of some of the high speed output signals employed by the input-output control unit and associated interface modules of FIGS. 3A-B.

FIG. 65 is a waveform diagram illustrating the operation of the interrupt mode of operation of the input-output control unit of FIGS. 3A-B.

FIG. 66 is a schematic diagram of logic that may be used to interface an output peripheral to the input-output control unit of FIGS. 3A-B.

FIG. 67 is a schematic diagram logic that may be used to interface an input peripheral to the input-output control unit of FIGS. 3A-B.

FIG. 68 is a schematic diagram of logic that may be used to interface an interrupting peripheral to the input-output control unit of FIGS. 3A-B.

FIGS. 69A-D are a detailed schematic diagram of the keyboard input unit employed in the adaptable programmable calculator of FIGS. 1-3B.

FIG. 69' is a diagram showing the arrangement of FIGS. 69A-D.

FIG. 70 is a detailed section of the keyboard circuitry of FIGS. 69A-D.

FIG. 71 is a pictorial view of a transformer employed in the keyboard input unit of FIGS. 3A-B and 69A-D.

FIG. 72 is a schematic diagram of the transformer of FIG. 71.

FIG. 73 is a schematic diagram of a portion of the keyboard input unit of FIGS. 69A-D.

FIG. 74 illustrates the required polarities for the drive and sense lines employed in the keyboard input unit of FIGS. 3A-B, 69A-D.

FIG. 75 is a block diagram of the magnetic card reading and recording unit employed in the calculator of FIGS. 1-3B.

FIGS. 76A-B are a schematic diagram of the magnetic card reading and recording unit of FIG. 75.

FIG. 76' is a diagram showing the arrangement of FIGS. 76A-B.

FIG. 77 illustrates the filtering required on the power lines feeding the circuitry of FIGS. 76A-B.

FIG. 78 is a block diagram illustrating how the magnetic card reading and recording unit of FIGS. 76A-B and 77 interacts with the adaptable programmable calculator of FIGS. 1-3B.

FIGS. 79A-D are a detailed schematic diagram of the output display unit employed in the adaptable programmable calculator of FIGS. 1-3B.

FIG. 79' is a diagram of the arrangement of FIGS. 79A-D.

FIG. 80A is a flow chart of the firmware display routine shown in FIGS. 13A-D.

FIG. 80B is a flow chart of the firmware display driver routine of FIGS. 13A-D.

FIG. 81 is an illustration of the character formation technique employed in the output display unit of FIGS. 1-3B and 79A-B.

FIG. 82 is a block diagram of the output printer unit employed in the adaptable programmable calculator of FIGS. 1-3B.

FIG. 83 is a cross-sectional view taken along the line A--A in FIG. 82.

FIGS. 84A-B are a detailed schematic diagram of the thermal printing head, isolation diodes, four group drivers, and one-of-ten decoder of FIG. 82.

FIG. 84' is a diagram showing the arrangement of FIGS. 84A-B.

FIG. 85 is a partial plan view of the thermal printing head of FIG. 82.

FIGS. 86A-D are a detailed schematic diagram of the twenty dot drivers, internal ten-bit shift register, printer control circuit, and printer control signals line of FIG. 82.

FIG. 86' is a diagram showing the arrangement of FIGS. 86A-D.

FIGS. 87A-B are a detailed schematic diagram of the motor drive control and motor drivers of FIG. 82.

FIG. 87' is a diagram showing the arrangement of FIGS. 87A-B.

FIG. 88 illustrates how the output printer unit of FIGS. 82-87B prints out each character.

FIG. 89 is a flow chart illustrating the printing operation of the output printer unit of FIGS. 82-87B.

FIG. 90 is a block diagram of the power supply system employed in the adaptable programmable calculator of FIGS. 1-3B.

FIG. 91 is a detailed schematic diagram of the five volt power supply of FIG. 90.

FIG. 92 is a detailed schematic diagram of the twenty-four volt power supply of FIG. 90.

FIG. 93 is a detailed schematic diagram of the sixteeen and twenty volt power supplies of FIG. 90.

FIG. 94 is a detailed schematic diagram of the positive twelve-volt power supply of FIG. 90.

FIG. 95 is a detailed schematic diagram of the negative twelve-volt power supply of FIG. 90.

FIG. 96 is a schematic diagram of an alternative ripple signal circuit that may be employed in the five-volt power supply of FIG. 91.

FIGS. 97A-B are a block diagram of an interface module that may be employed to interface a typewriter to the adaptable programmable calculator of FIGS. 1-3B.

FIG. 97' is a diagram showing the arrangement of FIGS. 97A-B.

FIGS. 98A-B are a detailed flow chart of the operation of the control logic block of FIGS. 97A-B.

FIG. 98' is a diagram showing the arrangement of FIGS. 98A-B.

FIGS. 99A-D are a detailed schematic diagram of the control logic block of FIGS. 97A-B.

FIG. 99' is a diagram showing the arrangement of FIGS. 99A-D.

FIGS. 100A-B are a detailed schematic diagram of the power gates of FIGS. 97A-B.

FIG. 100' is a diagram showing the arrangement of FIGS. 100A-B.

FIGS. 101A-B are a simplified logic diagram showing state qualifiers and instructions of the flow chart of FIGS. 98A-B.

FIG. 102 is a detailed schematic diagram of the ROM, data latch, and compare circuitry of FIGS. 97A-B.

FIGS. 103 and 104 are a tabulation of the components which may be used in the typewriter interface circuitry of FIGS. 99A-D, 100A-B, and 102.

FIG. 105 is a detailed schematic diagram of a power supply that may be employed to power the typewriter interface circuitry of FIGS. 99A-D, 100A-B, and 102.

FIG. 106A is a detailed flow chart showing processing for the LIST key illustrated in the more general flow chart of FIG. 14C.

FIGS. 106B-E are detailed flow charts of some of the subroutines employed in the flow chart of FIG. 106A.

DESCRIPTION OF THE PREFERRED EMBODIMENT

GENERAL DESCRIPTION

Referring to FIGS. 1 and 2, there is shown an adaptable programmable calculator 10 including both a keyboard input unit 12 for entering information into and controlling the operation of the calculator and a magnetic card reading and recording unit 14 for recording information stored within the calculator onto one or more external magnetic cards 16 and for subsequently loading the information recorded on these and other similar magnetic cards back into the calculator. The calculator also includes a solid state output display unit 18 for displaying alphameric information stored within the calculator. It may also include an output printer unit 20 for printing out alphameric information on a strip of thermally-sensitive recording paper 22. All of these input and output units are mounted within a single calculator housing 24 adjacent to a curved front panel 26 thereof.

As shown in FIG. 2, a plurality of peripheral input and output units including, for example, a digitizer, a marked card reader, an X-Y plotter, and a typewriter may be connected to the calculator at the same time by simply inserting interface modules 30 associated with the selected peripheral units into any of four receptacles 32 provided therefor in a rear panel 34 of the calculator housing. As each interface module 30 is inserted into one of these receptacles, a spring-loaded door 38 at the entrance of the receptacle swings down allowing passage of the interface module. Once the interface module is fully inserted, a printed-circuit terminal board 40 contained within the interface module plugs into a mating edge connector mounted inside the calculator. If any of the selected peripheral units require AC line power, their power cords may be plugged into any of three AC power outlets 42 provided therefor at the rear panel of calculator housing 24.

Referring to the simplified block diagram shown in FIGS. 3A-B, it may be seen that the calculator also includes an input-output control unit 44 (hereinafter referred to as the I/O control unit) for controlling the transfer of information to and from the input and output units, a memory unit 46 for storing and manipulating information entered into the calculator and for storing routines and subroutines of basic instructions performed by the calculator, and a central processing unit 48 (hereinafter referred to as the CPU) for controlling the execution of the routines and subroutines of basic instructions stored in the memory unit as required to process information entered into or stored within the calculator. The calculator also includes a bus system comprising an S-bus 50, a T-bus 52, and an R-bus 54 for transferring information from the memory and I/O control units to the CPU, from the CPU to the memory and I/O control units, and between different portions of the CPU. It further comprises a power supply for supplying DC power to the calculator and peripheral units employed therewith and for issuing a control signal POP when power is supplied to the calculator.

The I/O control unit 44 includes an input-output register 56 (hereinafter referred to as the I/O register), associated I/O gating control circuitry 58, and input-output control logic 60 (hereinafter referred to as the I/O control). I/O register 56 comprises a universal sixteen-bit shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from keyboard input unit 12, magnetic card reading and recording unit 14, and peripheral input units 28 such as the marked card reader via twelve input party lines 62. Information may also be transferred from I/O register 56 either bit-serially to CPU 48 via S-bus 50 or in parallel to magnetic card reading and recording unit 14, solid state output display unit 18, output printer unit 20, and peripheral output units 28 such as the X-Y plotter or the typewriter via sixteen output party lines 64.

I/O gating control circuitry 58 includes control circuits for controlling the transfer of information into and out of I/O register 56 in response to selected I/O gaulifier control signals from CPU 48 and selected I/O control instructions from I/O control 60. It also includes an interrupt control circuit 65, a peripheral control circuit 66, a magnetic card control circuit 67, a printer control circuit 68, and a display control circuit 69 for variously controlling the input and output units and issuing control signals QFG and EBT to I/O control 60 via two output lines 71 and 72. These last mentioned control circuits variously perform their control functions in response to control signal POP from the power supply, I/O qualifier control signals from CPU 48, I/O control instructions from I/O control 60, and control signals from keyboard input unit 12. Interrupt control circuit 65 initiates the transfer of information into I/O register 56 from keyboard input unit 12 or interrupting peripheral input units 28 such as the marked card reader and issues a qualifier control signal QNR to CPU 48 via output lines 73. Peripheral control circuit 66 enables interface modules 30 plugged into the calculator to respond to information from I/O register 56, control associated peripheral units 28, transfer information to and/or receive information from associated peripheral units 28, and in some cases initiate the transfer of information to I/O register 56 from the interface modules themselves. Magnetic card control circuit 67 enables magnetic card reading and recording unit 14 to respond to information in I/O register 56 and either read information into I/O register 56 from a magnetic card 16 or record information onto a magnetic card 16 from I/O register 56. Printer control circuit 68 and display control circuit 69 enable output display unit 18, and output printer unit 20, respectively, to respond to information from I/O register 56.

When a basic I/O instruction obtained from memory unit 46 is to be executed, CPU 48 transfers control to I/O control 60 by issuing a pair of I/O microinstructions PTR and XTR thereto. In response to these I/O microinstructions from CPU 48, control signal POP from the power supply, control signals QFG and EBT from I/O gating control circuitry 58, and I/O qualifier and clock control signals from CPU 48, I/O control 60 selectively issues one or more I/O control instructions to gating control circuitry 58 as required to execute the basic I/O instruction designated by CPU 48 and issues control signals, TTX, XTR, QRD, and SCB to CPU 48 via output lines 74-77. The I/O qualifier control signals issued to I/O control 60 and gating control circuitry 58 by CPU 48 are derived from the basic I/O instruction to be executed. Those qualifier control signals issued to I/O control 60 designate the specific I/O control instructions to be issued by I/O control 60, while those issued to gating control circuitry 58 designate selected control circuits to be employed in executing the basic I/O instruction.

Memory unit 46 includes a modular random-access read-write memory 78 (hereinafter referred to as the RWM), a modular read-only memory 80 (hereinafter referred to as the ROM), a memory address register 82 (hereinafter referred to as the M-register), a memory access register 84 (hereinafter referred to as the T-register), and control circuitry 85 for these memories and registers. RWM 78 and ROM 80 comprise MOS-type semiconductor memories. As shown in the memory map of FIGS. 4A-B, they are organized into nine 1,024-word pages. The basic RWM 78 contains a dedicated system storage section of 256 sixteen-bit words extending from address 1400 to address 1777 on page 0 and a separate user program and/or data storage section of 768 sixteen-bit words extending from address 16400 to address 17777 on page 7. All addresses on the memory map are represented in octal form.

An optional 1024 sixteen-bit words of RWM may be made available to the user at address 20000 to address 21777. This is accomplished by removing a top panel 90 of the calculator housing shown in FIG. 1, and inserting an additional printed circuit board containing the optional memory. The additional RWM is automatically accommodated by the calculator.

As shown in the more detailed memory map of FIG. 5, the RWM dedicated system storage section includes 12 words (addresses 1414-1427) employed as X, Y, and Z four-word working registers available to the user and 12 words (addresses 1400-1413) employed as A, B, and C four-word storage registers available to the user. A twentyfifth sixteen-bit word (address 1430) contains sixteen flags which are available to the user in writing programs for the calculator. Addresses 1430-1437 comprise a system stack and input buffer area. The high address end of this area contains keycodes as they are entered from the keyboard in building a statement to the calculator. If the keycode entered has proper syntax relative to the keycodes previously entered, that keycode is then stored in the input buffer area. The low address end of the area is known as the system stack area and is employed by CPU 48 in building Polish notated algebraic strings. Fifty-seven words (addresses 1540-1626) each having a nmemonic name, contain information which is employed by the firmware routines shown in FIGS. 13A-B. A similar area to that just described exists at addresses 1701-1715. A detailed description of the nmemonic variables is given on pages 6-12 of the calculator basic system firmware listing located elsewhere in this specification. Another area (addresses 1627-1647) of the system RWM contains information allowing plug-in ROM modules to interface with basic system firmware. An eight-word information storage area (addresses 1650-1657) is dedicated for use by the plug-in ROM modules. The following sixteen-word area is divided into two buffer areas, a display buffer (addresses 1660-1667) and an I/O buffer (addresses 1670-1677). These two areas are used to store ASCII coded information to be outputted through either the display unit 18 or the printer unit 20, of FIG. 1. Information to be printed is stored in the display buffer initially and is then placed on the printer by the printer firmware routines stored in the calculator FOM. ASCII characters representing information to be displayed may reside in either the I/O buffer or the display buffer. Various routines in the calculator firmware are employed for the purpose of retrieving information into ASCII characters for storage in the display or I/O buffers. Eighteen words (addresses 1716-1737 of FIG. 6) are employed for the temporary storage of information as control is passed from one routine to another. Eight words (addresses 1744-1747 and 1754-1757) are employed as "AR1" and "AR2" four-word working registers for performing binary-coded-decimal arithmetic. An additional eight words (addresses 1740-1743 and 1750-1753) are employed as working data registers Xc and Yc for implemention of the trigonometric functions in conjunction with the use of the trigonometric plug-in ROM module. The word located at address 1760 is used to store the contents of one of the working registers of CPU 48 during an interrupt cycle. A variable-length "system subroutine stack" (addresses 1761-1776) is employed for storing return addresses required by programs stored in ROM 80 and as temporary storage for housekeeping information required by CPU 48. The last word in the system RWM (address 1777) is used to store a pointer indicating the next available location for the return address of the next subroutine call within the basic system. A complete assembly language description of the system RWM is included at pages 5-12 of the calculator basic system firmware listing.

As shown in the memory map of FIGS. 4A-B, user program and/or data storage section of RWM 78 contains 692 words (173 registers) available to the user (as user addresses 16510-17777) for storing programs and/or data and 72 words dedicated for use by CPU 48. An additional 1024 program-step and/or data words (256 registers) may be made available to the user (as user addresses 20000-21777).

Also, as shown in the memory map of FIGS. 4A-B, the basic ROM 80 contains 7168 sixteen-bit words extending from address 0000 to address 1377 on page 0 , from address 2001 to address 7777 on page 3, and from address 16000 to address 16377 on page 7. Routines and subroutines of basic instructions for performing the basic functions of the calculator and constants employed by these routines and subroutines are stored in these portions of ROM 80. An additional 3,072 sixteen-bit words of ROM may also be added on pages 4, 5, and 6 in steps of 512 and 1,024 words. This is accomplished by simply insering plug-in ROM modules 92 into receptacles 94 provided therefor in top panel 90 of the calculator housing as illustrated in FIG. 1 by the partially-inserted plug-in ROM module on the left. As each plug-in ROM module 92 is inserted into one of these receptacles a spring-loaded door 95 at the entrance of the receptacle swings down allowing passage of the plug-in ROM module. Once the plug-in ROM module is fully inserted as illustrated by the plug-in ROM module on the right, a printed circuit terminal board 96 contained within the plug-in ROM module plugs into a mating edge connector mounted inside the calculator. A handle 98 pivotally mounted at the top end of each plug-in ROM module 92 facilitates removal of the plug-in ROM module once it has been fully inserted into one of the receptacles 94.

Routines and subroutines of basic instructions (and any needed constants) for enabling the calculator to perform many additional functions are stored in each plug-in ROM module 92. The user himself may therefore quickly and simply adapt the calculator to perform many additional functions oriented toward his specific needs by simply plugging ROM modules of his own choosing into the calculator. Added plug-in ROM modules are automatically accommodated by the calculator by momentarily interrupting power or by depressing an ERASE MEMORY key, and they are associated with definable section 91 of keyboard input unit 12 or employed to expand the functions performed by this and other sections of the keyboard input unit.

Referring again to FIG. 3A-B, M-register 82 of the memory unit comprises a recirculating sixteen-bit serial shift register into which information may be transferred bit-serially from CPU 48 via T-bus 52 and out of which information may be transferred bit-serially to CPU 48 via S-bus 50. Information shifted into M-register 82 may be employed to address any word in RWM 78 or ROM 80 via fifteen output lines 106.

T-register 84 of the memory unit comprises a recirculating sixteen-bit serial shift register into which information may be transferred either bit-serially from CPU 48 via T-bus 52 or in parallel from any addressed word in RWM 78 and ROM 80 via sixteen parallel input lines 108. Information may be transferred from T-register 84 either bit-serially to CPU 48 via S-bus 50 or in parallel to any addressed word in RWM 78 via sixteen parallel output lines 110. The four least significant bits of information contained in T-register 84 may comprise binary-coded-decimal information and may be transferred from the T-register in parallel to CPU 48 via three parallel output lines 112 taken with S-bus 50.

The control circuitry 85 of the memory unit controls these transfers of information into and out of M-register 82 and T-register 84, controls the addressing and accessing of RWM 78 and ROM 80, and refreshes RWM 78. It performs these functions in response to memory microinstructions, memory clock pulses, and shift clock pulses from CPU 48.

CPU 48 includes a register unit 114, an arithmetic-logic unit 116 (hereinafter referred to as the ALU), a programmable clock 118, and a microprocessor 120. Register unit 114 comprises four recirculating sixteen-bit shift registers 122, 124, 126, and 128 and one four-bit shift register 130. Shift registers 122 and 124 serve as sixteen-bit serial accumulator registers (hereinafter referred to as the A-register and the B-register, respectively) into which information may be transferred bit-serially from ALU 116 via T-bus 52 and out of which information may be transferred bit-serially to ALU 116 via R-bus 54. The four least significant bit positions of A-register 122 also serve as a four-bit parallel accumulator register into which four bits of binary-coded-decimal information may be transferred in parallel from ALU 116 via four parallel input lines 132 and out of which four bits of binary-coded-decimal information may also be transferred in parallel to ALU 116 via three parallel output lines 134 taken with R-bus 54.

Shift register 126 serves as a sixteen-bit system program counter (hereinafter referred to as the P-register) into which information may be transferred bit-serially from ALU 116 via T-bus 52 and out of which information may be transferred bit-serially to ALU 116 via R-bus 54. Information contained in the least significant bit position of P-register 126 may also be transferred as a qualifier control signal QPO to microprocessor 120 via output line 135.

Shift register 128 serves as a sixteen-bit qualifier register (hereinafter referred to as the Q-register) into which information may be transferred bit-serially from ALU 116 via T-Bus 52 and out of which information may be transferred bit-serially to ALU 116 via R-bus 54, Information contained in the five least significant bit positions of Q-register 128 is transferred to I/O gating control circuitry 58 as five one-bit I/O qualifier control signals Q00-Q04 via five parallel output lines 136, and information contained in the six next least significant bit positions of the Q-register is transferred to I/O control 60 as six one-bit I/O qualifier control signals Q05-Q10 via six parallel output lines 138. Similarly, information contained in the seven least significant, the ninth and eleventh least significant, and the most significant bit positions of Q-register 128 and information derived from the thirteenth, fourteenth, and fifteenth bit positions of the Q-register may be transferred to microprocessor 120 as eleven one-bit microprocessor qualifier control signals Q00-Q06, Q08, Q10, Q15, and QMR via eleven output lines 140. Information contained in the twelfth through the fiteenth least significant bit positions of Q-register 128 may be transferred to microprocessor 120 as a four-bit primary address code via four parallel output lines 142.

Shift register 130 serves as a four-bit serial extend register (hereinafter referred to as the E-register) into which information may be transferred bit-serially either from ALU 116 via T-bus 52 or from the least significant bit position of T-register 84 via input line 144. Information may also be transferred out of E-register 130 to ALU 116 via R-bus 54.

Register unit 114 also includes control circuitry 146 for controlling the transfer of parallel binary-coded-decimal information into and out of A-register 122 and the transfer of serial binary information into and out of A-register 122, B-register 124, P-register 126, Q-register 128, and E-register 130. This is accomplished in response to register microinstructions from microprocessor 120, control signals TTX and XTR from I/O control 60, and shift clock control pulses from programmable clock 118. Control circuitry 146 includes a flip-flop 148 (hereinafter referred to as the A/B flip-flop) for enabling the transfer of information into and out of either the A-register 122 or the B-register 124 as determined by the state of the A/B flip-flop. The state of A/B flip-flop 148 is initially determined by information Q11 transferred to the A/B flip-flop from the twelfth least significant bit position of Q-register 128 but may be subsequently complemented one or more times by microinstruction CAB from microprocessor 120.

ALU 116 may perform either one-bit serial binary arithmetic on data received from T-register 84 or M-register 82 via S- bus 50 and/or from any register of register unit 114 via R-bus 54 or four-bit parallel binary-coded-decimal arithmetic on data received from T-register 84 via output lines 112 taken with S-bus 50 and/or from A-register 122 via output lines 134 taken with R-bus 54. It may also perform logic operations on data received from memory unit 46 and/or register unit 114 via any of these lines. The arithmetic and logic operations performed are designated by ALU microinstructions from microprocessor 120 and are carried out in response to these microinstructions, shift clock control pulses from programmable clock 118, and control signal SCB from I/O control 60. Information is also transferred from ALU 116 to A-register 122 via output lines 132 or to I/O register 56, M-register 82, T-register 84, or any register of register unit 114 via T-bus 52 in response to microinstructions and control signals applied to these registers. If a carry results while ALU 116 is performing either one-bit serial binary arithmetic or four-bit parallel binary-coded-decimal arithmetic, the ALU issues a corresponding qualifier control signal QBC and QDC to microprocessor 120 via one of two output lines 152 and 154.

Programmable clock 118 includes a crystal-controlled system clock 156, a clock decoder and generator 158, and a control gate 160. System clock 156 issues regularly recurring clock pulses to clock decoder and generator 158 via output line 162. In response to these regularly recurring clock pulses from system clock 156 and to four-bit clock codes from microprocessor 120, clock decoder and generator 158 issues trains of n shift clock pulses to ALU 116, M-register 82, T-register 82, and all of the registers of register unit 114 via output line 164. These trains of n shift clock pulses are employed for shifting a corresponding number of bits of serial information into or out of any of these registers or for shifting a carry bit in the ALU. The number n of pulses in each of these trains may vary from one to sixteen as determined by the number of bits of serial information required during each operation to be performed. In response to a control signal CCO from microprocessor 120, control gate 160 prevents any shift clock pulses from being applied to the ALU or any of these registers. Upon completion of each train of n shift clock pulses, clock decoder and generator 158 issues a ROM clock pulse to microprocessor 120 via output line 166 and an I/O clock pulse to I/O control 60 via output line 168. In response to the regularly recurring clock signal from system clock 56, clock decoder and generator 158 also issues correspondingly regularly recurring memory clock pulses to memory unit 46 via output line 170.

Microprocessor 120 selectively issues two I/O microinstructions to I/O control 60 via two output lines 172, six memory microinstructions to memory unit 46 via six output lines 174, thirteen register microinstructions to register unit 114 via thirteen output lines 176, and five ALU microinstructions to ALU 116 via five output lines 178. It also issues a four-bit clock code associated with each of these microinstructions to clock decoder 158 via four output lines 180. These microinstructions and associated clock codes are issued as determined by the control signal POP from the power supply, the eleven microprocessor qualifier control signals from Q-register 128, the four-bit primary address codes from Q-register 128, and the five microprocessor qualifier control signals from I/O control 60, interrupt control 65, ALU 116, and P-register 126.

As shown in the simplified flow chart of FIGS. 6A-B, microprocessor 120 executes a hardware diagnostic routine (stored within the microprocessor itself) in response to the control signal POP. Upon completion of this diagnostic routine, ALU 116 issues the qualifier control signal QBC indicating whether or not the diagnostic routine was successful. Microprocessor 120 thereupon responds to this qualifier control signal by entering the basic machine operating loop and issuing microinstructions causing a sixteen-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to Q-register 128. Microprocessor 120 thereupon sequentially responds to one or more additional qualifier control signals by issuing microinstructions and associated clock codes for executing the instruction then contained in Q-register 128 and causing another sixteen-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to the Q-register. When an instruction requiring multiple branching is contained in Q-register 128, microprocessor 120 issues a pair of microinstructions UTR and XTR causing the micro-processor to respond to a four-bit primary address code from the Q-register by issuing additional microinstructions and associated clock codes for executing the instruction contained in the Q-register.

As illustrated by the basic machine operating loop shown in the flow chart of FIGS. 6A-B, microprocessor 120 initially responds to the qualifier control signal QNR either by issuing microinstructions and associated clock codes for interrupting the basic machine operating loop and executing an I/O service routine or by issuing microinstructions and associated clock codes for loading A/B flip-flop 148 with the information Q11 contained in Q-register 128. The manner in which microprocessor 120 responds is determined by the condition of the qualifier control signal QNR, which in turn indicates whether or not the basic machine operating loop should be interrupted.

Assuming the basic machine operating loop is not to be interrupted, microprocessor 120 loads the information Q11 into A/B flip-flop 148 and responds to the qualifier control signal QMR either by issuing microinstructions for transferring an address portion of the instruction contained in Q-register 128 from T-register 84 into M-register 82 or by responding to another qualifier control signal Q15. Again, the manner in which microprocessor 120 responds is determined by the condition of the qualifier control signal QMR, which in turn indicates whether or not the instruction contained in Q-register 128 is a memory reference instruction.

Assuming the instruction contained in Q-register 128 is a memory reference instruction, microprocessor 120 transfers the required address information into the M-register 82 and responds to qualifier control signal Q10 either by issuing microinstructions and associated clock codes to select the base page of the memory (i.e. page 0) or by issuing microinstructions and associated clock codes to select the current page of the memory (i.e. the page from which the instruction contained in Q-register 128 was obtained). In either case, the microprocessor then issues microinstructions as required to read data from the preset page of the memory at the address designated by the address information last transferred into M-register 82. Upon completion of this operation, microprocessor 120 responds to qualifier control signal Q15 by issuing additional microinstructions and associated clock codes to execute an indirect memory access operation if the condition of this qualifier control signal indicates that the address information contained in M-register 82 is indirect.

Assuming the address information contained in M-register 82 is direct (or upon completion of the indirect memory access operation), microprocessor 120 issues microinstructions and associated clock codes causing the microprocessor itself to respond to a four-bit primary address code from the Q-register. The microprocessor responds by issuing additional microinstructions and associated clock codes for executing whichever one of ten possible memory reference instructions is contained in Q-register 128 and designated by the four-bit primary address code. Following execution of the designated memory reference instruction, microprocessor 120 issues microinstructions and associated clock codes causing another sixteen-bit instruction stored in ROM 80 to be loaded into T-register 84 and transferred from there to Q-register 128 thereby beginning another cycle of the basic machine operating loop.

As illustrated by other possible paths of the basic machine operating loop shown in FIGS. 6A-B, microprocessor 120 sequentially responds to other qualifier control signals when other types of instructions are contained in Q-register 128. For example, when an I/O instruction is contained in Q-register 128, microprocessor 120 sequentially responds to qualifier control signals QNR, QMR, Q15, Q10, and QRD by issuing microinstructions and associated clock codes to execute the I/O instruction. It should be noted that the microprocessor qualifier control signals not shown in the simplified flow chart of FIGS. 6A-B are variously contained within those flow chart blocks requiring decisions as will hereinafter become apparent.

The calculator firmware operational diagram of FIGS. 13A-B illustrates the basic components of the calculator firmware. These components comprise routines which reside in the calculator ROM 80 and serve to implement the definition of the calculator. Control information passing between routines is represented by solid lines on the drawing, while the broken lines represent information transfer between the system and user portions of RWM 78 and the firmware routines.

Referring to FIGS. 13A-B, it is shown that the calculator hardware units are controlled by firmware routines contained in ROM 80. These units comprise an on-off power switch 182, a keyboard input unit 12, a display unit 18, a printer unit 20, and a magnetic card reading and recording unit 14.

Operation of the calculator is begun by placing the on-off switch in the "on" position, thus forcing the hardware internal to the calculator to execute the instruction located at address 0000 of ROM 80. This instruction directs control to the start-up routine 200, which is depicted on the memory map of FIGS. 4A-B (addresses 2127-2226), and described in detail on pages 40 and 41 of the basic system firmware listing. The purposes of this routine are to initialize RWM 78, set the stack pointer address at location 1777, set the rotation of numeric output to float 9, initialize certain variables in the system RWM area for later use by other firmware routines, set up a configuration code describing which option blocks are in use, and set up a nmemonic link, a syntax link, and an execution link to the option blocks. These links are placed in RWM 78 at addresses 1627-1647 as shown in the detailed memory map of FIG. 5.

After completion of the start-up routine, control is passed to the system monitor routine 202 (addresses 6221-6235), which directs all keycodes to their proper handling routines. A detailed description of this routine is shown at page 125 of the basic system firmware listing.

FIG. 14A shows the sequences discussed above from "power on" through start-up to system monitor routine 202. Also shown is a more detailed drawing of the system monitor. Upon entry of the system monitor from start-up the display routine 204 (FIGS. 13A-B) is called. Control resides therein until a new key is depressed on keyboard 12. During the start-up initialization described above the input buffer was also given the first line of the user area of RWM 78. Thus, when the display routine is initially called the following display will appear: 0:END. This display is used to indicate the occurence of reset in machine operation.

Referring again to FIGS. 13A-B, control now resides in display routine 7204, after having received control from system monitor routine 202 with the command to display the input buffer. The display routine will retain control until a new key is depressed and passes control to display driver routine 206 whenever necessary to make a display. The display driver routine accepts ASCII coded information from either the display buffer or the I/O buffer as previously described and converts such information to a 5 × 7 bit matrix as required by the light-emitting-diode (LED) display 18. After each complete pass through the display buffer, control is returned to display routine 204, which in turn checks a nmemonic word labeled .WMOD to see if a new key has been depressed. Upon entry of a new key, control is passed to the basic interrupt routine 208, which stores the keycode information in the system RWM 78 and at the same time sets a flag indicating that a new key has been depressed. When display routine 204 discovers that a new key has been depressed, control is returned to system monitor routine 202.

Referring again to FIG. 14A, it is seen that if a new key is entered the answer to the new-key question is yes, and key processing begins.

As shown in FIGS. 14A-B, the coding below the point labeled SMON has been implemented as a subroutine which is called by the system in processing certain keys. The processing routine for each key is determined by examining the keycode class, a biased control number CN, and a table state word TSW. TSW takes on values from one through six and uses its sign bit as a flag. For TSW equal to one, a line is being built by the keyboard. TSW equal to two indicates a current line recalled from the user RWM 78. TSW equal to three means insert a keycode rather than replace a keycode. For TSW equal to four the interpreter has control of the system. TSW equal to five indicates the intermode state. If TSW is equal to six the current line has been executed. Except for TSW equal to three the sign bit set means that the end of line character () is present in the current line. For TSW equal to three the sign bit indicates overflow in the user program area. The value of TSW indicates a particular state of system monitor routine 202 shown in FIG. 13A-B.

The class and control number are determined by data in MTABL, which occupies addresses 0005-0204 of ROM 80 as shown on the detailed memory map of FIGS. 4A-B. A detailed compilation of the information stored in MTABL relative to each key appears at pages 13-15 of the basic system firmware listing. The format for each of the sixteen-bit words in MTABL is as follows: the most significant six bits represent the control number associated with the particular keycode; the following two bits are referred to as the class; the next four bits indicate the stack priority or the option block source for the keycode; the least significant four bits show the compare priority or relative value of the keycode if it is an option block key associated with a plug-in ROM module. When a keycode is processed, the corresponding sixteen-bit word from MTABL is loaded into CODE. The keycode value is stored in SKEY; the control number is identified and placed in nmemonic location CN; and the class is extracted from the word when needed. The classes of keys are as follows: class equal to zero are the programmable keys; class equal to one are the option block keys; class equal to two are the user program interruptable keys; class equal to three are the control keys. The class two keys are the STOP, FIXED N, FLOAT N, NORMAL, TRACE, and SET-FLAG keys. The class three keys are the RUN, EXECUTE, LIST, STORE, INSERT, FORWARD, RECALL, CLEAR, DELETE, and BACK keys. The addresses of the processing routines referred to above and as shown in the flow chart of FIGS. 14A-C are arranged as a two dimensional array with locations determined by TSW and the biased control number CN. These addresses are stored by row. The processing routines are labeled to indicate the values of TSW and CN; that is, A.12 located on the path of the store key indicates TSW equal to one and CN equal to two. The processing routines shown in the lower portion of the flow chart indicate general considerations in processing particular keycodes, and not all routines are illustrated. Detailed flow charts of display routine 204 and display drive routine 206 are shown in FIGS. 80A-B, respectively. The basic system firmware listing may be consulted for a more detailed explanation of the processing sequence. FIGS. 106A-E are detailed flow charts of the processing involved in the LIST key routine shown in FIG. 14C.

Referring again to FIGS. 13A-B, control has resided in the system monitor routine 202 as passed to it by display routine 204 upon entry of a new key from keyboard 12. In the case of a programmable key, control is passed to the compiler routine 210. As shown in the detailed memory map of FIGS. 4A-B, the compiler routine resides in ROM addresses 4055-4546 and can be examined in detail at pages 72-86 of the basic system firmware listing. The compiler routine is employed to convert algebraic expressions from infix notation to Polish notation to speed program execution and also serves to check the propriety of statements entered into the calculator from the keyboard. As shown in FIGS. 13A-B, once processing has been completed by compiler routine 210, control is returned again to system monitor routine 202 along with syntax error information. If the current keycode is correct within the framework of previously entered keys, no syntax error exists, and the system monitor proceeds to build ASCII information from the keycodes in the input buffer and place it into the display buffer to be displayed by display routine 204. Control will then reside in the display routine until a new key is entered.

The above described procedure continues until the end-of-line () is reached, at which time the user may exercise one of several options. He may decide to store the current line as a program line within a program, in which case he depresses the STORE key, giving control to the system monitor routine 202. In response to the STORE key, information in the compiler area is brought from the system RWM area to the user RWM area and placed into the program residing therein, after which control is returned to system monitor routine 202 for building the correct display in the display buffer for use by the display routine.

If the RUN PROGRAM key is now depressed, control is passed from display routine 204 to the system monitor routine 202 and then to the interpreter routine 214, which extracts program information in Polish notation from the user RWM. Had the EXECUTE key rather than the RUN PROGRAM key been depressed, the interpreter routine would have taken the information from the compiler output area. Interpreter routine 214 occupies ROM addresses 4547-5700 as shown on the memory map of FIGS. 4A-B and is described in detail at pages 87-106 of the basic system firmware listing. As the interpreter routine extracts keycodes from memory their execution routines are called. The system continues in this state until a program error is encountered or a stop command is given. Keys which can effect interruption of the system during the running of a program are the so called program-interruptable keys referred to above as the class two keys. These are the STOP, FIX N, FLOAT N, NORMAL, TRACE, and SET FLAG keys.

As described above, the nmemonic word TSW is set equal to four when control resides in program interrupt routine 216. When keys are entered under this condition only those are processed which are valid at that time. If the key entered is a class two interruptable key, control is passed from the interpreter routine to the system monitor routine and then to the program interrupt routine. Upon completion of processing thereby, control returns to system monitor routine 202 and then to interpreter routine 214, provided the interruptable key depressed was not the STOP key. Upon completion of processing by the interpreter routine, control is again passed to the system monitor routine. In response to entry of the RUN PROGRAM, EXECUTE key the system monitor routine calls format routine 218 which resides in system ROM addresses 2227-2535 and is described in detail in pages 42-49 of the basic system firmware listing. The format routine converts numeric information from internal format to ASCII characters and places them in the display buffers. When such processing is complete, control is passed to the system monitor routine 202 and then to display routine 204 for display of the results.

In response to the LIST key, the system monitor routine passes control to the program list routine 220, which calls the uncompile routine 222 for the purpose of converting algebraic expressions from Polish to infix notation and placing the result in the input buffer, after which control is returned to the program list routine. Program list routine 220 then converts the information contained in the input buffer to ASCII coded information and places it in the display buffer, after which control is passed to printer driver routine 224 for the purpose of outputting sixteen characters on printer 20. Control then returns to program list routine 220 which checks whether or not more characters are required to complete outputting the line. If more characters are required, the print driver routine 224 is recalled, and program listing continues until an end-of-program mark (-1) is encountered or the STOP key is depressed on keyboard 12. When listing is complete the program list routine computes the number of data registers available to the program, adjusts the printer paper so that the listing contained thereon may be torn from printer 20, and resets the program pointers to the beginning of the program. Control is then passed to the system monitor routine 202 and the display routine 204.

Magnetic card driver 226 is called by a record and mainline routine which is part of the execution routines residing in interpreter routine 214. The record and mainline routine is given control when the interpreter routine encounters a load and record command. Magnetic card driver 226 takes data register or program information from user RWM 78 and transfers sixteen-bit words onto an external magnetic card.

Detailed assembly language information relating to all of the firmware routines and subroutines herein described may be obtained by referring to the memory map of FIGS. 4A-B and the basic system firmware listing.

KEY OPERATIONS

All operations performed by the calculator may be controlled or initiated by the keyboard input unit and/or by keycodes entered into the calculator from the keyboard input unit, the magnetic card reading and recording unit, or peripheral input units such as the marked card reader and stored as program steps in the program storage section of the RWM. An operational description of the keyboard input unit is therefore now given with specific reference to FIG. 1, except as otherwise indicated.

TURN-ON PROCEDURE

When the OFF/ON switch located on the front of the calculator is set to the ON position, the following display appears:

φ : END

The calculator is then ready for operation.

INITIALIZING THE CALCULATOR

The ERASE key has the same effect as switching the calculator off and then on again. It erases all stored data and programs from memory and clears the results of any previous calculation or operation.

THE FUNDAMENTAL USER OPERATION

Communication with the calcuator is through the display. In general, there are two basic steps to follow when performing operations:

1. A set of directions is written into the display by actuating the appropriate keys.

2. The calculator is then instructed to follow these directions, and the result of any numerical operation is automatically displayed. When making keyboard calculations, this step consists solely of actuating the EXECUTE key.

These two basic steps form the fundamental user operation. With a few exceptions, all operations such as making calculations, loading or running programs, giving directions to the printer, etc., consist of some variation of the fundamental user operation.

DIAGNOSTIC NOTES

In addition to displaying numbers, directions, and the results of operations, the calculator also displays diagnostic notes to inform the user of operational errors or of special situations. The basic notes are numbered from 01 to 16 (higher numbered notes are associated with the various plug-in ROM's). The note number indicates the type of error or situation. For example, NOTE 01 indicates that the calculator was given a direction which it could not understand; NOTE 16 indicates that the printer paper supply has been exhausted. A list of the basic notes and a brief description of their meanings is given in the appendix at the end of Key Operations.

When a note condition occurs in a program execution is halted. The display then indicates the note as well as the number of the program line in which the note condition occurred; e.g.,

NOTE φ2 IN 4

indicates that a note 02 condition occurred during line 4.

KEYING DIRECTIONS AND NUMBERS

Directions are written into the display by actuating the appropriate keys. Suppose, for example, that the user desires to add 2 to 4 and print out the result. The keys PRINT 2 + 4 are actuated. The calculator does not, however, follow these directions until it is instructed to do so by actuating EXECUTE. It then prints (and displays) the result, 6. Numbers are keyed into the display, as on any standard office-machine, by actuating the number keys (0 through 9) and the decimal point key in the required order. If a number is negative the minus sign should be keyed first before the number is keyed. Use of commas (such as in 32,341.6) is not allowed. As is the case with a direction, even though the keyed number is displayed, it will not be executed by the calculator until the EXECUTE key is actuated. It is not normally desirable to execute just a single number. The number would usually be included within some set of directions, and then the directions would be executed.

USE OF CLEAR

The CLEAR key clears the display, but leaves the memory unaltered. It operates immediately and does not have to be followed by EXECUTE. An end-of-line symbol () appears in the display when CLEAR is actuated, which indicate that the calculator is idle. It is not necessary to clear the display before keying the next direction as long as the previous direction has been executed. In this case use of CLEAR is optional. If no subsequent execution has taken place since the last direction was keyed, then CLEAR must be used. These keys will be printed, and subsequent tracing will cease.

MAKING ARITHMETIC CALCULATIONS

For arithmetic, the fundamental user operation consists of writing an arithmetic expression into the display and then actuating the EXECUTE key, to instruct the calculator to evaluate that expression. An arithmetic expression is written into the display by pressing keys in the same order as they would be written on paper, one key per character or symbol. The arithmetic expression may then be executed by simply pressing the EXECUTE key. This is illustrated by the keying sequences and displayed answers given below.

______________________________________ Keying Sequence Displayed Answers ______________________________________ 3 + 6 EXECUTE 9.φφ 9 . 3 - 6 EXECUTE 3.3φ - 7 EXECUTE -7.φφ 6 * ( - 7 ) EXECUTE -42.φφ 8 . 2 5 * 4 EXECUTE 33.φφ 6 * 3 / ( 1 1 - 2 ) EXECUTE 2.φφ √ 3 EXECUTE 1.73 √ 4 + 5 EXECUTE 7.φφ √ ( 4 + 5 ) EXECUTE 3.φφ ______________________________________

As in the above examples, quantities in parentheses are treated as one quantity. Thus √(4 + 5) is equivalent to √9, whereas, √4 + 5 adds 5 to the square root of 4. The expression 4(3 + 2) is the equivalent of the expression 4*(3 + 2). Use of the multiplication operator is implied and is therefore optional in such cases. Parentheses can be nested (i.e., parentheses inside parentheses, etc.) but they must always be balanced, that is, there must be the same number of left-handed parentheses as there are right-handed.

THE ARITHMETIC HIERARCHY

When an arithmetic expression contains more than one operator, as do several of the preceding examples, there is a prescribed order of execution. An expression must be properly written or the answer will be wrong. The order of execution, known as the hierarchy is shown below:

1. Mathematical functions such as square root;

2. Implied multiplication;

3. Multiplication and division; and

4. Addition and subtraction.

Where an expression contains two or more operators at the same level in the hierarchy, they will be executed in order from left to right. The use of parentheses enables the order of execution to be changed. Thus, in the expression √(4 + 5) the addition operator is executed before the square root operator even though the addition operator occupies a lower level in the hierarchy.

EXCEEDING THE LENGTH OF THE DISPLAY

The length of an expression is not limited to the length of the display. As each excess symbol is keyed, the display shifts left to make room. The maximum allowable length for an expression varies between 35 and 69 keystrokes, depending upon the nature of the expression. If too many keys are pressed the display shows NOTE 09 (see the section on diagnostic notes below). Depending upon the nature of the expression the note may appear either before or after the EXECUTE key is pressed. In either case, the operator must press CLEAR and write a shorter expression.

MAKING CORRECTIONS

The BACK and FORWARD keys enable a displayed expression to be altered or corrected without re-keying the entire sequence. If a wrong key is pressed when writing an expression, it can be corrected immediately by pressing the BACK key followed by the correct key, as illustrated below:

Keying Sequence Display ______________________________________ 2 + BACK * 4 2 * 4 ______________________________________

A displayed expression can be blanked, key by key in reverse order, by pressing BACK once for each displayed key. The blanked keys can then be returned to the display one at a time by pressing FORWARD. If an expression contains a wrong key, press BACK until that key is blanked, press the correct key and then press FORWARD to return each subsequent key (or, if extra keystrokes are required, key in the remainder of the expression). For example, if the number 123456789 is keyed incorrectly into the display as 123444789, the error may be corrected as indicated by the following steps:

Keying Sequence Display ______________________________________ BACK BACK BACK BACK BACK 1234 5 6 FORWARD FORWARD FORWARD 123456789 ______________________________________

If the incorrect expression has been executed but no key has since been pressed, the expression can be returned to the display (by pressing BACK), corrected as before, and then again executed.

Any line of a stored program may be recalled into the display and then completely blanked by repeatedly actuating the BACK key. One additional actuation of the BACK key will bring the entire next preceding line of the stored program into the display. It is then possible to backstep through that line and bring its predecessor into the display, etc. Analogously, the FORWARD key may be repeatedly actuated to bring those lines succeeding the current line into the display.

To remove a portion of a line the BACK key is repeatedly actuated until the right most character, symbol or mnemonic of the portion to be deleted becomes the right most item in the display. The DELETE key is then actuated once for each character, symbol or mnemonic to be removed. Then, if the right most item of the line is not visible in the display, the FORWARD key is repeatedly actuated. The user may then continue writing the line, execute it, or store it, as appropriate. For example, assume it is desired to delete the underlined portion from the following line:

FXD 2;X➝Y;PRT (A + B)/A;GTO 4

This is accomplished by repeatedly actuating the BACK key until the display appears as follows:

;X➝Y;PRT (A + B)/A

Next, the DELETE key is actuated thirteen times. At first the display shifts to the right to bring the first part of the line into view, which in this case is FXD 2. However, FXD will not appear until there is room in the display for all four characters plus the space between D and 2. After this first part of the line comes into view, the line appears to shorten by losing an item from the right-hand side of the display each time the DELETE key is actuated, while the rest of the line remains stationary. After the segment has been deleted, the FORWARD key is repeatedly actuated until the end of the now modified line comes into view as follows:

FXD 2;GTO 4

The user may now continue writing this line, execute it, or store it, as he desires.

To add a segment to the interior of a line the BACK key is repeatedly actuated until the right most item visible in the display is the character, symbol or mnemonic immediately preceding the segment sought to be added. The INSERT key is then actuated and followed by the keys which describe the desired segment. The FORWARD key is next repeatedly actuated until the end of the line is in view. As the keys following INSERT but preceding FORWARD are actuated their mnemonics are inserted into the line with no loss of any other items in the line. The right-hand portion of the line is shifted to the right to make room for the additional items being inserted. This action continues until one of the keys, BACK, FORWARD, DELETE, CLEAR, EXECUTE or STORE is actuated. Generally the insertion of a portion of a line is terminated with the FORWARD key to return to the end of the line. For example, assume it is desired to insert the portion

2φ➝B

into the line

1φ➝A;3φ➝C

To accomplish the insertion, the BACK key is repeatedly actuated until the semicolon becomes the right most item in the display. The INSERT key is then actuated and followed by the key sequence 2φ➝B. Next, the FORWARD key is actuated until the entire line is visible as follows:

1φ➝A;2φ➝B;3φ➝C

If an error is made by the user during the entry of a portion of a line being inserted into an existing line, the erroneous items may be removed by actuating the DELETE key. The user may then continue writing the desired line portion after actuating the INSERT key.

In addition to modifying individual lines of a program as discussed above, it is also possible to insert entire lines into or delete entire lines from, the interior of a program stored in memory. If it is desired to add a line between existing lines 4 and 5, the added line would become new line 5 while the old line 5 would become the new line 6. Similarly, if it is desired to remove line 3 from a program, the old line 4 would become the new line 3, the old line 5 would become the new line 4, etc. In both cases the number of available R registers is automatically adjusted after the change.

To insert a line into a program the program line counter is first set to the line number which will be associated with the new line. This may be accomplished, for example, by actuating the GO TO key followed by the number keys representing the line number followed by the EXECUTE key. The new line is then written into the display and followed by sequential actuation of the INSERT and STORE keys. The new line becomes stored, and all succeeding lines of the program together with their line numbers are shifted to provide room.

To delete a line from a program the program line counter is first set to the line number of the line to be deleted. Sequential actuation of the RECALL and DELETE keys will remove the line and shift all succeeding lines and their line numbers to close the gap.

THE DATA MEMORY

The basic calculator contains 179 registers: six storage and working registers (A, B, C, X, Y and Z) and 173 program and data storage registers (RO through R172). An additional 256 R-registers (R173 through R428) may be added giving a total of 435 registers.

The A, B, C, X, Y and Z registers are selected by pressing the A, B, C, X, Y and Z keys, respectively, while the R registers are selected by pressing the R() key followed by the appropriate number keys 0 through 172 or 428. The argument of the R() key may be a computed quantity. For example, sequentially pressing the R(), (, 7, 0, /, 2, and )keys denotes the R35 register. The argument of the R() may also be a variable. Then, if the register A contains the number 15, sequentially pressing the R() and A keys denotes R15 register. Similarly, if the R5 register contains the number 10 and the C register contains the number 25, sequentially pressing the R(), (, R(), 5, +, C, and) denotes the R35 register.

The register denoted by the keying sequence R(), R(), R() . . . R() followed by one or more number keys is determined by the number designated by the number keys and by the numbers contained in the various registers. For example, the keying sequence R(), R(), 2 denotes the R8 register if R2 contains the number 8.

When the number following the R() key does not have a strictly integral value, the fractional part of the value is ignored. Thus, the keying sequence R(), 3, 5, 6, . , 6 denotes the R35 register. A plus sign immediately following the R() key is dropped when the line containing it is stored. Thus, the keying sequence R(), +, /, % is stored as R() 35. A minus sign immediately following the R() key is not permitted, and causes a syntax error (NOTE φ1) If the R() key is followed by a quantity whose value is either negative, or greater than the number of available R registers, an error during executiom results (the indication will be either NOTE φ5 or NOTE φ6, depending upon the exact circumstances).

Some of the plug-in read-only memory modules require part of the memory for their own use. When one of these modules is installed, it automatically takes the required registers, starting at the highest numbered register and working downwards. Those registers are then temporarily not available for program or data storage, until the module is removed.

When programs are stored they start in the highest-numbered available R-register and sequentially fill the memory downwards. Programs cannot be stored in the A, B, C, X, Y and Z registers. It is, therefore, most convenient to store data first in the A, B, C, X, Y and Z registers and then in the lower numbered R-registers. If the memory contains no program (i.e. at turn-on, or if ERASE has been pressed), then all registers (except those required by a plug-in read-only memory module will be available for data storage. If the memory does contain a program, then the higher-numbered registers will not be available for data diagnostic NOTE φ6 will be displayed if the operator attempts to store data in a register which is not available.

The number of available R-registers can be determined at any time by pressing CLEAR LIST STOP. The printer will start to list the program (the STOP saves having to wait for the whole program to be listed). At the bottom of the list will be a number preceded by the letter R indicating the number of R-registers available. (The lowest-numbered register is R0; subtract 1 from the number printed to obtain the name of the highest-numbered register available for data storage).

STORING DATA

One register can contain one data-number. It is not necessary to clear a register before storing a number in it because the number being stored automatically substitutes for the existing stored number. The entire memory is, however, cleared at turn-on or if ERASE is pressed. Storing data requires use of the ➝ key. For example, pressing

1 2 . 6 ➝ A EXECUTE

stores 12.6 in the A register. Similarly, pressing

6 ➝ X EXECUTE

stores 6 in the X register, and pressing

1 9 ➝ R() 1 2 EXECUTE

stores 19 in register R12. A stored number may be viewed by using either the DISPLAY or the PRINT keys. For example, pressing

DISPLAY A EXECUTE

displays the number currently stored in A (the number remains stored in A). Similarly, pressing

PRINT R() 1 2 EXECUTE

prints the contents of R12 (the number remains stored in R12).

IMPLIED Z

In general, if a stored number is to be kept for any length of time it should not be stored into the Z register because the result of any arithmetic expression is automatically stored in Z if no other storage location is specified, thus

1 4 . 2 EXECUTE

is equivalent to

1 4 . 2 ➝ Z EXECUTE

Both expressions result in a display 14.2 which is also stored in the Z register. Similarly,

3 * 4 + 1 6 / 3 EXECUTE

is equivalent to

3 * 4 + 1 6 / 3 ➝ Z EXECUTE

A statement involving numerical activity usually contains an instruction, such as PRT, DSP, or ➝. If there is no such instruction, the form (quantity) ➝ Z; or (mathematical expression) ➝ Z, is usually automatically assumed when the line is executed or stored.

The automatic addition of Z onto the end of a statement is called the `implied store in Z`.

For instance, if the operator presses A EXECUTE to view the contents of A, the line A ➝ Z is what is actually executed. The contents of A are seen because that is the numerical quantity associated with the last assignment instruction executed in the line. Meanwhile, the contents of Z have been replaced by those of A, and are lost. The recommended procedure for viewing the contents of a register is to use the PRINT or DISPLAY statements, as they do not disturb the contents of any registers.

Because of the implied store into Z, the Z register is not recommended for storing data during calculations performed from the keyboard, except in certain situations. For instance, suppose the operator wished to add a series of numbers: n ₁ , n ₂ , n ₃ , . . .To do this, the register is first set to zero by executing the line O➝ Z. Then, the numbers are added in the following manner:

n ₁ + Z

n ₂ + Z

n ₃ + Z

Because of the implied store into Z, this is what is actually happening:

n ₁ + Z➝ Z n ₁ + 0➝Z n ₂ + Z➝ Z n ₂ + n ₁ ➝Z n ₃ + Z➝ Z n ₃ + (n ₁ + n ₂ )➝Z . . . . . .

REGISTER ARITHMETIC

Arithmetic expressions may be written using register names instead of actual numbers. When the expression is executed, the values currently stored in those registers will be automatically substituted for the register names in order to evaluate the expression. For example, assume the user has made the following storage assignments:

12.6 in A 6 in X 19 in R12

With the above values stored, the keying sequence

A + R() 1 2 - X EXECUTE

would be equivalent to the keying sequence

1 2 . 6 + 1 9 - 6 EXECUTE

Other values stored in these registers would, of course, give a difficult result for the same expression.

Numbers and register-names may be mixed in an expression, as follows:

3 * 1 2 . 6 + 4 - 6 EXECUTE

FIXED- AND FLOATING-POINT NUMBERS

Numbers can be keyed into the display and displayed in either fixed point or floating point notation. In fixed-point notation, a number appears in the display as commonly written, with the decimal point correctly located. Floating-point numbers are written with the decimal point immediately following the first digit (discounting leading zeros) and with an exponent. The exponent, which represents a positive or negative power of ten, indicates the direction, and the number of places, that the decimal point should be moved, to express the number as a fixed-point number. In the calculator the exponent may be any integer within the range -99 to +99. Examples of fixed point and floating point notation follow:

Fixed Floating ______________________________________ 1234.5 1.2345 × 10 ³ ➝ (exponent) 0.0012345 1.2345 × 10 ^-3 1.2345 1.2345 × 10 ⁰ ______________________________________

The FIXED N key selects fixed point display of displayed results. The letter N indicates that the key must be followed by one of the number keys (0 through 9) to select the number of digits to be displayed to the right of the decimal point.

The FLOAT IN key operates in the same way as FIXED N except that floating point display is selected, with N designating the required power of ten. (When the calculator is turned on, FLOAT 9 is automatically assumed). For example, the number 123.456789 in float 9 notation would be displayed as 1.23456789φEφZ. The letter E in the display indicates that the next two digits constitute the exponent. If the exponent is negative a minus signal follows the E, as illustrated below.

______________________________________ Keying Sequence Display ______________________________________ 0 0 1 2 3 4 EXECUTE 1.234φφφφφφ3 ______________________________________

No more than ten significant digits can be displayed; therefore if a number becomes too large to be properly displayed as a fixed point number, it will be automatically displayed as a floating point number. If the number becomes too small, only zeros are displayed but the number may still be seen if floating point notation is then selected.

The ENTER EXPONENT key is used to designate the E (exponent) when numbers are being keyed in floating point form, as illustrated below:

Keying Sequence Display FLOAT N 4 EXECUTE 2 . 5 6 ENTER 2 EXECUTE 2.56φφE φ2 EXP 4 . 7 3 ENTER - 2 EXECUTE 4.73φφE-φ2 EXP

RANGE OF CALCULATION

The range of the calculator is from ±10 ^{- 99} to ±9.999999999 X 10 ⁹⁹ ; when this range is exceeded during a calculation diagnostic NOTE 10 is displayed. Calculations which normally result in zero, such as subtracting a number from a number equal to itself, do not exceed the range.

OPERATING THE PRINTER

The print key is used to print both numerical values and alphameric messages (the form of a numerical printout is changed by the FIXED N and FLOAT N keys in the same way as the display is changed). This is illustrated by the following examples (in which it is assumed the FIXED N key, 2 key and EXECUTE key have previously been pressed to determine the form of the printout):

Printing Operation Keying Sequence Printout Print A Number PRINT 1 2 3 EXECUTE 123.φφ Print result of a calculation PRINT 6 + 8 / 2 EXECUTE 10.φφ Print contents of a storage register PRINT A EXECUTE (CONTENTS OF A)

To print an alphanumeric message requires the use of the quote key (") to both start and end the message (the quote symbol is not printed) as illustrated by the following example:

Keying Sequence

Print " m e s s a c e space n 0 . 2 " execute

printout

message no. 2

no more than 16 characters (including spaces) can be printed on one line of a message, and each line must be enclosed in quotes. When following the same PRINT instruction, lines must be separated by commas, as indicated below:

PRINT "--------" , "--------" EXECUTE

This prints two lines. If messages and values are to be mixed, they must be separated by a comma as illustrated by the following example in which it is assumed that the number 456 has been stored in the A register.

Print " a = " , a execute a=456.φφ

pressing the SPACE N key followed by one or more number keys designating any one of the numbers 0 through 15 causes the printer to space vertically (the number key specified in the number of lines spaced). This is illustrated by the following example: Keying Sequence Printout PRINT " D A Y S " EXECUTE DAYS SPACE N 2 EXECUTE PRINT 4 EXECUTE 4.00

When used in a message, most keys result in the character printing being the same as the character on the key. The following keys are the exceptions:

1. SPACE -- prints one blank character-space

2. GO TO -- prints

3. R() -- prints :

4. STOP -- prints !

5. ENTER -- prints↑

EXP

The following keys either cannot be used in a message or they result in some meaningless character being printed:

1. All of the half-keys at the top of the keyboard and the four blank keys in the left-hand keyblock.

2. The EXECUTE key, RUN PROGRAM key, and STORE key.

3. The JUMP key, END key, IF key, GO TO/SUB key, FLAG N key, RETURN key, and SET/CLEAR FLAG N key.

PROGRAMS

A program enables the calculator to automatically execute the keys necessary to solve a particular problem. First the program must be loaded into the calculator's memory to teach the calculator which key sequences are required and the order in which they are to be executed. Once loaded, the calculator can remember that program until a new one is loaded over it or until the calculator is switched off. A program need not be keyed into the calculator more than once because a loaded program can be recorded on magnetic cards. Recorded programs may then be loaded back into the calculator any time in the future. Once the program has been loaded, it is initialized, and then execution is commenced by actuating RUN PROGRAM key.

A complete program consists of lines of program information, each of which may be separately loaded into the calculator memory from the keyboard by actuating the STORE key when the line has been completed. An end-of-line symbol is automatically displayed at the end of each line after that line has been stored. A program line counter keeps track of which line of a program is currently being executed or is about to be executed or stored next. Before storing a line into the calculator memory, it maY be edited with the aid of the BACK, FORWARD, CLEAR, DELETE and INSERT keys. After all lines of the program have been stored, individual lines may be recalled into the display for editing or other purposes. Recall is accomplished by sequentially actuating the CLEAR and GO TO keys followed by the number keys representing the line number of the line to be recalled followed, finally, by the RECALL key. When restoring the recalled line or the edited version thereof it is only necessary to actuate the STORE key.

MAGNETIC PROGRAM CARDS

A magnetic card 16 such as that shown in FIG. 1 is used to permanently or temporarily store programs or data. The card has two sides that may be used independently to store either data or programs (however, data and programs cannot be mixed on the same side of the card). Once a recording has been made on a card-side, that card-side can be protected from erasure by tearing out a corresponding protect tab on the card. The recording on a protected card side cannot be changed.

A program loaded into the memory may be recorded on a magnetic card 16 by pressing

END EXECUTE RECORD EXECUTE

to start the card-reader motor and by then inserting an unprotected card into the card reader. The program from the card may be loaded back into the memory by first sequentially pressing the ERASE key to clear the memory, by then pressing the END, EXECUTE, LOAD and EXECUTE keys, and by thereupon inserting the card into the card reader.

THE PROGRAM LINE

Even though the lines of a program are stored in the same memory as data, the length of individual lines bears no relationship to the length of a register. The calculator simply uses however many registers are necessary to accommodate a particular line. The length of a line is determined by the programmer and depends upon the requirements of his program. However, the length is limited by machine requirements, in the same way that an individual expression is limited (see Exceeding the Length of the Display). Diagnostic NOTE 09 appears either before or after STORE is pressed, if the line is too long. When NOTE 09 appears the operator should press CLEAR and key in a completely new (shortened) line.

Line numbers are automatically assigned, by the calculator, in strict numerical sequence, beginning with line 0. The operator must known what line numbers will be assigned if there are any GO TO statements in his program. The line numbers are not strictly a part of the program because they will automatically change if the program is moved to a different location in memory. For example, suppose a program (No. 1) is a ten-line program (lines 0 through 9) and is already stored in the memory. If a second program (No. 2) is now loaded below program No. 1, then the first line of program No. 2 will be line 10, whereas, if program No. 2 had been the only program in the memory, then its first line would have been line 0. (Any GO TO statements must be corrected, by the programmer, to reflect any such line number changes.)

A line can have one or more statements, separated by semicolons. The actual number of statements on any one line is generally not significant, it being more important to have the statements in the correct order rather than on a particular line. Position of a statement does become significant where a line contains an IF statement or where a branch is to be made. In the former case, those statements which are to be conditionally executed must be on the same line as the IF statement and must come after the IF. In the latter case, a branch is always made to the beginning of a line. Therefore, the first statement to be executed after a branch must be the first statement of the line to which the branch is made. It is recommended that not too many statements be put on the one line because a short line is easier to change (once stored) than a long line.

THE DATA ENTRY STATEMENT

Program statements resulting from actuations of the ENTER key are used to halt the program during execution so that the user can key in data. The simplest statement contains only a register name, which is displayed when program execution is halted. The data keyed during the halt is stored, into the register designated, when RUN PROGRAM is subsequently pressed. For example, ENT A; results in the keyed data being stored in register A. An enter statement may contain several register names (which must be separated by commas). The program will halt for each register in turn. For example, ENT A, R13, X; is the equivalent of the three separate statements ENT A; ENT R13; ENT X;. A label (followed by a comma) may precede the register name. In this case the label will be displayed, instead of the name, when the halt occurs. For example, ENT "A = ?", A; displays A = ? and stores the subsequent data entry into register A.

BRANCHING

Program lines are normally executed in numerical sequence. However, some statements cause the sequence of execution to be changed. This is known as branching (instead of the program going to the next sequential line, it branches to some other specified line and continues program execution there). There are two kinds of branching, conditional and unconditional. Unconditional branching is accomplished with the GO TO, JUMP and GO TO SUB keys while conditional branching is done with the IF key.

There are three types of unconditional branching with GO TO. The first type is an absolute GO TO. On absolute GO TO statements take the form GO TO N, where N is an integer that refers to a particular program line. The second type is a relative GO TO. The form of the relative GO TO statement is GO TO + N or GO TO - N, where N is an integer. This means to skip forward or backward N program lines. The third type is a GO TO label. This type of GO TO statement takes the form GO TO "LABEL," where LABEL is any unique alphameric group of characters and must be enclosed in quotes. The number of characters in he label is virtually unlimited, however, the calculator will only look at the last four characters in the label. When a GO TO "LABEL" statement is executed the program will branch to a program line with "LABEL" as the first statement of that line, where LABEL has the identical last four characters as the original GO TO "LABEL" statement. If two lines have the same label branch execution will always go to the first label.

In a program, a GO TO statement causes program execution to continue with the line whose number is specified. When a GO TO statement is entered from the keyboard and followed by the RUN PROGRAM key, the GO TO statement causes program execution to start at the line whose number is specified. However, when a GO TO statement is entered from the keyboard and followed by the EXECUTE key, the GO TO statement causes the calculator to go to the line specified but not to start program execution. Any subsequent activity then depends upon the next key pressed. A line number is valid only if a currently stored program has a line identified by that number, or if it is the next higher number after the number identifying the last stored line. All other numbers are non-valid and, if used in a GO TO statement, will cause diagnostic NOTE 08 to be displayed.

JUMP allows relative branching. But, unlike the GO TO, can have a numeric constant, a register or any legitimate calculator expression as a parameter. JUMP-6 on execution would go back six lines in the program. If the contents of A were 6.23 then JUMP A would jump the integer value of A lines, or in this case 6 lines in the program. If A were 6.23 and B were 2, then JMP (A + B) would be acceptable and would jump eight lines on execution.

Often it is desirable to execute the same operations at several places in a program. One could simply repeat a group of program lines as needed, but this can be time consuming and error prone. More important, unnecessary repetition of program lines wastes memory space. The calculator has the capability to store a set of program lines once, and allow a program to execute this set of lines many times. Such a group of program lines is called a subroutine.

Once a subroutine has been written and stored in memory, execution may branch to the subroutine from a program. This is known as calling a subroutine. The program which calls the subroutine is usually referred to as the mainline program or calling program. When the subroutine execution is completed a branch is made back to the calling program and mainline execution is resumed where it was interrupted by the subroutine call. The branch from the subroutine to the mainline program is called a return. Note that if a subroutine is called in line N, the return is made to line N + 1. Branching to a subroutine is accomplished by using the GO TO SUB. GO TO SUB works almost exactly like GO TO and may branch to an absolute, relative or "LABEL" address. The difference between GO TO and GO TO SUB is that when a GO TO SUB is used for a branch, the calculator stores the line number for the return branch address. To make the return branch RETURN is stored at the end of the subroutine. The calculator itself will provide the address for the return branch.

The IF statement allows the powerful feature of conditional branching in the calculator enabling the calculator to decide whether or not to execute the succeeding statement(s) on the same line as that IF statement. The general form of the IF statement is IF followed by a condition completing the statement. (For Example, IF A - B;). The line in which the IF statement appears may be completed with any other statements. The operation will be as follows. First the condition immediately following the IF will be evaluated to check the truth of the condition. If the condition is true, the statements following the IF statement are executed, and if the condition is false, execution immediately goes to the next line. Thus, in the example given above, A = B is first computed to determine whether the contents of the A register equal the contents of the B register. If this condition is true, the rest of the line would be executed. If it is false, the rest of the line would be ignored and execution would go immediately to the next line.

The conditions in IF statements all use one of the following keys to test the relationship of any two values, registers, arithmetic expressions, or flags:

1. > (greater than)

2. ≤ (less than or equal to)

3. = (equal to)

4. ≠ (not equal to)

If the relationship is the same as that indicated by the key used an answer of true (one) will be given and if not an answer of false (zero) will be given. For example, if the contents of A and B were 2 then

A = B ➝ C

would store 1 in C,

A ≠ B ➝ C

would store 0 in C, and

A + B = A ➝ C

would store 0 in C.

Again, these can be used in any expression A + B (A = B) + AB (A≤ B) + (A + B + C) (A > B)➝ C would store 2 + 2(1) + 4(1) + 6(0) which is 8 in C.

THE STOP AND END STATEMENTS

The STOP key, used as a statement in a program or pressed while a program is running, halts program execution. STOP should be used only to abort a program (in the sense that it is no longer desired to run the program, or that it is desired to start execution again at the beginning).

The END key serves the dual purpose of halting program execution and of initializing the calculator for commencing program execution at line 0.

THE FLAGS

The calculator makes sixteen flags available to the user as selected by the FLAG N key followed by numeric keys to designate one of the flags 0 through 15. For example, actuation of the FLAG N 4 selects flag 4. Flags are used generally as part of an IF statement to enable the user to define some special condition.

The calculator terminology used to describe flags is quite simple: If a flag is raised, it is set; a set flag is considered to have the value 1. If a flag is lowered, it is cleared; a cleared flag is considered to have the value 0.

Flags are set and cleared by means of the SET/CLEAR FLAG N key. This key is actuated once to set a flag and twice to clear it. For example, a single actuation of the SET/CLEAR FLAG N key followed by the 1 and 2 number keys sets flag 12. Similarly, a double actuation of the SET/CLEAR FLAG N key followed by the 7 key cleared flag 7. Once set, a flag remains set until it is deliberately cleared. However, all flags are automatically cleared at turn-on, or when ERASE is pressed, or when an END statement is executed.

As long as no program is being executed, the state of any flag can be examined actuating the FLAG N key followed by number keys representing the flag in question followed by the EXECUTE key. The state (value) of the flag will then be displayed. Such a test will not change the state of any flag.

In addition to their normal use, flags 0 and 13 also have a special purpose. Flag 0 may be set from the keyboard while a program is actually running, by pressing the SET/CLEAR FLAG N key. Flag 13 is set automatically if the program halts for an ENTER statement and the RUN PROGRAM key is then actuated without any data being keyed.

LIST MODE

The LIST key facilitates printing by means of the calculator printing unit a program listing of an internally stored program. The listing includes the line number of each line together with an alphameric mnemonic representation of the line. An indication of the number of storage registers remaining is printed at the end of the listing.

Program listing is accomplished by first setting the program line counter to the line at which listing is to commence. This may be done by actuating the GO TO key followed by the number keys representing the line number followed by the EXECUTE key. Next, the LIST key is actuated to begin the listing operation, which will terminate at the last program line stored.

TRACE MODE

A trace mode of the calculator enables the user to obtain a printed record of its operation. The form of this printed record is a function of the type of operation in progress.

The calculator may be placed in the trace mode by actuating the TRACE key followed by the EXECUTE key or by program execution of a TRACE command. The calculator may be returned to normal mode by actuating the NORMAL key followed by the EXECUTE key or by program execution of a NORMAL command. The calculator is automatically placed in the normal mode when it is turned on.

While in the trace mode, the calculator prints a representation of each line execution from the keyboard and the results of those executed statements which produce a quantity that is considered a result. A few keys, such as CLEAR, are not printed.

The following example is illustrative of the printout obtained when the calculator is operating in the trace mode: φ➝A;φ➝B φ.φφ φ.φφ A+1➝A;B+1φ➝B φ1.φφ 1φ.φφ A+1➝A;B+1φ➝B 2.φφ 2φ.φφ PRT "A=",A, "B=", B A= 2.φφ B= 2.φφ

While running a program in the trace mode the calculator prints the line number of each line as it is executed, and below that, any quantities that were stored into registers by that line. Running a program in the trace mode may be very helpful in debugging a program by analyzing the numbers stored during the execution of the program. A program may, without alteration, be run in the trace mode simply by sequentially actuating the TRACE and EXECUTE keys before execution of the program is begun. In addition, the calculator may be placed in the trace mode during execution of any program which does not contain a NORMAL statement by simply actuating the TRACE key. It is not necessary to halt execution of the program first.

DIAGNOSTIC NOTES APPENDIX

The following diagnostic notes and associated explanations will be displayed when a particular program or operator error is detected by the calculator. NOTE φ1: In view of the preceding keys, the last key pressed does not make sense to the calculator. For example, a multiplication operator following the R () key. Note 01 is the most commonly seen note and generally occurs as soon as an incorrect key is pressed.

Note φ2: an attempt to execute an instruction which is followed by an improper value; for example, the FIX N key followed by a number larger than 9.

Taking a square root is a special case:

a. √- causes NOTE 01 when minus is pressed.

b. √(-4) or √A (where A contains a negative number) when executed cause NOTE 02 to appear.

Note φ3: statement has an extra left-hand parenthesis [(] or a missing right-hand parenthesis [)].

Note φ4: statement has an extra right-hand parenthesis [)] or a missing left-hand parenthesis [(].

Note φ5: a. Attempt to use a non-existent or unavailable R-register as a value in an expression. b. Attempt to designate a flag other than as an integer from 0 through 15. NOTE φ6: a. Attempt to store into a non-existent or unavailable R-register b. Attempt to enter a number whose exponent has an absolute value greater than 99.

Note φ7: attempt to execute a RET not preceded by a matching GSB.

Note φ8: attempt to execute a GTO followed by an invalid line number or label. Also applied to GSB and JMP.

Note φ9: a. Writing, executing or storing too long an expression or program line. b. Nesting subroutines too deeply.

Note 1φ: an intermediate or final result of a calculation exceeds the range of the calculator.

Note 11: a. Pressing any half-key in the three left-hand keyblocks when:

1. It is not part of a quote field; e.g. PRT". . . " and

2. The key is not defined by some plug-in read-only memory module.

b. Attempt to execute an ENTER statement from the keyboard instead of in a program.

Note 12: a. Storing a program line [ or loading a program or data from a magnetic card] and exceeding the memory. b. No GTO or GSB preceding LOD when loading a program (from a magnetic card) under the control of the existing program.

Note 13: attempt to record on a protected magnetic card.

Note 14: an additional card side is required when recording on, or loading from, a magnetic card. Press EXECUTE and insert the next card-side.

Note 15: appearing after a program has been loaded from a magnetic card, indicates that the calculator does not have the same ROM's installed (in the same slots) as it did when the card (or cards) was recorded. This will not affect the running of the program as long as the particular ROM's required for that program are installed in the same slots (press CLEAR and run the program in the normal way).

Recordings made when no ROM's are installed do not result in NOTE 15 when they are loaded into calculators which do have ROM's installed.

Note 16: attempt to use the printer when paper supply has been exhausted. To continue using the calculator without printer paper: If the PRINT instruction came from the keyboard, press CLEAR; if the program press STOP RUN-PROGRAM.

SYMBOLS AND MNEMONICS

The table below shows the symbols and mnemonics for the keys of the calculator as they are used both inside and outside of a quote field (some keys have two different symbolics or mnemonics under these two different conditions).

________________________________________________________ __________________ SYMBOLS AND MNEMONICS FOR THE KEYS OF THE CALCULATOR ____________________________________________________________ ______________ IN QUOTE FIELD IN QUOTE FIELD KEY NO YES KEY NO YES 1 1 1 R( ) R = 2 2 2 = = = 3 3 3 ≠ ≉ ≉ 4 4 4 > > > 5 5 5 ≤ ≤ ≤ 6 6 6 GO TO G T O b 7 7 7 GO TO SUB G S B b FOOT-NOTE 2 8 8 8 RETURN R E T b FOOT-NOTE 2 9 9 9 STOP S T P b 0 φ φ END E N D b FOOT-NOTE 2 ° ° ° JUMP J M P b FOOT-NOTE 2 ENTER EXP E IF I F b FOOT-NOTE 2 + + + FLAG IN F L G b - - - uz,28/30 SET S F G b FOOT-NOTE 2 CLEAR FLAG N * * * SET C F G b FOOT-NOTE 2 * * * CLEAR CLEAR FLAG N FLAG N / / / FIXED N F X D b FOOT-NOTE 2 √ FLOAT N F L T b FOOT-NOTE 2 ( ( ( ENTER E N T b FOOT-NOTE 2 ) ) ) DISPLAY D S P b ; ; ; PRINT P R T b FOOT-NOTE 2 , , , SPACE N S P C b FOOT-NOTE 2 " " FOOT-NOTE 1 NORMAL N O R b FOOT-NOTE 2 TRACE T R C b FOOT-NOTE 2 LOAD L O D/; FOOT-NOTE 2 s FOOT-NOTE 3 S RECORD R E C b FOOT-NOTE 2 t FOOT-NOTE 3 T A A A u FOOT-NOTE 3 U B B B v FOOT-NOTE 3 V C C C w FOOT-NOTE 3 W X X X s FOOT-NOTE 3 Y Y Y % FOOT-NOTE 3 Z Z Z & FOOT-NOTE 3 & d FOOT-NOTE 3 D . FOOT-NOTE 3 e FOOT-NOTE 3 E ? FOOT-NOTE 3 ? f FOOT-NOTE 3 F SPACE FOOT-NOTE 3 g FOOT-NOTE 3 G These keys have no Mnemonics or Symbols. H FOOT-NOTE 3 H EXECUTE -- -- I FOOT-NOTE 3 I STORE -- -- J FOOT-NOTE 3 J RUN PROGRAM -- -- K FOOT-NOTE 3 K CLEAR -- -- L FOOT-NOTE 3 L ERASE -- -- M FOOT-NOTE 3 M BACK -- -- N FOOT-NOTE 3 N FORWARD -- -- O FOOT-NOTE 3 O DELETE -- -- P FOOT-NOTE 3 P INSERT -- -- Q FOOT-NOTE 3 Q RECALL -- -- R FOOT-NOTE 3 R LIST -- -- ____________________________________________________________ ______________ 1. The " character never occurs inside a quote field; it is used exclusively to begin or terminate a quote field. 2. This key produces one character with an arbitrary pattern. Sometimes the pattern will vary according to which plug-in ROM's are installed. 3. If this key is used outside of a quote field, NOTE !! will result unless the key is defined by a plug-in ROM, in which case the mnemonic or symbol is determined by the ROM. 4. The character b denotes a blank space.

PLUG-IN READ-ONLY MEMORY MODULES

The Mathematics Plug-in Block (henceforth referred to as the Math Block) provides additional mathematical functions for the Calculator. The keyboard overlay associated with the Math Block is shown in FIG. 6. As indicated by this keyboard overlay, the additional mathematical functions provided by the Math Block include logarithms, both natural and common; exponential functions; trigonometric and inverse-trigonometric functions (in degrees, radians, or grads), and others. Use of these functions requires no special programming techniques; once the block is installed, its functions become a part of the calculator, in the same way as, for example, the square root function is part of the calculator.

The Math Block functions are quite straightforward to use; in most cases they require little explanation. The rules and hierarchy applicable to mathematical operations, as described in the calculator's operation, also apply to the operations available with the Math Block. The hierarchy, listed below, is fully discussed in the calculator's operating description.

______________________________________ First: Functions Exponentiation Unary Minus Implied Multiplication Explicit Multiplication, and Division Addition and Subtraction and Unary Plus Last: Relational Operators ______________________________________

Some plug-in blocks decrease the amount of programmable memory available to the user, by automatically requiring a portion of that memory for their own internal usage -- the Math Block has no such requirement and does not affect memory availability.

The table below described all Math Block Functions. As can be seen from the table, a `prefix` key (∇) is used to redefine certain other keys. Each key which is to be redefined must be immediately preceded by the `prefix` key -- there is no `continuous prefix` mode.

When the prefix key is pressed, a triangle appears in the display; when the next key is pressed, the lower of the two mnemonics on that key is substituted for the triangle (ASN is displayed, for example, when the sine key is pressed). The triangle cannot now be recovered by pressing the BACK key -- in effect the mnemonic for the two keys (the prefix and the next key), once generated, is treated as if it had been generated by one single key.

Reminder: If the argument of a function is negative, then the argument and its sign must be enclosed in parentheses.

SIN (-40) not SIN -40

The functions available with the mathematics plug-in read-only memory module together with syntax information and typical examples are shown in the table below (the left hand side of this table is included on the following page and the right hand side is on the next following page). ##SPC1## ##SPC2##

The calculator's User Definable Functions Accessory includes a 1024-bit plug-in ROM with three 10 key overlays shown in FIGS. 8A-C. Five keys are used for control and 25 keys are available for definition if no other plug-in ROM's are in the machine. Fifteen keys are available if one other plug-in ROM is used and five are available if both other ROM slots are used. The uses of this accessory are described below.

In a program it frequently happens that some basic calculation is needed at several different places. It is clumsy, wasteful and error prone to duplicate the necessary statements each time they are needed. It is easier and more desirable to write them once and refer to the statements as the calculation is required. This capability is provided by subroutines and functions. Here we describe the basic subroutine and function capabilities of the calculator and how they are extended with the USER DEFINABLE FUNCTIONS accessory.

The calculator has basic subroutine capabilities provided by the GO SUB and RETURN keys. These keys allow one or more lines in the main program to be called as a subroutine by jumping to the first line with the GO SUB statement and returning to the main program by executing a RETURN statement. For example, it may be necessary to set the first ten R register to zeros at several places in the program. This job can be accomplished with the following program using a subroutine labeled "ZERO" as follows:

0: GO SUB "ZERO" . . . Program 20: GO SUB "ZERO" with three . calls to "ZERO" . . 35: GO SUB "ZERO" . . . 40: "ZERO" 41: 10 ➝ Z Subroutine 42: Z - 1 ➝ Z; 0➝RZ; IF Z>0 GTO +0 zero 43: RETURN

The calls to "ZERO" from lines 0, 20 and 35 cause the ten R registers to be cleared before returning to lines 1, 21, and 36, respectively. The usage of subroutine "ZERO" clearly saves space since the code in lines 41 through 43 need not be duplicated. In addition, as the program is segmented into subroutines it becomes easier to read and understand. If the subroutine is useful to others, it may be incorporated in their programs.

In the simple example, subroutine "ZERO" always does exactly the same job: setting the first ten R registers to zero. A more general subroutine would have the capability to set any ten consecutive R registers to zeros starting at R(J). To accomplish this, the subroutine must be altered and the value of the parameter J must be known by (or passed to) the subroutine. This value could be stored in the X register before calling the subroutine and the program could be changed as follows: 0: 0➝X; GO SUB "ZERO 1" . . . 20: 40➝X; GO SUB "ZERO 1" . . . 35: 30➝X; GO SUB "ZERO 1" . . 40: "ZERO 1" 41: 10 ➝ Z 42: Z - 1 ➝ Z; 0 ➝ R(X+Z), if Z>0 GTO + 0 43: RETURN

The subroutine "ZERO 1" clears R registers 0-9, 40-49 and 30-39 in lines 0, 20 and 35, respectively. The programmer must be careful, however, since the subroutine uses both the X and Z registers. These registers must be saved if they contain valued information when the subroutine is called. This bookkeeping complicates using the subroutine and makes is less attractive and more conducive to errors. The problems become even worse as more parameters must be passed to the subroutine and as more working registers, such as Z, must be made available. These problems are circumvented by using advanced features found in the USER DEFINABLE FUNCTION ROM.

In addition the USER DEFINABLE ROM includes the concept of a function. A function differs from a subroutine in that the name of a function has a value associated with it. Therefore, function names can appear in any arithmetic expression to reference the value associated with the functions such as the names A, B, C, X, Y, Z, and R are used for registers. For example,

SIN, COS, LN and EXP

are functions which have values associated with their names and

SIN (LN A) - COS (EXP B)➝X

is a valid arithemtic statement containing several functions.

While some standard functions are built in to the calculator, it is desirable to be able to define other functions and have them work in the same manner that the functions sin, cos, ln, exp, etc. work. For example, if a solution of a problem required hyperbolic functions, it would be desirable to define the functions and write statements like

SINH (A + B) - COSH (A - B)➝X

The problems encountered in defining functions are similar to those of writing subroutines. Parameters of functions (arguments) must be known by or passed to the function and the working registers must be made available to the function so temporary results may be stored during the calculations. Defining functions differ from defining subroutines in that the value must be assigned to the function. The USER DEFINABLE FUNCTION block provides capabilities to solve these problems.

The option block has key arrangements as shown i FIGS. 8A-C. Keys FA, FB, FC, FD and FE are assignable to any five subroutines or functions. GA through GJ and HA through HJ are also assignable in the absence of one or two other ROM blocks, thus extending the capacity to 15 or 25 functions or subroutines. The remaining five keys facilitate defining and calling these functions and subroutines.

Subroutines and functions that are defined with the USER DEFINABLE FUNCTION block are similar in structure to the main program: each routine is a list of one or more statements, numbered from zero, followed by an END. To define a simple subroutine to calculate the volume of a sphere and assign this subroutine to the FA key. First press

GTO FA EXECUTE

This places the machine in define subroutine mode related to key FA. Any other assignable key could be used in place of FA. Next, to define the subroutine for calculating the volume, STORE

0: 4/3*πzzz➝z

1: end

storing the END returns the machine to the normal mode of operation. To use this subroutine to calculate the volume of a sphere with radius 5, press

5; FA EXECUTE

which is equivalent to

5➝Z; GSB FA EXECUTE

The Z register is displayed. To call the subroutine from a program STORE

3: 5➝z; gsb fa

the five control keys (left keys of FIG. 8A) extend these basic subroutine capabilities to include immediate execute as well as parameter passing and function subprograms. These keys are described below.

IMMEDIATE EXECUTE. The immediate execute key (displayed as IEX) is used in making the calculator respond immediately to the depression of a key without pressing EXECUTE. The IEX must be the first statement of the subroutine for the key to respond in this manner. When the key associated with such a subroutine is depressed, the routine is executed without pressing EXECUTE. For example, if the previous program was changed to

0: IEX

1: 4/3*πzzz z

2: end

then merely press

5 FA

to invoke the routine. This specialized execution mode is valuable in simplifying keyboard operation to increase efficiency and productivity when moving similar calculations must be made from the keyboard.

CALL. To call a subroutine with parameters the CLL must be used. This key is used to indicate that a list of parameters will follow the subroutine name. Otherwise, the key is used exactly as GSB key. That is,

Gsb fa (no parameters)

Cll fa (a, 5, b + x) (parameters)

The CLL statement should be the last statement of a line. The parameters need not be enclosed in parentheses.

PARAMETER. The P() or parameter key is used to access parameters that are being passed to subroutines and functions and is probably the most heavily used key of this ROM block. In addition to accessing parameters, the P() key may be used to create and access memory that is used temporarily as working registers while the subroutine is being executed. Accessing parameters and working registers is done with the P() key without affecting the A, B, C, X, Y, Z, or R registers.

The P() key is used exactly like the R() key but it references a sequence of parameters registers instead of the R registers. For example, if a subroutine FB is called with three parameters, P1 references the first parameters, P2 references the second, etc. That is, ##SPC3##

In this CLL, P1 references the A register, P2 and P3 reference memory locations where 5 and the value of X-B are stored temporarily during the execution of subroutine FB. The calculation of X-B is made and placed in a temproary location each time the CLL statement is executed before executing subroutine FB.

Temporary working registers may be created and accessed by using the P() key with subscripts higher in value than the number of parameters being passed. For example, subroutine fB had three parameters (P1, P2, P3). P4, P5, etc. could be used as working registers. Obviously, the number of such registers is limited since the calculator will run out of internal temproary storage eventually. An exact limit cannot be given since it is dependent on the availability of memory when the subroutine is initiated.

As the first example, consider rewriting subroutine "ZERO 1" to zero the specified ten R registers without destroying the value of the X or Z registers as the previous routine did. One parameter P1 must be passed replacing X and one working register P2 is used in place of Z. The necessary statements follow.

______________________________________ PRESS GTO FA EXECUTE STORE 0: "ZERO 1" 1: 10➝P2 2: P2-1➝P2; 0➝R (P1 + P2); IF P2>0 GTO+0 3: END ______________________________________

Then, CLL of the form

40➝X; GO SUB "ZERO 1"

are replaced pressing

Cll fa 4 0 store

which is displayed as

20: CLL ZERO 1 40

since the subroutine is started with the label "ZERO 1." The new routine operates as prescribed without destroying the values of either register X or Z freeing them for other purposes.

Another example is a routine to increment a register. The one parameter of this subroutine specifies the register to be incremented:

PRESS GTO FC EXECUTE STORE 0: "INCR" 1: P1+1➝P1 2: END

Incr may be called by

10: CLL INCR A

to increment the A register of

20: CLL INCR R(A + B)

to increment the R register specified by A + B. This example shows that a parameter may be used to return a result as well as access a value. Any number of parameters may be used in calling a subroutine.

DEFINE. A function differs from a subroutine in that it has a value associated with its name and, therefore, can be part of an expression. The DEF/➝F key allows functions to be defined in the calculator. The key has two uses as its label indicates. First, it is used to place the machine in function definition mode DEF. Secondly, once the calculator is in function definition mode, it is used to assign a value to the function ➝F.

To place the calculator in function definition mode,

Press def fa execute

this is analogous to placing the machine in subroutine definition mode; that is pressing

GTO FA EXECUTE.

After placing the machine in function definition mode, the function is defined exactly as a subroutine with parameters except the ➝F allows a value to be assigned to the function.

As an example consider writing a function to define the hyperbolic sin function.

sinH X = e ^x - e ^-x /2

as the FD key. First, to place the calculator in function definition mode,

Press def fd execute

to define the sinh function,

STORE 0: "SINH" 1: (EXP P1 - EXP(-P1) )/2➝F 2: END

To use the function, the FD key is referenced just like the SIN key. For example,

PRESS FD (5 ) + FD (4 ) EXECUTE

which is displayed as

SINH (5 ) + SINH (4 )

before EXECUTE is pressed since the definition begins with the label "SINH." Similarly,

5: SINH (A + B ) / SINH (A - B ) ➝A

can be stored as a program line. The machine truly behaves as if it had a "built in" capability to calculate hyperbolic sines.

As a second example, the maximum value function is programmed. This function has two parameters and is assigned the value of the larger of the two parameters. First,

PRESS DEF FE EXECUTE and STORE 0: "MAX" 1: P1➝F 2: IF P2>P1 P2➝F 3: END

Notice that P1 is assumed to be the larger of the two parameters in line 1, and line 2 makes a correction if this is not the case. This function can be used to calculate and store the product of two maximum values as follows:

Max (6, 9 ) max ( -5, -4 ) ➝ra

or

Max (ab - c, 5) max (z↑3, 5 - a)➝rc

performing similar operations without using this function capability would require several registers to store intermediate results and would be very hard to read and understand in comparison.

SCRATCH. The SCR is used for several functions. Its primary use is to delete a user defined subroutine or function from memory to allow a key to be used for other programs or to increase the amount of memory available for the main program. To delete function FA,

Press scr fa execute

to delete two (or more),

Press scr fb, fc execute

special functions of this key included recording and loading of programs. To record all programs in memory in the order stored,

Press gto scr; rec execute

to load these programs,

Press gto scr; lod execute

to record one function or subroutine per one half card, place one subroutine or function in the machine and

Press gto fa (or other key defined); rec execute

similarly, to configure a machine from a library created in this manner, order the functions and subroutines and PRESS

Gto fa;φlod execute

gto fb; lod execute

etc.

to list function FA,

Press gto fa list

the ability to configure the calculator in this manner makes it possible to customize the calculator from one problem to the next without reprogramming, entering and debugging the functions and subroutines needed. This ability combined with the capability of the calculator to modify the keyboard with a variety of plug-in ROMS allows versatility never before found in a calculator.

In summary, the USER DEFINABLE FUNCTIONS ROM for the calculator greatly extends the capabilities of the calculator. It has been shown how the block is used to write general purpose subroutines and functions. These routines communicate with the main program by parameter passing and allow working registers within the subroutine to be established and accessed. These features allow the user to define routines that do not require or destroy the content of the A, B, C, X, Y, Z and R registers. Therefore, the programmer is relieved of all the bookkeeping that is associated with calling a subroutine when parameters must be placed in specified registers; these registers usually have to be saved before storing parameters and restored after calling the subroutine. The programs written with this required bookkeeping become clumsy, obscure, hard to debug, and in general discourages the use of subroutines and functions.

Another advantage of the USER DEFINABLE FUNCTIONS ROM is its ability to define functions (subroutines that have a value associated with their names such as SIN and LN) that exactly imitate the behavior of the built in functions of the calculator. This allows the capabilities of the machine to be extended naturally when a problem that is based on different functions is encountered. The option block also alloww a library of general purpose subroutines and functions to be established and used easily. This ability greatly emancipates the programmer by allowing him to borrow something written by another with a minimum of effort.

In general, the USER DEFINABLE FUNCTIONS extend the capabilities of the calculator to make the machine easier and more natural to program. It may be the user's most valuable addition to the calculator.

The Peripheral Control I accessory includes a 1024 bit addition to the read-only memory and keyboard overlay, as shown in FIG. 7, to identify the ten keys associated with this accessory. Of these ten keys five are for the operation of a X-Y plotter, two for typewriter and the remaining three for general control of both input and output peripherals. A description of these 10 keys follow. First the five plotter keys.

SCALE. This key allows the user to scale the physical limits of the X-Y plotter to any units he desires. The syntax for this key is as follows:

SCL X _min , X _max , Y _min , Y _max

The four limits after the SCL follow the rules of any parameter list in the calculator. After SCL is executed all communication with the X-Y plotter may be in the ranges specified by the scale statement. An example: if the user were going to plot Y = 8 sinX for -2 × 2 and with a range for Y of -10 Y 10 he would specify:

SCL -2π, 2π, -10, 10

(this same example will be used in other key descriptions

AXES. This key allows the user to draw both X and Y axes on his plot with one instruction. The syntax is as follows:

AXE X _o , Y _o , ΔX, ΔY

Here X _o , Y _o specifys the values on the scaled plot in user units where the axes will cross. The optional X and Y specify the distance between tic marks on the X and Y axes respectively. These tic marks will be generated starting from the origin. For the example cited previously:

AXE 0, 0, ρ/4, .1

PEN UP. This instruction is used without parameters and instructs the X-Y plotter to raise the marking pen off of the paper staying in the same X, Y location.

LETTER. This instruction with its parameter list sets up the X-Y plotter for plotting alphameric characters. The syntax follows:

LTR X, Y, hwθ

Here X, Y specifies the X, Y location, in user units, of the lower left hand corner of the first alpharmeric character to be plotted. hwθ is a three digit number that specifies the size of the letters and the direction of lettering on the plot. The h is a digit in the range 1≤h≤9 which specifies the alphameric character height. The actual height is .64th percent of full scale (i.e. Y _max - Y _min if plotted horizontally). Similarly w is a digit in the range 1≤w≤9 which specifies the alphameric character width. The actual width is .64w percent of full scale (i.e. X _max - X _min if plotter horizontally). The θ must fall in the range 1≤θ≤4. 1 allows plotting horizontally left to right, 2 is vertically bottom to top (right reading), 3 horizontally right to left (up-side-down) and 4 is vertically top to bottom (left reading). To set up a lable for the example specified above:

LTR π/2, 8, 321

the actual plotting of the alphameric characters is accomplished with the plot key described below.

PLOT. Plot does three things, allows point plotting, alphameric label plotting and numeric results plotting.

PLT X, Y

The above syntax is used for point plotting. It must have two parameters which have the same limitations as other calculator parameters. If the X-Y plotter pen is up on execution of this statement it will remain up, the pen will travel to the X, Y location specified then the pen will go down to the paper. If the pen is down on execution of the statement it will remain down as it travels to the X, Y location, thereby drawing a line from the old location to the one specified. To plot the sin curve in our previous example assuming the register X is our variable X then we could scale, draw axes and plot with a program shown below.

0: TBL 2 (set calculator to radians)

1: SCL -2π, 2π, -10, 10

2: axe 0, 0, π/4, .1

3: -2π ➝ x

4: plt x, 10 sin X

5: .1 + x➝x

6: if x≤ 2π; gto 4

plot is used to plot alphameric labels with a single parameter enclosed in quotes.

PLT "(Alphameric Label)"

To continue our program from above and plot a heading on it would require a letter statement and a plot statement.

7: LTR π/2, 8, 321

8: plt " sin × vs. x "

the final syntax for plot is:

PLT (numeric or arithmetic expression)

Where again we only have one parameter. On execution this will plot the numeric or value of the arithmetic expression in the format specified by the FIXED N or FLOAT N keys on the calculator. To extend our example program to plot a label for the left most X axes tic mark.

9: FXD 3

10: ltr -2π, -1, 211

11: plt -2π

this would give at the location -2π, -1:

-6.283

This concludes the description of the five plotter keys. Next the two typewriter keys.

FORMAT. This key allows specification of a format for alphameric character output. It is of the form:

FMT Spec 1, Spec 2 . . . Spec n

Where Spec 1 etc. are either conversion specifications for converting the internal calculator floating point numbers to a desired output form or edit specifications which allow location manipulation, alphameric outputs and control of special typewriter commands.

Conversion specifications have three forms:

r FLT w.d Floating point number (w≤ d + 7)

r FXD w.d Fixed point number

r FXD w.o Integer without decimal point

In these cases r specifies the number of times the conversion specification will be repeated. FLT or FXD comes from depression of the FLOAT N or FIXED N keys on the calculator. The w specifies the total field width for this output and d the number of digits to the right of the decimal point. r, w and d must be integer numerics.

Editing specifications may include the following:

nX

Which specifies a blank field of n characters. n must be an integer, X is the X key on the calculator.

r/

Specifies r carriage return, line feeds to the typewriter. r must be an integer, / is the / (divide) key on the calculator keyboard.

Normally a carriage return, line feed is given automatically at the end of each FMT statement. If the calculator key Z is included as a specification in the FMT the automatic carriage return, line feed is suppressed.

r "(alphameric label & typewriter control)"

In this r again is an integer specifying the number of times this specification will be repeated. Inside the quotes may be used a variety of calculator keys to allow outputting to the typewriter the following:

Upper case alphabet

Lower case alphabet

Special symbols

$ % & ' ? space / * - + . ,

() : .about. > < = # !

Special controls

Red ribbon, black ribbon, back space, tab, line feed, carriage return, clear all tabs, set tab

The key assignments for these characters and controls for the calculator keyboard are shown in FIG. 11. To accommodate all of these symbols on the limited number of keys it is necessary to use the shift key. This is the normal DISPLAY key. When used in a quote field it gives the special symbol in the display. The shift key is a toggle type. The entry to a quote field always sets the keyboard to upper case (unshifted) then on each encounter with after that the keyboard mode is toggled between upper case (unshifted) and lower case (shifted). For example, to output Bill Hewlett on the typewriter would require a program line as follows:

FMT "B ILL H EWLETT"; TYP

TYPE. The FMT sets up the actual output specification but does not specify the actual output. To do this requires the TYPE key. This is followed by a parameter list where parameters are numerics, registers or expressions. On execution of the TYP first, the last encountered FMT is found. The FMT specifications are sequentially scanned left to right, starting at extreme left, outputting edit specifications to the typewriter until the 1st conversion specification (or all specifications executed) is found. Then the first parameter in the TYP statement is evaluated and this is outputted with first conversion specification of the FMT. Scanning of FMT specifications then continues, outputting edit specifications until the next conversion specifications is found. Then again we go to the TYP parameter list and evaluate the second parameter and output to the typewriter with this conversion. This process continues until either the end of FMT specifications or the end of the TYP parameters is reached.

If the end of the FMT specifications is reached before the end of TYP a carriage return, line feed is given and the process described above continues starting with the beginning of the FMT specifications again.

If the end of FMT is reached at the same time the TYP parameter list is depleted then carriage return, line feed is given and the calculator program continues with the next statement.

If after finding a conversion specification in the FMT and there is no corresponding TYP parameter (end of parameter list) a carriage return, line feed is given an execution of the program continues with the next statement. In this case the next TYP will start again with the first FMT specification, not where it discontinues previously.

Any time a conversion specification cannot accommodate the number to be outputted first, an attempt will be made to go to floating point 9maintaining the same w.d) if it still overflows the field will be filled with dollar signs.

The following example will illustrate the TYP with FMT. To output a trig table as shown below:

TRIGONOMETRIC TABLE ______________________________________ DEGREES SIN COS TAN ______________________________________ 0 0.000 1.000 0.000 1 .018 1.000 .016 2 .035 .999 .035 . . 89 1.000 .018 57.29 90 1.000 0.000 $$$$$$$ ______________________________________

Use a program as shown:

0: SFG 14; TBL 1

1: fmt 5x, "trigonometric table", /

2: typ

3: fmt "degrees sin cos tan", /

4: typ

5: 0➝x

6: fmt fxd 6.0, 2 fxd 8.3, 2x, fxd 7.3, /

7: typ sin x, cos x, tan x

8: 1 + x➝x

9: if x≤ 90; gto 7

10: stp

there is a default option with the TYP statement if no FMT is specified. This default has four features.

The first is, the setting specified by the calculator FIXED N or FLOAT N keys is assumed for outputting data.

The second, four fields of 18 characters each are assumed for field width specifications across the page.

The third, the parameter list of the TYP statement may now include label parameters, i.e. "(Alphameric Label)." These will be outputted in the 18 character fields. These labels may only include the unshifted (upper case) characters. They will use as many 18 character fields as necessary.

The final feature is, all outputs are right justified in the 18 character fields.

The following examples will illustrate: TYP " HEADING " HEADING ______________________________________ 1➝A; 2➝B; 3➝C; FXD 0 TYP A, B, C 1 2 3 FXD 2 TYP "X=", 1.345 X= 1.35 ______________________________________

The final 3 keys of this accessory are described now. These are for general peripheral control. They use the concept of select codes. The select code is a number assigned to a particular peripheral to identify it. A digitizor may be select code 3, a paper tape punch select code 13, etc. Select code will be designated by SC. Usually this can be a number, register or arithmetic expression. When evaluated the integer value will be used.

WRITE. This key is the output key and like TYP is used with the FMT key. It does not have the default option as the TYP. It's description is identical to the TYP key with these exceptions. In this case the peripheral to be outputted to must be identified by SC. This must be the first parameter in the WRT parameter list. The actual outputs out of the calculator are ASCII codes. How they are interpreted is determined by the peripheral itself. For example, the teletype interpretation of the keyboard keys is shown in FIG. 12.

READ. This allows data input from external peripherals. The syntax is:

RED SC, A, B, R12

The first parameter must be the select code of the inputting peripheral. The following parameters must be register names that specify registers to accept the inputted data. On execution the calculator will send instructions to turn on the peripheral device and then standby for ASCII characters coming in. It will accept the characters 0-9 . , / - + E (enter exponent) and any other characters except leading spaces and one space following the enter exponent will be interpreted as delimiters and cause the number inputted to be stored in the register specified. The sequence is repeated for each register in the parameter list.

TRANSFER. This key is used to transfer directly from one external peripheral to another.

TFR SC ₁ , SC2

This does a direct transfer from the peripheral with SC ₁ to the peripheral with SC ₂ (e.g. a paper tape reader to a typewriter). The transfer is initiated when the TFR is executed and terminates on transferring an 8 bit code of 00 000 011.

BASIC INSTRUCTION SET

Every routine and subroutine of the calculator comprises a sequence of one or more of 71 basic sixteen-bit instructions listed below. These 71 instructions are all implemented serially by the micro-processor in a time period which varies according to the specific instruction, to whether or not it is indirect, and to whether or not the skip condition has been met.

Upon completion of the execution of each instruction, the program counter (P register) has been incremented by one except for instructions JMP, JSM, and the skip instructions in which the skip condition has been met. The M-register is left with contents identical to the P-register. The contents of the addressed memory location and the A and B registers are left unchanged unless specified otherwise.

Memory Reference Group

The 14 memory reference instructions refer to a specific address in memory determined by the address field (m ), by the ZERO/CURRENT page bit, and by the DIRECT/INDIRECT bit. Page addressing and indirect addressing are both described in detail in the reference manuals for the Hewlett-Packard Model 2116 computer (hereinafter referred to as the HP 2116).

The address field (m) is a 10 bit field consisting of bits 0 through 9. The ZERO/CURRENT page bit is bit 10 and the DIRECT/INDIRECT bit is bit 15, except for reference to the A or B register in which case bit 8 becomes the DIRECT/INDIRECT bit. An indirect reference is denoted by a (, I) following the address (m).

REGISTER REFERENCE OF A OR B REGISTER: If the location (A) or (B) is used in place of (m) for any memory reference instruction, the instruction will treat the contents of A or B exactly as it would the contents of location (m). See the note below on the special restriction for direct register reference of A or B.

Ada--m,I Add to A. The contents of the addressed memory location m are added (binary add) to contents of the A register, and the sum remains in the A register. If carry occurs from bit 15, the E register is loaded with 0001, otherwise E is left unchanged.

Adb--m,I Add to B. Otherwise identical to ADA.

Cpa--m,I Compare to A and skip if unequal. The contents of the addressed memory location are compared with the contents of the A register. If the two 16-bit words are different, the next instruction is skipped; that is, the P and M registers are advanced by two instead of one. Otherwise, the next instruction will be executed in normal sequence.

Cpb--m,I Compare to B and skip is unequal. Otherwise identical to CPA.

Lda--m,I Load into A. The A register is loaded with the contents of the addressed memory location.

Ldb--m,I Load into B. The B register is loaded with the contents of the addressed memory location.

Sta--m,I Store A. The contents of the A register are stored into the addressed memory location. The previous contents of the addressed memory location are lost.

Stb--m,I Store B. Otherwise identical to STA.

Ior--m,I "Inclusive OR" to A. The contents of the addressed location are combined with the contents of the A register as an "INCLUSIVE OR" logic operation.

Isz--m,I Increment and Skip if Zero. The ISZ instruction adds ONE to the contents of the addressed memory location. If the result of this operation is ZERO, the next instruction is skipped; that is, the P and M registers are advanced by TWO instead of ONE. The incremental value is written back into the addressed memory location. Use of ISZ with the A or B register is limited to indirect reference; see footnote on restrictions.

And--m,I LOgical "AND" to A. The contents of the addressed location are combined with the contents of the A register as an "AND" logic operation.

Dsz--m,I Decrement and Skip if Zero. The DSZ instruction subtracts ONE from the contents of the addressed memory location. If the result of this operation is zero, the next instruction is skipped. The decremented value is written back into the addressed memory location. Use of DSZ with the A or B register is limited to indirect reference; see footnote on restrictions.

Jsm--m,I Jump to Subroutine. The JSM instruction permits jumping to a subroutine in either ROM or R/W memory. The contents of the P register is stored at the address contained in location 1777 (stack pointer). The contents of the stack pointer is incremented by one, and both M and P are loaded with the referenced memory location.

Jmp--m,I Jump. This instruction transfers control to the contents of the addressed location. That is, the referenced memory location is loaded into both M and P registers, effecting a jump to that location.

Shift-Rotate Group

The eight shift-rotate instructions all contain a 4 bit variable shift field (n) which permits a shift of one through 16 bits; that is, 1 ≤ n ≤ 16. If (n) is omitted, the shift will be treated as a one bit shift. The shift code appearing in bits 8,7,6,5 is the binary code for n - 1, except for SAL and SBL, in which cases the complementary code for n - 1 is used.

Aar-- n--Arithmetic right shift of A. The A register is shifted right n places with the sign bit (bit 15) filling all vacated bit positions. That is, The n + 1 most significant bits become equal to the sign bit.

Arb--n--Arithmetic right shift of B. Otherwise identical to AAR.

Sar--n-- Shift A right. The A register is shifted right n places with all vacated bit positions cleared. That is, the n most significant bits become equal to zero.

Sbr--n-- Shift B right. Otherwise identical to SAR.

Sal--n-- Shift A left. The A register is shifted left n places with the n least significant bits equal to zero.

Sbl-- n--Shift B left. Otherwise identical to SAL.

Rar-- n--Rotate A right. The A register is rotated right n places, with bit 0 rotated around to bit 15.

Rbr-- n--Rotate B right. Otherwise identical to RAR.

Alter-Skip Group

The sixteen alter-skip instructions all contain a 5-bit variable skip field (n) which, upon meeting the skip condition, permits a relative branch to any one of 32 locations. Bits 9, 8, 7, 6, 5 are coded for positive or negative relative branching in which the number (n) is the number to be added to the current address, (skip in forward direction), and the number (-n) is the number to be subtracted from the current address, (skip in negative direction). If (n) is omitted, it will be interpreted as a ONE.

______________________________________ (n)= 0 CODE=00000 REPEAT SAME INSTRUCTION (n)= 1 CODE=00001 DO NEXT INSTRUCTION (n)= 2 CODE=00010 SKIP ONE INSTRUCTION (n)= 15 CODE=01111 ADD 15 TO ADDRESS (n)= -1 CODE=11111 DO PREVIOUS INSTRUCTION (n)= -16 CODE=10000 SUBTRACT 16 FROM ADDRESS (n)= nothing CODE=00001 DO NEXT INSTRUCTION ______________________________________

The alter bits consist of bits 10 and bits 4. The letter (S) following the instruction places a ONE in bit 10 which causes the tested bit to be set after the test. Similarly the letter (C) will place a ONE in bit 4 to clear the test bit. If both a set and clear bit are given, the set will take precedence. Alter bits do not apply to SZA, SZB, SIA, and SIB.

Sza-- n--Skip if A zero. If all 16 bits on the A register are zero, skip to location defined by n.

Szb-- n--Skip if B zero. Otherwise identical to SZA.

Rza-- n--Skip if A not zero. This is a "Reverse Sense" skip of SZA.

Rzb-- n--Skip if B not zero. Otherwise identical to RZA.

Sia --n-- Skip if A zero; then increment A. The A register is tested for zero, then incremented by one. If all 16 bits of A were zero before incrementing, skip to location defined by n.

Sib-- n--Skip if B zero; then increment B. Otherwise identical to SIA.

Ria-- n--Skip if A not zero; then increment A. This is a "Reverse Sense" skip of SIA.

Rib-- n--Skip if B not zero; then increment B. Otherwise identical to RIA.

Sla-- n,S/C Skip if Least Significant bit of A is zero. If the least significant bit (bit 0) of the A register is zero, skip to location defined by n. If either S or C is present, the test bit is altered accordingly after test.

Slb--n, S/C Skip if Least Significant bit of B is zero. Otherwise identical to SLA.

Sam--n, S/C Skip if A is Minus. If the sign bit (bit 15) of the A register is a ONE, skip to location defined by n. If either S or C is present, bit 15 is altered after the test.

Sbm--n, S/C Skip if B is Minus. Otherwise identical to SAM.

Sap--n, S/C Skip if A is Positive. If the sign bit (bit 15) of the A register is a ZERO, skip to location defined by n. If either S or C is present, bit 15 is altered after the test.

Sbp--n, S/C Skip if B is Positive. Otherwise identical to SAP.

Ses--n, S/C Skip if Least Significant bit of E is Set. If bit O of the E register is a ONE, skip to location defined by n. If either S or C is present, the entire E register is set or cleared respectively.

Sec-- n,S/C Skip if Least Significant bit of E is Clear. If bit O of the E register is a ZERO, skip to location defined by n. If either S or C is present, the entire E register is set or cleared respectively.

Complement-Execute-DMA Group.

These seven instructions include complement operations and several special-purpose instructions chosen to speed up printing and extended memory operations.

Cma--complement A. The A register is replaced by its One's complement.

Cmb--complement B. The B register is replaced by its One's complement.

Tca--two's Complement A. The A register is replaced by its One's Complement and incremented by one.

Tcb--two's complement B. The B register is replaced by its One's Complement and incremented by one.

Exa--execute A. The contents of the A register are treated as the current instruction, and executed in the normal manner. The A register is left unchanged unless the instruction code causes A to be altered.

Exb--execute B. Otherwise identical to EXA.

Dma--direct Memory Access. The DMA control in Extended Memory is enabled by setting the indirect bit in M and giving a WTM instruction. The next ROM clock transfers A➝M and the following two cycles transfer B➝M. ROM clock then remains inhibited until released by DMA control.

Note: Special Restriction for Direct Register Reference of A or B

For the five register reference instructions which involve a write operation during execution, a register reference to A or B must be restricted to an INDIRECT reference. These instructions are STA, STB, ISZ, DSZ, and JSM. A DIRECT register reference to A or B with these instructions may result in program modification. (This is different from the hp 2116 in which a memory reference to the A or B register is treated as a reference to locations 0 or 1 respectively.) A reference to location 0 or 1 will actually refer to locations 0 or 1 in Read Only Memory.

Input/Output Group (IOG)

The eleven IOG instructions, when given with a select code, are used for the purpose of checking flags, setting or clearing flag and control flip-flops, and transferring data between the A/B registers and the I/O register.

Stf (sc)--set the flag. Set the flag flip-flop of the channel indicated by select code (SC).

Clf (sc)--clear the flag flip-flop of the channel indicated by select code (SC).

Sfc (sc)--skip if flag clear. If the flag flip-flop is clear in the channel indicated by (SC), skip the next instruction.

Sfs (sc) h/c--skip if flag set. If the flag flip-flop is set in the channel indicated by (SC), skip the next instruction. H/C indicates if the flag flip-flop should be held or cleared after executing SFS.

Clc (sc) h/c--clear control. Clear the control flip-flop in the channel indicated by (SC). H/C indicates if the flag flip-flop should be held or cleared after executing CLC.

Stc (sc) h/c--set Control. Set the control flip-flop in the channel indicated by (SC). H/C indicates if the flag flip-flop should be held or cleared after executing STC.

Ot* (sc) h/c--output A or B. Sixteen bits from the A/B register are output to the I/O register. H/C allows holding or clearing the flag flop after execution of OT*. The different select codes allow different functions to take place after loading the I/O register.

Sc = 00--data from the A or B register is output eight bits at a time for each OT* instruction given. The A or B register is rotated right eight bits.

Sc = 01--the I/O register is loaded with 16 bits from the A/B registers.

Sc = 02--data from the A/B register is output one bit at a time for each OT* instruction for the purpose of giving data to the Magnetic Card Reader. The I/O register is unchanged.

Sc = 04--the I/O register is loaded with 16 bits from the A/B register and the control flip flop for the printer is then set.

Sc = 08--the I/O register is loaded with 16 bits from the A/B register and the control flip flop for the display is then set.

Sc = 16--the I/O register is loaded with 16 bits from the A/B register and then data in the I/O register is transferred to the switch latches.

Li* (01) h/c--load into A or B. Load 16 bits of data into the A/B register from the I/O register. H/C allows holding or clearing the flag flop after L1* has been executed.

Li* (00)--the least significant 8 bits or the I/O register are loaded into the most significant locations in the A or B register.

Mi* (01) h/c--merge into A or B. Merge 16 bits of data into the A/B register from the I/O register by "inclusive or." H/C allows holding or clearing the flag flop after M1* has been executed.

Mi* (00)--the least significant 8 bits of the I/O register are combined by inclusive OR with the least significant 8 bits of the A or B register, and rotated to the most significant bit locations of the A or B register.

MAC Instruction Group

A total of 16 MAC instructions are available for operation

a. with the whole floating-point data (like transfer, shifts, etc), or

b. with two floating-point data words to speed up digit and word loops in arithmetic routines.

Note: (a ₀ -3) means: contents of A-register bit 0 to 3

Ar 1 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1744 to 1747 (octal)

Ar 2 is a mnemonix for arithmetic pseudo-register located in R/W memory on addresses 1754 to 1757 (octal)

D _i means: mantissas i-th decimal digit; most significant digit is D1, least significant digit is D12, decimal point is located between D1 and D2

Every operation with mantissa means BCD-coded decimal operation.

Ret--return

16-bit-number stored at highest occupied address in stack is transferred to P- and M-registers. Stack pointer (=next free address in stack) is decremented by one.

(A), (B), (E) unchanged.

Mov--move overflow

The contents of E-register is transferred to A ₀ -3. Rest of A-register and E-register are filled by zeros.

(B) unchanged.

Clr--clear a floating-point data register in R/W memory on location (A)

Zero➝ (a), (a) + 1, (a) + 2, (a) + 3

(a), (b), (e) unchanged

XFR Floating-point data transfer in R/W memory from location

(A) to location (B).

Routine starts with exponent word transfer.

Data on location (A) is unchanged.

(E) unchanged.

Mrx--ar1 mantissa is shifted to right n-times. Exponent word remains unchanged.

(B ₀ -3) = n (binary coded)

lst shift: (A ₀ -3)➝D ₁ ; D _i ➝D _{i +1} ; D ₁₂ is lost

jth shift: θ ➝ D ₁ ; D _i ➝D _{i +1} ; D ₁₂ is lost

nth shift: θ ➝ D ₁ ; D _i ➝D _{i +1} ; D ₁₂ ➝A ₀ -3 θ ➝ E, A ₄ -15

each shift: (B ₀ -3) - 1 ➝ B ₀ -3

(b ₄ -15) unchanged

Mry--ar2 mantissa is shifted to right n-times. Otherwise identical to MRX

Mls--ar2 mantissa is shifted to left once. Exponent word remains unchanged.

θ ➝ D ₁₂ ; D _i ➝ D _{i -1} ; D ₁ ➝ A ₀ -3

(b) unchanged

Drs--ar1 mantissa is shifted to right once Exponent word remains unchanged

θ ➝ D ₁ ; D _i ➝ D _{i +1} ; D ₁₂ ➝ A ₀ -3

Zero ➝ e and A ₄ -15

(b) unchanged

Dls--ar1 mantissa is shifted to left once. Exponent word remains unchanged.

(A ₀ -3) ➝ D ₁₂ ; D _i ➝ D _{i -1} ; D ₁ ➝ A ₀ -3

θ ➝ e, a ₄ -15

(b) unchanged

Fxa--fixed-point addition

Mantissas in pseudo-registers AR2 and AR1 are added together and result is placed into AR2. Both exponent words remain unchanged. When overflow occurs "0001" is set into E-reg., in opposite case (E) will be zero.

(AR2) + (AR1) + DC ➝ AR2

Dc = θ if (E) was 0000 before routine execution

Dc = 1 if (E) was 1111 before routine execution

(B), (AR1) unchanged

Rmp--fast multiply

Mantissas in pseudo-registers AR2 and AR1 are added together (B ₀ -3)-times and result is placed into AR2. Total decimal overflow is placed to A ₀ -3. Both exponent words remain unchanged.

(AR2) + (AR1) * (B ₀ -3) + DC ➝ AR2

Dc = 0 if (E) was 0000 before routine execution

Dc = 1 if (E) was 1111 before routine execution

Zero ➝ e, a ₄ -15

(ar1) unchanged

Fdv--fast divide

Mantissas in pseudo-registers AR2 and AR1 are added together so many times until first decimal overflow occurs. Result is placed into AR2. Both exponent words remain unchanged. Each addition without overflow causes +1 increment of (B).

1st addition: (AR2) + (AR1) + DC ➝ AR2

Dc = 0 if (E) was 0000 before routine execution

Dc = 1 if (E) was 1111 before routine execution next additions: (AR2) + (AR1) ➝ AR2

Zero ➝ e

(ar1) unchanged

Cmx--10's complement of AR1 mantissa is placed back to AR1, and ZERO is set into E-register. Exponent word remains unchanged

(B) unchanged

Cmy--10's complement of AR2 mantissa.

Otherwise identical to CMY

Mdi--mantissa decimal increment.

Mantissa on location (A) is incremented by decimal ONE on D ₁₂ level, result is placed back into the same location, and zero is set into E-reg.

Exponent word is unchanged.

When overflow occurs, result mantissa will be

1, 000 0000 0000 (dec)

and 0001 (bin) will be set into E-reg.

(B) unchanged.

Nrm--normalization

Mantissa in pseudo-register AR2 is rotated to the left to get D ₁ ≠ 0. Number of these 4-bit left shifts is stored in B ₀ -3 in binary form ((B ₄ -15)=0)

When (B ₀ -3) = 0,1,2, . . . , 11 (dec) ➝ (E) = 0000 When (B ₀ -3) = 12 (dec) ➝ mantissa is zero, and (E) = 0001

Exponent word remains unchanged

(A) unchanged.

The binary codes of all of the above instructions are listed in the following coding table, where * implies the A or B register, D/I means direct/indirect, A/B means A register/B register, Z/C means zero page (base page) (current page, H/S means hold test bit/set test bit, and H/C means hold test bit/clear test bit. D/I, A/B, Z/C, H/S, and H/C are all coded as O/l. ##SPC4##

DETAILED LISTING OF ROUTINES AND SUBROUTINES OF BASIC INSTRUCTIONS

A complete listing of all of the routines and subroutines of basic instructions employed by the calculator and of all of the constants employed by these routines and subroutines is given below. All of these routines, subroutines, and constants are stored either in the basic ROM or in the plug-in ROM modules employed therewith. Each page of each different group of routines, subroutines, and constants is numbered at the top left-hand corner of the page, and each line of each page is separately numbered in the first column from the left-hand side of the page. This facilitates reference to different parts of the listing. Descriptive headings are also provided throughout the listing to identify routines, subroutines, groups of constants, different portions of the ROM, the plug-in ROM modules, etc. Each instruction of each routine or subroutine and each constant stored in the ROM or plug-in ROM modules is represented in octal form by six digits in the third column from the left-hand side of the page, and the address of the ROM location in which each such instruction or constant is stored is represented in octal form by five digits in the second column from the left-hand side of the page.

Mnemonic labels serving as symbolic addresses or names are given in the fourth column from the left-hand side of the page for most of the constants and many of the instructions to facilitate references to these constants and instructions and associated instructions. The mnemonic code of each basic instruction and of each pseudo instruction is given in the fifth column from the left-hand side of the page. As noted above, each basic instruction is employed as a step in a routine or subroutine of one or more basic instructions and therefore has an address in the ROM. Psuedo instructions such as ORG, EQU, etc. which appear (and are recognizable as not being one of the 71 basic machine instructions listed above) are used for control of the Assembler, which translates the symbolic/mnemonic coding of the fourth, fifth, and sixth columns into the address and contents of ROM registers shich appear in the second and third columns. (See chapter 4 of the Hewlett-Packard "Assembler Programmer's Reference Manual" of April, 1970.) They are not employed as steps in the routines and subroutines performed by the calculator and therefore have no addresses in the ROM. Mnemonic operand codes are given in the sixth column from the left-hand side of the page, and descriptive comments are given to the right of the sixth solumn. The format, assembly, and use of the listing is explained in greater detail in the above-mentioned Hewlett-Packard "Assembler Programmer's Reference Manual." ##SPC5## ##SPC6## ##SPC7## ##SPC8## ##SPC9## ##SPC10## ##SPC11## ##SPC12## ##SPC13## ##SPC14## ##SPC15## ##SPC16## ##SPC17## ##SPC18## ##SPC19## ##SPC20## ##SPC21## ##SPC22## ##SPC23## ##SPC24## ##SPC25## ##SPC26## ##SPC27## ##SPC28## ##SPC29## ##SPC30## ##SPC31## ##SPC32## ##SPC33## ##SPC34## ##SPC35## ##SPC36## ##SPC37## ##SPC38## ##SPC39## ##SPC40## ##SPC41## ##SPC42## ##SPC43## ##SPC44## ##SPC45## ##SPC46## ##SPC47## ##SPC48## ##SPC49## ##SPC50## ##SPC51## ##SPC52## ##SPC53## ##SPC54## ##SPC55## ##SPC56## ##SPC57## ##SPC58## ##SPC59## ##SPC60## ##SPC61## ##SPC62## ##SPC63## ##SPC64## ##SPC65## ##SPC66## ##SPC67## ##SPC68## ##SPC69## ##SPC70## ##SPC71## ##SPC72## ##SPC73## ##SPC74## ##SPC75## ##SPC76## ##SPC77## ##SPC78## ##SPC79## ##SPC80## ##SPC81## ##SPC82## ##SPC83## ##SPC84## ##SPC85## ##SPC86## ##SPC87## ##SPC88## ##SPC89## ##SPC90## ##SPC91## ##SPC92## ##SPC93## ##SPC94## ##SPC95## ##SPC96## ##SPC97## ##SPC98## ##SPC99## ##SPC100## ##SPC101## ##SPC102## ##SPC103## ##SPC104## ##SPC105## ##SPC106## ##SPC107## ##SPC108## ##SPC109## ##SPC110## ##SPC111## ##SPC112## ##SPC113## ##SPC114## ##SPC115## ##SPC116## ##SPC117## ##SPC118## ##SPC119## ##SPC120## ##SPC121## ##SPC122## ##SPC123## ##SPC124## ##SPC125## ##SPC126## ##SPC127## ##SPC128## ##SPC129## ##SPC130## ##SPC131## ##SPC132## ##SPC133## ##SPC134## ##SPC135## ##SPC136## ##SPC137## ##SPC138## ##SPC139## ##SPC140## ##SPC141## ##SPC142## ##SPC143## ##SPC144## ##SPC145## ##SPC146## ##SPC147## ##SPC148## ##SPC149## ##SPC150## ##SPC151## ##SPC152## ##SPC153## ##SPC154## ##SPC155## ##SPC156## ##SPC157## ##SPC158## ##SPC159## ##SPC160## ##SPC161## ##SPC162## ##SPC163## ##SPC164## ##SPC165## ##SPC166## ##SPC167## ##SPC168## ##SPC169## ##SPC170## ##SPC171## ##SPC172## ##SPC173## ##SPC174## ##SPC175## ##SPC176## ##SPC177## ##SPC178## ##SPC179## ##SPC180## ##SPC181## ##SPC182## ##SPC183## ##SPC184## ##SPC185## ##SPC186## ##SPC187## ##SPC188## ##SPC189## ##SPC190## ##SPC191## ##SPC192## ##SPC193## ##SPC194## ##SPC195## ##SPC196## ##SPC197## ##SPC198## ##SPC199## ##SPC200## ##SPC201## ##SPC202## ##SPC203## ##SPC204## ##SPC205## ##SPC206## ##SPC207## ##SPC208## ##SPC209## ##SPC210## ##SPC211## ##SPC212## ##SPC213## ##SPC214## ##SPC215## ##SPC216## ##SPC217## ##SPC218## ##SPC219## ##SPC220## ##SPC221## ##SPC222## ##SPC223## ##SPC224## ##SPC225## ##SPC226## ##SPC227## ##SPC228## ##SPC229## ##SPC230## ##SPC231## ##SPC232## ##SPC233## ##SPC234##

##SPC235## ##SPC236## ##SPC237## ##SPC238## ##SPC239## ##SPC240## ##SPC241## ##SPC242## ##SPC243## ##SPC244## ##SPC245## ##SPC246## ##SPC247## ##SPC248## ##SPC249## ##SPC250## ##SPC251## ##SPC252## ##SPC253## ##SPC254## ##SPC255## ##SPC256## ##SPC257## ##SPC258## ##SPC259## ##SPC260## ##SPC261## ##SPC262## ##SPC263## ##SPC264## ##SPC265## ##SPC266## ##SPC267## ##SPC268## ##SPC269## ##SPC270## ##SPC271## ##SPC272## ##SPC273## ##SPC274## ##SPC275## ##SPC276## ##SPC277## ##SPC278## ##SPC279## ##SPC280## ##SPC281## ##SPC282## ##SPC283## ##SPC284## ##SPC285## ##SPC286## ##SPC287## ##SPC288## ##SPC289##

MICROPROCESSOR

All of the above-listed routines and subroutines of basic instructions are implemented by the basic computing system shown in FIGS. 3A-B. Central control of this system is achieved by microprocessor 120. As shown in the block diagram of FIG. 34 and in the detailed schematic diagram of FIGS. 35A-D, the microprocessor comprises a bipolar ROM 300 including seven ROM chips organized into 256 words of 28 bits. Eight J-K flip-flops contain the ROM address; (i.e. a 4-bit primary address and a 4-bit secondary address). A single chip 16-bit data selector permits any one of 16 different qualifier lines to be tested with a 4-bit qualifier code. This 4-bit qualifier code ROM chip serves a dual function in that it provides a complementing code to the 4 primary address flip-flops as well as selecting the proper qualifier to be tested. If branching in any ROM state is desired, the microinstruction BRC must also be given, BRC occurring with a QN (qualifier not met) signal from the data selector will cause the least significant bit of the address code to be inhibited to the secondary address flip-flop, thus causing the address to "branch" according to the state of the qualifier.

An additional feature of this ROM organization is the IQN microinstruction (inhibit if qualifier not met). When the IQN is given and the qualifier selected by the qualifier code is not met, the signal CCO (clock code zero) goes low. This inhibits all shift clock pulses from the clock decoder which in effect prevents execution of microinstructions in that ROM state.

To minimize the ROM word length, two 3-to-8 line decoders are used to expand 3 R-code outputs and 3 X-code outputs into a total of 14 microinstructions. Also the SCO and SCI outputs from ROM No. 5 are decoded in the Memory. The ALU code outputs AC0, AC1, and AC2 are treated as address inputs to the ALU ROM and therefore need no decoding.

The microprocessor is responsible for the following:

1. Issuing a four-bit clock code to the clock decoder during each ROM state.

2. Issuing microinstructions to the memory, including the read and write microinstructions.

3. Issuing microinstructions to the shift registers for gating serial data into or out of the proper registers.

4. Issuing a four-bit ALU code to the Arith Logic Unit to select the proper binary or BCD arithmetic function.

5. Performing logical decisions (branching) based on the states of 16 qualifier inputs to the microprocessor.

6. Issuing next address information to the ROM address flip-flops in the microprocessor.

7. Transferring control to the input/output controller via the I/O strobe for execution of input or output instructions.

The full set of 28 ROM outputs with their associated microinstructions, the list of 16 qualifiers and assigned codes, and the microprocessor mnemonics are contained in the following tables: ##SPC290##

MICROPROCESSOR MNEMONICS Clock Signals ______________________________________ MCK Memory Clock SCK Shift Clock XTC External Clock RCF ROM Clock for Flip Flops RCA ROM Clock for Address Flip Flops IIC Inhibit Internal Clock INH Inhibit Clock IPS Inhibit ROM Clock (Also primary and secondary Flip Flop) CC8 CC4 CC2 Clock Code: Binary Code that programs the number CC1 of shift clocks CCφ Inhibits Shift Clocks Address Mnemonics POP Power on Preset IQN Inhibit if Qualifier not met BRC Branch Q-Register TQR Transfer Q11, Q12, Q13, Q14 to primary addr. Flip Flops TTQ T-Bus to Q-Register QTR Q-Register to R-Bus Q10 Q9 Q8 Q7 Q6 Bits 1φ- φ of Q-Register Q5 Q4 Q3 Q2 Q1 Qφ Data Qualifiers QPφ Bit φ of P-Register QRD Qualifier ROM Disable (I/O interupt) QNR Qualifier No Request (Keyboard Interupt) QDC Decimal Carry QBC Binary Carry Memory SCφ S-Bus Code SCI TTT T-Bus to T-Register TTM T-Bus to M-Register RDM Read Memory WTM Write Memory A, B, P E- Registers QAB Q-Register to AB Flip Flop AB = φ A-Register Operation AB = φ B-Register Operation TTX (ROM) T-Bus to A or B Register (Originates at ROM Decoder) XTR A or B Register to R-Bus TTP T-Bus to P-Register PTR P-Registers to R-Bus TBE T-Bus to E-Register to R-Bus TRE T-Register to E-Register UTR Units to R-Bus AC2 AC1 Arithmetic Codes for Arithmetic ACφ Logic Unit BCD Decimal Arithmetic SDR Disables ROMs for Single Step Tester Operation

Each of the ROM chips of FIGS. 34 and 35A-D is organized into 256 words of 4 bits each constructed in accordance with the following table, where each "L" represents a low (or "0") state and each "H" represents a high or ("1") state:

ROM CHIP 3 ____________________________________________________________ ______________ φφ12 2φ53,φ9,1,4,φ1φ24 φφ13 ROM3 φφ14 φ2,11,71 φφ15 414 φφ16 φφφ-φφ7 LLLL LLHL HHHH LHHL HHHH LHHH HHLH HHLH φφ17 φφ8-φ15 LHLL LHLL HLHH HLLH HLHL LHLH LLLL LLLL φφ18 φ16-φ23 LHHH LHHH LLLL LHHH LLLL LLLL LHLL HHLL φφ19 φ24-φ31 LLHL LLHL LHLH HLHL LHLL HLHL LLLL LLLL φφ2φ φ32-φ39 LHLL LLLL HHLL LLLL HLLL HLLL LLHL HLLH φφ21 φ4φ-φ47 LLHH LLHH LLLL LLLL LHLH HLLL HHLH LHHH φφ22 φ48-φ55 HLLL HHLL LLLH LLLH LHHL LLLH HLHH HLHH φφ23 φ56-φ63 LLLH LLLH HHLL LHLH LLLH HHLH HLHH LHLL φφ24 φ64-φ71 LHHL LHHH HLHH HHHL LLLL HLLL LHHL HLHH φφ25 φ72-φ79 LLLH LLLH LHLL LHLL HLLL LLHL LLLL HLLH φφ26 φ8φ-φ87 LHHH LHLH HLLL LHHL HLHH HHLL LLLL LLLL φφ27 φ88-φ95 LLHH LLLL HHHH LHHH LLLL LLHH LLLL LHLL φφ28 φ96-1φ3 HHHL HLLL LHHL LHHH LHHH LHHH LHHH HHHH φφ29 1φ4-111 LLHH LLHL LHLL LLLL LLLL LHLH HHLL HHLL φφ3φ 112-119 LLLH LLLH LLLL LHLH LHLH LHLH HLLH LHHH φφ31 12φ-127 LLLL LHLH HHHH LHHL LLLH LHLL LLLL LHLH φφ32 128-135 HLHL LHLL HHLL LHLH LHHH HLHH LLLL LLLL φφ33 136-143 LHLH LLHL LLHH HHLH LLHL HLHL HLLH LHLL φφ34 144-151 LLLL LLHL HLLH HLLL HLLH LLLH HLLH HLLH φφ35 152-159 HHHL LHHH HLHH HLLH LLLH LLLL LHHH HHLH φφ36 16φ-167 HLLL HHHL LLLH HHHL LHHH LLHL LLHL HHHH φφ37 168-175 LHHL HLLL LHLL HLHL LLLL LLLH LHLL HLLL φφ38 176-183 LLLL LHHL LLHL HLLH LHHH LLHH HLHH HLHH φφ39 184-191 LHHH HLLL LLHL LLHL LHLH LLLL LLHL LLLL φφ4φ

192-199 LLLH LLLL LLLH LLLH HHLH HHLH LLHH HLHH φφ41 2φφ-2φ7 HHHH LHLH HLLH LHLL HHLH LHLH LLLL LLLL φφ42 2φ8-215 HLHH HLLL LHHL LLLH HHHL LLHL HLHL HLHL φφ43 216-223 HHHH HHLH LLLL LLLL LLLL LHLL LLLH HLLH φφ44 224-231 HLLH HLLH LLLL LLLL HHLH HLLL LHHL HHHL φφ45 232-239 LLLL HHHL HLLL HLLH HHLL HLHL LLLL LHHH φφ46 24φ-247 LLHL LLHL LLHH LLLL LLLH HHLH LLHL LHLL φφ47 248-255 LHLL LHLH HLLL LHHH LLLL LLLL LHLH LLLL φφ48 ____________________________________________________________ ______________

ROM CHIP 4 ____________________________________________________________ ______________ φφ49 2φ54,φ9,1,4,φ1φ24 φφ5φ ROM4 φφ51 φ2,11,71 φφ52 441 φφ53 φφφ-φφ7 HLHL HLLH LLLH HLLL LHHL HLLL HLHH LLHH φφ54 φφ8-φ15 LHHH HHLH HLLL HLLL HLLH LHHL HLLL LHHH φφ55 φ16-φ23 HLLL LLHH LLHL LLLL HLHH HLLH LLLL LLLH φφ56 φ24-φ31 LLLL LLLL HLHL LLHL LLLL LLLH LHLL LHHH φφ57 φ32-φ39 LHLH HLLH HLLL HLHH LHLH HHLH HHLL HLLL φφ58 φ4φ-φ47 LLLL LLLL HHLH HHLL HHLH HHLL HLLH HLHL φφ59 φ48-φ55 HHHH LLHH LLLL HLLL LLLL HLHH HHLL LHLL φφ6φ φ56-φ63 LLLH LLLH HHHL HHHL LLLL HLLL HLHL LLLL φφ61 φ64-φ71 LLLH HHLH HHLH HLLL HLHL LLLL HHHH HLHH φφ62 φ72-φ79 LLLL LLLL HLHL LLHL LLHH HLLL LHLH LLHH φφ63 φ8φ-φ87 HHHL HLHH HLHL HLLL LLLL HHLH LHLL LLLH φφ64 φ88-φ95 HLLL LHLH HHHL HHLL LHHH LHLL HLLL LLLL φφ65 φ96-1φ3 HHHL HLHH HLLL HLHL HHHH HHLL HHHL LLHL φφ66 1φ4-111 LLLL LLLL LHLL LLHL HLLL LLLL HLHL LLHH φφ67 112-119 LHHH LHLH HLLL HLLL LLHH HLHH HHHH LHLL φφ68 12φ-127 LLHL HHHH HLLL HLHH LHLL HLLH HLLH HHHL φφ69 128-135 LLLH HLHH LHHL HLHH HLHH HLLH HLHH LLHH φφ7φ 136-143 HLLH LHLL HLHL LLHH LLLL HHHH LLLL HLLH φφ71 144-151 HLHL HLHL HLLL HLLH HLHH LHLL HHLL HHLL φφ72 152-159 HLLL HLLH HLHL HHHH LLLL HLLL HLHL LHLL φφ73 16φ-167 LLLH HHHL HHHL LLHH HHHL HLHH HHHH HHHL φφ74 168-175 HLLL HHLH LHLL HLLL HLLL LLLL LLHL LLLH φφ75 176-183 HHLL HLLH HLLH HLLL HHHH HLLL HHLL LHLL φφ76 184-191 HLLL LLHH LHLL HHLL LLHH HLLL LHLH LHHH φφ77

192-199 LHHL HLLH LLLL HLLL HLHH HLLL HHHL HHHL φφ78 2φφ-2φ7 LLHL HHHH HHHL HHHL LLHH LLLH HLLL LHHH φφ79 2φ8-215 LHHH HLLL HLLL LLLH HLHL LLLH LHLL LHHL φφ8φ 216-223 LLHL HLHL HLHL LLHL HLLL LLLL LLLL HLHL φφ81 224-231 HLLL HLLH LHHL HHLL HLLL LHLL LHLL LHHH φφ82 232-239 HHLL LLHH LLHL LHLH LHHH LLLL HLLL LLHH φφ83 24φ-247 HHLL LHLL LLHH HLLL HLLL HLHH LHLL LHLL φφ84 248-255 LLHH HHLH LLLH LLLL HHLL HHLH LHLL HLLL φφ85 ____________________________________________________________ ______________

ROM CHIP 5 ____________________________________________________________ ______________ φφ86 2φ55,09,1,φ1φ24 φφ87 ROM5 φφ88 φ2,11,71 φφ89 515 φφ9φ φφφ-φφ7 HHHH LLLL LLLL HHHH LLLL LLLL LLLH LLLH φφ91 φφ8-φ15 HHHH LLLL HLLH LLLL HHHH HHHH LLLL LLHH φφ92 φ16-φ23 LLLL LLLL LLLL LLHH LLLL HHHH HLHH LLLL φφ93 φ24-φ31 LLHH LLHH LLLL LHLH LLHH LHLH HLHH HLHH φφ94 φ32-φ39 HHHH LLLL LLLL LLLL HLHH HLHH HHHL LLLL φφ95 φ4φ-φ47 LHHH LHHH LLLL LLLL LLHH HLHH LLLL LLLH φφ96 φ48-φ55 LHLH HLHH LLLL HHHH LLLL LLLL LLLL LLLL φφ97 φ56-φ63 LLLH LLLH LLHH LLHH LLLL HLHH HHHH HHHH φφ98 φ64-φ71 HHHH HLHH LLHH LLLL LLLH LLLL LLLL LHLH φφ99 φ72-φ79 HHHH LLLH HHHH LLLL HHHH HHHH LLLH HHHL φ1φφ φ8φ-φ87 LLLL LLLL HLHH LLLL HHHH HHHH HHHH HHHH φ1φ1 φ88-φ95 LHHH LLLL LLLH LLLL LHLL LLHH LLHL HHLL φ1φ2 φ96-1φ3 HHHH HLHH HLHH HLHH LLHH HLHH LLLL LLLH φ1φ3 1φ4-111 LLLL LLHH HHHH HHHH HLHH HHHH HHHH LLLL φ1φ4 112-119 HHHH HLHH HHHL LLLL LLHL LLLL LLHH LLLL φ1φ5 12φ-127 HLHH LLLL LLHH HLHH LLHH HHLH LLLL HHHH φ1φ6 128-135 HHHH LHLH HHHH LLLL LLLH LLHH LLLL LLLL φ1φ7 136-143 HHHH HHHH LHLH HLHH HLHH HLHH LLLL LLLH φ1φ8 144-151 LLLL LLHH HLHH LLHH LLLL HHHL LLLL HHHL φ1φ9 152-159 LLLL LLLL LLLL LHLL HHHH HLHH LLHH LHLL φ11φ 16φ-167 HHHH HHHH LHLH LLHL HHHH LLLL HHHH LLLH φ111 168-175 HHHH HHHH HHHH LLLL HHHH HHHH HHHH LHLL φ112 176-183 HHHH LHLH HHHH HHHH LLLL LLHL HHHL LLLL φ113 184-191 HHHH HLHH LHLH LHLH HHHH HLHH LLHH LLHH φ114

192-199 HHHH HLHH HHHH HHHH LHLH HLHH LHLH LHLH φ115 2φφ-2φ7 LLLL HHHL HHHH LLLH HHHH LLLL HLHH HHHH φ116 2φ8-215 HHHH LLHH HLHH HHHH LLHH HHHH LLLL HHHH φ117 216-223 LLLL HLHH LLLL LLLL HLLH LHLH LHLH LLLL φ118 224-231 LLLL LLLL LLLL HHHL HLHH HLHH LLHL LLLL φ119 232-239 HHHH LLLL HLHH HHHH LLLL LLLL HHHL HHHL φ12φ 24φ-247 LLHH LLLL LHLL LLLH HHHH HHHH HLLH LHLH φ121 248-255 HHHH LLLL HLHH LLHH HHHH LLLL HHHH HHHH φ122 ____________________________________________________________ ______________

ROM CHIP 6 ____________________________________________________________ ______________ φ123 2φ56,φ 9,2,4,φ1φ24 φ124 ROM6 φ125 φ2,11,71 φ126 595 φ127 φφφ-φφ7 LHHL LHHH HHHL LLHH HHHL HLHH HHHL HHHL φ128 φφ8-φ15 LLHL LLHH LLHH LHLH LHLH LHLL LHHH LHLH φ129 φ16-φ23 LHHH LHHH LHHH LHHL LLLH LHHL LHHH LHHH φ13φ φφ24-φ31 HHHH HLHH LLHH LLLH LHLH LLLH LHHH LHHH φ131 φ32- φ39 LLLL LHHH LHHH LHHH LHLH LHHH LHHL HHHH φ132 φ4φ-φ47 HHHH HLHH HHHH HLHH HLHH LHLH LHHH HHHL φ133 φ48-φ55 LLLH LHLH LHHH LHLL LHHH LLLH LLHH LLHH φ134 φ56-φ63 HHHH HLHH LHHH LHHH LHHH LLHH LHLH LLLH φ135 φ64-φ71 LLHH LHHL LHHH LHHH LHHL LHLH HLHH LLLH φ136 φ72-φ79 LHHH HLHL LHHL LHHH LHLH LHHL LLHL LHHH φ137 φ8φ-φ87 LHHH LHHH LLHH HHHL LHHH LHHL LHLH LHHH φ138 φ88-φ95 HLHL HLHL LLHH LHHH LHHH LHHL LLHH LHHH φ139 φ96-1φ3 LLHL LHHH LHHH LHHL LHLH LHHL LHHH HHHL φ14φ 1φ4-111 LLHH HLHL LHHH LLHL LLHH LHHL LHLH LHHH φ141 112-119 LHLL LHHH LHHL LHLH LLLH LHHH HHLH LHHH φ142 12φ-127 LHLH HLHH LHLL LHHH LHHH LHHH LHLH LHHH φ143 128-135 LLHL LHHH LHHL LHHH LHLH LHHH LHLH LHLH φ144 136-143 LHHL LLHH LLLH LHLH LHLH LHHH LHHH LLLH φ145 144-151 LHHH LHHH LLLH LHLL LHHH LHHH LLHH HHHL φ146 152-159 HLHL HHHL LHHH LHHH LHHH LLHH LHHH LLHH φ147 16φ-167 LHLL LLLL LLLH LLHH LHHH LLHH LHLH LLHH φ148 168-175 LLLL LLHL LHHH LHHH LHHH LHLH LHHH LHHH φ149 176-183 LHHH LHHH LHLH LHLH LHLH LLHH LHHL LHHH φ15φ 184-191 LLHL LLHH LHHH LHHH LHLH LHHH LHHH LLHH φ151

192-199 LHLH LLHH LHLH LHHH LHLH LHHH LLLH LLLH φ152 2φφ-2φ7 HLLH HHHL LHHL LHHH LHHL LHHH LHLH LHHH φ153 2φ8-215 LHLH LHLL LHLH LHLH HHHH LHLH LHHH LHHH φ154 216-223 HLHH LHHH LHHH LHHH LLHH LHHH LHLH LLHH φ155 224-231 HLHH HHHL LHHH LHHH LLHH LHLH LHHH HLHH φ156 232-239 HLLL LHHH LLLH LLHH LLLH LHHH LLHH LHHH φ157 24φ-247 LHLL LHHH LHLH LLLH LHLL LHLH LLHH LLLH φ158 248-255 LLHL LHHH LHHH LHLL LHLH LHLH LHHH LHHH φ159 ____________________________________________________________ ______________

ROM CHIP 7 ____________________________________________________________ ______________ φ16φ 2φ57,φ9,1,4,φ1φ24 φ161 ROM7 φ162 φ2,11,71 φ163 596 φ164 φφφ-φφ7 LHHH HHHH LLLL LLLH LLLL HHHH LHHH LHHH φ165 φφ8-φ15 LLLH HLLH HHHH HHHH LLHL LHHH LHHH LHLH φ166 φ16-φ23 LHLL LHLL LHHH LHHH LHHH LHHH LLHH LHHH φ167 φ24-φ31 LHHH LLLL LHHH LHHH LLHL LHHH LHHH LLHH φ168 φ32-φ39 LHHH LHHH LHLL HHHH LLLL LHHH LHHH HHHH φ169 φ4φ-φ47 LHHH LLLL LHHH LLLL HHHH HHHL HHLH LHLL φ17φ φ48-φ55 LHHH LHHL LHHH LHHH LHLH LHHH LHHH LLLL φ171 φ56-φ63 LHHH LLLL LHHH LLLL LHHH HHHL HLHL LLLL φ172 φ64-φ71 LHHH HHHH LHHH HHHH LHHH LHLL HLLL HHHH φ173 φ72-φ79 LLLH LHHH LHHH LHHH LHLL LHHH LHHH LHHH φ174 φ8φ-φ87 LHLL HHLL HHHL HHHH LHHH LHLL LLLL LLLL φ175 φ88-φ95 LHHH LHHH LHHH LHHH LHLL LHHH LHHH LHHH φ176 φ96-1φ3 LHHH HHHL HLHH HHHH HHHH HHHH HHLL LHHH φ177 1φ4-111 LLLH LHHH LLLL LHHH LLHH LHHH HLLL LHHH φ178 112-119 LHHH LHHL LHHH LHHH LHHH LHHH LHHH LHHH φ179 12φ-127 LHHH HLLL LHHH LLHH LLLL LHHH LHLL LHHH φ18φ 128-135 LHHH HLLL LHHH HHHH HHHH HHHH LLLL LHHH φ181 136-143 HHHH LHHH LHHH LLHH LHHL LHHL LHHH HLLL φ182 144-151 LLLL HHHH HLHH HHHH HHHH LHHH LLLL HHHH φ183 152-159 LLLH LHLL HHHH LHLH LHHH LLHH HHHH HLLL φ184 16φ-167 LHHH LHHH LHHH LLLL LLLL HLLH LHLL HHHH φ185 168-175 LLLH LHHH LHLL HHHH LLLL LHLL LHLL LHLL φ186 176-183 LLLL HHHH LLLL LLLL LLLH HLLH LHHH LHHH φ187 184-191 LLLH LHHL LHHH LHHH LHLH LHHL LHLH LLLL φ188

192-199 LLLL HHHL LLLL LHHH HHHH HHHH HHHH HHHH φ189 2φφ-2φ7 LLLH HHHH LHLH HLLL LHHH LHHH LLHH LLLL φ19φ 2φ8-215 LHHH HHHH HLHH LHLL HHHH LLHL LHHH LHHH φ191 216-223 LLLH HLHH LLLH LLLH LLLL LHHH LHHH HHHH φ192 224-231 HLLL HHHH LHHH LHLL HHHL LLHH LLLL LHHH φ193 232-239 HHHH LHHH LLHH LLLL LHHH LHLH LHHH LHHH φ194 24φ-247 LHHH LHHH LLLL LLLL HHHH LLHL LLLH LHHH φ195 248-255 LHHH HHHH LLHH LHHH HHHH HLLH LHHH LHHH φ196 ____________________________________________________________ ______________

ROM CHIP 8 ____________________________________________________________ ______________ φ197 2φ58,φ9,1,4,φ1φ24 φ198 ROM8 φ199 φ2,11,71 φ2φφ 733 φ2φ1 φφφ-φφ7 LHHH HHHL HHHL HHHL HHHL HLHL LLHL LLHH φ2φ2 φφ8-φ15 HHHL HHHL HHHL HHHH HHHL LHHL LHHL HHHH φ2φ3 φ16-φ23 HHHL HHHL HHHL LHHH HHHH LHHH LHLL LHLL φ2φ4 φ24-φ31 LHHL LHHL HHHH HHHH HHHL HHHH HHHL HHHL φ2φ5 φ32-φ39 HHHL LHHL HHLH HHHL HHHH HHHL HHHL LHHL φ2φ6 φ4φ-φ47 LHHL LHHL LHHL LHHL HLHL HHHH HHHL HHHL φ2φ7 φ48-φ55 HHHH HHHH HHHL LHHL HHHL HHHH HHHH HHHH φ2φ8 φ56-φ63 LHHL LHHL HLHH HHHH HHHL LHLH HLHL HHHL φ2φ9 φ64-φ71 LHHL HHHL HLHH HHHL HHHH HHHL LHHL HHHH φ21φ φ72-φ79 HHHL HHHL LHHH HHHL LLLH LHHH HHHH HHHH φ211 φ8φ-φ87 HHHL HHHL HHHH HHHL HHHH HHHH LHHL LHLH φ212 φ88-φ95 HHHL HHHL HHHL HHHL HHHL LHHH HHHH HHHH φ213 φ96-1φ3 HHHL LHLL HHHL HHHL LHHL HHHL HHHL LLHL φ214 1φ4-111 HHHL HHHL HHHH HHHL LHLH LHHH LLLL LHLL φ215 112-119 HHHH HHHL LHHH HHHH HLHH HHHL HLHL HHHL φ216 12φ-127 LHHL LHHL HLHL LHLL HHHH HHHL HHHL HHHH φ217 128-135 LHHL HHHH LHHH HHHL HHHL HLHL HHHH HHHH φ218 136-143 HHHH LHHL HHHH LHLH HHHH HHHL HHHH LLHL φ219 144-151 HHHH HLHH HHHH HHHL HLLL HHHH LHHL HHHL φ22φ152-159 HHHL HHHL HHHL HHHL HHHH HHHH HLHL HHHL φ221 16φ-167 LHHL HHLL HHHH HHHH HHHH HHHH LHLL HHHL φ222 168-175 HHHL HHHL HHLH HLLL HHHH HHHH HHLH HHHL φ223 176-183 HHHH LHLL HHLL HHLL HHHH HHHL HHHL HHHL φ224 184-191 HHHL HHHH HHHL HHHL HHLL HHHL HHHL HLLL φ225 192-199 LLLL

HHHH HHHL HHHH HLHL HLLL HLHH HLHH φ226 2φφ-2φ7 HLHL HHHL HHHH HHHH HHHH HHHL HHHH HHHH φ227 2φ8-215 HHLH HHHL HHHH HHHL HLHH HLHL LHLL LHLH φ228 216-223 HLHL HHHL HHHH HHHH HHHL HHHL HHHL HHHH φ229 224-231 HHHL LHHH LLLL HHLH HHHH LHLH HHHH HHHH φ23φ 232-239 LHHL HHHL HHHH LLLL HHHH HHHL LLLH HHHH φ231 24φ-247 HLHL HHHL LHLH LLHL HHHL HLHL HHHL HHHH φ232 248-255 HHHL HHHL LHLL HLHL HHHL HHHL LHHL LHHL φ233 ____________________________________________________________ ______________

ROM CHIP 9 ____________________________________________________________ ______________ φ234 2φ59,φ9,1,4,φ1φ24 φ235 ROM9 φ236 φ2,11,71 φ237 586 φ238 φφφ-φφ7 HHLH HHLL HHLL LHLH HHLL HHHH HHLH HHLH φ239 φφ8-φ15 HHLL HHHH LHLH HHLL HLHH HHLL HHLL LHLL φ24φ φ16-φ23 HHLL HHLL HHLL HHHH HHLL HHLL HHLL HHLL φ241 φ24-φ31 HHLL HHHH HHHL LHLL HLHH LHLL HHHL HHLL φ242 φ32-φ39 HLLH HHLL LHHH HHLL LHHH LHLL HHLL HHLL φ243 φ4φ-φ47 HHLL HHHH HHLL HHHH HHHH HHLL HHLL HHLL φ244 φ48-φ55 LHLL HHLL HHLL HHLH HHLL HHLL LHLL LHHH φ245 φ56-φ63 HHLL HHHH HHLL HHLH HHLL HHLL HHHH HLLH φ246 φ64-φ71 HHLH HHLH HHLL HHLL HHLL LHLL HHHH LHLL φ247 φ72-φ79 HLLL HLHH HHLL HHLL HHLH LHLL HHLL LHHL φ248 φ8φ-φ87 HHLL HHLL HHLL HHLL LHHL HHHH HHLH HHLH φ249 φ88-φ95 HLHH HLHH HHLL HHLL HHLL HHHH HHHL LHHL φ25φ φ96-1φ3 HLLL HHLL HHLL HHLL HHLL HHLL HHLL HHLH φ251 1φ4-111 HHHH HLHH HHLH LHLL HHLL LHLL HHLH HHLL φ252 112-119 HLLL HHLL HHLL HHLL HHLL HHLL HHLL HHLL φ253 12φ-127 HHLH HHHH HHHH HHLL HHLH HHHL LHLL HLLH φ254 128-135 HHLH LHHH HHLL HHLL LHLL HHLL LHHH LHLL φ255 136-143 HHHH HHHL LHLL HHLL HHLL HHLL LHHL HHLL φ256 144-151 HLLH HHHH HHLL HLHH HHLL HLLH HHHH HHLL φ257 152-159 HHLL HHLL HHLL HHLL HLLH HHLL HHLL LHHH φ258 16φ-167 HHLH HHHL LHLL LHHH LHHL HHHH LLLL HHLL φ259 168-175 HHHH LHLL HHHH HHLL LHLH HLLL LHHL HHLL φ26φ 176-183 HLLH LHLL HHLH HHLH LHHH LHHH HHLL HHLL φ261 184-191 HHLL HHLL LHLL HHHL LHHH HHLL HHLL LHHH φ262

192-199 HHHL HHLL LHLH LHLL LHLL HHHL LHLL LHLL φ263 2φφ-2φ7 HHHH HHLL HLHL LHHH LHLL LHLL HHLL HLLH φ264 2φ8-215 HHHL HLHH HHLL HLHH HLLL HHHH HHHL LHHL φ265 216-223 HHLL HHLL HHLL HHHH LHHH LHLL LHLL HHLL φ266 224-231 LHHH HHHH LHLL LHLL HHLL HHLL LHHL HHLL φ267 232-239 HHHH HHLL HHLL LLHH HHLL HHLL HHLL LHLL φ268 24φ-247 HHHH HHLL LHHH HHLL LHHH HHHH LHHH LHLL φ269 248-255 HLLL HHLL HHLL HHHH HLLL HHLL HHLL HHLL φ27φ ____________________________________________________________ ______________

Each of the 71 basic instructions employed by the calculator is implemented by one or more of the abovedescribed microinstructions and associated control signals issued by the microprocessor. The manner in which this is accomplished is shown and described in detail in the flow charts of FIGS. 36A-H and 37. Each rectangular box of these flow charts represents a state of ROM 300 of the microprocessor and includes the mnemonic of the microinstructions and control signals stored in that ROM state. The number at the upper right-hand corner of each of these rectangular boxes represents the number of shift clock pulses required by the microinstructions of that ROM state. A simplified overview of these detailed flow charts is shown in FIGS. 6A-B.

PROGRAMMABLE CLOCK

Given a computing system organized to process binary data serially and under control of microinstructions stored in ROM 300 as shown in FIGS. 3A-B and 34, the implementation of a general purpose instruction set requires that some number of bits be shifted into or out of the storage registers. Depending on the operation being performed, the number of bits may vary from zero to n, where n is the number of bits in a single machine word.

If each clock period of the ROM clock corresponds to a one bit shift, a count loop must be employed to provide the desired number of shifts. A rather large number of such count loops would exist in order to implement an entire instruction set. An alternative method is to provide additional hardware which permits assignment of the desired number of shifts in a single state of ROM 300. Such an arrangement requires a variable cycle time for each state of ROM 300, but results in a very substantive saving in total number of ROM states.

To implement a variable number of shift clocks in a single state of the microprocessor, two separate clocks are required. The shift clock is applied to the data storage registers in the memory, the shift register block, the arithmetic logic unit and the input/output block. The ROM clock is applied to the ROM address flip-flops in the microprocessor, and occurs once for each state in the microprogram. The number of shift clock pulses that occur in any given ROM state is determined by a 4-bit clock code sent to the clock decoder from the microprocessor.

If no shift clocks are desired, a separate signal CCφ from the microprocessor inhibits the shift clock output, independent of the clock code issued in that state. In this way, any number of shifts between and including zero and 16 may be implemented with a 4-bit clock code and an inhibit signal.

This inhibit signal offers an additional powerful feature when gated by the qualifier test logic in the microprocessor as shown in FIG. 3A. The qualifier test logic includes a 4-bit qualifier code from ROM 3 that selects one of 16 qualifier inputs to the data selector. The data selector output QN (qualifier not met) will be high if the selected qualifier input was low. By using the QN signal to gate the inhibit microinstruction, IQN, the shift clock will be inhibited only when the qualifier is not met. Thus, all microinstructions requiring shift clocks that are issued in a given ROM state may be either executed or inhibited, depending on the logical state of the qualifier under test.

The ROM clock is applied to the eight J-K flip-flops which address the 256 word microprocessor ROM. During any given state, the complementing (J-K) inputs to the four primary address flip-flops are set up by the qualifier code or q-register code. The four secondary address flip-flop inputs are determined by the ROM 4 outputs, the BRC microinstruction, and the data selector output QN. When the ROM clock goes low, the negative edge-triggered flip-flops will cause transition of the ROM address to the next ROM state.

As shown in the block diagram of FIG. 37 and the detailed schematic diagram of FIGS. 38A-C, a crystal controlled system clock output is inverted to generate memory clock, MCK. This signal is again inverted to clock a D flip-flop having an output (control clock), which will go low if the end-of-count signal (borrow) from the down counter has occurred at the D input. The ROM clock will also go low at this time, initiating a new ROM state in the microprocessor. The control clock will normally remain low for one system clock period, and in turn generates a load signal which is delayed a half period from control clock by means of a second D flip-flop. The 4-bit clock code from the microprocessor is preset into the counter while the load signal is low.

As the load signal goes high, the ROM clock also goes high, completing the fixed interval portion of the ROM clock and shift clock as shown in FIG. 39. A series of clock pulses are now gated onto the shift clock line; SCK, until the preset counter has counted down to zero, causing control clock to again go low, completing the ROM cycle.

The inhibit signal, INH, from memory may lengthen the normal fixed interval of the ROM clock by clearing the D flip-flop and holding control clock low. This may occur during memory refresh or external test operations. In this situation, the counter remains preset and the correct number of shifts will be generated when the inhibit goes away.

SHIFT REGISTER UNIT

As shown in the detailed schematic diagrams of FIGS. 35A-D and 40A-D, A-register 122, B-register 124, P-register 126, Q-register 128, and E-register 130 of FIGS. 3A-B comprise bipolar status registers, the contents of which are recirculated when data is outputted to the R-bus or the S-bus. Full control of these registers in use and type of operations performed is maintained by the microinstructions from the microprocessor. The number of bits to be shifted in any one ROM state of the microprocessor is determined by the number of shift clocks from the clock decoder. This shift clock appears at the shift clock input of each shift register that is enabled by the microprocessor during that ROM cycle.

ARITHMETIC LOGIC UNIT

The development of complex read-only memory arrays on a single chip has made possible a hardware implementation of central processing units (CPUs) and arithmetic logic units (ALUs) with far fewer components than were previously possible. In this application, two bipolar read-only memory chips are combined with carry flip-flops and adapted to perform one-bit binary logic and arithmetic operations as well as four-bit binary coded decimal (BCD) arithmetic operations. The two bipolar read-only memory chips may comprise, for example, Hewlett-Packard 16-pin dual-in-line packaged bipolar ROMs organized into 256 words by 4-bits and of the same type as shown and described in U.S. Pat. app. Ser. No. 12,262 filed Feb. 18, 1970 by John C. Barrett, et. al and assigned to the same assignee as this patent application.

The binary/BCD Arithmetic Logic Unit consists of five integrated circuits connected as shown in the block diagram of FIG. 41 and the detailed schematic diagram of FIGS. 40A-D. Specifically, the packages consist of two 1024bit ROMs, a dual D-type flip-flop and two quad two-input NAND gates.

Internally the desired binary logical function, binary arithmetic operation or BCD operation is selected by the ALU code as shown below.

________________________________________________________ __________________ ALU FUNCTION CODE ASSIGNMENTS ____________________________________________________________ ______________ ALU CODE: BCD AC2 AC1 AC0 ALU FUNCTION DESCRIPTION ____________________________________________________________ ______________ 0 0 0 0 XOR Exclusive OR R♁S➝T 0 0 0 1 AND Logical AND R ^. S➝T 0 0 1 0 IOR Inclusive OR R + S➝T Binary 0 0 1 1 ZTT Zero ➝ T-bus Functions 0 1 0 0 ZTT ^. CBC Zero ➝ T-BUS, Clear Binary Carry 0 1 0 1 IOR ^. CBC Inclusive OR, Clear Binary Carry 0 1 1 0 IOR ^. SBC Inclusive OR, Set Binary Carry 0 1 1 1 ADD Binary ADD B + S + BC ➝ T,C BCD 1 0 1 1 BCD ADD BCD ADD T _{0 -3} + A _{0 -3} ➝ Σ _{0 -3} Functions 1 1 1 1 BCD COMP/ADD IO's Complement and BCD ADD ____________________________________________________________ ______________

The function code input "BCD" selects between the binary mode and BCD mode of operation.

In the binary mode, the function code inputs AC0, AC1, and AC2 select the desired logical function or arithmetic operation. The binary input data enters ROM No. 1 on the carry, S-bus and R-bus input lines, and the binary result appears on the T-bus and binary carry output lines. ROM No. 2 is not used in the binary mode.

In the BCD mode of operation, the two function code lines AC0 and AC1 are disabled from the Micro-pressure and these two lines carry the T02 and T03 bits of BCD data from the T-Register. The ALU function code line AC2 is used to select the desired BCD operation. If AC2 is low, the four-bit output Σ0, Σ1, Σ2, Σ3 will be the BCD sum of the two BCD data inputs. If AC2 is high and decimal carry has been set, the four-bit output Σ0, Σ1, Σ2, Σ3 will be the BCD Tens Complement of the BCD data from the T-Register. In the BCD mode, the binary carry output will be disabled and the decimal carry output will be enabled to ROM No. 1.

Although only one-fourth of the available registers in ROM No. 1 are required for the eight binary operations, the concept of adding a second 1024-bit ROM to perform the BCD operations grew from several basic concepts:

1. The least significant BCD sum bit, Σ0, is always identical to the binary sum bit; therefore, only three additional outputs, Σ1, Σ2, and Σ3 need be generated. For BCD complement operations, the decimal carry flip-flop defines whether or not the least significant bit should be complemented.

2. In forming the "nine's complement" of the T-Register BCD data in ROM No. 1, it can be seen that for 8421 code the second least significant bit T01 is the same before and after forming the complement. Thus only two bits, T02 and T03 need be complemented prior to input into ROM No. 2. The ten's complement with add is then found by presetting decimal carry and performing a BCD sum of the three most significant digits in ROM No. 2.

3. With only eight ROM inputs available, some sharing of inputs is required for ROM No. 1. During binary operations, all four function codes and only one bit of T-Register data is required. During BCD operations, all four bits of T-Register data and only two function codes are required. Use of two NAND gates in wire-OR connection with the open collector function codes AC0 and AC1 permits sharing of the two inputs.

This arrangement left one input still available to ROM No. 2. By programming this input to always make output DCI true, the micro-instruction UTR can serve two purposes--placing units on the R-bus and also set decimal carry if BCD is true. When BCD is false, clock is inhibited to decimal carry. This feature permits saving decimal carry information during all binary operations. Similarly, binary carry is saved during the four binary operations AND, IOR, XOR, and ATT by connecting AC2 such that when AC2 is false the shift clock is inhibited to the binary carry flip-flop.

In summary, the mode select input "BCD" performs the following functions:

1. Addresses the proper 128 word set of word lines in ROM No. 1.

2. Enables the T02 and T03 data lines to ROM No. 1 only in BCD mode.

3. Enables clock to decimal carry flip-flop only in BCD mode.

4. Selects binary carry or decimal carry into ROM No. 1 as appropriate.

5. Transfers outputs Σ0, Σ1, Σ2, Σ3, to A-Register only in BCD mode.

The remaining three ALU function codes select the proper set of word lines in ROM No. 1 to perform the eight binary functions. In addition, the AC2 input performs the following functions.

1. Enables clock to binary carry flip-flop only during the four carry-related binary functions and the BCD comp/add function.

2. In the BCD mode, AC2 causes BCD data bit TOO, T02 and T03 to convert to nine's complement form.

The ALU has a total of 15 inputs which include 8 data inputs, 2 clock inputs and 5 microinstructions. Four data output lines are required, and two additional output lines from carry flip-flops are available as qualifier inputs to the microprocessor. The ALU and shift register mnemonics are listed in the following table:

SHIFT REGISTERS & ALU BOARD MNEMONICS ______________________________________ TRE T-Register to E-Register to R-Bus T0φ Bit φ of T-Register TBE T-Bus to E-Register to R-Bus TTX - TEST T-Bus to A/B-Register from Tester TTX - I/0 T-Bus to A/B-Register from I/0 (Board No. 12) TTX - ROM T-Bus to A/B-Register from Processor (Board No. 13) TTX Logical "OR" of Three TTX Signals AB Status of AB-Flip-Flop AB = 0 A-Reg. Operation AB - 1 B-Reg. Operation XTR A/B Register to R-Bus UTR Logical "I" to R-Bus TQR Q-Register to Primary Address Flip-Flop AB Complement of AB TTP T-Bus to P-Register SCK Shift Clock QPφ Qualifier, Bit φ of P-Register PTR P-Register to R-Bus QOφ Q-Register Bit φ QTR Q-Register to R-Bus RCK ROM Clock QAB Q-Register to AB-Flip-Flop, - also clears decimal carry. -SCB Set Binary Carry BCD Decimal Arithmetic AC2 ALU Operation Code QBC Qualifier, Binary Carry S-BUS Data Bus AC1 ALU Operation Code ACφ ALU Operation Code T02 Bit 2 of T-Register T03 Bit 3 of T-Register SDR Signal to Disable ROMs T01 Bit 1 of T-Register T-BUS Data Bus ALU Arithmetic Logic Unit (--) Indicates Negative True Signal ______________________________________

The following table gives an example of how the two ALU ROM chips shown in FIG. 41 can be constructed to implement the above described ALU functions (in this table each 1 represents a "low" state and each 0 represents a "high" state):

ROM No. 1 ______________________________________ I33φ1-φφφ6/ / 1φφφ; 1/ φφφφ; 2/ φφφφ; 3/ 1φφφ 4/ 1φφφ; 5/ φφφφ; 6/ φφφφ; 7/ 1φφφ 8/ φφφφ; 9/ φφφφ; 10/ φφφφ; 11/ 1φφφ 12/ φφφφ; 13/ φφφφ; 14/ φφφφ; 15/ 1φφφ 16/ φφφφ; 17/ 1φφφ; 18/ 1φφφ; 19/ 1φφφ 20/ φφφφ; 21/ 1φφφ; 22/ 1φφφ; 23/ 1φφφ 24/ 1φφφ; 25/ 1φφφ; 26/ 1φφφ; 27/ 1φφφ 28/ 1φφφ; 29/ 1φφφ; 30/ 1φφφ; 31/ 1φφφ 32/ 1φφφ; 33/ φφφφ; 34/ φφφφ; 35/ 1φφφ 36/ 1φφφ; 37/ φφφφ; 38/ φφφφ; 39/ 1φφφ 4φ/ φφφφ; 41/ φφφφ; 42/ φφφφ; 43/ 1φφφ 44/ φφφφ; 45/ φφφφ; 46/ φφφφ; 47/ 1φφφ 48/ φφφφ; 49/ 1φφφ; 50/ 1φφφ; 51/ 1φφφ 52/ φφφφ; 53/ 1φφφ; 54/ 1φφφ; 55/ 1φφφ 56/ 1φφφ; 57/ 1φφφ; 58/ 1φφφ; 59/ 1φφφ 60/ 1φφφ; 61/ 1φφφ; 62/ 1φφφ; 63/ 1φφφ 64/ 11φφ; 65/ 11φφ; 66/ 11φφ; 67/ 11φφ 68/ 11φφ; 69/ 11φφ; 70/ 11φφ; 71/ 11φφ 72/ φφφφ; 73/ φφφφ; 74/ φφφφ; 75/ 1φφφ 76/ φφφφ; 77/ φφφφ; 78/ φφφφ; 79/ 1φφφ 80/ φ1φφ; 81/ φ1φφ; 82/ φ1φφ; 83/ 11φφ 84/ φ1φφ; 85/ φ1φφ; 86/ φ1φφ; 87/ 11φφ 88/ φφφφ; 89/ 1φφφ; 90/ 1φφφ; 91/ φ1φφ 92/ 1φφφ; 93/ φ1φφ; 94/ φ1φφ; 95/ 11φφ 96/ 11φφ; 97/ 11φφ; 98/ 11φφ; 99/ 11φφ 1φφ/ 11φφ; 1φ1/ 11φφ; 1φ2/ 11φφ; 1φ3/ 11φφ 1φ4/ φφφφ; 1φ5/ φφφφ; 1φ6/ φφφφ; 1φ7/ 1φφφ 1φ8/ φφφφ; 1φ9/ φφφφ; 11φ/ φφφφ; 111/ 1φφφ 112/ φ1φφ; 113/ φ1φφ; 114/ φ1φφ; 115/ 11φφ 116/ φ1φφ; 117/ φ1φφ; 118/ φ1φφ; 119/ 11φφ 12φ/ φφφφ; 121/ 1φφφ; 122/ 1φφφ; 123/ φ1φφ 124/ 1φφφ; 125/ φ1φφ; 126/ φ1φφ; 127/ 11φφ 128/ φφφφ; 129/ φφφφ; 13φ/ φφφφ; 131/ φφφφ 132/ φφφφ; 133/ φφφφ; 134/ φφφφ; 135/ φφφφ 136/ φφ1φ; 137/ 1φ1φ; 138/ 1φ1φ; 139/ φ11φ 14φ/ 1φ1φ; 141/ φ11φ; 142/ φ11φ; 143/ 111φ 144/ φφφ1; 145/ 1φφ1; 146/ 1φφ1; 147/ φ1φ1 148/ 1φφ1; 149/ φ1φ1; 15φ/ φ1φ1; 151/ 11φ1 152/ φφ11; 153/ 1φ11; 154/ 1φ11; 155/ φ111 156/ 1φ11; 157/ φ111; 158/ φ111; 159/ 1111 16φ/ φφφφ; 161/ φφφφ; 162/ φφφφ; 163/ φφφφ 164/ φφφφ; 165/ φφφφ; 166/ φφφφ; 167/ φφφφ 168/ φφ1φ; 169/ 1φ1φ; 17φ/ 1φ1φ; 171/ φ11φ 172/ 1φ1φ; 173/ φ11φ; 174/ φ11φ; 175/ 111φ 176/ φφφφ; 177/ φφφφ; 178/ φφφφ; 179/ φφφφ 18φ/ φφφφ; 181/ φφφφ; 182/ φφφφ; 183/ φφφφ 184/ φφ11; 185/ 1φ11; 186/ 1φ11; 187/ φ111 188/ 1φ11; 189/ φ111; 19φ/ φ111; 191/ 1111 192/ φφφφ; 193/ φφφφ; 194/ φφφφ; 195/ φφφφ 196/ φφφφ; 197/ φφφφ; 198/ φφφφ; 199/ φφφφ 2φφ/ 1φ1φ; 2φ1/ φφ1φ; 2φ2/ φ11φ; 2φ3/ 1φ1φ 2φ4/ φ11φ; 2φ5/ 1φ1φ; 2φ6/ 111φ; 2φ7/ φ11φ 2φ8/ 1φ11; 2φ9/ φφ1φ; 21φ/ φ111; 211/ 1φ11 212/ φ111; 213/ 1φ11; 214/ 1111; 215/ φ111 216/ 1φφ1; 217/ φφφ1; 218/ φ1φ1; 219/ 1φφ1 22φ/ φ1φ1; 221/ 1φφ1; 222/ 11φ1; 223/ φ1φ1 224/ φφφφ; 225/ φφφφ; 226/ φφφφ; 227/ φφφφ 228/ φφφφ; 229/ φφφφ; 23φ/ φφφφ; 231/ φφφφ 232/ 1φ11; 233/ φφ11; 234/ φ111; 235/ 1φ11 236/ φ111; 237/ 1φ11; 238/ 1111; 239/ φ111 24φ/ φφφφ; 241/ φφφφ; 242/ φφφφ; 243/ φφφφ 244/ φφφφ; 245/ φφφφ; 246/ φφφφ; 247/ φφφφ 248/ 1φ1φ; 249/ φφ1φ;

25φ/ φ11φ; 251/ 1φ1φ 252/ φ11φ; 253/ 1φ1φ; 254/ 111φ; 255/ φ11φ ______________________________________

ROM No. 2 ______________________________________ I33φ1-φφφ7/ / φφφφ; 1/ φφφφ; 2/ φφφφ; 3/ φφφφ 4/ φφφφ; 5/ φφφφ; 6/ φφφφ; 7/ φφφφ 8/ φφφφ; 9/ φφφφ; 1φ/ φφφφ; 11/ φφφφ 12/ φφφφ; 13/ φφφφ; 14/ φφφφ; 15/ φφφφ 16/ φφφφ; 17/ φφφφ; 18/ φφφφ; 19/ φφφφ 2φ/ φφφφ; 21/ φφφφ; 22/ φφφφ; 23/ φφφφ 24/ φφφφ; 25/ φφφφ; 26/ φφφφ; 27/ φφφφ 28/ φφφφ; 29/ φφφφ; 3φ/ φφφφ; 31/ φφφφ 32/ φφφφ; 33/ φφφφ; 34/ φφφφ; 35/ φφφφ 36/ φφφφ; 37/ φφφφ; 38/ φφφφ; 39/ φφφφ 4φ/ φφφφ; 41/ φφφφ; 42/ φφφφ; 43/ φφφφ 44/ φφφφ; 45/ φφφφ; 46/ φφφφ; 47/ φφφφ 48/ φφφφ; 49/ φφφφ; 5φ/ φφφφ; 51/ φφφφ 52/ φφφφ; 53/ φφφφ; 54/ φφφφ; 55/ φφφφ 56/ φφφφ; 57/ φφφφ; 58/ φφφφ; 59/ φφφφ 6φ/ φφφφ; 61/ φφφφ; 62/ φφφφ; 63/ φφφφ 64/ φφφφ; 65/ φφφφ; 66/ φφφφ; 67/ φφφφ 68/ φφφφ; 69/ φφφφ; 7φ/ φφφφ; 71/ φφφφ 72/ φφφφ; 73/ φφφφ; 74/ φφφφ; 75/ φφφφ 76/ φφφφ; 77/ φφφφ; 78/ φφφφ; 79/ φφφφ 8φ/ φφφφ; 81/ φφφφ; 82/ φφφφ; 83/ φφφφ 84/ φφφφ; 85/ φφφφ; 86/ φφφφ; 87/ φφφφ 88/ φφφφ; 89/ φφφφ; 9φ/ φφφφ; 91/ φφφφ 92/ φφφφ; 93/ φφφφ; 94/ φφφφ; 95/ φφφφ 96/ φφφφ; 97/ φφφφ; 98/ φφφφ; 99/ φφφφ 1φφ/ φφφφ; 1φ1/ φφφφ; 1φ2/ φφφφ; 1φ3/ φφφφ 1φ4/ φφφφ; 1φ5/ φφφφ; 1φ6/ φφφφ; 1φ7/ φφφφ 1φ8/ φφφφ; 1φ9/ φφφφ; 11φ/ φφφφ; 111/ φφφφ 112/ φφφφ; 113/ φφφφ; 114/ φφφφ; 115/ φφφφ 116/ φφφφ; 117/ φφφφ; 118/ φφφφ; 119/ φφφφ 12φ/ φφφφ; 121/ φφφφ; 122/ φφφφ; 123/ φφφφ 124/ φφφφ; 125/ φφφφ; 126/ φφφφ; 127/ φφφφ 128/ 1111; 129/ 11φ1; 13φ/ 1φ11; 131/ 1φφ1 132/ φ111; 133/ φφφφ; 134/ φφφφ; 135/ φφφφ 136/ 11φ1; 137/ 1φ11; 138/ 1φφ1; 139/ φ111 14φ/ 111φ; 141/ φφφφ; 142/ φφφφ; 143/ φφφφ 144/ 1φ11; 145/ 1φφ1; 146/ φ111; 147/ 111φ 148/ 11φφ; 149/ φφφφ; 15φ/ φφφφ; 151/ φφφφ 152/ 1φφ1; 153/ φ111; 154/ 111φ; 155/ 11φφ 156/ 1φ1φ; 157/ φφφφ; 158/ φφφφ; 159/ φφφφ 16φ/ φ111; 161/ 111φ; 162/ 11φφ; 163/ 1φ1φ 164/ 1φφφφ; 165/ φφφφ; 166/ φφφφ; 167/ φφφφ 168/ φφφφ; 169/ φφφφ; 17φ/ φφφφ; 171/ φφφφ 172/ φφφφ; 173/ φφφφ; 174/ φφφφ; 175/ φφφφ 176/ φφφφ; 177/ φφφφ; 178/ φφφφ; 179/ φφφφ 180/ φφφφ; 181/ φφφφ; 182/ φφφφ; 183/ φφφφ 184/ φφφφ; 185/ φφφφ; 186/ φφφφ; 187/ φφφφ 188/ φφφφ; 189/ φφφφ; 190/ φφφφ; 191/ φφφφ 192/ 11φ1; 193/ 1φ11; 194/ 1φφ1; 195/ φ111 196/ 111φ; 197/ φφφφ; 198/ φφφφ; 199/ φφφφ 200/ 1φ11; 201/ 1φφ1; 202/ φ111; 203/ 111φ 204/ 11φφ; 205/ φφφφ; 206/ φφφφ; 207/ φφφφ 208/ 1φφ1; 209/ φ111; 210/ 111φ; 211/ 11φφ 212/ 1φ1φ; 213/ φφφφ; 214/ φφφφ; 215/ φφφφ 216/ φ111; 217/ 111φ 218/ 11φφ; 219/ 1φ1φ 220/ 1φφφ; 221/ φφφφ; 222/ φφφφ; 223/ φφφφ 224/ 111φ; 225/ 11φφ; 226/ 1φ1φ; 227/ 1φφφ 228/ φ11φ; 229/ φφφφ; 230/ φφφφ; 231/ φφφφ 232/ φφφφ; 233/ φφφφ; 234/ φφφφ; 235/ φφφφ 236/ φφφφ; 237/ φφφφ; 238/ φφφφ; 239/ φφφφ 240/ φφφφ; 241/ φφφφ; 242/ φφφφ; 243/ φφφφ 244/ φφφφ; 245/ φφφφ; 246/ φφφφ; 247/ φφφφ

248/ φφφφ; 249/ φφφφ; 250/ φφφφ; 251/ φφφφ 252/ φφφφ; 253/ φφφφ; 254/ φφφφ; 255/ φφφφ ______________________________________

MEMORY UNIT

The calculator uses an all semiconductor memory system. Peripheral circuitry is bipolar and the memory consists of n-channel MOS read only memory (ROM) and p-channel MOS read/write memory (RWM).

Addressing and physical layout of the memory module are done so that the number of words can be increased from 5K in the basic machine to 9K in the largest machine. The smallest increment of memory that can be added is 512 words.

The basic machine contains 5K words of memory, organized into 4K × 16 ROM, and 1024 × 16 RWM. The 16 bit RWM words are divided into user registers and processor words.

The largest machine contains 7K words of ROM and 2K words of RWM.

Read/Write Memory

As shown in FIGS. 42-44 memory is made up of 1024 × 1, dynamic read/write memory chips (Intel 1103). These devices are P-channel, MOS using silicon gate technology. To maintain the contents of memory, the device must be refreshed every 2 ms. This is accomplished by performing a read cycle at a given address. On each chip are 32 refresh amplifiers so that each read cycle, 32 cells get refreshed. The entire chip is then refreshed by cycling through the lower 5 address bits and reading each distinct address. The refresh period is 20 μs at least every 2 ms.

Logic levels on all input lines to the RWM chips are 0 to + 16v. This includes the three clock lines (chip select, Y-enable or write, and precharge), 10 address lines, and input data. The output data, however, is a current of 600 μa or more into 1K ohms or less. This low level output is "wire-or able" with other chips to build larger systems.

Read Only Memory

As shown in FIGS. 42, 43A-B, and 44A-B ROM chips are 4096 bit, n-channel MOS arranged 512 × 8. The devices are static and consume no power when not enabled. Data is retrieved from the ROMs by pulling the chip enable line from 0 to + 12v (turning the chip on), addressing the desired cells (0 or 4v levels) and selecting which output devices are to be enabled (4v or 0v). The output levels are sufficient to drive one TTL gate directly, and can be "wire-or/ed" for large systems.

As further shown in FIGS. 47 and 48A-B each ROM chip comprises six input buffers. These input buffers generate both the input and its complement. On the basis of the 64 possible combinations of the 6 inputs I ₀ -I ₅ , one of the 64 lines in the decoder is selected. The selected line enables one of the vertical lines in the 64 × 64 bit storage array. For example, let I ₀ - I ₅ = 0 and I ₆ - I ₈ be "don't cares." This means line X00 (octal) is selected.

The two 8 out of 32 select decoders must choose 16 lines from the 64 horizontal lines selected by the vertical line X00. (The 8 out of 32 select decoder is actually a 2 out of 8 decoder repeated 4 times in each of the sections A - B). The output from four MOS Fet's a, b, c, and d are "wire or/ed." MOS devices a' , b' , c', and d' are also connected similarly. If I ₆ and I ₇ = 0, horizontal lines 1XX 2XX, 3XX, 5XX, 6XX, 7XX are grounded in each of the four sections A-B. This insures that MOS Fet's b, c, d, b' , c', and d' are non-conductive. This allows signals on lines 0XX and 4XX to pass into the output sections through transistors a and a'.

The output section contains the output buffer, 1 of 2 decoder, and the output drivers s. The output buffer provides a stage of gain and "wire or 's" 4 lines from the storage array. The 1 of 2 decoder clamps the gates of 2 of the 4 output drivers in each section A-B by enabling either line I ₈ or its complement (I ₈ ). This disables 1 of 2 signals coming from the output buffer. The output drivers then can be tied together with line (e) for a 512 × 8 organization.

Each of the above-listed constants and routines and subroutines of basic instructions employed by the calculator is stored in these ROM chips. The sixteen bits of each constant and basic instruction are stored in the 512 ₁₀ × 8 ₁₀ ROM chips by organizing the ROM chips into 64 × 64 bit matrices and computing the row and column numbers of each bit of each matrix by operating on each address and the particular bit (15 through 8, or 7 through 0). The column number is computed by subtracting the last two digits of the address from 100 ₈ . For example, the column number of address 000 = 100 ₈ - 00 ₈ = 100 = 64 ₁₀ and the column number of address 777 = 100 ₈ - 77 ₈ = 1. The computation of the row number (referred to as IR in the flow-chart of FIG. 50) can best be described by referring to the flowchart of FIG. 50 and the associated table of FIG. 51. Once the row and column numbers are found it is a simple matter of storing in that location of the matrix that particular bit (i.e., a 1 or a 0). A 0 is stored at a designated location by forming a metal gate to complete a MOS FET device at that location, and a 1 is stored at a designated location by leaving off the metal gate so that a a MOS FET device is not formed at that location.

M-Register

As shown in FIGS. 42 and 52A-B included on the M-Register board is the 16 bit Address or M-Register, all chip enable decoding and buffering, and address buffers for both ROM and RWM. The register uses four, four bit, serial in and out, parallel in and out shift Registers. Upon receipt of a TTT instruction from the microprocessor, serial data from the T-Bus is accepted into the M-Register. Nothing is done with this data until either a read or write instruction is received, then one of two decoders are enabled. These chip Enable decoders uniquely decode which block of 512 words, either ROM or RWM, is being addressed. If ROM is being addressed, the signal is inverted and amplified to +12v. For RWM the Chip Enable enables a gate, which allows a 16 Volt clock signal to reach the enabled RWM chips. The clock wave-form is generated on the control card.

The dynamic characteristic of the RWM chips, requires that all chips be enabled simultaneously during a refresh cycle, to refresh the entire read/write memory. The buffer circuits in the output of the Chip enable decoders allow the chip select clock to reach all of the RWM chips during refresh but only those being accessed, during a read or write cycle.

Totem Pole output and gates with resistor pull-ups are used as buffers for the ROM address lines. Using the totem pole output gates, the effects of crosstalk can be minimized while the resister pullup lifts the address lines above the required 4v level. The nand gates are enabled during a memory cycle so that the ROM address lines are inhibited at a 5v level. The RWM address lines must pull from 0v to + 16v. High voltage, open collector, inverters with discrete transistor pull-ups are used as buffers for the five most significant bits. The five least significant address bits are bussed to the control card where they are used in part of the refresh circuitry.

Control

A memory cycle consists of a read or write instruction from the processor accompanied by 12 clock pulses from the shift clock. As shown in FIGS. 42, 53A-D and 54, control uses these pulses and instructions to generate the clocks required by the RWM chips. A synchronous 4 bit counter (SN74193) is used to count clock pulses and the four outputs are decoded by a 1 and 16 decoder (SN74154) to generate J and K input to flip-flops. The outputs from the flip-flops are then buffered to become the required clock signals (Precharge, Y-enable, chip select).

Refreshing the read/write memory is also taken care of by the control card. An astable multivibrator with a repetition rate of 500 HZ minimum generates a signal which allows a refresh cycle to occur. A flip-flop generates the actual signal (REF), but only if the astable multivibrator signal is high, there is no read or write cycle in progress and the processor signal, CCT, is high. CCT goes high between processor instructions, thus it is known that nothing is going to be interrupted when REF is generated. REF is then buffered by an open collector inverter and given to the processor INH. INH halts the machine and the refresh cycle begins.

The same counter used for a memory cycle is used during refresh to again generate the necessary clocks (Precharge and chip select). When the counter returns to state 0 and REF is present, a second counter is advanced one count. This second counter provides the refresh addresses which go to the RWM only if REF is present. When this counter returns to state 0, it causes REF and INH to return to preset conditions and the machine continues normal operation.

Another function of the control card is to provide for extended memory capability. The control card handles any external memory as if it were an extension of the internal memory. From the user's point of view, he does not need to know if an extended memory is connected other than the fact that available memory has increased.

In addition, the control card has the provision for extracting information from or loading information into the calculator T-Register through the D-Bus (data bus).

Other signals generated on the control card are employed to direct the flow of data in the T-register.

T-Register

Data to and from the memory is temporarily stored in the T-register. As shown in FIGS. 42 and 55A-D four 4 bit, serial in and out, parallel in and out shift registers make up the actual T-register. The registers have a mode control (TMC) which when low, allows serial data flow and when high, allows parallel data flow.

Serial data enters the T-register in the presence of the TTT instruction, and simultaneously recirculated into the T-register to prevent loss of data.

Parallel data is accepted from either ROM or RWM during a read cycle. The ROM data is buffered by nand gates and the RWM by sense amplifiers followed by the same nane gates. All 16 bits are read from either RWM or ROM simultaneously. Each bit to be written into RWM has its own discrete buffer stage that translates T ² L logic levels into 16v logic levels used by the RWM.

MEMORY SYSTEM MNEMONIC TABLE

SIGNALS GENERATED OUTSIDE MEMORY I/O CONNECTOR

Cct -- control clock-not, the inverted envelop of SCK.

Sck -- shift clock.

Mck -- memory clock, a continuous pulse train, used by the memory control for timing of the memory and refresh cycles.

Iod -- i/o data. Goes to control board to be gated to S-BUS.

Its -- i/o to S-BUS, the signal which gates IOD to S-BUS.

Sco & sci -- coded signals which generate

Uts -- units to S-BUS

Zts -- zero to "

Mts -- m-reg to "

Tts -- t-reg to "

Ttt -- t-bus to T-Reg, OV = True.

T-bus -- data on this bus acts as inputs to M & T registers.

Rdm -- read memory, negative true. Lasts for 12 clock pulses.

Wtm -- write memory, negative true. Lasts for 12 clock pulses.

Inh -- inhibit, negative true. The processor is stopped whenever INH is at zero volts. The memory control generates this signal while a R/W memory refresh cycle is present. I/O also generates it.

______________________________________ OTHER SIGNALS AT I/O CONNECTOR Name Source ______________________________________ T00 T-Register T01 do. T02 do. T03 do. ______________________________________

D-bus -- data Bus -- external data (extended memory data) enters machine via this bus.

Edt -- external Data Transfer gates D-BUS data into machine O ^v = True.

Emb -- extended memory busy. Signal provided by extended memory that tells memory control

a. Extended memory cycle is complete

b. Extended memory is present.

SIGNALS GENERATED ON READ/WRITE MEMORY CARDS

Rwd(xx) -- read/Write data. Output from the 1103 memory. 600μa into 150 = 1"0 current = 0

Aof -- add-on function not .5 ^v signal if the add on R/W board (option 01) is not present in the machine. 0 ^v = True.

______________________________________ OTHER SIGNALS USED BY (RWM) Name Source ______________________________________ Aφφ-A04 CONTROL A05-A09 M-REG CSB M-REG CSA M-REG RWI(XX) T-REG YBL CONTROL PCG CONTROL ______________________________________

SIGNALS GENERATED ON T-REGISTER CARD

T00-t15 -- t-register data bits. Used as data into memory T00-T03 are also outputs to the CPU. (4 bit processing)

Rwi(xx) -- read/write inputs. T-register data gates to Read/write memory. +16V ➝ GND.

______________________________________ OTHER SIGNALS USED BY T-REGISTER Name Source ______________________________________ ROD(XX) ROM TRI CONTROL TSC CONTROL TMC CONTROL TPC CONTROL RWD(XX) R/W MEM RWE M-REG MAW M-REG ______________________________________

Aof -- add on R/W Board (Option φ1)

SIGNALS GENERATED ON M-REGISTER CARD

Moo-m15 -- m-register data bits. Used to generate address and chip select information. (MOO also is gated out on S-BUS by MTS)

I00-i07 -- rom address bits. Decodes down to two bits available at ROM output buffers.

I08-i08 -- selects which ROM output buffers are enabled.

Ceb(xx) -- chip enable, basic machine selects which ROM chips are turned on (+12V -- ON)

Cea(xx) -- chip enable add-on function.

Aen -- address enable. AEN = RDM + WTM

A05-a09 -- address bits for R/W memory. (+16V & GND)

Csb(xx) -- chip select, basic machine a negative true clock which selects which R/W chips are turned on. (+16V & GND)

Csa(xx) -- chip select, add-on.

Rwe -- read/Write enable. A +5V signal any time a R/W chip is addressed for a machine memory cycle.

Maw -- max addressable work (+5V signal whenever addressing memory location octal 1377).

Nva -- non-valid address +5 ^v signal for all addresses greater than octal 22000.

Rwa -- read/Write add on. Whenever addressing R/W memory between octal 20000 & 22000 0 ^v = True.

Rwb -- read/Write Basic. Whenever addressing R/W memory between octal 1400 & 1777 or ocatal 16400 & 17777.

______________________________________ OTHER SIGNALS USED BY THE M-REGISTER Name Source ______________________________________ T-BUS PROCESSOR SCK do. RDM do. WTM do. TTM do. VLD CONTROL MTS do. CSL do. REF do. ______________________________________

SIGNALS GENERATED ON CONTROL BOARD

Vor -- a signal generated half way through the memory cycle to disable the active pull up devices on the ROM outputs.

Tri -- t-register input TRI = (T-BUS) . (TTT) + (TOO) . (TTS)

Mts -- m-register to S-BUS. Generated from SCO, SC1

A00-a04 -- address bits for R/W memory also used during memory refresh.

Tsc -- t-register series clock. TSC = SCK. (TTS + TTT + EDT)

Tpc -- t-register parallel clock. (Strobes in data from memory) only during internal memory read cycle.

Ybl -- y-enable. A clock which left at +16V for a read and clocked to GND during a write. (R/W memory only)

Pcg -- precharge. The 3rd 16V clock required by the 1103 R/W memory chips.

Csl -- chip select clock. The signal which is anded with M-register data to provide chip selects.

Ref -- refresh. OV when the memory is in a refresh cycle.

Cem -- call extended memory. Prevents ROM clock from changing μ processor states. Given for all read and write commands. Signal is removed if the memory cycle is not extended memory cycle. If extended memory cycle, CEM Is removed after extended memory has completed cycle. O ^v = True.

S-bus -- gates I/O register, data, Tφφ, Mφφ or ones onto S-BUS and sent to processor. O = True.

Inh -- inhibit, negative true. The processor is stopped whenever INH Is at zero volts. The memory control generates this signal while a R/W memory refresh cycle is present. I/O also generates it.

Tmc -- t-reg mode control. TMC = 0; T-reg is set up to accept information from memory. TMC = 1; T-reg. is set up to shift serially.

Emc -- extended memory cycle. +5 ^v signal used to signal extended memory to begin its cycle. O ^v = True.

Vld -- a signal generated half way thru memory cycle to allow data to flow out of ROM. Same timing as VOR.

______________________________________ OTHER SIGNALS USED BY THE CONTROL Name Source ______________________________________ CCT PROCESSOR T00 T-REG IOD PROCESSOR ITS do. SCO do. SCI do. TTT do. T-BUS do. SCK do. RDM do. WTM do. MCK do. M00-M04 M-REG AEN M-REG EDT EXTENDED MEMORY D-BUS I/O CONNECTOR NVA M-REG AOF ADD-ON R/W MEMORY (Option 01) EMB EXTENDED MEMORY MAW M-REG RWA M-REG ______________________________________

SIGNALS GENERATED ON ROM BOARD

Rod(xx) -- read Only Data OTHER SIGNALS USED BY ROM Name Source ______________________________________ CEA(XX) M-REG CEB(XX) M-REG I00-I07 M-REG I08 I08 M-REG VOR CONTROL ______________________________________

INPUT-OUTPUT CONTROL UNIT

The input-output control unit allows the calculator to communicate with the internal input, input-output, and output units and with external peripheral devices. As shown in FIGS. 38A-C and 56A-D, the input-output control unit is contained on two printed circuit boards, the "control and system clock" board and the "I/O register and gate interface" board. A third board, shown in FIG. 57, is an I/O motherboard providing room for connecting four external interface cards to the calculator.

The internal input, input-output, and output units are distinguished from peripheral devices by the fact that the I/O language set addresses them directly. Hence, each I/O instruction contains an internal peripheral address as part of its makeup. The four internal directly-addressable input, input-output, and output units are the I/O register, the magnetic card reading and recording unit, the output printer unit and display unit.

The external peripheral devices are indirectly addressable and are connected via cable to an interface card which is plugged into the I/O motherboard at the rear of the calculator. The term indirectly addressable is defined here to mean the external peripheral devices are addressed by lines leading from the four most significant bits in the I/O register, thereby requiring an address word to be loaded into the directly addressable I/O register.

I/O Control and System Clock Section

The function of the I/O control and system clock section is to provide control to the I/O register and gate interface section. This is accomplished by use of an I/O instruction set stored in the main memory of the calculator.

The microprocessor causes instructions from the memory unit to be loaded into the T-Register and then to be transferred to the Q-Register. The microprocessor determines the type of instruction and causes the proper execution of the instruction. If the instruction is an I/O type, control is transferred by the microprocessor to the I/O control and system clock section.

The microprocessor remains in a two-state waiting loop while the I/O control section is active. Time in the wait loop is between .72 micro seconds and 6.5 micro seconds.

Bits 5 through 10 from the Q-Register are connected to the I/O control section and remain constant during an I/O instruction execution time. Bits 5 through 8 representing the I/O instruction code are gated to the I/O address flip flops and entered on each clock time while the I/O is inactive. The four outputs of the address flip flops are connected to the address input of a 1 of 16 decoder and represent the starting state address of the I/O instruction to be executed. When the I/O control section is enabled, the input gates passing bits 5 through 8 to the I/O address flip flops are closed and the 1 of 16 decoder enabled. This allows the starting state I/O micro instructions to come from the 1 of 16 decoder. The next state address coming from the closed input gates will be the exit state (1111 = 17 ₈ ) unless modified by reopening the gates to let the original starting state code through or by modifying the output of one or more of the input gates using a "wire or" connection coming from the 1 of 16 decoder output. This address is sent to the I/O address flip flops inputs and clocked in on the leading edge of the first half clock cycle. The first half clock cycle turns off the 1 of 16 decoder and the address changes. The second half clock cycle enables the 1 of 16 decoder, allowing the next state micro instruction to appear. (See FIG. 58 for the timing described above). This process continues until the exit state is encountered. On the exit state, the I/O Control is disabled and control is returned to the microprocessor.

The I/O instructions involving the transfer of data between the I/O and the CPU (OT, LI, MI), require 16 passes through the same state (1 pass for each of 16 bits). This is achieved by checking the output of a 16 bit down counter and then decrementing after each pass through the state. If the counter indicates 0 has not been reached, it causes the starting state address to be reloaded into the address flip flops by opening the input gates. When 16 passes have been indicated by the counter, the input gates are not allowed to open; however, the next state (1111) is modified by the output of the 1 of 16 decoder through a "wire or" connection on the 2nd bit to give state 1101. This address is input to the I/O address flip flops as in the preceeding paragraph.

The above-described operation of the I/O control section is also illustrated and further described in the flow chart of FIG. 59.

Bit 9 is called a hold/clear bit. It allows a clear flag (CLF) to take place or not to take place after execution of the other I/O instructions (STF excepted).

Bit 10 is used in conjunction with the micro instructions PTR and XTR to give control to the I/O.

The I/O control and programmable clock mnemonics are given in the following table:

I/O CONTROL BOARD MNEMONICS ______________________________________ CCφ Clock Code Zero CC1 do. One CC2 do. Two CC4 do. Four CC8 do. Eight CCT Control Clock to Tester CEM Call Extended Memory CLC Clear Control CLF Clear Flag DRC Data Register Clock EBT Eight Bit Transfer EOW End of Word IIO Inhibit Internal OSC INH Inhibit Clock IPS Inhibit Primary/Secondary ITS Input to S-Bus MCK Memory Clock POP Power On Pulse PTR P-Reg to R-Bus QFG Qualifier Flag Q5 do. Five Q6 do. Six Q7 do. Seven Q8 do. Eight Q9 do. Nine Q10 do. Ten QRD do. ROM Disable RCA ROM Clock Address RCF ROM Clock Flip Flop SCB Set Carry Bit SCK Shift Clock SCT do. to Tester SRA Service Request Acknowledge STC Set Control STF Set Flag TCK Tester Clock TTO T-Bus to Output TTX T-Bus to A/B Reg. XTO External OSC XTR A/B Reg. to R-Bus Note: ( ) indicates negative true signal ______________________________________

I/O Register and Gate Interface Section

As shown in FIGS. 56A-D, the directly addressable I/O register (address 01) is a 16 bit universal parallel in/out, serial in/out) register that is connected to the calculator processor by the serial-in S-Bus and the serial-out T-Bus. Information is passed non-inverted from the A or B registers bit serial to the I/O register with the I/O instruction OTX φ1. Sixteen lines connected to the parallel outputs of the I/O register provide data out to the internal input, input-output, and output units and to the external output interfaces. (NOTE: each I/O unit or interface may place only 1 TTL load on the output lines.)

Parallel entry to the I/O register is through 12 party lines connected to the 12 least significant parallel inputs. The input lines are negative true with all input interfaces tying to the lines through open collectors. Care must be taken to insure there is no disturbance to the lines while an interface is inactive. Input information is passed inverted to the A or B register bit serially with the I/O instructions LIX φ1 or MIX φ1. (The inversion puts positive true information into the A or B register).

Input information is entered into the I/O register in three ways:

a. Service Request

Entry by the service request method is controlled by a service inhibit flip flop. When the service inhibit flip flop has been cleared with the I/O instruction CLF φ1, a service request may be initiated by returning the SSI (Service Strobe Input) partly line to ground through an open collector on the interface. This signal causes the parallel inputs to be strobed into the I/O register and sends a request for service (QNR) to the microprocessor. The microprocessor prior to receiving a request for service would have been cycling through various instruction paths and checking for a service request after execution of each instruction. Upon receipt of a request for service, the processor interrupts the sequence of instructions it was doing and loads an address into the M-Register which contains the starting address of the service routine. At the same time a signal, SRA (Service Request Acknowledge), turns off the service inhibit flip flp and also sets the single service flip flop which permits only one service interrupt to the process per service strobe input. The single service flip flop is reset when the service strobe is removed. All lines from an interface using the service request method for entering information are inhibited when the service inhibit flip flop is set.

b. Return of Channel Flag After Command is Given to an External Peripheral Device

This method implies the calculator must control the peripheral. That is to say the calculator transmits the indirect address and control enable (CEO) from the "I/O Register and gate interface" section to the interface with the expectation of information being returned by the peripheral through the interface to the I/O register. Because of this expectation, only limited instructions may be performed by the calculator while waiting. The service request method must be inhibited during this wait so that input information is not destroyed by another peripheral using service request.

When a controlled peripheral responds, its flag and data are processed at the interface. The signal CFI (Channel Flag In) causes the loading of parallel data from the interface into the I/O register and clears the control enable flip flop so that the CEO signal is removed from the interface. The calculator can interrogate the control enable flip flop with the instructions SFS φ1 or SFC φ1 to determine when data has been loaded in.

c. Giving the I/O Instruction STF φ1

The instruction STF φ1 as described in (a) sets the service inhibit flip flop inhibiting the service request mode of entry. The STF φ1 instruction also causes a parallel load of the input lines into the I/O register.

The I/O register is used to transfer data and control between the calculator and the directly addressable magnetic card reader (address 02). To record information on a card, the control word and data is transferred from the A-Register to the I/O register. The I/O instruction STCφ2 clocks this information via MLS into a latch located at the card reader. The strobe bit for the recorded data is output to the I/O register from the B-Register. The I/O instruction STFφ2 clocks the strobe latch located at the card reader via MCR. The I/O instruction STFφ1 loads status from the card reader into the I/O register (see 1-C). This status is transferred to the A or B Register where it is processed.

To enter information from the magnetic card reader a control word is transferred from the A-Register to the card reader latch as above. When a strobe is encountered from the card, the card reader sends a signal, MFL, to the I/O Register and gate interface section, which sets the magnetic card flag flip flop. The I/O instruction SFSφ2 is used to determine the state of the magnetic card flag flip flop. When the flip flop is set, data is loaded into the I/O Register with the I/O instruction STFφ1.

The directly-addressable output printer (address 04) requires 26 bits of parallel information from the calculator. Sixteen bits come from the I/O register and 10 bits come from a register at the printer. A 16 bit word with "don' t cares" in the least 6 significant bits is transferred to the I/O register with the I/O instruction OTX φ1. A second 16 bit word is transferred to the I/O register with the instruction OTX φ4. The 10 valid printer bits already in the I/O register overflow into the 10 bit printer register. The significance of the address φ4 in the OTX instruction is that it allows the micro instruction EOW (End of Word) to set the printer enable flip flop after the 16th bit has been transferred. At the end of the printers response it returns a signal (PTF) to the printer enable flip flop clearing it. The printer enable flip flop can also be cleared with the I/O instruction CLF φ4. The state of the printer enable flip flop is checked with the I/O instructions SFC φ4 or SFS φ4.

The directly-addressable output display (address 08) receives information from the I/O register. A 16 bit word is transferred to the I/O register with the instruction OTX φ8. The address φ8 allows the display enable flip flop to be set with the micro-instruction EOW after the 16th bit has been transferred. The display enable flip flop sends a signal DEN to the display indicating information is ready in the I/O Register. The display enable flip flop is cleared with the I/O instruction CLF φ8.

The keyboard operates as described below. 7 bit ASCII assigned keycodes are entered into the calculator by an interrupt process. When a key on the keyboard is depressed the keyboard interface card requests service. Input data is stored along with the request for service on the keyboard interface card. The stored signal for service is gated with the Prevent Interrupt signal through an open collector NAND gate onto the Service Request party line (SSI = Low for service). The giving of Service Request causes the I/O register to be loaded. However, input data from the keyboard interface card is not enabled yet. Thus all status and data inputs are high. This indicates to the CPU that a keyboard is interrupting. An OT × 16 instruction is given by the firmware. The select code of 16 enables the gate of the data input lines by a STF 1 instruction and data is loaded into the I/O register. LIA φ allows data to be taken from the I/O register.

All external peripheral interfaces are indirectly addressed from the four most significant bits in the I/O register. Thus to communicate with an external peripheral, an address (φφφφ excluded) must be loaded into the I/O register. Data and status will be loaded at the same time if the peripheral is to act as a receiver. If the peripheral is to act as a transmitter, only the address and status need be loaded. Next, the I/O instruction STC φ1 sets the Control Enable Out flip flop. This flip flop sends a signal CEO to all external interface slots. The CEO signal and the decoded (from the 4 bit address) address allow the interface to command the peripheral. After the peripheral has responded, information given back to the interface by the peripheral is processed to the I/O register in the manner described above under (b) "Return of Channel Flag After Command is Given to an External Peripheral Device."

The I/O register and gating control circuit mnemonics are given in the following table:

I/O REGISTER AND GATE BOARD ______________________________________ CEO Control Enable Out CFI Channel Flag In CLF Clear Flag COφ, 1,2,3 Code Out DEN Display Enable DIφ, 1,2,3,4,5,6,7 Data In DOφ, 1,2,3,4,5,6,7 Data Out DRC Data Register Clock EBT Eight Bit Transfer EOW End of Word IOD I/O Data KLS Key Lights Strobe MCR Mag Card Reset MFL Mag Flag MLS Mag Latch Strobe PEN Printer Enable POP Power On Pulse PTF Printer Flag Qφ Qualifier Bit φ Q1 do. 1 Q2 do. 2 Q3 do. 3 Q4 do. 4 QFG do. Flag QNR do. Not Request SIH Service Inhibit SIφ, 1,2,3 Status In SOφ, 1,2,3 Status Out SRA Service Request Achknowledge SSI Service Strobe In STC Set Control STP Stop STF Set Flag T-Bus T-Bus TTO T Bus to Output NOTE: ( ) indicates negative true signal ______________________________________

As shown in FIG. 60, when addressing a peripheral device, bits loaded into the 4 most significant locations in the I/O register from the CPU constitute the peripheral address code. As part of the output party line system the address code is routed to all I/O interface slots. Each I/O interface card decodes the 4 line address code to a unique single line for use on that particular I/O card. The binary codes 10 through 15 have been reserved for dedicated peripheral addresses which are used by dedicated keys (from the keyboard) and dedicated I/O drivers. Binary codes 1 through 9 are for general use. Code "0" is a non-addressing code and is used in operations that do not involve addressing a specific peripheral. The following table summarizes the address code assignments:

ADDRESS CODE ASSIGNMENTS ADD 4-BIT ASSIGNED PERIPHERAL RESS CODE ______________________________________ 15 HHHH TYPEWRITER 14 HHHL PLOTTER 13 HHLH 12 HHLL KEYBOARD & KEYBOARD-LIKE PERIPHERALS 11 HLHH 10 HLHL 9 HLLH GENERAL USE; ONE OF NINE SELECTABLE 11 8 HLLL do. 7 LHHH do. 6 LHHL do. 5 LHLH do. 4 LHLL do. 3 LLHH do. 2 LLHL do. 1 LLLH do. USED ON INTERRUPT I/O INTERFACE CARDS φ LLLL WHEN THE INTERRUPT BECOMES ENABLED ______________________________________ The general usage codes (1-9) are decoded outputs from a 4 line to 1 of 10 decoder (SN 7442 for example). It is intended that the codes 1 through 9 be jumper selectable. This would allow the user to select a code for his system peripherals or allow him to use more than one of the same peripheral by selecting different address codes.

Since the I/O register is used to communicate with the internal input, input-output, and output units as well as peripheral devices, a given peripheral' s address code will appear randomly in the I/O register address field with there being no intention of expecting the peripheral to respond: Therefore, a second piece of information is necessary for the I/O interface card to form a unique signal which will indicate to the peripheral to respond. This second piece of information is control information and is described hereinafter.

The I/O interface cards contain TTL compatible logic for manipulating control and data from the calculator and/or the peripheral. All I/O interface cards which are intended to be used with the calculator must provide storage either on the I/O interface card or in the peripheral. Thus data being transferred from the calculator to the I/O card must be stored at the instant the peripheral is requested to respond. Likewise data coming from a peripheral must be stored until the calculator accepts it. This requirement is important and must be considered on all compatible interface cards.

The calculator can supply up to 100 ma. maximum at +5 volts to each I/O interface card. Power exceeding this absolute maximum must be supplied by the peripheral.

The following table lists the pin assignments for all I/O lines at the plug-in slots on the calculator back plane, as viewed from the rear of the calculator, left to right.

EXTERNAL I/O INTERFACE PIN ASSIGNMENTS ______________________________________ 1 A 2 +5 B +5 3 USED C USED 4 USED D 10/20 5 USED E USED 6 DI φ F DO φ 7 DO 1 H DO 2 8 DI 3 J DO 3 9 DI 2 K DI 1 10 DO 4 L DI 4 11 DO 5 M DI 5 12 DO 6 N DI 6 13 DO 7 P DI 7 14 SO φ R SI φ 15 SO 1 S SI 1 16 SO 2 T SI 2 17 SO 3 U SI 3 18 CO φ V CO 1 19 CO 2 W CO 3 20 SSI X SIH 21 CEO Y CFI 22 Z STP ______________________________________

The chart below lists all I/O lines with brief definitions and specifications and FIG. 57 shows the source and relative relationship of the I/O lines. The output address data lines (Co 0-3) transmit the address code along the party lines to all interface slots. These lines will go high and low according to information being shifted in or out of the I/O Register. At anytime a peripheral is addressed the lines will

I/O Line Specification Chart Name of Direc- Voltage of Line Line Definition Action Load/Loading High Low Lines 1 Address Data Transmits a 4 bit address from the Out 1 TTL (1.6ma) ≥2.4v ≤ 44v I/O Register to be recognized by allowed per (CO φ-3) an interface card. (Data = High) interface. 2 Device Ready Indicates calculator is ready for in- Out 1TTL (1.6ma) ≥2.4v ≤.4v 1 formation interchange with an ad- allowed per CEO dressed peripheral. interface (Active State = Low) 3 Device Request Acknowledges receipt of data by a In Loading of 1k re- Must 1e peripheral from the calculator or 6.6ma to the sistor driven (CFI) indicates data is to be input to the interface to + 5v. below calculator. card. use open .4v. (Active State = Low) collector 4 Halt Status Indicates stop key has been de- Out 1 TTL (1.6ma) ≥2.4v ≤.4 1 pressed. Allowed/inter- (STP) (Active State = Low) face. 5 Input Data Receives input data to I/O register. In Loading of 1kRes. Driven 12 (DI φ-7. 6.1ma to + 5v ≤ .4v SI φ-3) (Data = Low) 6 Output Data Transmits Data from the I/O register. Out 1 TTL (1.6 ma) ≥ 2.4v ≤ .4v 12 (DO φ-7, Allowed/inter- SO φ-3) (Data = High) face. 7 Prevent Inter- Indicates data cannot be entered under Out 1TTL (1.6 ma) ≥2.4v ≤.4 1 rupt service request. (Interrupt) Allowed/inter- (OIH) (Active State = Low) face 8 Service Re- Indicates a CPU interrupt is to In Loading of 1k Res. Driven quest (Lo) take place to allow data to enter. 6.6ma to + 5v ≤ .4 1 (SSI) (Active State = Low) ____________________________________________________________ ______________

become steady 1 instruction time (8 μs) before control information is passed to the I/O interface card or before data or status is taken from the I/O interface card and will remain constant until the control information is removed. After the control information is removed, the state of the I/O lines become unpredictable until the next addressing takes place. Address data coming to the I/O interface card is positive true and each interface may place 1 TTL load on each address line.

The output data lines (DO 0-7) output data from the A or B accumulator in 8 bit bytes from the 8 least significant locations in the I/O register to all interface card slots. The logic state is positive true (Data = 1 = High). Each interface card may place 1 standard TTL load on each data line.

The output data status lines (SO 0-3) output status data from the A or B accumulator and are driven from the next four locations above the data out positions in the I/O register. (DO positions = 0 thru 7; SO positions = 8 thru 11). These lines are used for sending additional information to a peripheral. The logic state is positive true. One standard TTL load may be placed on each output data status line. (Special drivers, fast data transfer, and interrupt do not make use of SO 3).

The input data lines (DI 0-7) transmit input data in 8 bit bytes to the 8 least significant bit positions of the I/O register (Locations 0 thru 7) from the I/O interface card. Each "Data In" line has a 1K pull up resistor to +5 volts and under the party line system must be driven low for a logical 1 from open collector gates on each addressed I/O interface card. The logic state is negative true.

The input data status lines (SI 0-3) receive information from the I/O interface cards and transmit it to location 8 through 11 in the I/O register. Each line has a 1K pull us resistor to +5 volts. These lines are used to provide additional information to the calculator about the state of a peripheral. The logic state is negative true.

The negative true "Device Ready" output line (CEO) transmits a control signal, which when combined with an address code will initiate a peripheral response on the addressed I/O interface card. "Device Ready" is controlled by the I/O interface driver and therefore may look different depending upon the driver. For example, when the calculator wishes to transmit data to the I/O interface card or to initiate a peripheral response prior to receiving data from the peripheral, the calculator causes the "Device Ready" output line to go low and stay low until the peripheral response is over and the calculator receives the signal "Device Request" (CFI) from the I/O interface card. The "Device Ready" flip-flop always receives a clear signal whenever the I/O register completes a parallel load.

The "Device Request" party line CFI when driven low from an open collector gate on the I/O interface card will cause the loading to parallel input information into the 12 least signficant locations of the I/O register. The active state of the line is low (negative true).

The peripheral flag, indicating to the I/O interface card the peripheral has received data/control or is ready to input data, is gated through an open collector nand gate onto the "Device Request" (CFI) party line. The open collector gate is enabled by the I/O interface card's address and "Device Ready" (CEO). The "Device Request" line is pulled up inside the calculator by 1K resistor to +5 volts.

The "Device Request" (CFI) signal must stay low until "Device Ready" (CEO) has been cleared (goes high). At this time data transfer has terminated and peripheral's flag and control must be cleared in preparation for the next pass. Since a parallel load in the I/O register causes the "Device Ready" flip-flop to receive a clear signal, when a "Device request" (CFI) is entered, a parallel load takes place and afterward "Device Ready" (CEO) is cleared. The calculator uses "Device Request" in its general mode of data transfer.

The "Halt Status" output line (STP) is a line that goes low when the STOP key on the calculator is depressed. It will stay low for the duration of the key depression. One standard TTL load may be placed on this line by each I/O interface card.

The "Prevent Interrupt" output line (SIH), when low indicates the I/O interface card that a request for service must not be given to the calculator. One standard TTL load may be placed on this line by each I/O interface card.

The "Service Request" (Lo) line (SSI), when driven low causes the loading of parallel input information into the 12 least significant locations of the I/O register and causes a CPU interrupt for service. The peripheral's request for service is gated with the "Prevent Interrupt" (SIH) line onto the "Service Request" party line through an open collector nand gate. A 1K a pull-up resistor to +5 volts is connected to the line inside the calculator.

The general format for all data transfer consists of 8 bit parallel bytes. Other data formats are handled by specially developed drivers, such as the ROM plug-in module employed for driving the typewriter.

The state of a peripheral is generally checked before attempting an output. This is done by first inhibiting the interrupt system. The address of the I/O interface card is shifted into the I/O register. The decoded address code enables the open collector gates on the I/O interface card. The status of the peripheral is passed to the "Status In" lines and loaded into the I/O register with an I/O instruction issued by the calculator. The I/O register information is transferred to the A or B accumulator and processed. If the peripheral is ready, the output data word consisting of the address code, output status (if necessary) and the eight bit data byte is formed in the A or B accumulator. The output data word is transferred to the I/O register after which the "Device Ready" (CEO) flip-flop is set. The I/O interface card receives the data, address code and "Device Ready" and a peripheral response is initiated. The calculator interrogates the state of the "Device Ready" flip-flop to determine when the I/O interface card has received the information and the peripheral response is done. The peripheral I/O interface card signals the calculator it is done by transmitting the "Device Request" (CIF) signal to the calculator. The output waveforms are shown in FIG. 62.

Before inputing data from the I/O interface card it is necessary to determine if the peripheral has responded and is ready to input data. After a peripheral response has been initiated, as described previously, the calculator waits for the "Device Request" (CFI) which loads the data onto the I/O register and clears the "Device Ready" (CEO). The calculator checks the state of "Device Ready" and when it goes false (CEO = HIGH), the calculator knows data is present in the I/O register and proceeds to shift it into the A or B accumulators for processing. The input waveforms are shown in FIG. 61.

When blocks of data are to be transferred between a peripheral and the calculator, the interrupt is turned off, and transfer rates as high as 100,000 bits/sec may be possible. Before either input or output of a block of data can start, it is necessary for the calculator to check the status of the peripheral to see if it is turned on and ready. The address locations of the I/O register will remain unchanged during the block transfer. A single I/O instruction shifts the 8 bit byte of data from the 8 least significant locations in A or B to the 8 data locations in the I/O register; gives: Device Ready (CEO goes low) 120 nanoseconds after the shift is completed; and shifts the 8 most signficant bits in A or B to the 8 least significant locations in A or B in preparation for the next transfer. (Note the address and status field in the I/O register are not disturbed in the shifting). "Device Ready" stays true (low) until the peripheral has received the data and is ready for more. The I/O interface card then returns "Device Request" (CFI) to the calculator. The receiving the "Device Request" (CFI) to the calculator causes loading of the parallel input party lines into the input status and input data location of the I/O register, and clears the "Device Ready" signal (CEO goes high). The logic sense of "Device Ready" is observed by the calculator and when it goes false (CEO = High) the CPU proceeds to output the next 8 bit byte of data.

If the output I/O interface card is not returning information on the input lines all input lines will be high when the loading, described in the preceeding paragraph, takes place. Therefore, if at the beginning the code in the output status field is being used by the I/O interface card and must remain something other than all high it will be necessary for the I/O interface card to receive the output status from the calculator and return it back to the status inputs so that when "Device Request" occurs the status field does not get changed in the I/O register.

Input: After determining if the peripheral is ready to start transferring a block of data the calculator turns off the interrupt and shifts the address code into the I/O Register. (The address code remains unchanged during the block transfer). The "Device Ready" is given (CEO = Low) to the calculator when the 8-bit data byte is ready for input. The "Device Request" signal causes the input data and status to be loaded into the I/O register and casues "Device Ready" to go false (CEO = High). The calculator by checking when "Device Ready" goes false knows the data has been loaded. A single I/O instruction shifts the 8-bit data byte from the I/O register into the 8 most significant locations in the A or B accumulators (Shifting the previous information in A or B 8 places to the right) and causes "Device Ready" to go true (CEO = Low) 120 ns after the last bit has been shifted into A or B. As before if output status is to be retained on the I/O interface card it must be returned to the I/O register upon each input data transfer. Wave forms illustrating high speed operations are shown in FIGS. 63 and 64.

The calculator software makes use of the interrupt system in two different manners. The first is for remote keyboard like peripherals.

These are those peripherals which logically resemble the calculator keyboard. Only 7 bit ASCII assigned keycodes are recognized by the calculator. The interrupt takes place by the peripheral indicating to the I/O interface card that a request for service exists. Input data must be stored along with the request for service on the I/O interface card or in the peripheral itself. The stored signal for service is gated with the "Prevent Interrupt" signal through an open collector NAND gate onto the "Service Request" party line (SSI = Low for service). The giving of "Service Request" causes the I/O register to be loaded. However, input data from the I/O interface card is not enabled yet. Thus all status and data inputs are high. This indicates to the CPU that a keyboard-like peripheral is interrupting and address code 12 is shifted into the I/O register. The decoded address 12 on the I/O interface card enables the gates to the data in lines and data is now loaded into the I/O register. After the data has been taken from the I/O register address 12 is again put into the I/O register and Device Ready is given as a 360 nanosecond pulse to clear all stored keyboard-like requests for service. This implies all keyboard-like periherals must be user controlled such that only one interrupt at a time is taking place. The second is a nonkeyboard-like peripherals.

These peripherals will output or enter standard ASCII codes for data by using a special ROM (other ROMs may be developed to handle different codes). When a request for service is given to the I/O interface card by a peripheral the request and all data must be stored until serviced by the calculator. The interface card may have any of 9 addresses (1 thru 9). The stored request for service is gated with "Prevent Interrupt" through an open collector NAND gate onto the "Service Request" party line. At the time "Service Request" is recognized address "φ" is gated with the stored request for service through an open collector onto an input data or status line which corresponds with the address of the I/O interface card. For example, "Data In" φ which is the 1st position in the I/O register represents card address 1, and 2nd position is card address 2, etc. When the I/O register is loaded as a result of the "Service Request" the interrupting I/O car's address is loaded into the I/O register and "Prevent Interrupt" enabled (SIH = Low). The contents of the I/O register are processed by the CPU which then shifts the interrupting card's address into the I/O register. The address enables the gates to the data-in lines and data is loaded into the I/O register. After the data is processed by the CPU the interrupting card's address is shifted from the CPU into the I/O register and a 360 nanosecond "Device Ready" pulse (CEO = Low) given to clear the stored request for service on the I/O interface card, after which the "Prevent Interrupt" is disabled and the next interrupt allowed to take place. Under this system, multiple interrupts may take place without consequence. Each will be serviced in turn from low to high address psotion. An interrupting peripheral may also interrupt to request output data from the I/O register. The interrupting process is the same as above except the calculator transmits data rather than receives data. FIG. 65 shows waveforms illustrating the interrupt.

The following table lists the general I/O instruction set and the associated codes: I/O INSTRUCTION SET INSTRUC- NAME TION INSTRUCTION CODE EXECUTION TIME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ____________________________________________________________ ______________ STF 9 μs H H H H -- H L H H H H SELECT CLF 9 μs H H H H -- H H H H H H do. SFC 9 μs H H H H -- H H/C H H H L do. SFS 9 μs H H H H -- H H/C H L H L do. CLC 9 μs H H H H -- H H/C H L H H do. STC 9 μs H H H H -- H H/C H H L L do. OT* 15 μs H H H H A/B H H/C L L H H do. LI* 15 μs H H H H A/B H H/C L H L H do. MI* 15 μs H H H H A/B H H/C L L L H do. ____________________________________________________________ ______________

The following describes the function of each I/O instruction with the 5 allowable select codes.

______________________________________ STF <SC> Set the flag. STF is a 240 nanosecond positive true pulse which accomplishes the following with the various select codes. STF φφ Not used by the calculator. STF φ1 a. Sets the "Service Inhibit" flip-flop to the true state (SIH = Low; interrupt not allowed). b. Causes parallel input data and status to be loaded into the I/O register. STF φ2 Generates a 240 nanosecond positive true MCR pulse for the magnetic card reader. STF φ4, φ8, 16 Not used by the calculator. CLF <SC> Clear the flag. CLF is a 240 ns positive true pulse which accomplishes the follow- ing with the various select codes. CLF φφ Not used by the calculator CLF φ1 a. Clears the "Service Inhibit" flip-flop to the false state. (SIH = High; interrupt allowed.) b. Loads address locations in I/O register with φ's. (φ= Low) c. Clears "Device Ready" flip-flop (CEO = High). CLF φ2 Clears magnetic card reader flag flip- flop. CLF φ4 Clears "Printer Enable" flip-flop (PEN = Low). CLF φ8 Clears "Display Enable" flip-flop (DEN = High). CLF 16 Generates a 240 nanosecond positive true KLS pulse. SFC <SC> H/C Skip if flag clear. SFC is a 240 ns positive true pulse which accomplishes the following with the various select codes. If C is given a 240 nanosecond CLF pulse is given after SFC. SFC φφ Causes the next instruction to be skipped if the STOP key has not been depressed. SFC φ1 Causes the next instruction to be skipped if Device Ready is true (CEO = Low). SFC φ2 Causes the next instruction to be skipped if the magnetic card reader flag flip- flop is clear. SFC φ4 Causes the next instruction to be skipped if the printer enable flip-flop is clear. (PEN = Low). SFS <SC> H/C Skip is flag set. SFS is a 240 nanosecond positive true pulse which accomplishes the following with the various codes. If C is given then a 240 nanosecond CLF Pulse is issued after SFS. SFS φφ Causes the next instruction to be skipped if the STOP key is depressed. SFS φ1 Causes the next instruction to be skipped if "Device Ready" is false (CEO = High). - SFS φ2 Causes the next instruction to be skipped if the magnetic card reader flag flip-flop is set. SFS φ4 Causes the next instruction to be skipped if the printer enable flip-flop is set (PEN = High). CLC <SC> H/C Clear Control. CLC is a 240 nanosecond negative true pulse and is not used by the calculator. If C is given then a 240 nanosecond positive true CLF pulse is given after CLC. STC <SC> H/C Set the Control. STC is a 240 nanosecond posi- tive true pulse which accomplishes the following with the various select codes. If C is given a 240 nanosecond CLF pulse is issued after STC. STC φφ Not used by the calculator. STC φ1 Sets the "Device Ready" flip-flop (CEO = Low). STC φ2 Generates a 240 nanosecond positive true MLS pulse for the magnetic card reader. STC φ4, Not used by the calculator. φ8, 16 OTX <SC> H/C Output A or B causes data bits from A or B to be shifted to the I/O register and accomplishes the following with the various select codes. If C if given, a 240 nanosecond CLF pulse is given after OTX is executed. OTX φφ The 8 least significant bits in the A or B register are shifted non-inverted to the 8 least significant locations in the I/O register, and 120 nanosecond after the 8th shift the "Device Ready" flip-flop is set (CEO = Low). The 8 most significant bits are shifted right 8 places and the least 8 significant bits are recirculated to the 8 most significant locations in the A or B registers. The 8 most signi- ficant bits in the I/O register are un- touched. OTX φ1 Sixteen bits from the A or B re- gister are shifted non-inverted to the I/O register. The data in A or B recirculates. OTX φ2 Not used by the calculator OTX φ4 Same as OTX φ1 and in addition, 120 ns after the 16th bit has been shifted nanoseconds printer enable flip-flop is set. OTX 08 Same as OTX φ1 and in addition, 120 nanoseconds after the 16th bit has been shifted the display enable flip-flop is set. OTX 16 Same as OTX φ1 and in addition, 120 nanoseconds after the 16th bit has been shifted the 240 nanosecond KLS signal is generated LIX <SC> H/C Load into A or B. Loads data bits from the I/O register into the A or B register and accomplishes the following with the various select codes. If C is given, a 240 nanosecond CLF pulse is given after LIX is executed. LIX φφ The eight least significant bits in the I/O register are shifted inverted to the eight most significant locations of A or B, and 120 nanoseconds after the 8th shift the "Device Ready" flip-flop is set (CEO = Low). A or B is shifted right eight places as the I/O register data comes in. The 8 most significant bits in the I/O register are untouched. LIX φ1 The 16 bits of the I/O register are trans- ferred inverted to the A or B register. Data in the I/O register is lost. LIX φ2, φ4, Not used by the calculator. φ8, 16 MIX <SC> H/C Merge into A or B. Merges data from the I/O register into A or B registers and accomplishes the following with various select codes. If C is given, a 240 nanoseond CLF pulse is given after MIX is executed. MIX φφ The eight least significant bits in the I/O register are merged with the eight least significant bits of the A or B register and shifted to the 8 most signi- ficant locations of A or B; 120 nanosecond the merge takes place the Device Ready flip-flop is set (CEO = Low). A or B shifts right 8 places as the data is merged and shifted to the most significant locations. The 8 most significant bits of the I/O register are untouched. MIX φ1 The 16 bits of the I/O register are merged with the 16 bits of the A or B register and contained in the A or B register. ______________________________________

MIX φ2, 04, 08, 16 Not used by the calculator. Examples of various drivers which transfer data are given below:

Example 1: Typical Subroutine to Get Status of I/O Device. ____________________________________________________________ ______________ Calling Sequence: LDB Select Code JSM Stat Stat STF 1 Turn off the interrupt system. OTB 1 Load I/O register with select code. STF 1 Load I/O register with status of I/O device. LIA 1 Load A-Register with status information CLF 1 Turn on interrupt. - RET Return. ____________________________________________________________ ______________

Example 2: Typical Subroutine to Output an 8 bit character. ____________________________________________________________ ______________ Calling Sequence: OTA 1 Output 16 bits to the I/O register. STC 1 SFS 1 Loop until I/O flag is set by the JMP *-1 output device. CLF 1 ____________________________________________________________ ______________

Example 3: High Speed Output Where the Calculator is Faster than Output Device. ____________________________________________________________ ______________ Calling Sequence ST* I -(Number of 16 bit words to be output) + 1 ST* J Address of first word in the array. LDB SC Select Code JSM OUT2 OUT2 JSM STAT Get status of output device RAR 9 and position it. ____________________________________________________________ ______________

Example 4A: Typical Subroutine to Input an 8-bit Character. ____________________________________________________________ ______________ Calling sequence is: LDB Select code JSM In . . . Return is made with the data in the A Register. In STF 1 Turn off interrupt system OTB 1 Load I/O register with the select code STC 1, C Pulse the flag and turn interrupt system on JSM STAT Get status off the input device RAR 9 and position it. SAP *-2, C If device is busy then continue to loop SAR 7 else position data bits RET Return. SAP OUT2 If device is busy, continue to loop STF 1 Turn off interrupt system. OTB 1 Output select code LDB 1 B➝Counter for number of words to be output LDA J, I Load next data word SEC *+1, C E➝φ OTA φ Output 8 bits from A SFS 1 Loop until device sets JMP *-1 flag. SEC *-3, S If E=φ and E➝J then loop to output last 8 bits ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished. CLF 1 Turn on interrupt system RET Return ____________________________________________________________ ______________

Example 3B: If the Output Device is Faster than the Calculator then Fewer Instructions can be Used. ______________________________________ OTA φ Output first 8 bits OTA φ Output second 8 bits. . . . ______________________________________

Example 5A: High speed input where the calculator is faster than the input device. ____________________________________________________________ ______________ Calling sequence: ST* I -(Number of 16 bit words to be input) + 1 ST* J Address LDB SC Select code JSM In2 In 2 JSM STAT Get status of input device RAR 9 and position it. SAP In2 If device is busy, continue to loop STF 1 Turn off interrupt system OTB 1 Output select code STC 1 Command device to read LDB I R➝Counter for number of words to be input SEC *+1, C E➝φ SFS 1 Loop until input JMP *-1 device sets flag LIA φ Load 8 bits from I/O register SEC *-3, S If E=φ and E➝1 then loop to input last 8 bits STA J, I Save data word in array ISZ J Increment array address pointer RIB *-7 Increment count and loop if not finished. CLF 1 Turn on interrupt system RET Return ____________________________________________________________ ______________

Example 5B

If the input device is faster than the calculator then the number of instructions can be reduced.

Lia φ -- input first 8 bits

Lia φ -- input second 8 bits

All output I/O interface cards which are to be fully interchangeable with both the present and other calculators must have storage either on the I/O interface card or in the peripheral to which information is being transmitted. FIG. 66 illustrates the logic used to interface an X-Y plotter which has storage on the I/O interface card.

Blocks (A) and (B) are the storage latches which store information coming from the I/O register. When the output of gate (C) goes high, data is latched; when low, the outputs of the latch track the inputs. Gates (D) decode the address code (14 = 111φ) and pass it positive tru to gate (E). "Device Ready" (CEO) is also passed positive true to gate (E). Gates (H) are open collector and pass status and "Device Request" (CFI) onto the input party lines.

An example of a calculator output would be: Output the address 14 which enables status gates (H) and see if the power is on. If on, output address, status, and data to gates (A), (B), and (D). The output of (C) is low allowing data and status to pass. Next give "Device Ready" (CEO = Low); this enables flip-flop (G), clocks flip-flop (F) which causes (A) and (B) to latch, and sends control to the peripheral. The peripheral acknowledges receipt of control by returning FLAG (FLAG = High) in a busy state this continues to keep (A) and (B) latched and clears control flip-flop (F). When the peripheral is done acting, the FLAG is returned to the not busy state (FLAG = Low) which clocks flip-flop (G) and cuases output at (C) to go low enabling (A) and (B). The output of (G) drives the CFI gate which has been enabled from (E) and CFI goes low. CFI is received by the calculator which responds by returning CEO high. This causes the output of (E) to go low, clearing flip-flop (G) and returning CFI high. This completes 1 output cycle.

All input I/O interface cards which are to be fully interchangeable with both the present and other calculators must have storage either on the I/O interface card or in the peripheral from which information is being received. FIG. 67 illustrates the logic required on a general purpose interface card with storage.

Block (A) is used to store information coming from the peripheral. (B) stores status coming from the I/O register which may be needed by the peripheral. The output tracks the input whenever the enable on the latch is low. Block (C) decodes the address code into one of 10 addresses which are jumper selectable. An example of a calculator input would be as follows: the address code would be decoded by (C); the calculator would load status through the open collector input status gates (D). If the peripheral is on and ready, the address code and output status (if necessary) would be sent to (B) and (C). The decoded address is passed, positive true, to gate (E). The enable at (B) is low so that status is passed to the peripheral. The "Device Ready" is given (CEO = Low) and comes to (E) positive true. The output of (E) clocks flip-flop (F) through gate (H). The output of (F) gives control to the peripheral and also enables (A) to receive data. The peripheral responds in a busy state (FLAG = High). When data is ready to be input the FLAG is driven low. Data is latched when the FLAG goes low in (A). Also when FLAG goes low, (G), having been enabled by the output of (H), is clocked driving (J) from its Q output. (I) is enabled by the output of (H) and so CFI is driven low. Data is loaded into the I/O register from open collector gates (I) and CEO driven high as a result of the calculator receiving CFI. This clears flip-flop (G) and disables the input gates (I) completing an input cycle.

FIG. 68 illustrates the logic required, on an I/O interface board, to input using the interrupt.

A power preset circuit, block (A), will be necessary on this card to prevent an interrupt when the peripheral power is turned off or on. This can usually be done by sensing the peripherals' +5 volts and presetting when the voltage drops below 3 to 4 volts.

An example of a calculator interrupt would be as follows: (B) may be clocked at any time storing the data is (E) and (F). The calculator enables the interrupt to take place by making "Prevent Interrupt" false (SIH = High) and outputting address φ to decoder (L). (G) is enabled when SIH goes high through gate (M) causing SSI to be driven low. The calculator responds by loading the I/O register. Gates (H) are inhibited by gates (N) and (J) and gate (K) is enabled because of address φ, thus DIφ is the only true signal loaded into the I/O register. The calculator interprets this to mean the I/O interface card at address 1 has caused the interrupt. The calculator outputs address 1 to the decoder which enables gates (H) with (N) and (J) and then loads the data. After the data is stored the calculator outputs address 1 and sends "Device Ready" (CEO = Low) as a 360 nanosecond pulse which is used to clear (B) through gates (O) and (D). This completes an input cycle.

KEYBOARD INPUT UNIT

The keyboard input unit is shown in FIGS. 69A-D and 70. It includes a contactless keyboard of the type shown and described in U.S. Patent application Ser. No. 74,949 entitled NONCONTACTING KEYBOARD, files on Sept. 24, 1970, and assigned to the same assignee as this patent application. The contactless keyboard is made up of an array of printed circuit transformers. Each transformer has its secondary and primary interlaced in a spiral coil as shown in FIGS. 71 and 72. The secondaries of all the coils are tied in series to form the sense line. The primaries of the coils are arranged in separate pairs. Each coil is connected in series, with opposite polarity, to its pair as shown in FIG. 73. Every pair has a drive and sink line, which is being selected and driven by the scanner.

Centered above each coil is a metal disc at the end of the key shaft. When a key is depressed the disc proximates the coil. The disc acts like a shorted turn, reducing the coupling of the coil, and unbalancing the pair. This unbalance is amplified by the comparator, when it is greater than the on bias. The comparator triggers the one shot, which turns off the scanner and lowers the on bias. The scanner remains at its present state, which corresponds to the drive and sink line of the key depressed. This state is the keycode of the key pressed. When the key is released a spring retracks the key and disc. When the unbalance is less than the new bias, the comparator turns off and the scanner starts again ready for a new key. The two bias levels give the key mechanical hysteresis.

When two keys are depressed the first one down will be entered, and as long as a key is down no other key can be entered. An exception is when the other key is its pair. In this case the two keys will cancel each other. When the first key is released, the second one will be entered. When the first key is released, while more than one other key is down, the next key to be entered will be the next in the scan sequence, not necessarily the second key down.

For the keyboard to work each pair of primary coils must be balanced. To balance a pair of coils the following rules should be used when laying out the printed circuit board:

1. Sense lines must run in pairs as close together as possible. They should be thin traces.

2. The sense windings of a pair of coils can be anywhere on the sense line. For best results they should be close.

3. Drive lines should be in pairs when possible. Drive clamp and source lines should be grouped together well away from the sense lines. When a drive line crosses a sense line it should be at right angles.

4. Connect to spiral so to add a turn (or part of a turn) not to subtract. Try to duplicate additional turns on a spiral pair. Connect to spiral at a right angle, from a distance.

5. For a pair of spirals separated by some distance, run the common connection away from the sense line and in the drive grouping.

6. Check each pair of spirals for errors in drive or sense polarity. This can cause either an incorrect code (least digit), or a constant full output. One method to check for proper polarity is to assign current direction for both drive and sense. Then at each spiral check for proper polarity. This is illustrated in FIG. 74.

OUTPUT DISPLAY UNIT

Referring to FIGS. 79A-D, there is shown the hardware associated with the calculator display. The display comprises a single register 400 of sixteen alphanumeric characters, each character position of which is a seven row by five column matrix of light emitting diodes (LED). Register 400 is divided into four guadrants 402 of four character positions each. In addition to the display hardware illustrated, the complete calculator display system comprises bit patterns stored in the calculator ROM, a firmware display routine, and an I/O register, all of which are described in detail elsewhere in this application. The firmware display routine reads a particular bit pattern, generates a column address 406 to position the bit pattern on the display register 400, and transfers the bit pattern and column address to the I/O register. The display hardware then decodes the column address and turns on each LED as selected by the bit pattern. This process occurs once for each scan of each of the eighty columns of the display. The complete display is scanned approximately sixty times per second.

Inputs required for the display hardware are: seven bits of character data 404, a seven-bit column address 406, and an enable signal 408. These signals are positive true logic except for the enable signal 408 which must be zero to enable the display.

The character data 404 is applied through character data inverters 410 to each of four sets of row drivers 412 (eg. row one character data is applied to all four row one drivers, etc.). The five least significant bits of the column address 406 are decoded by the 1-of-20 decoder 414 and turn on one of the column drivers 416. The two most significant bits of column address 406 are applied to the 1-of-4 decoder 418 which turns on one of the quadrant gates 420 when the enable signal 408 is received. The LEDs at the intersections of rows selected by character data 404 and columns selected by column address 406 are then forward biased and emit light.

The 1-of-4 decoder 418 has a fourth input fed by the retriggerable monostable multivibrator 412. In the event the enable signal 408 remains on for approximately five hundred microseconds, the retriggerable monostable multivibrator 422 changes state and turns off the 1-of-4 decoder 418, thereby acting to protect the LED matrix and other circuit components from high DC currents.

MAGNETIC CARD READING AND RECORDING UNIT

The magnetic card reading and recording unit is shown in the block diagram of FIG. 75 and in the detailed schematic diagram of FIGS. 76 and 77. The manner in which it interacts with the calculator and operates to record and load secure and unsecure programs and to separately record and load data is shown and described in the block diagram of FIG. 78.

Operation of the card reader is largely automatic. It is only necessary to specify the type of operation and the limits desired. These commands are entered via the calculator keyboard. The calculator then determines the necessary commands required to cause the magnetic card reader to perform the desired operation.

Several modes of operation are possible. Programs can be recorded on magnetic cards and loaded back into the calculator. Similarly, program and data information can be recorded and loaded, or data alone. Very long programs or blocks of data can be stored on several cards. The information is loaded back into the calculator by inserting the cards into the reader in the same sequence as they were recorded. The proper linking of the information stored on the cards is automatically performed by the calculator.

Information is stored on the magnetic card in 3 bit bytes. Three tracks record the information and a fourth track provides a timing mark. The card reader automatically begins and terminates the recording, irrespective of the length of card used. Different card lengths can be mixed together without affecting the operation of the reader. Cards may be interchanged from one calculator to another.

No mechanical switches are used in the card reader. The only moving part is the card drive motor and capstan. The mechanical assembly and electronics assembly are modular and can be replaced as separate and independent units in the calculator.

OUTPUT PRINTER UNIT

Several methods have been described for producing printed characters by thermal means (see particularly U.S. Pat. No. 3,161,457 issued to H. Schroeder et al.) but they typically employ a rectangular matrix of resistors to form an entire character at once. Commercial versions of this sort of printer are marketed by National Cash Register and Texas Instruments. As described in Schroeder's patent, a matrix five elements wide and seven elements high is typically employed.

The output printer unit employed in this calculator is constructed as shown in FIGS. 82-89. It includes a row of print elements distributed linearly across a printing head, as shown in FIG. 85, to print a 16-character line. Each print element is an electrical resistor, of a size and shape intended to produce a dot on thermally-sensitive paper moved at right angles to the line of print elements. Dots are formed in the conventional manner by pulsing the resistor element with a pulse of electrical current, which raises its temperature by joule heating.

Each of the sixteen characters of each line is formed in a 5 × 7 dot matrix. For example, as illustrated in FIG. 88 the letter A is produced by printing the darkened dots in the top row and then stepping down to the next row, etc.

Each line of print contains sixteen 5 × 7 matrices. The matrices are comprised of seven rows of 80 dots spaced in five dot groups to produce sixteen characters. The printer produces each line of print by printing the top row of all sixteen characters and then stepping down to print the second row and so on until all seven rows are printed. Three blank steps are then added to produce the space between lines.

Each of the seven rows of printing contains 80 dots (5 for each of the sixteen characters) which may or may not be printed. This requires that eighty information bits be supplied for each row printed. To accomplish this, each row is split into four groups of twenty dots (four characters). (Since the I/O Register of the calculator is only sixteen bits long an extra ten bit shift register is contained in the printer hardware.) Each group of 20 bits is transmitted to the printer along with the group number by the I/O register and is printed when the printer enable signal is given. The printer then prints that group of dots and returns a printer flag signal to the calculator. The next group of information is then supplied until all 28 groups have been printed. The three step commands are then given to provide the space between lines.

The printer requires the following information to print any group of dots:

1. Dots to be printed,

2. Group number, and

3. Printer enable signal.

As shown and described in the flow chart of FIG. 89, this information is transmitted to the printer through the calculator I/O register. Since the total number of information bits needed is greater than the I/O register's length, two 16-bit words are transmitted to the printer. The first 16-bit word contains the dot patterns for characters 1 and 2 as shown in the following table: ##SPC291##

Character one is contained in bits S02-S00 and D07, D06 with the left dot in bit S02 and the right dot in D06. Character 2 is contained in bit C03-C00 and S03 with the left dot in C03 and the right dot in S03. When the I/O register is loaded with the second 16-bit word these bits will appear in the internal 10-bit shift register. The second 16-bit word contains the dot pattern for characters 3 and 4 and the group number as shown in the following table: ##SPC292##

Character 3 is contained in bits S02-S00 and D07, D06 with the left dot in S02 and the right dot in D06. Character 4 is contained in bits C03-C00 and S03 with the left dot in C03 and the right dot in S03. The group number is contained in bits D00 and D02. Groups are number as follows:

GROUP PRINTED CHARACTERS D01 D00 ______________________________________ From Left to Right 1 1, 2, 3, 4 0 0 2 5, 6, 7, 8 0 1 3 9, 10, 11, 12 1 0 4 13, 14, 15, 16 1 1 ______________________________________

When group 4 is detected the printer automatically steps to the next line. The time interval between printer enable and the return of printer flag is extended to allow the system to physically move.

The printing speed is given in the following table:

Group 1 8 ms Group 2 8 ms Group 3 8 ms Group 4 18 ms Row 1 42 ms Row 2 42 ms Row 3 42 ms Row 4 42 ms Row 5 42 ms Row 6 42 ms Row 7 42 ms Space 18 ms Space 18 ms Space 18 ms Total Time to Print 1 line 348 ms Lines per second 2.87 ms

As shown in FIG. 82, paper is loaded into the output printer unit by lifting the wire bucket cover 220' and placing a roll of paper 222' with the free end into the paper bucket formed by the front and rear bucket halves, 224' and 226' respectively. The only care needed by the operator is to be sure that the paper uprolls forward from the bottom. The wire bucket cover performs a dual function of keeping the free end of the paper in the bucket while loading and after the paper is loaded prevents the free end from reloading itself through the mechanism.

The weight of the paper then stretches the rubber belts 228' and the roll of paper rolls forward until it rests against the paper guide 230'. The paper rolls forward due to the "downhill" slope of the belt from the top of the rear idler pulley 232' to the bottom of the paper guide. With the roll of paper in the position described above the belts moving forward, the free end of the paper is constrained by the belts, paper guide and roll to move below the paper guide and between it and the belts.

The belts are driven by the drive pulley 234' which is in turn driven by a gear set from the platen 236'. The platen is driven by the motor 238' via a belt and gear set. The diameter and speed of the platen is such that its surface speed is approximately 5 percent faster than that of the belts to insure that the paper is always under tension after loading is completed. The drive and rear idler pulleys are crowned so that the belts will be self-centering. The front idler pulley 270' is flat and serves to keep the lower portion of the belt out of the bucket area.

The print head 242' is pressed against the paper and platen by means of a spring, hence it is necessary to remove the print head from the platen while loading paper. This is accomplished by the head lifter and paper deflector 244' such that when it is rotated on its axis it cams the print head off the platen and positions a small plate in the path of the paper which guides the paper up and between the platen and print head.

The paper is guided through the mechanism while loading and while the printer is working by edge guiding the paper. Ordinarily paper does not lend itself well to edge guiding due to its very low compressive strength. To overcome this the paper is bent around the convex bottom surface of the paper guide and the belt, which is under tension, is very near the edge, thereby preventing the paper from buckling. The relationship of the paper, paper guide and belts can be seen by looking at Section AA of FIG. 83.

When selecting materials for the various parts of the loading mechanism it is important to be sure that the coefficients of friction between the various parts are compatible. The C.F. between the paper and paper guide should be low relative to the C.F. between the paper and belts in order that the belts can drive the paper through the mechanism. Similarly, the C.F between the paper and platen should be high relative to the C.F. between print head and paper in order that the paper can be driven through while printing. In addition, the drag introduced by the belt and paper guide due to the paper moving faster than the belt while printing must not be so great as to tear the paper or impose an impossible load on the motor.

The right half of top panel 90 of the calculator housing is hinged at the back and provided with a handle 246 at the front so that it may readily be raised by the user and stopped at an oblique upright position to expose and facilitate replenishment of the supply of thermally-sensitive paper for the output printer unit and also to serve as a music stand for holding operating or program-running instructions or any other material the user desired. A transparent plastic retainer is mounted on the underside of the hinged right half of the top panel 90 to hold such material.

POWER SUPPLY

The power supply system employed in the calculator is constructed as shown in FIGS. 90-96. As shown in FIG. 90, a centertapped transformer secondary is connected to supply the unregulated DC voltages indicated. Referring to FIG. 91, the AC voltage from the transformer is rectified to diodes CR1 and CR2 and filtered by capacitor C1. The output of this rectifier/filter circuit is nominally 19 volts DC at 2.7 amps with a 2 volt peak to peak ripple. Q1 and Q2 serve as a switch to connect the five volt output bus to the 19 volt unregulated supply through inductors L1 and L2. CR3 serves to clamp the input of L1 to ground when Q1 and Q2 are switched off. Current flow in L1 and L2 is 0substantially constant and equal to the load current.

Loss in high current transistor Q2 is minimized because Q2 can be completely saturated. Loss in driver transistor Q1 is minimized because Q1 can also be saturated. Resistor R7 limits the maximum drive current to Q2. Losses in R7 can be minimized by proper positioning of the tap on L1 consistent with transistor parameters and circuit requirements.

IC1 is a linear differential amplifier integrated circuit to drive Q1 and Q2. ANy differential amplifier with sufficient voltage capability and bandwidth will work. Since the amplifier employed is linear, R7 and R4 have been included in the circuit to provide sufficient hysteresis for reliable switching. This hysteresis stabilizes the switching frequency and thus stabilizes the switching losses.

Because hysteresis has been added to the circuit, a significant ripple signal (at switching frequency) must be present on the feedback signal to the amplifier. This need for a ripple signal limits the amount of capacity that can appear between the output of L1 and ground. L2 serves to isolate this point from the rest of the system. The amount of capcitance that can appear between the output of L2 and ground is essentially unlimited and significantly reduces power supply ripple, and greatly improves response to load transients.

The second winding of L2 is a path for the feedback from the remote sensing. The required ripple signal is added to the feedback signal by transformer action in L2. Another possible configuration is shown in FIG. 96.

The power supply also includes an overvoltage crowbar circuit (Q4, CR4, and R9) and a short circuit shut-down circuit (using Q5). In the event that the +5 volt bus is grounded, or the crowbar is triggered, Q5 saturates and locks IC1 off.

The resistor R8 makes a current generator of IC1. Resistors R5 and R6 discharge the bases of Q1 and Q2, respectively. IC2 and its associated components generate a "power on pulse," POP, to initialize the instrument. IC1 is referenced and powered from an external +12 volt supply. Powering the IC from +12 rather than the unregulated +19 reduces power dissipation in IC1.

The +24 volt supply of FIG. 92 is referenced by the +16 volt supply with the amplifier common returning to +12 volts to minimize power loss and voltage stress in IC1 of FIG. 92. The +12 volt supply of FIG. 93 references the -12, +5, and +16 supplies directly. The +12 amplifier IC1 of FIG. 93 may be biased either from the unregulated supply for the +12 volt supply or from the operating +16 volt supply. Diodes CR5 and CR6 determine the appropriate source. This provides a greater power supply margin for the +12 volt supply. Similarly the +16 volt amplifier is biased from the +20 to give that supply greater margin.

All supplies except the +20 volt supply are current limited. The +24 volt supply is current limited at a value greater than the rating of its series fuse. If a short circuit occurs in the +24 volt supply, it will current limit until the fuse opens. The average current from this supply is 1.1 amps with transients to 2 amps. The current limit is set to 2.5 amps. There is not sufficient thermal capacity available to allow W1 of FIG. 92 to carry sustained short circuit current so the fuse has been included to protect the various power supply components. All supplies except the +20 volt supply are crowbar protected against over-voltage.

TYPEWRITER INTERFACE

This interface couples the Facit-Odhner model 3841 output typewriter to the calculator.

The unit mounts directly on the back of the typewriter. Communications with the calculator are made through about five feet of cable which is terminated by the I/O plug containing a board for buffering and some logic.

Referring to FIGS. 97A-B through 105, characters from the calculator appear on the data lines as ASCII codes. These codes are recoded by a ROM into the six bit Facit typewriter code for the 46 type bars, and one bit for upper case shift. Functions such as space, tab, line feed, etc. are recoded for easy recognition in the interface since each function must be driven by a separate line. A data latch after the ROM holds codes for processing. If new data arrives during this processing, the two codes are compared to determine if they both drive the same type bar and if they are both numbers. Non-repeating numbers can be typed at 14.5 characters per second, otherwise typing speed is 12 characters per second (reduce these speeds 17 percent for 50 HZ duration). Codes in the latch are gated to the program solenoids or the function solenoids by the control logic.

To understand the coding, notice that two blocks of facts on the Facit typewriter code map are empty. If all fraction codes are put in these blocks, they can be identified its control logic by testing for (6 ^. 4). Each function code puts a 1 on one of five lines and this line opens the correct solenoid gate. Bit 8 is used to discriminate between two sets of function gates. In the case of a program solenoid code, bit 8 identifies numerals.

The control clock is provided by a sync. pulse which is generated in the typewriter by a vaned wheel attached to the end of the main drive shaft. The vanes interrupt a light beam. When a type cycle is initiated, a modulo eight counter counts sync. pulses and the count is decoded by a 1-of-8 decoder. At each of the eight states, combinational logic can enable solenoid gates, set or clear flag flip-flops or change the counter to state zero, or state 6, or inhibit the counter.

The tables below contain a guide for interpretation of bit pattern data as well as the actual bit patterns for ROM No. 10 and ROM No. 11 as shown in FIG. 102.

INTERPRETATION OF BIT PATTERN DATA

(Bipolar ROM of FIG. 102)

1. format

the bit pattern information is in the following format:

X ₁ x ₂ x ₃ --x ₅ x ₆ x ₇ b b x ₁₀ x ₁₁ x ₁₂ x ₁₃ b x ₁₅ x ₁₆ x ₁₇ x ₁₈ b . . . x ₄₅ x ₄₆ x ₄₇ x ₄₈

a. x ₁ x ₂ x ₃ -- three digits indicating the address (decimal) of the first word of that line. *1

B. x ₅ x ₆ x ₇ -- three digits indicating the address of the last word in that line. *1

C. x ₉ x ₁₀ x ₁₁ x ₁₂ -- four characters indicating the output states of the first word of that line (corresponding to address X ₁ X ₂ X ₃ ). *2

D. x ₁₅ x ₁₆ x ₁₇ x ₁₈ through X ₄₀ X ₄₁ X ₄₂ X ₄₃ indicate successive output staties. *2

E. x ₄₅ x ₄₆ x ₄₇ x ₄₈ -- four chatacters indicating the output states of the last word of that line (corresponding to address X ₅ X ₆ X ₇ ). *2

F. b = blank or space between group of characters.

2. Truth Table

Logic level definition

L -- output Low (Logic φ)

H -- output High or Open Collector (Logic 1)

X -- don't Care -- Output may be High or Low

________________________________________________________ __________________ BIPOLAR ROM 10 OF FIGURE 102 ____________________________________________________________ ______________ φφφ-φφ7 LLLL LLLH LLLL LLLL LLLL LLLL HLLL LHLL φφ8-φ15 HLLL LLLL LHLL LLHL LLLL LLHL LLLL LLLL φ16-φ23 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL φ24-φ31 LLLL LLLL LLLL LLLL LLLL LLLLL LLLL LLLL φ32-φ39 LLLH LLLH LLHL LLHH LHLL LHLH LHHL LHHH φ4φ-φ47 HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH φ-2φφ55 LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH φ56-φ63 HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH φ64-φ71 LLLL LLLH LLHL LLHH LHLL LHLH LHHL HHHH φ72-φ79 HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH φ8φ-φ87 LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH φ88-φ95 HLLL HLLH HLHL HLHH LLLL HHLH HHHL LLLL φ96-1φ3 LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH 1φ4-111 HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH 112-119 LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH 12φ-127 HLLL HLLH HLHL HLHH LLLL HHLH HHHL LLLL 128-135 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 136-143 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 144-151 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 152-159 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 16φ-167 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 168-175 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 176-183 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 184-191 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 192-199 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 2φφ-2φ7 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 2φ8-215 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 216-223 LLLL LLLL LLLL HHLH

HLHH LLLL HHHL HHHL 224-231 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 232-239 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 24φ-247 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 248-255 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL ____________________________________________________________ ______________

________________________________________________________ __________________ BIPOLAR ROM 11 OF FIG. 102 ____________________________________________________________ ______________ φφφ-φφ7 LLLL HLLL LLLL LLLL LLLL LLLL HLLL HLLL φφ8-φ15 LLLL LHLL LLLL HLLL HHLL LLLL LLLL LLLL φ16-φ23 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL φ24-φ31 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL φ32-φ39 LLLL LHLH LHLH LHLH LHLH LHLH LHLH LHLH φ4φ-φ47 LHLH LHLH LHLH LHLH LLLH HLLH LLLH LLLH φ48-φ55 HLLH HLLH HLLH HLLH HLLH HLLH HLLH HLLH φ56-φ63 HLLH HLLH HLLH LLLH LHLH LHLH LHLH LHLH φ64-φ71 LLHL LHHL LHHL LHHL LHHL LHHL LHHL LHHL φ72-φ79 LHHL LHHL LHHL LHHL LHHL LHHL LHHL LHHL φ8φ-φ87 LHHH LHHH LHHH LHHH LHHH LHHH LHHH LHHH φ88-φ95 LHHH LHHH LHHH LLHH LLLL LLHH LLHH LHLH φ96-1φ3 LHHL LLHL LLHL LLHL LLHL LLHL LLHL LLHL 1φ4-111 LLHL LLHL LLHL LLHL LLHL LLHL LLHL LLHL 112-119 LLHH LLHH LLHH LLHH LLHH LLHH LLHH LLHH 120-127 LLHH LLHH LLHH LHHH LLLL LHHH LHHH LLLL 128-135 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 136-143 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 144-151 LLLL LLLL LLLLL LLLL LLLL LLLL LLLL LLLL 152-159 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 16φ-167 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 168-175 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 176- 183 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 184-191 LLLL LLLL LLLL LLLL LHHL LLLL LLLL LLLL 192-199 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 2φφ-2φ7 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 2φ8-215 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 216-223 LLLL LLLL LLLLL LHHH

LHHH LLLL LLHH LHHH 224-231 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 232-239 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 24φ-247 LLLL LLLL LLLL LLLL LLLL LLLL LLLL LLLL 248-255 LLLL LLLLL LLLL LLLL LLLL LLLL LLLL LLLL ____________________________________________________________ ______________