Title:
GRAPHIC DISPLAY HAVING RECIRCULATING VIDEO MEMORY
United States Patent 3836902
Abstract:
Graphic information from an electronic computer or the like is written into a memory matrix in a dotted pattern corresponding to a figure to be displayed using a function generator which generates line segments, corresponding to the graphic information. The information in the memory matrix is then shifted into a recirculating memory for displaying the graphic information in the form of a figure on a CRT, such as the screen of a TV set. The recirculating memory is synchronized with the raster scan of the TV set, and thus there is no need for synchronizing the display system with the computer.
US Patent References:
Point matrix display unit for testing logic circuit
Farrow - April 1965 - 3179883
Display data processor
Strout - August 1968 - 3396377
DISPLAY SYSTEMS
Clark - January 1969 - 3422420
Point matrix display unit for testing logic circuit
Farrow - April 1965 - 3179883
Display data processor
Strout - August 1968 - 3396377
DISPLAY SYSTEMS
Clark - January 1969 - 3422420
Inventors:
Okuda, Nobuo (Yokohama, JA)
Kunikyo, Tomoo (Tokyo, JA)
Kunikyo, Tomoo (Tokyo, JA)
Application Number:
05/315012
Publication Date:
09/17/1974
Filing Date:
12/14/1972
View Patent Images:
Export Citation:
Assignee:
Tokyo Shibaura Electric Company, Ltd. (Kawasaki-shi, Kanagawa-ken, JA)
Primary Class:
Other Classes:
708/270
International Classes:
G09G5/39; G09G5/42; G09G5/36; G06F3/14
Field of Search:
340/324AD 235/198
Primary Examiner:
Caldwell, John W.
Assistant Examiner:
Curtis, Marshall M.
Attorney, Agent or Firm:
Oblon, Fisher, Spivak, McClelland & Maier
Claims:
What is claimed as new and desired to be secured by letters patent of the United States is
1. A graphic display system comprising:
2. A graphic display system, as in claim 1, further comprising:
3. A graphic display system as in claim 1 wherein said function generator means includes reversible counter means for addressing said memory matrix means and further includes gate means connected to said reversible counter means for counting the origin coordinates of a line segment.
4. A graphic display system as in claim 1 including means for a partial elimination of said figure to be displayed.
5. A graphic display system as in claim 1 including means for a partial addition of said figure to be displayed.
1. A graphic display system comprising:
2. A graphic display system, as in claim 1, further comprising:
3. A graphic display system as in claim 1 wherein said function generator means includes reversible counter means for addressing said memory matrix means and further includes gate means connected to said reversible counter means for counting the origin coordinates of a line segment.
4. A graphic display system as in claim 1 including means for a partial elimination of said figure to be displayed.
5. A graphic display system as in claim 1 including means for a partial addition of said figure to be displayed.
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to graphic display systems, and more particularly to a graphic display system useful as an input-output device for an electronic computer.
2. Description of the Prior Art
In the past, graphic display systems which used the so-called "stroke writing method" were known for handling exchanges of information with computers. These stroke writing systems, however, were expensive to manufacture because of the necessity of using an electron beam deflection device which requires electric power amplifiers of a large capacity and a corresponding large capacity electric power supply.
SUMMARY OF THE INVENTION
It is therefore one object of this invention to provide a new, improved and unique graphic display system which does not require an electron beam deflection device of the type required in stroke writing display systems.
Another object of this invention is to provide a graphic display system in which the graphic display is made by controlling the brightness of a cathode-ray tube.
A further object of this invention is to provide a graphic display system in which graphic information from an electronic computer is written in a memory matrix through a function generator which generates a function representing a line segment, and then the content in the memory matrix is fed into a refresh or recirculating memory device for displaying a figure on the screen of a cathode-ray tube of a TV set, wherein it is not required to synchronize the computer with the TV set.
Briefly, in accordance with one aspect of the invention, a function generator is provided for generating coordinate components of each line segment of a figure to be displayed in accordance with information emanating from an electronic computer. There is provided a memory matrix for storing a dotted pattern of the figure to be displayed in accordance with the output from the function generator. A refresh or recirculating memory device is also provided for storing the content of the memory matrix. The contents of the memory matrix are circulated in the refresh memory synchronized with the scanning raster of a cathode-ray tube so as to feed brightness signals thereto.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 1 is a block diagram of one embodiment of a graphic display system in accordance with the present invention;
FIG. 2 shows the details of the function generator illustrated in block form in FIG. 1;
FIG. 3 is a more detailed block diagram of the memory matrix illustrated in FIG. 1;
FIG. 4 is a detailed logic block diagram of the refresh memory device illustrated in FIG. 1;
FIG. 5 is a block diagram of a circuit for carrying out a partial supplement of a figure to be displayed; and,
FIG. 6 is a block diagram of a circuit for carrying out a partial elimination of a figure to be displayed.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to the drawings, and more particularly to FIG. 1 thereof, a graphic display system is shown referenced generally by the numeral 10. This system displays a figure or image on the screens of either one of, or both of, cathode-ray tubes 11 and 12 in response to graphic information from an electronic computer 13, or similar device fed through a control circuit 14. For convenience of description, each cathode-ray tube is referred to as a CRT. The control circuit 14 is provided for controlling circuit elements described hereinbelow in response to clock pulses coming from computer 13.
The figure to be displayed on the CRT screen is first written or stored in a fixed memory device within the computer 13 in the form of numerous line segments, and the signals corresponding to each of the segments are fed sequentially to a function generator 15 under the control of control circuit 14.
The function generator 15 generates an output therefrom in response to the coordinate components of each line segment as described below, and the coordinate components of each line segment are written into the corresponding addresses of a memory matrix 16 under the control of control circuit 14. In this way, the figure to be displayed on the CRT screen is written in memory matrix 16 in the form of a dotted pattern.
When a figure has been thus written into memory matrix 16, the content of memory matrix 16 is shifted into either of refresh memories 17 or 18 selectively under the control of control circuit 14. The contents of refresh memories 17 and 18 are circulated in synchronism with the raster scanning of CRT's 11 and 12, and are used to apply brightness signals to the CRT's 11 and 12 which are overlapped with the raster thereof.
The function generator 15 is shown in detail in FIG. 2 as including an X-axis component register 19 and a Y-axis component register 20 which are respectively set to the coordinate components of a line segment which are fed from control circuit 14 in binary coded form. The largest digits S X and S Y of registers 19 and 20 are bits for defining the polarity of the coordinate of the line segment. A binary counter 21 is provided for counting clock pulses C p from control circuit 14 through an AND gate 22 when a line command is introduced from control circuit 14 to AND gate 22 after the coordinate components of a line segment have been set into registers 19 and 20. The individual digit stages of registers 19 and 20 and binary counter 21 are respectively connected to AND gates 23 to 26 and 27 to 30 as shown, and the outputs of AND gates 23 to 26 and 27 to 30 are respectively connected to OR gates 31 and 32. Thus, as the binary counter 21 carries out a counting operation, the content of counter 21, which corresponds to the repetition frequency of the clock pulses, is modulated in accordance with the contents of registers 19 and 20. Accordingly output pulses are produced at the outputs of OR gates 31 and 32 which are frequency modulated by the coordinate components of a line segment which are set in registers 19 and 20.
The output of OR gate 31 is connected to an addition input and a subtraction input of an X-axis reversible counter 33 through AND gates 34 and 35. AND gate 34 is also connected to the largest digit of register 19 so as to conduct the output pulses of OR gate 31 to the addition input of counter 33 when the largest digit of register 19 presents one polarity S X of the coordinate components of a line segment. Similarly, AND gate 35 is connected to the largest digit of register 19 through a NOT circuit 36 so as to conduct the output pulses of OR gate 31 to the subtraction input of counter 33 when the largest digit of register 19 presents the other polarity S X of the coordinate components of the line segment.
Similarly, the output of OR gate 32 is connected to an addition input and a subtraction input of a Y-axis reversible counter or register 37 through AND gates 38 and 39. AND gate 38 is also connected to the largest digit of register 20 so as to conduct the output pulses of OR gate 32 to the addition input of register 37 when the largest digit of register 20 presents one polarity S Y . AND gate 39 is also connected to the largest digit of register 20 through a NOT circuit 40 so as to conduct the output pulses of OR gate 32 to the subtraction input of counter 37 when the largest digit of register 20 presents the other polarity S Y .
In order to initially define the origin of a line segment, AND gates 41 and 42 are connected to reversible counters 33 and 37. In this way, a positioning signal is fed to AND gates 41 and 42 from control circuit 14 prior to the counting operation of the output pulses from OR gates 31 and 32, and then pulses which present the origin coordinates X o and Y o of the line segment are fed from control circuit 14 into the reversible counters 33 and 37 so as to cause them to count the origin coordinates X o and Y o of the line segment.
In this way, the origin of a line segment is first counted in counters 33 and 37, and next the coordinate components of the line segment, which correspond to the contents of registers 19 and 20, are counted in the counters 33 and 37 in accordance with the polarities of the largest digit of registers 19 and 20. Thus, when the content of binary counter 21 becomes full, the binary counter 21 generates an end signal therefrom to thereby begin the next operation of the control circuit 14 so that the various segments of a line are sequentially counted in counters 33 and 37.
The memory matrix 16 is shown in more detail in FIG. 3. If it is assumed that the screens of CRT's 11 and 12 are formed of a cluster of 512 dots, there are provided 512 rows of integrated circuits IC 1 , IC 2 ,-- and IC 512 respectively having 512 addresses. The X-axis counter 33 shown in FIG. 2 is coupled to the integrated circuits IC 1 , IC 2 ,-- and IC 512 to separately select them. The Y-axis counter 37 of FIG. 2 is also coupled to the integrated circuits IC 1 , IC 2 ,-- and IC 512 to select appropriate addresses.
As stated above, when the X and Y-axis counters 33 and 37 count the coordinate components of a line segment, the coordinate components are respectively written into the corresponding addresses of integrated circuits IC 1 , IC 2 -- and IC 512 . The segments of a line are thus written into memory matrix 16 sequentially under the control of control circuit 14 so as to form a dotted pattern corresponding to a figure to be displayed.
In order to transfer the dotted pattern in the memory matrix 16 to the refresh or recirculating memories 17 or 18, there is provided a group of flip-flops 45 connected to the integrated circuits IC 1 , IC 2 -- and IC 512 . When the content of memory matrix 16 is to be read out, the X-axis counter 33 is cut out of the memory matrix 16, and then the read-out pulses are fed from control circuit 14 to the Y-axis counter 37 to transfer the content of one line of memory matrix 16 to flip-flops 45 in parallel, as shown with a reference numeral 46.
In FIG. 4, the refresh or recirculating memory 17 is shown in more detail. The refresh memory includes 512 rows of shift registers SR 1 , SR 2 --SR 512 , which may be MOS integrated circuits for example, and each of which corresponds to a respective raster of the CRT screen and has a number of bits corresponding to the sum of the number of dots to be displayed on one raster and the fly-back time of the electron beam. The shift registers SR 1 , SR 2 --SR 512 are respectively connected in a closed loop. A high frequency pulse generator 47 is provided in the aforesaid control circuit 14 of FIG. 1 for feeding shift pulses to the shift registers SR 1 , SR 2 --SR 512 so that the content of the respective shift registers can be circulated in the closed loop.
A line counter 48, which has the same capacity as the respective shift registers SR 1 , SR 2 --SR 512 is provided for counting shift pulses from pulse generator 47. The output pulses of line counter 48 are fed to a raster counter 49 as horizontal synchronizing signals H. The outputs from each stage of the raster counter 49 are employed for selection of the corresponding shift registers SR 1 , SR 2 --SR 512 as follows.
In order to transfer the content of flip-flops 45 of memory matrix 16 of FIG. 3 to the shift registers SR 1 , SR 2 , --SR 512 , an AND gate 50 is provided for feeding the shift pulses from pulse generator 47 to flip-flops 45. AND gate 50 also has an input connected to the output of line counter 48 through a NOT circuit 51. Thus, the AND gate 50 passes the shift pulses from pulse generator 47 to flip-flops 45 during the counting operation of line counter 48.
In order to select one of shift registers SR 1 , SR 2 --S 512 to which the content of flip-flops 45 is transferred in series, AND gates 51, 52, 53, 54 etc. are provided corresponding to shift registers SR 1 , SR 2 -- and SR 512 . One input of each of AND gates 52, 53, 54 etc. is connected to the output of flip-flops 45 and other input of each of the same AND gates is connected to the respective output stages of raster counter 49.
If it is assumed that an output has been produced by the uppermost stage of raster counter 49 due to a horizontal synchronizing pulse H from line counter 48, AND gate 52 allows the content of flip-flops 45 to be transferred into the uppermost shift register SR 1 .
Thus, when the first data transfer from flip-flops 45 has been made, the other data from the second line of memory matrix 16 of FIG. 3 is set into flip-flops 45, and then AND gate 53 is opened by the second stage output of raster counter 49 caused by the next output pulse from line counter 48. In this way, the content of flip-flops 45 is now transferred into the second shift register SR 2 .
The contents of all of the lines of memory matrix 16 are similarly transferred into the corresponding shift registers SR 1 , SR 2 --SR 512 .
AND gates 55, 56, 56 etc. are provided for reading out the contents of shift registers SR 1 , SR 2 --SR 512 in turn, and the same respectively each have one input connected to the output of the corresponding shift registers SR 1 , SR 2 --SR 512 . Additionally, each of the AND gates 55, 56, 57 etc. respectively have their other input connected to the corresponding stage of raster counter 49.
When the uppermost stage of raster counter 49 generates an output signal, AND gate 55 is opened to read out the content of shift register SR 1 , and at the same time the scanning of the uppermost raster of the CRT screen is started. The content of shift register SR 1 is sequentially fed out through AND gate 55 by the shift pulses from pulse generator 47 applied to the shift register SR 1 . It can be understood that if the read-out of the content of shift register SR 1 has terminated, the content shift register SR 1 is returned to the initial condition because of the circulating operation due to the closed loop.
When the second output is produced by line counter 48, the raster counter 49 generates an output at the second stage thereof so that AND gate 56 allows the content of the second shift register SR 2 to be read out therethrough. Similarly, when the read-out of the content of shift register SR 2 has terminated, the content of shift register SR 2 is returned to the initial condition because of the circulating operation due to the closed loop, and then AND gate 56 is closed. In this way, the contents of Shift registers SR 1 , SR 2 --SR 512 are read out in turn in accordance with the raster sequence.
The outputs of AND gates 55, 56 etc. are fed into OR gate 58, and then applied to CRT 11 so as to carry out the brightness modulation of the raster thereof.
In this way, the rasters on the screen of CRT 11 are respectively modulated by the content of the corresponding shift registers SR 1 , SR 2 -- and SR 512 so that a figure is displayed on CRT screen in accordance with the graphic information from computer 13.
If it is necessary to display a suitable background on the CRT screen overlapping the display resulting from the refresh memory 17, an overlapping circuit 59, which is connected to another video signal source 60, such as a TV camera or a video tape recorder, may be provided between OR gate 58 and CRT 11.
Referring again to FIG. 1, it is understood that the refresh memory 18 may also be constructed as shown in FIG. 4. The CRT 12, located at a different position, can be used to display the same figure as the CRT 11. Additionally, when the memory matrix 16 is not employed for displaying a figure on CRT 11, it can be employed for transferring other contents thereof to the refresh memory 18 in order to display another figure on the screen of CRT 12 under the control of control circuit 14.
The memory matrix 16 of FIG. 3 can be constructed having a memory capacity of one fourth (1/4) that of the refresh memory 17 of FIG. 4 in order to reduce the cost thereof. In this case, the refresh memory 17 of FIG. 4 is divided into four sections corresponding to four sections of the display screen, each including 256X256 dots therein. The content of memory matrix 16 is then selectively transferred into each section of the refresh memory 17 under the control of control circuit 14.
FIG. 5 shows a block diagram for the partial addition of a figure to be displayed. A part of the figure to be added is written into the memory matrix 16 and overlapped with the circulating content of the refresh memory 17 through an OR gate 61 to be displayed on the screen of CRT 11.
FIG. 6 shows a block diagram for the partial elimination of a figure to be displayed. A part of the figure to be eliminated is similarly written into the memory matrix 16, and transferred into the refresh memory 17 through an AND gate 62 so as to be displayed on the screen of the CRT 11 as a bar pattern.
In accordance with the invention, the graphic display system can be made inexpensively because the electron beam deflection device which was required for writing a figure with the "stroke writing" system has been eliminated. The figure information from a computer is written into a memory matrix in a similar manner to that of the stroke writing system, and then the content of the memory matrix is transferred into the refresh memory to be displayed on a CRT screen. Accordingly, it is not necessary to have synchronization between the computer and the CRT display device. Further, the present system can be easily made to draw a figure on the CRT screen with a light pen in a similar manner to that of the stroke writing system.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
1. Field of the Invention
The present invention relates generally to graphic display systems, and more particularly to a graphic display system useful as an input-output device for an electronic computer.
2. Description of the Prior Art
In the past, graphic display systems which used the so-called "stroke writing method" were known for handling exchanges of information with computers. These stroke writing systems, however, were expensive to manufacture because of the necessity of using an electron beam deflection device which requires electric power amplifiers of a large capacity and a corresponding large capacity electric power supply.
SUMMARY OF THE INVENTION
It is therefore one object of this invention to provide a new, improved and unique graphic display system which does not require an electron beam deflection device of the type required in stroke writing display systems.
Another object of this invention is to provide a graphic display system in which the graphic display is made by controlling the brightness of a cathode-ray tube.
A further object of this invention is to provide a graphic display system in which graphic information from an electronic computer is written in a memory matrix through a function generator which generates a function representing a line segment, and then the content in the memory matrix is fed into a refresh or recirculating memory device for displaying a figure on the screen of a cathode-ray tube of a TV set, wherein it is not required to synchronize the computer with the TV set.
Briefly, in accordance with one aspect of the invention, a function generator is provided for generating coordinate components of each line segment of a figure to be displayed in accordance with information emanating from an electronic computer. There is provided a memory matrix for storing a dotted pattern of the figure to be displayed in accordance with the output from the function generator. A refresh or recirculating memory device is also provided for storing the content of the memory matrix. The contents of the memory matrix are circulated in the refresh memory synchronized with the scanning raster of a cathode-ray tube so as to feed brightness signals thereto.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 1 is a block diagram of one embodiment of a graphic display system in accordance with the present invention;
FIG. 2 shows the details of the function generator illustrated in block form in FIG. 1;
FIG. 3 is a more detailed block diagram of the memory matrix illustrated in FIG. 1;
FIG. 4 is a detailed logic block diagram of the refresh memory device illustrated in FIG. 1;
FIG. 5 is a block diagram of a circuit for carrying out a partial supplement of a figure to be displayed; and,
FIG. 6 is a block diagram of a circuit for carrying out a partial elimination of a figure to be displayed.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to the drawings, and more particularly to FIG. 1 thereof, a graphic display system is shown referenced generally by the numeral 10. This system displays a figure or image on the screens of either one of, or both of, cathode-ray tubes 11 and 12 in response to graphic information from an electronic computer 13, or similar device fed through a control circuit 14. For convenience of description, each cathode-ray tube is referred to as a CRT. The control circuit 14 is provided for controlling circuit elements described hereinbelow in response to clock pulses coming from computer 13.
The figure to be displayed on the CRT screen is first written or stored in a fixed memory device within the computer 13 in the form of numerous line segments, and the signals corresponding to each of the segments are fed sequentially to a function generator 15 under the control of control circuit 14.
The function generator 15 generates an output therefrom in response to the coordinate components of each line segment as described below, and the coordinate components of each line segment are written into the corresponding addresses of a memory matrix 16 under the control of control circuit 14. In this way, the figure to be displayed on the CRT screen is written in memory matrix 16 in the form of a dotted pattern.
When a figure has been thus written into memory matrix 16, the content of memory matrix 16 is shifted into either of refresh memories 17 or 18 selectively under the control of control circuit 14. The contents of refresh memories 17 and 18 are circulated in synchronism with the raster scanning of CRT's 11 and 12, and are used to apply brightness signals to the CRT's 11 and 12 which are overlapped with the raster thereof.
The function generator 15 is shown in detail in FIG. 2 as including an X-axis component register 19 and a Y-axis component register 20 which are respectively set to the coordinate components of a line segment which are fed from control circuit 14 in binary coded form. The largest digits S X and S Y of registers 19 and 20 are bits for defining the polarity of the coordinate of the line segment. A binary counter 21 is provided for counting clock pulses C p from control circuit 14 through an AND gate 22 when a line command is introduced from control circuit 14 to AND gate 22 after the coordinate components of a line segment have been set into registers 19 and 20. The individual digit stages of registers 19 and 20 and binary counter 21 are respectively connected to AND gates 23 to 26 and 27 to 30 as shown, and the outputs of AND gates 23 to 26 and 27 to 30 are respectively connected to OR gates 31 and 32. Thus, as the binary counter 21 carries out a counting operation, the content of counter 21, which corresponds to the repetition frequency of the clock pulses, is modulated in accordance with the contents of registers 19 and 20. Accordingly output pulses are produced at the outputs of OR gates 31 and 32 which are frequency modulated by the coordinate components of a line segment which are set in registers 19 and 20.
The output of OR gate 31 is connected to an addition input and a subtraction input of an X-axis reversible counter 33 through AND gates 34 and 35. AND gate 34 is also connected to the largest digit of register 19 so as to conduct the output pulses of OR gate 31 to the addition input of counter 33 when the largest digit of register 19 presents one polarity S X of the coordinate components of a line segment. Similarly, AND gate 35 is connected to the largest digit of register 19 through a NOT circuit 36 so as to conduct the output pulses of OR gate 31 to the subtraction input of counter 33 when the largest digit of register 19 presents the other polarity S X of the coordinate components of the line segment.
Similarly, the output of OR gate 32 is connected to an addition input and a subtraction input of a Y-axis reversible counter or register 37 through AND gates 38 and 39. AND gate 38 is also connected to the largest digit of register 20 so as to conduct the output pulses of OR gate 32 to the addition input of register 37 when the largest digit of register 20 presents one polarity S Y . AND gate 39 is also connected to the largest digit of register 20 through a NOT circuit 40 so as to conduct the output pulses of OR gate 32 to the subtraction input of counter 37 when the largest digit of register 20 presents the other polarity S Y .
In order to initially define the origin of a line segment, AND gates 41 and 42 are connected to reversible counters 33 and 37. In this way, a positioning signal is fed to AND gates 41 and 42 from control circuit 14 prior to the counting operation of the output pulses from OR gates 31 and 32, and then pulses which present the origin coordinates X o and Y o of the line segment are fed from control circuit 14 into the reversible counters 33 and 37 so as to cause them to count the origin coordinates X o and Y o of the line segment.
In this way, the origin of a line segment is first counted in counters 33 and 37, and next the coordinate components of the line segment, which correspond to the contents of registers 19 and 20, are counted in the counters 33 and 37 in accordance with the polarities of the largest digit of registers 19 and 20. Thus, when the content of binary counter 21 becomes full, the binary counter 21 generates an end signal therefrom to thereby begin the next operation of the control circuit 14 so that the various segments of a line are sequentially counted in counters 33 and 37.
The memory matrix 16 is shown in more detail in FIG. 3. If it is assumed that the screens of CRT's 11 and 12 are formed of a cluster of 512 dots, there are provided 512 rows of integrated circuits IC 1 , IC 2 ,-- and IC 512 respectively having 512 addresses. The X-axis counter 33 shown in FIG. 2 is coupled to the integrated circuits IC 1 , IC 2 ,-- and IC 512 to separately select them. The Y-axis counter 37 of FIG. 2 is also coupled to the integrated circuits IC 1 , IC 2 ,-- and IC 512 to select appropriate addresses.
As stated above, when the X and Y-axis counters 33 and 37 count the coordinate components of a line segment, the coordinate components are respectively written into the corresponding addresses of integrated circuits IC 1 , IC 2 -- and IC 512 . The segments of a line are thus written into memory matrix 16 sequentially under the control of control circuit 14 so as to form a dotted pattern corresponding to a figure to be displayed.
In order to transfer the dotted pattern in the memory matrix 16 to the refresh or recirculating memories 17 or 18, there is provided a group of flip-flops 45 connected to the integrated circuits IC 1 , IC 2 -- and IC 512 . When the content of memory matrix 16 is to be read out, the X-axis counter 33 is cut out of the memory matrix 16, and then the read-out pulses are fed from control circuit 14 to the Y-axis counter 37 to transfer the content of one line of memory matrix 16 to flip-flops 45 in parallel, as shown with a reference numeral 46.
In FIG. 4, the refresh or recirculating memory 17 is shown in more detail. The refresh memory includes 512 rows of shift registers SR 1 , SR 2 --SR 512 , which may be MOS integrated circuits for example, and each of which corresponds to a respective raster of the CRT screen and has a number of bits corresponding to the sum of the number of dots to be displayed on one raster and the fly-back time of the electron beam. The shift registers SR 1 , SR 2 --SR 512 are respectively connected in a closed loop. A high frequency pulse generator 47 is provided in the aforesaid control circuit 14 of FIG. 1 for feeding shift pulses to the shift registers SR 1 , SR 2 --SR 512 so that the content of the respective shift registers can be circulated in the closed loop.
A line counter 48, which has the same capacity as the respective shift registers SR 1 , SR 2 --SR 512 is provided for counting shift pulses from pulse generator 47. The output pulses of line counter 48 are fed to a raster counter 49 as horizontal synchronizing signals H. The outputs from each stage of the raster counter 49 are employed for selection of the corresponding shift registers SR 1 , SR 2 --SR 512 as follows.
In order to transfer the content of flip-flops 45 of memory matrix 16 of FIG. 3 to the shift registers SR 1 , SR 2 , --SR 512 , an AND gate 50 is provided for feeding the shift pulses from pulse generator 47 to flip-flops 45. AND gate 50 also has an input connected to the output of line counter 48 through a NOT circuit 51. Thus, the AND gate 50 passes the shift pulses from pulse generator 47 to flip-flops 45 during the counting operation of line counter 48.
In order to select one of shift registers SR 1 , SR 2 --S 512 to which the content of flip-flops 45 is transferred in series, AND gates 51, 52, 53, 54 etc. are provided corresponding to shift registers SR 1 , SR 2 -- and SR 512 . One input of each of AND gates 52, 53, 54 etc. is connected to the output of flip-flops 45 and other input of each of the same AND gates is connected to the respective output stages of raster counter 49.
If it is assumed that an output has been produced by the uppermost stage of raster counter 49 due to a horizontal synchronizing pulse H from line counter 48, AND gate 52 allows the content of flip-flops 45 to be transferred into the uppermost shift register SR 1 .
Thus, when the first data transfer from flip-flops 45 has been made, the other data from the second line of memory matrix 16 of FIG. 3 is set into flip-flops 45, and then AND gate 53 is opened by the second stage output of raster counter 49 caused by the next output pulse from line counter 48. In this way, the content of flip-flops 45 is now transferred into the second shift register SR 2 .
The contents of all of the lines of memory matrix 16 are similarly transferred into the corresponding shift registers SR 1 , SR 2 --SR 512 .
AND gates 55, 56, 56 etc. are provided for reading out the contents of shift registers SR 1 , SR 2 --SR 512 in turn, and the same respectively each have one input connected to the output of the corresponding shift registers SR 1 , SR 2 --SR 512 . Additionally, each of the AND gates 55, 56, 57 etc. respectively have their other input connected to the corresponding stage of raster counter 49.
When the uppermost stage of raster counter 49 generates an output signal, AND gate 55 is opened to read out the content of shift register SR 1 , and at the same time the scanning of the uppermost raster of the CRT screen is started. The content of shift register SR 1 is sequentially fed out through AND gate 55 by the shift pulses from pulse generator 47 applied to the shift register SR 1 . It can be understood that if the read-out of the content of shift register SR 1 has terminated, the content shift register SR 1 is returned to the initial condition because of the circulating operation due to the closed loop.
When the second output is produced by line counter 48, the raster counter 49 generates an output at the second stage thereof so that AND gate 56 allows the content of the second shift register SR 2 to be read out therethrough. Similarly, when the read-out of the content of shift register SR 2 has terminated, the content of shift register SR 2 is returned to the initial condition because of the circulating operation due to the closed loop, and then AND gate 56 is closed. In this way, the contents of Shift registers SR 1 , SR 2 --SR 512 are read out in turn in accordance with the raster sequence.
The outputs of AND gates 55, 56 etc. are fed into OR gate 58, and then applied to CRT 11 so as to carry out the brightness modulation of the raster thereof.
In this way, the rasters on the screen of CRT 11 are respectively modulated by the content of the corresponding shift registers SR 1 , SR 2 -- and SR 512 so that a figure is displayed on CRT screen in accordance with the graphic information from computer 13.
If it is necessary to display a suitable background on the CRT screen overlapping the display resulting from the refresh memory 17, an overlapping circuit 59, which is connected to another video signal source 60, such as a TV camera or a video tape recorder, may be provided between OR gate 58 and CRT 11.
Referring again to FIG. 1, it is understood that the refresh memory 18 may also be constructed as shown in FIG. 4. The CRT 12, located at a different position, can be used to display the same figure as the CRT 11. Additionally, when the memory matrix 16 is not employed for displaying a figure on CRT 11, it can be employed for transferring other contents thereof to the refresh memory 18 in order to display another figure on the screen of CRT 12 under the control of control circuit 14.
The memory matrix 16 of FIG. 3 can be constructed having a memory capacity of one fourth (1/4) that of the refresh memory 17 of FIG. 4 in order to reduce the cost thereof. In this case, the refresh memory 17 of FIG. 4 is divided into four sections corresponding to four sections of the display screen, each including 256X256 dots therein. The content of memory matrix 16 is then selectively transferred into each section of the refresh memory 17 under the control of control circuit 14.
FIG. 5 shows a block diagram for the partial addition of a figure to be displayed. A part of the figure to be added is written into the memory matrix 16 and overlapped with the circulating content of the refresh memory 17 through an OR gate 61 to be displayed on the screen of CRT 11.
FIG. 6 shows a block diagram for the partial elimination of a figure to be displayed. A part of the figure to be eliminated is similarly written into the memory matrix 16, and transferred into the refresh memory 17 through an AND gate 62 so as to be displayed on the screen of the CRT 11 as a bar pattern.
In accordance with the invention, the graphic display system can be made inexpensively because the electron beam deflection device which was required for writing a figure with the "stroke writing" system has been eliminated. The figure information from a computer is written into a memory matrix in a similar manner to that of the stroke writing system, and then the content of the memory matrix is transferred into the refresh memory to be displayed on a CRT screen. Accordingly, it is not necessary to have synchronization between the computer and the CRT display device. Further, the present system can be easily made to draw a figure on the CRT screen with a light pen in a similar manner to that of the stroke writing system.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.