Prescher, Kenneth E. (Lombard, IL)
Schauer, Ronald E. (Hanover Park, IL)
Sikorski, Frank B. (Des Plaines, IL)

05/342323

09/10/1974

03/19/1973

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GTE Automatic Electric Laboratories, Inc. (Northlake, IL)

379/237

379/302, 379/273, 379/290, 379/269, 379/279

H04Q3/545; F02B75/02; H04Q3/54

179/18ES

Brown, Thomas W.

Franz B. E.

This is a continuation-in-part of application Ser. No. 130,133 filed Apr. 1, 1971, now abandoned.

What is claimed is

1. A communication switching system comprising:

2. A communication switching system as claimed in claim 1, wherein said central processor comprises a stored program computer operating with said central processor memory.

3. A communication switching system as claimed in claim 2, wherein said data processing unit includes an auxiliary processor having its own memory including apparatus for associative searches, arranged to operate with said central processor to receive data therefrom, to use the associative search apparatus to find correspondence between a part of the data and information in the memory of the auxiliary processor, to extract related information from the memory of the auxiliary processor and return it to the central processor, while the central processor is independently proceeding with the execution of other routines.

4. A communication switching system as claimed in claim 3, wherein the memory of the auxiliary processor is used as an extended memory for storing programs which upon request from the central processor are transferred to the central processor memory for execution, the transfer being effected without interference with the simultaneous processing of other routines by the central processor.

5. A communication switching system as claimed in claim 4, wherein said auxiliary processor is a drum memory system in which its memory comprises magnetic drum means.

6. A communication switching system as claimed in claim 2, wherein said data transfer means interconnecting the central processor and the register subsystem comprises means for a direct access from the central processor to the register memory on a random access basis, with means to prevent interference with the sequential access by the register subsystem to the junctor areas in the respective time slots.

7. A communication switching system as claimed in claim 6, wherein said common logic means of the register subsystem includes wired logic with sequence control means.

8. A communication switching system as claimed in claim 1, wherein said originating marker means and terminating marker means each include wired logic apparatus with sequence control means, and wherein said data communication means interconnecting the central processor with the originating marker means and the terminating marker means comprises serial data transmission apparatus.

9. A communication switching system as claimed in claim 8, wherein said register subsystem includes sending means for outpulsing on calls to other offices; wherein for all the dial pulse mode of direct current signaling, there is an arrangement comprising multiplex means to effectively connect the common logic means and the register junctors during their respective time slots for receiving and sending from or to relay repeating means in the register junctors;

10. A communication switching system as claimed in claim 9, wherein said central processor and said register subsystem are each provided in duplicate and operated in synchronism to process the same call information, with each central processor normally communicating with a given one of the register subsystems, one of the central processor-register subsystem combinations being on line to supply output information ot other subsystems, and wherein the system may be reconfigured with either central processor communicating with either register subsystem, and any combination of them being on line to supply output information.

11. A communication switching system as claimed in claim 10, wherein said originating marker means is duplicated with both operating simultaneously, interlocked so that any given call request is served by only one originating marker; and wherein said terminating marker means is duplicated and arranged to operate only one at a time, with reconfiguration means permitting either originating marker means or either terminating marker means to be temporarily taken out of service.

12. A communication switching system as claimed in claim 11, wherein said data processing unit includes an auxiliary system with its own memory, the auxiliary system being duplicated, with both or either central processor working with either auxiliary system.

13. A communication switching system as claimed in claim 12, wherein the system includes a control section comprising one said data processing unit and either one or two said register subsystems depending upon the call processing traffic load of the system, and wherein in a control section comprising two register subsystems said data transfer means comprises an arrangement for the central processor to selectively communicate with the register memories of both register subsystems.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a processor controlled communication switching system, and more particularly to a system using a stored program computer processor and separate wired logic processors.

2. Description of the Prior Art

Today there are a number of applications for highly reliable program-controlled data processing systems which have a real time demand on the system services. One example is a modern communication switching system for voice and/or data communication.

Such a data processing system has operational requirements such as an ability to cope with real time demands and an extremely high degree of system dependability. The term "real time" as employed herein, means that the processor must be capable of coping with all requests without significant delay, and the term "dependability" means that the system shall remain operative even though it has all the frailties of a man-made device.

There are many known common control communication switching systems, some of which use exclusively wired logic controlled common systems, and others of which use primarily stored program control for the common functions. Examples of a wired logic controlled system are disclosed in U.S. Pat. No. 3,170,041 by K. K. Spellnes, and U.S. Pat. No. 3,299,214 by K. E. Prescher et al. While such systems perform many of the common control functions well, it has become desirable in a modern system to have the flexibility of a stored program control. However, systems concentrating substantially all of the common functions in a single stored program control data processor may be unable to cope with the real time demands on such a system for high traffic density, particularly in emergency situations in which the demand may be several times the capability of the system. A communication switching system using multi-processors to divide the tasks involved in call processing is disclosed in U.S. Pat. No. 3,408,628 by R. L. Brass et al. While the multiprocessing approach increases the capacity of a system such that the normal call processing ability may be greatly increased, it is still possible in unusual situations that the processing apparatus may become greatly overloaded to the extent that the amount of output is actually decreased because of the time spent in serving new requests. It would be desirable to have a system arrangement such that the number of call requests presented to the central data processing system is limited so as not to exceed its capacity.

SUMMARY OF THE INVENTION

An object of the invention is to provide a switching system using an optimum combination of wired logic and stored program control. Another object is to provide a system in which the stored program data processor does not have its call handling capacity actually reduced due to overloading during periods of unusually high demand. Still another object is to provide a system which has a high degree of maintainability to provide the required dependability to insure continuous service.

According to the invention a communication switching system comprises wired logic markers arranged to independently find idle paths and establish connections through the switching network, and the markers further include means to detect originating call requests from calling line circuits and for each call request to establish an originating connection for the call to an idle register junctor; a separate register subsystem including the register junctors arranged to receive and store call digits for each call; a data processing unit is provided for processing the call data; data communication arrangement is provided interconnecting the data processing unit with the markers, and a data transfer arrangement is provided interconnecting the data processing unit with the register subsystem; with the markers having arrangements effective after the originating connection between the calling line circuits and the register junctor has been established to seize the data communication path and transmitting and originating data message identifying the calling line circuit and register junctor terminals to the central processor.

In the preferred form of the invention the data processor includes a stored program control computer, while the markers and the register subsystem use wired logic control. In the preferred embodiment the register subsystem uses a time division multiplex arrangement with cyclical access to its memory for serving the register junctors. For data transfer between the data processor computer and the register subsystem the computer has direct access on a random access base to the register subsystem memory.

According to a further feature of the invention, the data processing system includes a separate relatively slow speed processing system for functions such as translations between directory number and equipment number line designations, and also for providing an extended memory for storing programs for the computer. In the disclosed embodiment the memory for this system is a magnetic drum system.

CROSS-REFERENCE TO RELATED APPLICATIONS

The register-sender subsystem for this system is generally similar to that disclosed in U.S. Pat. No. 3,301,963 by D. K. K. Lee et al. for a Register-Sender Arrangement for a Communication Switching System Common Control Arrangement. The markers for the system are generally similar to the arrangement disclosed in U.S. Pat. No. 3,293,368 by W. R. Wedmore for a Marker for a Communication Switching Network.

The above patents relate to a prototype system which did not include a stored program computer central processor.

The system covered by the present application, known as No. 1 EAX, or simply EAX, has some of the subsystems thereof described in the following U.S. patent applications, which are incorporated herein and made a part hereof as though fully set forth. The system disclosed herein uses integrated-circuit electronic logic circuits.

The memory access, and the priority and interrupt circuits for the register-sender subsystems are covered by U.S. Pat. application Ser. No. 139,480, filed May 3, 1971 now U.S. Pat. No. 3,729,715, issued May 3, 1973, by C. K. Buedel for a MEMORY ACCESS APPARATUS PROVIDING CYCLIC SEQUENTIAL ACCESS BY A REGISTER SUBSYSTEM AND RANDOM ACCESS BY A MAIN PROCESSOR IN A COMMUNICATION SWITCHING SYSTEM, hereinafter referred to as the REGISTER-SENDER MEMORY CONTROL patent application. The register-sender subsystem is described in U.S. Pat. application Ser. No. 201,851 filed Nov. 24, 1971, now U.S. Pat. No. 3,737,873 issued Nov. 24, 1973, by S. E. Puccini for DATA PROCESSOR WITH CYCLIC SEQUENTIAL ACCESS TO MULTIPLEXED LOGIC AND MEMORY, hereinafter referred to as the REGISTER-SENDER patent application. Maintenance hardware features of the register-sender are described in four U.S. Pat. applications having the same disclosure filed July 12, 1972, Ser. No. 270,909, now U.S. Pat. No. 3,784,801, by J. P. Caputo and F. A. Weber for a DATA HANDLING SYSTEM ERROR AND FAULT DETECTING AND DISCRIMINATING MAINTENANCE ARRANGEMENT, Ser. No. 270,910, now U.S. Pat. No. 3,783,255 by C. K. Buedel and J. P. Caputo for a DATA HANDLING SYSTEM MAINTENANCE ARRANGEMENT FOR PROCESSING SYSTEM TROUBLE CONDITIONS, Ser. No. 270,912 by C. K. Buedel and J. P. Caputo for a DATA HANDLING SYSTEM MAINTENANCE ARRANGEMENT FOR PROCESSING SYSTEM FAULT CONDITIONS, and Ser. No. 270,916, now U.S. Pat. No. 3,783,256, by J. P. Caputo and G. O'Toole for a DATA HANDLING SYSTEM MAINTENANCE ARRANGEMENT FOR CHECKING SIGNALS, these four applications being referred to hereinafter as the REGISTER-SENDER MAINTENANCE PATENT APPLICATIONS.

The marker for the system is disclosed in the U.S. Pat. No. 3,681,537, issued Aug. 1, 1972 by J. W. Eddy, H. G. Fitch, W. F. Mui and A. M. Valente for a MARKER FOR COMMUNICATION SWITCHING SYSTEM, and U.S. Pat. No. 3,678,208, issued July 18, 1972 by J. W. Eddy for a MARKER PATH FINDING ARRANGEMENT INCLUDING IMMEDIATE RING; and also in U.S. Pat. applications Ser. No. 281,586 filed Aug. 17, 1972 by J. W. Eddy for an INTERLOCK ARRANGEMENT FOR A COMMUNICATION SWITCHING SYSTEM, Ser. No. 311,606 filed Dec. 4, 1972 by J. W. Eddy and S. E. Puccini for a COMMUNICATION SYSTEM CONTROL TRANSFER ARRANGEMENT, Ser. No. 303,157 filed Nov. 2, 1972 by J. W. Eddy and S. E. Puccini for a COMMUNICATION SWITCHING SYSTEM INTERLOCK ARRANGEMENT, hereinafter referred to as the MARKER patents and applications.

The communication register and the marker transceivers are described in U.S. Pat. application Ser. No. 320,412 filed Jan. 2, 1973 by J. J. Vrba and C. K. Buedel for a COMMUNICATION SWITCHING SYSTEM TRANSCEIVER ARRANGEMENT FOR SERIAL TRANSMISSION, hereinafter referred to as the COMMUNICATIONS REGISTER patent application.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a telephone switching exchange;

FIG. 2 is a block diagram of the system showing the duplication of the subsystems of FIG. 1 and the reconfiguration control;

FIG. 3 is a block diagram showing how the computer central processor interfaces with other units of the data processing unit and of a register sender subsystem which together form the common control of the switching system;

FIG. 3A is a block diagram in a computer central processor showing a data bus and an address bus interconnecting a plurality of registers;

FIG. 4 is a functional block diagram of the processor timing control;

FIG. 5 is a functional block diagram showing the sources for data bit φ;

FIGS. 6 and 7 are functional block diagrams showing the data bus sources for all bit positions;

FIG. 8 is a functional block diagram showing the address bus sources for bit φ;

FIG. 9 is a functional block diagram showing all of the address bus sources;

FIG. 10 is a functional block diagram of the instruction register;

FIG. 11 is a functional block diagram of the Y and S registers;

FIG. 12 is a functional block diagram of the arithmetic logic unit;

FIG. 13 is a functional block diagram of the A and Q registers;

FIG. 14 is a functional block diagram of the program count and last program count registers;

FIG. 15 is a block diagram of the index registers and a shift register;

FIG. 16 is a timing diagram for the instruction ADM (add to memory);

FIG. 17 is a block diagram of the computer line processor interfaces with other subsystems;

FIG. 18 is a block diagram of the computer memory control and drum systems;

FIGS. 19 and 19A comprise a drum access circuit block diagram;

FIG. 20 is a diagram of a drum segment, word organization;

FIGS. 21 and 22 are flowcharts for drum access circuit peripheral adapter read and write transfer;

FIG. 23 is a drum control unit block diagram;

FIG. 24 is a graph of the down control unit timing;

FIGS. 25 and 25A comprise a diagram of the block transfer module of the drum control unit block diagram;

FIGS. 26, 26A and 26B comprise a flowchart for read sequence and write sequence in the drum memory system;

FIGS. 27 and 27A comprise a flowchart for termination sequence in the drum memory system;

FIGS. 28 and 28A comprise a block diagram for associative search control in the drum memory system;

FIGS. 29 and 29A comprise an MLS flowchart for the drum memory system;

FIGS. 30 and 30A comprise an SLAS flowchart for the drum memory system;

FIGS. 31, 31A, 31B, 32 and 32A comprise an MLS control actions flowchart for the drum memory system;

FIGS. 33 and 33A are an MLS decision table for the drum memory system;

FIG. 34 is a DCU sequence flowchart for the drum memory system;

FIG. 35 is a block diagram of the input/output system;

FIG. 36 is a diagram interface information between the register-sender and the data processing unit;

FIG. 37 is a layout diagram of the register-sender memory;

FIG. 38 is a layout diagram of the storage area in memory for one register;

FIG. 39 is a diagram of the call history table;

FIGS. 40-46 are layout diagrams of the call history table contents during time frames φ-6 respectively;

FIG. 47 is a field program block diagram flowchart;

FIG. 48 is a typical layout of a portion of the main core memory;

FIGS. 49-69 are memory diagrams and flowcharts for the executive program;

FIG. 70 is a combined hardware and software simplified flowchart for a local-to-local call;

FIGS. 71-103B are call processing software flowcharts; and

FIGS. 104-125A are executive software flowcharts.

GENERAL SYSTEM DESCRIPTION

Referring now to FIG. 1 of the drawings, there is shown a system 100 which incorporates the principles of the present invention and which comprises a line group 110, a selector group 120, a data processor unit 130, a maintenance and control center 140 for the data processor unit, a trunk-register group 150, an originating marker 160, a terminating marker 170, and a register sender 200. The line group 110 includes reed-relay switching networks A, B, C and R for providing local lines L000 to L999 with a means of accessing the system 100 for originating calls and for providing a means of terminating calls destined for local customers. The trunk-register group 150 also includes reed-relay switching networks A and B to provide access to the system 100 for incoming trunks 152 from distant offices, and to route trunk calls through the system to local customers or to outgoing trunks 120 to distant offices. The selector group 120 forms an intermediate switch and may be considered the call distribution center of the switching system 100. The selector group 120 routes calls appearing on its inlets to appropriate destinations, such as local lines or other offices represented by outgoing trunks, by means of reed-relay switching networks A, B and C. Thus, the line group 110, the trunk-register group 150, and the selector group 120 form the switching network for the system 100 and provide full-metallic paths through the office for signaling and transmission.

As seen in FIG. 1, the originating marker 160 provides high-speed control of the switching networks to connect the calls entering the system 100 to the register sender 200. The terminating markers 160 control the switching networks of the selector group 120 for establishing connections therethrough. If a call is to be terminated on a customer's line within the office, the terminating marker 170 sets up a connection through both the selector group 120 and the line group 110 to the customer's line.

The register sender 200 provides for receiving and storing of incoming digits, and for outpulsing digits to distant offices, when required. Incoming digits in the dial pulse mode, in the form of touch calling multifrequency signals from local lines, or in the form of multifrequency signals from incoming trunks are accommodated by the register sender 200. A group of register junctors RRJ provides an interface for the incoming digits which are transferred to tone receivers 201 via a sender-receiver matrix RSX. A ferrite-core memory RCM stores the digital information via a memory access circuit RMA under the control of a common logic control 202. Digits may be outpulsed by dial pulse generators or multifrequency senders 203, which are selectively connected to the register junctors RRJ via the sender-receiver matrix RSX. The common logic control 202, the memory access RMA, and the core memory RCM form the register apparatus of the present invention, and provide a pool of registers for storing call processing information received via the register junctors RRJ. The information is stored in the core memory RCM on a time division multiplex basis, and the memory RCM can be accessed by the data processor unit 130 on a random access basis.

The data processor unit 130 provides stored-program computer control for processing calls through the system 100. Instructions provided by the unit 130 are utilized by the register sender 200 and other subsystems for processing and routing of the call. The unit 130 includes a drum memory 131 for storing, among other information, the equipment number information for translation purposes. A pair of drum control units, such as the unit 132 cooperate with a main core memory 133 and control the drum 131. A central processor 135 accesses the register sender 200 and communicates with the main core memory 133 to provide computer control for processing calls through the system 100. A communication register 134 transfers information between the central processor and the originating markers 160 and the terminating markers 170. An input/output device buffer 136 and a maintenance control unit 137 transfer information between the maintenance and control center 140.

The maintenance and control center 140 provides a centralized facility for interfacing between the attendant and the system equipment. The center 140 provides displays and alarms to monitor system operation, and includes input-output devices, such as a teletypewriter 142, tape punch and tape reader unit 144, and a maintenance console 145, which cooperates with the maintenance control unit 137 of the data processor unit 130.

Line Group

The line group 110 is an equipment group which enables lines L000 to L999 to access the system 100. The line group 110 is also the equipment group from which lines L000 to L999 are accessed. In step-by-step electromechanical systems, each line has a dual appearance, one at a linefinder for originating calls and the other at a connector for receiving calls. In the system 100 of the present invention, customer lines have only one appearance which is at the line group for both originating and receiving calls.

The line group 110 may be considered to be a large switching network which provides two-way switching to 1,000 lines. For larger size offices, such as a 10,000 line exchange, additional line groups and other equipment are provided. On an originating call, the line group 110 provides concentration from 1,000 lines to 140 originating junctors. Each originating junctor provides a split between calling and called parties while the call is being established, thereby providing a separate path for signaling. On a terminating call, the line group 110 provides expansion from 120 terminating junctors to 1000 lines being served. The terminating junctors provide ringing control, battery feed, and line supervision for calling and called lines. Crosspoint switching networks, such as A network 111 and B network 112, are switching matrices and form a full-metallic path for signaling and transmission.

The line group 110 also includes line circuits LC1 to LC1,000, which are individually associated with the lines L000 to L999. The line circuits LC1 to LC1,000 each include line and cut-off reed relays to provide a call-for-service on an originating call, to mark the line busy on an originating or terminating call, and to remove the attachments from the line on a terminating call.

The line matrices are arranged in four stages -- A, B, C and R. The crosspoints used in the A, B, and C stages are two-winding three- or four-contact reed relay crosspoints. The R stage crosspoints are two-winding ten-contact crosspoints. The line matrices establish connections to the originating junctors and the register junctors RRJ of the register sender 200 from the lines L000 to L999 connected to their inlets for originating calls. The line matrices also establish connections to terminating junctors 170 to the lines L000 to L999 on terminating calls.

The A and B stages provide paths to the originating junctors and provide concentration from 1000 line inlets to 140 originating junctors. The R stage provides a temporary connection between the originating junctor and the register junctor RRJ on originating calls.

The A, B, and C stages provide paths from terminating junctors for terminating calls. Both originating and terminating calls are connected through the A and B stages, with separate outlets being provided on the B stage to originating junctors and C stages for handling each type of call. The C stage operates during terminating calls only, and provides a matrix that distributes the traffic from 120 terminating junctors to all parts of the A and B stages. This traffic is then expanded to a maximum of 1000 line inlets.

An originating junctor is used for every call originating from a local line, and remains in the connection for the duration of the call. The originating junctor extends the calling line's signaling path to the register junctor RRJ in the register sender 200, and at the same time provides a separate signaling path from the register sender to the selector group 120 for outpulsing, when required. The originating junctor isolates the calling line until cut-through is effected, at which time the calling party is switched through to the selector group inlet. The originating junctor also provides line lock-out.

A terminating junctor is used for every terminating call and remains in the connection for the duration of the call. Its functions include ringing control, battery feed, and line supervision for calling and called lines.

There is provided a connect and access circuit (not shown) which is associated with the line matrices of the line group 110. The purpose of this circuit is to provide a means for connecting a marker to a matrix or a junctor to permit the marker to manipulate them, to perform tests on them, and to receive information from them.

Selector Group

The selector group 120 is an equipment group which provides intermediate mixing and distribution of the traffic from various trunks and junctors on its inlets to various trunks and junctors on its outlets. The outlets of the selector group 120 are arranged so that a path may be selected to one of a group of equipment on its outlets. Line groups are connected to a plurality of outgoing trunks 121 or other line groups through the selector group 120, and a plurality of incoming trunks 152 are connected to line groups or outgoing trunks through the selector group. An analogy may be made between the functions of the selector group 120 of the system 100, and those of selector switches of the electromechanical step-by-step system.

The selector group 120 comprises a selector matrix, such as the A stage 122, to provide the signaling and transmission paths, and connect and access equipment (not shown) which controls the selector group 120 in response to the terminating marker 170. The crosspoints used to form the switching network in the selector group 120 are two-winding four-contact reed relays.

The selector matrix comprises three switching stages -- A, B, and C. The function of the three-stage selector matrix is to interconnect the originating junctors, the incoming trunks, and special local facilities, such as the insertion junctor 123, with the terminating junctors, the outgoing trunks 121, intertoll, EAS, toll terminating, and special local facilities on a "fan-out" basis.

The connect and access circuit (not shown) associated with the selector matrix of the group selector provides a means for connecting the terminating marker 170 to a matrix to control the matrix, to permit the marker to perform tests on it, and to receive information from the matrix. Only the terminating marker 170 can access the selector matrix.

Trunk-Register Group

The trunk-register group 150 provides access to the system 100 from the group of incoming trunks 152, or special feature junctor circuits (not shown).

The trunk-register group comprises a two-stage trunk-register matrix to provide the signaling and transmission paths, and connect and access circuitry (not shown) which controls the matrix of the trunk-register group in response to the originating marker 160.

The trunk-register matrix provides a signaling path from the distant party, via the associated trunk or junctor to the register junctor RRJ, and a signaling path between the register junctor RRJ and the selector group 120. Thus, the trunk-register matrix provides the connection for the trunk or junctor to the register junctor RRJ during sending and receiving of dial pulse or tone signaling.

Originating Marker

The markers used in the system 100 are electronic units which control the selection of idle paths and the establishment of connections through the matrices. The originating marker 160 detects calls for service in the line and/or trunk-register group 150, and controls the selection of idle paths and the establishment of connections through these groups. On line-originated calls, the originating marker 160 detects calls for service in the line matrix, controls path selection between the line and originating junctors, and between originating junctors and register junctors. On incoming trunk calls, the originating marker 160 detects calls for service in the incoming trunks connected to the trunk-register 150 and controls path selection between the incoming trunks 152 and register junctors RRJ.

Originating markers are provided in pairs, operating simultaneously but not in synchronism. In case of marker fault, the redundant marker can handle the entire traffic load. Ordinarily, the same originating markers are used for setting up connections through both line and trunk-register matrices. When the traffic warrants it, originating markers are provided separately for the line matrix and for the trunk-register matrix in an office. The marker pair handling incoming trunk traffic in a selector section only can serve up to 10 trunk-register groups.

The communication transceiver accepts data from the assigner, inlet control, and outlet control circuits as to the identity of the matrix accessed, inlet saved, and junctors to be used to service the call. The communication transceiver forwards this data to the data processor unit. For maintenance, the transceiver is used by the data processor unit to gather status information from the marker for analysis of fault conditions, and to instruct the marker to change status, i.e., on-line to off-line. It is also used to establish test calls for the purpose of error and fault separation. Test call results determine reconfiguration and later enable detailed diagnostics to be performed.

The originating marker can work in a reverse mode as well. That is, the data processor sends a frame of data to the communications transceiver, indicating inlet identity, and originating and register junctors identity. This mode is employed when routining the office equipment. In this case, the inlet control will access only the inlet indicated. The outlet control section will be restricted to a particular junctor if a junctor identity has been included in the data frame. The communications transceiver then returns a data frame response to the data processor unit as in a normal call.

Terminating Marker

The terminating marker 170 controls the selection of idle paths and the establishment of connections for terminating calls. The terminating marker 170 controls the establishment of all calls through the selector matrix of the selector group 120 and, in the case of a call terminating on a local line, establishes connections through the line matrix of the line group 110.

The marker connects an inlet of the selector group 120 to an idle junctor or trunk circuit. If the call is to a local line, the terminating marker selects the idle terminating junctor and connects it to a line group inlet, as well as connecting it to a selector group inlet. For this purpose, the appropriate idle junctor is selected and a path through a line group 110 and the selector group 120 is established.

A terminating marker is designed to serve up to 8 selector groups and up to 10 line groups when serving an office section and up to 10 selector groups when serving a selector section. They are provided in pairs and operate alternately. One of the markers of a pair is selected for each termination, but the two markers are not operated simultaneously. In case of a marker fault, the alternate marker can handle the entire traffic load.

The communications transceiver is the primary link for signaling and communicating with the data processor unit, both for call processing and maintenance activity. Switching instructions are received from the data processor unit as to a connection to be established. This information (data) indicates the selector group inlet to be serviced and the selector group outlets having the correct junctor or trunk circuit group, and includes information to be loaded into these junctors or trunk circuits. If the call is to a line group, the data also indicates the line to which the call is to be terminated. At the end of call processing, the communications transceiver returns a data frame (block of information) to the data processor unit containing the above information along with the identification of the exact junctor or trunk chosen.

Register Sender

The register sender 200 is a time-shared common control unit with the ability to register and process 192 calls simultaneously from local lines or incoming trunks. The register sender 200 provides the electronic time-shared register apparatus for receiving and storing incoming digits, and pulse generating sender circuitry to forward a call toward its destination. In this regard, the register sender 200 generally includes a plurality of register junctors RRJ which are space-divided electromechanical access circuits for providing an interface between the switching matrices of the system 100 and the time-shared register apparatus, which includes the electronic logic of a common logic control 202, a ferrite-core memory RCM to store digits to be received and sent via the register junctors RRJ, and supervisory information pertaining to the call under the control of the common logic control 202 via a memory access RMA. A sender-receiver matrix RSX selectively connects a plurality of tone receivers 201 and senders 203 to the register junctors RRJ for signaling modes other than the dial pulse mode which is provided for by the register junctors RRJ.

The time-shared common logic control 202 of the register sender 200 is duplicated and runs identical operations in synchronism with one another. Under normal conditions, both sets of time-shared equipment are partially active, one set serving one-half of the register junctors RRJ and the other set serving the remaining half of the register junctors RRJ. In case of equipment faults, either set of time-shared equipment can serve all of the register junctors RRJ.

The space-divided equipment of the register sender 200 includes the register junctors RRJ, the senders and receivers, and the sender-receiver matrix RSX. The register junctors RRJ with their associated multiplex equipment (not shown) provide an interface between the space-divided matrix outlets connected to the register junctors RRJ and the time-shared common logic control 202. The sender-receiver matrix RSX provides a concentration of the traffic from the register junctors RRJ to the tone senders and receivers under the control of the common logic control 202. The senders 203 provide for sending in the multifrequency mode, and the receivers provide for receiving in either the touch-calling multifrequency mode from the local lines or the multifrequency mode from the incoming trunks 152.

The register junctors RRJ are the entry and exit point of the register sender 200 for information transferred between the switching network and the register sender. The register junctors enable the register sender to provide the following features: dial pulse receiving and sending, coin and party testing, line busy, and dial tone and reorder tone application. The incoming and outgoing matrix paths are held by the register junctors RRJ during call processing. The register junctors comprise electromechanical components for compatibility with lines, trunks, and switching network circuits, however they also include electronic interfacing circuits which are similar to those in the markers for compatability with the electronic common logic control 202. Signals from lines, trunks, and network circuits are received by the register junctors and forwarded to the common logic control for processing.

The common logic control 202 contains the control logic for call processing by the register sender 200. The purpose of the common logic control 202 is to perform all functions associated with receiving, sending, and timing of digits, and to control processing of calls by generating commands for other circuits in the register sender and for the switching network. Since the common logic control 202 operates on a time-shared basis to store call processing information in the memory RCM, the common logic control 202 has the ability to register and process 192 simultaneous calls. The common logic control works closely with the core memory RCM which together form the register apparatus of the present invention, and which provides storage of information concerning the calls in progress and information relating to the data processor unit 130.

The core memory RCM is a conventional ferrite core memory, which need not be disclosed in detail. The memory RCM automatically restores the information in the same cores after a read operation, and it likewise automatically clears the information from the cores immediately prior to writing information into them. It is to be understood that the memory RCM could also be any suitable type of non-destructive read-out memory.

DATA PROCESSOR UNIT

The data processor unit 130 is the central coordinating unit and communication hub for the system 100. The data processor unit 130 is in essence a general-purpose computer with special input-output and maintenance features which enable it to process data. It uses hardware interrupts with eight levels of priority, and several sources per level. It has a two-microsecond main memory cycle.

The call processing operation includes control of: the originating process communication (receipt of line identity, etc.), the translation operation, route selection, and the terminating process communication. The translation operation includes: class-of-service look-up, inlet-to-directory number translations, matrix outlet-to-matrix inlet translation, code translation, and certain special feature translations. The maintenance operations include: monitoring the system for trouble conditions, trouble access to system units, routining, storage of information about certain calls being established, trouble diagnosis, and printout. Traffic operations include: monitoring equipment usage and overloads, providing the proper response to relieve overload conditions, and providing a means to measure the quality of service.

The data processor unit assembles information that is received from markers and the register sender 200 into a series of call processing instructions which are sent to the markers and register sender to provide for processing of service demands throughout the system 100. Storage is also provided for a directory number group consisting of 25,000 blocks of numbers which can be associated with up to a maximum of 16 different office codes. A library is maintained of semi-permanent information concerning each line inlet's classification, and of tables for use in translating customer or machine pulse information into switching instructions. There is also maintained a library of semi-permanent information concerning the grading of the office and the connection of all trunks and junctors, and a library of semi-permanent instructions which are utilized for automated diagnosis and maintenance of all portions of the system essential to call processing. Required traffic monitoring functions for calls handled by the system 100 are performed by the unit 130.

The data processor unit is comprised of a computer complex 130 and a drum memory system. The computer complex is comprised of the central processor 135, ferrite-core main memory 133, computer memory control (FIG. 2), and communication links including communication register 130.

The computer complex 130 is a high-speed digital computer which is designed for high availability and to allow the system to expand in both features and additional equipment. This is accomplished through the inherent flexibility of the stored program and the orderly expansion of the computer complex 130 with use of modular design. Through the use of its stored-program capability, the computer complex 130 is used in call processing for making high-speed translations. It is also used to control the communications between all sub-systems.

Another important function of the computer complex 130 is in the area of maintenance for the entire system. By utilizing its stored-program capability, the computer complex recognizes error conditions in other sub-systems, isolates the error to a particular sub-system; removes it from service and assists in locating the error to a minimum of replaceable plug-in modules. The computer complex also provides for communication with other central office equipment such as ticketers, routiners, and call metering equipment.

The central processor 135 is the central control unit of the computer complex 130 and is used to obtain program instructions stored in the main memory 133, interpret each instruction, and perform the necessary operations specified by the instruction. The main memory 133 is a ferrite-core memory and stores the system control program which is an executive program, and call processing programs whose frequency of usage requires that they be locally available.

The drum memory 131 provides mass storage for translation data, diagnostic programs, tables, and other information. The drum control unit provides control for transferring information between the main core memory 133 and the drum memory 131, on a cycle stealing basis, so that there is no interference with the central processor in accessing the memory 133.

Either of two possible drum memory arrangements may be employed. The entire drum may be accessed by one drum control unit. This method may be used for low traffic on the drum. In the case of high traffic on the drum, the drum is divided into two storage areas and a separate drum control unit is provided for accessing each section of the drum simultaneously.

The drum control unit has the ability to provide two different search modes; the block transfer or extended memory mode, and the associative search mode. The block transfer mode of operation is used in transferring programs and tables between computer core memory and the magnetic drum. (The programs and tables which are drum resident are those which are not used frequently enough to warrant the cost of core residence). The block transfer takes place via the computer memory control (FIG. 2) without interferring with the operation of the central processor, which continues its operation. The location of each word on the drum is uniquely defined by the segment number and an angular index value. The angular index value, 1-11,000 defines a drum location relative to a single fixed reference point (a single pulse on a clock track). A counter, advanced one count per drum location, is used to develop the index value. The pulses for advancing and resetting this counter are derived from clock tracks written on the drum. The drum index clock track consists of 11,000 consecutive pulses (one for each location), and the drum reset pulse consists of one pulse per revolution of the drum.

The associative search mode, used for translations in call processing, requires an associative search of the information stored on the drum to find the record to be transferred. This is a "read only" mode, and the search may be either single-level or multi-level. This mode likewise proceeds while the central processor continues operation independently.

Maintenance and Control Center

The maintenance and control center 140 serves as a centralized facility for interfacing between the operating personnel and the switching system 100. The center 140 serves as the focal point for monitoring system and sub-system operation, exercising manual controls, initiating test call routines and test programs, and providing print-out of maintenance information. Additionally, the maintenance and control center 140 provides a visual indication of all traffic conditions along with sufficient control for switch management.

The maintenance and control center 140 also provides the interface for use of optional remote test equipment to provide compatibility with other testing in the exchange area. The remote test equipment would be used to provide for testing of lines served by an office located beyond the supervisory limits of the local test trunks in the main office.

Multi-Section Offices

A switching unit may be divided into several sections of equipment. These sections are: (a) office section(s), (b) selector section, and (c) control section.

Office Section

"Office section" is a term applied to a given grouping of matrices and markers in an office. The office section includes a number of line groups, a number of selector groups, a single pair of terminating markers, one or two pairs of originating markers, and one or two trunk-register groups. An office section provides a standardized arrangement of switching equipment for up to 10,000 lines and associated trunks and junctors. The office section may have up to ten line groups. These line groups will provide up to 10,000 lines (10 × 1,000) or 12,500 directory numbers. Although the office section serves up to 10,000 lines, there is no association with directory numbers such as a single office code with the office section. The lines are only associated with respect to the traffic they generate.

Up to five trunk-register groups may be included in the office section. These trunk-register groups will provide for up to 1,000 trunk circuits (5 × 200) and the special junctors which require a register junctor. All incoming and two-way trunk circuits and a few insertion junctors require connection to a trunk-register group. Most insertion junctors and any intermediate junctors from a "Selector Section" do not require connection to a trunk register group.

The office section may have up to eight selector groups. These groups will provide up to 2400 inlets (8 × 300). Since the line groups will require 1400 or less inlets for originating junctors (10 × 140 maximum), there will be 1000 inlets or more for junctors and trunk circuits. These will include inlets for insertion junctors, intermediate junctors, incoming trunk circuits, and the incoming portion of two-way trunk circuits.

One or two pairs of originating markers may be included in an office section. One pair of originating markers will handle ten line groups as well as some trunk-register groups. The number of trunk-register groups which can be served is a function of traffic. If all trunk groups are stop-dial trunks, all of the trunk-register groups may be served by the same marker pair that is serving the ten line groups. If a large number of inter-digitally switched trunks must be served, a second originating marker pair may be required to serve those trunk-register groups which cannot be served by the first originating marker pair.

A single pair of terminating markers is included in an office section. The reason for this is that both the office section and the selector section are built around a terminating marker pair.

A system switching unit may contain one or two office sections, equipped as required in accordance with the information presented in the preceding paragraphs.

When the number of inlets provided by eight selector groups would be too small, the office must be equipped with a selector section (incoming portion) or the number of lines and/or trunks per office section must be reduced. When the number of outlets provided by the selector groups would be too small, the office must be equipped with a selector section (outgoing portion) or the number of lines and/or trunks per office section must be reduced. When the traffic limits imposed would be exceeded, the number of lines and/or trunks per office section must be reduced.

The choice of the ultimate number of selector groups within an office section affords some degree of flexibility. The number chosen must be made such as to plan for the ultimate sized office. (This consideration is also true when determining the requirements for selector group outlets.) If the office will ultimately require that trunks be served by a selector section, the number of selector groups may be kept less than the maximum, and new trunks served by either the selector section or by a second office section so as to avoid adding a selector group which later would not be required.

Selector Section

A selector section is a term applied to a given grouping of markers and matrices in a system. This section is a supplementary section which provides for trunk switching. The selector section contains the same equipment as an office section, except it does not have any line groups and it may have up to ten selector groups. It may also include up to fifteen trunk-register groups, equipped as dictated by the number and type of trunks. The selector section may include up to three originating marker pairs, and a terminating marker pair.

In any system, the selector section may be referred to by its function, such as incoming selector section, outgoing selector section, or a combination of the two. An incoming selector section extends incoming trunks to office sections and outgoing trunks, and where required, to an ougoing selector section. An outgoing selector section extends the outlets of office sections and incoming trunks, and where required, the outlets of an incoming selector section, to outgoing trunks. A selector section is sometimes provided in two parts to function as both an incoming selector section and an outgoing selector section.

Control Section

The control section is that part of the switching system used to receive incoming signals from lines or trunks, to control the call processing and translation, to control switching of the call by the terminating markers, and send outgoing signals to the line or trunk. The control section also provides for maintenance and control of the system.

A control section always contains the following common control equipment:

a. one register-sender with redundant RS common logic unit and associated temporary memory for maintainability. Provides for registering the called number, sending interoffice signaling, and storage of supervisory information.

b. one data processor, with redundant circuitry, utilizes stored program control for call processing control, translation, maintenance, and traffic functions.

c. one maintenance and control center. Provides display and control for the craftsman.

No switching system may have more than one control section. It may, however, include two register-senders if traffic warrants it.

SYSTEM OPERATION

This part presents a simplified explanation of how three basic call types are processed by the system. The following call types are covered in the order listed: (1) call from a local party served by one switching unit to another local party served by the same switching unit, (2) call from a local party served by a switching unit destined for a party served by a distant office, via an outgoing trunk, and (3) call coming into the office via an incoming trunk, and terminating at a local customer's line served by the switching unit.

In the following presentations, reed relays are referred to as correeds. All of the data processing operations which take place are not included.

Local Line-to-Local Line Call

When a customer goes off-hook, the D.C. line loop is closed, causing the line correed of his line circuit to be operated. This action constitutes seizure of the equipment, and places a call-for-service. One originating marker is assigned to the call. A line identifier in the originating marker upon detecting a call-for-service scans to select only one line if a plurality are calling, and identifies the equipment number (matrix and terminal identity), in the manner disclosed in U.S. Pat. No. 3,211,837 by L. Bruglemans.

After the marker has identified the calling line number (line matrix number, AB group number, A unit, and A unit inlet), and has preselected an idle path identified in terms of the B unit, B unit outlet, and R unit outlet; this information is loaded into the marker communication register and sent to the data processor unit via its communication transceiver.

While sending line number identity (LNI) and route data to the data processor, the marker operates and tests the path from the calling line to the register junctor. The closed loop from the calling station operates the register junctor pulsing relay, contacts of this relay are coupled to a multiplex pulsing highway.

Upon detecting the pulsing highway and a notification from the data processor that an origination has been processed to the specified register junctor, the central control circuits set up a hold ground in the register junctor. The marker, after observing the register junctor hold ground and that the network is holding, disconnects from the matrix. The entire marker operation takes approximately 75 milliseconds.

The data processor unit, upon being informed of a call origination, enters the originating phase. The originating phase is one of the three major phases of the call processing function, and can best be defined as all program functions that are performed from the time the originating marker informs the data processor of an originating call until the register-sender is initialized to receive the incoming digital information.

As previously stated, the "data frame" (block of information) sent by the marker includes the equipment identity of the originator, originating junctor and register junctor, plus control and status information. The control and status information is used by the data processor control program in selecting the proper function to be performed on the data frame.

The data processor analyzes the data frame sent to it, and from it determines the register junctor identity. A register junctor translation is required because there is no direct relationship between the register junctor identity as found by the marker and the actual register junctor identity. The register junctor number specifies a unique cell of storage in the core memories of both the register-sender and the data processor, and is used to identify the call as it is processed by the remaining call processing programs.

Once the register junctor identity is known, the data frame is stored in the data processor's call history table (addressed by register junctor number), and the register-sender is notified that an origination has been processed to the specified register junctor.

Following the register junctor translation, the data processor performs a class-of-service translation. The class-of-service translation is needed because different inlets on the line matrix require different services by the system. Included in the class-of-service is information concerning dial tone, party test, coin test, type of ready-to-receive signaling required, type of receiver (if any) required, billing and routing, customer special features, and control information used by the digit analysis and terminating phase of the call processing function. The control information indicates total number of digits to be received before requesting the first dialed pattern translation, pattern recognition field of special prefix or access codes, etc.

The class-of-service translation is initiated by the same marker-to-data processor data frame that initiated the register junctor translation, and consists of retrieving from drum memory the originating class-of-service data by an associative search, keyed on the originator's LNI (line number identity). Part of the class-of-service information is stored in the call history table (in the data processor unit core memory), and part of it is transferred to the register-sender core memory where it is used to control the register junctor.

Before the transfer of data to the register-sender memory takes place, the class-of-service information is first analyzed to see if special action is required (e.g., non-dial lines or blocked originations). The register junctor is informed of any special services the call it is handling must have. This is accomplished by the data processor loading the results of the class-of-service translation into the register-sender memory words associated with the register junctor.

The register junctor returns dial tone and the customer proceeds to key (touch calling telephone sets) or dial the directory number of the desired party. (Party test on ANI lines is performed at this time).

The register junctor pulse repeating correed follows the incoming pulses (dial pulse call assumed), and repeats them to the register-sender central control circuit (via a lead multiplex). The accumulated digits are stored in the register-sender core memory.

In this example, a local line without special features is assumed. The register-sender requests a translation after collecting the first three digits. At this point, the data processor enters the second major phase of the call processing function -- the digit analysis phase.

The digit analysis phase includes all functions that are performed on incoming digits in order to provide a route for the terminating process phase of the call processing function. The major inputs for this phase are the dialed digits received by the register-sender and the originator's class-of-service which was retrieved and stored in the call history table by the originating process phase. The originating class-of-service and the routing plan that is in effect is used to access the correct data tables and provide the proper interpretation of the dialed digits and the proper route for local terminating (this example) or outgoing calls.

Since a local-to-local call is being described (assumed), the data processor will instruct the register-sender to accumulate a total of seven digits and request a second translation. The register-sender continues collecting and storing the incoming digits until a total of seven digits have been stored. At this point, the register-sender requests a second translation from the data processor.

For this call, the second translation is the final translation, the result of which will be the necessary instructions to switch the call through to its destination. The data processor initiates a request to the drum memory system for a look-up of the local directory number table (terminating lists) to provide the line equipment number of the called line and terminating class-of-service of the called line (including ringing code and special features). Grouping digits (selector outlet arrays) for the terminating junctors are obtained from a core-memory table look-up keyed on the terminating line matrix. The data processor also requests the drum memory system to determine the selector matrix inlet identity. This information is assembled in the dedicated call history table in the data processor core memory. Control is transferred to the terminating process phase. The digit analysis phase is complete.

The terminating process phase is the third (and final) major phase of the call processing function. Sufficient information is gathered to instruct the terminating marker to establish a path from the selector matrix inlet to either a terminating local line (this example) or a trunk group. This information plus control information (e.g. ringing code) is sent to the terminating marker.

On receipt of a response from the terminating marker, indicating its attempt to establish the connection was successful, the data processor instructs the register-sender to cut through the originating junctor and disconnect on local calls (or begin sending on trunk calls). The disconnect of the register-sender completes the data processor call processing function. The following paragraphs describe the three-way interworking of the data processor, terminating marker, and the register-sender as the data frame is sent to the terminating marker, the call is forwarded to the called party and terminated.

A check is made of the idle state of the data processor communication register, and a terminating marker. If both are idle, the data processor writes into register-sender core memory that this register junctor is working with a terminating marker. All routing information is then loaded into the communication register and sent to the terminating marker in a serial communication.

The register-sender now monitors the ST lead (not shown) to the network, awaiting a ground to be provided by the terminating marker.

The terminating marker decodes the line matrix specified for line termination, determines that the matrix is idle (no originating marker processing it) and assigns itself to the matrix. The terminating marker connects to the specified line and selector matrices by operating dedicated access correeds in the respective matrices. It then operates connect correeds accessing the selector inlet, selector AB and BC links, line AB and BC links, and the line equipment of the called line.

The marker checks the called line to see if it is idle. If it is idle, the marker continues its operations. These operations include the pulling and holding of a connection from the originating junctor to the called line via the selector matrix, a terminating junctor, and the line matrix. While controlling the path, the marker makes a series of checks to monitor the proper operation of the matrices, e.g., links are tested for busy, paths are pulled and checked for foreign potentials, and the complete path from selector inlet to line equipment is checked for continuity.

Upon receipt of the ground signal on the ST lead from the terminating marker, the register-sender returns a ground on the ST lead to hold the terminating path to the terminating junctor.

When the operation of the matrices has been verified by the marker, it releases then informs the data processor of the identity of the path and that the connection has been established. The data processor recognizes from the terminating class that no further extension of this call is required. It then addresses the register-sender core memory with instructions to switch the originating path through the originating junctor.

The register junctor signals the originating junctor to switch through and disconnects from the path, releasing the R matrix. The originating junctor remains held by the terminating junctor via the selector matrix. The register-sender clears its associated memory slot and releases itself from the call. The dedicated call history table (for that register) in the data processor core memory is returned to idle.

The calling party, now connected to the terminating junctor, loop seizes the battery-feed (BFI) correed. The terminating junctor splits the transmission path and connects ringing current to the called line and ring-back tone to the calling line. When the called party answers, a closed loop is detected by the ring-trip circuit of the terminating junctor, which removes ringing and ring-back tone from the line. The transmission path is completed and transmission battery is provided to both calling and called parties.

When the parties are through talking and hang up, the terminating junctor releases the terminating line matrix and the selector matrix. Release of the selector matrix releases the originating junctor which releases the originating line matrix. The cut-off correeds of both line circuits release, and the customer's line circuits are idled for future calls.

Local Line-to-Outgoing Trunk Call

The processing of a call originated by a local customer, but destined for a distant office, is handled the same as previously described for a "local-to-local" call up to the point where a three-digit translation has occurred. The digits are analyzed and it is determined that the call destination is not a local line. Operation from this point forward is described in subsequent paragraphs.

For this example, the call is originating from a rotary dial line. The customer is making a seven-digit EAS (extended area service) call requiring tandem switching through the connecting office. The connecting office is equipped for wink-start pulsing. The trunk to the connecting office is an E and M trunk requiring D.C. pulsing.

The data processor requests the drum memory system to access the drum to obtain routing tables from which the following information is obtained: (a) outgoing trunk group to the connecting office, (b) selector switching digits for use by the terminating marker, (c) codes for terminating marker selection or control of outgoing circuits, (d) signaling and sending modes used on this trunk group, and (e) alternate routing information.

The drum memory system also provides the originating junctor-selector inlet translation. The routing information and the class of the calling party allows the data processor to determine all register-sender instructions necessary to forward this call towards its destination.

The data processor writes the sending requirements into the register-sender core memory fields. These include the following information and instructions for this example: (a) early outpulsing of all digits received, (EOP field is set), (b) when seven digits are received, dialing is finished (TL field is set equal to 7), (c) close terminating loop in the register junctor, and (d) working with the terminating marker.

The network switching instruction is sent to the terminating marker via the communication register. The marker then makes various tests, selects a selector outlet, and completes a path thereto. When the marker recognizes that the path has been connected properly, it clears from the matrix and sends a message to the data processor indicating successful call completion, and the identity of the trunk that was used.

The data processor will place this information in the call history table and write into register-sender core memory that outpulsing may proceed when start signals have been received. When the distant office is prepared to receive digits, it will return an off-hook signal of approximately 150 milliseconds which the outgoing trunk converts to a ground on the S lead. This causes the stop dial (SD) relay in the register junctor to operate. At the end of the 150-millisecond period, the SD relay restores and outpulsing begins.

The register-sender will outpulse the digits accumulated at this point (early outpulsing) and will outpulse each additional digit as it is received from the customer (no digits are deleted or prefixed in this example). When seven digits have been accumulated and sent, the register-sender will signal the originating junctor to switch through.

The register junctor will release itself from the call, releasing the R matrix. The register-sender memory is cleared, and the call history table in the data processor is reset. The calling party now controls the outgoing trunk. When the called party served by the connecting office answers, they may begin to converse. The calling line is now connected to the connecting office via the line matrix, originating junctor, selector matrix, and outgoing trunk.

When the calling party disconnects, the outgoing trunk releases the selector matrix, releasing the originating junctor and line matrix. Release of the line cut-off correed idles the customer's line for future calls.

The outgoing trunk remains busy for a short time to insure release of the connecting office. It then returns to idle.

Incoming Trunk-to-Local Line Call

For purposes of explanation, it is assumed that a call has been placed by a customer served by a distant office, and the call is a locally-terminating EAS call. The signaling mode is dial pulse, and the trunk is arranged for loop seizure. It is further assumed that the local office has one central office code with less than 10,000 directory numbers, and the ABC digits of the called number have been absorbed by preceding equipment.

In this example, the local office arrangement includes both an office section and an incoming selector section. The incoming trunk is located on the incoming selector section. The call is terminating via the office section.

When the incoming trunk is seized from the distant end, the trunk-register matrix inlet lead is marked with resistance battery, denoting a call-for-service request.

An idle originating marker is assigned to this call. A scan of the inlet leads identifies the trunk calling for service. One register junctor is selected.

The calling trunk number identity (TNI) and the selected B outlet information are loaded into the marker communication register and sent to the data processor. The data processor enters the originating phase of the call processing function and executes a core translation of the data frame information which indicated the section, matrix, B unit, and B unit outlet selected. This translation yields the register junctor identity, which specifies the unique cell of storage in the core memories of both the register-sender and the data processor. Once the register junctor identity is known, the data frame is stored in the data processor's call history table (addressed by register junctor number).

The data processor also writes into the specified register-sender core memory location that the register should begin timing the arrival of pulsing over the line from the network.

While sending the TNI and path data to the data processor, the originating marker operates the path from the incoming trunk to the register junctor.

The incoming trunk loop, assisted by marker circuitry, seizes the A correed in the register junctor. Operation of the register junctor's A correed indicates a completed line loop to the register-sender common logic. Upon detection of the completed line loop, a hold is set in the register junctor. The marker, observing that the register junctor is busy and the network is holding, disconnects from the matrix.

Following the register junctor translation, the data processor performs a class-of-service translation as previously described for a local-to-local call. In the case of the incoming trunk call, the drum search is keyed on the trunk number identity (TNI). For a call now being processed, the class-of-service translation will indicate the mode of start signaling, mode of receiving, quantity and numerical value of previously absorbed digits, digit pattern to be expected, and the total number of digits to receive before requesting a final translation. These instructions are written into the register-sender core memory of the proper register junctor.

When the register-sender has accumulated a total of four digits, it requests the data processor to perform a translation. The data processor performs a memory core table look-up to determine grouping digits (selector outlet arrays) of intermediate junctors which connect the incoming selector and office sections. Note: An intermediate junctor is an interface device used between sections.

A check is made for an idle communication register and an idle terminating marker in the incoming selector section. When they are idle, the data processor writes into register-sender core memory that the register is working with the terminating marker.

Operation proceeds as previously described for a local-to-local call. The terminating marker, upon completing a path, returns a data transmission to the data processor indicating successful completion and the selected selector outlet of the incoming selector section. Control of the path is left to the register junctor.

The data processor performs a drum look-up to obtain the local selector section inlet identity of the intermediate junctor. If not previously performed, the data processor also performs a drum look-up of the terminating list to determine class-of-service and switching digits of the called line. To obtain the grouping digits of terminating junctors in the called matrix, the data processor executes a core table look-up. All the switching information is sent to a terminating marker in the office section.

The terminating marker processes the call as a normal local termination. The intermediate junctor appears as a register junctor to the terminating marker. When hold is returned to the selector by the terminating junctor, the intermediate junctor switches the supervisory lead through and the register junctor controls the entire path.

Switch-through of the incoming trunk is accomplished by the register-sender in the manner described for local calls, via originating junctors. When the called party answers, ground is returned from the terminating junctor to the incoming trunk via the S lead. The incoming trunk then returns answer supervision to the distant office.

DUPLICATED SYSTEM

FIG. 2 is a simplified block diagram showing in broad scope how subsystems are duplicated and how the system may be reconfigured. Reconfiguration is the removal of a malfunctioning subsystem. When a malfunction is detected and isolated the system must be reconfigured in order to continue normal call processing. Any single subsystem of a pair can be removed from call processing without seriously degrading service. Both subsystems of a pair must not be removed from call processing; since this would result in the system being out of service. The system can continue call processing with only one subsystem of each pair functioning.

Normally computer A and computer B operate in synchronism, and at particular intervals during each clock cycle which is related to the access of a word of memory, certain points of the systems are compared and the comparison is monitored by the third party circuit. The third party circuit contains logic enabling it to control the reconfiguration of the system, and to perform functions such as controlling one of the computers to analyze the other.

The register sender subsystems A and B in like manner are operated in synchronism and certain points of the systems compared during each cycle. Normally register sender A communicates with computer A and register sender B communicates with computer B. One of the computer-register sender combinations supplies output signals to other subsystems of the system. The system may be reconfigured so that either computer-register sender combination supplies the output signals, or for example computer A may communicate with register sender B to supply output signals or computer B may likewise work with register sender A.

The two computer subsystems A and B as a pair may work with either of the drum memory systems, or if one computer is out of service the other computer may work with either drum memory system. The computer and the drum memory system each access the main core memory via the computer memory control.

The originating markers A and B are arranged to process calls simultaneously, with the limitation that they cannot both be working with the same network matrix. They have an interlock arrangement such that any given call request will be serviced by only one of the originating markers. The terminating markers A and B are arranged so that only one may be serving calls at a time, but they are used alternately. There is also an interlock arrangement to prevent originating and terminating markers from accessing the matrices simultaneously. The communication registers A and B are arranged so that one of them is on line, for example, the communication register A, while the other is on standby. For example, when communication register A is on line communication register B is in standby. Both computers work with the communication register which is on line.

In like manner the input-output buffers A and B have one on line while the other is in standby, and both computers work with the one which is on line.

COMPUTER CENTRAL PROCESSOR

The common control apparatus of the switching system is shown in FIG. 3 in a block diagram which shows the duplication of units, and how they interface with the computer central processor CCP. The computer central processor is duplicated comprising units CCP-A and CCP-B. A computer third party CTP provides for maintenance and control functions, including coupling of the processors to a computer programming console PRC. The register-sender subsystem in a maximum configuration comprises two duplicated register-sender units, namely register-sender unit RS1A and its duplicate RS1-B, and unit RS2A and its duplicate RS2B.

The apparatus in FIG. 3 other than the register-sender subsystems and the console PRC comprise the data processor unit DPU.

Each of the computer central processors has its own core memory and computer memory control, for example core memory CMM-A and memory control CMC-A for the computer central processor CCP-A, and the duplicate units CMM-B and CMC-B for processor CCP-B. There is also a drum memory system with up to six units in the maximum configuration. The computer memory control has eight ports for each of the duplicate units. The computer memory control CMC-A uses ports 1, 3 and 5 principally for access to the drum memory systems 1, 3 and 5 and may also use ports 2, 4 and 6 for access to the drum memory systems 2, 4 and 6; while the memory control unit CMC-B uses ports 2, 4 and 6 for principal access to the drum memory systems 2, 4 and 6 and may also use ports 1, 3 and 5 for access to the drum memory system 1, 3 and 5. Each of the memory controls uses port 7 for access to its own computer central processor, and may use port 8 for access to the other processor. The memory control unit controls the transfer of data between the main core memory CMM and one of the ports for transfer to a drum memory or the central processor.

The computer line processors provide for processing of interrupts from other units in the data processing unit, the register-sender subsystem, and the markers. This unit is duplicated with computer line processor CLP-A coupled to the computer central processor CCP-A and the computer line processor CLP-B coupled to the computer central processor CCP-B, with interconnections between the two computer line processors.

The computer channel multiplex unit CCX-A connected to the computer central processor CCP-A, and unit CCX-B to unit CCP-B provides for input-output functions with various device buffers and the communication registers. The communication register comprising duplicated units CCR-A and CCR-B provides for communication with the markers as shown in FIG. 1. The channel device buffer CDB-A and its duplicate CDB-B provides for input-output to a local maintenance teletype-writer, a high speed paper tape punch, and a data set for remote teletypewriters; while its duplicate CDB-B provides for input-output to a local office administration teletypewriter and a high speed paper tape reader. The ticketing device buffer TDB-A and its duplicate TDB-B (not shown in FIG. 2) provide for coupling to a magnetic tape unit and scanner. The maintenance device buffer MDB-A and its duplicate MDB-B provide for input-output from a pushbutton control panel and displays, power monitors and alarms, and maintenance routine logic.

The registers shown in FIG. 3A are used primarily for arithmetic operations and address modification.

The A register, the main arithmetic accumulator, is a 24-bit register used in data transfer between the central processor and the register-sender, and between the central processor and the channel multiplexer via the data bus, as well as for all arithmetic operations. The A register can be shifted both logically and arithmetically.

The arithmetical operations are performed by the arithmetic logic unit ALU in conjunction with the A, Q, S and Y registers.

The Q register is a 24-bit register used in conjunction with the A register for shift and rotate operations. It is also used as an auxiliary arithmetic register for multiply and divide operations. It is used to hold the multiplier and the lower order bits of the product in a multiply process. For division, it is used for the low order bits of the divident. It accumulates the quotient and finally holds the resultant remainder.

The S register is a 24-bit register used during arithmetic operations and during address modification when placing a main memory address on the address bus.

The Y register is a 24-bit register used during arithmetic and logical operations. It is one of the inputs to the arithmetic logic unit ALU. It cannot be accessed by the program.

The instruction register IR is a 24-bit register that receives all instructions (coded information for the operation to be performed, address field, and the method of addressing) from the main memory via the computer memory control and the data bus.

The three index registers X1, X2 and X3 are 15-bit registers used for address modification, and as a counter.

The page register PR is a 6-bit register used to specify bits 15 and 16 of the address bus. It operates in conjunction with the program counter to address a location within a memory page. The page register is made up of three sections: the "instruction field" (bits φ and 1), the "branch field" (bits 2 and 3), and the "data field" (bits 4 and 5).

The last program count register LPC is a 15-bit register used to store return linkage to the running program during processing. It is continually updated by the program counter.

The last page reference register LPR is a 4-bit reigster used as an extension of the last program count register. It is continually updated by the page register. The last page reference register is made up of two sections: the "last instruction field" (bits φ and 1), and the "last data field" (bits 2 and 3). The "last data field" is loaded from the "data field" of the page register. The "last instruction field" is loaded from the "instruction field" of the page register.

The central processor includes a program counter and a shift counter.

The program counter PC is a 15-bit binary counter used to sequentially count the address of instructions. The program counter holds the address within a page of the next instruction to be retrieved from core memory. It is used with the page register to locate this address. This counter is incremented (increased by one) for each instruction to establish program sequence.

The shift counter SC is a 6-bit counter used to control the number of shifts during shifting operations.

SYMBOLISM FOR GATES, BISTABLE DEVICES AND EQUATIONS

The common logic circuits of the system are generally implemented with integrated circuits, mostly in the form of NAND gates, although some other forms are also used. The showing of the logic in the drawings is simplified by using gate symbols for AND and OR functions, the AND function being indicated by a line across the gate parallel to the input base line, and the OR function being indicated by a diagonal line across the gate. Inversion is indicated by a small circle on either an input or an output lead. The gates are shown as having any number of inputs and outputs, but in actual implementation these would be limited by loading requirements well known in the art. Latches are indicated in the drawing by square functional blocks with inputs designated S and R for set and reset respectively; the circuits being in practice implemented generally by two NAND gates with the output of each connected to an input of the other, which makes the circuit a bistable storage device. The block symbol for the latch implies inverters at the inputs so that it is set and reset with signals at the "one" level. The logic also uses bistable devices in the form of JK flip-flops implemented with integrated circuits, indicated in the drawings by rectangles having the J and K inputs indicated by a small semicircle, a clock input indicated by C, and set and reset inputs indicated by S and R. Not all of the inputs for these devices are shown in the drawings. The J and K inputs are each actually AND gates having three external inputs, but the unused inputs which are actually terminated in some manner are not shown on the drawings. The S and R inputs are effective at the zero level, the J and K inputs at the one level, and the C input on a trailing edge.

While some discrete transistor circuits are used for interfacing with relay circuits, most of the electronic circuits of the system of FIG. 2 are implemented with integrated circuits of the Sylvania SUHL TTL high level logic family or equivalents. The NAND gates used to implement AND and OR functions include types SG 43, SG 63, SG 132, and SG 143. The AND-OR functions are also implemented with chips having AND gates feeding a NOR gate such as types SG 53 and SG 113. JK flip-flops may be type SF 53.

Boolean expressions are used to designate signal leads in the drawings, and in equations and miscellaneous references in the specification. In the expressions for basic Boolean elements, capital letters, numbers, spaces and hyphens are used. The expressions for elements may also include parentheses enclosing two numbers separated by a hyphen, indicating the first and last of a group of bit positions of gates enabled by a control signal. For example the expression IR(φ - 5) - DSO is a single Boolean element. In combinations of elements, the period (.) is used for the AND function, the plus sign (+) for the OR function, and the apostrophe (') for negation. In a string of elements separated by periods and plus signs without parentheses or brackets, the AND operations are performed first and then the OR functions; for example A + B.C + D is the same as A + (B.C) + D. Parentheses and brackets are used in the usual manner indicating operations in inner parentheses are performed first, then those in outer parentheses or brackets, etc. On the drawings the minus sign (-) at the beginning of an expression indicates negation of the entire expression following it, and not merely the first element if there is more than one. The period may be omitted before or after parentheses which implies the AND function; but it cannot otherwise be omitted between elements, since a space can occur within an element.

In the equations, storage devices are indicated by using separate equations for the various inputs. For simple NAND gate type latches the set and reset inputs are indicated by (S) and (R). For JK flip-flops the inputs are indicated by (J), (K), (C), (S)' and (R)'. The apostrophe for the set and reset inputs indicates that the zero level is effective, namely the negation of the expression after the equal sign (=). The trailing edge of the entire expression is effective for the clock input. The combination of the three leads for J and K inputs is indicated by a single equation.

Throughout the description and drawings, it is implied that all circuits and signals relate to unit A of duplicated units, unless specifically indicated by a suffix -A or -1 for unit A, or a suffix -B or -2 for unit B.

TIMING FOR THE COMPUTER CENTRAL PROCESSOR

The timing generator CPT is shown in part in FIG. 4. There are additional control circuits not shown which will be described by Boolean equations.

The timing generator is designed to provide the timing increments upon which the instruction set of the central processor is structured. The basic timing intervals are the cycle which is two microseconds long, the level which is 500 nanoseconds long, and the pulse which is 100 nanoseconds long.

The timing is dependent upon a source providing a constant train of pulses at a 10 megahertz rate with a duty cycle of approximately 50 percent. This is provided by clock circuits which are a part of the third party circuit CTP. There is provided a main clock having its output train of pulses on lead MOA and a standby clock having its output train of pulses on a lead SOA. The third party circuit includes logic for monitoring the outputs of the clocks and insuring that one and only one of them is supplying output at all times. The two output leads are connected to the timing generators of both of the duplicate computer central processors CCP-A and CCP-B. FIG. 4 is the timing generator CPT of the processor CCP-A. Logic represented by exclusive OR gate 411 gates the train of pulses from whichever of the leads MOA or SOA they are occurring and supplies them to other logic circuits of the timing generator as the basic clock control.

The timing generator includes three main storage devices that are continually pulsed by the clock train from gate 411. These storage devices are required to permit an orderly shutdown of the timing generator, as well as an orderly processing during operation of the timing generator. These storage devices comprise JK flip-flops START CLK, CLK and SYNC. The clock inputs C of all three are connected to the output of gate 411. The two outputs of flip-flop START CLK feed respectively into the J and K inputs of flip-flop CLK. The purpose of flip-flop CLK is to prime flip-flop SYNC, to prime the basic timing pulse TCP and to prime the data bus and address bus of the computer central processor. The function of the flip-flop SYNC is to act as a primer for the basic timing pulse TCP, and as such is controlled by feedback from the main memory system by the register-sender memory system.

The basic timing pulses on lead TCP are normally supplied from one of the AND gates 413 or 414, but may also be supplied via the lead PULSE from the third party circuit. These three sources are gated via OR gate 415 to the lead TCP. The train of clock pulses from gate 411 is supplied as an input to both gates 413 and 414 as well as the three flip-flops previously mentioned. If the two processors are operating in a synchronization a signal on lead CYSYNC enables gate 414, whereas if the processors are not operating in synchronization the zero level signal on this lead via inverter 412 enables gate 413. If the processors are not in synchronization the coincidence of signals from flip-flops CLK and SYNC along with the signal from gate 412 enables gate 413 to gate the clock pulses via gate 415 to lead TCP; whereas if the processors are operating in synchronization it is required in addition that the duplicated processor have its synchronization flip-flop set to supply a signal on lead SYNC B, enabling gate 414 to supply the pulses via gate 415 to lead TCP.

The pulse counter shown as a single block 416 comprises five JK flip-flops, not shown, whose outputs are respectively P1 through P5. These five flip-flops are connected as a ring counter with the one and zero outputs of each connected respectively to the J and K inputs of the following flip-flop, the P5 outputs being connected to the P1 inputs; and the clock inputs are supplied from lead TCP for all five flip-flops. The counter is advanced on the trailing edge of each clock pulse, thus the outputs appear for 100 nanoseconds on each of the output leads in turn.

The level counter comprises four JK flip-flops L1 through L4. The clock inputs of these four flip-flops are supplied from lead P5, so that the level counter may advance once each 500 nanoseconds on the trailing edge of pulse P5. The output of a gate 450 is connected to the J and K inputs of flip-flops L1 and L2, while the output of a gate 460 is connected to the J and K inputs of flip-flops L3 and L4. In addition flip-flop L1 has another J input from L4, and the flip-flops L2, L3 and L4 have J inputs from leads SET L2, SET L3 and SET L4 respectively.

The cycle counter comprises JK flip-flops C1, C2 and C3. The lead L4 is connected to the clock as well as the J and K inputs of all three of these flip-flops so that the cycle counter may be advanced once each two microseconds on the trailing edge of the pulse on lead L4. In addition the flip-flops have J inputs connected respectively to leads GOC1, GOC2 and GOC3, and a K input of flip-flop C1 is connected to lead GOC2, a K input of flip-flop C2 is connected to an OR gate having inputs from leads GOC1 and GOC3, and a K input of flip-flop C3 is connected to lead GOC1. The signal on lead -CLR is used to set flip-flops P5, L4 and C3 and to reset the other flip-flops.

There are a number of JK flip-flops not shown which are a part of the timing generator, that are combinations of cycles, levels and pulses. It is necessary to supply these signals from storage devices, because if they were implemented with AND gates providing AND and OR functions their outputs would not be stable during the intended interval. Unless otherwise stated the clock inputs for these flip-flops are from lead TCP. The first has J inputs from leads L1, P2, and a lead -C2(MUL + DIV); and K inputs from leads L2 and P5; and provides an output L1(P3 + P4 + P5) + L2. The next flip-flop has J inputs from leads -C2(MUL + DIV), P4 and L2, and K inputs from leads P5 and the output of a gate providing the function (L3 + L4); and has an output providing the function (L2.P5 + L3). The next flip-flop has J inputs from leads L1, P4 and the lead -C2(MUL + DIV), and K inputs from leads (L3 + L4) and P1; and provides the output function (L1.P5 + L2 + L3.L1). The next flip-flop has J inputs from leads (L3 + L4, P3) and -C2(MUL + DIV), and J inputs from leads L4 and P5; providing an output L3(P4 + P5) the next flip-flop has a clock input from lead P4 so that it changes state on the trailing edge of pulse interval P4, a J input from lead L1, and a K input from lead L4; providing the output function (L2 + L3). The next flip-flop has a clock input from lead P5, a J input from lead L2, providing the output function (L1 + L2). The last flip-flop has a J input from lead P2 and a K input from lead P5; providing the output function (P3 + P4 + P5).

The length of instructions for the time required to process an instruction can vary with the type of instructions. Some instructions require only one cycle to process while others require two cycles. One instruction and traps require three cycles. Certain instructions although only two cycles circulate within a cycle as in shift instructions. Because of these differences controls are provided that allow the timing generator to go from cycle 1 to cycle 2 to cycle 3; or to set level 2, or to set level 3 or set level 4. Since some instructions require the contents of memory and cannot continue processing until the memory has retrieved the contents, or some instructions write into memory, and cannot continue until the write function is complete, a wait control is implemented to reset the flip-flop SYNC which in turn suspends the timing generator from proceeding until a feedback is received from memory. The feedback signals from the main memory via memory control include DAP7 and DLP7 designating respectively data available and data loaded at port 7; while the feedback signals from the register-sender subsystem are RSDAL and RSDLL for data available and data loaded respectively. The timing generator control logic is given by the following equations.

______________________________________ GOC1 =DAP7[IR23+PC-ASO(C2'+ZELO1')+XEC] +PREGOC1 GOC2 =C24INST.C1.L4.DAP7 +C1.L4.DAP7.C23INST.CCA'.SMP'.BSP'. (PRA+CPD.TSTCPD)' +(BSP+STC).MMDLL +C1.(CCA+SMP) +C1.(DIV+TRAP) +RSDAL.(PRA+CPD.TSTCPD) GOC3 =(DIV+ZELO1).C2.L4 RS DLL =RSSEL'.CRS1.RS1DLL +RSSEL.CRS2.RS2DLL +RSSEL'.CRS1'.RS1DLL +RSSEL.CRS2'.RS2DLL RS DAL =RSSEL'.CRS1.RS1DAL +RSSEL'.CRS1'.RS1DAL +RSSEL.CRS2.RS2DAL +RSSEL.CRS2'.RS2DAL SET L2 =C2.L3.MUL.SC3φ'(MODE.Qφ'+MODE'.Qφ)+ C2.L3.DIV.SC31'+L1(C2'+Qφ+MUL') SET L3 =C1.L1.MUL.Qφ'+L2(C1'+(SMP'+A23')(ENDCT'+ (CCA+SFTA+SFTL)') SET L4 =L3(C2'+SC3φ)(C2'+DIV1+SC31)+C1.L2 (SMP.A23+ENDCNT(CCA+SFTA+SFTL) START =TP POWER ON(RUN+INC+STEP+EXP B)+TP INC+ TP STEP+TP RUN STP CLK =P3(INC+TP INC)+P3.PC-ASO.L4.((TP POWER ON) (STEP+ADDRESS MATCH+EXPB)+HLT+TP STEP) WAIT STATE =C1.(STX+STA+STQ).MMDLL' +L3' +C1.PAR.RSDLL' +C2.MMDLL'(ADM+AOM+XAM+RPA+SOM) ______________________________________

BUS SOURCES

The data bus sources for the bit in position φ is shown in FIG. 5, while the sources for all bit positions are shown in FIG. 6. For each bit position of each source there is a two input AND gate with one input being the signal source for that bit position and the other input being an enabling control signal. For example AND gate 501 has a signal source lead DBφ and an enabling control signal lead LATCH DB. In each bit position the outputs of all these AND gates are combined through OR gate circuitry to the single bit position lead for the bus. FIG. 5 shows some of the sources combined by OR gate 530 to lead DBAφ and other sources combined through OR gate 531 to lead DBBφ. The outputs of these two OR gates and the other AND gates are combined by circuits represented by the symbol 540 to lead DBφ. Symbol 540 in actual practice of course comprises a plurality of gates combined to provide the OR function. To show signal sources received from other subsystems on different frames via cables, cable receivers such as 521 are shown in FIG. 5, with the subsystem designated by a mnemonic preceding a bracket. For example the signal on lead DRP7-0 is received from the computer memory control unit CMC. Signals received from the B units of the two register sender subsystems are received via cable receivers of unit CCP-B and supplied to both units CCP-A and CCP-B. Similarly the signals received from the A units of the register sender subsystems following the cable receivers of unit CCP-A are supplied to both the A and B units of the computer central processor CCP.

In FIG. 6 and in several of the other figures, rectangular blocks designated AND are used to represent a set of AND gates having signal sources from the respective bit positions and a common enabling signal; and blocks designated OR are used to represent the set of OR logic for the several bit positions combining signals from the AND blocks. The arrangement of the gates within these blocks is shown at the bottom of FIG. 11 with block 1150 representing an AND block and 1170 representing an OR block. In some cases the bit positions are subdivided into groups with different enabling signals; for example in the block 604 the control signal A(φ - 5) - DSO enables bit positions φ - 5, the control signal A(6 - 7) - DSO enables the gates for bit positions 6 and 7, etc. The signal source leads for block 604 are all from the A register; but in some cases the signal sources for different bit positions will be from different registers or other sources. For example in block 607 the control lead SC-DSO enables bit positions φ-13 to gate the signals from bit position φ-5 from the shift counter SC with ones into bit positions 6-13, while the signal on lead PC-DSO enables bit positions 12-21 to gate a 0 into bit position 14, the signals from the page register PR in the bit positions 15-20, and a 0 into bit position 21. In bit positions 22 and 23 both the enable signal and the source leads are 0's so that the output from these positions is always 0. The signal ONES is derived from an electronic ground via an inverter. For 0's electronic ground is used directly. The OR gating corresponding to block 540 in FIG. 5 is represented in FIG. 6 by OR blocks 637, 638 and 639 feeding OR block 640 for convenience. The OR function gating corresponding to gates 530 and 531 is shown in FIG. 7 by blocks 730 and 731 respectively. The block 730 has only 15 bit positions for sources from the index registers and program counter which likewise have only 15 bit positions. The other signals for leads DBA15-DBA23 are derived from OR gates having four inputs each from control pulse directive CPD sources except that the last input of the gate for bit position DBA23 is the signal C STROBE.

As shown by AND gate 501 which is a part of the AND logic 601, the Data Bus leads DB-φ to DB-23 are connected back as input data sources. These AND gates are enabled by the signal LATCH DB, so that any ones appearing on the data bus are latched as long as the signal LATCH DB is true. However, it is possible to enable another source to gate additional 1's onto the data bus.

The sources for the address bus AB are shown in FIG. 8 with the actual logic for bit φ, and in FIG. 9 for fifteen bit positions via the OR logic 940 plus two additional bit positions from the page register. Latching of the address bus is provided via AND logic 901 with bits ABφ to AB14 as sources enabled by the signal LATCH AB. This latter signal is provided by a latch which is shown along with its setting and resetting logic.

The program counter is used as a source when the enabling signal GPC-ASO is true, and the S register is used as a source when the enabling signal S-ASO is true.

For interrupts the AND logic 904 is enabled by signal IA-ASO. Four of the five octal digits for the address source are provided by hardwired inputs so that the address is 7371X, where the value of X is determined by the three inputs 1A0, 1A1 and 1A2 which are received from the computer line processor CLP. For traps the address is provided by AND logic 905 enabled by a signal TA-ASO to provide a wired address 737φX, where the value of X depends on signals TA0 and TA1 derived from the computer third party CPT.

The paging bits of the address are supplied via OR gates 906 and 907 for bit positions AB15 and AB16 respectively, with the logic providing inputs from the page register as shown.

REGISTERS OF THE COMPUTER CENTRAL PROCESSOR

The registers shown in the block diagram of FIG. 1 are shown in more detail in FIGS. 10-15.

The instruction register IR comprises 24 storage devices in the form of latches. Each of the latches comprises an integrated circuit chip comprising two four-input AND gates such as 1011 and 1012 feeding a NOR gate such as 1013. The output from gate 1013 via an inverter 1014 supplies the output signal IRφ, while the output from gate 1013 is the negative signal -IRφ. Both the true and inverted signals may be taken from each of the latches. The instruction register is loaded from the data bus bits DBφ-DB23. The load signal to the latches is supplied in inverted form shown as an input to the latches for positions IRφ-IR11 as -LOAD. The loading of these latches depends on a time delay achieved in the inverters such as 1010. For example when the signal LOAD becomes true (-LOAD false) then via inverter 1010 the upper input of AND gate 1012 is enabled and if the source signal DBφ is also true then the output of the latch becomes true. This output is fed back to the upper input of AND gate 1011. When LOAD goes false (-LOAD true) then gate 1011 is enabled to maintain the latch

TABLE A ____________________________________________________________ ______________ OP00 -- OP20 ADX OP40 ADD OP60 PRA 01 ADI 21 SBX 41 SUB 61 PAR 02 SBI 22 CAX 42 MUL 62 BSP 03 HWL 23 CSX 43 DIV 63 -- 04 HWS 24 IBP 44 AOM 64 LDQ 05 SEL 25 IBN 45 SOM 65 STQ 06 LSGA 26 STX 46 ADM 66 LPR 07 SSNT 27 -- 47 XEC 67 HLT 10 RTN 30 BPX 50 ANA 70 SMNT 11 BUN 31 BNX 51 ORA 71 SMNZ 12 SFTL 32 BZX 52 ERA 72 SANE 13 BZA 33 CCA 53 XAM 73 SANG 14 BNA 34 SFTA 54 LDA 74 LDC 15 BPA 35 BAO 55 STA 75 STC 16 BRR 36 RTR 56 CSA 76 SAMQ 17 CPD 37 MIS 57 RPA 77 SMNN ____________________________________________________________ ______________

set before the upper input of gate 1012 becomes false. The signal on lead -CLR is normally true, and when it goes false it clears all of the latches to zero. The LOAD IR logic is shown in simplified form within block 1000. During normal operation the AND gate 1001 is enabled in response to the condition C1.L1.P3, which normally is the necessary condition for loading all bit positions. The loading of bit positions IR12, IR13 and IR14 may be inhibited at gate 1002 by the signal EXT OP PROTECT, the loading of bit positions IR15-IR2φ may be inhibited at gate 1003 by the signal INOP, and the loading of bit positions IR21 and IR22 may be inhibited at gate 1004 by the signal INX. All bit positions may alternatively be loaded by the third party signal TP LOAD IR. FIG. 10 also shows the OP code decoder 1020 for the instruction set, and a control pulse directive decoder 1030. The control pulse directive decoder 1030 is enabled by the signal on lead C STROBE which is true in response to the condition CPD.L3. It decodes the value of the control pulse directive from the six bit positions IR9-IR14 which provide the output octal codes φφ to 77. These outputs are supplied to the data bus as shown in FIG. 7, and also to the various subsystems to which they apply.

The outputs of the OP Code decoder 1020 represent the decoding of the six instruction register bits IR2φ-IR15 along with the signal INHIBIT'. The six IR bits are expressed as two octal digits. For example ADM = OP46 = IR20.IR19'.IR18'. IR17.IR16.IR15'.INHIBIT. The full decoding is shown in Table A. Note that codes OPφφ, OP27 and OP63 are invalid codes which via an OR function gating provide the signal IOP.

The Y register shown at the top of FIG. 11 comprises 24 latches similar to those used in the instruction output from all of the odd positions is in true form while that from even positions is an inverted form. With this arrangement the carry is propogated through all of the bit positions via only the single integrated circuit chip for each position, thus minimizing the propogation time.

When the signal ARITH is true the output is the sum of the contents of the Y register and data bus. When the signal EXO is true the output is the exclusive OR function of the Y register and data bus. When the signal on lead AND is true the output is the AND function of the Y register and data bus. To provide the OR function the signals on leads AND and EXO are supplied simultaneously. To provide the subtract function with 2's complement arithmetic the signals on lead INVERT and the carry input on lead Cφ are provided. To simply invert a number in 2's complement form it is supplied into the Y register, with the data bus all zeros, and the signals INVERT and Cφ are provided.

The A register and Q register are shown in FIG. 13. These registers each comprise twenty-four JK flip-flops. These registers are loaded by supplying a load signal to the clock inputs and supplying the data to be loaded to the J inputs and inverted to the K inputs. The clock input for the Q register is LOAD Q, while for the A register the flip-flops are divided into four groups with separate load signals to the clock inputs as shown. Both registers may be set to all zeros by a signal on lead -CLR at zero level. Register A may be loaded from the arithmetic logic unit bits ADφ-AD23 with an enabling signal ADA, may be the sink for the data bus bits DB0-DB23 with the enabling signal A-DSK, may be loaded from its own output shifted one bit position to the right and register. This register is also loaded from the data bus bit positions DBφ-DB23 in response to an LOAD Y signal. The S register shown at the bottom of FIG. 11 also comprises twenty-four latches similar to those of the IR register, except that the AND gates have only two inputs. This register may be loaded from either the data bus or the arithmetic logic unit in response to a signal LOAD S. It is loaded from the data bus via AND logic 1150 when the signal on lead S-DSK is true indicating that the S register is the data sink. It is loaded from the arithmetic logic unit bits ADφ-AD23 via AND logic 1160 in response to an enabling signal on lead ADS, which is true whenever the signal on lead S-DSK is false. The bit positions 15-23 are inhibited when the signal on lead XH is true to prevent loading from bits AD15-AD23. The outputs from the AND logic 1150 and 1160 are passed through OR logic 1170 to the data inputs of the S register. The arrangement of the gates within the blocks 1150, 1160 and 1170 is shown here, whereas in other figures only the blocks are shown to represent the same form of logic.

The arithmetic logic unit ALU is shown in FIG. 12. This is a 24 bit parallel adder. The circuit for bit positions AD1 and AD2 is shown in detail. The data inputs to the register are from the Y register and the data bus, and the output on leads ADφ-AD23 is the result of the arithmetic operation. A feature of the adder is that the carry output from each bit position is from an integrated circuit chip which as shown for bit position AD1 comprises a two-input AND gates 1201, 1202 and 1203 feeding an NOR gate 1204. The chip actually contains four AND gates but one of them has its inputs connected to ground. The arrangement is such that the carry supplying the signal A23IN for the twenty-third bit with an enabling signal STR, and may be loaded from itself shifted one bit to the left and supplying the signal AφIN for bit position zero with an enabling signal STL. Similarly the Q register may act as a data sink for the data bus with an enabling signal Q-DSK, may be loaded from itself shifted one bit position right and a signal Q23IN in the twenty-third bit position with an enabling signal STR, and may be loaded from itself shifted one bit position left with a signal QφIN in bit position zero with an enabling signal STL. The flip-flop Qφ may also be set by a zero level signal on lead -Qφ(S).

The program counter PC and last program count register LPC are shown in FIG. 14. The program counter PC comprises fifteen JK flip-flops connected as a binary counter, advancing one count each time a trailing edge of a pulse appears on lead COUNT PC connected to the clock inputs. The counter may also be loaded from the data bus in response to a signal on lead LOAD PC, the loading being effective via the asynchronous inputs S and R. The counter may also be cleared by a zero level signal on lead -CLR to the second reset input of each flip-flop. The first seven flip-flops and the last one have been shown in order to illustrate the binary counting logic at the J and K inputs. The logic is arranged in groups of three flip-flops which with each having an AND gate supplying J and K inputs of all three, for example gate 1423 supplies J and K inputs of flip-flops PC3, PC4 and PC5 with the inputs of gate 1423 being from the preceding three flip-flops PC/, PC1 and PC2, and one input from the AND gate of the preceding three flip-flops. The second flip-flop of each group, for example flip-flop PC4 also has J and K inputs from the preceding flip-flop, namely, PC3, while the third flip-flop of each group such as PC5 has J and K inputs from both of the other flip-flops, namely PC3 and PC4. The output of gate 1423 is then supplied as an input to gate 1426 for the next group of three, etc. For the first group of three instead of an AND gate an inverter 1420 with input from ground is substituted.

The last program count register comprises fifteen latches of the type each comprising two NAND gates. AND gates are provided to load the output of the program counter PC into the last program count register LPC in response to a signal on lead LOAD LPC.

The three index registers X1, X2 and X3 shown in FIG. 15 each comprise fifteen latches similar to those used in the instruction register and Y register. Each of these registers may be loaded in response to each individual load command from the fifteen low order bits of the data bus.

The shift counter SC shown at the bottom of FIG. 15 is a six-bit counter with JK flip-flops generally similar to the program counter PC. The count is advanced once upon each occurrence of a trailing edge on lead COUNT SC. The counter may be loaded via AND logic from the inverted six low order bits of the data bus in response to the command LOAD SC. The output of the counter is decoded for certain values as shown, SC = 0 for the state in which all the flip-flops are set to zero, SC27, SC30 and SC31 for corresponding octal values, and ENDCT for the octal value 77.

CONTROL LOGIC FOR THE COMPUTER CENTRAL PROCESSOR

The control unit logic block CPC in FIG. 1 represents the logic for supplying the control signals for transferring data and address information among the registers and buses. The definitions of the various signals, and the Boolean equations follow.

________________________________________________________ __________________ Definitions ACKN ACKNOWLEDGED RECEIPT OF DATA FROM I/O ADA = OUTPUT OF ADDER TO RA ADD1 INDICATION THAT A CORRECTIVE ADDITION OF ONE MUST TACKED ON TO THE QUOTIENT ADZ = OUTPUT OF ADDER EQUALS ALL ZEROS. AND = LOGICAL AND A-DSO = REGISTER "A" AS A DATA SOURCE A23IN = DATA INTO BIT 23 OF REG.A BCHI = A STORED BRANCH INDICATOR BDIS PRCF BUTTON DISPLAY ENABLE C STROBE SIGNAL USED TO STROBE DATA BUS DURING CPD CAR (S) = CARRY,OUT OF BIT 23 OF ADDER,STORED CCX-DSO = CHANNEL MULTIPLEX AS A DATA SOURCE CLR = CLEARS TO AN INITIAL STATE THE FOLLOWING: RA,RO,Y,IR,X1,X2,X3,PC.SC,TP TRAP, START CLK,CLK,SYNC,MMREAD,MMWRITE LOCKOUT, CARRY,OVF,EVEN PARITY TEST STORAGE,LATCH AB, TST CPD,WMPB,PCINH,RSSEL,TRAP DISABLE, XH,LOAD LPC INHIBIT,BRH,INST,SW TO STDBY RT CLK,QZ,MADD,ADDI,INX,INTIN,INOP,SREJECT, 6 Cφ = CARRY INTO BIT 0 OF ADDER COUNT SC COUNT SHIFT COUNTER CRS1 SELECT REGISTER SENDER 1 UNIT A WHEN SET, AND RS 1 UNIT 1B WHEN RESET C13 INST = INDICATES AN INSTRUCTION THAT ACCESS MEMORY DURING CYCLE 1 LEVEL 3 C23 INST = INDICATES AN INSTRUCTION THAT ACCESS MEMORY DURING CYCLE 2 LEVEL 3 DEPE = DATA EVEN PARITY ERROR DIVZ INDICATES A DIVISION BY ZERO DSTROBE DATA STOBE TO CCX DS-DSO = PRCF DATA SWITCH REGISTER AS A DATA SOURCE ENWD = ENABLE WATCHDOG TIMER EXO = EXCLUSIVE"OR" IEPE = INSTRUCTION EVEN PARITY ERROR INHIBIT = INHIBIT OF OP CODE INVERT = INVERTS THE OUTPUT OF Y REG. 1'S COMPL. INOP INHIBITS LOADING OF OPERATION FIELD IN IR INVOP ERROR INDICATING AN INVALID OP CODE INX INDICATION OF A NON INDEXABLE INSTRUCTION IRL-DSO = INSTRUCTION REG BITS(12-23) AS A DATA SOURCE IS SYNC SYNC PULSE SENT TO THE CLP LATCH AB = LATCH ADDRESS BUS LBF LOAD BRANCH FIELD OF PAGE REGISTER LDF LOAD DATA FIELD OF PAGE REGISTER LOAD AL LOAD RA BITS 12-23 LOAD AR LOAD RA BITS 0-11 LOAD LPC LOAD LAST PROGRAM COUNT REGISTER LOAD SC = LOAD SHIFT COUNTER LPC-DSO = LAST PROGRAM COUNT AS DATA SOURCE MADD INDICATES THAT AN ADDITION PROCESS DURING MULTIPLICATION MODE INDICATES SUCCESSIONS OF '1'S"OR"0"S"IN MUL OFV = OVERFLOW PBRM PROTECT BIT OF REFERENCED MEMORY PCINH INHIBITS COUNTING OF PROGRAM COUNTER PC = PROGRAM COUNTER PC-DSO = PROGRAM COUNTER AS A DATA SOURCE PEP7 = PORT 7 ERROR THAT INDICATES AN ERROR HAS OCCURRED IN THE COMPUTER MEMORY CONTROL CIRCUIT RELATIVE TO PORT 7 WHICH IS ASSIGNED TO THE CENTRAL PROCESSOR. THE ERROR IS CAUSED WHEN THE CCP ADDRESSES A LOCATION OUTSIDE THE RANGE OF MEMORY, OR WHEN THE CCP ATTEMPS TO WRITE INTO READ ONLY MEMORY QOIN = DATA INTO BIT O OF RQ Q23IN = DATA INPUT TO REG.Q BIT 23 DURING A SHIFT REI = RESET ERROR INDICATORS RS1B-DSO = REGISTER SENDER 1 UNIT B AS DATA SOURCE RS1A-DSO = REGISTER SENDER 1 UNIT A AS DATA SOURCE RS2A-DSO = REGISTER SENDER 2 UNIT A AS DATA SOURCE RSSEL SELECTS REGISTER SENDER 2 WHEN SET AND REGISTER SENDER 1 WHEN RESET AS A SINK RST MEM REQ RESETS A MEMORY REQUEST FROM THIRD PARTY RWD = RESET WATCHDOG TIMER SC(R) = RESET SHIFT COUNTER SC-DSO = SHIFT COUNTER AS A DATA SOURCE SET L2 SET LEVEL 2 SG-DSO = SENSE GROUP AS A DATA SOURCE SKIP ON SANG = A LESS THAN OR EQUAL TO EA. SANG SMP = SHIFT AND MARK POSITION INSTRUCTION SREJECT = STORED REJECT INDICATING A REJECTION OF AN ARITHMETIC PROCESS DURING DIV. START START THE TIMING GENERATOR STP CLK STOP THE TIMING GENERATOR STR = SHIFT RIGHT GATING SW TO STDBY RT = SWITCH TO STANDBY REAL TIME CLOCK S(0-14)-DSO = REGISTER S BITS 0 THRU 14 AS A DATA SOURCE TID TRANSFER INSTRUCTION FIELD TO DATA FIELD TOVF = TEMPORARY OVERFLOW OF PARTIAL PRODUCTS DURING MULTIPLICATION. TP DSTROBE DATA STROBE TO THIRD PARTY TST CPD A MAINTENANCE SIGNAL THAT ALLOWS A CHECK FOR A LATENT FAULT ON THE INPUT TO THE CPD DECODE CIRCUIT WMPB STORED SIGNAL TO WRITE MEMORY PROTECT BIT XHQ INDICATION THAT AN INDEX IS BEING PROCESSED ZELO1 = TP TRAP + ERR TRAP ____________________________________________________________ ______________ ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6## ##SPC7## ##SPC8## ##SPC9## ##SPC10## ##SPC11## ##SPC12##

ADM (ADD TO MEMORY) OPERATION

To illustrate latching of the buses, the operation for an ADM instruction will be described. The timing chart is FIG. 16. An octal representation is used in the following description for all data and addresses in the registers and on the buses.

Assume initially that toward the end of the preceding instruction PC-ASO and therefore GPC-ASO become true along with MM read. The program counter PC (FIG. 14) contains some address, for example (13257), which is gated onto the address bus AB (FIG. 9).

During the last cycle, which may be any one of C1, C2 or C3 depending on the instruction, the signal GO from gate 422 becomes false. Therefore at P4, L4, input K of flip-flop SYNC becomes true. The next clock pulse advances the pulse counter to P5 and also resets SYNC. This blocks further pulses from lead TCP and thus prevents the timing generator from advancing further.

In the meantime the memory control circuit causes the data word to be read from the main memory and placed in a data register having outputs on the cable leads DRP7-φ to 23. A signal DAP7 becomes true indicating data available at port 7.

The signal GOC1 becomes true in response to the condition (DAP7.PC - ASO.ZELO1'). The element ZELO1 relates to a trap condition and is normally false. GOC1 via gate 422 along with CLK makes the J input of SYNC true so that the next clock pulse sets it. When SYNC-B from the duplicate processor is also true, gate 414 is enabled to supply pulses to lead TCP. The next clock pulse then sets the timing to C1.L1.P1. The signal PC-ASO becomes false as the timing is set to L1.

To use the memory data register as a data source, the signal MDR-DSO becomes true in response to the signal condition [C1.L1.P5'(EXPB+XH)'CLK]. The data from leads DRP7-φ to 23 is then gated onto the data bus (FIG. 6) during pulses P1-P4 of cycle C1 level L1.

During the second pulse MM READ is reset in response to DAP7.L1.P2.CLK.

During the third pulse the condition (C1.L1.P3) is used to LOAD IR, LOAD Y and COUNT PC. In the equation for COUNT PC, EXPB and PCINH will usually be false. (The signal PCINH may be true in certain instances in which the program counter has already been advanced with indirect addressing indexing, an interrupt or a trap and should not be advanced again.)

The situation now is that the program counter has advanced to (1326φ), and the contents of the word at address (13257) have been placed via the data bus into registers IR and Y. Assume this word to be (14621372). The (1) corresponding to bits 23, 22, 21 indicates indexing with register X1, the (46) is the OP code for ADM and (21372) is the operand address.

INDEX is true in response to (IR21.IR19'). During the fifth pulse MDR-DSO becomes false, and index register X1 becomes the data bus, source by X1 - DSO = (X1.C1.L1.P5.INDEX), where X1 = (IR22'.IR21). The signal ADS is normally true during cycle C1 unless RTR is true.

As shown in FIG. 11, the input for register S is normally from the adder of FIG. 12, via AND logic 1160 enabled by signal ADS which is normally true except when S-DSK is true. The signal LOAD S is true with (ADX IN1.C1.L2.P5) where ADX INI is true with INDEX true. LOAD S causes register S to be loaded with the output of the adder, which is the sum of the operand address instruction which has been loaded into register Y and the contents of register X1 which appears on the data bus. Assuming for example a value (φφφ12) from the index register, the address in register S is now (21404).

On the first pulse of the thid leve., MMREAD latch is set on (C1.L3.MRI.PRA'); where MRI is true with bit IR20 true, this bit being true for the ADM code OP46. The signal S-ASO is also true with (CLK.MMDLL'.C1.L3.MRI). The main memory is now accessed via memory control CMC to read the data from the word at address (21404). In the meantime the processor continues other operations.

During level L4 the signal A-DSO becomes true with C1.L4.ADM. During pulse P3 the signal LOAD Y is true with (ADM.C1.L4.P3), and LATCH AB is also set on the same condition. Therefore data from register A via the data bus is placed in register Y, and the address from register S is latched on the address bus. Assume data from A into Y is (φφφφφ132).

It is now necessary to wait for the data to be available from the main memory, indicated by the signal DAP7. ADM is a C24 instruction so GOC2 becomes true on the condition C1.L4.C24INST.DAP7. This initiates the cycle C2.

The signal MDR-DSO becomes true on C2.L1.P5'(C2,MDR-DSO Inhibit)'CLK, which gates the data from the memory onto the data bus. Assume data is (23512562).

The latch MMREAD is reset on (DAP7.L1.C2.CLK).

The signal LATCH DB becomes true on (ADM.C2[L1(P3 + P4 + P5) + L2]) so that the data from memory is latched on the data bus during the last three pulses of level L1 and all of level L2.

During pulse P4 of level L2, LOAD S becomes true on ADM.C2.L2.P4. therefore the sum from the adder is placed in register S. This sum is (φφφφφ132) + (23512562) = (23512724).

During level L3 the signal S-DSO is true on (C2.L3.ADM); and MMWRITE is true on (C2.L3.ADM.MMDLL'.LATCH AB). This signal along with LATCH AB remains true during all of level L3. Therefore a command is given to memory control to write the data from register S at the address of the data word which is latched on the address bus.

The timing stops at C2.L3.P5 while awaiting a signal from the memory control that the data is loaded in memory. This is accomplished by the signal WAIT STATE on the condition (C2.MMDLL'.ADM).

The latch MMDLL is set in response to the signal DLP7 from memory control indicating data loaded at port 7. LATCH AB is reset in response to MMDLL. With MMDLL true, WAIT STATE becomes false and makes GO from gate 422 true. Flip-flop SYNC sets on the next clock pulse, and along with SYNC-B enables gate 414 to provide clock pulses on lead TCP and advance the timing to level L4. MMWRITE becomes false and the latch MMDLL is reset (DLP7 becomes false to remove the set signal). The signal S-DSO becomes false when the level goes to L4.

The last level of the cycle is used to initiate reading the next instruction, whose address is in the program counter, now at 13260. MMREAD sets and PC-ASO becomes true on (C2.L4.C24INST), and GPC-ASO then becomes true. The timing stops at C2.L4.P5 while waiting for the data available signal DAP7.

OTHER INSTRUCTIONS WITH BUS LATCHING

As seen in the equations for LATCH AB(S) and LATCH DB, the instructions AOM for add one to memory and SOM for subtract one from memory, use latching of both the address bus and the data bus; the instructions XAM for exchange contents of register A and memory, and RPA for replace address, use address bus latching; and the instructions SANG for skip an instruction if contents of register A is not greater than memory contents at the effective address, SANE for skip if contents of register A not equal to memory contents, and PRA for place contents of register-sender memory into register A, use data bus latching.

The operation for instructions AOM and SOM is very similar to ADM. Both omit A-DSO during C1.L4 so that the data bus has all zeros when register Y is loaded during C1.L4.P3. For AOM the carry into bit φ signal Cφ is true on (C2.AOM), while for SOM a negative one is effectively added by INVERT = C2.SOM.

The instructions XAM and RPA use latching of the address bus to keep the address available while using the S register for other purposes.

The instructions SANG and SANE use latching of the data bus to retain information read from memory to do arithmetic operations (subtract contents of register A from the data read from memory) during cycle C2, levels L1 and L2.

COMPUTER USER MANUAL

SECTION 1.0 Computer Central Processor

1.1 Introduction to Computer Organization

An understanding of the Computer Central Processor will aid the user to manipulate, maintain and to analyze the system.

1.1.1 Word Formats

The memory data word is represented in octal format as follows: ##SPC13##

e.g., a number represented as octal 24176653 has a corresponding binary representation of:

010100001111110110101011

The instruction word format for the central processor is: ##SPC14##

Bits φ - 14 contain the address for memory reference instruction or micro-instructions for non-memory reference operations.

Bits 15 - 20 contain the code representing the operation to be performed.

Bits 21 & 22 are coded to represent any of three index registers to be used in address modification.

______________________________________ Bits Specify ______________________________________ 22 21 0 0 No Index 0 1 Index 1 1 0 Index 2 1 1 Index 3 ______________________________________

Bit 23 is the indirect address bit.

(Bits 15 - 23 are referred to as the instruction field.)

The single precixion fixed point data word format (24 bits) is represented as an 8 octal digit number with the highest order bit denoting a positive or negative quantity: ##SPC15##

The word format for a double precision data word (48 bits) is represented by two separate single precision words with the highest order bit in the word of most significance denoting a positive or negative quantity. ##SPC16##

Fixed point numbers are stored in memory in two's (radix) complement form. Thus, magnitudes of negative numbers are not directly available but must be recomplemented. The Clear A and Subtract instruction has been provided to facilitate this operation.

1.1.2 Main Memory (CMM)

The Main memory is a high speed random access store capable of a complete read or write cycle time 1 microsecond and a read-modify-write cycle time of 1.6 microseconds. (Slower memories may be substituted with the only penalty being a derating in processing speeds and Drum Transfer rates). Main Memory is expandable in 4096, 8192, 16384 or 32768 word modules to a maximum of 131,072 words or four modules, whichever occurs first.

Each memory module contains its own address register, data register, and read-write control circuitry. A set of margin switches is provided with each memory module that can be manually changed to improve fault localization resolution and run preventive maintenance routines. An amber lamp is provided on the memory module front panel to indicate that any one or more of these switches is off-normal.

Each word in Main Memory contains 26 bits: 24 bits are used for storing data, 1 bit is used for storing the parity of the complete word, and 1 bit is used for storing the "protect" status of the word.

A 17 bit address bus allows any word in main memory to be directly addressable. Each word can be read out of or "written" into, or both. However a memory protect system is utilized to protect specified locations in core from being altered. A hard wired section of memory of 512 or 1024 words, within the first 1024 locations, cannot be written unless the memory protect system is inactivated. The memory protect system can only be inactivated by depressing the memory protect inhibit switch, on the Maintenance control center panel. With the memory protect system active, other locations in memory are protected by the setting of a read only memory storage element in the CMC and that particular word having bit 25 set. This read only memory storage element is programmed controlled by a CPD instruction.

A parity check feature is provided for all memory transfer operations (both reading and writing). The parity generation and checking is provided in the CMC and extends over the complete memory word, including the memory protect bit, for additional security.

1.1.3 Addressing Alternates

For most instructions, which reference memory from the operand, the following addressing modes are available.

Paging

the core memory of the Central Processor is organized into pages. The maximum number of pages is four, with the maximum number of location or addresses assigned to a page being 32,768. This totals a maximum of 131,072 words of memory.

Addressing a page is via the hardware page register. Bits 15 and 16 (the 16th and 17th bits of the address bus) are taken from the instruction field or the data field of the Page Register whenever a memory reference occurs. The Page Register can be altered via programmed instructions (refer to section 1.3.3 Paging).

Direct addressing

the operand or address field of an instruction specifies an address within a page on a memory reference instruction. A maximum of 32,768 words of core within any one of four pages is directly addressable.

Indexing

the contents of any one of the three 15 bit index registers is added to the contents of the instruction address field to form a new operand address. Indexing does not carry over into a new page, rather a wrap around effect will occur. Indexing does not affect the page register.

Indirect addressing

the address field of an instruction, after modification by indexing if required, specifies a memory location which will contain a new address for the operand. The indirect addressing is multilevel with indexing allowed at each level.

The indexing operations always precede indirect referencing operations. Indirect references proceed until the indirect address bit is false. Instructions which are used to specify index operations are themselves not indexable.

1.1.4 ARITHMETIC

Parallel, binary, fixed point arithmetic is provided in the No. 1 EAX computer. Single precision numbers are stored in memory as 23 bit integers (i.e., binary point at extreme right) with the highest order (leftmost) 24th Bit considered as a sign.

Negative numbers are held in memory in two's complement form and are operated on in the arithmetic unit in a two's complement number system.

Provisions for double length products and dividend are made by using two registers in the multiply and divide operations. The two registers may be shifted logically or arithmetically and may be logically rotated (circular shift).

1.1.5 INPUT/OUTPUT

The EAX processor input/output system is made up of two distinct sections; the Computer Channel Multiplex and Channel Buffers.

The Channel Multiplex (CCX) provides a unique communication path between the Central Processor and the Channel Buffer. The CCX can accommodate a maximum of 16 Channel Buffers.

Standard Channel Buffers provided with a EAX Office Switching Unit are: (1) Computer Channel Device Buffer. This buffer provides an interface to the peripheral adapters which provide control features for the operation of the Teletype Model 35ASR, Teletype Model 35KSR, Paper Tape Punch and Paper Tape Reader. (2) Computer Communications Register. This shift register provides the serial communication link between the Central Processor and the Originating or Terminating Markers. (3) Maintenance Device Buffer. This buffer provides a store and forward interface between the Central Processor and the Maintenance and Control Center. (4) Automatic Toll Ticketer. A channel buffer provides the interface between the central Processor and the Automatic Toll Ticketer.

1.1.6 PRIORITY INTERRUPT

Since the operation of the No. 1 EAX system is dictated by events occurring external to the Central Processor, provision is made to alert the CP to these external occurrences; this provision is called the Priority Interrupt system.

The interrupt system is a true multi-level system, 8 levels of interrupt are available, and the program of highest active priority is always being processed.

The eight general categories of interrupts and their priorities are listed below.

1. Manual Requests and Power Failures

2. Major Alarm Errors

3. Real Time Clock

4. Communication Register and Drum Control Unit Ready Interrupts

5. Register-Sender Requests for Translation

6. Minor Alarm Errors

7. Input/Output and Originating Marker Interrupts

8. Clock Errors and Register-Sender Minor Errors.

Additional program control is provided by separate instructions which either DISABLE the interrupt system or ENABLE the interrupt system.

1.1.7 TRAPS

Failures that could disrupt the No. 1 EAX system require immediate attention. The priority interrupt system has a time lag of at least one cycle time before recognition for service can be processed, also a program disable feature can delay recognition for any length of time. Because of these features, a trap system is used to accommodate failure recognition. There are two trap levels, and both have a higher priority than the interrupt system but only at the time of failure. Once the trap has been recognized, and the BSP instruction at the trap address has been processed, an interrupt can occur. The recognition of the interrupt can be delayed, however, by processing a disable interrupt (DSI) instruction.

Trap level 1 has a higher priority than trap level 2. Trap level 1 is called the third party trap. It is triggered whenever the duplicated central processors, while running in sync, do not agree with each other. Recognition of this trap is immediate. However, the instruction in process is allowed to be completed before a force is made to the trap location. (Refer to section 1.6 for further detail).

Trap level 2 is called the computer error trap. It is triggered when an error, internal to a central processor or its associated computer memory control, occurs. Recognition of this trap is immediate, and the instruction in process is aborted. (Refer to section 1.6 for further detail).

1.1.8 COMPUTER REGISTERS

In addition to the registers shown in FIG. 3A, the computer operates in conjunction with Memory Registers. Each memory module contains its own data, or information register and its own address register. Data registers are 26 bits (one parity and one protect bit). Address registers may be 12 to 14 bits for module sizes of 4096 to 16,384 respectively. These registers are time multiplexed as required between the central processor and a direct access I/O device (optional). The memory registers are not accessible for program control. 1.1.8.8 Register "PR" is a 6 bit register used to specify bits 15 and 16 of the address bus. The 6 bits are assigned to a data field (2 bits); a branch field (2 bits); and an instruction field (2 bits). Program access to this register is via the instruction set.

SECTION 1.2 Central Processor Instruction Set

1.2.1 Introduction

This section contains the description of the Central Processor Circuit instructions. The descriptions are separated into functional groupings.

All instruction execution times are expressed in terms of memory cycles unless otherwise noted. The timing indicated includes instruction access time and address modification time. Where indirect addressing is specified, one additional memory cycle is required.

Indexing and indirect addressing apply to every instruction unless otherwise noted.

A timing cycle is equal to 2 μsec plus time for memory reference in some instructions. Refer to section 8.12.

The term "effective address," EA, is used to describe the final operand field of the instruction after all indirect references and modification. For memory reference instructions, the effective address denotes the location of the memory cell containing the actual operand. For non-memory reference instructions, the effective address is used literally as the operand.

(EA) = Contents of Main Memory at the Effective Address within a memory page.

(A) = Contents of Register A.

Ea = effective Address -- Indicates Direct or Literal Operation Using Modified Address Field.

: = Colon Defined as Notation "if: then."

(nn) = Octal representation of Op code.

1.2.2 Arithmetic Group

Add (40) add Memory to A (A) _{0 -23} + (EA) _{0 -23} ➝(A) _{0 -23}

the contents of the memory location at the effective address are added to the contents of Register A. The sum replaces the contents of the A register. If an overflow occurs, the overflow indication will be set. A carry out of bit position 23 will be recorded by setting the carry indicator.

Register affected: A

Timing: 2 cycles

Sub (41) subract Memory From A (A) _{0 -23} -(EA) _{0 -23} ➝(A) _{0 -23}

the contents of the memory location at the effective address are subtracted from the contents of Register A. The difference replaces the contents of the A register. If an overflow occurs, the overflow indicator will be set. A carry out of bit position 23 will be recorded by setting the carry indicator.

Register affected: A

Timing: 2 cycles

Mul (42) multiply Memory by Register Q (EA) _{0 -23} × (Q) _{0 -23} ➝(AQ) _{0 -47}

register A is reset, the contents of the memory location at the effective address are multiplied by the contents of register Q. The product will replace the contents of the double precision registers A-Q, bits 0-47.

Register affected: A and Q

Timing: 7.5 cycles min., 10.5 cycles max. ##SPC17##

The contents of the double precision registers A and Q are divided by the contents of memory at the effective address. The quotient will replace the contents of Register A. The remainder will replace the contents of register Q and will be signed as dividend. If a division overflow occurs, the overflow indicator will be set. Division by zero will result in a computer error TRAP (LEVEL 2).

Registers affected: A and Q

Timing: 15 cycles

Adi (φ1) add Immediate (A) _{0 -23} + EA _{0 -14} ➝(A) _{0 -23}

the effective address is added directly to the contents of register A. If indirect addressing is specified, only bits φ thru 14 at the indirect address are added to register A. A carry out of bit position 14 will propagate. If an overflow occurs, the overflow indicator will be set. A carry out of bit position 23 will be recorded by setting the carry indicator.

Register affected: A

Timing: 1 cycle; 2 cycles if Indexed

Sbi (φ2) subract Immediate (A) _{0 -23} - EA _{0 -14} ➝(A) _{0 -23}

the effective address is subtracted directly from the contents of register A. If indirect addressing is specified, bits φ thru 14 at the indirect address take part in the subtraction process. Borrows from bit positions of higher order than 14 will propagate. If an overflow occurs, the overflow indicator will be set. A carry out of bit position 23 will be recorded by setting the carry indicator.

Register affected: A

Timing: 1 cycle; 2 cycles if Indexed

Aom (44) add One to Memory (EA) _{0 -23} + 1➝(EA) _{0 -23}

the contents of the memory at the effective address are incremented and stored back in memory at the same address. Overflow and carry indicators are not affected.

Register affected: None

Timing: 2 cycles

Som (45) subtract One from Memory (EA) _{0 -23} - 1➝(EA) _{0 -23}

the contents of the memory at the effective address are decremented, and stored back in memory at the same address. Overflow and carry indicators are not affected.

Register affected: None

Timing: 2 cycles

Adm (46) add A Register to Memory (A) _{0 -23} + (EA) _{0 -23} ➝(EA) _{0 -23}

the contents of the A register are added to the contents of the memory at the effective address. The result is stored back in memory at the same address. Overflow and carry indicators are not affected.

Registers Affected: None

Timing: 2 cycles

1.2.3 Indexing Operations

(Multilevel Indirect Addressing is allowed but the loading of the index bits of the tag field is suppressed)

Adx (2φ) add to Index (XR) _{0 -14} + EA _{0 -14} ➝(XR) _{0 -14}

(not Indexable). Add the effective address directly to the specified index register. If no index register is specified, ADX will be treated as a no-op. Overflow not affected.

Register affected: XR _n

Timing: 1 cycle

Sbx (21) subtract from Index (XR) _{0 -14} - EA _{0 -14} ➝(XR) _{0 -14}

(not Indexable). Subtract the effective address directly from the index register specified in the tag field of the instruction. If no index register is specified, SBX will be treated as a no-op. Overflow is not affected.

Registers affected: XR _n

Timing: 1 cycle

Cax (22) clear and Add Index EA _{0 -14} ➝(XR) _{0 -14}

(not Indexable). Load the effective address bits 0 thru 14, directly into the specified index register. If no index register is specified, the CAX will be treated as a no-op.

Register affected: XR _n

Timing: 1 cycle

Csx (23) clear and Subtract Index 2 ¹⁵ - EA _{0 -14} ➝(XR) _{0 -14}

(not Indexable). The effective address is loaded in two's complement form into the specified index register. If indirect addressing is specified, the effective address portion of the memory word at the indirect address is loaded in two's complement form to the specified index register. If no index register is specified, the CSX will be treated as a no-op.

Register affected: XR _n

Timing: 1 cycle

STX (26) Store Index (XR) _{0 -14} ➝(EA) _{0 -14} 0 ➝(EA) _{15 -23}

(Not Indexable). Store the contents of the specified index register in the memory location at the effective address.

Register affected: None

Timing: 1 cycle

IBP (24) Increment Branch Positive (XR) _{0 -14} +1➝(XR) _{0 -14} (XR) ₁₄ =0:EA _{0 -14} ➝(PC) _{0 -} 14

(Not Indexable). The contents of the specified index register are incremented. If bit 14 of that index register is zero, a branch to the effective address will be executed.

Register affected: XR _n :PC if Branch Occurs

Timing: 1 cycle

IBN (25) Increment Branch Negative (XR) _{0 -14} +1➝(XR) _{0 -14} (XR) ₁₄ =1:EA _{0 -14} ➝(PC) _{0 -} 14

(Not Indexable). The contents of the specified index register are incremented. If bit 14 of that index register is not zero, a branch to the effective address will be executed.

Register affected: XR _n ; PC if Branch Occurs

Timing: 1 cycle

Bpx (3φ) branch Positive Index (XR) ₁₄ = 0:EA _{0 -14} ➝(PC) _{0 -14}

(Not Indexable). A branch to the effective address will be executed if bit 14 of the specified index register is zero.

Register affected: PC if Branch Occurs

Timing: 1 cycle

Bnx (31) branch Negative Index (XR) ₁₄ = 1:EA _{0 -14} ➝(PC) _{0 -14}

(not Indexable). A branch to the effective address will be executed if bit 14 of the specified index register is not zero. If no index register is specified, or if the test fails, the BNX will be treated as a no-op.

Register affected: PC if Branch Occurs

Timing: 1 cycle

Bzx (32) branch Zero Index (XR) _{0 -14} = O:EA _{0 -14} ➝(PC) _{0 -14}

(not Indexable). A branch to the effective address will be executed if the contents of the specified index register are equal to zero.

Register affected: PC if Branch Occurs

Timing: 1 cycle

1.2.4 Load and Store Group

Csa (56) clear and Subtract A 2 ²⁴ - (EA) _{0 -23} ➝(A) _{0 -23}

the contents of the memory at the effective address are loaded in two's complement form into the A register. Overflow and carry indicator are not reset.

Register affected: A

Timing: 2 cycles

RPA (57) Replace Address (EA) _{15 -23} ➝ (EA) _{15 -23} (A) _{0 -14} ➝ (EA) _{0 -14}

The address portion of register A (bits 0 thru 14) replaces the address portion of the memory word at the effective address. Bits 15 thru 23 of the memory word at the effective address are not affected.

Register affected: None

Timing: 2 cycles

Lda (54) load A (EA) _{0 -23} ➝(A) _{0 -23}

the contents of memory at the effective address are loaded into the A register. The overflow and carry indicators are not reset.

Register affected: A

Timing: 2 cycles

Sta (55) store A (A) _{0 -23} ➝(EA) _{0 -23}

the contents of register A are stored in memory at the effective address.

Register affected: None

Timing: 1 cycle

Ldq (64) load Q (EA) _{0 -23} ➝(Q) _{0 -23}

interrupt ignored during instruction. The contents of the memory at the effective address are loaded into the Q register.

Register affected: Q

Timing: 2 cycles

Stq (65) store Q (Q) _{0 -23} ➝(EA) _{0 -23}

the contents of the Q register are stored in memory at the effective address.

Register affected: None

Timing: 1 cycle

Pra (60) place RS Memory into "A" Register

(Register Sender (EA)) _{0 -23} ➝(A) _{0 -23}

The contents of the register Sender Memory at the effective address are loaded into the A register of the CP. The overflow and carry indicators are not reset.

Register affected: A

Timing: 2 cycles

Par(61) place "A" Register into RS Memory

(A) _{0 -23} ➝(Register Sender (EA)) _{0 -23}

The contents of register A are stored in the Register Sender Memory at the effective address.

Register affected: None

Timing: 1 cycle

Lpr (66) load Page Register

Interrupts Ignored During Instruction

This Op-Code with its extended field allows the loading of the data field and branch field of the page register. This instruction is indexable. A zero extended OP code will be treated as a no-op.

Lpd (661) load Data Field EA ₃ ,4 ➝(PR) ₄ ,5

(not Indexable)

The effective address bits 3 and 4 are loaded directly and respectively into bits 4 and 5 of the Page Register.

(DATA FIELD).

Register affected: Page Register

Timing: 1 cycle

Lpb (662) load Branch Field EA ₀ ,1 ➝(PR) ₂ ,3

(not Indexable)

The effective address bits 0 and 1 are loaded directly and respectively into bits 2 and 3 of the Page Register.

(BRANCH FIELD).

Register affected: Page Register

Timing: 1 cycle

Lpdb (663) load Data and Branch Fields

(Not Indexable) EA ₃ ,4 & 0,1 ➝(PR) ₄ ,5 & 2,3

the effective address bits 3,4,0 and 1 are loaded directly and respectively into the Page Register bits 4,5 (DATA FIELD) and 0,1 (BRANCH FIELD).

Register affected: Page Register

Timing: 1 cycle

Tid (664) transfer Instruction Field to Data Field

(Not Indexable) (PR) ₀ ,1 ➝(PR) ₄ ,5

this instruction will allow data storage reference within the memory page of the running program.

Register Affected: Page Register

Timing: 1 cycle

Ldc (74) load Output Channel (EA) _{0 -23} ➝(OC) _{0 -23}

the contents of the memory at the effective address are loaded on the output channel. A separate sampling level is extended to external devices to indicate when data is stable.

Register affected: None

Timing: 2 cycles

Stc (75) store Input Channel (IC) _{0 -23} ➝(EA) _{0 -23}

the contents of the input channel are stored in memory at the effective address. A separate sampling level is extended to the external devices to acknowledge storage.

Register affected: None

Timing: 2 cycles

1.2.5 Miscellaneous Control Group (37) (Non-Indexable) DSI Disable Interrupt (SET INIT) (3700001)

Interrupts are accepted into the WAIT STATE. Interrupts will not be scanned and therefore not acknowledged by the Central Processor, while in this state.

Register affected: None

Timing: 1 cycle

ENI Enable Interrupt (RESET INIT) (3700002)

All interrupts are acepted into a WAIT STATE and interrupt break will be acknowledged during the next sequential instruction providing it allows interrupt recognition. Thus this instruction resets the DSI storage and will allow the interrupt system access at the end of next processed instruction if that instruction allows it.

Registers affected: None

Timing: 1 cycle

Ecr enable CPD Routine (Refer to Section 8.5 Maintenance)

(3700004)

This instruction sets a storage element, the output of which will allow loading of the data bus into the "A" register of the Central Processor during level 3 of a CPD instruction. The format of the "A" register after loading is as follows: ##SPC18##

Bit 15 = cpd00 + cpd11 + cpd22 + cpd33

bit 16 = cpd01 + cpd12 + cpd23 + cpd34

bit 17 = cpd02 + cpd13 + cpd24 + cpd35

bit 18 = cpd03 + cpd14 + cpd25 + cpd36

bit 19 = cpd04 + cpd15 + cpd26 + cpd37

bit 20 = cpd05 + cpd16 + cpd27 + cpd30

bit 21 = cpd06 + cpd17 + cpd20 + cpd31

bit 22 = cpd07 + cpd10 + cpd21 + cpd32

register affected: RA

Timing: 1 cycle

Dcr disable CPD Routine

(3700010)

This instruction resets the storage element set by ECR. Register affected: None

Timing: 1 cycle

Rei reset Error Indicators

(3700020)

All internal Central Processing Unit stored error indicators will be cleared. These include: Memory Even Parity Error, Invalid OP Error, Division by Zero Error, Error Trap and

Cmc errors.

Register affected: None

Timing: 1 cycle

Mps memory Protect Set

(3700040)

The WMPB indicator is set. This becomes bit 25 of the data bus.

Register affected: None

Timing: 1 cycle

Mpr memory Protect Reset

(3700100)

The WMPB indicator is reset.

Register affected: None

Timing: 1 cycle

Bps set Bad Parity

(3700200)

This instruction generates bad parity to main memory in the following manner.

Whenever this storage element is set by the above execution, the succeeding memory reference instructions will generate bad parity. The Store Register A (STA) instruction or Place A in Register-Sender (PAR) instruction or character copy out (CCO) instruction or load channel (LDC) will generate bad data parity to either Main memory (STA) or Register-Sender memory (PAR) or to the channel multiplexor (CCO or LDC). Any other memory reference instruction will generate bad address parity. PRA will generate bad address parity to the Register-Sender memory while all the others (Operation Code = 26 or 40 through 77 except 55 (STA) and 61 (PAR) will generate bad address parity to the Main Memory. Indirect addressing will also cause bad address parity.

Registers affected: None

Timing: 1 cycle

Bpr reset Bad Parity

(3700400)

Resets the Bad Parity Storage element.

Registers affected: None

Timing 1 cycle

Ssrtc switch to standby real time clock

(3701000)

this instruction sets a storage element, the output of which switches the MAIN REAL TIME CLOCK output off thus allowing the STANDBY REAL TIME CLOCK to run. A simulated MAIN REAL TIME CLOCK ERROR is created causing a level 8 interrupt.

Register affected: None

Timing: 1 cycle

Smrtc switch to main real time clock

(3702000)

this instruction resets the above storage element. The MAIN REAL TIME CLOCK takes over and the error indication caused by the previous action (SSRTC) is removed.

Register affected: None

Timing: 1 cycle

Enwd enable Watch Dog Timer

(3704000)

This instruction enables the Watch Dog Timer so that it can reset. (See 8.6)

Register affected: None

Timing: 1 cycle

Riw reset Interrupt Waits

(3720000)

This instruction resets the Wait States of the eight Interrupt Levels.

Register affected None

Timing: 1 cycle

Note: simultaneous selection of separate operators is allowed, e.g., 3700021 will effect the DSI and the REI operation. Ambiguous selections attempting to specify two states of a single operator (e.g. 3700014) result in unpredictable operation.

Rwd reset Watch Dog Timer

(3710000)

This instruction resets the Watch Dog Timer.

(See 8.6)

Register Affected: None

Timing 1 cycle

Sync resync Watch Dog Timer

(3740000)

This instruction resynchronizes the Watch Dog Timer. (See 8.6 for operation).

Register affected: None

Timing: 1 cycle

1.2.6 Branch and Skip Group

Rtn (10) branch Unconditional EA _{0 -14} ➝(PC) _{0 -14}

the next instruction in program sequence is at the effective address in the page specified by the instruction field of the Page Register.

INDIRECT ADDRESSING of this instruction will load the Page Register from the contents of the effective address as follows. When returning the data contents of the locations specified by the operand bits 0-14 will be loaded into the IR register in the normal manner and then loaded into the program counter; bits 15 thru 18 will be loaded into the branch and data fields of the Page Register. Thus return linkage to a different page other than the one where the RTN resides is possible. (refer to section 1.3.3 Paging).

Register affected: PC; PR if indirect

Timing: 1 cycle; 2 cycles if indirect

Bun (11) branch Unconditional EA _{0 -14} ➝(PC) _{0 -14}

the next instruction in program sequence is at the effective address in the page specified by the instruction field of the Page Register.

Register affected: PC

Timing: 1 cycle

Bao (35) branch A Register Overflow OVF = 1:EA _{0 -14} ➝(PC)

(not Indexable)

If the A register overflow indicator is set, the next instruction is taken from the location specified by the effective address. The overflow indicator is reset.

Register affected: PC if Branch Occurs

Timing: 1 cycle

BZA (13) Branch if A Register Zero (A) _{0 -23} = 0:EA _{0 -14} ➝(PC)

the next instruction is taken from the location specified by the effective address if the A register contents are zero.

Register affected: PC if Branch Occurs

Timing: 1 cycle; 2 if Indexed

Bna (14) branch if A Register Negative A ₂₃ = 1:EA _{0 -14} ➝ (PC)

the next instruction is taken from the location specified by the effective address if the contents of register A are negative.

Register affected: PC if Branch Occurs

Timing: 1 cycle; 2 if Indexed

Bpa (15) branch if A Register Positive A ₂₃ = O:EA _{0 -14} ➝(PC)

the next instruction is taken from the location specified by the effective address if the contents of register A are positive.

Register affected: PC if Branch Occurs

Timing: 1 cycle; 2 if Indexed

Bsp (62) branch and Store Program Linkage

OVF➝(EA) ₂₀ , CARRY➝(EA) ₁₉ , (LPR) _{0 -3} ➝(EA) _{15 -18} , (LPC) _{0 -14} ➝(EA) _{0 -14}

The current contents of the program counter and the page register as stored in the last program count register and the last page reference register and the overflow indicator and the carry indicator, replaces the contents of the memory word at the effective address. The next instruction is taken from the effective address plus one. This instruction will delay an interrupt by one instruction.

This instruction facilitates real time sub-routine linkages. The interrupt dealy feature provides a safeguard against inadvertent sub-routine re-entry; the interrupt system may be disabled by the first instruction in the sub-routine.

Register affected: PC

Timing: 2 cycles

Brr (16) branch Return Reset EA _{0 -14} ➝PC: 0➝INT. ACTIVE

if indirect

(EA) ₂₀ V OVF ➝OVF, (EA) ₁₉ V CARRY ➝CARRY

(EA) _{15 -18} ➝(PR) _{2 -5} (EA) _{0 -14} ➝(IR) _{0 -14}

the next instruction is executed at the effective address. The highest active interrupt is reset.

Register affected: PC

Timing: 1 cycle; 2 if Indexed

This instruction is used to exit from an interrupt subroutine and should be an indirect reference to the subroutine link location to properly restore the interrupted program. SMNT (7φ) Skip Memory Not True, i.e., if A and Memory Do not Compare Ones.

(A) _{0 -23} ^. (EA) _{0 -23} ≠0: (PC) + 1 ➝(PC)

Contents of the memory at the effective address are compared with register A. If they do not match in positions that contain a one in register A, skip one instruction.

Register affected: PC if Skip

Timing: 2 cycles

Smnz (71) skip if A and Memory Do Not compare Zeros

(A) _{0 -23} ^. (EA) _{0 -23} ≠0: (PC) + 1 ➝(PC)

Contents of the memory at the effective address are compared with register A. If the memory operand does not contain zeros in bit positions corresponding to "ones" in register A, skip one instruction.

Register affected: PC if Skip

Timing: 2 cycles

Smnn(77) skip if Memory Not Negative

(EA) ₂₃ = 0: PC + 1 ➝(PC)

If Bit 23 of the memory location at the effective address is a zero, skip one instruction.

Register affected: PC if Skip

Timing: 2 cycles

Ssnt (φ7) skip if Sense Group Not True

(SG _n ) ^. EA _{0 -7} ≠ 0: (PC) + 1 ➝(PC)

A portion of the effective address (bits 9 thru 7) form a mask. This mask is compared to 8 sense line inputs in any of 128 possible groups as specifed by bits 8 thru 14 of the effective address. If the selected sense line group and the mask do not compare one's, skip one instruction.

Register affected: PC if Skip

Timing: 1 cycle; 2 cycles if Indexed

The word format of the SSNT is as follows: ##SPC19##

The SSNT instruction can be used to test the condition of a maximum of 1024 individual input lines.

The sense group numbering, by nature of the position in the computer instruction follows the sequence (000, 010, 020, . . . 760, 770, 004, 014, 024, . . . 764, 774).

See Section 1.5.3 for explanation of sense lines. See Section 8.3 for sense line assignments.

Sane (72) skip if A Register Not Equal to Memory

(EA) _{0 -23} - (A) _{0 -23} ≠ 0:(PC) + 1 ➝(PC)

The contents of the memory at the effective address are compared with the A register. If the A register is not algebraically equal to the contents of the memory location at the effective operand address, skip one instruction.

Register affected: PC if Skip

Timing: 2 cycles

Lsga (φ6) load Sense Group into "A" Register

0 ➝(A) _{8 -23}

Selected SG ➝(A) _{0 -7}

The upper seven bits of the effective address defines the desired sense group. The assignment of sense group numbers for the seventy-one (71) standard sense groups given in the SSNT instruction also applies to this instruction. The contents of the selected sense group is placed in the lower eight bit position of the A register.

Register affected: A

Timing: 1 cycle

Samg (76) skip if Register A and Memory Do Not Compare

Equal as Masked by Register Q ##SPC20##

Register A and the contents of memory at the effective address are compared in positions extracted by the mask bits of Register Q. If they do not compare identically, skip one instruction.

Example:

Register A 6 7 4 0 6 1 5 3 (EA) 1 2 7 3 6 0 1 2 Register Q 0 0 0 0 7 0 0 0 (A) _{0 -23} ♁ (EA) _{0 -23} 7 5 3 3 0 1 4 1 ##SPC21##

Registers affected: PC if Skip

Timing: 2 cycles

Half Word Skips (φ4) Indexing will not affect extended Op code

This is an extended operation provided for half word immediate (or literal) tests of the A Register. The effective address field bits 12, 13 and 14 are used to specify the following skip tests: The execution time is 1 cycle.

Slnt (φ4φ) skip Left Not True (A) _{12 -23} ^. EA _{0 -11} ≠0:(PC) + 1 ➝(PC)

skip one instruction if bits 12-23 of register A do not compare one's as masked by bits 0-11 of the effective address.

Srnt (φ41) skip Right Not True (A) _{0 -11} ^. EA _{0 -11} ≠0: (PC) + 1 (PC)

skip one instruction if bits 0-11 of register A do not compare one's as masked by bits 0-11 of the effective address.

Slnz (φ44) skip Left Not Zeros (A) _{12 -23} ^. EA _{0 -11} ≠0: (PC) + 1 (PC)

skip one instruction if bits 12-23 of Register A do not contain zeros as masked by bits 0-11 of the effective address.

Srnz (φ45) skip Right Not Zeros (A) _{0 -11} ^. EA _{0 -11} ≠0: (PC) + 1 (PC)

skip one instruction if bits 0-11 of register A do not contain zeros as masked by bits 0-11 of the effective address.

Slne (φ42) skip Left Not Equal (A) _{12 -23} - EA _{0 -11} ≠0: (PC) + 1 (PC)

skip one instruction if bits 0-11 of the effective address and bits 12-23 of register A are not equal.

Srne (φ43) skip Right Not Equal (A) _{0 -11} - EA _{0 -11} ≠0: (PC) + 1 (PC)

skip one instruction if bits 0-11 of the effective address and bits 0-11 of register A are not equal.

1.2.7 Shift Group

The execution time for all shift instructions is N + 3/4 cycles; N is specified in the effective address of the instruction.

The notation convention utilized in the following descriptions are iteration formulas. Termination occurs after N iterations unless otherwise specified.

Sal (34φ) shift Register A Left Arithmetic

(A) _i ➝(A) _i + 1

0➝(A) ₀

(a) ₂₂ ♁ (a) ₂₃ :1 ➝ovf

(not Indexable) the A register is shifted left N bit positions. Zeros are placed in the N least significant bits of Register A (open end shift). An overflow occurs if the register is shifted when bit 23 does not equal bit 22. N shifts will be completed regardless of overflow.

Registers affected: A

Sar (341) shift Register A Right Arithmetic

(A) _i ♁ 1 ➝(A) _i

(A) ₂₃ ➝(A) ₂₂

(a) ₂₃ ➝(a) ₂₃

(not Indexable) the A Register is shifted right N positions. Bit 23 is not changed and is shifted to bit 22 for each specifed shift.

Registers affected: A

Lsl (342) long Shift Left Arithmetic

(A) _i 43 (A) _{i + 1} ; (Q) ₂₃ ➝(A) ₀ ; (Q) _i ➝(Q) _{i + 1} ; 0➝(Q) ₀ ; (A) ₂₂ ♁ (A) ₂₃ :1 ➝ OV

(Not Indexable) the double precision register A-Q is shifted left N bit position. Zeros are entered into the least significant N bits of A-Q. An overflow will occur if the double register is shifted when A ₂₃ does not equal A ₂₂ . Bit 23 of Register Q is shifted. N shifts will be completed regardless of overflow.

Registers affected: A-Q

Lsr (343) long Shift Right Arithmetic

(A) _{i +1} ➝(A) _i ; (A) ₀ ➝(Q) ₂₃ ; (Q) _{i +1} ➝(Q) _i ; (A) ₂₃ ➝(A) ₂₂ ; (A) ₂₃ ➝(A) ₂₃

Not Indexable. The double precision register A-Q is shifted right N bit position. Bit A ₂₃ is not changed, however, its value is copied into Bit A ₂₂ . Bit Q ₂₃ is shifted. Bits shifted beyond Q ₀ are lost.

Registers affected: A-Q

Smp (344) shift and Mark Position

(A) ₂₃ =1 Termination 0➝(Q) ₀ ; (Q) _i ➝(Q) _{i +1} ; (Q) ₂₃ ➝(A) 0 ; (A) _i ➝(A) _{i +1}

(Not Indexable) A ₂₃ is tested to see if it equals one. If A ₂₃ ≠1, A-Q registers are shifted left until A ₂₃ 32 1 or the number of shifts equal the maximum field length has been tested, the number of shifts is placed in the index register specified by the TAG field.

Registers affected: A, Q, X

Llr (120) long Left Rotate

(A) _i ➝(A) _{i +1} ; (Q) ₂₃ ➝(A) ₀ ;

(q) _i ➝(Q) _{i +1} ; (A) ₂₃ ➝(Q) ₀

the double precision register A-Q is shifted right N bit positions. Bit Q ₀ is shifted to bit A ₂₃ ; and bit A ₀ is shifted to bit Q ₂₃ .

Registers affected: A-Q

Lrr (121) long Right Rotate

(A) _{i +1} ➝(A) _i ; (A) ₀ ➝(Q) ₂₃ ;

(q) _{i +1} ➝(Q) _i ; (Q) ₀ ➝(A) ₂₃

the double precision register A-Q is shifted right N bit positions. Bit Q ₀ is shifted to bit A ₂₃ ; and bit A ₀ is shifted to bit Q ₂₃ .

Registers affected: A-Q

Lla (122) left Shift A Logical

(A) _i ➝(A) _{i +1} ; 0➝(A) ₀

the contents of register A are shifted left N bit positions. Zeros are entered in the least significant N Bits of register A. Bits shifted out of position A ₂₃ are lost. No overflow is recorded.

Register affected: A

Llq (124) left Shift Q Logical

(Q) _i ➝(Q) _{i +1} ; 0➝(Q) ₀

the contents of register Q are shifted left N bit positions. Zeros are entered in the N least significant bits. Bits shifted out of Q ₂₃ are lost. No overflow is recorded.

Register affected: Q

Lra (123) right Shift A Logical

(A) _{i +1} ➝(A) _i ; 0➝(A) ₂₃

the contents of register A are shifted right N bit positions. Zeros are entered in the N most significant bits of register A. Bits shifted out of position A ₀ are lost.

Register affected: A

Lrq (125) right Shift Q Logical

(Q) _{i +1} ➝(Q) _i ; 0➝(Q) ₂₃

the contents of register Q are shifted right N bit positions. Zeros are entered into the N most significant bits of Register Q. Bits shifted out of Q ₀ are lost.

Register affected: Q

1.2.8 logical Operator Group

Ana (5φ) and a with Memory (A) _{0 -23} ^. (EA) _{0 -23} ➝(A) _{0 -23}

the contents of memory at the effective address and Register A are compared bit by bit. Register A will contain a one where corresponding bits in both register A and the memory word are one's. The result remains in A.

Register affected: A

Timing: 2 cycles

Ora (51) or (Merge) Memory with A

(a) _{0 -23} v (ea) _{0 -23} ➝(a) _{0 -23}

the contents of the memory at the effective address and Register A are compared bit by bit. Register A will contain a one in bit positions corresponding to those in which either Register A or the memory word contain a one. The result remains in A.

Register affected: A

Timing: 2 cycles

Era (52) exclusive-Or Memory with A

(a) _{0 -23} ♁ (ea) _{0 -23} ➝(a) _{0 -23}

the contents of the memory location at the effective address and Register A are compared bit by bit. Register A will contain a one where either register A or the memory word, but not both, contain a one in corresponding bit positions. The result remains in A.

Registers affected: A

Timing: 2 cycles

Half Word Logicals (HWL)

This is an extended operation provided for half word immediate logical operation on Register A. Three bits (12, 13 and 14) of the effective address field are used to specify the following logical operations.

Timing: 1 cycle, 2 if Indexed.

Anl (φ3φ) and Left (A) _{i +12} ^. EA _i ➝(A) _{i +12} ; 11 ≥ i ≥ 0

The effective address bits 0-11 are compared bit by bit with register A bits 12-23. Register A bits 12-23 will contain a one where corresponding bits in both register A and the effective address contain a one.

Register affected: A

anr (φ31) and Right (A) _i ^. EA _i ➝(A) _i ; 11 ≥ i ≥ 0

The effective address bits 0-11 are compared bit by bit with register A bits 0-11. Register A bits 0-11 will contain a one where corresponding bits in both Register A and the effective address contain a one.

Register affected: A

orl (φ32) or Left (A) _{i +12} V EA _i ➝(A) _{i +12} ; 11 ≥ i ≥ 0

The effective address bits 0-11 are compared bit by bit with Register A bit 12-23. Register A will contain a one where corresponding bits in either effective address bits 0-11 or register A bits 12-23 contain a one.

Register affected: A

Orr (φ33) or Right (A) V EA _i ➝(A) _i 11 ≥ i ≥ 0

The effective address bits 0-11 are compared bit by bit with Register A bit 0-11. Register A will contain a one where corresponding bits in either the effective address bits 0-11 or Register A bits 0-11 contain a one.

Register affected: A

Erl (φ36) exclusive Or Left

(A) _{i +12} ♁ EA➝(A) _{i +12} ; 11 ≥ i ≥ 0

The effective address bits 0-11 are compared bit by bit with register A bits 12-23. Reigster A will contain a one where corresponding bits in either the effective address bits 0-11 or Register A bits 12-23, but not both, contain a one.

Register affected: A

Err (037) exclusive Or Right

(A) _i ♁ EA _i ➝(A) _i ; 11 ≥ i ≥ 0

The effective address bits 0-11 are compared bit by bit with Register A bits 0-11. Register A will contain a one where corresponding bits in either the effective address bits O-11 or Register A bits 0-11 but not both, contain a one.

Register affected: A

Adl (034) add Immediate Left

Ea _{0 -11} + (a) _{12 -23} ➝(a) _{12 -23}

the effective address bits 0-11 are added to register A bits 12-23. Register A bits 0-11 are not affected. Overflow and carry indicators are not affected.

Register affected: A

Adr (035) add Immediate Right

Ea _{0 -11} + (a) _{0 -11} ➝(a) _{0 -11}

the effective address bits 0-11 are added to register A bits 0-11. Register A bits 12-23 are not affected. Overflow and carry indicators are not affected.

Register affected: A

1.2.9 program Control Group

Hlt (67) halt EA _{0 -14} ➝PC

processing this instruction will cause the central processor to stop. If the processor is on-line, a timer, after a delay of 1 microsecond, will cause the processor to run. If not on-line, then a signal from the computer programming console or the computer third party, will be required before the processor can start.

Register affected: None

Timing: 1 cycle

Xec (47) execute

The instruction at the effective address will be executed. The next instruction will be taken from the location specified by the program counter. Thus, a branch or a skip could change the program counter. The instruction at the effective address may be indexable or indirectly addressable.

Register affected: Refer to appropriate instruction being executed.

Timing: 1 cycle plus Execution Time of Instruction

1.2.10 Input/Output Group

Sel (05) select Input Output Operation

The effective address is interpreted to select an input/ output Channel Controller, Peripheral Adapter device and function at the device for subsequent data transfer operations. Bit 14 of the effective address is used to arm the Channel Ready Interrupt. A Channel Controller disconnect function will disarm the interrupt. The Priority Interrupt System will be disabled for one instruction execution time. This instruction is also used in selecting third party functions.

Register affected: None

Timing: 1 cycle

Cpd (17) control Pulse Directive

The effective address of this instruction is interpreted by external functions as follows: ##SPC22##

Register affected: None

timing: 1 cycle

See Section 8.5 for CPD explanation.

Cca character Copy I/O Register A (33)

This is an extended operation provided for versatile input and output word assembly and disassembly under program control. Three bits (12, 13, and 14) of the effective address are interpreted as an operation code extension field to determine register format control. The N field is used in a manner similar to the shift instructions to determine the number of binary positions for rotation. This instruction is not indexable.

Cco character Copy Output

(33φφφφ6)

Rotate Register A left six binary digit positions

(N = 6) and copy bits 0-5 to the output channel.

(331 φφ1φ)

Rotate Register A left eight binary digit positions

(N - 10 ₈ ) and copy bits 0-7 to the output channel.

(332 φφ14)

Rotate Register A left twelve binary digit positions

(N = 14 ₈ ) and copy 0-11 to the output channel.

(333φφφφ)

Copy Register A bits 0-23 to the output channel.

Cci character Copy Input

(334 φφφ6)

Rotate Register A left 6 binary digit positions (N = 6)

and copy bits 0-5 of the input channel into bits 0-5

of Register A.

(335φφ1φ)

rotate Register A left 8 binary digit positions

(N = 10 ₈ ) and copy bits 0-7 of the input channel into

bits 0-7 of Register A.

(336φφ14)

rotate register A left twelve binary digit positions

(N = 14 ₈ ) and copy bits 0-11 of the input channel into

bits 0-11 of Register A.

(337 φφφφ)

copy bits 0-23 of the input channel into bits 0-23

of Register A.

Register affected: A

Timing: N + 7/4 cycles

1.2.11 Transfer and Exchange Group

Xam (53) exchange Register A and Memory

(EA) _{0 -23} ➝(A) _{0 -23}

the contents of memory at the effective address are exchanged with the contents of Register A.

Register affected: A

Timing: 3 cycles

Rtr (36x) register to Register

This is a non-indexable extended operation provided for operations between registers. Three bits (12, 13, and 14) of the effective address field are interpreted as an operation code extension (OPE) field. The instruction word format for this instruction is as follows: Single cycle. ##SPC23##

Crr copy Register to Register

Ope 000 (so) ➝(sk)

copy selected source register into sink register Source register in uneffected. Multiple sources selection results in logical "OR" copies. Multiple sink selection results in simultaneous copy to all selected registers.

Ccr copy then Clear Register

Ope 001 (so)➝(sk); 0➝(so)

copy selected source register to sink register. Source register is cleared to zeros except PC which remains unaffected. Multiple source selection results in a logical "OR" copies and cleared. Multiple sink selection is allowed.

Exr exchange Registers

Ope 010 (so) (sk); (sk) (so)

exchange selected source register with selected sink register. Multiple selection of source or sink will result in logical "OR" of source or sink registers participating in the exchange For exchange involving a small register and a large register, non-corresponding bits are zeroed or lost as the case may be.

______________________________________ Bit 0 Reg A is the Sink 1 Reg Q is the Sink 2 Reg X1 is the Sink 3 Reg X2 is the Sink 4 Reg X3 is the Sink 5 Reg Diag is the Source 6 Reg A is the Source 7 Reg Q is the Source 8 Reg X1 is the Source 9 Reg X2 is the Source 10 Reg X3 is the Source 11 Reg PC and PR is the Source ______________________________________

See section 8.2 for register to register operation map.

Section 1.3 address Modification

Address modification in the No. 1 EAX computer is accomplished by: Indexing, Indirect Addressing, Paging.

Indexing and Indirect addressing operate directly with the operand portion of the instruction.

Indirect addressing in specific instructions operates also on the Page Register.

Paging operates only on the Page Register.

Indexing and indirect addressing are operators to an instruction while paging in an instruction itself. Indexing and indirect addressing can be used by themselves or in combination. If both are specified, indexing is done first and then indirect addressing. The instructions upon which the address modification is performed is retained in memory in its unaltered form.

1.3.1 Address Modification Using Index Registers

Three hardware index registers are provided in the basic standard mainframe for address modification. Any of the three registers (X ₁ , X ₂ , X ₃ ) can be specified by the programmer by encoding the appropriate bits in the tag field of the instruction. The instruction is then executed as if its address field contained the specified address of the instructions plus the contents of the index register (additive indexing).

EXAMPLE

Instruction = ADD 47631,2 (Note: 2 specifies index register No. 2)

Contents of X ₂ = 00135

Address of Data = 47766

Address modification is accomplished by using binary radix complement (2's complement) arithmetic modulo 2 ¹⁵ . The algorithm may be stated as follows:

EA = (Y + X _n ) modulo 2 ¹⁵ EA = Effective Address Y = Specified Instruction Address X _n = Specified Index Register

A powerful set of instructions is provided for index register modification. These instructions operate on the index registers using 2's complement arithmetic modulo 2 ¹⁴ . Thus, the index registers may be incremented or decremented and tested for terminal condition by examination of the highest order bit. The incrementing and decrementing operations may be explained as follows:

1. Index register in "positive" range -- Index register may be incremented or decremented and terminal test is for a "one" in the 15th bit position (negative index).

2. Index Register in the "negative" number range. -- Index register may be incremented or decremented in this range and the terminal test is for a "zero" in the 15th bit position (positive index).

This method of indexing allows the programmer complete flexibility in his choice of address manipulation.

Literal Add (ADX) and Subtract (SBX) operations on the specified index registers, coupled with individual conditional Branch instructions provide yet another degree of programming freedom.

Programming flexibility is further enhanced by the provision of literal clear and subtract index (CSX) and the clear and add index (CAX) instructions. By the use of these instructions, an index register is easily initialized. The literal index operator instructions are unique in the use of the indirect reference bit. These instructions are normally used to load the index register directly from the operand field of the instruction, however, if the indirect addressing bit is set, the index register is loaded from memory at an effective address specified by the address field of the instruction.

Register transfer instructions (RTR) provide the capability of transferring the index registers to any other operating register and conversely, from the operating registers to the index registers.

1.3.2 Indirect Addressing

The concept of providing alternatives for addressing is extended by the use of indirect addressing. In very much the same manner as the index registers are specified by 2 bits in the tag field, indirect addressing also is specified by a separate bit in the tag field; thus allowing an instruction to have index modification and indirect addressing by a single tag field specification.

If an instruction operation calls for an operand to be retrieved from memory, and if that same instruction has its indirect addressing tag bit set, the address field of the instruction after modification by the indexing operations refers to the memory location at which the address of the operand will be found. Further, if that location also has the indirect tag bit set, the contents of that location after modification by indexing, is interpreted as the address at which the address of the operand will be found. Thus, the indirect addressing and indexing process is iterative. Instruction execution time is increased by one cycle for each level of indirect addressing. The following example will further illustrate the concept of indirect addressing (*will be used to indicate the indirect address tag field bit):

LOCATION CONTENTS REMARKS ______________________________________ 00345 *ANA 43217 Instruction to be executed. 43217 * 0037416 Location of next indirect address. 37416 00037500 Location of operand address. 37500 77777777 Operand location. ______________________________________

1.3. Paging

In order to increase the memory addressing capabilities of the Central Processor beyond the 32K of directly-addressable core memory that is possible with its 15 bit address field, a paging technique is employed. A page consists of no more than 32K of core memory. No more than 4 pages are to be implemented under present design. This limits the size of core memory to 131K. To implement paging, a page register, a last page reference, and paging instructions are described as follows.

1.3.3.1 The Page Register will be a six-bit storage register:

The Page Register is sectioned into three fields:

a. The DATA FIELD is bits 4 and 5,

b. The BRANCH FIELD is bits 2 and 3.

c. The INSTRUCTION FIELD is bits 0 and 1.

The format for the Page Register is as follows: ##SPC24##

1.3.3.2 Last Page Reference

The Last Page Reference is a four-bit storage register, sectioned into two two-bit fields, called the LAST DATA FIELD, and the LAST INSTRUCTION FIELD.

The format for the Last Page Reference is as follows: ##SPC25##

The LAST DATA FIELD is loaded during every Cycle One, Level Two, except when a trap occurs. The LAST DATA FIELD is loaded from the DATA FIELD of the Page Register.

The LAST INSTRUCTION FIELD is loaded during every Cycle One, Level Two (except when a trap occurs), from the INSTRUCTION FIELD of the Page Register.

1.3.3.3 The Paging instructions are as follows:

LOAD PAGE REGISTER GROUP (66)

(Not indexable)

This is an extended operation, provided for the loading of the Page Register.

The effective address field, bits 12 and 13, is used to specify which field of the Page Register is to be loaded. Bit 14 of the effective address is used to specify a transfer of INSTRUCTION FIELD information bits into the DATA FIELD.

Bits 0, 1, 3, and 4 of the operand will specify the page number to be loaded into the selected field, except during a transfer of the INSTRUCTION FIELD into the DATA FIELD. In this latter case bits 0, 1, 3 and 4 are ignored.

Simultaneous selection of the extended OP codes is allowed. E.g. 06630011 will load both the BRANCH FIELD and the DATA FIELD of the Page Register with page 01.

This is a single-cycle instruction.

Interrupts will be ignored during this instruction.

(Refer to Section 1.5.2.2)

Lpd (661): load data field ea ₃ ,4 ➝(pr) ₄ ,5

(not Indexable)

The effective address, bits 3 and 4, is loaded directly and respectively into bits 4 and 5 of the Page Register (DATA FIELD).

Register affected: Page Register

Timing: 1 cycle

Lpb (662): load branch field ea ₀ ,1 ➝(pr) ₂ ,3

(not Indexable)

The effective address, bits 0 and 1, is loaded directly and respectively into bits 2 and 3 of the Page Register (BRANCH FIELD).

Register affected: Page Register

Timing: 1 cycle

Lpdb (663): load data and branch field ea ₃ ,4 & 0,1 ➝(pr) ₄ ,5 & 2,3

(not Indexable)

The effective address, bits 3, 4, 0 and 1 is loaded directly and respectively into bits 4, 5 (DATA FIELD) and 2, 3 (BRANCH FIELD) of the Page Register.

Register affected: Page Register

Timing: 1 cycle

Tid (664): transfer instruction field to data field

(not indexable) (PR) ₀ ,1 ➝(PR) ₄ ,5

this instruction will allow referencing data storage within the instruction storage references of the running program.

Register affected: Page Register

Timing: 1 cycle

Rtn (10)..return ea _{0 -14} ➝(pc)

(indexable)

This instruction is an unconditional branch, the same as BUN with the following exception:

When RTN is processed indirect, bits 15 thru 18 of the indirect location will be loaded into the BRANCH FIELD and the DATA FIELD of the Page Register, bits 2 through 5 respectively.

Brr (16) branch return reset

when this instruction is processed indirect it will load bits 15 thru 18 of the indirect location into the branch field and the data field, bits 2 thru 5 respectively, of the Page Register. (Refer to instruction set section 1.2 for further information on this instruction).

Bsp (62) branch and store program linkage

bsp will store the LAST DATA FIELD and the LAST INSTRUCTION FIELD of the Last Page Reference Register into bits 18 and 17 and bits 16 and 15 of the location referenced by the operand. Bits 0 through 14 therefore, contain the Last Program Count Register (LPC); bits 15 and 16 contain the LAST INSTRUCTION FIELD: and bits 17 and 18 contain the LAST DATA FIELD. Bits 19 and 20 will contain the carry and overflow indicators.

When processed indirect, BSP will inhibit loading of address bits 15 and 16 onto the Address Bus, thus forcing the memory reference to page 00. The data word read from the indirect location is stored in the processor's logic and appears at the output of the Adder. Adder bits 15 and 16 are loaded into the BRANCH FIELD of the Page Register. The BRANCH FIELD becomes the address source and specifies the page where the Last Page Reference Register and Last Program Count Register is to be stored.

The Exact location within that page is specified by the "S" register. After storage of the information, the Adder output, bits 17 and 18, are loaded into the DATA FIELD of the Page Register, and the BRANCH FIELD is transferred to the INSTRUCTION FIELD of the Page Register.

Rtr.. register-to-register transfer

the Page Register will become a source whenever the Program Counter becomes a source. Thus when used in this way with Register A or Register Q, the address plus the six bits of the Page Register can be transferred to these programmable registers so that the Page Register can be interrogated for maintenance purposes. PRO-5 to (A+Q) 15-20.

1.3.3.4

the Address bus of the Central Processor contains the 15 bits of the "S" register or the program counter, depending whether a data reference or an instruction reference is in process, and two bits from the output of the Page Register. These two bits, (15 and 16) are the controlled "OR"(ed) output of the DATA FIELD, BRANCH FIELD and INSTRUCTION FIELD of the Page Register.

1.3.3.5

Definition of DATA AND INSTRUCTION storage

1.3.3.5.1

DATA storage is defined as those locations of memory where references are made for the purpose of:

1.3.3.5.1.1

Loading information into programmable registers Instructions that do this are: ADD (40), SUB (41), MUL (42), DIV (43), CSA (56), LDA (54), LDQ (64), ANA (50), ORA (51), ERA (52), XAM (53), PRA (60).

1.3.3.5.1.2

modifying locations: Instructions that do this are: AOM (44), SOM (45), ADM (46), STX (26), RPA (57), STA (55), STQ (65), STC (75).

1.3.3.5.1.3

executing an instruction out of sequence with the running program. Such an instruction is XEC (47).

1.3.3.5.1.4

comparing such storage. Instructions that do this are SMNT (70), SMNZ (71), SANE (72), SANG (73), SAMQ (76), SMNN (77).

1.3.3.5.1.5

distributing data to the input-output path. Instructions that do this are LDC (74) and PAR (61).

1.3.3.5.1.6

modifying the address or operand of any instruction, except BUN (11), BSP (62), HLT (67) and RTN (10), BRR (16).

1.3.3.5.2

instruction storage is defined as those locations of memory where references are made for the purpose of:

1.3.3.5.2.1

Obtaining the next instruction to be processed, except XEC (47)

1.3.3.5.2.2

modifying the address of a BUN (11), HLT (67), RTN (10), BRR (16) instruction.

1.3.3.5.2.3

Storing the Last Page Register and LPC (Last Program Count) Register, and then branching to the following location, where the storage took place. The instruction that does this is a BSP (62). In this case the BRANCH FIELD will be the page source.

1.3.3.6

Address Modification

1.3.3.6.1

Indexing is accomplished over the 15-bit operand field of the instruction. Indexing will not be extended to the Page Register. Thus, if indexing modifies the operand beyond the 15-bit capacity, a "wrap-around" effect will occur within the page referenced.

1.3.3.6.2

Indirect modification of the operand of an instruction will be via the DATA FIELD of the Page Register, except in the BRR, BUN, HLT, and RTN instructions. These instructions will use the Instruction Field as memory references. An additional exception will be the BSP instruction. BSP indirect will inhibit the output of the Page Register, forcing the indirect reference to page φφ. The location referenced will point to the page and location where the Last Page Reference Register and LPC are to be stored. During the BSP instruction the Page Reference Register LAST DATA FIELD and LAST INSTRUCTION FIELD are stored at the location specified, and the Page Register is loaded with the data and branch information that was stored in the indirect reference.

1.3.3.7

Features of Page Register and Last Page Reference Register Operation

1.3.3.7.1

Whenever any branch instruction is executed, the BRANCH FIELD of the Page Register will transfer its contents into the INSTRUCTION FIELD.

1.3.3.7.2

during data storage references, the DATA FIELD of the Page Register will be gated onto the Address Bus of the CCP.

1.3.3.7.3

during instruction storage references, the INSTRUCTION FIELD of the Page Register will be gated onto the Address Bus of the CCP, except during the BSP instruction. For this instruction the BRANCH FIELD is used as the page source.

1.3.3.7.4

During each Cycle One, Level Two, Pulse Three, the LAST DATA FIELD and the LAST INSTRUCTION FIELD of the Last Page Reference Register will be loaded from the DATA FIELD and INSTRUCTION of the Page Register, except when a trap occurs. 1.3.3.8 Example of Page Register Operation

Page 00 ______________________________________ LOCATION MACHINE LANGUAGE ASSEMBLER LANGUAGE ______________________________________ 00100 00000104 A NDS 00000000+E 00101 00102 00103 00104 00100106 E NDS 00105 06610010 LPD 01 00106 05400112 LDA K 00107 41000104 RTN*E (=RTN G) 00110 00111 00000005 NDS 05 00112 05400111 L NDS 05400111 ______________________________________

Contents of Page 01 ______________________________________ LOCATION MACHINE LANGUAGE ASSEMBLER LANGUAGE ______________________________________ 00100 06200102 A BSP C 00101 01100105 B BUN F 00102 00100101 C NDS 00103 04700112 D XEC L 00104 41000102 E RTN*C (=RTN B) 00105 46200100 F BSP*A (=BSP E) 00106 41100112 G BUN*K (-BUN J) 00107 00110 00111 06700111 J HLT $ 00112 00000111 K NDS 0111 ______________________________________

Initial Conditions for the Example

The initial condition of the Page Register is DATA FIELD = 00, BRANCH FIELD = 01, INSTRUCTION FIELD = 01, and the Program Counter of the CCP = 00100.

This initial condition allows the processing of the instruction located in page 01, address 00100. The BSP to location C references instruction storage. The BRANCH FIELD of the Page Register indicates the page in which location C resides. The BSP instruction will store contents of the DATA FIELD and the INSTRUCTION FIELD of the Page Register into location C (Bits 18 thru 15). Condition of the Page Register after this instruction is: ##SPC26##

Since the INSTRUCTION FIELD of the Page Register is set to 01, and the Program Counter of the CCP now equals 00103, the next instruction to be processed will be XEC. XEC references data storage and since the DATA FIELD of the Page Register is set to 00, the data in location L (00112) in page 00, will be processed as an instruction, and will in this case, load Register A of the CCP from location 00111 in page 00. This is because the LDA instruction references data storage and the DATA Field still is set to 00. Condition of the Page Register after this instruction is: ##SPC27##

The INSTRUCTION FIELD is at 01 and the Program Counter of the CCP is at 00104, therefore the next instruction to be processed resides in page 01 location 00102. RTN*C references instruction storage. Location C (00102) is in page 01 as indicated by the INSTRUCTION FIELD of the Page Register, and contains the return location (00101) and the stored DATA FIELD and INSTRUCTION FIELD. The stored values for DATA FIELD and INSTRUCTION FIELD are loaded respectively into the DATA FIELD and the BRANCH FIELD of the Page Register. The BRANCH FIELD's contents are then transferred into the INSTRUCTION FIELD, so that the return can be complete. Condition of the Page Register after this instruction is: ##SPC28##

The Progam Counter of the CCP now reads 00101, and the INSTRUCTION FIELD of the Page Register reads 01. The next instruction is read from page 01, location 00101. The BUN F is processed as an instruction storage. No changes are made to the Page Register and the next instruction is read from Page 01, location F (00105).

The instruction BSP*A inhibits the output of the Page Register, so that location A (00100) in page 00 will be referenced. The BSP instruction will temporarily store not only bits 9 through 14 of the referenced location, but also, bits 15 through 18. These bits will contain information for the BRANCH FIELD and the DATA FIELD of the Page Register respectively. Before loading the information into the Page Register, however, the DATA FIELD and the INSTRUCTION FIELD contents of the Page Register will be stored. After storage, the Page Register will be loaded, and then the BRANCH FIELD will transfer its contents to the INSTRUCTION FIELD. Processing of the instruction has now changed the Page Register so that the INSTRUCTION FIELD is now 00 or pointed to page 00. The next instruction therefore will be read out of Page 00, location 00105. These changes in the Page Register occur during the BSP* instruction: ##SPC29##

The next instruction to be processed is in Page 00, location 00105. An LPD (Load Data Field) instruction is inserted at this point, because the next instruction to be processed references data storage in page 01. (LDA K requires data from page 01 location K (00112). The LPD 01 will load the Page Register's DATA FIELD = 01. There will be no change in the other fields. The next instruction processed, then, would be the LDA K. Since LDA K references data storage and the DATA FIELD is equal to 01, Register A will be loaded with 00000111. Since the next instruction to be processed, RTN*E, does not use the DATA FIELD for memory references, and since the RTN*E will pick up new DATA FIELD information, it is not necessary to use a LPD to alter the DATA FIELD of the Page Register.

RTN*E references instruction storage. Location E (00104) is in page 00 as indicated by the INSTRUCTION FIELD of the Page Register. This storage contains the return location (00106) and the stored DATA FIELD and INSTRUCTION FIELD. The stored DATA FIELD and INSTRUCTION FIELD are loaded into the DATA FIELD and BRANCH FIELD of the Page Register. The BRANCH FIELD contents are then transferred into the INSTRUCTION FIELD, so that the return can be complete.

Conditions of the Page Register during this instruction are: ##SPC30##

The INSTRUCTION FIELD points to page 01 and the Program Counter of the CCP reads 00106. The BUN*K references instruction storage and goes to location K, (00112) in page 01 for the address where the next instruction resides. The Page Register is not changed at this time. Condition of the Page Register after this instruction is: ##SPC31##

Page 01 and location 00111 hold the instruction HLT $. This is an instruction storage reference. The address of the next instruction is in Page 01, location 00111. No change to the Page Register.

1.4 ARITHMETIC

The Computer performs binary, fixed point, arithmetic computations on basic single precision (24 bits) data words. For certain arithmetic operations, (e.g. MUL. DIV. SHIFT) register Q is provided for some degree of extended precision. The extended register Q facilitates double precision operations but it is emphasized that the basic accumulation of an arithmetic process is single precision only. Extensive shifting and exchange operations on registers A and Q are provided to simplify programmed multiple precision subroutines. Extended precision is provided for multiply operations in that the product of two single precision numbers can result in a double precision product which in turn appears in registers A and Q as if they were a single register. Division on the other hand, is basically an inverse of multiplication and register A-Q is now used for a double precision divident; the resultant remainder appears in register Q and the quotient in register A.

Negative numbers are represented in 2's complement form. The arithmetic shifting operations are consistent with this notation ##SPC32##

An overflow indicator is provided for the following:

a. a Sum or a difference (resulting from ADD, ADI, SUB or SBI operations) that cannot be contained within the A register.

b. A Division operation which would result in a quotient exceeding the capacity of the A register (Division by zero is a special case resulting in a trap level 2)

c. The results of arithmetic left shift operations (SAL, LSL,) which would exceed the number range of the original data words (for example a negative number that is shifted into a positive number range).

A CAR storage element is set whenever a carry out of bit 23 of the adder is true during an ADD, SUB ADI or SBI instruction. The storage element is reset when a carry is not true out of bit 23 of the adder during an ADD, SUB, ADI or SBI instruction.

The CAR storage element is also set during a BRR instruction indirect, if the indirect location contained bit 19 true.

Section 1.5 priority Interrupt and Sense Line System

1.5.1 Introduction

The Computer Central Processor is equipped, with a real time, priority Interrupt and Sense Line System, to handle external requests and abnormal conditions.

All external signals that require immediate service are assigned to one of the eight levels of interrupt priority. Each of these signals are also assigned to a unique Sense Line as are other external signals not requiring immediate attention. Some internal indicators of the Central Processor are also assigned to Sense Lines.

1.5.2 Interrupt System

1.5.2.1 Description

There are eight levels of Interrupt. Priority is hard wired and the highest level is assigned to Interrupt One, the next highest level of priority is assigned to Interrupt No. two and so on down to the lowest level which is assigned to Interrupt No. eight.

The Interrupt System is scanned each instruction cycle to see if a signal, with a higher priority than the program running, requires servicing. If such a signal exists the Central Processor is forced to execute an instruction from the dedicated location of the interrupt involved. If linkage to the interrupt program is to be saved a BSP instruction should reside in the dedicated location. After processing the signal, the use of a BRR instruction indirect will take you back into the program where the interrupt occurred, and into the next sequence of instructions. The BRR will have also reset the highest Active Interrupt.

1.5.2.2 Interrupt Control: Enable and Disable

There are two control instructions which allow the programmer to exercise some influence over the interrupt system. The enable Interrupt (ENI) is provided to allow interrupts to break into the running program. The disable interrupt (DSI) is provided, so that the running program will not be bothered with an Interrupt Break.

Certain instructions will ignore interrupt requests during their process time. This will enable at least one more instruction to be processed before being forced to an interrupt address. These instructions are the, BSP (Branch and Store Last Program Count), thus protecting the loss of its re-entry capability. ENI (enable Interrupts), thus allowing programming to enable the interrupts, and to process at least one more instruction without interrupt. LDQ (Load Register Q), thus allowing the program time to process a sense line instruction (SSNT or LSGA) for the purpose of interrogating the sense line indication of the 25th bit of the memory location referenced by the LDQ. An interrupt between the processing of these two instructions can lose the indication. LPR (Load Page Register), thus allowing the Last Page Register to reflect the updated Page Register and maintain correct linkage. SEL (Select an I/O Channel or Third Party), thus allowing a subsequent data transfer.

1.5.2.3 Priority Interrupt Assignments to levels and their unique Sense Lines (See Section 8.4).

1.5.2.4 Priority Interrupt Operation

Any given priority interrupt level may be in one of three states: Inactive, Wait, Active.

The inactive state is completely neutral; no interrupts are awaiting service and none are being serviced.

The wait state stores the fact that an external signal requires servicing. The wait state will persist until all higher level interrupts which are waiting or are active, have been processed. When all higher level interrupts have been serviced the wait condition will be transferred to the active state.

The active state indicates that the Central Processor has recognized that level of interrupt, has caused an automatic transfer to the levels dedicated location and is being processed. Interruptions by higher level interrupts, or traps will not change this state, but will defer the completion of the processing associated with it. The active state is reset by the execution of a BRR instruction when no other interrupt of higher priority is active.

Disabling the Interrupt system does not affect the state of any level. New signals will be allowed into wait states, Active interrupts could be reset with BRR instructions. During a Disable period no interrupt breaks will be formed.

The active state of each level can be interrogated via the Sense Line group 52 the individual assignments are as follows:

64001 INTERRUPT 1 ACTIVE

64002 interrupt 2 active

64004 interrupt 3 active

64010 interrupt 4 active

64020 interrupt 5 active

64040 interrupt 6 active

64100 interrupt 7 active

64200 interrupt 8 active

1.5.3 sense Line System

1.5.3.1 Description

Certain conditions within the Central Processor and within the subsystems external to the Central Processor must be available for immediate decision making. The Sense Line system is the concentration point of these signals and its output is controlled by the Two Sense Line Instructions SSNT (Skip Sense Line not true) and LSGA (Load Sense Group into Register A).

These two instructions present the following format: ##SPC33##

The tag field is for indirect addressing or indexing as explained in section 1.3. Both SSNT and LSGA, instrucions can be indexed and are capable of indirect addressing.

The op code field specifies the instruction.

The octal numeral representation for LSGA is 06.

The octal numeral representation for SSNT is 07.

The group specifies one of a possible 128 sense groups. Each group contains 8 Sense Lines. All groups are not implemented. Some groups are specified for maintenance use, others are for furture expansion.

The group field, (numeral representation,) by nature of it's bit position in the instruction follows the sequence (000, 010, 020, . . . , 760, 770, 004, 014, 024, . . . , 764, 774). Each group is assigned a decimal numeral. The decimal numeral is not directly translatable to the octal representation of it's associated group, however a translation is obtainable by the following algorithm.

1. Convert the decimal to three octal digits.

2. Rotate answer left one octal digit.

3. Multiply the right most digit by 4.

Examples

decimal 52 converts to octal 064

rotate left one equals 640

multiply right most digit by 4 equals 640

decimal 71 converts to octal 107

rotate left one equals 071

multiply right most digit by 4 equals 074

The Sense Line Field is useful only with the SSNT instruction. During the SSNT instruction the 8 bits of the field are used as a mask, to indicate which of the sense lines, are to be tested. The LSGA instruction ignores the Sense Line Field.

1.5.3.2 Operation

When the condition of a sense line is required, a SSNT or a LSGA instruction must be used. The SSNT instruction, via its group field, selects a group of 8 sense lines and signals the sense line system to invert their output. The mask of the SSNT instruction is then "and" (ed) with the eight sense lines, and the results checked.

If the results are all zeros, then the Sense lines that were true corresponded with bits of the mask that were true. No action will take place and the program will proceed to the next instruction.

If the result is not zero then the masked and true bits of the sense lines did not match and the program counter will be incremented by one. This will result in the program skipping the next sequential instruction.

The LSGA instruction like the SSNT instruction selects a group of eight sense lines, however, it does not want the 8 lines inverted. Instead it loads the eight lines, as is, into the "A" register of the Central Processor. The eight lines can then be processed in whatever manner the program chooses.

1.5.3.3 Sense Line Assignments

As stated previously Sense lines are assigned to groups, and that certain groups are specified for maintenance. The reason for the maintenance assignment is for routining Sense Group Cards (See section 1.5.4).

The assignments of all implemented signals are as follows:

Maintenance Groups

______________________________________ NUMERIC REPRESENTATION DECIMAL OCTAL ______________________________________ 0 000 8 100 16 200 24 300 32 400 40 500 48 600 56 700 64 004 72 104 80 204 88 304 96 404 104 504 112 604 120 704 ______________________________________

1.5.4 maintenance

1.5.4.1 Tools (Hardware and Software)

For efficiency in routining, 16 CPD instructions were implemented for the Computer Line Processor system.

The CPD instruction for the CLP has the following format. ##SPC34##

The tag field defines address modification (Indexing and indirect addressing are allowed).

The Directive field and a description is as follows. (Octal representation).

000 -- LOCKOUT ALL EXTERNAL SIGNALS

Inhibits all external signals from entering system.

001 -- RESET LOCKOUT

002 -- set test signals true

this simulates a true condition on all external signals that normally enter the system. It does not simulate the signals from the CCP.

003 -- set test signals false

this simulates a false condition on all external signals that normally enter the system. It does not simulate the signals from the CCP.

004 -- reset: control signal errors, pseudo clp cpd signals, gate group signals and gate card signals.

control Signals Errors are:

Cpd clp err 1 sense line 04420

cpd clp err 2 sense line 04440

sync err 1 sense line 04404

sync err 2 sense line 04410

cls cont err 1 sense line 04500

cls cont err 2 sense line 04600

005 -- cls clear:

this signal clears all Sync Hold Storage Elements.

006 -- INHIBIT IS SYNC 1

This CPD will not allow a sync pulse into unit 1 of the CLP. The affect will be a CLS CONT ERR 1 and 2 (sense lines 04500 & 04600).

007 -- INHIBIT IS SYNC 2

This CPD will not allow a sync pulse into unit 2 of the CLP. The affect will be a CLS CONT ERR 2 and 1. (sense lines 04600 & 04500).

010 -- PSEUDO IS SYNC 1 (from CCPA)

This CPD will extend the normally 100 nanosecond IS Sync Pulse into a 500 nanosecond pulse. This will simulate a stuck true condition. The affect will be a SYNC ERR 2 (SENSE LINE 04410) and an inhibit of the IS SYNC 1 signal.

011 -- PSEUDO IS SYNC 2 (from CCPB)

This CPD will extend the normally 100 nanosecond IS SYNC Pulse into a 500 nanosecond pulse. This will simulate a stuck true condition. The affect will be SYNC 2 signal.

012 -- PSEUDO p1 1

This CPD will expand the normal 100 nanosecond P1, from CCPA, to 500 nanoseconds. This will result in a simulated stuck true condition for P1. The affect will be to set SYNC ERR 2 (sense line 04410). The possibility also exists that one or both of the CLS CONT ERR flops will set (sense lines 04500 and 04600).

014 -- SET PSEUDO CLP CPD 1

This storage element will provide a signal that will create a CPD CLP ERR 2 on the next non CPD instruction. It simulates a stuck true condition. The affect will inhibit the CLP CPD 1 signal.

015 -- SET PSEUDO CLP CPD 2

This storage element will provide a signal that will create a CPD CLP ERR 1 on the next non CPD instruction. It simulates a stuck true condition. The affect will inhibit the CLP CPD 2 signal.

016 -- GATE GROUPS

This CPD will set a storage element that will gate the decode of the 7 groups assigned to each card and card 9 onto the sense line bus for use by the CCP during an SSNT or LSGA instruction. The groups are to be selected during the selection of card 16 and card 9 is selected with group 1. This storage element is reset with 004.

017 -- GATE CARDS

This CPD will set a storage element that will gate the decode of the first 8 cards onto the sense line bus for use by the CCP during an SSNT or LSGA instruction. The cards are to be selected along with group 1. This storage element is reset with 004.

1.5.4.2 Operation

1.5.4.2.1 Routining of the Sense Line System requires either both CCP(s) on line or both CCP(s) off line. So that routining will not be interrupted the Interrupt System must be disabled, and all external signals locked out via CCP, 01, 0. A CPD, 01, 02 will place a true signal on all sense lines in all groups except the following Groups 1, 2, 52, 60, 67, 68, 69, 70 and 71. A true signal will be placed on lines 1 thru 6 of group 60, and on lines 1, 2 and 5 and 6 of group 67; by selecting each group via an LSGA or SSNT instruction it can be verified whether the intended result exist. After exercising as stated above the simulated signal can be set to a false condition (CPD, 01, 03) and again the results can be verified as above. Those Sense lines not included in the above test are to be routined individually.

1.5.4.2.2 Routining of the Interrupt System.

With the Interrupt System Disabled, the MIS Instruction RIW (reset interrupt waits) is executed along with 8 BRR (branch return reset) instructions to initialize the interrupt system. The external signals are locked out (CPD, 01, 00) and simulated to a true condition (CPD 01, 02). The MIS instruction ENI (enable interrupts) is executed. Only the Highest Priority level should request servicing. Upon acknowledging the request and with the issue of a BRR instruction the Highest level will be reset and the next highest will request service and this will continue until all interrupts have been serviced in succession. Any deviation indicates a fault, and this fault can be isolated and localized.

1.5.4.2.3 Routining of the Control Circuitry

The CLP receives its control signals from the duplicated CCP(S). The signals are "OR"(ed) together only when the two CCP(S) are on-line. When this condition does not exist then only the on line CCP(S) signals are used. A failure in three of these control signals at point where they are common to both halves of the CLP system could bring the system down therefore hardware to detect such an error is implemented. Hardware controlled by software (CPD instructions) has also been implemented to exercise the error detection circuitry. When such an error occurs (control signal fault) the error detection hardware will lock out the signal from bringing down the system and will set a storage element. A latent fault could also exist in the control signal IS sync within a CLP Power Module that would lock out all external signals to that half of the system. Hardware will detect such a fault and the hardware is exercised via a CPD instruction.

Test one would inhibit a sync pulse in one half of the system and then the other half. (CPD 01, 06 and CPD 01, 07) an error should occur in each instance (CLS CONT ERR 1 and CLS CONT ERR 2).

Test two would simulate the IS sync pulse stuck true first from one CCP and then the other (CPD 010 and CPD 011) in each case the storage elements SYNC ERR 1 and SYNC ERR 2 will be set.

Test three would set storage elements in both halves of the CLP. (CPD 01, 014; CPD 01, 015). These storage elements would simulate the CLP CPD signal stuck true and would be programmed such that first one would be set and tested and then the other. In each case subsequent instruction executions which were other than CPD would set the error storage elements. CPD CLP ERR1 and then CPD CLP ERR 2.

Test four would gate the group decode circuitry outputs on to the Sense Line Bus for monitoring. (CPD, 01, 016). This is necessary to catch a latent fault on the input to the decode circuitry. The use of an LSGA or SSNT instruction can then determine if the correct group is being selected and that only one group is being selected. Group 1 does not exist on a card. SL 1 = group 2; SL2 = group 3; SL3 = Group 4; SL4 = group 5; SL5 = group 6; SL6 = group 7; SL7 = group 8; SL8 = CARD 9.

Test five would gate the Card decode circuitry outputs on to the Sense line bus for monitoring. (CPD 01, 017) As in the case of the group decode, this method is used to catch a latent fault. The LSGA and SSNT instructions can determine if the correct card is being selected and that only one card is selected. SL1 = Card 1; SL2 = Card 2; CL3 = Card 3; SL4 = Card 4; SL5 = Card 5; SL6 = Card 6; SL7 = Card 7; SL8 = Card 8.

Card 9 was placed in group SENSE LINE 8. All faults in the system can be isolated with the tools provided.

The block diagram of FIG. 17 shows the interfacing of the computer line processor CLP with other subsystems for processing of sense line and interrupt signals, for a duplicated system. The computer line processor comprises duplicate units CLP-A and CLP-B. The principal inputs are data sense lines in cables designated DSL. The data sense lines from drum control units DCU-1, DCU-3 and DCU-5 are routed via computer memory control CMC-A to line processor CLP-A; while the data sense lines from drum control units DCU-2, DCU-4 and DCU-6 are routed via computer memory control CMC-B to line processor CLP-B. The data sense lines from the channel multiplex units CCX-A and CCX-B are routed to their respective line processor units CLP-B and CLP-B. The register-senders RS1-A and RS-1B have data sense lines to line processor CLP-A, while RS-1B and RS-2B data sense lines go to CLP-B. There are up to four pairs of originating markers OM-A1 to OM-A4 and OM-B1 to OM-B4. The terminating markers have a pair TM-A1 and TM-B1 for office section 1, a pair TM-A2 and TM-B2 for office section 2, and a pair TM-AS and TM-BS for a selector section. The data sense lines from the markers are cabled through the communication registers CCR-A and CCR-B as shown to the respective line processors CLP-A and CLP-B. There are also data sense lines from the computer central processors CCP-A and CCP-B to the respective line processors CLP-A and CLP-B. Control signal lines from the central processors CCP-A and CCP-B are supplied to the line processors CLP-A and CLP-B. There are also data sense lines from the maintenance routine logic MRL to both line processors CLP-A and CLP-B. The eight merged sense line leads SLφ-7 and address signals are supplied from the line processors CLP-A and CLP-B to the computer central processors CCP-A and CCP-B. Since the computer line processor receives many external signals, and many of these signals are required by the maintenance and control circuit, the specified signals are cabled directly to the maintenance display and control circuit MDC.

Section 1.6 Trap System of the Computer Central Processor

1.6.1 Introduction

The trap system for the Computer Central Processor was devised to handle those events that directly affect the internal operation of the Processor, and to facilitate recovery from programming errors There are two trap levels.

Trap level one third party trap

trap level two computer internal errors

1.6.2 traps: Description, Operation

1.6.2.1 Trap Level One (Third Party Trap)

1.6.2.1.1 Description:

Should a mismatch occur between the duplicated Central Processors, while they are in sync, a Third Trap signal will be initiated by the Third Party Circuitry.

This event is given the highest priority of any event associated with the Central Processor and is assigned to trap level one.

1.6.2.1.2 Operation:

When a Third Party Trap signal is initiated the Central Processor will allow the instruction in process to finish and then process the trap. The Central Processor's timing generator will proceed to cycle three where the trap address will be formed, and used, as an address source. Thus the next instruction read from memory will be located in the address specified. The address of where this trap occurred plus one has been stored in the Last Program count register and last page register. To Store this information a BSP (Branch and Store Last Program Count) instruction must reside in the trap address. No other trap can break in to a program while the Third Party Trap is true. However Interrupts can occur from the Interrupt system, unless a DSI (Disable Interrupt) Instruction is implemented as the first instruction in the trap program.

1.6.2.2 Trap Level Two (Computer Internal Error Trap)

1.6.2.2.1 Description:

Should one of the following events occur in one or both of the duplicated Central Processors, that Processor will initiate an error trap signal.

1.6.2.2.1.1 Instruction Even Parity Error is true when even parity is detected while reading a new instruction from memory.

1.6.2.2.1.2 Data Even Parity Error is true when even parity is detected during the transfer of data from main memory, the Register-Sender or the Channel Multiplexor.

1.6.2.2.1.3 Division by zero is true when during a division instruction the divisor is detected as being all zeros.

1.6.2.2.1.4 Invalid Operation Code is true when the decode of the Instruction operation field detects one of the following invalid Codes. 00; 27; 63.

1.6.2.2.1.5 Memory Reference Time Out is true when one of the memory reference signals remain true for more than 140 microseconds. Memory reference signals are Main Memory read, Main Memory Write; Register-Sender, Read or Register-Sender Write. Reason for failure is signal failure or lack of a feedback from the Main Memory or Register-Sender.

1.6.2.2.1.6 Port 7 error is true when the Central Processor attempts to access memory out of range, or when it attempts to write into "Read Only" memory.

1.6.2.2.2 Operation

When an error trap signal is initiated the Central Processor will abort the instruction in process, from the point of recognition. If a read or write signal to memory is true the abort will be delayed until the signals are removed.

The Central Processors timing generator will proceed to cycle three where the error trap address will be formed and used as the address source.

Note the error trap signal will be ignored if a Third Party trap signal is present.

The address of where this trap occurred plus one has been stored in the Last Program Count register and last page register. To store this information a BSP (Branch and Store Last Program Count) instruction must reside in the trap address.

Interrupts can occur from the interrupt system, unless a DSI (Disable Interrupt) instruction is implemented as the first instruction in the trap program.

The errors that caused the error trap signal as well as the error trap signal itself can be reset by a REI instruction or a master clear. An indication of which error caused the trap resides in the Sense Line system under groups 1 and 2. Refer to section 8.3 for Sense Line Assignments. Should an error signal that would usually initiate an error trap occur, while in the error trap program, the sense line associated with that signal will be the only indication of it being active. Unless, therefore, that signal is scanned after it becomes true, it is possible to lose it when an REI instruction is executed.

Section 1.7 memory protect system

1.7.1 introduction

the Program Protect System of the computer provides hardware protection for Computer Main Memory (CMM). The Program Protect System is activated by releasing the INHIBIT MEMORY PROTECT switch on the Maintenance Display and Control Panel (MDCF). All memory protection is disabled when the Inhibit Memory Protect pushbutton is operated.

Hardware in the Computer Memory Controller (CMC) allows four types of protection for the main memory. The four are: Switch-Protected Read Only Memory, Software- Protected Read Only Memory, Initialization Table Protection and Block Transfer Area (Non-Resident Area) Protection.

1.7.2 Switch-Protected Read Only Memory

This block of words in core may only be written into when the INHIBIT MEMORY PROTECT pushbutton on the MCC is operated (Inhibit position). Protection is in effect both for the Drum Control Units (DCU's) and the computer Central Processor (CCP), regardless of their status.

Bit 25 of each word in this block may be written into when the INHIBIT MEMORY PROTECT pushbutton on the MDCF is operated and the PCROM flip-flop is reset (CPD 012, 066). Bit 25 will be written true if the MIS instruction MPS (03700040) has set the Write Memory Protect Bit (WMPB) storage element. Bit 25 will be written False if the MIS instruction MPR (03700100) has reset the WMPB storage element.

Switch-Protected Read Only Memory is strappable to 512 or 1024 words and may start at location 0 or 512 but does not extend beyond location 1023.

1.7.3 Software-Protected Read Only Memory

Program protection of individual words is available via the 26th bit (Bit 25) of the word as written in core. This protection is in effect for the Central Processor only. Drum Control Units may overwrite Software-Protected Read Only Memory.

The Computer Maintenance Panel (PNL) or the Computer Programming Console (PRC) write through the Central Processor and therefore protection is in effect for these units. Software Protection, Bit 25 written True in core, may be applied to any location in core. Protection however is redundant in Switch-Protected Read Only Memory. A Software Read Only Memory Error will be generated when trying to write into a software-protected location in Switch-Protected Read Only Memory.

When the Program-Controlled Read Only Memory (PCROM) Active FF is set and the INHIBIT MEMORY PROTECT pushbutton has not been operated (Memory Protect System "ACTIVE" state) the Central Processor, PNL or PRC can write into all core locations except Switch Protected Read Only Memory. Bit 25 will be written into Core as a One if the WMPB flip-flop is set or as a Zero if WMPB flip-flop is reset. If the PCROM Active flip-flop is reset and INHIBIT MEMORY PROTECT pushbutton has been operated (Memory Protect System `INHIBITED` state) the CCP, PNL or PRC can write into any core location.

When the INHIBIT MEMORY PROTECT pushbutton has been operated (Memory Protect System "Inhibited" state) the CCP can write into any core location. However if the PCROM Active flip-flop is set and the Central Processor writes into core, Bit 25 in core will always be written as Zero regardless of the state of WMPB and correct parity will be provided by CMC.

The PCROM Active flip-flop is a S/R latch located in the Computer Memory Controller. The state of this latch is controlled by CPD instructions and can be interrogated via sense line. The PCROM Active latch is reset ("inactive state") by CLEAR.

1.7.4 initialization Table Protection

A 64-word block of main memory is dedicated to each DCU as its initialization table. When a DCU is being initialized (Init lead to CMC True) it may access only its own initialization table. Otherwise a DRUM TABLE ERROR occurs and write operation is aborted.

A DCU may write into another DCU's initialization table only when it is "privileged," i.e., its PT lead to the CMC is true.

In summary, a DCU may access only its own initialization table when it is in the initialization sequence and a DCU may not write outside of its own initialization table or the Block Transfer Area unless it is privileged or the INHIBIT MEMORY PROTECT pushbutton is operated. All DCU initialization tables are contiguous within a 512-word block of main memory. The starting location of the first DCU (DCU1) Initialization Table is strapped to the last word (word 511) of the 512-word initialization tables block minus (n + 1) × 64, where n = 2,4,6 is the TOTAL number of DCU's attached to the CMC. In this way the DCU Initialization Tables occupy the highest-numbered addresses in the 512-word block leaving the last 64 words at the end of the block for other usage (trap and interrupt addresses). The 512-word block may be strapped in increments of 512 words to any location in core. However the trap and Interrupt addresses generated by CCP are not relocatable.

1.7.5 Block Transfer Area Check

With initialization Table Protection this check may be considered to be `Bound Checking` on DCU access to main memory. A DCU may not write outside of its own initialization table or the Block Transfer Area ("non-resident" Area) unless it is privileged. If a DCU attempts to write outside these areas a DRUM TABLE ERROR will be generated and write operation will be aborted. A DCU which is privileged may write in any core location except Switch Protected ROM. When the INHIBIT MEMORY PROTECT button is operated any DCU may write in any location in core.

Section 2.0 main Memory and Drum Control

2.1 Main Memory

2.1.1 Introduction

The CMC (Computer Memory Control) can best be thought of as a bi-directional multiplex - distributor such that any of the units at the ports can transfer data to any memory bank in main memory and data from any memory bank can be transferred to any port on a one-transfer-at-a-time basis. FIG. 18 shows the maximum configuration of Drum Control Units, Central Processors and CMC's in a No. 1 EAX office. Smaller offices may have only 2 or 4 DCU's (Drum Control Units). DCU's are supplied in redundant pairs.

2.1.3 Operational Description

The CMC operates on a request acknowledge basis. If no requests are presented by the Drum Control Units or the Central Processor the CMC and the core memories are idle. The Central Processor is pre-selected as the Address Bus Source at the end of each memory request and remains pre-selected if no requests are presented to the CMC. This enables accelerated access to main memory by the CCP. If a DCU request is presented to CMC a 350 ns timer is started to allow selection of the port making the request and to allow the address to propagate to the bank selection circuitry and to the memory banks. At the end of the 350 ns delay if all main memories have finished their previous requests a Start Read command is issued to the main memory bank specified by the address bits supplied by the requesting port.

The memory bank will return a Memory Busy signal and after the word at the address specified has been read it will return a Data Available signal and the data read at the address. On a read request, a data available signal and the data, will be returned to the port within 1.0 microseconds after the request was received. On a read request, the CMC will send a Restore Control signal to the memory and the word read from memory will be written back in. On a write request at the end of the data available signal the CMC will send to the memory bank the data to be written into the location.

After the data is written into the data register of the memory it will return a Data Loaded signal to the CMC and the CMC will return a Data Loaded signal to a port having a write request. After the data word has been written into memory and another memory cycle can be initiated the Memory Busy signal will go false. The memory will also return an END of Cycle signal which is used for timing in the CMC.

The CMC has seven ports of which up to six DCU's and the CP will be connected. Simultaneous memory requests are resolved by a predetermined priority assignment to each port. Port 1 has the highest priority, port 2 has the next highest and so on to port 7. The Central Processor is assigned to port 7 due to the inability of the DCU's to wait for any extended period. Service of one memory request is always completed before another is started. The next request to be serviced is always the one of highest priority in the queue.

The port selection to determine which request will be answered can be made while the previous request is being completed.

Failure of a port to remove a read request or write request after it is answered will result in a Port Request Time-Out Error. Any error which occurs while a port is accessing the memory will cause the port to be locked out except for the CP, which is never lockout. Also a read request or write request must be removed before the next memory request from that port can be recognized.

The time required for the Data Available signal to be sent to a port after a read request is received varies from 0.8 microseconds to (1.0 + 1.8N) microseconds where N is the number of the port in the queue. The Data Loaded signal is sent to port N1.4 to (1.6 + 1.8N) microseconds after the write request is received.

A word is read from the magnetic drum of the Drum Memory system once every 1.5 to 1.63 microseconds and since the words on the drum have an interlace of five this means that the maximum time the DCU can wait for a Data Loaded signal after a write request goes out is 7.5 microseconds. If four DCU's present read requests or write requests to the CMC at a time when the CMC is answering a memory request from the CP, then one of the DCU's may not have its request answered in the time necessary and its CORE ACCESS TROUBLE sense line to Computer Line Processor will go true. The DCU will remove its write or read request and if it does not receive a malfunction indication from the CMC a DCU TIME OUT interrupt will be generated 8 drum revolutions (approximately 136 milliseconds) after a request was first sent to the DCU.

When the CMC's are running in sync the port selections of the two CMC's must agree before a port can be selected. When a memory request appears a 350 ns delay, Delay 1, will be started to allow port selection to take place. At the end of Delay 1 a comparison will be made to see if the port selections agree. If another memory request was being answered when the memory request appeared, Delay 1 will not start until 150 ns after the fall of the Data Available signal from the first request.

If two ports presented read requests at the same time it would be possible for the two CMC's to select different ports. When at the end of Delay 1, the port selections did not agree, a second delay, Delay 2, of 150 nanoseconds would be started and at the end of it a retry at port selection can be made. After the third retry a port will be selected regardless of whether the port selections compare. If three retries have been made and the port selections do not agree an error interrupt will be generated and the PORT SELECT RETRY ERROR sense line will go to the one state. Any write operations will be aborted to a read operation and the Abort write sense line will become true. Each retry adds a maximum of 614 ns to the time required for port selection so that if three retries are made, the third DCU will receive a Data Loaded signal within 7042 ns which is within the 7500 ns maximum required to guarantee that the DCU does not encounter port blockage.

2.1.3 Status Indicators and Interrupts

Besides the data return leads the following outputs from the CMC are connected directly to the CP to indicate the status of the CP's read requests and write requests.

______________________________________ LEAD DESCRIPTION REMARKS AND TIMING ______________________________________ DATA AVAILABLE Indicates that data is being read from main memory. Becomes true 0.8 to (1.0 +1,8N) μs after read request becomes true and remains true for as long as read request is true. DATA LOADED Indicates that data has been written into main memory. Becomes true 1.4 to (1.6+1.8N) .about.s after write request becomes true and remains true for as long as write request is true. PROGRAM ERROR Indicates that the CP caused an Address Out of Range, attempted Read Only Memory Write or Protected Location Write malfunction during main memory access. Becomes true 0.3 to (2.2+1.8N) μs after read request or write request becomes true. Reset by REI or CLR. Causes a CP level 2 trap. COMPARE ERROR Indicates that a mismatch was detected between the two CMC's. Causes a Computer Third Party trap. ______________________________________

The only interrupts assigned to the CMC's are CMC 1 Error and CMC 2 Error in interrupt level 2 with octal sense line numbers 73002 and 73020 respectively. The following sense lines are assigned to the CMC's:

COMPUTER MEMORY CONTROL: GROUP 53 ______________________________________ OCTAL SENSE LINE NO. SENSE LINE NAME SENSE LINE DESCRIPTION ______________________________________ 65001 PAICEST 1 Port Address In Compare Error Stored. The Addresses supplied by the port are different in the two CMC's. 65002 PDICEST 1 Port Data In Compare Error Stored. The Data words supplied by the port are different in the two CMC's 65004 PAIPEST 1 Port Address in Parity Error Stored The address supplied by the Port has even parity. 65010 PDIPEST 1 Port Data In Parity Error Stored The data word supplied by the port has even parity. 65020 PINVCIEST 1 Port Invalid Control In Error Stored The port has made an invalid request for service. 65040 RTRYEST 1 Retry Error Stored The CMC's have made 3 port select retries and the port selections still do not match. 65100 PTOEST 1 Port Time Out Error Stored The port has not removed its read or write request after it was answered. 65200 CMC PROT SYSTEM ACT 1 The memory protection system has not been disabled by the switch on the control panel. COMPUTER MEMORY CONTROL: GROUP 54 ______________________________________ 66001 SYNCTOST 1 Sync Time Out Stored The two CMC's have fallen more than 800 nanoseconds out of synchronization. 66002 MARCEST 1 Memory Address Return Compared Error Stored The addresses returned from the memories associated with the two CMC's do not compare. 66004 MDRRCEST 1 Memory Data Return Read Compare Error Stored The words read from the two memories do not compare. 66010 MDRWCEST 1 Memory Data Return Write Compare Error Stored The data words returned from the memories on the write portion of the cycle do not compare. 66020 MARPEST 1 Memory Address Return Parity Error Stored The address returned by the memory has even parity. 66040 MDRWPEST 1 Memory Data Return Write Parity Error Stored The data returned from memory on the write portion of the cycle has even parity. 66100 MINVCREST 1 Memory Invalid Control Return Error Stored The control signals returned from memory are invalid. 66200 BSRCEST 1 Bank Select Register Compare Error Stored The bank selections of the two CMC's do not agree. COMPUTER MEMORY CONTROL: GROUP 55 ______________________________________ 67001 BSMR[0]1 Bank Select Malf Reg. These leads indicate the bank which was selected when the first error occurred. 67002 BSMR[1] 1 67004 ABORT WRITE 1 A core write transfer has been aborted to a READ/MODIFY/WRITE or core read operation. 67010 PCIMR[RR] 1 Port Control in Malf Reg. These leads contain the state of the Port Control In leads when the first error occurred. 67020 PCIMR[WR] 1 67040 PCIMR[RMPB] 1 67100 PCIMR[PT] 1 67200 PCIMR[INIT] COMPUTER MEMORY CONTROL: GROUP 57 ______________________________________ 71001 AOREST 1 Address Out of Range Error Stored The address exceeds the range of memory used. 71002 ROMEST 1 Read Only Memory Error Stored The port has tried to write into read only memory. 71004 CROSS WRITE ACTIVE FF SET Cross Write configuration has been achieved. 71010 DTEST 1 Drum Table Error Stored A DCU has tried to read or write outside of its initialization table while in the initialization sequence or write outside of its initialization table and outside of the block transfer area while it was not privileged. 71020 PSMR[0] 1 Port Select Malf Reg. These leads carry the binary-encoded number of the port selected when the first error occurred. 71040 PSMR[1] 1 71100 PSMR[2] 1 71200 PSMR[3] 1 COMPUTER MEMORY CONTROL: GROUP 58 ______________________________________ 72001 PMALFR[1] 1 Port Malfunction Register 72002 PMALFR[2] 1 An error has occurred while 72004 PMALFR[3] 1 this port was selected. 72010 PMALFR[4] 1 72020 PMALFR[5] 1 72040 PMALFR[6] 1 72100 CCP PMALFR 1 72200 PMALFR[8] COMPUTER MEMORY CONTROL: GROUP 59 ______________________________________ 73001 PC ROMEST 1 Program Controlled Read Only Memory Error Stored. The CCP has tried to write into program controlled read only memory. 73002 CMC ERR ST 1 The CMC has detected one of the errors listed here. 73004 MDRRPEST 1 Memory Data Return Read Parity Error Stored. The data word read from memory has even parity. 73010 PC ROMACT 1 Program Controlled Read Only Memory Active Read only memory protection is in effect for the program controlled read only memory selection. 73020 PC ROMEST 2 Same as 73001 73040 CMC ERR ST 2 Same as 73002 73100 MDRRPEST 2 Same as 73004 73200 PC ROM ACT 2 Same as 73010 COMPUTER MEMORY CONTROL: GROUP 61 ______________________________________ 75001 PAICEST 2 75002 PDICEST 2 Similar to Group 53 75004 PAIPEST 2 75010 PDIPEST 2 75020 PINVCIEST 2 75040 RTRYEST 2 75100 PTOEST 2 75200 CMC PROT SYST ACT 2 COMPUTER MEMORY CONTROL: GROUP 62 ______________________________________ 76001 SYNCTOST 76002 MARCEST 2 Similar to Group 54 76004 MDRRCEST 2 76010 MDRWCEST 2 76020 MARPEST 2 76040 MDRWPEST 2 76100 MINVCREST 2 76200 BSRCEST 2 COMPUTER MEMORY CONTROL: GROUP 63 ______________________________________ 77001 BSMR[0] 2 77002 BSMR[1] 2 Similar to Group 55 77004 ABORT WRITE 2 77010 PCIMR [RR] 77020 PCIMR[WR] 2 77040 PCIMR[RMPB] 2 77100 PCIMR[PT] 2 77200 PCIMR[INIT] 2 COMPUTER MEMORY CONTROL: GROUP 65 ______________________________________ 01401 AOREST 2 01402 ROMEST 2 Similar to Group 57 01404 CROSS WRITE ACTIVE 2 01410 DTEST 2 01420 PSMR[0] 2 01440 PSMR[1] 2 01500 PSMR[2] 2 01600 PSMR[3] 2 COMPUTER MEMORY CONTROL: GROUP 66 ______________________________________ 02401 PMALFR [1] 2 02402 PMALFR [2] 2 Similar to Group 58 02404 PMALFR [3] 2 02410 PMALFR [4] 2 02420 PMALFR [5] 2 20440 PMALFR [6] 2 02500 CCP PMALFR 2 02600 PMALFR [8] 2 ______________________________________

2.1.4 data and Instruction Formats

Besides the data bus and address bus the following inputs are provided to the CMC from the CP.

______________________________________ Input Description ______________________________________ READ REQUEST Becomes true to read main memory. WRITE REQUEST Becomes true to write into main memory. SYSTEM MEMORY MP STAT is alway true unless the Disable PROTEST STATUS Memory Protect Switch on the Maintenance Control Panel is operated. RESET ERROR INDICATORS REI becomes true during the execution of an REI instruction. MASTER CLEAR CLR is always false unless the computer test panel is plugged in and the MASTER CLEAR Push button is depressed or the THIRD PARTY CLEAR signal becomes true to clear a CCP. CONTROL PULSE DIRECTIVE Control Pulse Directive is a signal for CMC to interpret data bus bits 0 to 8. CCP ON LINE The CP is on-line. ______________________________________

Control pulse directives from the CP are used to set or reset Maintenance registers in the CMC. Which register receives a pulse is determined by data bus bits 0 to 8 and the register is set if bit 0 is a one and reset if it is a zero. The registers which are set or reset by a control pulse directive and the various combinations of bits 0-8 on the data bus are given in the following list.

CMC Control Pulse Directive ____________________________________________________________ ______________ Data Bus Octal No. Action Description of Register ____________________________________________________________ ______________ 000 MCLTR{MB}-RST Memory Control Logic 001 MCLTR{MB}-SET Test Register {Memory Busy} MCLTR simulates a memory request from a port and the control signals returned from the memory to test CMC control logic. 002 MCLTR{DA} RST MCLTR {Data Available} 003 do. SET 004 MCLTR{DL} RST MCLTR {Data Loaded} 005 do. SET 006 MCLTR{EOC}RST MCLTR {End of Cycle } 007 do. SET 010 MCLTR {MREQ}RST MCLTR {Memory Request} 011 do. SET 012 MMDBSOCR{1}RST Maintenance Memory 013 do. SET Data Bus Source 014 MMDBSOCR{2}RST Control Register 015 do. SET By setting MMDBSOCR{1} 016 MMDBSOCR{3}RST {2} {3} the test points 017 do. SET previously listed will be connected to the data bus if the CP is off-line 020 PENTR{1} RST Port Enable Test Register 021 " SET {1 - 6} 022 PENTR{2} RST PENTR enables the CMC 023 " SET to answer a memory 024 PENTR{3 } RST request from an off-line port 025 do. SET if the CP is off-line 026 PENTR{4} RST 027 do. SET 030 PENTR{5} RST 031 do. SET 032 PENTR{6} RST 033 do. SET 034 POLR{1} RST Port On Line Register {1 - 6} 035 do. SET POLR controls the on-line 036 POLR{2} RST status of the six DCU's 037 do. SET attached to ports 1 to 6. 040 POLR{3} RST The POLR's of a DCU must be 041 do. SET reset in both CMC's before 042 POLR{4} RST an off-line indication is 043 do. SET given to that DCU. POLR is 044 POLR{5} RST also reset by the MASTER 045 do. SET CLEAR button on the computer 046 POLR{6} RST test panel. 047 do. SET 050 INPUT TEST Input Test Register {1-6} REG {1} RST 051 INPUT TEST REG {1} SET 052 INPUT TEST used to test the signal paths REG {2} RST from the DCU's to the CMC's 053 INPUT TEST When an input test register REG {2} SET is set all the inputs to the 054 INPUT TEST CMC's from that DCU should REG {3} RST be true. 055 INPUT TEST REG {3} SET 056 INPUT TEST REG {4} RST 057 INPUT TEST REG {4} SET 060 INPUT TEST REG {5} RST 061 INPUT TEST REG {5} SET 062 INPUT TEST REG {6} RST 063 INPUT TEST REG {6} SET 064 MCLTR{LCH-MDB}RST Memory Control 065 do. SET Logic Test Register {Latch Memory Data Bus} If the CP is off-line setting MCLTR{LCH-MDB} latches the data bus so that a one applied to the data bus remains on the data bus after the input is removed. 066 PC ROM ACT-RST Program Controlled 067 PC ROM ACT-SET Read Only Memory Active. Setting this register enables the program controlled read only memory protection. 076 CROSS WRITE-RST 077 CROSS WRITE-SET Cross write enables an on-line CCP to write into its own memory and the duplex memory which must be off ____________________________________________________________ ______________ line.

2.1.5 Configuration

The configuration of ports enables to access main memory is software controlled. Two registers are provided in the CMC for control of the ports. One bit in each register is assigned to each port. For a DCU to access an `On Line` main memory (i.e CCP ON LINE signal from CCP to CMC true) its associated bit in the Port On Line Register (POLR 1-6) must be true. For the port to access an Off Line main memory (the CCP ON LINE signal from CCP to CMC false) its associated bit in the Port Enable Test Register (PENTR 1-6) must be true. Bits of the POLR and PENTR are individually set by CPD instructions. Bits of the POLR and PENTR are individually reset by CPD instructions and both registers are reset to all zeros by CLEAR. The status of the POLR and PENTR are available for interrogation on Maintenance Memory Data Bus Source word 3. See Section 2.1.4.

The status of Port 7 and Port 8 is under control of the Cross Write feature, refer to section 2.1.6.

2.1.6 Maintenance Features

2.1.6.1 Error Detection

A list of errors detected by the CMC and their description appears under CMC sense lines. Certain of these errors cause the CMC to take immediate action.

All errors will cause the following actions. The port which was accessing main memory will be blocked from any further access until REI or CLEAR is received from the CCP. The CCP (PORT 7) is only blocked if it does not remove its memory request after the request is answered. Other errors do not block Port 7.

The Port Selected Malfunction Register (PSMR) is set indicating via sense line which port was accessing memory when the error occurred. The Bank Selected Malfunction Register (BSMR) set indicating via sense line which bank of main memory was selected when the error occurred. The Error Stored Flop and Disable Error Load Flop (ESF and DERLF) are set. DERLF will prevent any subsequent errors from changing the value of PSMR or BSMR and will prevent any subsequent errors from changing the error indicators to the CLP. DERLF will cause subsequent errors to be ignored by the CLP until the first error is reset by REI or CLEAR from CCP.

If DERLF (disable error load flop) is set, a THIRD PARTY TRAP can be caused by Synchronism Time Out (SYNCTOF) only, and an ERROR TRAP can be generated.

In addition to the above any error will cause its associated sense line to become true if DERLF was not previously set and to remain true until REI or CLEAR is issued to CMC by CCP.

The following errors will cause an Error Trap if they occur while the CCP is accessing main memory:

Read Only Memory Error (Switch protected)

Address Out of Range Error

Program Controlled Read Only Memory Error (25th bit protected words).

The following errors will cause a Third Party Party Trap when both CCP's are On Line only:

Bank Selection Comparison Error

Memory Address Returned Comparison Error

Memory Data Returned Read Comparison Error

Memory Data Returned Write Comparison Error

Port Address In Comparison Error

Port Data In Comparison Error

Retry Error (Port selection does not compare after three retries)

Synchronism Time Out Error

A Third Party Trap is not generated by a miscomparison during Cross Write. The associated sense line to CLP does become true.

To protect the integrity of information in memory the following errors will generate a Restore Control Signal to Main Memory and thus abort a write operation. If these errors occur during a write operation a sense line to CLP, Abort Write, will become true:

Read Only Memory Error (Switch Protected)

Port Invalid Control In Error

Bank Select Comparison Error

Port Address In Compare Error

Port Address in Parity Error

Address Out of Range Error

Retry Error

Drum Table Error

Software Protected Read Only Memory Error.

2.1.6.2 Program Controlled Read Only Memory

A set-reset latch in CMC is provided to activate 25th bit read only memory protection. (See section 1.7.3, Software Protected Read Only Memory for the operational description of this latch.)

2.6.3 Maintenance Data Bus Source

The status of internal points in the CMC may be interrogated by returning these points to the CCP on the Data Bus. When a CCP is OFF LINE it is connected as a sink to the CMC Data Bus. (This is also true during Cross Write).

By execution of the associated CPD instruction in the ON LINE CCP the following three words describing the status of control points may be placed on the Data Bus of the off line CMC and thus onto the Data Bus of the off line CCP.

Mmdbsocr{1}

________________________________________________________ __________________ data Bus Bits Test Point Description ____________________________________________________________ ______________ 0-17 MAB (0-17) MEMORY ADDRESS BUS (0-17) The address bus of the CMC may be the address in from port or the address returned for the last Memory Bank accessed. 18-23 POLR (1-6) PORT ON LINE REGISTER (1-6) The on-line status of the DCU's. 24 DATA BUS (0-25) causes MMDBSOCR{1} to be EVEN PARITY sent to CCP with odd parity 25 EG Logic 0 MMDBSOCR {2} 0 EG Logic 0 1 ROMF READ ONLY MEMORY FLIP-FLOP The last Address in accessed Switch Protected Read Only Memory 2 DIIITF DRUM IN ITS INITIALIZATION TABLE FLIP-FLOP The last request was from a DCU for a word in its initialization table. 3 DOBTAF DRUM OUTSIDE BLOCK TRANSFER AREA FLIP-FLOP The last request was from a DCU which accessed a location outside of the Non-Resident area. 4 PCIR{RMPB} PORT CONTROL IN REGISTER {RETAIN MEMORY PROTECT BIT} The last request was from CCP and Software Read Only Memory Pro- tection was in effect. 5 PCIMR{RMPB} PORT CONTROL IN MALFUNCTION REGISTER {RETAIN MEMORY PROTECT BIT} Same as above when an error occurred. 6 MARGIN SW OFF NOR MARGIN SWITCH OFF NORMAL One of the Power Supply Level switches on one of the Main Memories is oper- ated to the `high` or `low` position. 7 MDRREPF MEMORY DATA RETURNED READ EVEN PARITY FLIP FLOP Even parity on the word returned from Main Memory during a ready cycle. 8 MDIEPF MEMORY DATA IN EVEN PARITY FLIP FLOP Even Parity on the word supplied by the port during a write cycle. 9 MDRWEPF MEMORY DATA RETURN WRITE EVEN PARITY FLIP FLOP Even parity on the word returned from Main Memory during a write cycle (will also become ture if MDRREPF is true) 10 DERLF DISABLE ERROR LOAD FLIP FLOP No further errors will be stored until REI or CLEAR is issued by CCP. 11 RTRY3F RETRY 3 FLIP FLOP 3 attempts have been made at port selection and port selection does not compare. 12 MDF{25}F MEMORY DATA BIT {25} STORED The status of bit 25 in the last core location accessed. 13 -PH0 PHASE 0 (inverted) A CMC internal timing pulse occurring while CMC is idle. 14 -PH1 PHASE 1 (inverted) A CMC internal timing pulse occurring where a memory request is received and before a Start Read is issued to Main Memory. 15 PH2 PHASE 2 A CMC internal timing pulse occurring while Start Read to Main Memory is true. 16 PH3 PHASE 3 A CMC internal timing pulse occurring after Start Read to Main Memory is issued and before Data Available is returned. 17 PH4 PHASE 4 A CMC internal timing pulse occurring while Data Available returned from Main Memory is true. 18 -PH5 PHASE 5 (inverted) A CMC internal timing pulse occurring during a 150 ns monopulser which is triggered at the falling edge of the Data Available signal returned from Main Memory. 19 -PH6 PHASE 6 (inverted) A CMC internal timing pulse occurring from the end of Phase 5 until the Data Loaded signal is returned from Main Memory 20 PH7 PHASE 7 A CMC internal timing pulse occurring while the Data Loaded signal is returned from Main Memory. 21 -PH8 PHASE 8 (inverted) A CMC internal timing pulse occurring from the fall of the Data Loaded signal until the End of Cycle signal returned from main memory. 22 -PH3 & PH4 PHASE 3 or PHASE 4 (inverted) 23 -PH5 & PH6 PHASE 5 or PHASE 6 (inverted) 24 Data Bus (0-25) Causes MMDBSOCR (2) Even Parity to be returned to CCP with odd parity 25 EG LOGIC 0 MMDBSOCR {3} 0 PCIR{RR} PORT CONTROL IN REGISTER {READ REQUEST} The last memory request presented by a port was a read request. 1 PCIR{WR} PORT CONTROL IN REGISTER {WRITE REQUEST} The last memory request presented by a port was a write request. 2 PCIR{PT} PORT CONTROL IN REGISTER {PRIVILEGED TRANSFER} a. The last request was from a DCU which was allowed to access a location outside of its initiali- cation table and outside of the block transfer area, because the Privileged Transfer lead from that DCU was true at the time of the request. b. The last request was from the CCP and Program Controlled read only memory protection was disabled. 3 PCIR{INIT} PORT CONTROL IN REGISTER {IN INITIALIZATION TABLE} The DCU INIT lead from the last DCU to make a memory request was true indicating that the DCU was attempting to access its initiali- zation table. 4 START READ The START READ command to Main (11,12) Memory Bank one from CMC (inverted) 5 START READ The START READ command to Main (21,22) Memory Bank two from CMC (inverted) 6 START READ The START READ command to Main (31, 32) Memory Bank three from CMC (inverted) 7 START READ The START READ command to Main (41,42) Memory Bank four from CMC (inverted) 8-13 PENTR (1-6) PORT ENABLE TEST REGISTER (1-6) The associated port is enabled to access CMC when the CCP is off line. 14 ACKR{1}+ACKR{2} ACKNOWLEDGE REGISTER 1 or 2 or 3. + ACKR{3} A Data Available signal has been returned to a port and that port's memory request remains true. 15 ACKR{4}+ ACKR{5} ACKNOWLEDGE REGISTER 4 or 5 + ACKR{6} or 6. 16 ACKR{7}+ ACKR{8} ACKNOWLEDGE REGISTER 7 or 8 + ACKR{9} 9 17 MAR EPF MEMORY ADDRESS RETURNED EVEN PARITY FLIP FLOP The address stored in the address return buffer register has even parity. 18 AORF ADDRESS OUT OF RANGE FLIP FLOP The address supplied with the memory request was for a location outside of the available core. 19 PAIEPF PORT ADDRESS IN EVEN PARITY FLIP FLOP The address supplied with a memory request had even parity 20 PAICF PORT ADDRESS IN COMPARISON FLIP FLOP The address supplied by a port to both CMC's while running in synchro- nism did not compare. 21 MEM ADD RTRN MEMORY ADDRESS RETURN COMPARE FLOP COMPARISON FLIP FLOP The address stored in the address return buffer registers of Main Memory attached to CMC-A and that attached to CMC-B did not compare. 22 PAI{17} PORT ADDRESS IN BIT 17 FLIP FLOP Indicates the parity bit of the address supplied with the last memory request. 23 RESTORE RESTORE CONTROL signal instructing CONTROL Main Memory to change from a R/M/W to a R/M/W cycle. 24 DATA-BUS {0-25} CAUSES MMDBSOCR{3}to be sent to EVEN PARITY CCP with odd parity. 25 EG LOGIC 0 ____________________________________________________________ ______________

2.1.6.4 memory Control Logic Test Register

An OFF LINE CMC may be stepped through a simulated memory cycle by executing CPD instructions in the ON LINE CCP. In this manner the ON LINE CCP may simulate:

1. A Memory Request via the MCLTR{MREQ} set CPD

2. memory Busy signal from Main Memory via the MCLTR{MB} set CPD

3. data Available signal, MCLTR{DA}

4. data Loaded signal, MCLTR{DL}

5. end of Cycle signal, MCLTR{EOC}

If the proper sequence of set and reset CPD's are executed the CMC will simulate a complete memory cycle. Note that the CMC under test must be OFF LINE and the other CCP which executes the test must be ON LINE.

2.1.6.5 input Test Register

A bit set `true` in the Input TEST REGISTER, INPTR{1-6} will cause the inputs from the associated DCU to CMC to become true. This does not include the eight DCU sense lines which are passed through CMC.

INPTR{1-6} are set and reset in CMC by CPD instructions executed in the CCP associated with that CMC. All bits of INPTR are reset by CLEAR.

2.1.6.6 cross Write

A maintenance feature is incorporated into the CMC's which enables an on line CCP to refresh an off line core main memory directly from the on line copy of main memory. Once the CMC's are in the Cross Write Active configuration one CCP may independently refresh all locations in main memory by merely repeating a two instruction loop; LOAD A, STORE A. Note that all memory protection features remain in effect in the on-line CMC during a cross write operation. During cross write Program Controlled Read Only Memory protection is disabled in the off-line CMC. Thus the on line CCP will write over 25th bit protected words in the off line memory. (ref. sect. 1.7).

Cross Write may only be employed by an on-line CCP and the memory being refeshed must have its associated CCP off line. If both CCP's become either on line or the configuration is reversed by the Third Party, Cross Write Configuration is immediately lost and must be entirely reinitiated. If both CCP's become off-line Cross Write remains Active.

During Cross Write, the DCU's may be active when Cross Write is initiated and during cross write. Since the DCU's can access the on line, main memory it is necessary to also allow them access to the off-line memory. This insures that the off-line memory is updated by any DCU to main memory transfer which occurs during a cross write.

The duplex CMC's are configured to Cross Write Active state by means of master-slave storage elements. The master is loaded at the time the on-line CCP issues the SET CROSS WRITE CPD.

The slave is not set until both CMC's become idle. Note that setting CROSS WRITE ACTIVE requires a re-synchronization of the CMC's. If 3 DCU's request access to the on line main memory at the time CCP tries to set Cross Write a worst case maximum of 7.0 μsec. could elapse between the SET CROSS WRITE CPD and the achievement of Cross Write Active configuration. A sense line is provided indicating CROSS WRITE ACTIVE.

Once Cross Write Active configuration is achieved the on line CCP is enabled by the Cross Write Active Flop to access the off line CMC through Port 8 (Port 8 is connected to Port 7 of the duplex CMC unit via backplane wiring). In the off line CMC Port 7 is blocked to insure that the off line CCP can not interfere with actions of the on line CCP. CPD instructions from the off line CCP are allowed access to the off line CMC during Cross Write. To insure that both CMC's will be available for transfers during Cross Write Active the CMC's are run in synchronism. Because they are in sync the following comparisons are made:

i. Port Address in

ii. Port Data in

iii. Memory Address returned

iv. Synchronism Time Out

v. Bank selection Comparison

vi. Port Selection Retry Error

The memory data returned is not compared as it is not expected to compare during Cross Write. The above mismatches are available on sense lines for interrogation. The CMC MISMATCH signal however is DISABLED during cross write as this signal is used to generate a THIRD PARTY trap.

Data and control signals are returned to the CCP from the on-line main memory (via CMC) only during CROSS WRITE. DATA LOADED is returned to the on-line CCP by the on-line CMC only after DL is returned to the CMC by BOTH memories. Control signals are returned to the DCU's from both CMC's but DATA is returned to the DCU's only from the on-line CMC.

All error detection circuitry in both CMC's with the exception of Memory DATA (READ and WRITE) RETURNED COMPARISON ERROR remains active during CROSS WRITE.

Two means of exit (other than system master CLEAR) from cross write are available:

1. Execution of RESET CROSS WRITE CPD. In this case the same sequence of events occurs as does when entering cross write. The CROSS WRITE ACTIVE (SLAVE) latch is not reset until both CMC's are idle. When Cross Write Active flop becomes reset the DCU's will not have access to the off line CMC unless their associated PENTR's are set.

2. Bring the off-line CCP back on line. This causes immediate resetting of Cross Write Active Flop. The DCU's will now be enabled to both CMC's by the CCP ON LINE signal if their associated POLR's are set.

In summary the steps required to enter CROSS WRITE ACTIVE configuration are:

1. One CCP must be on-line, one CCP must be off-line.

2. The Port On Line Register (POLR 1-6) of the off-line CMC must be equal to the POLR of the on-line CMC.

3. Issue SET CROSS WRITE CPD to the on-line CMC by execution of the associated CPD instruction in the on-line CCP.

4. Sense for CROSS WRITE ACTIVE sense line true.

5. When CROSS WRITE ACTIVE sense line is true begin reading the on-line core main memory and writing both memories with the STA, STQ, etc. instruction executed in the on-line CCP only.

To exit from Cross Write

1. System Clear in the off-line CCP. Subsequent DCU transfers will not effect the off-line CMM.

2. Issue Reset Cross Write CPD and sense for Cross Write Active sense line false. DCU transfers will now be lost unless the Port Enable Test Register (PENTR 1-6) in the off-line CMC is equal to the POLR of the on-line CMC.

3. Bring the off-line CCP back on-line. No DCU transfers will be lost as long as the POLR in the off-line CMC has been left set.

Section 2.2 drum memory

2.2.1 introduction

drum memory is used as storage area for the programs and data that do not require "immediate" access by the central processor. Drum Memory information is readout of and written into main memory under control of a Drum Control Unit (DCU) via the Computer Memory Control (CMC) circuit. Each DCU is assigned a specific port, in the CMC. These ports are numbered 1 through 6 and are assigned a priority. Port 1 having a higher priority than port 2 and so on down to port 6 with the lowest priority of DCU's. The central Processor has port 7 assigned to it and attains the least priority. Each DCU can control an entire drum of 18 segments or one half a drum (9 segments). Thus a maximum of 6 drums could be handled. Each drum segment contains 10,999 words of 27 bits each.

The writing into and reading out of drum must be accomplished when the Drum is ready. Failure to do so will create an error. A word can be read out of, or written into memory every 1.6 microseconds. If more than one Drum, or a Drum and the CCP wished to access memory, transactions in the Drum area would be lost, or the CCP would not get a change to access memory. In order to avoid this the drums are handled at an interlace rate of 5. This means that successive Drum locations to be read or written into are actually spaced every five locations. Thus when a drum reads from memory, it will not be ready to read again until 8 microseconds later. Thus one Drum will not hog memory. With this interlace, three Drums and a CCP can be running simultaneously without loosing drum and yet allowing the processor to access memory at least once for every three separate Drum transactions. If a fourth Drum is accessed, the CCP may get locked out for a longer length of time or conceivably until one of the drums stops processing. As a Fifth Drum is added the possibility of locking out the CCP becomes more prevalent. The loss of transactions on a drum are also possible. Simultaneous use of a sixth drum exaggerates the problem.

2.2.2 OPERATIONAL DESCRIPTION (HARDWARE)

2.2.2.1 modes of processing

there are three basic modes of processing the Drum Memory System (DMS). Initialization, search and transfer, and termination.

2.2.2.1.1 INITIALIZATION

Initialization involves loading the various registers in the DMS from the initialization table located in main core memory.

2.2.2.1.1.1 The even numbered locations (0-16) of the initialization table are loaded by the Central Processor's running program. All information necessary for a Drum Control Unit (DCU) to fulfill an assigned task is present in these nine locations.

2.2.2.1.1.2 The odd numbered locations are used by the DCU, to write into them, the data contained in the proceeding even numbered locations, so that a check can be made, that the information in those locations are correct.

2.2.2.1.1.3 Location 18 thru 24 will contain other data that will be explained further on in the article.

2.2.2.1.1.4 Initialization is accomplished by the issuance of a CPD instruction from the CCP to a selected DCU.

2.2.2.1.2 search and transfer

two methods of search are available. Single Level Counter Start (SLCS) or associative search. The SLCS mode of operation is used in transferring program and tables between core memory and drum. Large blocks of data may be transferred, the limit being defined by the Limit Register (LR). Blocks of 2048 words are reserved in core as SLCS (block transfer) areas.

A search is made in the DAC for address coincidence. The address in the Drum Address Register (DAR) of the DAC is compared with the binary or BCD counter. When match is found, the words are transferred on interlace until the number of words defined by the contents of the LR are read (from core or drum). Associative Search

The associative search module of the DCU is a read drum write core data transfer sequence, where the data is located by searching for data coincidence between the drum data and the specified search register (SR). There is an associated mask register (MR) that specifies which of the SR bits are to be involved in the associative coincidence. There are two associative search sequences, single and multilevel. Associative Search (MLS) can perform one to three levels of search and read.

2.2.2.1.3 Termination

After the required number of words have been transferred, the termination cycle is entered. This cycle dumps the contents of the Core Address Register (CAR) of the DCU into the initialization table of core. This information aids the program in accessing retrieved data. Following this, the DCU interrupts the CCP with a DCU Ready Interrupt indicating the process is complete.

2.2.2.2 HARDWARD DESCRIPTION

The following section will present the Drum, the Drum Access Circuits (DAC) and the Drum Control Unit (DCU) from a hardware point of view.

2.2.2.2.1 Drum Characteristics

The magnetic drum used in the EAX system is a Bryant Computer Products Model 10512. It operates at 3600 rpm and has a hard plated nickel-cobalt surface. The drum comes equipped with 504 data recording heads and 6 clock track recording heads.

2.2.2.2.1.1 Storage Characteristics

The drum is divided into 18 segments. Each segment contains 27 active recording heads and one spare recording head. There are 10,999 locations around the peripheral of the drum, thus, each segment is capable of recording 10,999, 27 bit parallel words. The total storage per drum is then 18 × 10,999 or 197,982 words.

Depending upon the system application, the drum can be arranged in one of two configurations. One configuration treats the drum as a single storage area of 18 segments. The other divides the drum into two independent storage areas of nine segments each. The two areas can be accessed simultaneously without electrical interaction. Each drum unit, whether nine or 18 segments, will have 3 sets of clock tracks. Each set consists of two tracks; one has a single bit recorded at drum location φ and the other is a continuous closed track with a bit recorded at every drum location.

There is one master set and two auxiliary sets for each drum unit. The auxiliary tracks provide redundant clock sources for the Drum Memory System. One set will be active and the other will be on standby. The master tracks provide backup for re-recording auxiliary tracks.

The drum is equipped with Bryant AH-020 recording heads. A modified return-to-bias recording method is used at a recording frequency of 660 KHz (350 bits per inch). The write current pulse width is 400 nsec. and the pulse amplitude is 80 ma. For reading, a playback voltage of 60 mv is obtained across a 1K ohm read amplifier input.

2.2.2.2.1.2 Power Distribution and Control

The distribution and control of power to the Drum Memory System refers to the circuits and equipment necessary to run the drum motor and apply the D-C voltages to the Drum Memory System circuit.

2.2.2.2.1.2.1 Drum Motor Power

The drum motor operates on 117 volts, 60 Hz A-C. The motor starts on commercial power and after a preset time delay, a DC-AC inverter is switched in to provide motor power. If the inverter output fails, the motor will be switched back to commercial power with no other discontinuities in the system. The failure will cause an alarm signal to be sent to the Maintenance Control Center (MCC) and a lamp to come on at the A-C power control panel to the DMS.

The starting current requirements of the motor are about three times the run current requirements, e.g., the measured start and run currents for the Bryant drum are 15 and 5 amps respectively. A special circuit, the Drum Motor Start Circuit, is used to provide a high starting current and yet permit the use of a smaller, more economical and more reliable inverter. Basically, the circuit holds start capacitors in the motor power circuit until the motor has been on for a few minutes, at which time it switches the capacitors out. A short time after the capacitors have been switched out, the power source will be switched from the commercial line to the DC-AC inverter.

A thermal overload switch which is preadjusted by the manufacturer for maximum allowable internal temperature of the drum, is supplied with the drum. When a thermal overload occurs, power is removed from the drum, an alarm signal is sent to the MCC and a lamp at the A-C power control panel of the DMS provides a local indication of the thermal overload condition.

2.2.2.2.1.2.2 D-C Power Sequencing

Three D-C supply voltage levels are used in the Drum Access Circuits (DAC). These are the -5V off-bias voltage, the +5V logic voltage, and the +24V write/read voltage. In order to protect the information on the drum, the sequence of power application and removal must be defined. The Power Sequencing Circuit provides this function automatically when -50V is applied to the circuit by depressing the D-C power sequencing switch on the D-C control panel of the DMS. The sequence of application is -5V and +5V together and then +24V. In removing power, the opposite sequence must be used, i.e., +24V is removed first, then +5V and -5V. The DCU has a separate supply which is not sequenced with the DAC supplies.

2.2.2.2.1.2.3 Power Supply Monitor

The output of each power supply in the DMS is connected to an inlet of a voltage monitor. There is one voltage monitor per DMS frame. Whenver the output voltage of a power supply drifts beyond a predetermined allowable tolerance, the voltage monitor board indicates which supply is in trouble, and an alarm signal will be sent to the MCC indicating that the DMS subsystem has power supply trouble.

2.2.2.2.1.3 DMS Power Panel

The power panel is mounted on the DMS frame and is equipped as follows.

1. A-C Power

1. Lighted POWER-ON Switch

2. Lighted POWER-OFF Switch

3. Inverter Failure lamp

4. Thermal overload lamp

5. Lamp check pushbutton

2. DC Power

1. D-C power sequencing lighted switch

2. +24 volt lighted switch

3. Lamp check pushbutton

2.2.2.2.2 Drum Access Circuits (DAC)

FIGS. 19 and 19A illustrate the three major sections of the DAC. They are the Recording Circuits, the Clock Circuits and the Peripheral Adapter (PA). The recording circuits are those circuits including their drivers, monitors and protect circuits which communicate directly with the magnetic drum. The clock circuits provide clock pulses for referencing drum locations and for timing logical functions in the DAC and DCU. The PA contains the storage and control circuits necessary for interfacing the DCU and the recording circuits.

2.2.2.2.2.1 Recording Circuits

The functional blocks of the recording circuits are shown in FIG. 19A. These include the Write/Read Circuits; the Head Select Circuit; the Write/Read Control Circuit; the Head Select Monitor Circuit; and the Memory Protect Circuit.

2.2.2.2.2.1.1 Write/Read and Select Circuits

Write/Read Circuits and Head Select Circuits FIG. 20 illustrates the organization of recording heads and their write circuits -- the Head Select Circuit and the Write/Read Amplifiers. The Head Select Circuit selects the heads in the horizontal direction defined as a segment. Each segment contains 27 heads (number of bits per word). Corresponding heads (same bit number) are connected together as shown and are driven by one write amplifier. For a write operation, one segment is selected and all write amplifiers are energized. Data will be recorded only at the drum location related to the selected segment. Each write amplifier has a corresponding read amplifier to sense the information recorded on a particular bit and segment. The input to the read amp is the playback voltage developed across the recording head.

1. Head Select

The Head Select Circuit receives its inputs from a circuit in the PA that decodes the segment portion of the drum address. Only one segment decode input will be true at a time. The Head Select Circuit will place +24V on the center tap of all heads of the selected segment; all other center taps will be grounded. Write current for the 27 heads, approximately 2.5 amperes, is applied to the heads in this manner.

2. Write Amplifiers

The write amplifiers switch current directly to the heads previously selected by the Head Select Circuit. Control comes from the DAC Write/Read Control Circuit which receives write commands from a PA control circuit. Each amplifier has two outputs; they are connected to opposite endtaps of the same head via shielded twisted pair leads.

3. Read Amplifiers

The read amps read the playback voltage across the recording heads and output a logic 1 for a recorded logic 1 and a logic 0 for a recorded logic 0. The physical connection between the read amp inputs and the recording heads is via the same shielded twisted pair that connects the write amp to the head. The shield is grounded at both ends. The read amps have a differential input stage. This, along with the twisted pair, provides a high degree of balance. The differential input has a relatively high common mode rejection which is necessary because of the noisy environment that may exist around the cable between head and read amp input. The output of the read amplifier is a 800 nsec pulse from a standard NAND gate.

2.2.2.2.2.1.2 Write/Read Control Circuit

The Write/Read Control Circuit develops the pulses and levels necessary to control and drive the 27 Write/Read Circuits. Since the timing of the write pulses to the amplifiers is critical, the circuit contains precision timing and checking circuits. To write informatiion on the drum, an enable signal (WRITE LEVEL) and write pulses (WRITE PULSE) are sent from the PA to the Write/Read Control Circuit. Timing is not critical at the WRITE PULSE input level since the critical delay and shaper circuits are on the Write/Read Control Circuit itself. To read information from the drum, the PA sends an enable signal. Data to be recorded on the drum is sent from the DCU to the Drum Buffer Register in the PA and then to the write amplifiers. Data read from the drum is sent from the read amplifiers to the Drum Buffer Register and to the DCU. Two error detectors, the Access Circuit Err and Write Control Err, check the integrity of control signals to the write/read circuits.

2.2.2.2.2.1.3 Head Select Monitor Circuit

The Head Select Monitor Circuit detects a selection of none or more than one segment. There are two one-out-of-18 circuits on each monitor card. One monitors the decoded segment select information at the input to the Head Select Circuit; the other monitors the output of the Head Select Circuit. The error signals sent to the PA are Head Select Input Fault and Head Select Output Fault respectively. Either one will cause a DCU interrupt.

2.2.2.2.2.1.4 Memory Protect Circuit

The DAC contains a Memory Protect Circuit which acts to protect drum recording information in the event of a power supply or drum speed failure. This circuit also acts to protect drum and reset the DMS when power is turned on or off. (See DMS-PDR document). A power supply failure is indicated by a lamp on the power supply monitor panel as well as bits 22 and 19, word 20 and bit 19, word 22 (refer to sections 4.1 and 4.2 on error status indicator words) of ITE if the Error Termination Sequence is at all possible. A drum speed error will set bits 19, 22 and 13 of word 20 and bit 19, word 22 of ITE.

The Memory Protect Circuit is independent of the +5 logic power supply. It utilizes an on-the-card DC-DC converter powered by redundant +24V power supplies. A failure on this card causes a DCU error interrupt indicated by bits 19 and 23 word 20, and bit 19 word 22 of the ITE.

Problems within the drum may cause the thermal overload contacts to open and release A-C power to the drum motor. This condition will cause the drum speed detection circuits to set and trigger an error termination sequence setting the same bits as mentioned for a Drum speed failure.

2.2.2.2.2.2 Clock Circuits

The Clock Circuits will provide the Drum Reset Pulses (DRP) and the Drum Index Pulses (DIP) for referencing the angular index of the drum. A clock track, called Master Reset Pulse (MRP), will be recorded with one bit. This bit develops the DRP which marks the start location on the drum perimeter.

A second clock track, called Drum Index Pulse, will be recorded with 10,999 bits. This will be a continuous closed track and each bit will reference a word location on drum.

For reliability reasons, it was decided there would be three sets of clock tracks, one set called master (MRP and DIP) and two sets called auxiliary tracks (1 and 2). The master tracks will provide backup for re-recording auxiliary tracks. The two sets of auxiliary tracks provide backup for each other. If an auxiliary track which is on-line failed, the Clock Circuit would automatically switch the respective standby track on line and indicate a clock track error. The responsibility of the Clock Circuits is to record clock tracks, transfer tracks, and indicate clock track errors. These functions are shown on the DAC Block Diagram; FIG. 19 and 19A.

2.2.2.2.2.2.1 recording Clock Tracks

The Clock Track Control (CTC) is a panel which contains all the controls for writing clock tracks. Each clock track has its own write/read amplifier. The mode of recording tracks is return-to-bias (RB).

The manual procedure for writing a clock track is as follows:

1. Select the track to recorded

2. Enable the write amplifier

3. Depress the erase button. This will bias the associated clock track.

4. Depress the write button. This will start the Clock Track Writer (CTW) recording sequence.

When recording Master MRP, the CTW will generate one pulse which will record one bit on the associated MRP track. When recording Master DIP, the CTW in conjunction with the Binary Counter (BC) will generate a train of 10,999 pulses which will record the associated DIP track. The frequency of these pulses will have to be adjusted to obtain a closed track. It may take several attempts to record a perfect DIP track. The CTW will have the capability of recording 10,500 to 11,500 bit tracks. The BC is a standard 15 bit counter programmable from 0 to 16,383.

When recording the auxiliary tracks, the CTW will record the associated master track data (read amp. output) on to the selected auxiliary clock track. There will be a delay adjustment to minimize the skew between auxiliary DIP tracks. After all clock tracks have been recorded the Clock Track Control Panel may be removed. However, it is necessary to strap the Write Inhibit lead of the Write/Read amplifier to ground before removing the CTC. This strapping is accomplised on the CTW card where jacks are provided.

2.2.2.2.2.2.2 Transfer and Error Check

The Transfer Circuit will switch on-line the alternate axuiliary track either automatically (due to a clock pulse error), or manually from the CTC, or on command from the PA. The MRP on-line develops the Drum Reset Pulse (DRP) which will be in coincidence with one DIP. DRP and DIP are the clock timing pulses for the Drum Memory System.

There are five error checks for Clock Circuit Faults. Error detectors will set latches which will retain the error indication for diagnostics.

1. Master Track Error Detector -- this detects coincidence between MRP and DIP bit 10,998.

2. DIP Track Skew Detector -- This detects the skew between the auxiliary DIP tracks.

3. Drum Speed Detector -- This detects the speed of the drum by timing the DIP pulses.

4. DRP Error Detector -- This detects the absence of DRP pulses.

5. DIP Error Detector -- This detects the absence of DIP pulses.

2.2.2.2.2.3 DAC Peripheral Adapter (PA)

The PA contains the circuitry necessary for locating drum addresses; drum interlacing; temporary storage of drum data; timing of drum write/read control signals; and detection of hardware and software errors.

2.2.2.2.2.3.1 Locating Drum Addresses

The PA locates drum addresses by finding coincidence between the contents of an address register and the count of a counter which is advanced one count for every Drum Index Pulse (DIP). The following information is required to find a drum address: (1) the segment number, (2) whether the drum location is specified in binary or BCD, and (3) the address of the word relative to DRP (location 0). This information is loaded into the Drum Address Register (DAR) at the beginning of a transfer. The segment number (bits 16-20) is decoded and sent to the Head Select Circuit, which in turn, energizes the appropriate segment. DAR bits 0-15 contain the drum address (relative to DRP). DAR bit 22 specifies which counter will be compared with the address bits. Two counters, one binary and one modified BCD, continuously count DIP pulses. Each count up to the equivalent of decimal 10,998 and then are reset to zero by DRP. Thus, each count in the counters is related to a specific drum location or drum location references in this manner is called a drum index value.

The search for coincidence starts upon command from the DCU (START COUNTER SEARCH).

2.2.2.2.2.3.2 drum Interlacing

A maximum of 6 DCU's will be interfaced with two CMC's working in sync. Words can be read from each drum at a 1.6 microsec. rate and the core memory cycle time is 1 to 2 microsec. Thus, since several DCU's might request access to core simultaneously, it is not possible to transfer successive words from drum to core. A drum interlace, whereby one word every five locations is read (written) from drum and written (read) into core, is used. The interlace rate of five was selected so six DCU's and the CCP would access core with the probability of a request going unanswered minimized. The interlace rate is not variable, but could be increased to 6, 7 or 8 if required.

Interlacing is controlled by a 3 stage counter on the PAD sequence Control Circuit. The counter starts when coincidence is found in either the PA (counter coin) or in the DCU (assoc. coin) and outputs one pulse (MI-DCP2) for every 5 drum locations. MI-DCP2 will effectively skip ahead one location for every complete drum revolution. For example if drum locations 0, 5, 15 etc. were read on the first drum revolution, locations 1, 6, 16, etc. would be read on the second revolution.

2.2.2.2.2.3.3 Temporary Data Storage

One register, the Drum Buffer Register (DBR) is used as temporary storage for both writing and reading operations. The register contains 26 bits including a parity bit and a memory protect bit. Another bit, The Block Mark Bit, is treated as the 27th bit of the DBR. This bit is located on the PAD Data Control circuit. Parity is checked across all bits except Block Mark for both read and write operations.

The use of DRB in transferring data is described in detail in section 2.2.2.2.2.3.5.

2.2.2.2.2.3.4 Timing and Write/Read Control

The PAD Sequence Control Circuit and the PAD Data Control Circuit are the PA circuits that provide timing and write/read control.

The DIP clock track is the source for all DAC write/read timing signals. For some applications, DIP is used directly; for others timing pulses are generated by pulse circuits on the PAD Data Control Circuit. These pulses are sent to the other DAC circuits for write/read control and to the DCU (refer to section 2.3.1.4 and FIG. 24, for additional DMS timing details). Write/read control signals are developed on the PAD Sequence Control Circuits. For both writing and reading, an enable signal and pulse are developed. These are WRITE LEVEL and WRITE PULSE for writing, and PA READ ENABLE and STROBE DBR for reading. The write/read control interface with the DCU is described in detail in section 2.2.2.2.2.3.5.

2.2.2.2.2.3.5. Operational Explanation of the PA

The operational explanation of the PA will be divided into read and write categories.

2.2.2.2.2.3.5.1 Read Transfer (drum to core).

Refer to the flow chart of FIG. 21. A data transfer is started when the Drum Address Register (DAR) is loaded during the initialization cycle of the DCU. Bits 16 thru 20 of the DAR contains the segment address of the first word to the transfer. If the specified segment is valid (within range of implemented segments), the number of the specified segment is decoded and sent to the Head Select Circuits. The Head Select Circuit then notifies the PA that one and only one segment has been selected and the PA sends the ONE SEGMENT SELECTED (ISS) signal to the DCU. When the DCU acknowledges the ISS signal, it initiates an enable signal (in this case READ ENABLE) and either a CONTINUOUS READ or a START COUNTER SEARCH signal.

Assume that the DCU sent a CONTINUOUS READ signal. If there have been no DAC errors up to this point, the PAD sequence Control Circuit sends the PA READ ENABLE signal to the recording circuits. Data is transferred from the Drum to the Drum Buffer Register under control of the PA. After each word is loaded into the DBR, its parity is checked. If parity is correct, the DCU, by sending a DIPLAY DBR signal transfers the data from the DBR to the PA Output Bus and thus to the DCU. In this manner, the DMS presents a continuous stream of data, and the contents of a register in the Associative Search Module of the DCU. When coincidence is found, the contents of the specified counter is stored in the address bits of the DAR and the PAD Sequence Control Circuit switches the PA to interlaced control. The count stored in the DAR will be the address of the coincidence word +8.

If, instead of a CONTINUOUS READ signal the DCU had sent a START COUNTER SEARCH signal (refer to the CR decision box on the flow chart), the address search would have been performed in the Address Coincidence circuit of the PA. Bit 22 of the DAR specifies which counter (binary or BCD) will be compared with the address bits of the DAR. When coincidence is found, the PAD Sequence Control Circuit sends the PA READ ENABLE signal to the recording circuits and switches the PA to interlaced control. With the PA in the interlaced control mode, every fifth drum word (for interlace of 5) will be loaded into the DBR, checked for correct parity and sent to the DCU. Control of the data transfer will handled in the same manner as for a continuous read operation.

The transfer continues until the READ ENABLE signal from the DCU is removed. During the transfer, the count of the specified counter is transferred to the address bits of the DAR once for every 5 DIP pulses. At the end of transfer, the DAR will contain the address of the last word transferred +8.

2.2.2.2.2.3.5.1 Write Transfer (Core to Drum)

The DCU Associative Search Mode is not used for drum write operations. Therefore, PA operation for write transfers is less complex than that of read transfers. Refer to the flow chart of FIG. 22. The sequence of operation through initial loading of the DAR, segment decode, segment select and ONE SEGMENT SELECTED signal is identical to that of the read operation. If no errors have been detected, the DCU sends the START COUNTER SEARCH signal. The specified counter (binary or BCD) will be compared with the address bits of the DAR to locate the angular index value for the beginning of the transfer. When the angular index value is found the Z COUNTER signal is sent to the DCU and to the PAD Sequence Control Circuit. The DCU controls transfer of data to the DBR and the PAD Sequence Control Circuit sends the WRITE LEVEL and WRITE PULSE to the recording circuits. WRITE PULSES cause data to be written on the drum at the specified interlace rate. The transfer will continue until the WRITE ENABLE (from DCU) signal is removed, terminating the transfer. The count of the specified counter is stored in the address bits of the DAR. The stored count will be the address of the last word written +8.

2.2.2.2.2.3.6 Error Detection

Whenever an error occurs in any circuit of the DAC, the following actions are taken in the PA.

1. if a data transfer is in progress, it will be halted; the contents of the DBR and the 10 higher order bits of the DAR will be held intact for diagnostic purposes.

2. The contents of the binary or BCD counter, at the time of the trouble indication, is stored in the address field of the DAR. For most PA errors, this stored count is meaningless. However, for parity errors, it can be used to identify the bad word. Since binary numbers should be simpler to handle in diagnostic routines, parity errors will cause the binary count to be stored.

3. The error indication will be stored in a flip-flop or latch type of storage element, the output of which can be displayed on the PA Output Bus for diagnostics.

4. The DCU will be notified of the detected error. All DAC error indications will be OR'ed together and a single error signal, DAC ERROR, will be sent to the DCU.

Diagnostic routines, which simulate error conditions in the DAC, will be written so that DAC error detection circuitry is exercised periodically.

2.2.2.2.3 Drum Control Unit (DCU)

The DCU provides the control and data path for the transfer of information between the CMC and DAC. The DCU contains buses (I/O and internal), registers, error detectors, and control circuitry as depicted in the DCU Block Diagram, FIG. 23.

2.2.2.2.3.1 block Diagram Description

FIG. 23 illustrates the organization of the DCU, and aids in understanding the following sections.

2.2.2.2.3.1.1 Bus Structure

1. Data Bus A (Input)

Data to the DCU (25 bits and 1 parity) from the CMC or DAC is received via bus A. Parity at bus A is checked by the Bus A parity circuit.

2. Data Bus C (Output)

Data from the DCU (25 bits and 1 parity) to the CMC or DAC is sent via bus C. Parity is checked (Bus C parity) and corrected if necessary before data is sent to the CMC or DAC, i.e. bad parity will never be written in core or on drum.

3. Address Bus D

Addressing core (15 bits and 1 parity) is accomplished directly over bus D from the DCU. Correct parity is generated at bus D (Bus D parity circuit).

2.2.2.2.3.1.2 Registers

Each register in the DMS except the IAR contains parity and memory protect information in bits 24 and 25 respectively. The following is a description of the registers in the DCU. More detailed description of each DMS register is found in Appendix I of this section.

1. Instruction Register/Limit Register (IR/LR).

The IR portion (10 bits) will contain the directive to be executed by the DMS. The IR portion (14 bits) will contain the number of words to be transferred in the case of single level counter search or the number of words to be skipped (indexed) in the case of single level associative search.

2. Initialization Address Register (IAR)

The IAR is a 15 bit address register used to address core during certain DCU sequences. The low order 5 bits are preset and incremented during these sequences. The high order 10 bits are strapped internally whose value is determined by bound checks to be made in core.

3. Core Address Register (CAR)

This 26 bit register is used to address core during any of the data transfer modes. Bits 15 thru 20 are not programmable.

4. Core Buffer Register (CBR)

The 26 bit CBR is used as a temporary store of data being transferred.

5. Search Registers (SR1-SR3)

The Search Registers (26 bits) contain information that specifies the drum address or data coincidence to be encountered before entering the respective levels of associative search.

6. Mask Registers (MR1-MR3)

The Mask Registers (26 bits) contain information that specify which bits of their respective SR are to be involved.

2.2.2.2.3.1.3 Associative Search Match Circuit

This circuit decodes coincidence between bus A information from drum and the search register screened by the mask register.

2.2.2.2.3.1.4 Common Control

The Common Control contains the DMS timing, coincidence circuit, pulse distributor, and the directive decode circuit.

The DMS timing is illustrated in FIG. 24. DCP2 and DCP1 are generated in the PA of the DAC from the drum clock tracks (DIP). FRI-DCP2 (also generated in the PA) is a free running DCP2 whose period is 1 drum interlace time of 7.5 microsec. DCU TIMING CP (TCP) is generated from DCP2 by a pulse shaper on the Bus D Multiplex circuit of the DCU. The coincidence circuit recognizes the specified coincidence (counter or information) and enables the pulse distributor at the approximate time. The pulse distributor (PD) is a three stage counter which is synchronized with the interlace counter of the DAC and clocked by DCP2 pulses. The PD is strapped at the connector for an interlace rate of five. The strapping can be changed if a higher interlace rate of six, seven or eight is required. The DCU timing is dependent on the control pulses of the pulse distributor.

There are five control pulses, P1 through P5. The P1 pulses of the PD are synchronized with each MI-DCP2 of the DAC. The starting of the PD counter is different for the various DCU sequences.

During the write sequence, the PD counter will be set to P1 and started by Z counter (counter coincidence). For any read-drum write-core counter search sequence, the PD counter will be set to P1 and started by MI-DCP2.

When searching for associative coincidence, the PD will be set to P3 and started on match strobed by DCP2.

Regardless of what the PD counter is set to or which signal started the PD, the control pulses will not be enabled until the counter has been started and the count reaches P3 time.

The directive decode circuit will decode the instruction register bits 20-23 and determine the operation to be performed that is, read sequence (SLCS), write sequence (SLCS), single or multi level associative search DAC maintenance, or invalid operation.

2.2.2.2.3.1.5 Block Transfer

The Block Transfer module controls SLCS read drum, SLCS write drum, initialization, termination, error termination, spills, and the error detection associated with these functions. All of the CMC interface control, as well as the sense line circuitry is under the control of the SLCS module.

2.2.2.2.3.1.6 Associative Search Control

This module controls the multi level and the single level associative search sequences and provides enabling control to the SLCS module which interfaces with the CMC and DAC.

2.2.2.2.3.2 initialization

FIG. 25 is a detailed picture of the Block Transfer Module of the DCU block diagram. The Register/bus structure and some control are retained on FIG. 25 (from FIG. 23) for clarity.

Before data transfers between core and drum (or DAC maintenance) can be made, the DCU must be initialized.

Initialization is the process initiated by a CPD, by which information is read from fixed locations in core (Initialization Table) into the registers of the DMS. This information contains directives and associated data necessary for execution of the DMS request. A copy of the Initialization Table is shown in the left column in DMS Appendix III. These locations are addressed by the IAR via bus D and the information is controlled by the initialization control and register control multiplex (see FIG. 25).

2.2.2.2.3.3 single Level Counter Start (SLCS)

The following operation description will refer to the SLCS flow chart, FIG. 25 and FIG. 23.

2.2.2.2.3.3.1 drum Write (SLCS-write)

For the SLCS drum write IR directive (see DMS Appendix II for IR format); the IR/LR, DAR, and CAR are loaded in the DMS during initialization. When complete, the DCU mode control circuit (FIG. 25) sets the write sequence circuits. The Write Sequence bit of the Error/Status register (bit 2, word 22) is set. For detailed sequential circuit conditions see the flow chart on FIG. 26. The notes along side of the functions on the flow chart indicate the timing of the hardware functions.

A core read request is issued (FIG. 25). The CMC responds with a "Data Available" pulse indicating that the word at the core location defined by the CAR is available on bus A. The word is then loaded into the CBR. The CAR is advanced (1) to address the next core location, and the LR is stepped (decremented because LR contains 2's complement) to indicate a word was transferred to the DCU. The command to "Start Counter Search" is given to the DMS. The address search continues on interlace 1 until match between the address field of the DAR and the particular angular index counter in the PA is found. If there are no errors the DBR is loaded from the CBR and the word is written on drum where address match was found. The above functions of "Core Read Request," "Data Available," load CBR, load DBR, step CAR and LR, and check for errors are continued on interlace 5 until the LR contains all zeros. At this point the Write Sequence status bit is reset and the Termination Sequence is triggered. The Termination Sequence circuits control the necessary functions for storing the present contents of the CAR (core address of last word read) into core memory, and setting the DCU Ready interrupt (see FIG. 25).

A CPD spill after this directive reveals

1. the original contents of the IR/LR

2. final Drum address

3. final core address

4. last word transferred in CBR

5. last word transferred in DBR

2.2.2.2.3.3.2 drum Write-Block Mark

If the DCU was placed in the Block Mark Mode (set bit 18 in IR), the last word written on drum will set its block mark bit, i.e. bit 26 of the last word will record a 1.

2.2.2.2.3.3.3 Drum Read (SLCS-read)

For the read drum (write core) drective (see Appendix II for IR format; the same DMS registers are loaded as for Drum Write. In other words initialization is similar, but when complete, the DCU mode control circuit sets the read sequence circuits. The Read Sequence bit of the Error/Status register (bit 3, word 22) is set. For detailed sequential circuit functions see Read Sequence on flow chart FIG. 26. The notes along the flow chart functions indicate which DCU timing pulses cause the action. After the read sequence circuits set up the buses required to receive data from drum, the command to the PA to "start counter search" between the address field of the DAR and the particular angular index counter in the PA is found.

The data at the coincidence address is sent to the DCU via bus A and held in the CBR and placed on the output bus (bus C). A "write request" is issued to core. After the word is stored in core at the location defined by the CAR, the CMC responds with a "Data Loaded" pulse. The CAR is advanced (1) to address the next core location, and the IR is stepped (decremented) to indicate a word was transferred to the CMC.

The DAC continually places words from drum into the DBR at an interlace 5 rate. The DCU loads the DBR word into the CBR, issues a "write request" to core and steps the CAR and LR after the "Data Loaded" response from core. Parity is checked at the DBR, on bus A as the data enters the DCU, and at bus C just before the "write request" is issued to the CMC. This process continues until the LR contains all zeroes in which case a block mark bit is checked (if block mark mode), the Read Sequence status bit is reset and the Termination Sequence begins. The DCU Ready interrupt (see FIG. 25) indicates the completion of the Termination Sequence.

2.2.2.2.3.3.4 Drum Read -- Block Mark

If the DCU was placed in the Block Mark mode (IR Bit 26-1). The last word to be transferred is defined by the state of the LR = all zeroes.

If these two conditions

1. LR = 0 2. DBR bit 26 = 1

do not occur simultaneously an error interrupt occurs. A CPD spill following a read sequence reveals

1. the original contents of the IR/LR

2. final drum address

3. final core address

4. last word transferred in CBR

2.2.2.2.3.4 associative Search

The associative search function of the DCU is basically a read drum write core operation where the data to be transferred is located by associatively searching the drum. There are two associative search sequences multilevel and single level associative search.

The multilevel associative search (MLS) provides for three levels of search and transfer, however, a fourth level of search can be obtained by having a counter search prior to the first associative search. The normal three levels of search can be either a search for counter or associative coincidence. Indirect addressing on drum is possible because of the overwrite feature of the MLS. This feature is the capability of drum data to specify the location of coincidence for the next level of search. From the time the MLS has entered the first level until termination, the DCU is controlled by the drum data.

The single level associative search (SLAS) provides for only one level of associative searching which may or may not be preceded by a counter search. The number of words to be skipped after associative coincidence is specified by the limit register and the number of words to be transferred is specified by the instruction register. Therefore, the number of words transferred is under the control of the initialization table (refer to DMS Appendix III) in core.

When the first associative coincidence is preceded by a counter search, the Block Mark (BM) bit will be checked. If the BM bit comes true while searching for this first associative coincidence, the level end flag will be set and cause an interrupt.

2.2.2.2.3.4.1 MLS Description

The operation or control of the MLS sequence is for the most part data driven. During the Initialization sequence all the control registers are loaded with data pertinent to MLS transfer. That is, the Instruction Register (IR) has the MLS directive and specifies the type of coincidence (counter of associative) to be encountered for each level of search. If all levels of search are not to be used, the unused levels must be specified counter coincidence. The Drum Address Register (DAR) contains the drum address if a counter search and the specified drum segment to be searched. The Core Address Register (CAR) contains the location in core where the first data word is to be written. All the Search Registers (SR) are loaded with information that specifies the drum address or data coincidence to be encountered before entering their respective levels of MLS. The Mask Register (MR) contains information that specifies which bits of their respective SR will be involved.

Upon completing the Initialization sequence, the DCU will enter the MLS sequence as specified by the directive in the Instruction Register. Other than the Search Register specifying the drum address or information coincidence at which the DCU should enter the next level of associative search, the control bits (21, 33 and 23) of the data read from drum will direct the DCU through the MLS sequence word by word until directed to enter the termination sequence.

There are nine possible control actions the DCU can follow as each word is read from drum during the MLS sequence. The action taken is determined by the control bits of the previous (CBR) and present (DBR) word read from drum, the present level of associative search, the present state of the DCU (read or search), and if the present word is a coincidence word (address or information coincidence). Refer to the MLS decision table for more detail information of the MLS control actions, FIG. 33 and MLS flow diagram FIG. 29.

2.2.2.2.3.4.1.1 mls operation

After completing the Initialization Sequence the MLS sequence is set. This will display the Drum Buffer Register (DBR) on the DAC data bus, enable the drum data on bus A, display the Core Buffer Register (CBR) on bus C, and display the appropriate SR and MR on the match bus and bus B, (refer to DCU Block Transfer and Associative Search Control diagrams FIGS. 25 and 28). The Read Enable latch and EN CAR CBR CTL latch will be set for the MLS sequence. The Read Enable lead will condition the DAC to respond to DCU control. The EN CAR CBR CTL lead will ready the Block Transfer Read Sequence circuitry necessary to transfer the DBR data via CBR into core.

If the MLS Transfer is a counter start, the Start Counter Search will be set and the DAC will look for coincidence between the specified counter and the DAR. When coincidence is found the DAC will go active; this will send Z counter to the DCU, start the DAC interlace counter, and load the word associated with counter coincidence in the DBR. There will be an MI-DCP2 Pulse at the interlace rate which will start the Pulse Distributor in sync with the interlace counter of the DAC. The DCU will start searching the data at the interlace rate and associative match will be tested every P3 of the Pulse Distributor.

If the MLS Transfer is not a counter start, the Start Search circuit will send a Continuous Read to the DAC. The DAC will start reading drum and loading the DBR every DCP1, and every DCP2 associative match will be tested. When associative coincidence is found, the Pulse Distributor will be started at P3 time and Z associative will synchronously start the DAC interlace counter. The DMS will now transfer data at the normal interlace rate.

At this point, the operation of the MLS sequence is controlled by the MLS decision table FIG. 33. The MLS Sequence Decode circuit will decode the control action to be taken for each word transferred. This action will be decoded and loaded in the action register every P3 time. The Action Encode Multiplex initiates the appropriate control at the proper P time, refer to the control action flow charts of FIGS. 31 and 32.

The following is a description of the nine actions which control the MLS transfer until entering the termination sequence.

These actions are decoded by the MLS Sequence Decode circuit and executed by the Action Encode Multiplex. The following is a list of the associative search control actions:

1. Enter Next Level (ENL)

2. read Present Word (RPW)

3. drum Modify Search Word (DMSW)

4. drum Modify Mask Word (DMMW)

5. reset Read Latch (RRL)

6. previous Word Interrupt (PVWI)

7. present Word Interrupt (PSWI)

8. level End Interrupt (LEI)

9. invalid Action Interrupt (IAI)

ENTER NEXT LEVEL, every new level is started by an ENL action at P3 time. This Decoded action will set the ENL latch refer to the ENL flow chart (FIG. 31). At P4 time the Read latch will be set. This will send a Core Write Request, via DCU Block Transfer Control, to write each succeeding word from drum into core. The Level Register will be advanced to n + 1 (P4 trailing edge). The DAR, which will contain the address +8 of the word now in the DBR, will be displayed on bus A. Then at P5 time the DAR address will be loaded into SR (n), and at P1 time the DBR will be redisplayed on bus A. P2 will load the DBR into the CBR and set the Write Request latch. The modified search or mask register flag bits (23 and 22) will be enabled, so at P4 + 1 time the flag bits will be loaded in the MR along with the Core address of the coincidence word being written into Core. Bit 23 set indicates this level search register had been overwritten by the drum prior to ENL however, the drum can only overwrite level two and three search and mask registers. Bit 22 set indicates this level mask register has been overwritten prior to ENL control action. At P3 + 1 time a new action latch will be set and at P4 + 1 the MR will be loaded, as previously described and at P5 + 1 the ENL will be reset.

READ PRESENT WORD, there is no decode for the RPW action. If the read latch was set by the previous word control action and there is no present action decoded, the next P2 will set a write request and the present word will be written into core. DRUM MODIFY SEARCH WORD. This action is the search word overwrite feature of the DCU. At P3 time the decoded action sets the DMSW action latch. At P4 time the next level search register is reset and the Read Latch is set. At P5 the modifying drum word is loaded into the next level SR with the proper control bit corrections. That is, if the next level search is a counter search the control bits of the drum word will not be altered (000), if (n) is level 1 and searching associatively the control bits will be changed to 100, and if (n) is level 2 and searching associatively the control bits will be altered to 110. At this time the DMSW flag bit will be set to be used for the next ENL action. P2 time a core write request will be set to write the modifying drum word into core. The control bits of this word will not be altered (000).

DRUM MODIFY MASK WORD. This action is similar to the DMSW with the exception of modifying the Mask Register and the control bits load into the MR will always be altered to 110.

RESET READ LATCH. This action will stop the transfer of data from drum to core and continue searching if the next level is associative coincidence. If the next level is to be entered via counter coincidence, this action must load the new drum address into the DAR and start the counter search on interlace one.

At P3 the RRL action is set. At P4 the Read latch is reset to stop transferring to core; also the Read Control Bits latch is reset, this is to avoid decoding any control action until detecting a coincidence word. If entering the next level is via associative coincidence, detecting Z assoc (coincidence) will set the ENL latch. This will complete the RRL action. If a counter search, P4 will reset Read Enable thus deactivating the DAC. After receiving Data Loaded from core and stepping CAR, Parity C AS will be set. This will permit checking bus C parity while loading the new DAR address during P2. At P5+1 time, the pulse distributor will be reset for interlace one searching. When the DAC has selected the new segment a Start Counter Search will be sent and the next level will be entered on Z counter.

PREVIOUS WORD INTERRUPT. This action will reset the Read latch, Read Enable, EN CAR CBR CTL, and Read Control Bits latch at P4 time. Resetting Read Enable will capture in the DAR the drum address +13 of the last word written into core. Resetting EN CAR CBR CTL will capture in the CBR the last word written in core. Then, P2 will activate the SET END SEQ AS lead and the DCU will enter the normal termination sequence.

PRESENT WORD INTERRUPT. This action will reset Read Enable on P4 which will capture in the DAR the drum address +8 of the last word to be written. This will also capture in the DBR the last word to be written in core. At P2 time the Read Control Bits latch will be reset and a write request will be issued to write this last word in core. During P4+1 the Read latch will be reset to halt issuing any further write requests also EN CAR CBR CTL will be reset which will capture in the CAR the core address of the last word in core and hold in the CBR the last word written in core. At P2+1 the DCU will enter the normal termination sequence.

LEVEL END INTERRUPT. This action is identical to PSWI control action mentioned above with the exceptions, at P4 time the Read latch is set and a level end flag is set in the Error/Status Word 18 bit 14. The Read Latch is set to write the present word (the DBR word) into core.

INVALID ACTION INTERRUPT. This control action will not reset the Read latch, but will inhibit initiating any further write request. The Read latch is an indicator bit in the Error/Status word 18 bit 20 which will indicate the status of transfer when the interrupt occurred. The DAR will capture the drum address +8 of the word held in the DBR. If interrupt occurred while writing core, the CBR will contain the word being written and the CAR will contain the address of the same word. If the DCU was searching at the time of interrupt, the CBR would not contain intuitively meaningful information, however the CAR will contain the location at which the next word would have been put into core. At P2 time the DCU will enter the Error Termination sequence.

2.2.2.2.3.4.2 SLAS Description.

The SLAS is a single level transfer in which the data is located via information coincidence and the size of transfer is specified by the initialization table in core.

During the Initialization Sequence, the control registers are loaded with information necessary to perform a Single Level Associative Search (SLAS). The Instruction Register (IR) will contain the SLAS directive with or without a counter start (CS) and the WCT field which will specify the number of words to be transferred. The Limit Register will contain the complement of the number of words to be skipped (indexed) before transferring data. The first level Search and Mask registers will be loaded with the search information. The Core Address Register (CAR) will specify the address in core to start loading data. The Drum Address Register (DAR) will specify the segment to search and, if a counter start, specify the drum address to start associative searching, refer the SLAS flow diagram FIG. 30.

2.2.2.2.3.4.2.1 slas operation

After the Initialization Sequence is completed, the SLAS sequence will be set. This will display the DBR on the DAC data bus, enable the drum data on bus A, display the CBR on bus C, and display the level one SR and MR on the match bus B, (refer to DCU Block Transfer and Associative Search Control diagrams FIGS. 25 and 28). This will also set the Read Enable and EN CAR CBR CTL latches.

If the SLAS is not a counter start (CS) sequence, the DCU will associatively search the data from drum, on interlace one. If a CS sequence, the DAC will search for the drum address specified by the DAR. Upon counter coincidence, the DCU will begin searching associatively on interlace five.

Upon obtaining information coincidence, the ENL control action (refer to FIG. 31) will be set. This will cause the coincidence word to be written into core and will step (increment) the limit register. Each word read from drum will now increment the LR. When the LR equals zero, the Read Latch will be set and all successive words will be written into core. This will continue until the LR equals the WCT field of the instruction register. LR, WCT coincidence will reset Read Enable, Read Latch, and the EN CAR CBR CTL latch, thus capturing the last word in core in the DBR and CBR. The DAR will capture the drum address +8 and the CAR will capture the core address of the last word in core. The SLAS sequence will then relinquish control to the normal termination sequence.

There is a Block Mark (BM) check for the SLAS sequence without CS. If bit 26 (BM bit) of bus A is true for the associative coincidence word or any succeeding word prior to the last word transferred, the SLAS BM error will be set. This will relinquish control to the Error Termination sequence and will cause an error interrupt.

2.2.2.2.3.5 Termination Sequence (TS)

The Termination Sequence is an automatic sequence of the DCU which occurs at the completion of a DCU process. The contents of the CAR are dumped into location 24 (bits 0 thru 14) of the Initialization Table (FIG. A of Appendix III).

After the dump, a DCU interrupt is set. If the DMS process was completed with no errors, the DCU Ready interrupt follows the Termination Sequence.

FIG. 25 shows the input control to the Termination Sequence as outputs from the End Sequence. The End Sequence is a transient state providing the hardware link between drum-core transfers and Termination.

It should be noted that a Termination Sequence which follows an Error Termination Sequence will also dump the low order bits of the IAR.

2.2.2.2.3.6 error Termination Sequence (ETS)

When an error is detected the three error/status indicator words (E/S words) will be dumped into locations 18, 20, and 22 of the table giving details of the error and status of the DMS at the time of the error. The 5 low order bits of the LAR are captured into bits 15-19 of the CAR at the time of the error and are dumped into core by the normal termination sequence. A DCU Error Interrupt follows, and the DCU ERR/STATUS IN CORE sense line is set indicating a successful transfer of the error status indicator words in core.

(See FIG. 25). The status of the captured IAR bits in the CAR may be important for diagnostics depending upon when the error occurred. For example, the TS which follows an ETS from an error that occurred during initialization would reveal the last location of the table that was loaded into the DMS. An error during the execution of one of the data transfer directives causing the IAR to be captured would reveal the last entry read during initialization.

During a CPD Spill (see section 2.2.3.1.3), the captured IAR bits should display the state of the IAR just as the Error Termination Sequence is entered or 18 (10010), providing another check.

A hardware description of the TS and ETS is contained in the flow chart (FIG. 27). The notes along the flow chart functions indicate which DCU timing pulses cause the action in the boxes.

2.2.2.2.3.7 Forced Errors

The DCU has the hardware capability of checking some of its error detecting circuits. Certain bits of the E/S words will be set (1) if the particular detectors are working properly. This forced error routining of the DCU is possible thru the CPD Maintenance command which is discussed fully in section 2.2.3.1.4.

2.2.2.2.3.8 Spill

Under the control of CPD (CPD Spill) the DCU can dump all registers (including E/S words) of the DMS into the initialization table -- see the spill format shown in the right hand column of DMS, Appendix III.

2.2.3 interface

the following section will present the DMS from an interface point of view. The CPD control (interface with CCP) will be discussed in detail. Since sense lines reveal the states of the DCU, these states and a thorough analysis of the DCU sense and interrupt lines will be considered. The memory protect system and finally the core access characteristics of the DCU will be deliberated. Refer to FIG. 34 for access-response characteristics of the DCU.

2.2.3.1 cpd directives (Control Pulse Directives)

The CPD lines interface with the CCP thru the CMC. There are four CPD commands. Two data and one CPD line sent to the DMS. The CPD clears or begins processing in the DMS.

2.2.3.1.1 cpd clear (DLO = 0, DL1 = 0)

This CPD completely clears the DMS. All registers except for the IAR, all error latches, all control and sequence circuits are reset. If the machine has successfully cleared, the DCU IDLE sense line will be set. No interrupt will occur. When the CPD pulse is removed, the machine will be cleared and the IDLE sense line may be checked.

Under normal conditions (no error) the CPD Clear should be issued when either the DCU READY or DCU ERROR sense line is set. The directive may, however, be issued while the DCU is active. In this event, the job will be aborted after the completion of the present core request. An Error Termination Sequence will follow and bit 21 word 22 in the ITE will be set. Termination will set the DCU ERROR interrupt. A CPD Clear may now be issued to clear the DMS. If the double CPD is used to abort DCU processing and the interrupt is not desired, the following sequence of instructions must be used:

1. Set Input Test Register -- Cause Port Malfunction

2. Reset Input Test Register -- Restore Port

3. Reset Port on Line Register -- Since the REI below will initiate DCU requests (ETS), the CMC must ignore the requests.

4. REI -- Removes Port Malfunction

5. LLR 48 -- Wait 24 microsec. for DCU Core Access Trouble to be set. Inhibits DCU Interrupt.

6. DMS CPD Clear -- Reset DMS

7. set Port on Line Register -- Restore POLR.

2.2.3.1.2 cpd initialize (DLO = 1, DL1 = 0)

This CPD command begins initialization which is the process of loading the various registers in the DMS from an area in core called the Initialization Table (ITE, DMS, Appendix III). Each word is alternately copied back in core for parity checks. The even locations (left hand side of DMS, Appendix III) are read into the DMS registers and the odd locations are filled with a copy of the registers by writing back into core from the corresponding register of the DMS. The process follows an alternate read core-write core pattern.

Referring to FIGS. 23 and 25, the data is received over bus A, loaded in a register and placed on bus C (via bus B is required) and sent back to core. For the DAR, the cross transfer of bus A to bus B to bus C (see FIG. 25) is used to go from core to drum or from drum to core. In this manner, the integrity of the data, the DMS registers, and the DMS buses is checked by parity checking schemes in the DMS and CMC. If a parity error is detected in the DMS, the word is still copied back into core, but an attempt is made to correct the parity via (bit 24) at the output bus as it is written back in core. This way the core will always see correct parity, but a comparison between adjacent entries of the Initialization Table can be made in core to locate the erroneous bit if required.

During initialization, the complement of the core data is loaded into the LR; however, the actual uncomplemented value is copied back into core. The complement is loaded into the LR because this register will be decremented by the input clock pulses. The number of words read into the DMS registers (initialized) from the Initialization Table (ITE) and the time involved depends upon the directive in the IR as illustrated in the table below with reference to the ITE figure (DMS, Appendix III).

________________________________________________________ __________________ Locations Locations Execution Register read from Written in Directive Time Loaded ITE (DMS ITE (DMS in LR (DMS micro- in DMS Appendix III) Appendix III) Appendix II) seconds ____________________________________________________________ ______________ A IR/LR 0 1 DAC Maint 15 B A+DAR+CAR 0,2,4 1,3,5 Block Trans 45 Write or Read C B+SR1+MR1 B+6+8 B+7+9 SLAS 90 D C+SR2+MR2 C+10+12 C+11+13 MLS 135 +SR3+MR3 +14+16 +15+17 ____________________________________________________________ ______________

During this sequence the Initialization Sequence status bit of the error/status register of the DCU (Bit 0, word 22 in ITE) is set until the last register is loaded.

2.2.3.1.3 CPD Spill (DL0 = 0, DL1 = 1)

When this CPD is issued all DCU and DAC registers are dumped into the odd locations of the initialization table, and the three error status indicator words are dumped into locations 18, 20 and 22. The CPD Spill command utilizes the Initialization Sequence with dummy reads, Error Termination Sequence, and the Termination Sequence. The CPD Spill format is shown in the right hand column of DMS Appendix III.

Location 23 should contain all zeros if there are no faults, indicating the quiescent state of busses B and C. When the CAR is dumped in location 24, bits 15-19 will contain the low order bits of the IAR. If the spill is successful, these bits should display 18 or

Location 24 1 0 0 1 0 CAR in ITE 25 20 19 18 17 16 15 14 0

indicating the state of this register just as the Error Termination portion of the spill is entered. These bits have a different meaning when the CAR is dumped in location during the termination sequence of an error interrupt on DCU interrupts.

The meaning of the data dumped in the other locations is shown in the right hand column of DMS Appendix III. The CPD Spill takes 25 drum interlace periods or about 188 microsec.

2.2.3.1.4 CPD Maintenance (DL0=1, DL=1)

This CPD command can be used to check certain error detecting circuits of the DCU. When issued, the DMS will proceed as though a normal Initialize CPD was issued. After initialization, the instruction in the IR will be executed followed by normal termination.

The difference, however, is the DCU will be forced to detect certain errors. The error detectors will be set at the proper time during the CPD Maintenance Sequence but an Error Termination Sequence will not begin when the error occurs as would begin when an error occurs during any normal data transfer processing. This means that the indiciator bits of the particular error detecting circuits being checked will not be automatically dumped into core as they normally are following an error. A CPD spill request is necessary to dump into core the words containing the error/status indicator bits (words 18, 20, and 22 of the Initialization Table). If the error detecting circuits are working, ones should be present for certain indicator bits depending upon which directive was in the IR when CPD Maintenance was issued. If at least one of the error detecting circuits has detected the simulated error, the spill will be followed by a DCU Error interrupt.

1. CPD Maintenance -- Write Drum directive in IR. When CPD Maintenance is issued with a drum write directive in the IR, six indicator bits and one sense line should be set. The set indicator bits should be:

1. DAC ERROR -- bit 19 word 22 in ITE

2. dac parity -- bit 5 word 20 in ITE

3. bus a parity -- bit 22 word 22 in ITE

4. bus c parity -- bit 23 word 22 in ITE

5. pd skew -- bit 22 word 18 in ITE

6. read time out error -- bit 12 word 22 in ITE

The CORE ACCESS TRBL sense line will also be set because of the READ TIME OUT ERROR.

2. cpd maintenance-Read Drum Directive in IR. With a read drum directive in the IR, the same error bits except for 1 and 2 above should be set.

3. CPD Maintenance -- Other directive in IR. The CORE ACCESS TRBL sense line and READ TIME OUT ERROR (bit 12 word 22 in ITE) may be set by issuing a CPD Maintenance with a directive other than Read Drum or Write Drum in the IR.

The parity errors are detected by a technique of inhibiting three bits (21, 22 and 23) at the input bus (bus A). i.e., a word with correct parity from drum (core) may be used because the bad parity simulation takes place at the Data Bus A Multiplex circuit (FIG. 25). This approach eliminated the need to write bad parity in core or on drum since the bus A control for bits 21, 22 and 23 are handled separately because of Associative Search Requirements. It must be remembered; however; that bits 21, 22, and 23 of the known word as it exists in core or on drum must contain odd parity. Inhibiting them therefore causes even (bad parity in the DCU).

The execution time of CPD Maintenance is determined by the directive in the IR.

2.2.3.2 sense Lines and Interrupts

The DMS contains 10 sense lines to interface with the CCP (thru the CMC). Two of these sense lines are interrupts. The DMS sense lines provide indications of the present state of the machine. They are used; 1) as an aid in diagnostics when the E/S words are not available and 2) to indicate present states of the DMS which could be necessary information to the CCP before and/or after certain action is taken involving the DMS.

2.2.3.2.1 dcu interrupts

The two sense lines that interrupt the CCP are DCU READY AND DCU ERROR. The DCU Termination Sequence is followed by a DCU READY Interrupt if processing was successful (errorless). The DCU ERROR Interrupt is set indicating that an error or a CPD violation has been detected. A special case of the DCU ERROR interrupt is DCU TIME OUT detection.

The interrupts may be inhibited by the DCU ON LINE interface control from the CMC. In other words, the DMS may be accessed for normal processing but the interrupts will not be set.

2.2.3.2.2 DCU STATES

Table 1 below contains a summary of the basic states of the DMS. State (1) is the only state from which a data transfer directive may be issued. Tables 2 and 3 show other DMS States and are discussed in the sections on memory protect and core access problems.

TABLE 1 -- DCU STATES ____________________________________________________________ ______________ DCU State Sense Lines Description DCU DCU DCU RDY ERR IDLE ____________________________________________________________ ______________ (1) 0 0 1 DMS is IDLE and READY for any CPD (2) 0 0 0 MS is ACTIVE or QUIESCENT (see TABLE 2) (3) 1 0 0 DMS has completed task. Waiting See (B) of FIG. 34. (4) 0 1 0 An error was detected. Waiting See (B) of FIG. ____________________________________________________________ ______________ 34.

TABLE 2 -- DCU STATES FROM CORE ACCESS PROBLEM ____________________________________________________________ ______________ PORT MAL- PORT MAL- CORE DCU FUNCTION FUNCTION ACCESS DCU INTERRUPT DCU CMC TIME (ONE CMC) (OTHER CMC) TRBL STATE SET BY TRBL TRBL OUT ____________________________________________________________ ______________ 1 1 0 QUIESCENT CMC 1 0 0 1 0 0 QUIESCENT CMC 0 1 0 0 1 0 QUIESCENT CMC 0 1 0 0 0 1 QUIESCENT DCU 1 0 1 then INTERRUPT 1 0 1 QUIESCENT CMC 0 1 0 0 1 1 QUIESCENT CMC 0 1 0 1 1 1 QUIESCENT CMD 1 0 0 DCU-CMC SENSE LINE MP BIT AREAS IN CORE CONTROL Privileged Working Memory Prot Block Init Elsewhere Transfer With Table Bit 25 Trans 0 0 0 Yes Yes No 0 0 1 DCU ERROR 0 1 0 No Yes No 0 1 1 DCU ERROR 1 0 0 Yes Yes Yes 1 0 1 Yes Yes Yes 1* 1* 0 No Yes No) Impossible 1* 1* 1 No Yes No) ____________________________________________________________ ______________ *NOTE -- last two entries are normally impossible

2.2.3.3 Memory Protect Scheme

Bit 25 of all the registers in the DMS is the memory protect bit defining protected or unprotected locations in core (bit set or not set respectively). Bit 1 of the IR sets the DCU in the privileged transfer mode.

In writing drum the memory protect bit 25 will be recorded as it comes from core. In reading the drum, when the privileged transfer bit (bit 19 = 0 in IR) is not set, an error will be detected when the drum word being read has a memory protect bit set. An Error Termination Sequence and a DCU ERROR interrupt will follow. The word will not be written into core. When the DCU is not privileged, only words with bit 25-0 may be written into core. In reading drum when the DCU is privileged, words will be written into core regardless of the status of the memory protect bit 25. Memory protection is extended further by the "WORKING WITH TABLE" sense line. This line is set when the DCU is reading or writing into the initialization table. The two areas in core reserved for data transfers from the DMS are the Initialization Table Area (32 or 64 words) and the Block Transfer Area 2000 words). Table 3 in section 3.2.2 shows the locations in core that may be written for the various combinations of the "Privileged Transfer" control line, "WORKING WITH TABLE" sense line and Memory Protect bit 25. The "NO" entries in Table 3 imply that if an attempt is made to write in these core areas under these conditions, the error will be detected by the CMC.

The drum address of the last word transferred when a memory protect error occurs may be calculated. The word containing the memory protect violation will not be written into core.

Drum address of last word transferred =

dar _initial + 5(lr _initial - lr _final - 2)

where

Dar _initial = location 2 of ITE

Lr _initial = location 0 of ITE (bits 0-14)

Lr _final = location 1 of ITE (bits 0-14) after CPD Spill

2.2.3.4 Core Interface

The DMS is placed on line by the DCU ON LINE control signal from the CMC. This signal enables the DCU READY and DCU ERROR interrupt gates. To test the interface cables and cards all outputs to the CMC may be set to a logic 1 by the TEST CMC INPUTS control from the CMC. Core Address (15 bits and 1 parity) is provided over DCU bus D (FIG. 25). 26 data bits are received from core via bus A and sent to core via bus C.

To read core, the DCU sets a CORE READ REQUEST. Within one interlace period the CMC will select the identifying DCU port and fetch the word at the location defined by the address on bus D of the DCU. When the data is available to the DCU, the CMC sends a DATA AVAILABLE PULSE.

To write core, the DCU sets a CORE WRITE REQUEST. Within one interlace period the CMC will write the data present on DCU bus C at the core location defined by the address on DCU bus D. When complete, the CMC responds with a DATA LOADED PULSE.

2.2.3.5 maintenance

2.2.3.5.1 DCU Error Status Indicators (E/S words).

The following section describes each bit of the three E/S words. The description indicates when each bit is set and reset, drum location and other register status when applicable.

2.2.3.5.1.1 DCU E/S Indicator Word 22

The following is a description of the error/status indicator bits of the DCU indicator word 22.

Bit 0 -- Initialization Sequence (Init. Seq. Ind). Bit 0 is set in the DCU only when the DCU is in its initialization sequence, Bit 0 set in the initialization table indicates an error was detected during the initialization sequence.

Bit 1 -- Error Initialization Sequence (Err Init Seq Status). Bit 1 is set in the DCU when it has been issued a CPD initialize command while in an error interrupt state (DCU ERROR interrupt set). Bit 1 is reset when the ets begins. It must always be reset in the ITE.

Bit 2 -- Write Sequence (Write Seq Ind). Bit 2 is set in the DCU is reading from core and writing on drum. Bit 2 set in the initialization table indicates an error was detected during the Write Sequence for these conditions the LR contains the number of words -2 remaining to be written on drum.

Bit 3 -- Read Sequence (Read Seq Ind). Bit 3 is set in the DCU when it is reading from drum and writing into core. If set in the initialization table, an error was detected during the Read Sequence. The LR contains the number of words -1 remaining to be written into core.

Bit 4 -- Single Level Associative Search (SLAS Ind). Bit 4 is set in the DCU when it is in the SLAS sequence. If an error occurs during this sequence bit 4 will be set in the initialization table in core.

Bit 5 -- Multi Level Associative Search (MLS Ind) Bit 5 is set in the DCU when it is in the MLS sequence. If an error occurs during this sequence, bit 5 will be set in the initialization table in core.

Bit 6 -- Termination Sequence (Term Seq Ind). Bit 6 is set in the DCU during the Termination Sequence. This bit must always be reset in the ITE.

Bit 7 -- Error Termination Sequence (ETS Ind) This bit is set in the DCU, when the machine is dumping the three E/S words into locations 18, 20 and 22 of the initialization table. The bit should be set in the core table.

Bit 8 -- CPD Spill (CPD Spill Ind) The CPD Spill bit is set when CPD requests a dump of all registers and E/S words of the DMS into core. This bit is provided to inform the operator that a CPD spill was requested.

Bit 9 -- CPD Maintenance (CPD Maint Ind). Bit 9 is set in the DCU when the CPD Maintenance Directive is issued. This bit remains set until the next CPD clear is issued. In other words this bit will be set (written) in core by a CPD spill following CPD Maintenance.

Bit 10 -- Maintenance Sequence (Maint Seq Ind). Bit 10 is set in the DCU when it begins executing the DAC Maintenance directive specified in the IR.

Bit 11 -- Write Block Mark. (Write BM Ind). This bit is set in the DCU during the Write Sequence when the last word is written on drum. This bit must always be reset in the ITE.

Bit 12 -- Read Time Out Error (RTOE Err). This bit indicates that response to a CORE READ REQUEST was not received in the proper time.

Bit 13 -- Begin Error Termination Sequence (BETS Ind). This bit is set in the DCU whenever an error is detected. The bit is set in the initialization table if the E/S word dump was preceded by a detected error, as opposed to a CPD spill request and no existing errors.

Bit 14 -- ( - ) En A/D to Core. When bit 14 is reset in the DCU, bus A, C, and D are enabled for a drum read. This bit should always be set in the E/S words of the initialization table.

Bit 15 -- ( - ) En A/D to Drum. When this bit is reset in the DCU, bus A, C, and D are enabled for a drum write. See bit 14.

Bit 16 -- DCU Time Out (DCU Time Out Ind). Bit 16 indicates that a 23 drum revolution time period (approx. 385 ms) has elapsed between a CPD command and a DCU interrupt. The Selected Counter in the PA is captured and loaded into the DAR when the time out occurs.

Bit 17 -- Memory Protect Error (MP Err Ind). Bit 17 is set in the initialization table when an unprivileged DCU attempts to transfer (read a protected word from drum to core). The word causing the error is frozen in the DBR and does not get written into core. The number of words transferred =

LR _I - LR _f - 1

The drum address of the word containing the error may be found by

DA + 5 (LR _I - LR _f - 1)

where

Da = initial drum address

Lr _i = initial contents of LR

Lr _f = final contents of LR

The CAR contains the core address or core +1 of the last word written in core.

Bit 18 -- Block Mark Error -- SLCS (BM Err SLCS Ind) Bit 18 is set in the initialization table when the conditions below do not occur simultaneously during a read drum sequence:

1. LR = 0

2. block Mark Bit = 1

The word in the CBR when the error is detected is frozen and written into core. The drum address of this word may be found:

DA + 5 (LR _I - LR _f - 2)

The number of words transferred =

LR _I - LR _f - 1

(See bit 17 for definition of terms)

The CAR contains the core address or core address +1 of the last word written in core.

Bit 19 -- DAC Error (DAC Error (DAC Err Ind) The Drum Access Circuit Error Indicator is set in the initialization table when an error is detected in the PA or drum access circuits. (See E/S word 20)

Bit 20 -- Initialization Error (Init Err Ind). Bit 20 is set of the DCU is initialized with a data transfer directive in the IR and the DCU is in the READY or ERROR interrupt state.

Bit 21 -- CPD Error (CPD Err Ind) CPD Error is set in the initialization table when the DCU receives a CPD during a DCU active mode (processing). Where the LR is used the number of words transferred may be found by:

LR _I - LR _f - 1

Bit 22 -- Bus A Parity (Bus A Par Err Ind). Bit 22 is set when even parity is detected at Bus A (input bus). During a SLCS drum read, bus A parity error will freeze the word in the DBR and its drum address + 12 will be loaded into the DAR. The word will be parity corrected at bus C and written into core. The CAR contains the core address or core address + 1 of the word written into core. The number of words transferred may be found by:

LR _I - LR _f - 1

When writing drum, bus A parity checks the word from core. An error will freeze the word in the CBR and the word will not be written on drum. The CAR contains the address + 1 of the error detected word. The number of words transferred to drum may be found by:

LR _I - LR _f - 2

Bit 23 -- Bus C Parity (Bus C Par Err Ind). Bit 23 is set when even parity is detected at Bus C (output bus). During a SLCS drum read, bus C parity error will freeze the word in the DBR and its drum address + 12 will be loaded into the DAR. The word is parity corrected at bus C and written into core. The CAR contains the core address or the core address + 1 of the word written into core. The number of words transferred may be found by:

LR _I - LR _f - 1

When writing drum, bus C parity error freezes the word in the CBR, and the word will not be written on drum. The CAR contains the core address + 1 of the error detected word. The number of words transferred to drum may be found by:

LR _I - LR _f - 2

2.2.3.5.1.2 DCU E/S Indicator Word 18

The following is a description of the error/status indicator bits of the DCU indicator word 18.

Bit 0 -- The Previous Word Interrupt bit (PVWI STAT) is set during the PVWI action for the MLS sequence. If an error occurs at this time bit 0 will be set in the initialization table (ITE).

Bit 1 -- The Present Word Interrupt bit (PSWI STAT) is set for one interlace cycle (P ₃ to P ₃ + 1) during the PSWI action of the MLS sequence. If an error occurs at this time bit 1 will be set in the initialization table (ITE).

Bit 2 -- The Level End Interrupt Bit (LEI STAT) is for one interlace cycle (P ₃ to P ₃ + 1) during the LEI action of the MLS sequence. If an error occurs at this time bit 2 will be set in the initialization table (ITE).

Bit 3 -- The Invalid Action Interrupt bit (LAI STAT) is set during the IAI action of the MLS sequence. This action is an error condition, and the DCU will enter the Error Termination Sequence (ETS) and bit 3 will be set in the ITE.

Bit 4 -- The Enter Next Level bit (ENL STAT) is set for one interlace cycle (P ₃ to P ₃ + 1) during the ENL action of the MLS sequence. If an error occurs at this time bit 4 will be set in the ITE.

Bit 5 -- The drum Modify Mark Register bit (DMMR STAT) is set during the DMMW action of the MLS sequence. If an error occurs at this time bit 5 will be set in the ITE.

Bit 6 -- The Drum Modify Search Register Bit (DMSR STAT) is set during the DMSW action of the MLS sequence. If an error occurs at this time bit 5 will be set in the ITE.

Bit 7 -- The Reset Read Latch bit (RRL STAT) is set for one interlace cycle (P ₃ to P ₃ + 1) of the RRL action of the MLS sequence. If an error occurs at this time bit 7 will be set in the ITE.

Bit 8 -- Level 2 or level 3 bit (L ₂ + L ₃ ), this bit is set when the DCU is in level 2 or level 3 of the MLS Sequence. If an error occurs while in either level bit 8 will be set in the ITE. If a CPD spill is initiated after an MLS sequence and this bit becomes set in the ITE, the MLS sequence terminated in level 2 or level 3. To determine which level, it is necessary to refer also to bit 9 of E/S word 18.

Bit 9 -- Level 1 or Level 3 bit (L ₁ + L ₃ ), this bit functions the same as the preceding bit 8 except, bit 9 indicates the MLS sequence terminated in level 1 or 3.

Bit 10 -- The drum Modify Mask Word bit (DMMW BIT) is set if the drum has overwritten the mask register, and will remain set until the DCU enters the next level of MLS sequence. If an error occurred during this time bit 11 will be set in the ITE.

Bit 11 -- The drum Modify Mask Word bit (DMMW BIT) is set if the drum has overwritten the mask register, and will remain set until the DCU enters the next level of MLS sequence. If an error occurred during this time bit 11 will be set in the ITE.

Bit 12 -- The Drum Modify Search Word bit (DMSW BIT) is set if the drum has overwritten the search register, and will remain set until the DCU enters the next level of MLS sequence. If an error occurred during this time bit 12 will be set in the ITE.

Bit 13 -- The Read Control Bits bit (READ CTL BITS) is set when the MLS sequence is scanning the CBR and DBR control bits (21-23). The scanning of control bits starts with coincidence to enter a level and continues until a reset read latch or interrupt action is entered. This bit 13 must always be 0 in the ITE.

Bit 14 -- The Level End Interrupt Flag bit (LEIF) is set when level 1 or 2 coincidence cannot be found for a MLS sequence. This bit will also be set if, for a SLAS or MLS sequence with a counter start, a block mark is detected after counter coincidence (Z counter) and prior to associative coincidence (Z assoc.).

Bit 15 -- The Pulse Distributor Bit 1 (PAD BIT 1) is set for the counts of P ₂ and P ₄ but must always be 0 in the ITE.

Bit 16 -- The Pulse Distributor Bit 2 (INTERL STRAP 6) is set for the counts of P ₃ and P ₄ , but must always be 0 in the ITE.

Bit 17 -- The Pulse Distributor Bit 3 (PD BIT 3) is set for the count of P ₅ , but must always be 0 in the ITE.

Bit 18 -- The Associative Search Sequence bit (ASSEQ) is set when the DCU is in a SLAS or MLS sequence, but bit 18 must always be 0 in the ITE.

Bit 19 -- The Distributor Enable bit (DIST EN) is set when the Pulse Distributor is enabled, but bit 19 must always be 0 in the ITE.

Bit 20 -- The Invalid Action Interrupt Error bit (IAI ERROR) is set if there is an invalid combination of control bits, read latch status, coincidence status, and MLS sequence level. This invalid combination will cause an error interrupt and bit 20 in the ITE will be set.

Bit 21 -- The Block Mark Error bit (BM ERROR BIT) is set if the DCU is performing a SLAS counter start sequence and a block mark is detected after associative coincidence and before the last word of the transfer. This error will cause an error interrupt and bit 21 in the ITE will be set.

Bit 22 -- The Pulse Distributor Skew bit (PD SKEW) is set when the pulse distributor and the DAC interlace counter are not in synchronization. This will cause an error interrupt and bit 22 in the ITE will be set.

Bit 23 -- The Invalid Operation Code bit (INVALID OP) is true when the OP Code field of the instruction register is invalid. This will cause an error interrupt and bit 23 in the ITE will be set.

2.2.3.5.2 DAC Error/Status Indicators

A 24 bit word for storing a record of the operational status of the DAC circuitry has been assigned to the DAC. This word will be stored at address 20 of the Initialization Table as a result of a DCU error termination sequence or a CPD spill. These 24 bits indicate the status of 19 error detectors and 5 status monitoring points in the DAC. A bit set to 1 denotes the true condition in all cases. Bits 0 through 8 are assigned to Peripheral Adapter; bits 9 through 15 are assigned to the Clock Circuits; bit 16 indicates Block Mark status for the word currently in the DBR; and bits 17 through 23 are assigned to the Recording Circuits. A description of each indicator bit follows.

2.2.3.5.2.1 DAC Error Detector and Status Indicator Descriptions

Bit 0 -- Mode Error - Indicates a discrepancy between the RWI bit of the Drum Address Register (DAR) and the directive in the instruction register, the error latch will be set on the trailing edge of the first DCP1 after READ ENABLE or WRITE ENABLE (from DCU becomes true).

Bit 1 -- Invalid Segment Error -- Indicates that an attempt has been made to select a segment that is not assigned to that particular DCU. The error latch will be set when ROUTE TO DAR is sent from the DCU to the PA. DAC ERROR will not be enabled until READ ENABLE or WRITE ENABLE becomes true.

Bit 2 -- Protected Segment Error -- Indicates that an attempt has been made to write in a read only segment. The error latch will be set when WRITE ENABLE becomes true. This error indication can be inhibited by operating a manual switch which is mounted on the Segment Decode card.

Bit 3 -- Binary Counter Error -- Detects a binary counter failure or the absence of counter clock or reset pulses. The error latch will be set on the first Drum Reset Pulse (DRP) after the error occurs. DAC ERROR will not be enabled until READ ENABLE or WRITE ENABLE becomes true.

Bit 4 -- BCD Counter Error -- Detects a BCD counter failure or the absence of counter clock or reset pulses. The error latch will be set on the first Drum Reset Pulse (DRP) after the error occurs. DAC ERROR will not be enabled until READ ENABLE or WRITE ENABLE becomes true.

Bit 5 -- DAC Parity Error -- Detects a parity error in the data in the Drum Buffer Register (DBR). The error latch will be set appr. 450 ns after the word is loaded into the DBR. The count sent to the Drum Address Register (DAR) when the error occurs will be the data words address + 8 for a write operation.

Bit 6 -- Route Error -- The error occurs if

1. a Route to DAR is sent while the PA is active

2. a Route to DBR is sent while the PA is inactive.

The error latch will be set on one of these two signals depending upon the fault location:

Bit 7 -- PA Active -- PA Active is a storage element which is set when the PA is transferring data to or from the Drum. It is set by either counter coincidence (Z COUNTER) or associative search coincidence (Z ASSOC) and is reset at the end of a transfer when the DCU drops READ ENABLE or WRITE ENABLE.

Bit 8 -- Enable Binary Capture - This storage element indicates which counter is transferred to the address bits of the DAR. If set, the binary count is sent to the DAR at the appropriate times; if reset, the BCD count will be sent to the DAR. It is set by ROUTE TO DAR ^. DAR22 or a DAC Parity Error. It is reset by ROUTE TO DAR ^. DAR22.

Bit 9 -- Auxiliary MRP 1 Error - Detects an absence of DRP pulses. The error latch which is set during a master MRP, enables DMS Clock Track Error which causes an immediate DCU Error Interrupt.

Bit 10 -- Auxiliary MRP 2 Error -- same as Aux. MRP 1 Error.

Bit 11 -- Auxiliary DIP 1 Error -- Detects the absence of Drum Index Pulses (DIP). The error can occur randomly. The latch will be set immediately, enabling DMS Clock Track Error.

Bit 12 -- Auxiliary DIP 2 Error -- Same as Aux. DIP 1 Error.

Bit 13 -- Drum Speed Error -- Detects when the drum speed drops below an operable level. The latch will set immediately, enabling DMS Clock Track Error.

Bit 14 -- Master Track Error -- Detects the absence of master MRP. The detector circuitry checks for the presence of an MRP for each auxiliary DRP. This detector will also be set by the absence of a DIP. This Error does not cause DMS Clock Track Error.

Bit 15 -- DIP Skew Error -- Detects skew between the auxiliary DIP tracks. The error can occur randomly and does not cause a DMS Clock Track Error.

Bit 16 -- BM 26 DCU/WR -- This indicator denotes the status of the Block Mark bit of the word currently in the DBR. A 1 specifies that the BM bit is set. The indicator is set or reset each time a word is loaded into the DBR.

Bit 17 -- Head Select Input Error -- This detector is set by a 1 - out - of - 18 circuit which monitors the segment select input to the Memory Protect Circuit and is set if none or more than one segment has been selected. The error latch will be set appr. 15 microsec after ROUTE TO DAR and before READ ENABLE or WRITE ENABLE becomes true.

Bit 18 -- Head Select Output Error -- Same as Head Select Input Error except the monitor point is at the output of the Memory Protect Circuit.

Bit 19 -- Access Circuit Error - The error is detected on the DAC Write/Read Control Circuit and is gated in the PA so that DAC ERROR is not enabled until READ ENABLE becomes true.

Bit 20 -- Write Control Error -- Checks the integrity of write control signals to the write/read circuits. The error signal is gated in the PA.

Bit 21 -- MPC Write Inhibit -- This detector does not cause DAC ERROR directly. The signal sent to the DAC ERROR gate is MPC ERROR which cannot become true until either READ ENABLE or WRITE ENABLE becomes true.

Bit 22 -- Power Supply or Drum Speed Error -- Gated in the PA so DAC ERROR does not become true until READ ENABLE or WRITE ENABLE becomes true.

Bit 23 -- + 5V Redund Error -- Monitors the redundant power supply of the Memory Protect Circuit. The error signal is gated in the PA.

2.2.3.5.2.2 dac forced Error Checks

Simulated faults are forced into the DAC via an instruction register directive called DAC Maintenance. Ten simulated faults and a clock transfer feature are initiated by the same directive. The simulated faults provide a means of checking DAC error detectors that cannot be checked by forcing software errors. The clock transfer causes the alternate auxiliary clock track to be switched on-line and does not cause an error.

The first entry in the Initialization Table provides all the control and data information required for DAC maintenance. The format is shown below. ##SPC35##

Bits 0 through 15, except for the clock transfer bit (10), are error simulator bits. They are divided into three groups, the peripheral adapter, the clock circuits and the recording circuits. A logic 1 in bit 16, 17 or 18 will cause the circuitry to enable the appropriate group of simulator bits. It is possible to enable more than one group simultaneously or more than one error simulator within a group simultaneously. When writing programs, care will have to be taken to insure that only those bits associated with the fault to be simulated are set to logic 1. All others should be at logic 0. Bits 20 through 23 form the instruction word directive which sets up the DCU circuitry for a DAC maintenance operation.

The DAC maintenance directive is initiated by DCU Initialization CPD. After the first entry in the Initialization Table has been written into the Instruction Register of the DCU, bits 20 through 23 are decoded.

After recognizing the decoded directive as DAC maintenance, the DCU sends Instruction Register bits 0 through 18 and an enabling pulse (ROUTE ERR SIM) to the Error Simulator Circuit of the DAC. If bit 16, 17 or 18 is at logic 1 and one of the error simulator bits is also at logic 1, the Error Simulator Circuit will force a simulated fault in the appropriate circuit. For example, if bits 16 and 0 are at logic 1, the INHIBIT DRP error simulator signal will inhibit the resetting of the address counters after the maximum count (10,998) has been reached. This will cause the counter error detectors to be set. An error detector being set will cause DAC Error to be sent to the DCU, resulting in a DCU error interrupt. The DCU will go through its error termination sequence. Word 20 of the Initialization Table, the DAC error indicators, will be checked to see if the appropriate indicators were set. If so, it can be assumed that the detectors functioned properly.

The signal that forces the simulated fault will remain at a constant level until reset by the CPD CLEAR. If more than one error detector is to be checked in sequence, the DCU will be reinitialized for each individual test.

Error simulator signals, instruction register bits that must be set for each, and the word 20 indicator bits that will be set as a result of the simulated fault are listed on the next page.

DAC MAINTENANCE ERROR SIMULATOR ____________________________________________________________ ______________ LISTING FAULT SIMULATOR INSTRUCTION ERROR DETECTORS SET LEAD NAME REGISTER BITS AS RESULT OF SET TO LOGIC 1 SIMULATED FAULT COMMENTS ____________________________________________________________ ______________ INHIBIT DRB 16, 0 DAC ERR 3 -- BIN CTR ERR INHIBITS RESET OF PA DAC ERR 4 -- BCD CTR ERR ADDRESS COUNTERS. HOLD CTR RST 16, 1 DAC ERR 3 -- BIN CTR ERR HOLDS PA ADDRESS DAC ERR 4 -- BCD CTR ERR COUNTERS IN A RESET STATE. ADVANCE COUNT 16, 2 DAC ERR 3 -- BIN CTR ERR FORCES ADDRESS COUNTERS DAC ERR 4 -- BCD CTR ERR TO REACH MAX. COUNT EARLY. DECODE INHIBIT 16, 3 DAC ERR 3 -- BIN CTR ERR SIMULATES THE EFFECT OF DAC ERR 4 -- BCD CTR ERR MISSING COUNTER CLOCK PULSES. MRP ERR SIM 17, 6 DAC ERR 14 -- MASTER TRK ERR ERROR WILL BE FORCED ON WHICHEVER (DAC ERR 9 -- AUX MRP 1 ERR + TRACK IS ON-LINE THE FORCED ERROR DAC ERR 10 -- AUX MRP 2 ERR) WILL CAUSE A CLOCK TRANSFER. DIP ERR SIM 17, 7 DAC ERR 14 -- MASTER TRK ERR ERROR WILL BE FORCED ON WHICHEVER (DAC ERR 11 -- AUX DIP 1 ERR + TRACK IS ON-LINE. THE FORCED ERROR DAC ERR 12 -- AUX DIP 2 ERR) WILL CAUSE A CLOCK TRANSFER. SPEED/SKEW SIM 17, 8 DAC ERR 13 -- DRUM SPEED ERR DAC ERR 15 -- DIP SKEW ERR DAC ERR 22 -- PS DRUM SPD ERR TRANSFER CLOCK 17, 10 none 500 NSEC. TRANSFER CLOCK PULSE. FAIL TEST INPUT 18, 11 DAC ERR 17 -- HS INPUT ERR FORCES ERROR IN 1 OUT OF 18 DETECTOR MONITORING SEGMENT SELECT CKT OUTPUTS. FAIL TEST OUT 18, 12 DAC ERR 18 -- HS OUTPUT ERR FORCES ERROR IN 1 OUT OF 18 DETECTOR DAC ERR 19 -- ACCESS CKT ERR MONITORING HEAD SELECT CKT OUTPUTS. MPC FAIL SIM 18, 13 DAC ERR 22 -- PS DRUM SPD ERR DAC ERR 19 -- ACCESS CKT ERR ____________________________________________________________ ______________

2.2.3.5.3 dcu time Out

The DCU Time Out sense line causes the DCU ERROR interrupt and indicates that DMS processing cannot continue because of a hardware or software error not covered by the detection circuits. In other words, the DMS is stuck somewhere, and the E/S words may indicate where. There are some cases, however, where E/S words are not available for analysis (such as core access or ETS difficulties) in which case the sense lines must be used. Certain core access troubles cause DCU TIME OUT indications -- see section 4.4 for complete coverage of core access problems and related sense line status.

After the DCU TIME OUT is detected (DCU ERROR interrupt set) a period of eight interlace periods (approx. 60 μs on interlace 5) must elapse before error/status indicators may be used. In other words a software wait may be used by checking the DCU ERROR/STATUS IN CORE sense line. When set the E/S words are available in core for diagnostics.

2.2.3.5.4 Core Access Problems

Unique problems may arise which cause core access difficulties. The CORE ACCESS TRBL sense line is a monitor of the core request time out circuits. Certain core access trouble conditions could cause the CMC to set its CMC PORT MALFUNCTION in both CMC's. When this occurs, and the CORE ACCESS TRBL line is set or not set, the DCU will enter a state of quiescence (not idle, not ready, and not active). The DCU will sit in this state (without sending an interrupt) until another CPD is issued. The interrupt is sent by the CMC. In all cases (except for a certain prot malfunction) it may be concluded that the DMS contains the fault. The DMS may be accessed via CPD for diagnostics. Localization can be accomplished by running routines based on possible DMS error conditions.

If the PORT MALFUNCTION sense line of one CMC is set and the CORE ACCESS TRBL line of the DCU is set or not set, the DCU again enters the quiescent state, but the fault is in the CMC. The interrupt in this case is set by the CMC.

In the final case where the DCU has trouble accessing core (CORE ACCESS TRBL Set) and the PORT MALFUNCTION line is not set, the DCU will enter its quiescent state until a DCU ERROR interrupt is set by the DCU time out circuits (about .5 sec.).

These decisions are shown in the lower right of the flow chart in FIG. 34 beginning at D. Table 2 in section 2.2.3.2.2 shows at a glance the states of the DCU in the event of core access difficulties. This approach is used to insure that interface errors of this nature will not cause more than one interrupt to the CCP.

DMS APPENDIX I

FORMAT OF DMS REGISTERS

1. initialization Address Register -- IAR (15 bits)

This register consists of a 5 bit binary counter and a strapping field for the high order 10 bits. It is used to form the address for accessing the Initiation table entry (ITE) in main core memory during the initiation cycle or during the storage of all DMS registers into the ITE (caused by a spill CPD). When an Initialize CPD is issued, the low order 5 bits will be set to 0. This requires the ITE to begin at a location divisible by 32.

2. Core Address Register -- CAR (26 bits)

The low order 15 bits of this counter and storage register are used to access main core memory during all active processes other than the processes for which the Initialization Address Register is used. This address, loaded during initialization, is used to specify the starting core address where the data transfer between core and the drum will take place. Bits 15-20 are not programmable. The tag field (bits 21, 22, 23) are not used by the DCU and may be used to aid programs. When the DCU executes the error termination sequence, bits 15 through 19 will contain the low order 5 bits of the LAR.

3. limit Register (14 bits)

This is a 14 bit binary counter and storage register. For single level counter start, the number of words to be transferred is loaded into this register during the initialization cycle. The limit register is also used for indexing in the SLAS mode refer to DMS Appendix II.

4. instruction Register (12 bits)

This is a 12 bit storage register used to hold the DCU directive (4 bits) and the directive extension (6 bits); refer to DMS Appendix II.

5. core Buffer Register -- CBR (26 bits)

This is a 26 bit storage register used to buffer words which are written or read into core memory.

6,7,8. Information Search Register - ISR1, 2, 3 (26 bits)

These storage registers (one for each level of search) specify the drum address or data coincidence to be encountered to enter their respective levels of associative search. These registers are normally loaded during the initialization sequence however, the second and third can be modified with information on drum when specified by the control bits. When coincidence is found these registers will be loaded with the drum address +8 of the level 1,2,3 coincidence word respectively.

9,10,11. Information Mask Register -- IMR (26 bits)

These storage registers (one for each level of search) are provided to facilitate a masked associative search. These registers are loaded at initialization time similar to the Information Search registers. When each level of coincidence is found IMR1, 2, 3 respectively, will be loaded with the Core address register which contains the location of the coincidence word in core. The high order bit (23) of IMR 2 and 3 will be set if the corresponding search register was overwritten with a word from drum. Bit 22 will be set if the mask word was overwritten after initialization.

12. Drum Buffer Register -- DBR (27 bits)

This is a 27 bit register used to buffer words read from (written onto) Drum.

13. Drum Address Register -- DAR (26 bits)

This 26 bit register has the following format:

______________________________________ RWI CS Space Segment ADD ______________________________________ 23 22 20 16 15 0 ______________________________________

Address field -- this field is used to specify a location on the drum. The value of this field will vary from 0 to 10,998 (Binary or BCD).

Segment -- This field is used to specify a segment for a read (write) operation. Its value can vary from 0 to 18 depending on the number of DCU's assigned to a drum.

Counter select (CS) bit (bit 22)

This bit is used to select the counter BCD or Binary, to be used in accessing the drum via the angular index value. It also specifies which counter should be retrieved in the associative search mode.

Cs = 1 use modified BCD

Cs = 0 use Binary

Read/Write instruction (RWI) bit -- (bit 23) this bit must be set if the DCU is to write on drum.

Rwi = 1 write

Rwi = 0 read

14. Angular Index Counters

A standard binary and modified BCD counter is required for each DAC peripheral Adapter. The range of this counter is from 0 to 10,998. This counter will be reset by the drum reset pulse. This is not a standard BCD counter because of the requirements that the high order 4 bit stage count from 1 to 9 to 0 rather than 0 to 9. Also 0 in base 10 is represented by the bit pattern 1010. This counter is also reset by the drum reset pulse. The relationship between the values of each counter is illustrated in DMS Appendix III.

DAC ANGULAR INDEX COUNTERS ______________________________________ INTERLACE DECIMAL ADDRESS BINARY COUNTER BCD COUNTER ______________________________________ 0 5 00000000000000 0001101010101010 1 1 1 0001 2 2 10 0010 3 3 11 0011 4 4 100 0100 5 5 101 0101 6 1 110 0110 7 2 111 0111 8 3 1000 1000 9 4 1001 1001 10 5 1010 00011010 100 5 00000001100100 000110101010 1000 5 00001111101000 0010101010101010 9000 5 10001100101000 1010101010101010 10000 5 10011100010000 1011101010101010 10998 3 10101011110110 1011101010101000 0 4 00000000000000 0001101010101010 1 5 00000000000001 0001101010100001 ______________________________________

DMS APPENDIX II

DMS INSTRUCTION REGISTER AND CPD DIRECTIVES ##SPC36##

OP = Bits 23 thru 20 = 7 = (0111) ₂ PT = In WRITE DRUM Sequence, the PT is meaningless. BM = Bit 18 -- if bit 18 is true a block mark will be written on the drum along with the last word transferred. LIMIT = Bits 0 thru 13 the limit portion of the directives specifies the number of words to be read from core and written on the drum. Bits = 14 thru 17 are not decoded or used during this operation. Cycles = I + S + N (T) + ES + TERM/CORE CYCLE TIME I = 45.4 μsec = Initialize A = 0 to 16666 μsec = SEARCH N = number of words written/read T = 7.56 μsec = TRANSFER TIME PER WORD ES = 0 to 7.56 μsec = END SEQUENCE TERM = 7.56 μsec = TERMINATION

DRUM READ SINGLE LEVEL COUNTER START ##SPC37##

OP = Bits 23 thru 20 = 6 (0110) ₂ PT = Bit 19 -- if bit 19 is true the controller will assume a privileged transfer status for the entire transfer. BM = Bit 18 -- if bit 18 is true the controller will make a check for a block mark when the last word is read from drum. If the bit is false this check will be bypassed. It will check if BM comes true before LR = 0, or if LR = 0 and BM not true. LIMIT = Bits 0 thru 13 the limit portion of the directive specifies the number of words to be read from drum and transferred to core. Bits 14 thru 17 are not decoded or used during this operation Note: If PT is not set, the words may be transferred only to an unprotected area in core. Any attempt to write a word from drum to core when bit 25 of that word is a "1", will cause an error and being error sequence. Refer to Drum Write for calculating core cycle per task.

DRUM READ ROUTINE (SLCS) ##SPC38##

OP = Bits 23 thru 20 = 16 ₈ = (1110) ₂ BM = Bit 18 -- if bit 18 is true the controller will make a check for a block mark when the last word is read from drum. It will check if BM comes true before LR = 0. If the bit is false this check will be bypassed. LIMIT = Bits 0 thru 13 the limit portion of the directive specifies the number of words to be read from drum and checked for proper parity. Bits = 14 thru 17 are not decoded or used during this operation. Note: Refer to Drum Write for calculating core cycles per task.

SINGLE LEVEL ASSOCIATIVE SEARCH ##SPC39##

OP = Bits 23 thru 20 = 5 = (0101) ₂ PT = Bit 19 -- if bit 19 is true the controller will assume a privileged transfer status for the entire transfer. INDEX = Bits 0 thru 13 the index portion of the directive specifies the number of words to SKIP after information coincidence until a transfer to core memory will begin. LIMIT = Bits 14 thru 18 the limit portion of the directive specifies the total number of words to be read from drum and written into core. NOTE* Associative searching is performed in interlace 1, every word is examined. After information coincidence indexing and transfer will take place at the DCU interface rate. CYCLES = I + S + T (N + 1) + ES + TERM/CORE CYCLE TIME I = 75.6 μsec S = 0 to 16666 μsec T = 7.56 μsec N + 1 = Number of words read + coincidence word ES = 0 to 7.56 μsec TERM = 7.56 μsec

SINGLE LEVEL ASSOCIATIVE SEARCH ROUTINE ##SPC40##

OP = Bits 23 thru 20 = (15) ₈ = (1101) ₂ INDEX = Bits 0 thru 13 the index portion of the directive specifies the number of words to skip after information coincidence before the read latch is set. LIMIT = Bits 14 thru 18 the limit portion of the directive specifies the number of words to be read from drum with the read latch set. NOTE: Refer to Single Level Associative Search for calculating core cycles per task.

SINGLE LEVEL ASSOCIATIVE SEARCH COUNTER START ##SPC41##

OP = Bits 23 thru 20 = 4 = (0100) ₂

Bit 23 = Routine all operations will be performed with the exception of writing into core memory. NOTE* After counter coincidence associative search will be performed at the DCU interlace rate. CYCLES = I + S + 5 (S) + T (N + 1) + ES + TERM I = 75.6 μsec. = INITIALIZE S = 0 to 16666 μsec -- SEARCH N + 1 = Number of words read + associative coincidence word. T = 7.56 μsec = TRANSFER TIME PER WORD ES = 0 to 7.56 μsec = END SEQUENCE TERM = 7.56 μsec = TERMINATION

MULTI-LEVEL ASSOCIATIVE SEARCH AND ROUTINE ##SPC42##

OP = Bits 23 thru 20 = 3 = (0011) ₂ PT = Bit 19 -- if bit 19 is true the controller will assume a protected status for the entire transfer. A = Bit 14 -- if bit 14 is true the first level of search will be a counter coincidence. If false it will be associative with MR1 and SR1. B = Bit 15 -- if bit 15 is true the second level of search will be a counter search. If false the search will be associative with MR2 and SR2. C = Bit 16 --if bit 16 is true the third level of search will be a counter search. If false the search will be associative with MR3 and SR3. CS = Counter Start. If OP code OP = 2 - (0010) ₂ is true the first level of associative search will begin after counter coincidence. Bits = 0-13 are not used and not decoded. Bit 23 = Routine: All operations will be performed with the exception of writing into core memory. NOTE* Once the first coincidence is found all succeeding associative searches and transfers take place at the DCU interlace rate. All counter searches will be on interlace 1. CYCLES = LEV1 + LEV2 + LEV3 + ES + TERM LEV 1 = I + S + N (T) if level 1 is a counter start add the term 5(S) for searching an interlace five LEV 2&3 = if searching for associative coincidence = LD + W + S + N (T) ES = - to 7.56 μsec = END SEQUENCE TERM = 7.56 μsec = TERMINATION I = 136.2 μsec = INITIALIZE S = 0 to 16666 μsec -- SEARCH N = number of words read T = 7.56 μsec = TRANSFER TIME PER WORD LD = 7.56 μsec = LOAD DAR W = 0 to 15.0 μsec = WAIT FOR SEGMENT SELECTION

DCU DIRECTIVES AND FORMATS

The binary codes for the directives are summarized below. A more elaborate description is found within.

INSTRUCTION REGISTER BITS 23 22 21 20 DIRECTIVE DESCRIPTION ______________________________________ 0 0 0 0 INVALID OP CODE 0 0 0 1 INVALID OP CODE 0 0 1 0 MULTI LEVEL ASSOCIATIVE SEARCH- COUNTER START 0 0 1 1 MULTI LEVEL ASSOCIATIVE SEARCH 0 1 0 0 SINGLE LEVEL ASSOCIATIVE SEARCH-COUNTER START 0 1 0 1 SINGLE LEVEL ASSOCIATIVE SEARCH 0 1 1 0 READ DRUM -- BLOCK TRANSFER 0 1 1 1 WRITE DRUM -- BLOCK TRANSFER 1 0 0 0 INVALID OP CODE 1 0 0 1 DAC MAINTENANCE 1 0 1 0 MULTI LEVEL ASSOCIATIVE SEARCH- COUNTER START -- ROUTINE 1 0 1 1 MULTI LEVEL ASSOCIATIVE SEARCH -- ROUTINE 1 1 0 0 SINGLE LEVEL ASSOCIATIVE SEARCH- COUNTER START --ROUTINE 1 1 0 1 SINGLE LEVEL ASSOCIATIVE SEARCH-- ROUTINE 1 1 1 0 READ DRUM ROUTINE 1 1 1 1 INVALID OP CODE ______________________________________

DAC MAINTENANCE CONTROL ##SPC43##

Op = bits 23 thru 20 = 11 = (1001) ₁₁

This code will routine the error checking circuits of the DAC. For example, to check the PA circuits, bit 16 is set and any or all of bits 0-4 are set to check the circuits which correspond to each bit.

CPD CONTROL

The control between the CPU and DCU is as follows:

1. CPD Clear (DLO=0, DL1=0) 2. CPD Initialize (DL0=1, DL1=0) 3. CPD Spill* (DL0=0, DL1=1) 4. CPD Maintenance** (DL0=1, DL1=1)

The DCU must receive a CPD Clear before any data transfer may be executed via initialization.

At the completion of a data transfer or the completion of an Error Termination Sequence, the DCU will interrupt the DCU with a READY or ERROR interrupt respectively.

With the READY or ERROR interrupt set, the DCU may be called to execute a CPD Spill, a DMS Maintenance Sequence, or a CPD Maintenance The DCU will reset the interrupt upon execution of the command, and then set the previous interrupt. Any attempt to initialize for a data transfer (Block Transfer or Associative Search) will begin an Error Termination sequence and cause an ERROR interrupt. The DCU may be initialized for Maintenance, however.

This flow of DCU sequences is made clear by the attached flow chart, FIG. 34. The chart shows the normal sequential flow of the DCU for data transfers and errors. It also makes clear the consequences of a programming violation.

*CPD Spill. The CPD spill directive dumps all the registers of the DCU and CMS, and the error/status bits of the DMS.

The DAC error checking circuits may be routined by the DAC Maintenance word via initialization.

**The DCU error checking circuits and the parity circuits may be routined by the CPD Maintenance. This command causes the instruction in the IR to be routined.

APPENDIX III

INITIALIZATION TABLE FORMAT

The initialization format is a map of the initialization area in core. Each DCU has its own assigned initialization area in core. The even numbered location 0-16 contain all the pertinent information necessary to specify a drum task, refer to the following table. After the DCU has completed initialization the odd numbered location 1-17 will contain the image of their preceding even location. This is to verify that the information was accurately loaded into the DMS registers. If the drum task was completed successfully, location 24 will contain the last CAR address. If an error occurred, the error termination sequence will load the DAC and DCU error/status words in locations 18, 20 and 22.

After a CPD spill directive the odd numbered loications 1-23 and locations 18, 20, 22 and 24 will be updated with CPD spill format, refer to the following table. ##SPC44## ##SPC45##

3.0 CHANNEL MULTIPLEXOR

3.1 introduction

3.1.1 operational Description

The Computer Channel Multiplex (CCX) provides communication paths for I/O buses of the two CCP(S) up to sixteen controllers. Its functions are:

A. route output data and control data from either CCP to any one of sixteen controllers.

B. route input data from any one of the controllers to both CCP I/O buses so that both CCP's may operate synchronously.

C. check and verify that output and control data is received by the controllers and that controller parity checks are satisfied.

D. route I/O device controller interrupts and sense line data to the Interrupt and Sense Line Circuits.

E. decode and store I/O controller selected.

F. check that only one Controller is selected at a time.

G. interpret Channel Multiplex CPD instructions such that maintenance and reconfiguration may be performed on the CCX.

Except for the interface between the CCX and Controllers, the CCX may be considered to have two identical halves. Each half is associated with a CCP. The CCX operates on ACTIVE/STANDBY basis, only half can be active at a time. Either half may be made active only when its associated CCP is on line. Thus for synchronous CCP(s) operations, either half, but not both, may be active. For simplex CCP operations only the half associated with the on line CCP can be active.

The interface between the CCX and the Controllers are powered by two separate power modules: the odd numbered Controllers by one and the even numbered Controllers by the other, such that a failure in either power supply will not cause loss of all Controllers. (Note that duplicated Controllers are assigned odd and even identities).

3.1.2 Data and Instruction Format

There are three categories of instructions related to the CCX operations:

1. SEL Directives

2. Data Transfer Instructions (LDC, CCD, STL, CCI)

3. ccx cpd instructions.

3.1.3.1 SEL Directives: (Refer to section 1.2 page 1.2-28)

These are I/O Command Words for assigning a Controller to the CCX and/or a Device to the Controller. They are also used for sending control codes to the Controller/Device assigned. Once a Controller is assigned to the CCX, it will remain so until another Controller is assigned to the CCX by a subsequent SEL instruction, a Disconnect SEL instruction for that particular Controller, or a CPDCX7 is executed.

The format of the I/O Command Word (which is the effective address of the SEL instruction) is as follows: ##SPC46##

I -- arm I/O Ready Interrupt

C -- channel Controller Identity -- There can be a maximum of 16 controllers. The lower order bit of the C field (bit number 9) will be used to specify the odd or even controller.

X -- x field -- The X field is used in conjunction with the Y & Z fields to form a directive for the controller or peripheral adapter. A value of zero for the X field specifies that the Y & Z fields should be interpreted as controller directives. Non zero values of the X field are used to specify a particular peripheral adapter on a controller or as a directive extension. The X field is only used for directive extension, when the Y & Z field directives are exhausted or for maintenance.

Y -- y field -- The Y field is used as a directive modifier to the Z field directive for both controller and peripheral adapter directives.

Z --z field -- The Z field is used as a general directive field for controllers and specific directive field for peripheral adapters.

The Controller Codes are as follows:

C Field CONTROLLER NAME CONTROLLER NO. ______________________________________ 00 Channel Device Buffer A 1 01 Channel Device Buffer B 2 02 Ticketing Device Buffer A 3 03 Ticketing Device Buffer B 4 04 Maintenance Device Buffer 5 05 Channel Device Buffer 6 06 Communication Register A 7 07 Communication Register B 8 ______________________________________

3.1.2.3 data Transfer Instructions: (Refer to section 1.2)

There are a total of nine CPD instructions related to the CCX:

Cpdcxo -- put CCXA On-line (017 00001)

Cpdcx1 -- put CCXB On-line (017 00002)

Cpdcx2 -- put CCXA Off-line (017 00004)

Cpdcx3 -- put CCXB Off-line (017 00010)

Cpdcx4 -- make CCXA Active and CCXB Standby (017 00020)

Cpdcx5 -- make CCXB Active and CCXA Standby (017 00040)

Cpdcx6 -- reset CCX Errors (017 00100)

Cpdcx7 -- initiate Select Storage Check Routine (017 00200)

Cpdcx8 -- end Select Storage Check Routine (017 00400)

CPDCX0 through CPDCX3 are for removing a faulty half of the CCX off line for repair or putting a repaired half back to service.

CPDCX4 and CPDCX5 are for selecting which half of the CCX should be active.

CPDCX6 is for resetting all CCX error conditions.

CPDCX7 and CPDCX8 are for routining the error checking circuitry in the CCX. CPDCX7 informs the CCX that the following data transmission should be gated to the Select Storage in the CCX. This instruction will also disconnect any Controller from the CCX. DPCDX8 terminates data output to be gated to the Select Storage.

3.1.3 Status Indicators and Interrupt Stimuli

3.1.3.1 Select Error Check

This is a one out of sixteen check. It monitors the output of the Channel Select Storage, which contains the Selected Channel Controller Identity. Thus on a Select Instruction, if none or more than one, controller is selected, this Select Error Check will flag an error, (Sense Lines 74100 and/or 74200). This error will abort the affect of the SEL instruction and the channel buffers will not be initialized. In addition to the above, sense lines 07100 and/or 07200 will also be true.

The Channel Select Storage output is displayed on sense lines. (See Section 3.1.4 for Group and Line Number). The error can be reset by the execution of a RESET CCX ERROR (CPDCX6) instruction.

3.1.3.2 Time Out Error

This is used to check proper instruction and output data transfer from the CCP through the CCX to the selected controller. Specifically, upon receiving a select instruction or a data output instruction, the selected controller will check the parity of the information received. A Verify Strobe will be sent back to the CCX signifying all is well. Failure to receive this Verify Strobe by CCP timing period C1L2P2 of the next instruction will cause the CCX to indicate an error (Sense Lines 07100 and/or 07200). The identity of the selected controller that failed to return the Verify Strobe is stored in the CXX and is available through the sense line. (See Section 3.1.4 for Group & Line Number). All errors are reset by CPDCX6 instruction.

______________________________________ 3.1.4 SENSE LINES Channel Time Out (Group 47) ______________________________________ 57001 SCTOERR 1 Channel 1 Time Out Error 57002 SCTOERR 3 Channel 3 Time Out Error 57004 SCTOERR 5 Channel 5 Time Out Error 57010 SCTOERR 7 Channel 7 Time Out Error 57020 SCTOERR 9 Channel 9 Time Out Error 57040 SCTOERR 11 Channel 11 Time Out Error 57100 SCTOERR 13 Channel 13 Time Out Error 57200 SCTOERR 15 Channel 15 Time Out Error Channel Time Out (Group 49) ______________________________________ 61001 SCTOERR 2 Channel 2 Time Out Error 61002 SCTOERR 4 Channel 4 Time Out Error 61004 SCTOERR 6 Channel 6 Time Out Error 61010 SCTOERR 8 Channel 8 Time Out Error 61020 SCTOERR 10 Channel 10 Time Out Error 61040 SCTOERR 12 Channel 12 Time Out Error 61100 SCTOERR 14 Channel 14 Time Out Error Channel Selected (Group 50) ______________________________________ 62001 SCSELCT 1 1 Selected 62003 SCSELCT 3 3 Selected 62004 SCSELCT 5 5 Selected 62010 SCSELCT 7 7 Selected 62020 SCSELCT 9 9 Selected 62040 SCSELCT 11 11 Selected 62100 SCSELCT 13 13 Selected 62200 SCSELCT 15 15 Selected Channel Selected (Group 51) ______________________________________ 63001 SCSELCT 2 2 Selected 63002 SCSELCT 4 4 Selected 63004 SCSELCT 6 6 Selected 63010 SCSELCT 8 8 Selected 63020 SCSELCT 10 10 Selected 63040 SCSELCT 12 12 Selected 63100 SCSELCT 14 14 Selected 63200 SCSELCT 16 16 Selected ______________________________________

3.2 CHANNEL DEVICE BUFFER (CDB)

3.2.1 introduction

Maintenance and Support I/O Equipment is assigned to the CDB(s), and consist of the Teletypewriters, Paper Tape Reader, Paper Tape Punch, Line Printer and Card Reader. This equipment will have a configuration as shown in Intro FIG. 7, in the EAX Engineering Model. As seen in the figure, Controllers 1 & 2 are used as duplicated Channel Device Buffers, that handle the teletypewriters, a single Paper Tape Reader, and a Paper Tape Punch. The Line Printer and Card Reader are assigned to a single controller (6). The Maintenace TTY is equipped with Printing and Keyboard Entry facilities only. Backup for the readers and punch is provided by the Office Administration Teletypewriter which contains a low speed reader and punch.

The primary purpose of the Channel Device Buffers (CDB) is to function as a store and forward center for data and control between the Central Processor and the external devices. The CP communicates with the CDB and it subsequently communicates with the external device through a Peripheral Adapter. A unique Peripheral Adapter is provided for each I/O device. Its function is to provide an interface between the CDB and the device. Each CDB can control a maximum of four Peripheral Adapters.

With the configuration shown in FIG. 35 simultaneous operation of the Channel Buffers can be accomplished. Example, the CP can initiate a typeout on the Maintenance Typewriter and read tape from the High Speed Reader.

3.2.2 Operational Description

3.2.2.1 Channel Device Buffer

The CDB stores and forwards information between the Central Processor and the External devices. Thus all I/O "wait" operations are between the CDB and its associated devices. The Central Processor sends a command word via the Channel Multiplexer which assigns the CDB to the I/O Channel and a device to the CDB. The Channel Device Buffer then proceeds to perform the operation specified by the command word.

3.2.2.2 Input/Output Command Word is the effective address of a SEL instruction and is interpreted as follows: ##SPC47##

I = arm I/O Ready Interrupt (Refer to Section 3.2.2.5)

C = channel Buffer (function is performed by CCX, it defines which Channel Buffer is being selected).

X = x field (defines which Peripheral Adapter has been selected)

Y = y field (directive extension of the Z field)

Z = z field (directive to be performed)

3.2.2.3 Channel Device Buffer Directives

The C Field of the I/O Command Word is 00 when addressing the Maintenance Teletypewriter or High Speed Punch. It is 01 when addressing the Office Administration Teletypewriter or High Speed Reader. The directives are stored and routed to the appropriate Peripheral Adapter.

When the Channel Device Buffer is addressed, X Field -- 0 ₈ , the Y and Z Fields are interpreted by the CDB as follows:

X Y Z DIRECTIVE ______________________________________ 0 0 0 Load CDB Status --Places the CDB Status Lines into the CDB buffer. The CP can now load the status into the CP by executing a STC or CCI instruction. This directive does not destroy the previous status of the X, Y and Z Fields. 0 0 1 Display Buffer -- Places the contents of the CDB buffer register onto the I/O bus. This directive does not destroy the previous selection stored in the X, Y and Z Fields. This directive stays true until it is cleared by a CLEAR directive. 0 0 2 Not Used 0 0 3 Check 1 of 8 Circuits -- (Maintenance Directive) Gates register bits 0-15 into the two 1 out of 8 circuits. During the following data output, a routining field is loaded in the Buffer Register and a 1 out of 8 check is made on the two circuits. If an error is detected the appropriate error flip-flop is set. 0 0 4 Reset Errors -- All errors in the CDB and its associated Peripheral Adapters are reset. 0 0 5 Off Line -- Places the CDB off-line 0 0 6 On Line -- Places the CDB on-line. This is the only directive that will be recognized by the CDB when it is off-line. 0 0 7 Clear and Disconnect -- Clears the CDB and its associated Peripheral Adapters. In addition it disconnects itself from the I/O bus. 0 1 7 Clear -- Clears the CDB and its associated peripheral adapters. 0 2 7 Disconnect -- Disconnects the CDB from the I/O bus. Contents of CDB and PA's are not cleared. ______________________________________

3.2.2.4 Status Lines

When the directive, Load CDB Status (000), is executed the following status lines will be loaded into CDB buffer register. The CP can then load them into the CP by executing a STC or CCI instruction.

______________________________________ Buffer Bit STATUS LINE ______________________________________ 0 Loading Error -- If the CP or the I/O Device attempts to transfer new data to the buffer register before the old data has been removed, this error indicator will be set. The old data in the buffer will not be changed. This results in an Error Interrupt. 2 X Field One out of N Error None or more than one Peripheral Adapter has recognized the last SEL instruction or data transfer. 1 Z Field One out of N Error -- Either no directive or more than one has been decoded during the last SEL instruction. 1 Z Field One out of N Error -- Either no directive or more than one has been decoded during the last SEL instruction. 3 Interrupt Armed -- Channel Device Buffer is armed for Ready Interrupt. 7 Active -- The CDB Active flip-flop is set. 5 Device Error -- One of the 4 Peripheral Adapters has detected an error. The PA Status Lines must be examined to determine what caused the Device Error. This results in an Error Interrupt. 6 Parity Error -- If a parity error (even parity) exists on the data transfer (SEL, LDC, or CCO), the Parity Error is set. If a parity error exists, neither the directive or data will be forwarded to the Peripheral Adapters. This results in a Channel Time Out Error from the Channel Multiplexer. 4 GO Flip-Flop -- Indicates the condition of the GO flip-flop. This indicator determines whether or not directives and data are forwarded to the peripheral adapters. 8 Z Field=0 9 Z Field=1 10 Z Field=2 11 Z Field=3 12 Z Field=4 13 Z Field=5 14 Z Field=6 15 Z Field=7 16 X Field=0 17 Z Field Ackn 1 -- The Acknowledge flip-flop in Peripheral Adapter No. 1. 18 X Field Ackn 2 -- The Acknowledge flip-flop in Peripheral Adapter No. 2. 19 X Field Ackn 3 -- The Acknowledge flip-flop in Peripheral Adapter No. 3. 20 X Field Ackn 4 -- The Acknowledge flip-flop in Peripheral Adapter No. 4. 21 Y Field Bit 0 22 Y Field Bit 1 23 Y Field Bit 2 ______________________________________

3.2.2.5 Channel Ready Signalling

The Channel Device Buffer Ready signal is the means used by the Peripheral Adapters to indicate that they have completed the task assigned to it by the CCP. It is specifically used to indicate that the CDB buffer register is loaded or the peripheral adapter no longer needs the data in the buffer register. This signal is automatically reset during a Store, Load or Select (except CDB 1 out of n check) Channel operations.

The CDB Ready indicator is connected to the CCP via the Sense Line inputs, Group 41 Line 0 for CDB-A and Group 42 Line 0 for CDB-B.

The CDB Ready indicator may be armed for interrupt via bit 14 of the effective operand of the SEL instruction. Once armed, the Ready signals from the CDB's will create an interrupt, Level 7. When armed for interrupt, only the CLEAR directives, 007 or 017, will disarm the Ready interrupt.

3.2.2.6 CDB Error Signalling

The CDB Error indicator can be set by the CDB or by any selected malfunction at any Peripheral Adapters. Errors which cause the indicator are:

Loading Errors

X Field 1 out of N Error

Z Field 1 out of N Error

PA Device Error

Any one of the above errors will result in a Level 6 interrupt. The error can be sensed via Sense Line inputs, Group 43 Line 0 for CDB-A and Group 44 Line 0 for CDB-B.

Errors originating at the peripheral devices, PA Device Error, are combined and transmitted to CDB by the respective Peripheral Adapters. Appropriate status calls are executed to locate the offending device. The offending CDB error; Loading Error, X Field 1 out of N Error or 2 Field 1 out of N Error; is determined by executing the CDB directive, Load CDB Status (0,0,0) and testing the appropriate bits.

If a Parity Error is detected in the CDB on a transmission from the CCP (LDC, CCO or SEL) the Parity Error indicator is set. This does not result in a CDB Error however, it will result in a Channel Time Out Error. The Channel Time Out Error can be sensed via Group 47 Line 0 for CDB-A and Group 48 Line 0 for CDB-B. To determine if the fault was a Parity Error the Status Lines of the CDB (Line 6) must be examined.

All error signals; Loading Error, X Field 1 out of N Error, Z Field 1 out of N Error, PA Device Error and all errors originating at the peripheral devices are reset either by a Reset Error directive (004) or the Clear directive (007 or 017).

3.2.2 Teletypewriter Operation

3.2.3.1 Introduction

The System contains two teletypewriters, Maintenance (LMT) and Office Administration (LOAT). The LMT is a Teletype Model 35 KSR (Keyboard and Printer C Field = 00) while the LOAT is a Teletype Model 35 ASR (Keyboard, Printer, Punch and Reader C Field = 01). These devices operate at a maximum speed of 10 characters per second. They accept and transmit ASCII code with even parity.

To operate the TTY with the CCP, the LINE LOCAL switch must be turned to the ON LINE position. If the switch is in the LOC position, the TTY will neither accept or transmit data to and from the CP.

All data sent to and received from the TTY has the eighth channel as an even parity bit. Only in the case where the mode Switch is in the TTS or TTR positions can binary information be sent or received.

3.2.3.2 Modes of Operation for Model 35 ASR

The Mode of Operation may be set up by operating the rotary mode switch to the left of keyboard. The modes available are:

K Keyboard KT Keyboard Tape T Tape TTS Tape-Tape Send TTR Tape-Tape Receive

3.2.3.2.1 K -- (Keyboard) Operation

The keyboard and typing unit are connected to the computer. Transmission is provided from the keyboard to the CP and is printed. The reader is disabled and the punch is placed in the local circuit.

3.2.3.2.2 KT (Keyboard Tape) Operation

The keyboard, typing unit, reader and punch are connected to the computer. When the reader is transmitting to the computer, the information is copied by the typing unit and a duplicate tape is punched. The keyboard should not be operated when the reader is sending. When the keyboard is sending to the computer, the information is copied by the typing unit and tape is punched. In this case the reader should not be operated. LOC (local) operation is the same except the unit is not connected to the computer.

3.2.3.2.3 T (Tape) Operation

The reader and typing unit are connected to the computer. The typing unit copies what is being transmitted from the reader or from the computer. The keyboard and punch are on the local circuit. Tape can be prepared on the punch from the keyboard without interfering with transmission to the computer. LOC operation will be the same except the reader and typing unit are connected to the local circuit.

3.2.3.2.4 TTS (Tape-Tape Send) Operation

The reader transmits data other than ASCII coded data to the computer. The typing unit is blinded to outgoing and incoming information. The keyboard and punch are connected to the local circuit and can be used to prepare tape. This mode provides no functional use in the LOC operation.

3.2.3.2.5 TTR (Tape-Tape Receive) Operation

The punch is connected to computer and can receive from it data other than ASCII coded. The reader is disabled, the typing unit is blinded and the keyboard is in the local circuit. This mode provides no functional use in the LOC operation.

3.2.3.3 Modes of Operation For Model 35 KSR

The Teletype Model 35 KSR does not have any of the above (3.2.3.2) modes of operation. To operate the KSR with the CP the LINE LOCAL switch must be turned to the ON LINE position. This connects the TTY to the computer. When the switch is in the LOCAL position, the TTY is blinded from the computer however, the keyboard is connected to the typing unit for local use.

3.2.3.4 TTY Interrupt Pushbutton

On each Teletype machine there is a Request for Input pushbutton. This pushbutton is used to notify the computer program that the CP should accept data from the keyboard. This pushbutton should be kept depressed until the Ready to Receive Message lamp is lit. Once the keyboard is enabled, the TTY peripheral adapter will accept all information sent to it via the keyboard.

3.2.3.5 Teletype Directives

The effective address portion of the SEL instruction indicates the Peripheral Adapter, X Field = 1 for both typewriters, and the directive, Z Field.

______________________________________ X Y Z Field TTY Directive ______________________________________ 1 0 0 Present TTY Status -- Places the status lines from TTY Peripheral Adapter into the CDB buffer. The CCP can now load them into the CCP executing a STC or CCI instruction. 1 0 1 TTY Receive -- Alerts the Peripheral Adapter that the next data transmission, LDC or CCO, is to be sent to the Teletypewriter. 1 0 2 TTY Send -- Alerts the Peripheral Adapter to send the next data transmission, LDC or CCO, to the TTY and then monitor the incoming line and receives any characters sent via the TTY keyboard or reader. ______________________________________

3.2.3.6 Status Lines

When the directive, Load TTY Status (100) is executed, the following status lines will be loaded into the CDB buffer register. The CCP can then load them into the CCP by executing a STC or CCI instruction

Buffer Bit Status Line ______________________________________ 0 Shift Register Bit 2 1 do. Bit 3 2 do. Bit 4 3 do. Bit 5 4 do. Bit 6 5 do. Bit 7 6 do. Bit 8 7 do. Bit 9 8 do. Bit 10 9 do. Bit 11 10 do. Bit 0 11 do. Bit 1 12 Counter Decode = 0 13 do. =1 14 do. = 9 15 do. = 10 16 do. = 11 17 Record Start Pulse 18 Clock Enable 19 Counter Bit 3 20 Start Clock 21 Break Key 22 False Start 23 Paper Alarm ______________________________________

Bits 21, 22 and 23 are error indicators; all the other status lines are used for maintenance purposes.

3.2.3.7 Operation

The AC power to the Teletypewriter is turned on by placing the Line/Local switch into the Line position. This switch should be kept in this position as long as the TTY is on-line. The following explanation assumes the Mode Switch is in the K position.

3.2.3.7.1 Print One Character

To print one character on the TTY a SEL instruction (X = 1, Y = 0, Z = 1) must be executed. This directive alerts the TTY Peripheral Adapter that the next computer data transfer to its associated channel buffer (bits 0-7) will be printed on the Teletypewriter. Once the TTY Adapter has been alerted, it need not be reinitialized for each succeeding data transfer. When the character has been printed, the Channel Device Buffer is notified and a Ready signal (section 3.2.2.5) is sent to the computer. In order to keep the TTY operating at its maximum speed of 10 characters per second, the computer program must execute the next data transfer within 9 ms.

3.2.3.7.2 Punch One Character

To punch one character on tape the following sequence must be followed:

Sel -- tty receive (101)

Ldc or CCO-DATA = TAPE ON -- 00000022

Wait for Ready

Ldc or CCO -- DATA = Data to be punched

The remaining characters to be punched can be outputted without reselecting the TTY punch. When punching in the K position, the information will also be printed on the TTY. To punch and not print the mode switch must be in the TTR position. To turn the punch off, the following sequence must be followed: SEL TTY RECEIVE (101)

Ldc or CCO -- DATA = TAPE OFF = 00000024

3.2.3.7.3 keyboard Entry

To enter information into the computer from the TTY keyboard, the following procedure should be followed. The operator should notify the computer program via the Request for Service pushbutton on the TTY panel that he wishes to input from the keyboard. The program will then execute the next sequence of instructions.

Sel tty send (102)

ldc or CCO -- DATA = LAMP ON 0000005

This data transfer lights the Ready to Receive Message lamp thus notifying the operator that the keyboard information will now be forwarded to the computer. This transfer of information is ASCII coded with the 8th channel being the even parity bit. Whenever the keyboard is used, a printed copy of the information is made on the TTY.

When the keyboard operation is complete, the computer program must reset the selection and extinguish the Ready to Receive Message lamp by executing the following sequence of instructions:

Sel tty receive (101)

ldc or CCO -- DATA = LAMP OFF = 0000006

3.2.3.7.4 read Tape

The TTY paper tape reader has only one mode of operation that is read slew. Reading tape in the slew mode allows the tape to run until a stop character is recognized on tape. To initiate the reading of tape, the following programming sequence must be used.

Sel tty send (102)

ldc or CCO -- READER ON -- 00000021

The perper reader on the TTY will then read tape until the stop character on the tape is recognized by TTY. This character is TTY CODE DC1 (00000223). Following the tape off character, the TTY will read a maximum of two additional characters. Thus if successive records are on tape, a minimum of two delete characters should separate them. These delete characters as long as the TTY SEND directives is present.

3.2.3.8 Teletype Error Signalling

The TTY Peripheral Adapater recognizes three types of errors which result in a PA1 Device Error. This device error ultimately results in a CDB Error which notifies the computer of the error (see Section 3.2.2.6).

3.2.3.8.1 Paper Error

When the TTY detects either of the two signals, out of print paper or print paper jammed, the PA Device Error Signal is sent to the CDB. This error does not detect an outage or jamming of the paper tape. This error will stay set until paper error is corrected. Its status can be determined via status line No. 23.

3.2.3.8.2 Break Key

This error is detected whenever the Break Key is depressed or when an open line exists between the adapter and the teletype machine. In the case of the break key, the error can be reset by either the CLEAR or RESET ERROR directives. In the case of an open line, the error will be reset by the above directives but will reappear after a TTY SEND directive sequence is executed. The status of this error can be sampled via status line No. 21.

3.2.3.8.3 False Start

When the adapter receives a short start pulse, this error will be set. This results in a CDB Device Error. This error along with the CDB Device Error will remain set until a CLEAR or RESET ERROR directive is issued. This error can be sampled via status line No. 22.

3.2.4 PAPER TAPE READER

The High Speed Paper Tape Reader used in the EAX System is a photoelectric reader capable of reading at rates up to 400 characters per second. Reading is in the 8 bit binary mode in which all eight channels of the tape enter the computer as data bits. At all times blank tape (leader) and rub outs (deletions) are read into the computer. Prior to reading tape the AC power to the reader must be manually turned on via a switch on the front of the reader panel.

3.2.4.1 High Speed Paper Tape Reader Directives

The Controller Field (C Field) of the I/O Command Word is 01 when addressing the High Speed Reader. The X, Y and Z Fields are stored and decoded by the Channel Device Buffer (CDB) and routed to Paper Tape Adapter number 2 (X field = 2). When Channel Device Buffer 01 is addressed, the X, Y and Z Fields are interpreted by the Paper Tape Adapter for High Speed Reader as follows: X Y Z DIRECTIVE ______________________________________ 2 0 0 Load Paper Tape Adapter Status -- Places the Paper Tape Status Lines into the CDB Buffer. The CCP by executing a STC or CCI instruction. 2 0 4 Read Slew -- Reads Tape continuously at a rate of 400 characters per second. Stops when any other directive is selected on CDB 01 except CDB directives 0 and 1. When stopping, there is a record gap between records. 2 0 5 Read Step -- Reads one character from tape and automatically resets the selection. ______________________________________

3.2.4.2 Status Lines

When the directive, Load Paper Tape Status (200) is executed the following status line is loaded into the CDB buffer register. The CCP can then load it into the CCP by executing a STC or CCI instruction.

______________________________________ BUFFER BIT STATUS LINE 3 Reader On -- Indicates that the manual switch on the reader panel is the LOAD or RUN position. ______________________________________

3.2.4.3 Operation

The Power switch located on the reader panel must be turned on manually. This is a three position switch and its operation is as follows:

Off -- This position indicates that the power is turned off in the unit.

Load -- Indicates that the power is turned on however, the computer cannot access the reader. This position should be used when loading a new tape.

Run -- This position indicates the power is turned on and the unit is capable of reading tape.

3.2.4.3.1 Read Slew

A paper tape read slew operation is initiated by a SEL instruction (X = 2, Y = 0, Z = 4). Execution of this instruction causes the tape to start moving. When the first character is read, it is loaded into the CDB buffer register and the Ready indicator is set. If the Ready Interrupt is armed, an interrupt is sent to the computer. The tape will continue to advance until the directive is removed (either by executing another SEL or by executing the Clear directive).

The computer program has approximately 2 ms to remove the data from the CDB buffer. If it is not removed the next character from tape will be lost and a Loading Error signal will be generated by the CDB.

When the reader is stopped (either by executing a different SEL or by executing the Clear directive), the next character on tape is a record gap. (One character will not be read.)

3.2.4.3.2 Read Step

A paper tape read step operation is initiated by a SEL instruction (X = 2, Y = 0, Z = 5). Execution of this instruction causes the reader to advance one character and stop. The character is loaded into the CDB buffer and the signaling to computer is the same as explained in Section 3.2.4.3.1.

3.2.5 HIGH SPEED PAPER TAPE PUNCH

The paper tape punch is capable of punching at rates up to 120 characters per second in either binary or parity check modes. The C Field of the I/O Command Word is 00 when addressing the high speed punch.

3.2.5.1 High Speed Paper Tape Punch Directives

When the C Field equals 00, the X, Y and Z Fields are stored and decoded by the Channel Device Buffer and routed to Paper Tape Adapter number 2 (X Field = 2). When CDB 00 is addressed, the X, Y and Z fields are interpreted by the Paper Tape Adapter for the High Speed Punch as follows.

______________________________________ X Y Z Directives ______________________________________ 2 0 0 Load Paper Tape Adapter Status -- Places the Paper Tape Status Lines into the CDB Buffer the CCP can now load the status into the CCP by executing a STC or CCI instruction. 2 0 1 Turn Punch On -- this directive applies the AC power to the punch. The Computer program should allow 1 second for the motor to obtain its running speed. 2 0 6 Punch Binary -- Punches eight data bits from the computer into tape. 2 0 7 Punch with Parity Check -- Punches seven data bits and one parity bit from the computer into tape and checks them for even ______________________________________ parity.

3.2.5.2 Punch Status Lines

When the directive, Load Paper Tape Status (200) is executed the following status lines are loaded into the CDB buffer register. The CCP can then load it into the CCP by executing a STC or CCI instruction.

______________________________________ Buffer Bit Status Line ______________________________________ 0 Parity Error -- An odd number of holes was punched into the tape during a Punch with Parity Check operation. 1 Low Tape -- The low tape signal will give an indication when there is 50 feet ±20 feet of tape reamaining on the supply reel. This will result in a PA2 Device Error thus a CDB 00 Error. 2 Punch On -- Indicates that the AC power to the punch has been applied. 4 DTL Stored -- This signal indicates that the Data Transfer Level Stored Flip-Flop is set. (Used for Maintenance). 5 End of Tape -- When there is less than inches of tape remaining ahead of the punch head, this indicator will be ______________________________________ given.

3.2.5.3 Operation

The AC power must be turned on by executing a SEL instruction (X = 2, Y = 0, Z = 1). After waiting approximately 1 second for the motor to obtain its rated speed, a delete character (all holes punched) should be put on tape. Once the punch has been selected, bits 0 through 7 of the I/O bus will be put on tape whenever a LDC or CCO instruction is executed.

The AC power to the punch must be turned off via a Clear directive.

3.2.5.3.1 Punch Binary

A paper tape punch binary operation is initiated by the execution of a SEL instruction (X = 2, Y = 0, Z = 6). This directive alerts the paper tape Peripheral Adapter that the next computer data transfer (bits 0-7) will be punched into tape. Once the Peripheral Adapter has been alerted, it need not be reinitialized for each succeeding data transfer. When the character has been punched, the Channel Device Buffer is notified and a Ready signal (see section 3.2.2.5) is sent to the computer. In order to keep the punch operating at its maximum speed of 120 characters per second, the computer program must execute the next data transfer within approximately 8.33 ms.

3.2.5.3.2 Punch with Parity Check

To punch with a Parity Check a SEL instruction (X = 2, Y = 0, Z = 7) must be executed. The operation of this directive is identical with that of section 3.2.5.3.1 with the following additions.

When punching with parity check, the eights bits transferred from the CCP are checked for even parity after they are punched, an error indicator, Parity Error, will cause a CDB error, Device Error. When this error occurs, the tape is not advanced in the punch. This error can then be rectified by deleting (punch all holes) the character and repunching it. The error can be reset by either the execution of a Clear directive a Reset Error directive.

3.2.5.4 High Speed Punch Error Signalling

The high speed punch has three Device Errors (parity, low tape, end of tape).

3.2.5.4.1 Parity Error

When punching with parity check (X = 2, Y = 0, Z = 7) and an odd number of holes are punched into the tape, the Parity Error will be set. This results in a CDB Device Error. This error will stay set, along with Device Errors in the CDB, until a Clear or Reset Error directive is executed.

3.2.5.4.2 Low Tape

When there is 50 feet ± 20 feet of tape remaining on the supply reel, a low tape error signal will be generated that results in a CDB Device Error. This error signal will only interrupt when the AC power is turned on to the punch. However, it will always be available as a status line (bit 1). It can only be reset by placing a new role of tape on the supply reel.

3.2.5.4.3 End of Tape

An end of tape signal will be given when there is less than 2 inches of tape remaining ahead of the punch head. This error results in a CDB Device Error whenever the AC power is turned on to the punch. It will always be available as a Status line (bit 5). It can only be reset by rethreading the tape through the punch head.

Section 3.3 communication registers

3.3.1 introduction

the Communication Registers provide the media by which the Central Processors can communicate with the Originating and Terminating markers. For normal Call processing, the Originating marker transmits the equipment identity of junctors selected by the OM to the Central Processor. This is one way communication. The communication between the Central Processor and the Terminating Marker is two way in that the CCP sends the routing information to the TM and the TM responds with the results of the termination attempt.

Each originating and Terminating Marker is equipped with a single Communication Register (MCR) for communicating with the Data Processor. The Data Processor is equipped with a pair of CRs operated in an active -- standby configuration. The single CR in each marker and the active CR in the DP will be used to transfer call processing, metering, routining, and maintenance information between these subsystems.

The maximum system configuration, two office sections and a selector section, utilize a maximum of 14 markers. The constraints on the maximum number of Markers in an office section or selector section are as follows:

Each Office Section 2 OM Pairs (2 Sections) 1 TM Pair Selector Section 3 OM Pairs 1 TM Pair

The constraint on the number of TM pairs for a maximum size system is three, one pair for each section. The constraint on the number of OM pairs for a maximum size system is four pairs. This amounts to a maximum of eight individual Originating Markers and 6 individual Terminating Markers. Each Originating Marker and its duplicate can process different calls simultaneously as long as the calls are in different line or trunk register group matrices. The Termination Marker cannot be operated simultaneously because of a common data bus between a pair of TMs and the trunk and junctor they control. Therefore, each TM of a pair will be operating on an alternating basis. Based on the above the maximum number of markers that can be in operation at any one time is 11 (8 OMs and 3 TMs).

The on-line - standby status (configuration) of the two CRs in the Data Processor is under program control. Either CR can be put into either status by means of Select Directives (see section 3.3.2). An on-line CR in the CP scans all the markers in the office for calls for service for transmission to the DP. It is up to the program to determine which DR is on-line when a transmission to one of the markers is required.

3.3.2 COMMUNICATION REGISTER OPERATIONAL/DESCRIPTION

3.3.2.1 description of CR Data Register Formal

The format of each of the four data registers in the CR controller is as follows: ##SPC48##

Data -- This 24 bit field is used to hold the data for a transmission.

P -- parity bit -- This bit contains the parity of the data field and the CB field. The parity for the 26 bit word is odd.

Mp -- memory Protect bit - This bit is used to provide an even number of bits for the register. This bit is set = 0 by the CR controller on sending and set = 0 at the MCR when it is sending.

The order of the registers to provide a 106 bit shift register is as follows: ##SPC49##

3.3.2.2 Communication Register Control Directives

1. Select Command Format --

The DPU will use a Select (SEL) instruction with its associated I/O Command Word (effective address of SEL instruction) for directing the functions of the Communication Register (CR). The CR will use the standard controller I/O Command Word format as described below: ##SPC50##

I -- arm I/O Ready Interrupt

C -- channel Controller Identity -- This field is used to specify one of 16 controllers to be addressed.

Communication Register A = 06, Communication Register = 07

X -- - x field -- This field will not be used for the CR controller and should always be set equal to zero.

Y -- y field -- The Y field is used as a directive modifier to the Z field.

Z -- z field -- The Z field is used as a general directive.

2. Description of Directives

The Y & Z field directive codes for the CR controller are defined below:

Z = 0 display Status - Causes the status group specified by Y to be gated to the I/O bus. If this directive is followed by a STC or CCI instruction, the status word will be stored in memory or the A register.

Y = 0 standard Status Word & Arm Scanner Loading

Y = 1 error Status Word 1

Y = 2 error Status Word 2

Y = 3 - 7 spare

This directive also causes the CR to "lock" in its present status. If sending or receiving it will continue to do so. If scanning, the CR will stop scanning and will not recognize any call for service while the status is selected. The status will be "unlocked" by a Disconnect or Clear Controller directive (Z = 7, Y = 0 or 2) or a Send Directive (Z = 2, Y = 0, 1, 2, or 3).

Z = 1 display Buffer - Causes the buffer specified by the Y field to be gated to the I/O bus. This directive also causes the buffer specified by the Y field to be primed for loading. Therefore if this directive is followed by a STC or CCI instruction, the contents of the specified controller buffer will be stored in memory or the A register. If this directive is followed by a LDC or CCO instruction, the buffer in the controller will be loaded from memory or the A register.

Y = 0 data Register 0

Y = 1 data Register 1

Y = 2 data Register 2

Y = 3 data Register 3

Y = 4 - 7 spare

Z = 2 interrupt Control -- Based on the value of the Y field the CR can be directed to either interrupt or go into the "Idle and Scanning State" after a successful send operation. The CR will always interrupt if the send operation is unsuccessful.

Y = 0 -- interrupt after Sending -- The CR will maintain this state until an Inhibit Interrupt direction (Z = 2, Y = 1) is received.

Y = 1 -- inhibit Interrupts (after sending), -- The CR will maintain this state until an Interrupt after Sending directive (Z = 2, Y = 0) is received.

Z = 3 send Control -- Causes the CR to send the message stored in the shift register over the link whose address is stored in the Address Register in one of four modes, send two or four words normally or send two or four words in a special mode where the message is returned as sent. Each Send directive will reset the CR interrupt if set.

Y = 0 -- send 2 -- causes two words to be sent in the normal mode.

Y = 1 -- send 4 -- causes four words to be sent in the normal mode.

Y = 2 -- send 2 prime -- causes two words to be sent in the special mode that causes the message to be returned as sent.

Y = 3 -- send 4 prime -- causes four words to be sent in the special mode that causes the message to be returned as sent.

Z = 4 reset I/O Errors -- Causes the CR Controller to reset all errors and the controller error interrupt.

Z = 5 take Controller Off-Line or Enable Automatic Reset on Time Out Error on Receiving.

Y = 0 -- take Controller Off-Line -- Causes the Controller to be taken off line and inhibits the controller from any further access of the DP, namely, error and ready interrupts and gating to the I/O bus.

Y = 1 -- enable Automatic Reset on Time Out state where it will automatically reset itself and return to the idle and scanning state without causing an error interrupt if a time out error occurs while receiving. The controller will retain this state until a Z6 - Y3 directive is issued.

Z = 6 -- put Controller On-Line or Inhibit Automatic Reset on Time Out Errors in Receive Mode - Causes the Controller to be put in an on-line (active or standby) condition or in a state where time out errors during receiving will cause an error interrupt. The action to be taken is based on the Y value.

Y = 0 -- operative Active -- Causes the CR to scan all data links for calls for service. The CR will maintain this state until an Operate Standby (Z = 6, Y = 1) or a Take Controller Off-Line directive is received.

Y = 1 -- operate Standby -- Causes the CR to scan only the data link call for service from the other CR. While in this state, the CR can be directed to send a message over any idle data link. The CR will maintain this state until an Operate Active (Z = 6, Y = 0) or Take Controller Off-Line directive is received.

Y = 2 -- inhibit Automatic Reset on Time Out Errors while receiving -- causes CCR to be put in state where it will cause an error interrupt if a time out error occurs while in the receiving mode. In this state the CCR will not reset itself. It will remain in this state until a Z5-Y1 directive is issued.

Z = 7 controller Disconnect and Clear Based on the Y field, this directive either clears or disconnect the controller or does both.

Y = 0 -- disconnect and Clear the Controller - Resets and clears all stored directives, errors, and interrupts at the CR controller. The CR controller is also disconnected from the I/O bus. If the CR controller is in the On-line, Active state, this directive puts the controller in the "Idle and Scanning State".

Y = 1 -- clear Controller - Resets and clears all stored directives, errors, and interrupts at the CR controller. The CR remains in a Selected state.

Y = 2 -- disconnect Controller - Disconnect the CR controller from the I/O bus. Except for resetting the Selected Status State, and disconnection from the I/O bus, this directive has no other affect on the controller.

Y = 3 -- master Reset -- Reset shift register and serial transmission control, initialize scanner, and perform functions associated with "Clear Controller" (Z = 7, Y = 1).

3.3.2.3 status and Address Word Format and Description

The format and definition of each bit or field in the two status words and the address word are given below.

______________________________________ 1) Controller Status Word Bit Position Mnemonic Description ______________________________________ 0-4 ASO Address Scanner output -- indicates data link being scanned, 0 to 31. 5 IAS A 1 indicates that the state of the CR is Idle and Scanning. 6 SEN A 1 indicates that the CR is sending a message. 7 REC A 1 indicates that the CR is receiving a message. 8 SES A 1 indicates that the CR has sent a message successfully. 9 RES A 1 indicates that the CR has received a message successfully. 10 ERS A 1 indicates that the CR has sent a message with an error being detected. 11 ERR A 1 indicates that the CR has received a message with an error being detected. 12 SST A 1 indicates that the CR is in the Operating Full Scan state. A 0 indicates that the CR is in the Operate Standby state. 13 INS A 1 indicates that the CR will interrupt the DP after each message is sent successfully. A 0 indicates that the CR will not interrupt the DP after each message is sent successfully. 14 MGT A 1 indicates that the data link being scanned requires a four word message. A 0 indicates that the data link being scanned requires a two word message. 15 CRI A 1 indicates the CR interrupt flip-flop is set. 16 DB0 A 1 indicates that the 25th data bit of word 0 is a 1. 17 DB1 A 1 indicates that the 25th data bit of word 1 is a 1. 18 DB2 A 1 indicates that the 25th data bit of word 2 is a 1. 19 DB3 A 1 indicates that the 25th data bit of word 3 is a 1. 20-23 Spare = 0 2) Error Status Word 0 RPO A 1 indicates that word 0 was received with bad parity. (By either the CR or the MCR). 1 RP1 A 1 indicates that word 1 was received with bad parity. 2 RP2 A 1 indicates that word 2 was received with bad parity. 3 RP3 A 1 indicates that word 3 was received with bad parity. 4 ES0 A 1 indicates that bad shifting was detected in word 0's shift register. 5 ES1 A 1 indicates that bad shifting was detected in word 1's shift register. 6 ES2 A 1 indicates that bad shifting was detected in word 2's shift register. 7 ES3 A 1 indicates that bad shifting was detected in word 3's shift register. 8 SP0 A 1 indicates that the CR detected bad parity while sending word 0. 9 SP1 A 1 indicates that the CR detected bad parity while sending word 1. 10 SP2 A 1 indicates that the CR detected bad parity while sending word 2. 11 SP3 A 1 indicates that the CR detected bad parity while sending word 3. 12 PER A 1 indicates that a message was received by either the CR or an MCR with bad parity. 13 SER A 1 indicates that a message was received by either the CR or an MCR and bad shifting was detected. 14 PES A 1 indicates that the CR detected bad parity while sending a message. 15 DLE A 1 indicates improper responses over data link. 16 PB1 Indicates the status of the 1st prefix bit register. 17 PE2 Indicates the status of the 2nd prefix bit register. 18 LSC This bit indicates the current status of the "data" lead of the data link. 19 LSC This bit indicates the current status of the "clock" lead of the data link. 20-22 DLS These three coded bits indicate the status of three remaining status leads of the data line. DLS is coded as follows: DLS = 0 Idle 1 Spare 2 Good Message Received 3 Acknowledge 4 Bad Message Received 5 Call for service prime 6 Call for service 7 Spare 23 LOS A 1 indicates the link for the unit whose address is stored in the address register in the lockout condition. 3) The Address Word (from the DP to the CR) 0-4 ASI Input to the Address Scanner -- Indicates data link to be scanned, O-31. 5 PF1 A 0 causes a 1 to be the first bit of the prefix bit. A 1 causes a 0 to be the first of prefix bits. 6 PF2 A 0 causes a 0 to be the second bit of the prefix bits. A 1 causes a 1 to be the second prefix bit. 7-23 Spare = 0 ______________________________________

3.3.2.4 Scanning, DP Selection of the CR, and CR interrupts. The CR can be put in one of three major states listed below by means of the Select instructions described in section 3.3.2.2.

Off-Line -- State in which the CR is not in a condition to be put in service due to a fault or other maintenance reasons.

On-Line, Standby -- State in which the CR is ready to be put into service. In this state, the CR is scanning only the call for service request from the duplicate (active CR).

On-Line, Active -- State in which the CR is scanning the call for service leads from the Markers or is in the process of being used for a transmission (to or from the Marker).

When the CR is in this last state, it can be seized by the Markers for a transmission to the DP. Since the on-line active CR can also be seized by the DP for a transmission to the Markers, a scanning interlock is required. This interlock is achieved by stopping the scanner in the CR and inhibiting all Marker call for service requests from being recognized whenever the CR receives a select (SEL) instruction with a Display Status directive, from the DP. The CR will maintain this state until a Disconnect, Disconnect and Clear, or one of the four Send directives is received. Since the CR can be in the process of causing an interrupt (receive or send complete), the interrupt should be disabled when the CR is selected to determine its idle/busy status. If the CR is found idle, the interrupts can be enabled and the loading process can be initiated. If the CR is found busy the CR should be "unlocked" via a Disconnect directive prior to enabling the interrupts. The use of the above procedure for obtaining an idle CR for sending a frame to an Originating or Terminating Marker is described below.

1. Sending a Frame to the Originating Marker

The communication between the OM and the DP is normally a one way transmission from the OM to the DP. Communication from the DP to the OM is only needed for equipment routining (junctors, lines, etc.), marker routining and diagnostics, and marker directives (on line/off line, etc.). To communicate with a particular OM, the DP must select the CR when the CR is idle and the OM is either idle or in trouble. If the marker is in trouble and the CR is idle when selected, the CR loading process can be started. If the marker is in trouble and the CR is busy when selected, the next CR interrupt (send or receive complete) can be used to initiate the CR loading process for sending. If however, the marker is idle or busy (non trouble condition), the CPD directive STANDBY (Refer to section 8.5-10) can be processed. This directive will place a selected marker in the standby condition when it enters the idle state. In the standby condition the OM will not assign a CFS from a matrix, and will set the standby interrupt/sense line true to alert the Central Processor.

2. Sending a Communication Frame to the Terminating Marker.

The Terminating Marker differs from the Originating Marker in the way it receives a task to perform. The TM only performs tasks conveyed to it by the DP via the CR i.e. it never goes out of idle on its own. Also since the TM returns the results of the termination attempt (just prior to going idle) to the DP via the CR, the DP always has an indication of when the TM goes idle. Therefore the DP can use the interrupt from the CR to service the Terminating Marker queue(s). However if the TM and CR are both idle the frame for the TM can be loaded into the CR without waiting for the CR interrupt.

The above procedure can be used for all types of communication frames i.e. call processing, maintenance, routining, etc.

3.3.2.5 Receiving Sequence

The CR in the DPU is put into the receiving mode whenever the scanner stops on a call for service signal from one of the markers. The steps in the sequence after a request has been observed are as follows:

1. The CR returns an "acknowledge" signal to the marker.

2. When the MCR in the marker observes the "acknowledge" signal, it starts sending the information using serial transmission.

3. As each 26 bit word is shifted out of the MCR, a parity bit is generated and added to the frame of information to make up the 26th bit.

4. As each 26 bit word is shifted into the CR in the DPU, the word is checked for correct parity.

5. After two or four words (frames from OM and TM respectively) are received and the parity is correct for each word, the CR interrupts the DPU for unloading. The CR also returns a "Good Message Received" signal to the MCR.

6. after the DPU acknowledges the interrupt, the call processing status word and two or four data words are stored in core memory via Select and Store Channel Commands.

7. When the data is stored in memory, the DPU can either disconnect the CR and put it into the "idle and scanning" state or reset the CR and go into the loading sequence for sending a frame to one of the markers.

8. If in sequence 6, the call processing status word indicated trouble, the error status word would be retrieved via Select and Store Channel Commands. The CR will automatically return a "bad message receive" signal to the MCR. The MCR upon observing the signal, will make a second "call for service" to the CR.

9. the DPU must put the CR in an idle and scanning state (via Select command) to enable the scanner to observe the second call for service signal from the Marker. By loading the address word with the correct address (Add-1) prior to disconnecting the CR, the DPU can force the CR to observe the second call for service signal from the original marker before scanning any other MCR requests.

10. If the second transmission is error free, the original problem will be considered an error and the operation will proceed to sequence (6).

11. If the second transmission also has error(s), the CR will again send a "bad message received" signal to the MCR. This time, however, the MCR will not make another call for service to the CR.

3.3.2.6 sending Sequence

The sending sequence can be entered from the receive sequence or by selecting the CR and finding it in the idle and scanning state. If the CR is not in the idle and scanning state when selected, the DPU must wait for the next interrupt (receive or send complete) before entering the sending sequence. Once entered, the sending sequence is as follows.

1. The address word and two or four data words (depending on whether the frame is for the OM or TM respectively) are loading into the registers of the CR via Select and Load Channel commands.

2. Following a Select Command (Send), the CR will make a "call for service" to the MCR specified by the address word.

3. The MCR will return an "Acknowledge" signal and the CR will begin the serial transmission. As each 26 bit word, is shifted out of the shift register, the parity for the word is checked against the parity generated by the DPU. Any errors detected during the transmission will be stored and the transmission will be allowed to continue until completion. Following the transmission, the DPU will be interrupt if an error is stored.

4. As the information is received in the MCR, each 26 bit word is checked for correct parity. If parity is correct for all words received, and no other errors have occurred, the MCR will return a "Good Message Received" signal to the CR. If errors are detected in the MCR, it will return a "Bad Message Received" signal to the CR. For the second case see sequence 7.

5. the Following a "Good Message Received" signal from the MCR the CR will either go into the "Idle and Scanning" state or interrupt the DPU. The DPU can control the action taken by the CR with a Select Command (Interrupt After Sending directive).

6. If the CR is set to interrupt after successful sending, the DPU can either disconnect the CR or reenter the sending sequence.

7. If errors are detected in sequence 3 or 4, the DPU can initiate a retrial. This consists of resetting the CR with a Select Command before going to sequence 1.

8. If the retrial is successful, the original problem is considered an error. If the retrial is not successful the Communication Register fault isolation program will be called.

3.3.2.7 Holding Time of the CR

The holding time for the Communication Register includes the loading or unloading time in the DP, the send transmission time, and the overhaul time in the marker. The holding time will differ based on whether the transmission is involved with an Originating or Terminating Marker. Since the communication frame for the OM is one half the size of the frame for the TM, the holding time for the CR involving the OM is one-half that involving the T. The holding time for these cases is given below:

A) Transmission with OM 1) DP load or unload commands 50 μs 2) Transmission Time: 208 μs 52 bits at 250 KC 3) Marker & Signaling 20 μs Overhead B) Transmission with TM 1) DP load or unload 70 μs Commands 2) Transmission Time 416 μs 104 bits at 250 KC 3) Marker & Signaling 20 μs Overhead Total 506 μs

The loading or unloading time stated for the DP assumes no interrupts during the loading or unloading sequence. Also for loading the CR, it is assumed that the three or five words to be loaded into the CR are preformatted and are stored in a three or five word table prior to selecting the CR.

3.3.2.8 communication Register Maintenance

A. cr error Detection -- There are two error interrupts which are directly associated with the CR. The first is the error interrupt from the Channel Multiplex circuit. This interrupt will indicate a parity error on loading the CR or any other failure which would cause the CR not to return an acknowledge to the Channel Multiplex. The second type of error is that received from the CR controller. The different types of errors which are included in CR controller error are listed in section 3.3.2 under Controller and Error Status Words. A summary of these errors is given below:

1. Parity error indication for each word for both sending and receiving.

2. Shifting error indication for each word.

3. Data link-error.

4. Parity Error indication from the source or sink of the transmission.

B. cr routining -- There are two dynamic routines provided for CR fault isolation and localization. The first routine consists of sending a frame to a marker and instructing the MCR in the marker to return the message as received. This can be accomplished in one of two ways.

1. Issue a Send 2 Prime or Send 4 Prime directive rather than the normal Send 2 or Send 4 directive.

2. Set the instruction field (INT or INO) of word 0 of either the terminating or originating frame to zero.

Method 1 involves only the CR in the DP and the MCR in the Marker whereas the second method involves the instruction decoding and sending sequence control of the marker.

The second type of CR routine consists of sending a two or four word frame from the on-line active CR in the DP to the duplicate on-line standby CR. The two CRs in the DP can be put into the above state with Select directives. The routine is set up by loading the address scanner in the on-line CR with the address of the standby CR. Based on whether the routine is for checking a two or four word transmission, one of two procedures will be followed:

1. Two Word Transmission Routine

a. Two Words are loaded into data register 0 & 1.

b. A Send 2 Prime directive is given.

2. Four Word Transmission Routine

a. Four Words are loaded into the 4 data registers.

b. A Send 4 directive is given.

3.3.3 MARKER OPERATION

3.3.3.1 data Interface with Originating Marker

A. description of Originating Marker Communication Frames.

The frame of information which is transmitted via the CR between the Data Processor and the Originating Marker consist of two data words (48 data bits) two parity bits, and two other error detection bits. Included in the two data words are the following groups of data.

Line Group Originations

1. Control Data and Marker Identity

2. Line Number Identity

3. Matrix Identity of Originating Junctor (OJ)

4. matrix Identity of Register Junctor (RJ)

Trunk Group Originating

1. Control Data and Marker Identity

2. Trunk Number Identity

3. Matrix Identity of RJ

As described in section 3.3.2 the interface with the OM for call processing and metering consists of a single two word transmission from the OM to the DP. There is no response to the OM other than the "message received OK" signal returned by the hardware. The only case where the DP transmits a message to the OM (Via the CR) is for maintenance or routining. Given below are the format and description of the Originating Marker Communication Frame.

1. Data Word 0 -- Data word zero is the control and Marker identity word for the total frame of information. The format of this word is similar to the format of data word 0 for the Terminating Marker communication frame. ##SPC51##

Sbs -- subsection

1. Bit Position -- 2-3

2. Valid Range -- 0-3

3. Description -- This field specifies the type of marker and if there is more than one marker in a section, the subsection. This field, along with SEC & MID specifies a unique marker.

4. Value

Sbs = 0 terminating Subsection

Sbs = 1,2,3 originating Subsection 1, 2, 3 respectively

Mid -- marker Identity

1. Bit Position -- 4

2. Valid Range -- 0-1

3. Description -- This bit indicates which marker of a given pair specified by SEC & SBS) is involved in the origination.

4. Value

Mid = 0 marker A

Mid = 1 marker B

Mtn - maintenance Call

1. Bit Position -- 5

2. Valid Range -- 0-1

3. Description -- This bit indicates whether the frame should be interpreted as call processing or maintenance information.

4. Value

Mtn = 0 -- call Processing or test call

Mtn = 1 -- maintenance request or command

Tcl - test Call

1. Bit Position -- 6

2. Valid Range -- 0-1

3. Description -- This bit is used to indicate a test call on the return frame from the OM.

4. value

Tcl = 0 standard Call

Tcl = 1 test Call

Ino - instruction (Originating Marker)

1. Bit Position -- 7-11

2. Valid Range -- 0-31

3. Description -- When MTN = 0, this field is used by the DP to specify the type of action to be taken in the processing of test origination.

4. Value -- When MTN = 1, this field is used for maintenance instruction (See Section VI). The values below one for the normal case with MTN = 0.

Ino = 0 mcr test -- no call processing is performed, but the MCR will immediately return the data frame exactly as received.

Ino = 1 no pull -- this is a special call in which an inlet CFS is simulated and the selected or requested matrix path is not pulled, but a multiple path check is made. The test call is stopped at this point and a special call status is returned indicating the test call was successful. The TCL byte must always be set for this call.

Ino = 2 pull -- this special call simulates an inlet CFS and completes the test call to the selected or requested matrix outlet. On response will be returned at end of call was successfully completed. The TCL byte must always be set for this call.

Ino = 3 wire chief origination -- the path is completed from a specific matrix inlet even if the line is busy.

Ino = 4-31 spare

Bun - b unit

1. Bit Position -- 16-19

2. Valid Range -- 0-10

3. Description -- This field specifies which of 10 matrix B units for a given AB group was involved in the origination.

4. Value -- BUN = 0 Used for test calls only. As blank BUN field indicates that no specific B unit is required for the test call.

BUN - 1 - 10 Regular B units

Cso - call Status (originating)

1. Bit Position -- 20-23

2. Valid Range -- 1-15

3. Description -- This field is used to indicate the outcome of an originating marker attempt to process on origination.

4. Value

Ocs = 1 normal LN1 or TN 1 message

Ocs = 2 all AB Link busy

Ocs = 3 all RJ's busy

Ocs = 4 path busy

Sec - office Section

1. Bit Position -- 0-1

2. Valid Range -- 1-3

3. Description -- This field of the LNI or TNI specifies which office section was involved in the origination. LNIs can only be associated with office sections 1 and 2 while TNIs can be associated with all three sections.

4. Value

Sec = 1 office Section No. 1

Sec = 2 office Section No. 2

2. Data Word 1 - Data Word 1 contains the line or trunk number identification (LNI or TNI) and matrix information for identifying the selected Originating Junctor (Line originations only) and Register Junctor. The LNI or TNI includes all the fields from bit position 6 to 23 of Data Word 1.

MTX ABG AUN AUI RUO BUO 23 22 21 18 17 15 14 11 10 6 5 3 2 0

Buo -- b unit Outlet

1. Bit Position -- 0-2

2. Valid Range -- 0-4

3. Description -- This field specifies the outlet at the B unit that was selected for the origination.

4. Value -- BUO = 0 Used only for test calls. BUO = 0 indicates that no B unit outlet is being specified.

BUO = 1 - 4 Regular B Unit outlets

Ruo - line Matrix R Unit Outlet

1. Bit Position -- 3-5

2. Valid Range -- 0-6

3. Description -- For line originations, this field specifies which outlet on the Line Matrix R unit was selected. The R unit is not specified in the frame directly because it is identical to the B Unit Outlet (BUO). For trunk originations this field is blank.

4. Value -- RUO = 0 For test calls, it indicates that no R unit outlet is specified. For a RUO = 1-5 Regular Line Matrix R unit Outlets

Aui - a unit Inlet

1. Bit Position -- 6-10

2. Valid Range -- 1-20

3. Description -- The AUI field of the LNI or TNI specifies which of the 20 inlets of the A unit was identified in the origination.

4. Value

Aui = 0 invalid AUI = 1-20 Regular A Unit inlet

Aun - a unit

2. Bit Position -- 11-14

2. Valid Range -- 1-10

3. Description -- This field of the LNI or TNI specifies which of the 10 A Units of the Line Matrix was identified during the origination.

4. Value -- AUN = 1-10 Regular A Units

Abg - ab group

1. Bit Bosition -- 15-17

2. Valid Range -- 1-6

3. Description -- This field of the LNI or TNI specifies which of the 200 line AB group was identified during the origination. This field also indicates if the origination is associated with a line or trunk B register matrix.

4. Value -- ABG -- 1-5 Regular Line AB groups (LNI)

6 indicates a Trunk Register Matrix Identity (TNI)

7 invalid

Mtx - matrix (Line Group or Trunk Register)

1. Bit Position -- 18-21

2. Valid Range -- 1-11

3. Description -- This field of the LNI or TNI specifies which of the 10 Line Group Matrices or 5 Trunk Register Matrices was identified in the origination.

4. Value MTX = 1-10 Regular Line Group Matrices For Trunk Register Matrices the range is 1-5. MTX = 6 is the trunk test matrix.

B) Description of the Control for Setting the Fields of the Originating Marker Communication Frame

The control for setting the fields described above will vary based on whether the frame corresponds to a normal call or a test call. Table IV-A illustrates the 12 possible call processing and test call frames and indicates the control for each field. (Table IV-A).

The entry in the table have the following meaning:

M -- indicates the field is set by the OM.

D -- indicates the field is set by the DP.

M' -- indicates the field is set by the OM based on what was sent by the DP. The OM resets these fields and loads them from the internal hardware (scanners). Comparison of what was sent to the OM against what was received is one of the fault detection methods for the interface.

U -- indicates the field is returned to the DP unaltered.

Dc -- indicates the value of the field is a don't care because it will be overwritten by the OM. However for consistency, this field should either be set to zero or to the value that the OM will set it to.

Specific Values -- Some of the entries in the table have specific values. This is to indicate the required value of the field for the particular frame. Those entries where the value is not specified can take on any reasonable value.

1. Call Processing Frames. The first two frames No. 1 and No. 2 are the normal call processing frame received from an OM for a line and trunk origination respectively. Since the OM sets all fields on these two frames, these two frames are quite simple.

2. Test Call Frames. Frames 3 to 12 illustrate the setting control (Data Processor Originating Marker) for selecting certain lines and junctors during a test call. These frames are as follows:

Frame No.

3 -- Frame sent to OM to request the OM to cause an origination from the line specified (LNI) using any OJ or RJ.

4 -- frame returned from OM (to DP) as a result of frame No. 3.

5 -- Frame sent to OM to request the OM to cause an origination from an inlet on the Trunk Register Matrix as specified by the TN1 using any RJ.

6 -- frame returned from OM as a result of frame No. 5.

7 -- Frame sent to OM to cause an origination from the line specified (LN1) using the OJ specified and any RJ in specified R unit.

8 -- Frame returned from OM as a result of frame No. 7.

9 -- Frame sent to OM to cause an origination from the line specified (LN1) using the specified OJ and RJ.

10 -- frame returned from OM as a result of frame No. 9.

11 -- Frame sent to the OM to cause an origination from the inlet of the Trunk Register Matrix specified by TNI using the RJ specified.

12 -- Frame returned from OM as a result of frame No. 11.

3. Metering Frames. When blockage occurs in the Originating Marker, it will transmit a frame with the same information content and format as frames No. 1 or 2 based on whether the blockage occurred during a line or trunk origination respectively. The frame will always contain the correct LNI or TNI however if blockage occurs the matrix identities for the junctors will be whatever the marker scanner indicates when the blockage was detected.

4. Maintenance Frames. These frames are described in section 3.3.3.3.

TABLE IV A ____________________________________________________________ ______________ ORIGINATING MARKER COMMUNICATION FRAMES FRAME* CSO BUN INO TCL MTN MIO SBS SEC MTX ABG AUN AUI RUD BUO ____________________________________________________________ ______________ 1 M M M=0 M=0 M=0 M M M M 1-11 M 1-5 M M M M 2 M M M=0 M=0 M=0 M M M M 1-5 M 6 M M M M 3 D=0 D=0 D D=1 D=0 DC DC DC D D 1-5 D D D=0 D=0 4 M M U U U M M M M' M' M' M' M M 5 D=0 D=0 D D=1 D=0 DC DC DC D D=6 D D D=0 D=0 6 M M U U U M M M M' M'=6 M' M' M M 7 D=0 D D D=1 D=0 DC DC DC D D 1-5 D D D=0 D 8 M M' U U U M M M M M' 1-5 M' M' M M' 9 D=0 D D D=1 D=0 DC DC DC D D 1-5 D D D D 10 M M' U U U M M M M' M' 1-5 M M' M' M' 11 D=0 D D D=1 D=0 DC DC DC D 1-5 D=6 D D D=0 D 12 M M' U U U M M M M' 1-5 M'=6 M' M' M' M' ____________________________________________________________ ______________

3.3.3.2 data interface with terminating marker

a. description of Terminating Marker Communication Frames

The frame of information which is transmitted via the CR between the data Processor and the Terminating Marker consists of 4 data words (96 bit), 4 parity bits, and 4 error detection bits. The four data words contain the following groups of data

Word 0 -- Control data and Marker identity

Word 1 -- Selector Group Inlet Identity and Trunk control.

Word 2 -- Selector Group Outlet information.

Word 3 -- Terminating line identity.

The normal call processing interface with the TM consist of a 4 word (104 bit) transmission followed by a 4 word response from the TM indicating the result of the termination attempt. The format of the four data words is given below:

1. Data Word 0 -- Data word zero is the control and marker identity word for the total frame of information. The format of this word is similar to the format of data word 0 for the Originating Marker. ##SPC52##

Sbs - subsection

1. Bit Position -- 2-3

2. Valid Range -- 0-3

3. Description -- This field specifies the type of marker and if there is more than one marker in a section, the subsection. This field, along with SEC & MID specifies a unique marker.

4) Value

Sbs = 0 terminating Subsection

Sbs = 1, 2, 3 originating Subsection 1, 2, 3 respectively

Mid - marker Identity

1. Bit Position -- 4

2. Valid Range -- 0-1

3. Description -- This bit indicates which marker of a given pair (specified by SEC & SBS) is involved in the origination.

4. Value

Mid = 0 marker A

Mid = 1 marker B

Mtn - maintenance Call

1. Bit Position -- 5

2. Valid Range -- 0-1

3. Description -- This bit indicates whether the frame should be interpreted as call processing or maintenance information.

4. Value

Mtn = 0 -- call Processing or test call

Mtn = 1 -- maintenance request or command

Tcl - test Call

1. Bit Position -- 6

2. Valid Range -- 0-1

3. Description -- This bit is used to indicate a test call on the return frame from the OM.

4. value

Tcl = 0 standard Call

Tcl = 1 test Call

Int - instruction Terminating

1. Bit Position -- 7-11

2. Valid Range -- 0-31

3. Description -- When MTN = 0 this field is used to specify the type of termination required. This mode is used for normal call processing, routining, and test calls. When MTN - 1 the INT field will be used for maintenance instructions (see Section 3.3.3.3.)

4. Value -- When MTN = 0, the INT field will have the following interpretation.

Int = 0 -- mcr test -- no call processing is performed, but the MCR will immediately return the data frame exactly as received.

1. Normal Call, No Test -- Normal call process with no continuity test to the RJ.

2. normal Call with Test -- Normal call processing with a continuity test to the RJ. This test is specified by the DPU when the call is being processed through the final selector matrix and the call is not terminating to a local line matrix.

3. No Pull -- This is a special call in which the inlet potential is not checked and the path is not pulled, but a multiple path check is made. This call is used only as a test call and the TCL bit must always be set.

4. Busy Override -- The path is completed even if the line is busy. The BO instruction is only used to complete to lines and always uses an X-TJ. The BO instruction should never be used in conjunction with a specified matrix path. A continuity test to the RJ is made.

5. Wire Chief -- The path is completed even if the line tests busy and a line circuit test is performed. In addition the call is completed even with the detection of either foreign potential or power cross. If either of these conditions is detected, the TCS byte will indicate one of the line circuit fault codes.

6. Line Routine - This special call performs a line circuit test but does not override line busy or override any other check or test. ITN = 7 - 31 Spare

Cst - call Status Terminating

1. Bit Position -- 20-23

2. Valid Range -- 0-15

3. Description -- This field is used by the TM to inform the DP on the outcome of the Termination attempt. Table V-A illustrates the possible CST replies for each Terminating instruction (INT).

4. value -- CST = 0 Marker malfunction -- call not complete

1. Completed call -- line or outlet idle -- no line circuit fault.

2. Call not completed -- line busy.

3. All LX AB links busy

4. All TJ-LX paths busy or all outlets busy.

5. Special feature busy.

6. Path Busy

7. Call completed -- line or outlet busy - no line circuit fault.

8. Call completed -- line idle, -- line circuit fault.

9. Call completed -- line busy -- line circuit fault.

10. Marker Trouble -- call completed -- line idle -- no line circuit fault

11. Marker trouble -- call completed -- line busy -- no line circuit fault

12. Marker Trouble -- call completed -- line idle -- line circuit fault

13. Marker Trouble -- call completed -- line busy -- line circuit fault

14-15. Spare

In some codes where "no line circuit fault" is indicated, a line circuit test was not made. A line circuit test is only made when a Wire Chief or Line Routine instruction is received.

Sec - section

1. Bit Position -- 0-1

2. Valid Range -- 1-3

3. Description -- This field is used in the return frame from the TM to indicate the section in which the transmission was sent.

4. Value

Sec = 1 office Section No. 1 SEC = 2 Office Section No. 2 SEC = 3 Selector section

B. Data Word 1 - Data word 1 contains the 16 bit Selector Group inlet identity and the Trunk and junctor control field. ##SPC53##

Tkc - trunk control

1. bit Position -- 0-5

2. Valid Range -- 2 ⁶

3. Description -- The bit TKC field is a control field for controlling the Terminating Junctor or Trunk. The 6 bit field is transferred to the trunk or junctor via a 6 bit bus.

4. Value -- The value of the TKC field for specifying ringing frequency for TJs is as follows:

Tck = 16 frequency 1 to the R lead

Tck = 17 frequency 1 to the T lead

Tck = 18 frequency 2 to the R lead

Tck = 19 frequency 2 to the T lead

Tck = 20-25 spare ringing codes

Sau - selector Matrix A Unit

4. Value

Sau = 1 selector A Unit No. 1

Sau = 5 selector A Unit No. 10

Sab - selector Matrix AB Group

1. Bit Position -- 15-17

2. Valid Range -- 1-6

3. Description -- The SAB field defines one of the 6 AB group of the Selector Matrix in the total Selector Group inlet identity.

4. Value

Sab = 1 selector AB Group No. 1

Sab = 6 selector Ab Group No. 6

Smx - selector Matrix

1. Bit Position -- 18-21

2. Valid Range -- 1-11

3. Description -- The SMX field defines one of the 10 Selector Matrices in a Selector Group in the total Selector Group inlet identity.

4. Value

Smx = 1 selector Matrix No. 1

Smx = 10 selector Matrix No. 10

Smx = 11 selector Test Matrix

C. Data Word 2 -- Data Word 2 contains the fields for specifying a group of outlets of the Selector Group Matrices. It also contains the fields for retrieving the identity of the trunk or junctor selected by the Terminating Marker. ##SPC54##

Sut -- selector Units

1. Bit Position -- 0-3

2. Valid Range -- 0-10

3. Description -- On communication frames from the TM to the DP, this field and the STN field specified which outlet in the group was selected. On frames to the TM this field, in conjunction with the STN field, can instruct the TM to select any idle unit (SUT = 0) of a particular outlet specified by SUT & STN (both not equal to zero)

4. Value -- SUT = 0 In the transmission to the TM, this indicates that a scan is to be made.

1 In the transmission to the TM, this indicates that the path is specified and that Units No. 1 is to be used.

10 This indicates that the path is specified and that Units No. 10 is to be used.

In the return transmission to the DPU, the Units No. used in the call (1-10) is sent.

Stn -- selector Tens

1. Bit Position -- 4-7

2. Valid Range -- 0-8

3. Description -- See SUT

4. value -- STN = 0 In the transmission to the TM, this indicates that a scan is to be made.

1 In the transmission to the TM, this indicates that the path is specified and that Tens No. 1 is to be used.

8 In the transmission to the TM, this indicates that the path is specified and that Tens No. 8 is to be used.

In the return transmission to the DPU, the Tens No. used in the call (1-8) is sent.

Sqs - sequential Scan

1. Bit Position -- 8

2. Valid Range -- 0, 1

3. Description -- This field specifies the type of scan the TM should use in selecting in idle unit.

4. Value

-- SQS - 0 Random Scan

Sws = 1 sequential Scan

Pls -- plus

1. Bit Position -- 9-11

2. Valid Range -- 0-7

3. Description -- The PLS field is used to specify the size of the outlet group to be scanned. The PLS field specific how many arrays (10 outlets) should be scanned in addition to the array specified by the ARR field.

4. Value -- PLS = 0 Only the array indicated by ARR is to be scanned.

1 One Array (array ARR + 1) is addition to that specified by ARR is to be scanned.

6 Six Arrays in addition to that specified by ARR are to be scanned.

6 Six Arrays in addition to that specified by ARR are to be scanned.

7 Scan all Arrays on Horizontal specified.

Arr - array

1. Bit Position -- 12-15

2. Valid Range -- 1-8

3. Description -- The ARR Field is used to specify one of 8 outlet groups. An array consists of 10 outlets on the same horizontal. ##SPC55##

Ccg -- c card Group

1. Bit Position -- 16

2. Valid Range -- 0,1

3. Description -- The CCG field is used to indicate which group of C cards should be involved in the scan. Each C card group consists of 800 outlets maximum.

4. Value

Ccg - 0 c card Group A

(hor = 1, 10)

ccg - 1 c card group B

(hor = 1, 10 is interpreted as horizontal 11 to 20).

Hor -- horizontal

1. Bit Position -- 17-20

2. Valid Range -- 1-10

3. Description -- In conjunction with the CCG field, the HOR field specifies one of the 20 horizontal upon which the scan or selector should take place.

4. Value -- For CCG = 0, HOR has the following interpretation:

Hor = 1 horizontal No. 1

Hor = 10 horizontal No. 10

For CCG = 1, HOR has the following interpretation:

Hor = 1 horizontal No. 11

Hor = 10 horizontal No. 20

D. Data Word 3 -- Data word 3 contains the information required to specify a line equipment for a local termination. This word also contains information for termination to PBXs on the line matrix. For trunk terminations, data word 3 is blank.

______________________________________ L LMX LAB LAU LAI P X 23 22 21 18 17 15 14 11 10 6 5 4 0 ______________________________________

Lpx -- line Matrix PBX

1. bit Position -- 5

2. Valid Range -- 0-1

3. Description -- The LPX field is used to indicate a PBX line matrix termination. When LPX is a one, the interpretation of the remaining fields will differ from that of a normal line Termination (LPX = 0).

4. value

Lpx = 0 normal Line Termination (not PBX)

Lpx = 1 line Matrix PBX termination

Lai - line A Inlet

1. Bit Position -- 6-10

2. Valid Range -- 1-20

3. Description -- The LAI field, which is analogous to the AUI on originating, is used to specify the particular inlet in the A unit for terminating a local call.

4. Value -- The interpretation of LAI for LPX = 0 is as follows:

Lai = 1 line inlet No. 1

Lai = 20 line Inlet No. 20

When LPX = 1, the LAI field should be set = 0 by the DP. For this case, the TM will insert the particular inlet selected into the LAI field for the terminating response.

Lau - line Matrix A Unit

1. Bit Position -- 11-14

2. Valid Range -- 0-10

3. Description -- This field, which is analogous to SUN an originations, is used to specify one of 10 A units for terminating a local call. For a PBX call (LPX = 1), the LAU field is used to specify the scan group and the particular set of PBX inlets. For LPX = 0, LAU has the following interpretation

LAU - 0 Indicates that no Line A Unit is being used. ##SPC56##

4. Value -- For LPX = 1, LAU has the following interpretation:

Lau = 0xxx indicates inlets 1 and 6 of every A unit.

Lau = 1xxx indicates inlets 11 and 16 of every A unit ##SPC57##

If the LPX bit is a 1, the LAU field is broken into two pieces of data.

The most significant bit indicates whether inlets 1 and 6 or inlets 11 and 16 are to be used. The 3 least significant bits indicate the scan group.

Lab -- line AB Group

1. Bit Positions -- 15-17

2. Valid Range -- 0-6

3. Description -- This field, which is analogous to the ABG on originating, specifies which of five AB groups are involved in the local termination.

4. Value -- The interpretation of the LAB group is independent of the LPX field.

Lab = 0 indicates that no line matrix is being used. ##SPC58##

Lmx -- line Matrix

1. Bit Position -- 18-21

2. Valid Range -- 0-11

3. Description -- This field, which is analogous to MTX on originating, is used to specify 1 of 10 line matrices for a local termination.

4. Value -- The interpretation of LMX is independent of the LPX field.

Lmx - 0 indicates that no line matrix is being used ##SPC59##

B. Description of the Control for Setting the Fields of the Terminating Marker Communication Frame

The control for setting the fields described in section 3.3.2.8 will vary based on whether the frame correspond to a line, trunk, or PBX termination and whether the termination is a normal call or a test call. Table V-A illustrates the 10 call processing and test call frames and indicates the setting control for each field. The entries in the table have the same meaning as for Table IV A (Section 3.3.3.1). The 10 frames are as follows:

Frame No.

1 -- Frame sent to TM for a line termination.

2 -- Frame returned from TM as a result of frame No. 1.

3 -- Frame to TM for a line termination specifying a particular Terminating Junctor.

4 -- Frame returned from TM as a result of frame No. 3.

5 -- Frame sent to TM for a trunk termination on the Selector Group Matrix.

6 -- Frame returned from TM as a result of frame No. 5.

7 -- Frame sent to TM for a trunk termination specifying a particular trunk (particular Selector Group outlet).

8 -- Frame returned from TM as a result of frame No. 7.

9 -- Frame sent to TM for a PBX line termination.

10 -- Frame returned from TM as a result of frame No. 9.

When blockage or trouble occurs on a termination attempt the TM will convey this condition via the status field (CST) on the return frame.

The maintenance frames (MTN = 1) are described in section 3.3.3.3.

TABLE V-A ____________________________________________________________ ______________ TERMINATING MARKER COMMUNICATION FRAMES CST INT TCL MTN MID SBS SEC SGI* TKC SGO* STN SUT TLN* LPX ____________________________________________________________ ______________ 1 DC D D=0 D=0 DC DC DC D D D D=0 D=0 D D=0 2 M U U U M M M U U U M M U U 3 DC D D=1 D=0 DC DC DC D D D D D D D=0 4 M U U U M M M U U U M' M' U U 5 DC D D=0 D=0 DC DC DC D D D D=0 D=0 D=0 D=0 6 M U U U M M M U U U M M U U 7 DC D D=1 D=0 DC DC DC D D D D D D=0 D=0 8 M U U U M M M U U U M' M' U U 9 DC D D=0 D=0 DC DC DC D D D D=0 D=0 D ^t D=1 10 M U U U M M M U U U M M U ^t U M ____________________________________________________________ ______________ *SGI -- Selector Group Inlet Includes SMX, SAB, SAU, +SAI *SGO -- Selector Group Outlet Includes HOR, CCG, ARR, PLS, +SQS *TLN -- Terminating LNI includes LMX, LAB, LAU, LAI t -- The LAI Field Should be Set = 0 by DP + -- The Marker will Write LAI but return the Remainder of TLN unaltered

3.3.3.3 Marker Maintenance Frames

A. Retrieval of Marker Diagnostic Data

The transfer of all diagnostic information including error indication, Marker sequence state in which the error occurred, and marker status data (states of logic elements) to the DP will be via the Communication Register. The CR is presently planned to be used also for all maintenance directives such as on line/off line control, resetting error interrupts, etc. Word of either the Originating or Terminating frame will be used for both requesting the marker to return diagnostic data and for maintenance commands. Word one of either the Originating or Terminating frame will be used to transfer 24 bits of diagnostic information. The format of these two words are as follows: ##SPC60##

Tcl, & sec -- these fields have the same meaning as described in section 3.3.2 and 3.3.3.1. TCL should be set = 0 for the maintenance retrieval.

Mtn -- this field indicates the frame should be interpreted as a maintenance retrieval or command. It should be set = 1 for the maintenance mode.

In(x) -- the Instruction field, INO and INT for originating and terminating respectively, is used to specify which group of 24 status or indication points are to be returned to the DP.

Dg(x) -- the Data Group field, DGO and DGT for originating and terminating respectively, is used to specify which group of 24 status or indication points are to be returned to the DP.

Md(x) -- the Maintenance Data, MDO and MDT field for originating and terminating respectively, contains the 24 bits of status or indication points in the Marker. MD(X) should be set = 0 by the DP on the transmission to the Marker.

The additional two words of the frame on terminating communication frames will not be used for the maintenance transmissions and should be set = 0 by the DP.

The Marker (originating or terminating) will always attempt to return a communication frame to either a maintenance data retrieval command or a maintenance command. The only time this would not be possible would be the occurrence of trouble in the MCR sending operation.

3.3.3.4 CPD DIRECTIVES:

Both Originating and Terminating Markers can be controlled via CPD directives (refer to section 8.5-10) in the following manner.

Cpd n*, 001: RESET ENABLE:

This directive resets all error indicators in the markers and sets it to an idle state.

Cpd n*, 002: RESET INTERRUPTS

This directive resets only the malfunction alarm interrupts. It does not change the state or condition of the marker.

Cpd n*, 004: SEND SR DATA

This directive is used to unload the shift register in the MCR and transmit its contents to the CCP via the CR for analysis.

Cpd n*, 010: STANDBY

This directive will place the associated Originating Marker in a standby condition when that marker enters the idle state. The standby condition will inhibit the OM from assigning a CFS from a matrix and will set the standby interrupt/sense line true in order to alert the CCP of its condition.

Cpd z*, 020: report blockage:

after receiving this directive the OM will report (via the CR) to the CCP, the conditions of, all AB lines busy, All RJ(s) busy and path busy, whenever they are encountered. (With this directive true the initial (or same) CFS could cause redundant reports to be transmitted.)

Cpd z*, 040: do not report blockage

this directive cancels the preceding directive.

Cpd n*, 100: DO NOT PERFORM LINE TEST

This directive resets a latch in the markers that would test the conditions of the marker line.

Cpd n*, 200: PERFORM LINE TEST:

This directive sets the latch as described in CPD n, 100.

Cpd n*, 400: RESET SEND SR DATA

This directive cancels the directive CPD n, 004.

Section 4.0 register sender

4.1 introduction

a brief description is given here of the major hardware elements of the Register-Sender and their relationship to the Data Processing Unit (DPU.) A fully-equipped Control Section has one DPU and two Register-Senders.

Each Register-Sender (RS) has two identical Common Logic Units (CLU-A and CLU-B) and each CLU has an associated RS Core Memory (abbreviated as RCM-A or RCM-B). Each Register-Sender also has its own multiplex equipment and space-divided hardware.

Space-divided hardware is electromechanical in nature and provides interfaces with the system's network equipment. The multiplex equipment provides the interface between the space-divided electro-mechanical hardware and the time-shared electronic hardware of the CLU's.

A minimally-equipped EAX Control Section includes at least one RS (in addition to the Always-required DPU). Within the RS, both CLU's must be equipped but space-divided hardware and its associated multiplex equipment will be equipped to the extent called for by individual office requirements. The two CLU's within an RS normally operate in synchronism, simultaneously servicing each call. They are provided as a pair for reliability so that a single fault in the hardware will not put an RS out of service. The two Register-Senders in a fully-equipped EAX control Section operate independent of each other, never servicing the same call.

4.2 Interface

FIG. 36 shows the major elements involved in the interface between the RS and the DPU. The groupings involve signals from RS Core Memory (RCM) to the DPU, from the DPU to RCM (including parity signals not associated with RCM), RS/DPU configuration sense lines, RS multiplex configuration sense lines, and RS interrupt-associated Sense lines.

4.2.1 Signals from RCM to DPU

A group of 24 data bits, (Data Bits 0-23) and a parity bit (Data Bit 24) are sent to the DPU from the RCM. The DPU detects parity over all 25 leads as a check on the transmissions. This 25 lead grouping is used for the PRA instruction execution by the CCP.

4.2.2 signals from the DPU to RCM

A group of 24 data bits, is sent to the RS from the DPU. The RS generates parity on Data Bits 0-23 and stores this parity bit in the RCM. The 24 lead grouping is controlled by execution of the PAR instruction.

A group of 13 address bits is sent from the DPU to the RS. This 13 lead grouping is used for both the PAR and PRA instruction executions.

4.2.3 RS/DPU Configuration Sense Lines

Three sense lines from the RS give a partial status indication to the DPU of the configuration between the RS and DPU. The three lines are: (a) CCP-A Selected: indicates that this Register-Sender Common Logic Unit (CLU) is accepting read/write commands and data from CCP-A. (b) CCP-B Selected: indicates that this CLU is accepting read/write commands and data from CCP-B. (c) Run Simplex: indicates that this CLU will not attempt to sync read/write commands with its CLU mate before execution of such commands. This operation feature will typically be used when the other CLU has been configured off line with respect to its space-divided equipment.

These sense lines are assigned to groups 20-23 as shown in section 8.3 of this document.

4.2.4 RS Multiplex Configuration Sense Lines

Four sense lines from the RS indicate to the DPU the status of the configuration between the CLU's and their associated multiplex equipment. The multiplex circuits and CLU's have two sets of signals between them. One set, the scan leads, carry signals from the multiplex to the CLU's. The other set, the distribution set, carries signals from the CLU's to the multiplex.

Normally both CLU's scan multiplexed signals from all space-divided equipment but each CLU distributes signals (via the multiplex) only to the half of the space-divided equipment to which it is configured for distribution. CLU-A normally distributes signals to RJM Groups 0, 2, 4 and 6, and RSM Files 1, 3, 5, and 7. CLU-B normally distributes signals to RJM Groups 1, 3, 5, and 7 and RSM Files 2, 4, 6, and 8. The CLU-Multiplex configuration is controlled by means of Direct Control Pulses; see section 8.5. In the case of a Register Timing Generator (RTG) "Y" or "Z." Generator failure, the CLU-Multiplex scan configuration is automatically changed, via hardware, to a simplex mode in which the CLU's scan configuration is the same as the normal distribution configuration.

The four sense lines are:

a. Normal RJM Scan (RJM being the multiplex circuitry dealing with Register Junctors).

b. Normal RSM Scan (RSM being multiplex circuitry dealing with senders and receivers).

c. Normal RJM Distribution

d. Normal RSM Distribution

All four of these sense line types are assigned to each of groups 25, and 26 as shown in section 8.3 of this document.

4.2.5 RS Interrupt Associated Sense Lines

Three sense lines from the RS cause the DPU to be interrupted. The three are associated with maintenance; the RS Fault Interrupt Sense Line, the RS Error Count Interrupt, and the RS System Trouble Interrupt Sense Line. They are associated with interrupt levels 2 and 8.

These sense lines are assigned to groups 18 and 19 as shown in section 8.3.

The interrupt level assignments are given in section 8.4. 4.3 General RS Core Memory Accessing & Layout

FIG. 37 shows a sketch of the layout of the RCM. It is conceptually divided into five sections: normal call processing Register Junctor Memory slots which are associated with Register Junctor units, maintenance Register Junctor memory slots which are not associated with any physical Register Junctor units, miscellaneous RCM data words, the fault snapshot area, and a section of unassigned words.

4.3.1 Normal & Maintenance RJ Memory Slots

The first two sections of the RCM lie within the 10 millisecond operating scan of the RS. These areas are divided into 202 sixteen-word blocks. The layout of the first 201 blocks are defined in the REGISTER-SENDER patent application to which the reader is referred for full definition of the 16-word call processing blocks. The 202 word block controls the RS Direct Control Pulse and Latch hardware of the RS Maintenance Control Unit (RMU) which is described in section 4.4.5.

The first 192 blocks have a one-for-one fixed assignment to 192 space-divided Register Junctor circuits which may be equipped in a Register-Sender. Even though only part of the 192 Register Junctors may be equipped in a Register-Sender, all 202 RJ memory blocks are always dedicated and are scanned during each 10-millisecond scan cycle. Normally the Register-Sender executes the RJ memory block scan in one of two modes described below, starting with the memory block dedicated to the first Register Junctor circuit.

The RJ time slot is known as a Z time. There are 202 Z times, all of them occurring sequentially during the 10-msec cycle. Each Z time is normally divided into 9 intervals to allow successive appearances of 9 of 11 possible Y times, which are numbered Y1 to Y11. Each Y time represents operation by the Register-Sender on a pair of memory words within an R memory block.

A Y time is divided into five X times numbered X1 to X5. During X1 and X2 the RS successively reads two 26-bit words from the RCM into a 52-bit buffer. The combined contents of this buffer are referred to as a row. During X3 the call processing circuitry of the RS common logic acts on the contents of this buffer and on information from space-divided equipment associated with the call being serviced by the common logic during this Z time.

During X3 the RCM itself can be used for three purposes depending on the Y time. During Y1-X3 the RS always writes the RJ Scan Position Word (see section 4.3.2). During Y2-X3, if the associated RJ requires DPU data, the RS writes the Translation Interrupt Word (see section 4.3.2). If during Y2-X3 the associated RJ does not require DPU data, X3 may be used by the DPU for reading or writing at any location in RCM except at a location in the RJ Memory block (Z slot) which the RS is presently servicing (see writeup on the RJ Scan Position Word in section 4.3.2). During the X3 times of Y3 through Y11 the DPU is allowed access with only one restriction: the DPU may not access any word in the Z slot presently activated by the RS common logic.

The difference between the two normal scans is that: in one rows 5 & 6 are scanned and in the other rows 7 & 8. The selection is made by call processing hardware.

Maintenance hardware overrides the above given conditions at certain times. The maintenance sequences are covered in section 4.4.

4.3.2 Miscellaneous RCM Data Words

In the 203rd memory block, four words have been assigned as miscellaneous RCM data words. The RJ Scan Position Word contains the address of the RJ memory block currently being addressed by the RS. It is changed each time the Z time changes. This data is used by call processing software to prevent interference which would arise by both the RS and call processing software simultaneously altering the data within an RJ slot. If software finds the RS is serving or is about to serve the slot that it wants to access, software will delay its access until the RS is finished with that RRJ slot.

The Translation Word is written at the request of RS call processing circuitry. It contains the identity of an RJ which requires a translation. This data is used by call processing software to determine which RJ slot requests a Translation.

The System Trouble Interrupt Word is written under the control of RS maintenance hardware. It contains the RJI and the identity of the row and RJ memory slot during which a System Trouble Interrupt was set. This data is used by maintenance software to identify the cause of the interrupt. The Error Count Interrupt Word contains the same data and performs the same function as the System Trouble Interrupt Word except it is used when the Error Count Interrupt is set by RS maintenance hardware.

4.3.3 Fault Snapshot Area

Block number 203 is allotted for a Fault Snapshot of 16 words. The layout of the block is given in Section 8.2 of the MSSS. This block is loaded by RS maintenance hardware at the time of the detection of a fault or when requested by the DPU (see section 4.4.3). This data is used by maintenance software to determine the cause of the RS Fault Interrupt which is set by RS maintenance hardware after the fault snapshot is stored.

4.3.4 Unused RCM

The portion of RCM which is not used by the RS may be addressed by the DPU. One instance where this is done is when maintenance software attempts to localize faults associated with the RCM. This software must access certain words of RCM within this area in order to accomplish its tasks. DPU access of words in this area is executed in the same manner as for words in any other area.

4.4 RS Maintenance Functions

From a DPU point of view, there are two important features of RS maintenance. First, RS maintenance hardware can change the status of RS sense lines, RS interrupts, and RCM contents upon the detection of a fault. Second, certain functions of RS maintenance hardware are directly controlled by outputs of the DPU both by the altering of RCM and by the use of CPD's.

RS maintenance hardware is composed of three main elements all under the general heading of the RS Maintenance Circuit (RMN). The first element is the RS Maintenance Control Unit (RMU) which controls overall maintenance functions within a CLU. There are two RMU circuits (A and B) within the RMN, one unit associated with each common logic unit of an RS. The second element, RS Maintenance Data Selector and Parity Generator (RSP), gates data to be compared into comparison gates or maintenance signals to be stored into memory under the control of the RMU. It also generates parity on the data stored into RCM and the address signals sent to RCM. The RSP is duplicated in the same manner as the RMU, one RSP associated with each common logic unit.

The third element is the RS Maintenance Comparitor (RCP) which compares the signals gated to it from each RSP. This element is not duplicated within a Register-Sender.

Within each 16-word memory block associated with Register Junctor circuits there are certain bits dedicated for maintenance.

The FB Bit (Freeze Bit) is located in word 1B position K1. When set, it instructs the RMU to prevent alteration by the CLU of any word of that RJ memory block. The DCY Field (Data Collection Y Time Field) contains four bits and is located in word 4B positions L1 to L4. The contents of DCY are used by the RMU during Data Collection (see section 4.4.3). The DCX Field (Data Collection X Time Field) contains two bits and is located in word 4B positions K2 & K3. The contents of DCX also are used by RMU during data collection. The SB Bit (System Trouble Service Bit) is located in word 4B position K1. When set it indicates to the RMU that the System Trouble Interrupt generated by this RJ Memory block has been serviced by the DPU.

4.4.1 generation of an Error Count Interrupt or Fault Interrupt

The primary hardware fault detection method used by the RS in comparisons between certain signals of the synchronously running CLU's. When a non-comparison occurs or when a secondary detector (parity circuit for example) indicates a failure the RS initiates a recycle of the operations that have just been performed. If the recycle is successful, the Error Count Word (see section 4.3.2) is written and the Error Count Interrupt is set.

If the recycle is unsuccessful the RMU sets the FB bit to 1 in the appropriate memory word of this RJ memory block, a fault snapshot is taken under the control of the RMU (see section 4.3.3), and the Fault Interrupt is set.

The RMU will ignore all further fault detections in this and other RJ slots until the Fault Interrupt is reset by a CPD.

4.4.2 generation of a System Trouble Interrupt

Synchronously-operating RCC (RS Central Control) hardware in the CLU continuously monitors several conditions during the processing of a call. The reader is referred to the REGISTER-SENDER MAINTENANCE patent applications for a discussion of the conditions which result in the setting of the System Trouble Bit (TRB) in RJ-associated memory. The CLU's will detect a system trouble during Y1 to Y4 and will each set an associated common logic flip-flop. During Y5 each RMU senses this flip-flop set and examines the system trouble interrupt status flip-flop and the system trouble Service Bit (SB) flip-flop in the RMU. If neither of these latter flip-flops is set the RMU will store the System Trouble word with the proper information from this RJ memory slot (see section 4.3.2) and set the System Trouble Interrupt. If either the interrupt or SB is set, indicating that this or another system trouble is being serviced or that this system trouble has already been serviced, no action is taken. During Y9, the Freeze Bit (FB) in RJ memory is set as well as the TRB bit whether or not the interrupt was set in Y5. The Freeze Bit prevents alteration of the contents of the Z slot until reset.

If an RJ slot is entered and the FB and TRB memory bits are set but the SB bit is not set, the RMU knows that the System Trouble for that slot has not yet been serviced. An attempt to serve it will be made in Y5 in the same manner as the initial attempt. The RMU will continue to attempt to service the Trouble until successful.

After servicing the System Trouble the processing of the RJ can be allowed to continue in the presence of the trouble by resetting the FB bit and leaving the SB bit set. This capability allows for the clearing down of the call.