Title:
SIGN DISPLAY DEVICE
United States Patent 3820107
Abstract:
In a desk top electronic calculator, a visual display device is incorporated to display the numerical information, in which a zero a zeros preceding the significant digit or digits to be displayed are suppressed. When a sign such as minus (-) is required to be displayed, such sign is displayed in the digit adjacent to the most significant digit of the number or significant digits to be displayed.
US Patent References:
NUMBER AND SYMBOL DISPLAY SYSTEM
Yanagisawa et al. - December 1970 - 3551653
/3560954.html
Yanagisawa et al. - February 1971 - 3560954
READOUT SYSTEM FOR VISUALLY DISPLAYING STORED DATA
Evans et al. - May 1972 - 3651481
NUMBER AND SYMBOL DISPLAY SYSTEM
Yanagisawa et al. - December 1970 - 3551653
/3560954.html
Yanagisawa et al. - February 1971 - 3560954
READOUT SYSTEM FOR VISUALLY DISPLAYING STORED DATA
Evans et al. - May 1972 - 3651481
Inventors:
Niizawa, Yoshiaki (Kawasaki, JA)
Hirano, Reiji (Yokohama, JA)
Ito, Matsutoshi (Narashino, JA)
Ishiata, Junichi (Yokohama, JA)
Hirano, Reiji (Yokohama, JA)
Ito, Matsutoshi (Narashino, JA)
Ishiata, Junichi (Yokohama, JA)
Application Number:
05/288738
Publication Date:
06/25/1974
Filing Date:
09/13/1972
View Patent Images:
Export Citation:
Assignee:
Canon Kabushiki Kaisha (Tokyo, JA)
Primary Class:
Other Classes:
377/40, 708/171, 345/33
International Classes:
G06F3/14; G06F15/02; G08B5/36
Field of Search:
340/324R,336 235/92EA
Primary Examiner:
Trafton, David L.
Attorney, Agent or Firm:
Fitzpatrick, Cella, Harper & Scinto
Claims:
We claim
1. A sign display device comprising:
2. A sign display device according to claim 1, wherein said memory means comprises a flip-flop.
3. A sign display device according to claim 1, wherein said memory means is arranged to store a signal from a sign detection digit of an accumulator.
4. A sign display device according to claim 3, wherein there is provided a gate through which the signal generated by said arithmetic operation means and the signal from the sign detection digit of said accumulator are applied to said memory means, said gate being connected for control by an arithmetic command control signal from an arithmetic operation command control signal generator.
5. A sign display device according to claim 1, wherein said memory means is connected to a clear circuit operable in accordance with an operation of a clear key.
6. A sign display device according to claim 1, wherein the means for controlling said display means includes:
7. A sign display device according to claim 1, wherein said arithmetic operation control unit is connected to apply its output signal to said memory means through a gate circuit controlled by a signal from an entry control unit.
8. A sign display device comprising:
9. A sign display device comprising:
10. A sign display device comprising:
11. A sign display device comprising:
1. A sign display device comprising:
2. A sign display device according to claim 1, wherein said memory means comprises a flip-flop.
3. A sign display device according to claim 1, wherein said memory means is arranged to store a signal from a sign detection digit of an accumulator.
4. A sign display device according to claim 3, wherein there is provided a gate through which the signal generated by said arithmetic operation means and the signal from the sign detection digit of said accumulator are applied to said memory means, said gate being connected for control by an arithmetic command control signal from an arithmetic operation command control signal generator.
5. A sign display device according to claim 1, wherein said memory means is connected to a clear circuit operable in accordance with an operation of a clear key.
6. A sign display device according to claim 1, wherein the means for controlling said display means includes:
7. A sign display device according to claim 1, wherein said arithmetic operation control unit is connected to apply its output signal to said memory means through a gate circuit controlled by a signal from an entry control unit.
8. A sign display device comprising:
9. A sign display device comprising:
10. A sign display device comprising:
11. A sign display device comprising:
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a sign display device.
2. Description of the Prior Art
In a conventional display device such as used in a desk top electronic calculator of the type in which the display of the information having more than two digits changes from time to time, a sign display device is incorporated therein in order to display a sign such as a minus sign (-) in a fixed digit position independently of the information being displayed when such a sign is needed.
For example in the display device capable of 12-digit decimal numbers, a minus-sign display unit is disposed in the 13th digit in order to display the minus sign (-) when required indepently of the significant digits of the number displayed. Therefore it is very inconvenient to read the number displayed with the minus sign.
SUMMARY OF THE INVENTION
The present invention has been made in order to overcome the above and other defects encountered in the prior art display device by displaying the minus sign in the digit adjacent to the most significant digit of the number displayed.
One of the objects of the present invention is to provide a novel sign display device which may display a sign without destroying the content held in a display register.
Another object of the present invention is to provide a novel sign display device which may suppress the zero or zeros in the digit or digits except the significant digit and may display a sign in a digit spaced apart by a predetermined digit length from the most significant digit of the number displayed.
BRIEF DESCRIPTION OF THE DRAWING
The above and other objects, features and advantages of the present invention will become more apparent from the following description of one preferred embodiment thereof taken in conjunction with the accompanying drawing in which:
FIG. 1 is a block diagram of one preferred embodiment of a sign display device in according to the present invention;
FIG. 2 is a diagrammatic view of a flip-flop in an entry control unit included in the device shown in FIG. 1;
FIG. 3 is a diagrammatic view of a flip-flop in an arithmetic operation control unit included in the device shown in FIG. 1;
FIG. 4 is a view illustrating display segments in a display unit of the device shown in FIG. 1;
FIG. 5 shows the waveforms of the control signals and the number to be displayed used for the explanation of the mode of operation of the preferred embodiment shown in FIG. 1;
FIG. 6 is a view used for the explanation of the mode of shift in the display device of the decimal digits as they are entered;
FIG. 7 is a block diagram of a zero suppressor circuit used in the preferred embodiment shown in FIG. 1;
FIG. 8 shows the gate signal to be used in suppressing zeros or detecting the significant digits; and
FIG. 9 is a view used for the explanation of the change in content in the register when zero suppression or detection of significant digits is effected.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The preferred embodiment of the present invention will be described as being incorporated in a desk-top calculator. A display register 11 is a dynamic circulating register with a circulation loop 13 and an OR gate 12, and holds the binary coded decimal digits to be displayed each consisting of four bits. The content in the display register 11 is circulated from the least significant digit position to the most significant digit position through the circulation loop 13 and the OR gate 12.
Four binary bits in the least significant digit position in the display register 11 are transferred in parallel into a buffer register 14 the output signals of which are applied to a decoder 15. The decoder 15 has a function of decoding the four binary bit signals into patterns signals, and has seven output terminals in order to select the desired ones out of the seven segments A-G of the seven bar format shown in FIG. 4 in a display device. The decimal point segment P is directly energized by a decimal point counter to be described hereinafter. The output terminals 16 1 -16 7 of the decoder 15 are connected to AND gates 17 1 -17 7 to which are applied the control signal to be described hereinafter.
Each of cold-cathode-discharge type display units 18 1 -18 n may display one digit or sign by the combinations of seven segments 18 1 a-18 1 g, . . . , 18 n a-18 n g and by the decimal point segments P 18 1 p-18 n p. The similar segments 18 1 a, 18 2 a, . . . , and 18 n a; 18 1 b, 18 2 b, . . . , and 18 n b; . . . ; and 18 1 f, 18 2 f, . . . and 18 n f are connected together to the AND gates 17 1 -17 6 and are designated by 18a, 18b, . . . , and 18f respectively hereinafter. The similar segment 18 1 g, . . . 18 n g, which will be designated by 18g hereinafter, are connected together to the output terminal of an OR gate 20 to which is also applied the output signal of the AND gate 17 7 . The decimal point segments 18p are connected to the decimal point counter to be described hereinafter. It is seen that the segment G shown in FIG. 4 may be used to display the minus sign (-) in the digit adjacent to the most significant digit of a significant number to be displayed. To terminals 21 1 -21 n of the anode electrodes 19 1 -19 n of the display units 18 1 -18 n are applied the digit selection pulses.
The input numerical information is fed by a keyboard 22 including a decimal point entry key into an encoder 23. The encoder 23 converts the input numerical information into the binary coded signals which are fed to the display register 11 through the OR gate 12 and to an entry control unit 24. The entry control unit 24 comprises a plurality of flip-flops FN (See FIG. 2) which are set when the binary coded signals are entered and other flip-flops. By the combinations of the output signals of the flip-flops, the various controls are effected.
The arithmetic operation command is entered by a function keyboard 25 and is converted into the binary coded signals by an encoder 26 to be applied to an arithmetic operation control unit 27. The arithmetic operation control unit 27 comprises a plurality of subtraction flip-flops FS (SEE FIG. 3) and other flip-flops which are set when the function keys such as (X), (รท) and (+) are depressed. The various arithmetic operations may be effected in response to the output signals of the flip-flops.
The output signals of the entry control unit 24 and the arithmetic operation control unit 27 are applied to an AND gate 28, the output signal of which is applied to an OR gate 29.
The carry output of an adder 30 is applied to the OR gate 29 through an AND gate 31, and the output of an accumulator 32 is also applied to the OR gate 29 through an AND gate 33. The arithmetic command control signals which are produced by an arithmetic operation command control signal generator 34 are applied to the AND gates 31 and 33. The output signal of the OR gate 29 is applied to the set terminal of a flip-flop 35. The set output signal, which is generated when the flip-flop 35 is set in response to the signal given when the minus sign must be displayed, is used to drive the display unit to display the minus sign. The flip-flop 35 is reset in response to the reset signal given by a clear circuit 36 which is activated upon depression of a clear key. The set output signal of the flip-flop 35 is applied to an AND gate 37 whose output signal is applied to the OR gate 20 so that the cathode electrode or segment 18g is energized to display the minus sign (-).
The decimal point signal entered by the keyboard 22 is stored in a decimal point counter 38 as a digit information, and the output signal of the decimal point counter 38 is applied to the cathode electrode 18p in the display units and to a zero suppressor circuit 39 which serves to display only the significant figure. More particularly the zero suppressor circuit 39 detects zero or zeros in the digits higher than the decimal point or the most significant digit, and gives the output signal to the AND gates 17 1 -17 n . Various kinds of zero suppressor circuits have been already devised and demonstrated, but in the instant embodiment the zero suppressor circuit of the type shown in FIG. 7 is used.
Next referring to FIG. 7 the zero suppressor circuit 39 will be described in detail hereinafter. The signals representing four bits in the buffer register 14 are applied to an OR gate 42 so that the latter gives the signal "0" when the binary coded signal in the buffer register represents zero but gives the signal "1" when the numeral stored in the buffer register is other than zero. The decimal point signal is applied to an OR gate 44 to which is applied the output signal of the OR gate 42. The output signal of the OR gate 45 is fed into an one-bit memory 46 and the output signal of the memory 46 is fed into a memory 49 capable of holding a group of binary bits through an OR gate 47 and an AND gate 48. Four bits in each digit in the display register 11 are compressed in one bit and stored in the memories 46 and 49. Thus the zero suppression signal may be obtained from the memory or register 49. The least significant bit in the memory 49 is applied to the OR gates 45 and 47, and the shift pulses are applied to the memories 46 and 49 in synchronism with the shift in the display register 11.
The gate signals as shown in FIG. 8 are applied to the terminal 50 of the AND gate 48. It is assumed that the display register have five digits (20 bits) and the memories 46 and 49 have one and five bits respectively. At time T 1 , T 6 , T 11 , . . . the digits in the least significant digit position in the display register are read out. The numeral 500 is stored in the display register 11 in the form of 00500. During a time interval equal to (one bit X five periods), that is a time interval between T1 and T5, the information 00500 is converted into "00100." The memory 46 holds "0" whereas the memory 49 holds "0100."
The mode of obtaining the zero suppression signals by circulating the information through the memories 46 and 49 is illustrated in FIG. 9. At TP5 the display register holds 00500 whereas the memories 46 and 49 hold 00100. At TP6 the AND gate 48 is closed, and the information is shifted to the right so that the content in D1 is transferred into D5. At TP7 the high-level signal is applied to the terminal 50 of the AND gate 48, and the content in D1 is shifted to D5 and is also transferred into D4 through the OR gate 47 and the AND gate 48. However, the binary bit in D1 is "0" so that the content in D4 remains unchanged. At TP8 the shift is made in a similar manner, but the binary bit in D1 is "1" the binary bit in D4 changes into "1." At TP10 the content in the memory 49 changes to "00110." When the content is circulated again, it changes into "00111" and will not change even when it is recirculated. Three binary bits "1" indicate the digits to be displayed.
The output signal of the zero suppressor circuit 39 is at a high level E1 as shown in FIG. 5-II when the digits to be displayed exist, and falls to a low level E 2 when the zeros are suppressed. FIG. 5-I shows the digits to be displayed which are obtained from the display register 11.
Referring back to FIG. 1, the output signal of the zero suppressor circuit 39 is delayed by one bit time by a delay line 40 comprising a flip-flop or the like, and the output signal shown in FIG. 5-III and the inverted output signal of the zero suppressor circuit 39 are applied to an AND gate 41, which in turn gives the pulses (FIG. 5-IV) at the digit adjacent to the most significant digit to the AND gate 37.
Next the mode of displaying a negative number will be described. When the negative sign key (not shown) on the keyboard 25 is depressed, the flip-flop FS in the arithmetic operation control circuit 27 is set so that the high-level output signal is applied to the AND gate 28, but the latter is closed so that the minus sign (-) is not displayed. When the key "5" on the keyboard 22 is depressed, the numeral "5" is encoded by the encoder 23 and is applied to the entry control circuit 24 and to the display register 11. A binary coded digit in the display register 11 is transferred into the buffer register 14. The output signals of the buffer register 14 are decoded by the decoder 15, and are also applied to the zero suppressor circuit 39 so that the latter gives the high-level signal BS to the AND gates 17 1 -17 7 for a time equal to one digit time.
The decoder 15 gives the segment selection signals so that the segments A, C, D, F and G (See FIG. 7) in the display unit 18 2 are energized to display "5." In response to the depression of the key "5," the flip-flop FN in the entry control circuit 24 is set so that the set output signal is applied to the AND gate 28. Since the set output signal from the flip-flop FS in the arithmetic operation control circuit 27 is already applied to the AND gate 28, the latter is opened so that the output signal is applied through the OR gate 29 to the flip-flop 35 to reset it. The output signal of the flip-flop 35 is applied to the AND gate 37 to which is also applied the output signal X of the AND gate 41. This output signal X is BS . BS + 1 or BS . BS + 1 because the output signal BS of the zero suppressor circuit 39 and the output signal BS + 1 of the delay line 40 are applied to the AND gate 41 which gives the logical product of the two output signals.
Therefore the signal X rises to a high level for one digit time as soon as the signal BS of the zero suppressor circuit 39 falls from the high level to low level as shown in FIG. 5-IV. In other words, the AND gate 37 is opened for one digit time immediately when the output signal BS or the signal indicating the digits to be displayed of the zero suppressor circuit 39 disappears while the flip-flop 35 is set. The output signal of the AND gate 37 is applied to the segment G (See FIG. 4) through the OR gate 20, so that the segment G is energized to display the minus sign (-). In summary the signal X appears immediately after the signal BS falls to a low level so that the minus sign (-) is displayed in the digit adjacent to the digit "5." Hence "-5" may be displayed.
When the signal X is at high level, the zero suppression signal BS is at low level; the digit pulse has been already applied to the digit at which a numeral is to be displayed; and the signal X remains at high level during the time when the digit pulse is applied to the digit adjacent to the digit at which a numeral is to be displayed.
Whenever the next numerals are entered, the numerals with the minus sign are shifted to the left in the display device as shown in FIG. 6. In the instant embodiment, two zeros are entered after "5."
From the foregoing description it is seen that according to the present invention the minus sign (-) may be displayed in the digit adjacent to the most significant digit of the decimal number displayed by the logic product of the outputs of the zero suppressor circuit and the one-bit delay line.
So far the minus sign (-) has been described as being displayed upon depression of the minus key, but in practice the minus sign (-) must be displayed many times even when the minus key is not depressed because the result of the arithmetic operation is negative. In this case, the flip-flop 35 is set when the logic product of the carry signal of the adder 30 and the subtraction command signal SUB from the arithmetic operation control signal generator 34.
When the result of the ariehmetic operation is negative, the AND gate 33 is applied with a signal representing that the minus-sign signal is stored in the sign detection digit in the accumulator 32. In this case, the multiplication command, division command or the like is applied to the AND gate 33 from the arithmetic operation control signal generator 34. When the negative number is multiplied or divided, the result is always a negative number so that the flip-flop 35 is set in order to display the minus sign (-) in the digit adjacent to the most significant digit to be displayed. When it is desired to eliminate the minus sign, the signal may be applied to the reset terminal of the flip-flop 35 so that the latter may be reset and may give no output signal. This will be described in more detail with reference to the clear circuit 36.
When the clear key (not shown) is depressed, not only the minus sign but also the number must be cleared. When the entry keys are depressed to enter "-4 + 5 = 1" the minus sign (-) is once displayed, but the result of the arithmetic operation is positive. Therefore when the result is positive, the flip-flop 35 must be reset. In like manner the flip-flop 35 may be reset when it is desired to eliminate the minus sign.
1. Field of the Invention
This invention relates to a sign display device.
2. Description of the Prior Art
In a conventional display device such as used in a desk top electronic calculator of the type in which the display of the information having more than two digits changes from time to time, a sign display device is incorporated therein in order to display a sign such as a minus sign (-) in a fixed digit position independently of the information being displayed when such a sign is needed.
For example in the display device capable of 12-digit decimal numbers, a minus-sign display unit is disposed in the 13th digit in order to display the minus sign (-) when required indepently of the significant digits of the number displayed. Therefore it is very inconvenient to read the number displayed with the minus sign.
SUMMARY OF THE INVENTION
The present invention has been made in order to overcome the above and other defects encountered in the prior art display device by displaying the minus sign in the digit adjacent to the most significant digit of the number displayed.
One of the objects of the present invention is to provide a novel sign display device which may display a sign without destroying the content held in a display register.
Another object of the present invention is to provide a novel sign display device which may suppress the zero or zeros in the digit or digits except the significant digit and may display a sign in a digit spaced apart by a predetermined digit length from the most significant digit of the number displayed.
BRIEF DESCRIPTION OF THE DRAWING
The above and other objects, features and advantages of the present invention will become more apparent from the following description of one preferred embodiment thereof taken in conjunction with the accompanying drawing in which:
FIG. 1 is a block diagram of one preferred embodiment of a sign display device in according to the present invention;
FIG. 2 is a diagrammatic view of a flip-flop in an entry control unit included in the device shown in FIG. 1;
FIG. 3 is a diagrammatic view of a flip-flop in an arithmetic operation control unit included in the device shown in FIG. 1;
FIG. 4 is a view illustrating display segments in a display unit of the device shown in FIG. 1;
FIG. 5 shows the waveforms of the control signals and the number to be displayed used for the explanation of the mode of operation of the preferred embodiment shown in FIG. 1;
FIG. 6 is a view used for the explanation of the mode of shift in the display device of the decimal digits as they are entered;
FIG. 7 is a block diagram of a zero suppressor circuit used in the preferred embodiment shown in FIG. 1;
FIG. 8 shows the gate signal to be used in suppressing zeros or detecting the significant digits; and
FIG. 9 is a view used for the explanation of the change in content in the register when zero suppression or detection of significant digits is effected.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The preferred embodiment of the present invention will be described as being incorporated in a desk-top calculator. A display register 11 is a dynamic circulating register with a circulation loop 13 and an OR gate 12, and holds the binary coded decimal digits to be displayed each consisting of four bits. The content in the display register 11 is circulated from the least significant digit position to the most significant digit position through the circulation loop 13 and the OR gate 12.
Four binary bits in the least significant digit position in the display register 11 are transferred in parallel into a buffer register 14 the output signals of which are applied to a decoder 15. The decoder 15 has a function of decoding the four binary bit signals into patterns signals, and has seven output terminals in order to select the desired ones out of the seven segments A-G of the seven bar format shown in FIG. 4 in a display device. The decimal point segment P is directly energized by a decimal point counter to be described hereinafter. The output terminals 16 1 -16 7 of the decoder 15 are connected to AND gates 17 1 -17 7 to which are applied the control signal to be described hereinafter.
Each of cold-cathode-discharge type display units 18 1 -18 n may display one digit or sign by the combinations of seven segments 18 1 a-18 1 g, . . . , 18 n a-18 n g and by the decimal point segments P 18 1 p-18 n p. The similar segments 18 1 a, 18 2 a, . . . , and 18 n a; 18 1 b, 18 2 b, . . . , and 18 n b; . . . ; and 18 1 f, 18 2 f, . . . and 18 n f are connected together to the AND gates 17 1 -17 6 and are designated by 18a, 18b, . . . , and 18f respectively hereinafter. The similar segment 18 1 g, . . . 18 n g, which will be designated by 18g hereinafter, are connected together to the output terminal of an OR gate 20 to which is also applied the output signal of the AND gate 17 7 . The decimal point segments 18p are connected to the decimal point counter to be described hereinafter. It is seen that the segment G shown in FIG. 4 may be used to display the minus sign (-) in the digit adjacent to the most significant digit of a significant number to be displayed. To terminals 21 1 -21 n of the anode electrodes 19 1 -19 n of the display units 18 1 -18 n are applied the digit selection pulses.
The input numerical information is fed by a keyboard 22 including a decimal point entry key into an encoder 23. The encoder 23 converts the input numerical information into the binary coded signals which are fed to the display register 11 through the OR gate 12 and to an entry control unit 24. The entry control unit 24 comprises a plurality of flip-flops FN (See FIG. 2) which are set when the binary coded signals are entered and other flip-flops. By the combinations of the output signals of the flip-flops, the various controls are effected.
The arithmetic operation command is entered by a function keyboard 25 and is converted into the binary coded signals by an encoder 26 to be applied to an arithmetic operation control unit 27. The arithmetic operation control unit 27 comprises a plurality of subtraction flip-flops FS (SEE FIG. 3) and other flip-flops which are set when the function keys such as (X), (รท) and (+) are depressed. The various arithmetic operations may be effected in response to the output signals of the flip-flops.
The output signals of the entry control unit 24 and the arithmetic operation control unit 27 are applied to an AND gate 28, the output signal of which is applied to an OR gate 29.
The carry output of an adder 30 is applied to the OR gate 29 through an AND gate 31, and the output of an accumulator 32 is also applied to the OR gate 29 through an AND gate 33. The arithmetic command control signals which are produced by an arithmetic operation command control signal generator 34 are applied to the AND gates 31 and 33. The output signal of the OR gate 29 is applied to the set terminal of a flip-flop 35. The set output signal, which is generated when the flip-flop 35 is set in response to the signal given when the minus sign must be displayed, is used to drive the display unit to display the minus sign. The flip-flop 35 is reset in response to the reset signal given by a clear circuit 36 which is activated upon depression of a clear key. The set output signal of the flip-flop 35 is applied to an AND gate 37 whose output signal is applied to the OR gate 20 so that the cathode electrode or segment 18g is energized to display the minus sign (-).
The decimal point signal entered by the keyboard 22 is stored in a decimal point counter 38 as a digit information, and the output signal of the decimal point counter 38 is applied to the cathode electrode 18p in the display units and to a zero suppressor circuit 39 which serves to display only the significant figure. More particularly the zero suppressor circuit 39 detects zero or zeros in the digits higher than the decimal point or the most significant digit, and gives the output signal to the AND gates 17 1 -17 n . Various kinds of zero suppressor circuits have been already devised and demonstrated, but in the instant embodiment the zero suppressor circuit of the type shown in FIG. 7 is used.
Next referring to FIG. 7 the zero suppressor circuit 39 will be described in detail hereinafter. The signals representing four bits in the buffer register 14 are applied to an OR gate 42 so that the latter gives the signal "0" when the binary coded signal in the buffer register represents zero but gives the signal "1" when the numeral stored in the buffer register is other than zero. The decimal point signal is applied to an OR gate 44 to which is applied the output signal of the OR gate 42. The output signal of the OR gate 45 is fed into an one-bit memory 46 and the output signal of the memory 46 is fed into a memory 49 capable of holding a group of binary bits through an OR gate 47 and an AND gate 48. Four bits in each digit in the display register 11 are compressed in one bit and stored in the memories 46 and 49. Thus the zero suppression signal may be obtained from the memory or register 49. The least significant bit in the memory 49 is applied to the OR gates 45 and 47, and the shift pulses are applied to the memories 46 and 49 in synchronism with the shift in the display register 11.
The gate signals as shown in FIG. 8 are applied to the terminal 50 of the AND gate 48. It is assumed that the display register have five digits (20 bits) and the memories 46 and 49 have one and five bits respectively. At time T 1 , T 6 , T 11 , . . . the digits in the least significant digit position in the display register are read out. The numeral 500 is stored in the display register 11 in the form of 00500. During a time interval equal to (one bit X five periods), that is a time interval between T1 and T5, the information 00500 is converted into "00100." The memory 46 holds "0" whereas the memory 49 holds "0100."
The mode of obtaining the zero suppression signals by circulating the information through the memories 46 and 49 is illustrated in FIG. 9. At TP5 the display register holds 00500 whereas the memories 46 and 49 hold 00100. At TP6 the AND gate 48 is closed, and the information is shifted to the right so that the content in D1 is transferred into D5. At TP7 the high-level signal is applied to the terminal 50 of the AND gate 48, and the content in D1 is shifted to D5 and is also transferred into D4 through the OR gate 47 and the AND gate 48. However, the binary bit in D1 is "0" so that the content in D4 remains unchanged. At TP8 the shift is made in a similar manner, but the binary bit in D1 is "1" the binary bit in D4 changes into "1." At TP10 the content in the memory 49 changes to "00110." When the content is circulated again, it changes into "00111" and will not change even when it is recirculated. Three binary bits "1" indicate the digits to be displayed.
The output signal of the zero suppressor circuit 39 is at a high level E1 as shown in FIG. 5-II when the digits to be displayed exist, and falls to a low level E 2 when the zeros are suppressed. FIG. 5-I shows the digits to be displayed which are obtained from the display register 11.
Referring back to FIG. 1, the output signal of the zero suppressor circuit 39 is delayed by one bit time by a delay line 40 comprising a flip-flop or the like, and the output signal shown in FIG. 5-III and the inverted output signal of the zero suppressor circuit 39 are applied to an AND gate 41, which in turn gives the pulses (FIG. 5-IV) at the digit adjacent to the most significant digit to the AND gate 37.
Next the mode of displaying a negative number will be described. When the negative sign key (not shown) on the keyboard 25 is depressed, the flip-flop FS in the arithmetic operation control circuit 27 is set so that the high-level output signal is applied to the AND gate 28, but the latter is closed so that the minus sign (-) is not displayed. When the key "5" on the keyboard 22 is depressed, the numeral "5" is encoded by the encoder 23 and is applied to the entry control circuit 24 and to the display register 11. A binary coded digit in the display register 11 is transferred into the buffer register 14. The output signals of the buffer register 14 are decoded by the decoder 15, and are also applied to the zero suppressor circuit 39 so that the latter gives the high-level signal BS to the AND gates 17 1 -17 7 for a time equal to one digit time.
The decoder 15 gives the segment selection signals so that the segments A, C, D, F and G (See FIG. 7) in the display unit 18 2 are energized to display "5." In response to the depression of the key "5," the flip-flop FN in the entry control circuit 24 is set so that the set output signal is applied to the AND gate 28. Since the set output signal from the flip-flop FS in the arithmetic operation control circuit 27 is already applied to the AND gate 28, the latter is opened so that the output signal is applied through the OR gate 29 to the flip-flop 35 to reset it. The output signal of the flip-flop 35 is applied to the AND gate 37 to which is also applied the output signal X of the AND gate 41. This output signal X is BS . BS + 1 or BS . BS + 1 because the output signal BS of the zero suppressor circuit 39 and the output signal BS + 1 of the delay line 40 are applied to the AND gate 41 which gives the logical product of the two output signals.
Therefore the signal X rises to a high level for one digit time as soon as the signal BS of the zero suppressor circuit 39 falls from the high level to low level as shown in FIG. 5-IV. In other words, the AND gate 37 is opened for one digit time immediately when the output signal BS or the signal indicating the digits to be displayed of the zero suppressor circuit 39 disappears while the flip-flop 35 is set. The output signal of the AND gate 37 is applied to the segment G (See FIG. 4) through the OR gate 20, so that the segment G is energized to display the minus sign (-). In summary the signal X appears immediately after the signal BS falls to a low level so that the minus sign (-) is displayed in the digit adjacent to the digit "5." Hence "-5" may be displayed.
When the signal X is at high level, the zero suppression signal BS is at low level; the digit pulse has been already applied to the digit at which a numeral is to be displayed; and the signal X remains at high level during the time when the digit pulse is applied to the digit adjacent to the digit at which a numeral is to be displayed.
Whenever the next numerals are entered, the numerals with the minus sign are shifted to the left in the display device as shown in FIG. 6. In the instant embodiment, two zeros are entered after "5."
From the foregoing description it is seen that according to the present invention the minus sign (-) may be displayed in the digit adjacent to the most significant digit of the decimal number displayed by the logic product of the outputs of the zero suppressor circuit and the one-bit delay line.
So far the minus sign (-) has been described as being displayed upon depression of the minus key, but in practice the minus sign (-) must be displayed many times even when the minus key is not depressed because the result of the arithmetic operation is negative. In this case, the flip-flop 35 is set when the logic product of the carry signal of the adder 30 and the subtraction command signal SUB from the arithmetic operation control signal generator 34.
When the result of the ariehmetic operation is negative, the AND gate 33 is applied with a signal representing that the minus-sign signal is stored in the sign detection digit in the accumulator 32. In this case, the multiplication command, division command or the like is applied to the AND gate 33 from the arithmetic operation control signal generator 34. When the negative number is multiplied or divided, the result is always a negative number so that the flip-flop 35 is set in order to display the minus sign (-) in the digit adjacent to the most significant digit to be displayed. When it is desired to eliminate the minus sign, the signal may be applied to the reset terminal of the flip-flop 35 so that the latter may be reset and may give no output signal. This will be described in more detail with reference to the clear circuit 36.
When the clear key (not shown) is depressed, not only the minus sign but also the number must be cleared. When the entry keys are depressed to enter "-4 + 5 = 1" the minus sign (-) is once displayed, but the result of the arithmetic operation is positive. Therefore when the result is positive, the flip-flop 35 must be reset. In like manner the flip-flop 35 may be reset when it is desired to eliminate the minus sign.