05/205098

04/30/1974

12/06/1971

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Gretag Aktiengesellschaft (Regensdorf, CH)

380/47

380/260

H04L9/12; H04L9/02

178/22

Wilbur, Maynard R.

Birmiel H. A.

Pierce, Scheffler & Parker

1. A method of encoding and decoding messages comprising;

2. A method according to claim 1 including generating the fifth series of pulses in the same way as the third series of pulses are generated and synchronising the generation of said fifth series of pulses with said

3. A method according to claim 1, including providing said second series of pulses by means of a first clock, and at the receiving station providing by means of a second clock a sixth series of pulses representing the time of day, providing a seventh series of pulses representing said code program data, mixing the sixth series of pulses with said seventh series of pulses to provide said fifth series of pulses and synchronising the

4. A method according to claim 3 including generating said third and fifth series of pulses during intervals between the transmission of messages as

5. A method according to claim 3 including detecting the difference in time between the first and second clocks and synchronising the second clock with the first clock prior to mixing the fifth series of pulses with the

6. A method according to claim 1 including providing said second series of pulses by means of a first clock, and at the receiving station providing by means of a second clock a sixth series of pulses representing the time of day, providing a seventh series of pulses representing said code program data, mixing the sixth series of pulses with said seventh series of pulses to provide said fifth series of pulses, independently maintaining the time indication of the first and second clocks within predetermined limits, transmitting at least part of the third series of pulses, correlating said part of the third series of pulses with said fifth series of pulses to thereby derive a signal representing the time deviation between the second and first clocks, and synchronising said fifth series of pulses with the reception of the remaining part of said

7. A method according to claim 6 including storing said signal representing the time deviation, retarding the second clock by the amount of said deviation prior to decoding the received encoded message and resetting the second clock to its original setting by applying thereto the stored signal

8. A method according to claim 6 including storing said signal representing the time deviation and synchronising only the third and fifth series of

9. A method according to claim 6 including storing at said receiving station in separate stores time deviations between said first clock and second clocks in transmitting stations with which the receiving station communicates and using a stored time deviation associated with that transmitting station with which said receiver establishes a connection to synchronise the fifth series of pulses with the third series of pulses produced at that transmitting station upon reception of each coded

10. A method according to claim 6 including providing in each said second and sixth series of pulses, pulses of different predetermined values ranging from pulses having low values to those having high values which are integral multiples of said low values, the period of the pulses of highest value being greater than twice the maximum permissible time deviation between the first and second clocks and the period of the pulses of low value corresponding to the period of the message pulses in said fourth series of pulses, and further providing different identification

11. A method according to claim 10 including bringing pulses having the lowest value in the second series of pulses into time coincidence with pulses having a corresponding value in the sixth series of pulses, then bringing pulses having the next lowest value in the second series of pulses into time coincidence with pulses having a corresponding value in the sixth series of pulses and so on until the pulses in the second and sixth series of pulses having the corresponding highest values are brought into time coincidence thereby effecting synchronisation between the pulses of the received encoded message and the pulses in the fifth series of

12. A method according to claim 11 wherein said different predetermined values are different amplitude values of the corresponding different

13. A method according to claim 11 wherein said different predetermined values are different pulse durations of the corresponding different

14. A method according to claim 6 including binary coded pulses in said second series of pulses, the binary coded pulses forming groups of pulses, each group including sets of pulses, each set of a group representing the same clocktime and other groups representing different clocktime and

15. A method according to claim 14 including providing before each pulse

16. A method according to claim 14 in which the pulses in the last set of pulses in a group are arranged in reverse order to the pulses in the other sets and each pulse in said last set is coded with the opposite binary

17. A method according to claim 6 in which the pulses of said second and sixth series of pulses are arranged in groups, each group having associated therewith pulses coded to identify that group, and having sets of pulses each set including a group of binary coded pulses representing

18. A method according to claim 17 in which each set of pulses also includes binary coded pulses representing a correlation value, said method further including comparing the correlation value in the encoded message received at the receiving station with the correlation value in said fifth series of pulses to provide a signal to synchronise the encoded message

19. A method according to claim 17 including comparing the binary coded pulses representing at least part of the time indication of said first clock in one group of pulses in said second series of pulses with the binary coded pulses representing at least part of the time indication of said second clock in one corresponding group of pulses in said sixth series of pulses and using the difference between the compared time indications to correct the second clock to synchronise the encoded message

20. A method according to claim 1 including providing said second series of pulses by means of a first clock, and at the receiving station providing by means of a second clock a sixth series of pulses representing the time of day, providing a seventh series of pulses representing said code program data, mixing the sixth series of pulses with said seventh series of pulses to provide said fifth series of pulses and independantly maintaining the time indications of the first and second clocks in

21. A method according to claim 20 including producing a first pulse template of p digits at the transmitting station, transmitting the first pulse template to the receiving station, producing at the receiving station a second pulse template identical to the first template each template having a time duration greater than twice the maximum permissible time deviation between the first and second clocks, the first and second templates being arranged to provide a plurality of low correlation values when compared with each other in p-1 pulse template positions and a high correlation value in only one single position and synchronising the fifth series of pulses with the received encoded message by the correlation values produced during correlation of the first and second pulse

22. A method according to claim 21 in which a plurality of identical pulse templates are produced at the transmitting and receiving station, and correlating corresponding pairs of pulse templates to effect

23. A method according to claim 22 in which each template produced at the receiving station is different from the others of said plurality, each

24. A method according to claim 22 including preceding each template produced at the transmitting and receiving stations with a coded value of the first and second clocktimes respectively and utilising the difference in value between the clocktimes associated with those pulse templates producing said highest correlation value to effect synchronisation between

25. A method according to claim 20 including correlating the received encoded message in sections with corresponding sections of the fifth series of pulses to determine the difference in time indicated by said first and second clocks, stopping or retarding the second clock by at least the maximum permissible value by which the second clock can be advanced, increasing the second clock rate to correlate corresponding sections of the encoded message and the fifth series of pulse at an increased speed, and after one correlation of said sections, if syncronisation is not achieved, shifting said section of the fifth series of pulses relative to said encoded message and correlating said encoded message with the shifted section of the fifth series of pulses and continuing to correlate and shift until synchronism is achieved and then

26. A method according to claim 1 including mixing parts of the first series of pulses with the second series of pulses to form said third

27. Apparatus for encoding and decoding messages comprising,

28. Apparatus according to claim 27 wherein said clock supplies timing

29. Apparatus according to claim 27 including a correlation circuit responsive to the pulses produced by said code pulse generator and encoded message pulses received from a transmitting station, the correlation circuit being sequentially operable and having and adjustable threshold value, and further including a recirculating shift register for circulating the pulses from said code pulse generator to correlate them

30. Apparatus according to claim 29 in which said shift register is operable at two different speeds.

This invention relates to a method for the encoded transmission of messages in which the clear language message pulses are mixed on the transmitting side with coding pulses and the clear message pulses are restored on the receiving side by mixing the received coded pulse train with identical coding pulses, the coding pulses being generated at the transmitting and receiving stations by identical pulse generators in accordance with identical rules based on a secret basic code and a term derived from the date and time.

BACKGROUND OF THE INVENTION

In a previously proposed method of this kind the rules for forming the coding pulse sequences are selected so that they depend on the initial state of coding pulse generators, the initial state itself being defined by basic and supplementary codes. Since the coding pulse generators are set to a new initial state for each new message transmission it is impossible -- even for authorised third parties -- to gain access to a connection which is already established and over which a coded message is being transmitted. This is a disadvantage, in particular in multiple transmission networks.

The invention seeks to avoid this disadvantage by forming the coding pulse sequences in accordance with rules selected so that the last mentioned sequence depends only for a limited period of time on the condition of its terms at the beginning of the said period of time and that the instantaneous state of the data contained in all the storage cells of the coding pulse generator is constantly influenced by the term derived from the data and time, at least during message transmission.

SUMMARY OF THE INVENTION

In a method according to the invention the initial state of the coding pulse generators is no longer preset, instead the instantaneous state of the data in the storage cells of the coding pulse generator are constantly influenced by a term derived from the date and time, that is to say the initial state of the coding pulse generator is constantly reset. Moreover, the rules for forming the coding pulse sequences are selected so that these sequences depend only for a limited period of time on the state of their terms at the beginning of the said period of time. This means that the initial data produced by the coding pulse generator at an instant in time depends only on the input data which occurs during a predetermined period of time prior to that instant and is independent of all input data applied earlier. An authorised third party may without difficulty gain access to an existing encoded message transmission since he need only wait for those moments in time at which the coding pulse sequence which occurs at the output of the coding pulse generator at the transmitting station is independent of the secret and supplementary coding states occuring prior to the aforementioned moments in time and in which the instantaneous state of the coding pulse generator is influenced by the term derived from the date and time.

In practice this means that the third party switches on his receiver at any desired moment in time, the receiver then automatically switching itself into the existing connection at the next possible moment in time.

This invention furthermore provides apparatus for performing the aforementioned method, the apparatus having a clock, preferably electronic, and a coding pulse generator which may be driven by a control pulse sequence formed from a secret basic code and from a term derived from the date and time. The coding pulse generator may be programmed so that each coding pulse at the output of the coding pulse generator remains unaffected by that part of the control pulse sequence which occurs prior to the affected coding pulse by an amount of time equal to the so-called passage time and that the passage time switches from a larger to a smaller value for a predetermined period of time and at intervals which depend on the secret code.

In a preferred embodiment of the invention described in detail hereinafter the clock is connected as a timing generator for the coding pulse generator.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described in detail with reference to the accompanying drawings in which:

FIG. 1 is a block diagram of a coding apparatus.

FIGS. 2a and 2b are details of FIG. 1.

FIGS. 3 to 6 are graphs illustrating the pulses used in synchronising two sets of coding apparatus.

FIGS. 7, 8 illustrate detail modifications of FIG. 1.

FIGS. 9, 10 are diagrams showing the function of synchronising sets of coding apparatus.

FIGS. 11, 12 are detail variations of FIG. 1.

FIGS. 13, 14 are diagrams for explaining the synchronising stage illustrated in FIG. 12, and

FIGS. 15 to 20 show detail variations of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

As shown in FIG. 1, each coding station is provided with a clear language text-clear language pulse converter 9, the converter being adapted to convert the clear language message text into clear language message pulses at the transmitter or vice versa at the receiver. This converter may be, for example, a teleprinter. The output of the transmitter station converter feeds the clear language message pulses through a conductor 147 into a mixer 8 the output of which is connected to the transmission line 148, which may be a cable, wire or radio link. When using the above described coding apparatus as a receiver, the transmission line 148' is connected to a mixer 8 the output of which feeds a converter 9 through a conductor 102. To facilitate encoding, the mixer 8 is provided with encoding pulse sequences from coding apparatus which are mixed in the transmitter station mixer with the clear language message pulse sequences generated by the clear language text-clear language pulse converter 9. The pulse sequences thus encoded and received on conductor 148' are mixed with decoding pulse sequences identical to the encoding pulse sequences and fed to the clear language text-clear language pulse converter at the receiving station which restores the received encoded pulse sequences to the clear language message text.

The coding apparatus mainly comprises an encoding pulse generator 5 and a synchronising stage 6. The purpose of the coding pulse generator 5 is to produce a coding pulse sequence with the longest possible cycle and which is built up in such a way that variation between successive elements or element groups is as random as possible. The coding pulse generator comprises a number of storage positions, connectable to each other by electronic circuits which may be influenced by a secret basic code. The secret basic code is usually constant over a prolonged period of time. The instantaneous state at any time of the coding pulse generator, the instantaneous state in this context referring to the state of the data in all the storage cells, is defined by means of a variable supplementary routine, the so-called supplementary code.

The coding pulse generator 5 is provided with two inputs and two outputs; one input is connected through a conductor 140 to the output of a modulo-2 mixer 18, the other input being connected through a conductor 7 to a date/time store 1. One of the two outputs of the coding pulse generator 5 is connected through a conductor 81 to the mixer 8 and the other input is connected through a conductor 82 to the synchronising stage 6. The modulo-2 mixer 18 in turn is provided with two inputs of which one is connected through a conductor 154 to a number store 2 and to the date/time store 1 and the other is connected through a conductor 144 to a secret code store 3. The purpose of the date/time store 1 on the one hand is to function as a store for the supplementary code which is applied to the conductor 154, and on the other hand to function as timing generator for the coding pulse generator 5 and for the secret code store 3 to which it is connected via conductor 7. The date/time store 1 comprises an electronic clock which delivers data representing the day (T), month, year, hour, minute and second (sec) at predetermined intervals, for example once every second, to the modulo-2 mixer 18. It is obvious that because of its complete freedom from repeating the same data the output signal from the date/time store 1 is ideally suited as a supplementary code for mixing with the routine of the secret code store 3. The number store 2 is provided for storing a subscriber or address number represented by a three-digit number H (hundreds), Z (tens), E (ones) its purpose being to differentiate the coding pulse routine for different subscribers in different transmission networks while using the same secret code with the same date and tome. While the supplementary code alters continuously, the subscriber number in the number store 2 is usually constant for a given message transmission. The subscriber number may be manually fed into the number store 2. The date/time data is usually generated in the date/time store 1. To increase the variability of the supplementary data, that is the date/time supplementary code and subscriber number, it is possible for a separate store (not shown) to be provided for non-secret supplementary data, the store being connected so that its output signal is mixed with the date/time supplementary code and/or of the subscriber number. Furthermore, the secret code store 3 may be connected to the date/time store 1 and/or to the number store 2 so that predetermined parts of the data in the secret code store may be selected for combining with the contents of the date/time store and/or of the number store. The secret code store 3 may for example comprise a random access memory (RAM) which may be electronically interrogated and which is capable of delivering the stored data continuously and in sequence to the modulo-2 mixer. The output signal of the modulo-2 mixer 18 and therefore the input data to the coding pulse generator 5 depends on the secret code, the date/time supplementary code, the subscriber number and possibly on further supplementary data. Since of all such data only the secret code is actually secret and since the instantaneous state at any given time of the coding pulse generator is redefined at brief intervals by the date/time supplementary code, it is possible for an authorised subscriber having a coding pulse generator which is identical with the coding pulse generator at the appropriate transmitter and having knowledge of the non-secret supplementary data to gain access to an existing encoded message transmission provided his coding pulse generator is so constructed that the coding pulse sequences which occur at its output depend only for a limited period of time on the pulse sequences fed in to the input at the beginning of the said period of time.

According to FIG. 2a the incoming circuit 140 of the coding pulse generator 5 is connected to the input of a shift register 139. The output of shift register 139 is connected to the first input of a modulo-2-mixer 74. From the output of the modulo-2-mixer 74 the data flow, the principal direction of which is indicated by arrows D, passes through two shift register chains 73 and 611 and through modulo-2-mixers 118, 119 and 120 and through an AND circuit 908 to the output circuits 81 and 82 of the coding pulse generator 5. After the output of modulo-2-mixer 120 a circuit 518 branches from the data flow principal path. The circuit 518 is connected through an AND circuit 583 to the second input of modulo-2-mixer 74.

Data flow control circuits 500 are connected to the four-stage shift registers 73, said data flow circuits obtaining their input data from the shift register chain 73 to produce therefrom data control functions which act through AND circuits 75 on modulo-2-mixers 901, said modulo-2-mixers being arranged within shift register chain 611. Within the shift register chain 611 there are also arranged modulo-2-mixers 907, into which from data flow principal path branching and shift register chain 611 partly bridging data flow shunt paths 900 enter. Therefore, the data flow of data flow shunt paths is mixed with the data flow of data flow principal path.

The data flow control circuits 500 are constructed as binary dividers and are controlled by a timing step-down unit 112 and by the timing frequency on the incoming circuit 7, said timing frequency determining the timing frequency of the code pulse generator 5. The bit frequency is substantially lower than the timing frequency of the code pulse generator. The timing for the bit frequency is also obtained from the timing step-down unit 112, namely from its tapping t _B .

The output of one of the data flow control circuits 500 will be set to a logic "1" during a fraction of the time occupied by a counting period of the binary divider forming the control circuit so that the associated AND circuit 75 is driven into the conductive state and the data in the associated shift register 611 is "circulated." During the remaining period of time of the aforementioned counting period the output of the data flow control circuit will be set to a logic "0" and the associated circuit 75 will be driven to cut-off. The magnitude of the two time proportions is defined by the data of the associated shift register 73 at the moment at which each counting period begins The data flow control circuits 500, cooperating with AND circuits 75 and modulo-2-mixers 901 cause intermittent "circulation" of the data flow contained in the shift register 611.

Periodic setting of the initial position of the data flow circuits 500 is performed by timing step-down unit 112, said unit having a period containing sixteen cycles for each data flow control function. Since the total length of the shift register 73 is equal to 4 × 4 = 16 stages, this ensures that each individual input bit contributes to the formation of one of the four data flow control functions. Each of the four shift register stores 611 may be constructed as 64-stage units (MOS shift registers). The number of stages of these four shift registers may however also be four different prime numbers, for example the numbers 47, 59, 61 and 71. In association with the forward feed data flow path 900 this results in a continuously varying relative time position of the individual data flows.

The controllable feedback path 58 is returned through the AND circuit 583 to the mixer 74 (input). The aforementioned AND circuit is controlled by the bistable stage 110. The bistable stage 110 in turn is controlled through AND circuits 115 and 116 on the one hand by a bistable stage 511 and on the other hand by an AND circuit 114. The last mentioned AND circuit receives its data from shift register 139. The bistable stage 511 is driven through capacitors 117 from different tappings L (slow), S (fast). The time of the fast step-down (S) may amount to approximately 0.1 s and that of the slow stage (L) may amount to for example 10 s. The method of operation is such that pulses of the fast tapping (step-down stage) S trigger the bistable stage 511 which is swept back by pulses of the slow tapping (step-down stage) L. Since the pulses from L arrive only rarely, for example every 10 seconds, while those derived from S arrive in a brief sequence, for example every 0.1 seconds, it follows that the bistable stage 511 will be predominantly (practically every 10 seconds) in a position corresponding to the setting pulses of stage S. If the right hand upper output of the bistable stage 511 were to be connected directly to the AND circuit 583, the circuit and therefore the feedback 518 would be switched on for approximately 10 seconds and would be switched off briefly for approximately 0.1 seconds. The shift register 139 and the AND circuit 114 are however also provided in order to prevent unauthorized parties from gaining knowledge of the switching-on moments and switching-off moments which are thus also made dependent on the secrecy code. This circuit ensures that the bistable stage 110 is triggered only if a certain data combination (code word) is present in the shift register 139. Sweeping back is influenced in the same manner. Accordingly, the switching-on moment and switching-off moment of the feedback path is rendered dependent on the secrecy code.

The time during which the feedback is interrupted, for example 0.1 seconds is so chosen that during the aforementioned feedback-free time all store positions of the coding pulse generator are provided with a fresh data inflow. The operating interval of the closed feedback path of, for example, 10 seconds may be selected at will and it means that an authorized participant intending to enter into an encoded connection must wait for approximately 10 seconds from the moment of switching on his coding pulse generator until he is able to gain access. This time interval may be made longer or shorter as desired.

The date/time store 1 incorporates an electronic clock. As shown in FIG. 2b, a crystal oscillator 13, is connected to a first frequency divider 12 which is connected to a second frequency divider 11. The crystal oscillator 13 delivers a timing frequency of for example 1 MHz corresponding to a timing cycle T _o of 1/μs to the input of the first frequecy divider 12. The timing frequency is initially reduced to a frequency having a timing cycle T in a first register 15 of the divider 12. The frequency having the timing cycle T is supplied through the conductor 7 to the individual stages of the date/time store 1, the coding pulse generator 5 and the secret code store 3 and functions as the timing cycle for the entire encoding system. In a second multi-stage register 14 having 18 binary stages serially connected to the first register 15 and forming part of the first divider 12, the timing cycle T is further reduced to a timing cycle T _BL having a frequency of approximately 4 Hz corresponding to a periodicity of one-fourth sec. This frequency is supplied through a conductor 149 to the second frequency divider 11 where it is first reduced to 1 Hz in a two-stage divider unit 22. The timing signal T _BG at the output of the unit 22 therefore has a periodicity of 1 second. The logic circuits of the clock are adapted to produce conventional date/time data such as seconds (sec), minutes, hours, days (T), months and years and are driven by the aforementioned one-second timing signal T _BG . The date/time data are encoded in binary form, four binary digits being provided for each number. Quarter seconds are provided in addition to whole seconds in the seconds data output, two additional binary digits being sufficient to this end. A logic system, not shown, conventionally employed for electronic clocks, ensures that the appropriate carry-overs from seconds to minutes etc., are provided. The electronic clock includes a multi-stage store unit 26, part of which forms the subscriber's number store 2 having 12 stages for storing a subscriber's number in H (hundreds), Z (tens) and E (ones) encoded in binary form and other stages required for storing the date/time data.

The entire coding system operates with binary encoded signals as do the two stores 1 and 2. In the interests of reducing the number of conductors required the entire data from the stores 1 and 2 are supplied to the modulo-2-mixer 18 in series and not in parallel. This requires a kind of parallel-series conversion of the data contained in the units 26 and 22. The conversion is provided by a date/time shift register 19 which may be driven by pulses on a shift line 20, and which has as many stages as the two units 26 and 22. The data in each binary stage of the units 26 and 22 is supplied to a corresponding stage in the date/time shift register 19. Data in the individual binary stages of the units 26 abd 22 are transferred into the binary stages of the date/time shift register 19 after each pulse is transferred from the last stage of the register 14 to the first stage of the unit 22, that is to say every one-fourth second. During this one-fourth second the data in the units 26 and 22 is constant and the data in the date/time shift register 19 is shifted by pulses having a timing cycle T applied to conductor 20 from the conductor 7, the shifted data being applied to a conductor 25 which is connected to a modulo-2 mixer 21. Since the ratio of the two timing periods T _BL : T is approximately 1:250 000 and the number of stages in the date/time shift register 19 is 60, (10 stages each for seconds, 8 stages each for minutes, hour, day, month, year and 12 stages for number data plus 2 stages for the carry-over from the step-down part 22), it follows that the data in the date/time shift register 19 is supplied in unchanged form to the modulo-2 mixer 21 at the rate of 250 000 : 60 every one-fourth seconds, that is to say approximately 4000 times. In a preferred embodiment the binary stages of the units 26 and 22 and the stages of the date/time shift register 19 and including the appropriate counter carry-over circuits are constructed in the form of integrated circuits thus dispensing with the relatively expensive cross connections between units 22 and 26 and the shift register 19.

In addition to driving the date/time shift register 19, the pulses applied to the shift line 20 also drive a shift register 16 having a feedback connection. The shift register 16 has 20 stages, the third stage being connected via a line 152 to a modulo-2 mixer 17 which applies to the input of the shift register 16 via line 153 the product obtained by mixing data on the line 152 with data on the line 151 connected to the output of the shift register 16. A shift register of this kind having n stages supplies a so-called pseudonoise-sequence (PN sequence) having a periodicity of approximately 1 million timing pulses. It is a characteristic property of the PN sequence that it is practically identical to a statistical pulse sequence, with the exception of the overall periodicity. The PN sequence produced by the shift register 16 at its output 151 is supplied to the modulo-2 mixer 21 where it is mixed with the output from the shift register 19. The output signal of the modulo-2 mixer 21 provides a supplementary code which is supplied via the conductor 154 to the modulo-2 mixer 18 (FIG. 1). The periodicity of the PN sequence of the shift register 16 amounts to approximately 1 second but the contents of the date/time shift register 19 changes once every one-fourth seconds, i.e., the contents of the register in the divider 11 changes three times during one cycle of the PN sequence and will change at the beginning of the next period of the PN sequence.

The register 14 and the shift register 16 are both driven by the same timing signals having a timing cycle T. Since a n-stage shift register has a recirculation period of 2 ⁿ - 1 cycles and a n-stage binary register used as a frequency divider has 2 ⁿ cycles per period, it is necessary, in order to maintain synchronism, for the operation of the shift register 16 to be interrupted once during every period.

In addition to its function as a divider, it is possible for the register 14 to be used to provide timing pulses having different periodicities. As will be explained below, such timing pulses are utilised for synchronisation between transmitting and receiving stations. Timing pulses T _B , T _W and T _BL of such different periodicity may be obtained from the different stages of the register 14 and timing pulses T _BG from the last stage of the unit 22. If two stages for obtaining such timing pulses are spaced by Z binary stages, the corresponding timing cycles will be differentiated by the factor 2 ^Z . Accordingly, the periodicity of the timing pulses T _BG is four times as large as that of the timing pulses T _BL , the periodicity of the timing pulses T _BL being four times as large as that of the timing pulses T _W , the periodicity of the timing pulses T _W being eight times as large as that of the timing pulses T _B and the periodicity of the timing pulses T _B being eight times as large as that of the timing pulses T _Q . These different timing pulses form pulse trains which are ideally suited for synchronisation.

For all applications in which it is possible to dispense with such pulse trains it is also possible to dispense with the binary register 14 in which case the shift register 16 may be connected as the first frequency divider between the crystal oscillator 13 and the input 149 to the second frequency divider 11.

Since message pulses encoded at the transmitter station with a predetermined coding pulse sequence can be correctly received only if the appropriate encoded data is decoded at the receiving station with the same coding pulse sequence, as already mentioned, it follows that precise synchronisation between transmitter and receiver is essential. Since the coding pulse sequence depends on the date and time, such synchronisation is based in principle on the fact that clocks at the transmitter and receiver stations are synchronised, making due allowance for transmission transit time. The synchronising stage 6 shown in FIG. 1 comprises a time-comparison means 61, an OR network 63 and a time difference store 62. The date/time store 1 is preceded by time-correcting means 4, the input of which is connected to the output of the OR network 63. The time difference between the received signal fed into the time comparison means through the conductor 132, and the signal produced by the coding pulse generator 5 on conductor 82, or the signal produced by the receiver's own date/time store applied on line 128 is measured in the time comparison means 61 which is connected through a switch 23 to the coding pulse generator 5 or to the date/time store 1. This is possible because the coding pulse routine depends on the clocktime. Timing comparison may be performed on the basis of timing pulses incorporated in the reception signal or by correlation of the reception signal with the coding pulse routine. The time difference thus obtained may be utilised for resetting the receiver's own clock from the time comparison means 61 through the conductor 220, the OR network 63, the conductor 129 and the time correction means 4. The measured time difference may also be supplied through the conductor 131 to the time difference store 62 and stored therein so that after the received message has been decoded with the receiver's clock time synchronised with the transmitter's clock time by the value stored in store 62, this value may be cancelled and the time correction means 4 reset into its original state.

FIG. 3 is a basic example of the synchronisation between transmitting and receiving stations utilising synchronising pulse trains of different periodicity or frequency which are incorporated into the actual message pulses. In the description hereinbelow reference will be made to the valency of the pulses, valency in this connection being proportional to the periodicity and being indicated in the illustration by the line height of the individual pulses. As shown by line a, representing pulses received by the receiver, the actual message pulses N of periodicity T _B have the lowest valency, the so-called word pulses W _I of periodicity T _W having the next higher valency, one word pulse being associated with every four data pulses. The so-called block pulses BL _I of periodicity T _BL have the next higher valency and the so-called block group pulses BG _I of periodicity T _BG having the highest valency. One block pulse is associated with every four word pulses and one block group pulse is associated with every four block pulses. Line b shows the timing pulses produced internally by the receiver. The time difference between the received signal and the internally generated signal is Δ T. The following steps must be taken for clock synchronisation at the receiving station: first, the timing pulses of the lowest valency, that is to say the message pulses N, are synchronised. To this end the internally produced timing signal is displaced by a fraction of the periodicity T _B , namely by the difference Δ T _B . This ensures that the receiver clock pulses are moved to the position shown at line c. This is followed by correction of the word pulse position from line c to line d, the internally produced signal being displaced by 3 message pulse lengths. Accordingly, Δ T _W = 0. Next, the difference Δ T _BL between the block pulses is corrected by a shift of 3 word pulse lengths. Accordingly, line e is reached this being followed by correction of the difference Δ T _BG of the block group pulses by a shift of 3 block pulse lengths T _BL . The pulse train of line f, showing the corrected internal clock pulse train position, will then be synchronised with respect to time with the pulse train of the received signal shown at line a. Resetting the clock at the receiving station may be performed by additional pulses which are fed into the binary register 14 (FIG. 2) at the appropriate stages. It is of course possible to identify the different timing pulses by their different durations instead of by their different amplitudes.

Another example for obtaining synchronisation between the transmitting and receiving stations by means of synchronising pulse trains is illustrated in FIG. 4. Line a shows the timing pulse train of the crystal oscillator 13 (FIG. 2) having aperiodicity T _o , line b shows the timing pulse train of the coding pulse generator having a periodicity T. Line c shows the so-called data bit timing pulse train of periodicity T _Q and line d shows the data timing pulse train having a periodicity T _B . The period T _B corresponds to the bit length of an actual message pulse. Line e shows a brief sequence of message pulses comprising the binary digits 101. A reduction in the time scale is shown in line f in order that a larger number of message pulses may be displayed. The signal pulse train shown in this line is built up as follows: sets of 6 message pulses are disposed between every two word pulse W _I (shown in line g), for example the message pulses 101110 for the first word on the left, for the second word 001011, for the third word 100010, for the fourth word 010111 and so on. Data relating to a block pulse is positioned at one bit length before each word pulse W _I . The block pulse data shown in line f is also shown at line h, the correspondance being indicated by arrows. Prior to the first word on the left, the block pulse data is equal to 1, prior to the second word it is also equal to 1, in front of the third word it is 0, and in front of the fourth word it is O. The block pulse sequence (line h) is then repeated periodically, vis., 11001100 and so on. The block limits may be defined as shown at line i by means of such periodic data, namely by the change of block pulse data from 00 to 11. Finally line j shows the block group pulses BG _I . In the event of time deviations resetting of the receiver clock is performed by the method described above with reference to FIG. 3.

It should be noted that in general the periodicity of the synchronising pulses having the greatest valency in the examples shown in FIG. 3 and FIG. 4, that is to say T _BG , must be greater than twice the maximum deviation to be expected between the transmitter and receiver clocks. When the transmitter and receiver clocks are not synchronised each receiver clock pulse will be located between two transmitter clock pulses so that the interval between one transmitter clock pulse and the receiver clock pulse is shorter and the interval between the other transmitter clock pulse and the receiver clock pulse is longer than the periodicity of the aforementioned pulses having the greatest valency. Since, as already mentioned earlier, this periodicity is longer than twice the maximum expected clock deviation, a timing pulse on the receiver side must always overlap that timing pulse of the two adjacent transmitter side timing pulses relative to which the interval is shortest. Given the running accuracy of crystal-controlled clocks attainable at the present time -- maximum deviation per day 0.1 second -- it may be assumed that clock deviations will not exceed ± 5 seconds.

The synchronising methods described hereinbefore suffer from the disadvantage that at least the clock deviation time will be required for correcting the clock differences. Methods will now be described by means of which time difference may be corrected in a time which is substantially shorter than that time difference.

A first such method is illustrated in FIG. 5 in which the actual message pulses N are interposed between the periodic word pulses W _I as shown on line a. A block pulse bit is inserted in front of each word pulse W _I in a similar manner to that shown at line f of FIG. 4. In contrast with the example illustrated in FIG. 4, the block pulses are not only so shaped and positioned in time that they enable the block limits and block group limits to be detected but they also contain data. The appropriate binary representations 0 or 1 for the block pulses are shown in line b. Every 16 block pulses form a block, the block limits being marked by a sequence of four 0's and four 1's, the transition between the last `O ` and the first `1` representing a block pulse BL _I shown at line c by broken lines. As may be seen by reference to line b, the data within one block comprises three sequences of six binary symbols. Each of these sequences corresponds to a decimal number with two digits after the decimal point: the sequence 011001, appearing three times in the left half of line b corresponds to the number 6 1/4, and the sequence 011010 shown in the right-hand half corresponds to the number 6 1/2. Each number in a sequence is the clock time expressed in seconds and quarter seconds, the latter being the duration in which the supplementary date/time code is supplied via the modulo-2 mixers 21 and 18 to the coding pulse generator 5.

As mentioned in the description relating to FIG. 2b it follows that a new time value, namely the sequence of block pulses illustrated in line b, will be transmitted three times once every quarter second. The triple transmission ensures reliability against disturbances. The block time T _BL -- line a -- is also equal to one-fourth second. The reason for this is that normally a delay of one-fourth seconds is just tolerable and has no disturbing effects -- for example in a telephone conversation. However, a delay period of 1 second would certainly be disturbing in a telephone conversation, whilst 50 ms is unnecessarily short. A quarter second may be regarded as a "manipulating time" which is just acceptable. At the receiver it is merely necessary to detect the block limits and to compare the seconds value of the received signal with the seconds value of the receiver's own clock and then correct the clock. Correction may be performed on those stages of the storage unit 26 or register 19 storing the binary representation of seconds practically without any delay and directly. A time deviation of, for example, 5 seconds may be easily corrected within a quarter second.

FIG. 6 shows a variation in the method described with reference to FIG. 5 in which the block limits are not marked by a predetermined sequence of block pulses but by a representation of the clock time itself. In FIG. 6 the clock time in seconds is repeated three times withine one block T _BL . Block pulses are inserted in front of the periodic word pulses (not shown) in the same way as in FIGS. 4 and 5. The block length T _BL is once again one-fourth second so that a two-digit binary indication after the decimal point is sufficient. The block limits are defined by the third clock time in one block being transmitted in the reverse sequence to the other two and in inverted form. That is to say the first digit 0 of the third clock time 7 1/4, is inverted to 1 and placed as the last digit. Since the first clock time of the second sequence of three clock times in the second block length T _BL is normally represented, the detection of the inverted and reverse representation of the last clock time in the first sequence defines the end of one block and the beginning of the next.

Time comparison means 61 of the synchronising stage 6 in FIG. 1 will now be described with reference to FIG. 7. The means shown is suitable for detecting the block limits in the train of pulses described in FIG. 6 and comprises three shift registers 30, 31 and 32, three comparators 27, 28 and 29, one inverter 39 and one inverting AND network 38. The signal on the conductor 132 is applied to the three six stage shift registers 30, 31 and 32 during a shift cycle T _L corresponding to the word pulse cycle T _W (FIG. 3) -- the switches 35 and 36 and 37 being in the illustrated position and the switch 34 being closed. After each timing pulse TL the switches 35, 36 and 37 are switched to their other positions, the switch 33 closed and the switch 34 opened, for the duration of six timing pulses of a high-speed shift cycle T _S which is at least six times as fast as the shift cycle T _L . The data contained in each shift register is then recirculated once during the shift cycle T _S and the contents of each register will then once again be at the original locations. This recirculation proceeds prior to arrival of the next timing pulse T _L . During recirculation the contents of the shift register 30 are compared with the contents of the shift register 31 in the comparator 27, the contents of the shift register 30 and the contents of the shift register 32, inverted by means of the inverter 39, are compared in the comparator 29 and the contents of the shift register 31 and the inverted contents of the shift register 32 are compared in the comparator 28. The shift direction in the shift register 32 is reversed during the shifting cycle T _S since this shift register stores the reversed sequence of the third number in the group of numbers between block pulses as shown in FIG. 6, while the inverter 39 inverts the data. If a disparity is detected in one of the three comparators during recirculation and comparison the binary symbol 0 will appear at the output of the comparator and the binary symbol 1 will appear on the line 40 of the inverting AND network 38. The 1 insures that the entire procedure is repeated on the next timing pulse T _L , until during one recirculation of the data in the shift registers all outputs of the comparators remain at 1 so that an 0 representing the block limit appears on line 40. Detection of the block limit is necessary to enable the individual bits of the number data to be allocated their correct digit values. The number of shift timing pulses T _L required for detecting the block limit and representing the time difference between the transmitter and receiver station block limits, expressed as the number of words (timing cycle T _W ) may be stored in a counter. To this end a switch 134 is provided which is closed by the first shift cycle T _L and is opened when the binary symbol 0 appears on the line 40. The receiver station clock is corrected in accordance with the method described with reference to FIG. 3 by the number of shift timing pulses found in the aforementioned counter.

FIG. 8 shows a second form of time comparison means 61 (FIG. 1) in which the time difference between transmitter and receiver station clocks is obtained by so-called pulse templates. In FIG. 8, a four-stage shift register 400, having its output connected to a modulo-2 mixer 41 is used to generate PN pulse templates each comprising 15 bits. Each of the individual bits of the pulse templates are placed in front of a word pulse shown in the examples of FIGS. 4 to 6. Within any one block the appropriate pulse template will be transmitted three times. It is known that a pulse template of 15 bits when correlated with the same pulse template in different phases will provide the correlation value -- 1 in 14-phase positions and the correlation value +15 in the fifteenth phase position. It is therefore well suited for determining the relative phase between the transmitting and receiving stations. The length of the pulse template therefore also corresponds to the block length T _BL . The individual pulse template bits which occur at the same frequency as the word pulses pass from the conductor 132 of the receiver into a 15 stage shift register 42 and are fed thereto at a shift cycle T _L which corresponds to the word pulse period T _W . A recirculation connection of the shift register 42 is opened by a switch 43 during the application to the register 42 of the pulse template. Between every two timing pulses T _L and with the switch 43 closed one recirculation is performed at the timing frequency T _S . The contents of the shift register 400 are shifted at the same timing frequency T _S . The pulses of the pulse templates on the one hand and the recirculated data in the shift register 42 on the other hand are therefore supplied in time synchronism to a correlator 44. The pulse templates are of course produced at the transmitter station by an identical pulse template generator (shift register and modulo-2 mixer). In the event of phase disparity between the data stored in the shift register 42 and the data produced by the pulse template generator, the correlator will detect the correlation value - 1. If this is the case, the switch 43 is opened and a new shift timing pulse T _L shifts each bit of the data in the shift register 42 one stage. The switch 43 is closed again and the data is recirculated once at the timing frequency T _S and the correlation value is once again defined by the correlation 44. The number of timing pulses T _L required for the correlator 44 to define the maximum correlation value is determined in the same way as described with reference to the example illustrated in FIG. 7. The synchronisation process is completed when the maximum correlation value appears. This method is suitable only for correcting time differences which are shorter than the block length. It is of course not necessary for the maximum correlation value to be equal to its peak value, it must merely exceed a certain threshold value (for example the threshold value 10 for a correlation value 15) in order to effect synchronisation.

FIG. 9 illustrates a pulse train which can be applied to the apparatus illustrated in FIG. 8 to determine the difference between transmitting and receiving station clocks where the time difference is longer than a block length. FIG. 9 shows a sequence of block pulse bits which are incorporated in the transmitted message in front of each word pulse in the manner already repeatedly described hereinbefore. In contrast to FIG. 8, the individual blocks having a block period T _BL consist not only of a pulse template IS but in addition include seconds data, represented by 6 1/4, 6 1/2, 6 3/4 and so on. In this case the block length T _BL is one-fourth second. The apparatus required for defining the difference between transmitter and receiver station clocks is identical to that illustrated in FIG. 8. The block limits are determined in the manner described with reference to FIG. 8. The methods for correcting the time indications are described hereinbelow.

FIG. 10 also shows a pulse train which may be applied to apparatus similar to that shown in FIG. 8 to determine the difference between transmitting and receiving station clocks to compensate for differences in clock times which are substantially greater than the block length T _BL . As may be seen by reference to FIG. 10, three different pulse templates IS ₁ , IS ₂ and IS ₃ are successively transmitted in a constantly repeating cycle. Together the three pulse templates IS ₁ , IS ₂ and IS ₃ form a block group T _BG .

FIG. 11 shows apparatus for defining the clock time difference by means of the pulse template groups illustrated in FIG. 10, the apparatus comprising three sets of apparatus as illustrated in FIG. 8, one set for each pulse template, i.e. a separate shift register 400, having its output connected to a modulo-2 mixer 41 and functioning as pulse template generator, a separate correlator 44, and a separate shift register 46, 47 or 48, each register being driven by a low-speed or high-speed shift cycle T _L or T _S . Each of the shift registers 46, 47 and 48 has a number of stages corresponding to the number of bits in one pulse template and each receives one of the three pulse templates. The apparatus functions in a similar manner to that of the apparatus illustrated in FIG. 8, that is to say the contents of the shift registers 46, 47 and 48 are compared with the associated pulse template in the associated correlator. The clocktime difference is determined when the first maximum correlation value occurs in one of the three correlators. The clocktime difference is therefore determined in a period of time which does not exceed the duration of one of the three pulse templates.

FIG. 12 shows a further form of apparatus for providing synchronisation between transmitting and receiving stations. This kind of synchronisation may be described as correlation synchronisation and its principle has been disclosed in the Swiss Patent Specification No. 422 047. A pseudo-statistic pulse signal contained in the transmitted message signal is utilised for synchronisation, the pulse signal being completely defined by date and time and may take the following form:

1. it may be the coding pulse routine itself. In this case synchronisation of the receiver is obtained in transmitting intervals, that is to say when the coding pulse routine is not "covered" by clear language text or it is obtained by means of a clear language detector.

2. it may be a pseudo-statistical pulse signal, derived from a secret code and being generated by the coding pulse generator. This pulse signal may be transmitted either over a separate message channel or, as described above, may be transmitted in the form of timing pulses incorporated in the message signal.

3. it may be a non-secret but date and clocktime-dependent pseudo-statistical pulse signal.

The first two methods have the advantage that the pseudo-statistical pulse signal also depends on a secret code and access to synchronism is made very difficult for unauthorised parties.

The apparatus illustrated in FIG. 12 differs from the apparatus described above by the presence of a shift register 77 for storing the pseudo-statistical pulse signal received over the conductor 148' and by a shift register 80 for storing the pseudo-statistical pulse signal generated by its own coding pulse generator 5. Both shift registers are connected to a correlator 76 for comparing the store contents of both shift registers.

To explain the method of operation of this apparatus it may be assumed that the pseudo-statistical pulse signal is formed either by the coding pulse routine or by an additionally generated programme of the coding pulse generator 5. Furthermore it may be assumed that the pseudo-statistical pulse programme prior to its arrival on the conductor 132 has already been freed of the actual message pulses. A numerical example will now be given to provide a better understanding of the method of operation: the pseudo-statistical pulse signal received on the conductor 148' and having a pulse period duration of, for example, ms, is fed into the shift register 77. The pseudo-statistical pulse signal generated by its own coding pulse generator 5 is fed into the shift register 80. Since the transmitting and receiving station clocks may deviate initially from each other by, for example a few seconds, it is necessary for the time difference to be determined by a scanning operation which should be as rapid as possible. The signal arrives at a constant rate and cannot be accelerated because of the capacity of the transmission channel but generation of the pseudo-statistical pulse signal of the receiving means may be accelerated. The basic progress for synchronising the transmitting and receiving station clocks when a connection is established and when the clocks may deviate from each other by a few seconds is to set back the receiving station clock by at least the entire clock time difference to be expected. The receiving station clock then lags behind the transmitting station clock. The clock and the coding pulse generator at the receiving station are then allowed to run at an increased speed so that after a period of time the receiving station clock will be synchronised with the transmitting station clock.

The scanning operation is as follows: it will be assumed that the received pseudo-statistical signal has occupied all stages of the receiving station's shift register 77. If the register has, for example, 64 stages, the time taken to fill all those stages will be 0.64 seconds at the selected periodicity of the shift pulses. Compared with the desirable manipulation time of approximately one-fourth seconds, this time is too long, but can easily be reduced by reducing the number of stages in the shift register 77, for example to 32 stages, or by increasing the timing frequency of the pseudo-statistical pulse signal. After the receiving station's clock has been set back by the expected clocktime difference, a switch disposed between the crystal oscillator 13 and the frequency divider 12 is moved to the position illustrated in FIG. 12 so that the timing pulses of the crystal oscillator are coupled to the pulse generator 5 via line 7 and to a stage 165 of the register 14 which is the eighth stage of the register counting from the input connection coupled to the crystal oscillator 13. Accordingly, the clock and the coding pulse generator 5 will operate 2 ⁸ = 256 times faster. In consequence the coding pulse generator routine normally delivering pulses at a periodicity of 10 ms on line 82 also operates 256 times faster so that the pulse period is reduced to approximately 40 μs. The shift cycle for the two shift registers 77 and 80 also has a timing period of 40 μs since they are connected via switch 72 to stage 163 of the register 14. The oscillator 13 supplies a timing frequency of 1.64 MHz. In the illustrated position of the switch 71 this passes directly to the eighth stage of the register 14 and before reaching stage 163 passes 6 further stages so that the input frequency is stepped down 2 ⁶ = 64 times, providing a timing frequency of 1.64 MHz:/64 ≅ 25 000 Hz corresponding to a timing cycle of approximately 40 μs. When the switch 134 is in the illustrated position, the 40 μs shift pulses only reach the shift register 80 and not the shift register 77. Between every two shift cycles for the shift register 80, that is to say within 40 μs, the contents of the shift registers 77 and 80 are correlated with each other. This correlation is obtained by the entire shift register contents being circulated once at a high speed cycle of approximately 0.6 μs through the closed switches 78 and 79. The shift registers have 64 shift register stages, so that one complete circulation requires 64 timing steps that must be performed within 40 μs, giving the timing period of 0.6 μs. This timing period corresponds to the oscillator frequency of 1.64 MHz. Circulation is performed by moving switch 72 to connect the conductor 164 via switch 134 to the shift register 77, the switches 78 and 79 being closed and the switch 54 being opened. Sequential correlation of the contents of registers 77 and 80 is effected by a single correlator 76. The correlator 76 compares the individual corresponding bits of the contents of the shift registers 77 and 80 during the 64 correlation steps, producing a signal representing a value of +1 in the case of coincidence and a signal representing a value of - 1 in the case of non-coincidence and arithmetically counting the 64 values to produce a correlation value. In the event of non-coincidence between the clock-times the correlation value will be very small and on average fluctuate around zero. If the data in the shift registers 77 and 80 is precisely in phase, the correlation value will be 64 in the ideal case when there are no disturbances on the transmission line connecting the transmitter to the receiver. In practice, correspondence between the timing of the clocks is considered as having been achieved when a threshold value, for example between 50 and 60, is exceeded. The magnitude of the threshold value is selected so that response to random interference pulses is as rare as possible whilst allowing the apparatus to function in the presence of such interference. If the selected threshold value is not reached during determination of the first correlation value, a new 40 μ pulse of the pseudo-statistical pulse routine delivered by the coding pulse generator is fed into the shift register 80 while the switches 72, 134, 78 and 79 are reset to the position shown. Thereafter, a further correlation value is obtained by a single circulation with the new data fed into register 80 as described above. This procedure is continued until the threshold correlation value is exceeded whereupon a pulse from the correlator 76 triggers the switch 71 to its normal position connecting the oscillator 13 to the first stage of the register 14 so that the clock is then driven at its normal rate. Accordingly, the timing frequency during circulation which is derived from stage 163 of the register 14 and amounts to 1/256 times the normal timing period applied to stage 165 is decreased from 40 μs to approximately the normal timing period of 10 ms. The switch 134 will then remain in the position at which the 10 ms pulses are supplied to the shift register 77 which accepts the received pulses at the normal timing frequency.

During the synchronising phase the time difference store 62 counts the number of 40 μs timing pulses which occur between the beginning of the clock resetting operation and the time at which the correlation value is reached. This number of timing pulses represents deviation between the transmitting and receiving station clocks in terms of the pulse length of the pseudo-static pulse signal. The store value in the clocktime difference store 62 may be utilised for resetting the receiving station's clock to its original operating value after transmission ceases or the connection between the transmitting and receiving stations is discontinued.

Should it be found necessary it is possible after establishing a connection between a transmitting and a receiving station for synchronisation to be continuously checked by the correlator 67 at a normal timing cycles since the inputs to the correlator are connected to the received signal and to the output of the coding pulse generator. The time for scanning a clock difference of 5 seconds is exceptionally short. 5 seconds contain 500 of the 10 ms long pulses of the pseudo-static pulse sequence. In high-speed operation of the synchronising phase these 500 pulses require 500 times 40 μs corresponding to 20 ms. The entire range of clock deviation of 5 seconds is therefore scanned within 20 ms. Clock synchronisation may be obtained within a one-fourth second even if the clock deviation is 1 minute, such synchronisation proceeding with a high degree of reliability because of the extremely favourable correlation method.

The times at which operations in the synchronisation process described are carried out are graphically illustrated in FIG. 13. The time t is plotted on the X axis, the time setting t* of the receiving station's own clock being plotted along the Y-axis. At time t ₁ the clock is reset by the maximum deviation, in the previous example 5 seconds, to the clock position T*1. The clock is then driven at high speed twice the possible clock deviation 2ΔT _max to the point T* ₂ .

In FIG. 11 it is assumed that for certain reasons, for example severe interference on the transmission channel, synchronism was not established during this time between t ₁ and t ₂ . At time t ₂ the clock is reset by 2ΔT _max to T* ₃ whereupon the correlation scanning procedure is once again performed at high speed. At the point T* ₄ (time t ₃ ) the correlator responds and switches the receiving station's own clock to normal speed. The clocktime difference T as measured and retained in the store 62 is also plotted on the graph. At the time T* ₅ (time t ₄ ) transmission is discontinued and the store value ΔT in the time difference store 62 is utilised to reset the receiving station's clock to the original normal operation point T*hd 6. Fundamentally large clocktime differences must be compensated for only when the connection between a transmitting and receiving station is first established. As soon as the clock at the receiving station has once been compensated, it is possible for the aforementioned clock setting to be retained in special stores as described below so that when a new connection is established it is possible to confine the duration of the scanning operation to only 0.1 or 0.5 seconds since a crystal of 10 ^{- 6} seconds accuracy has a deviation of 0.5 seconds only after 5 days. The time for achieving synchronism is exceptionally short, for example 10 to 20 ms given a scanning time in the synchronising phase of only 0.5 seconds.

For pseudo-static pulse signals having a bit length of 10 ms, it is possible for clock deviations of ±20 seconds to be easily synchronised within approximately one-quarter second.

A deviation of this kind corresponds approximately to a deviation which is not exceeded within an entire year by a crystal-controlled electronic clock having an accuracy of 10 ^{- 6} . It is therefore possible for such a clock to be operated for a year without the need for resetting it. It is therefore advantageous for the clock to be operated from a battery, even when the encoding apparatus is not being used.

As already mentioned, the coding pulse generators utilised for the coding apparatus are of the kind having a limited storage time. This property of limited storage time is of special significance for the encoding apparatus since it is only this property which permits realisation of the kind of synchronisation described with reference to FIGS. 12 and 13. Resetting of the clock should be accompanied by resetting of the coding pulse generator so that when in the reset position it delivers the correct coding pulse routine corresponding to the reset clock time. Resetting of the code pulse generator however is not possible and in consequence it is necessary for the coding pulse generator to deliver the previously stored data in a sufficiently short time after resetting of the clock.

In order to avoid the need for extremely short storage times in the coding pulse generator 5 when the clock is synchronised, the clock can be stopped instead of being reset. The scanning operation will then proceed as illustrated in the graph of FIG. 14. At time t ₁ the clock is stopped for a period of time corresponding to the maximum expected time deviation ΔT _max . This is followed at time t ₂ by scanning at increased speed as already described with reference to FIG. 13. If synchronisation is not established in the scanning range ΔT*, the clock is stopped by an amount 2ΔT _max at time t ₃ until time t ₄ is reached and synchronisation is obtained at time t ₅ . With this method it is possible for the storage time of the coding pulse generator 5 to extend over several minutes or more, synchronisation however takes place in fractions of a second.

FIG. 15 shows a correlation synchronisation apparatus having certain similarities with that illustrated in FIG. 12 but whose clock cannot be reset. The synchronisation apparatus includes three shift registers 42, 620 and 610. The shift register 42 is connected by means of a switch 54 to the line 132 at the receiving station and the shift registers 620 and 610 are connected by a switch 55 to the coding pulse generator output 82. The shift registers 42, 620 and 610 are also connected to a correlator 59. The pseudo-statistical pulse signal (for example having a bit length of 10 ms) received on the conductor 132, is stored in the shift register 42 and the pseudo-statistical pulse routine produced by the receiving station's own coding pulse generator 5 is stored in the shift registers 620 and 610. The stored contents of the two shift registers 42 and 610 are once again circulated and scanned by the correlator 59 in the above described manner to determine the maximum correspondence, the switches 57 and 58 being closed. The time interval corresponding to the maximum expected difference between the transmitting and receiving clocks (that is to say for example 5 seconds) is stored in the shift register 620. The receiving station's clock is advanced by half the expected clocktime difference, i.e. 2.5 seconds, so that it is possible to obtain a pulse signal from the shift register 620 corresponding to a clock time which leads by 2.5 seconds. In the middle of the shift register 620, at stage S, it would be possible to obtain a pulse routine which corresponds to the "normal" clocktime and at the output of the shift register 620 it is possible to obtain a pulse routine corresponding to a clocktime which lags by 2.5 seconds behind the normal time. The shift register 620 may be regarded as a delay line or "time potentiometer," capable of delivering pulse signals at different times within the maximum expected clocktime difference. Since the receiving station's own clock is advanced by 2.5 seconds for synchronisation and thereby precedes the received signal, and since time comparison proceeds at the output of the delay line shift register 620, that section of the pseudo-statistical pulse signal contained in the shift register 42 will be contained somewhere within the delay line shift register 620. The illustrated circuit enables this fact to be established within a very short period of time and at a very high timing frequency although the clock continues to operate at its normal speed. The synchronising operation is as follows:

It is assumed that the pulse length of the pseudo-statistical pulse signal on the line 132 and that of the coding pulse generator on the line 82 amlunts to 10 ms. It is further assumed that the shift registers 42 and 610 are each constructed with 32 stages and the shift register 620 is constructed with 480 stages. The stored contents of the 512 stages of the shift registers 610 and 620 require a time of 512 times 10 ms which approximately equals 5 seconds to be shifted out. It may now be assumed that all shift registers are filled with data of the pseudo-statistical pulse signal. The switches 55 and 54 remain open for the entire scanning operation but the switches 57 and 58 are closed when the switch 63 is opened and vice versa. Initially the data in the shift registers 42 and 610 is circulated once at the high speed T _L (switch 53 in the right-hand position) when the switches 57 and 58 are closed and the total correlation value of the shift register contents is defined by means of the correlator 59. The timing frequency of the timing cycle T _L may be 2 MHz, corresponding to a timing period of 0.5 μs. If the correlation value thus determined is less than a defined threshold value the switch 53 is briefly connected to the timing source T _M (switch 53 in the middle position), the frequency of the source being no greater than T _L /32, that is to say for example 62.5 kHz, corresponding to a timing period of 16 μs. When the switch 63 is closed, the contents of the shift register 610 and 620 are shifted through one stage at the aforementioned cycle T _M , thereupon the switch 53 switches back to the high frequency cycle T _L after which the correlation value between the contents of the shift register 42 and shift register 610 are once again measured. This procedure, namely alternate circulation and defining of the correlation value and shifting of the data in the shift registers 610 and 620 by one stage is continued until the correlation value exceeds a predetermined threshold value thus completing the synchronisation operation during which the 16 μs shift cycles of the timing source T _M are counted by a counter 49 in the time difference store 62.

The number of shifting steps required to synchronise the clocks at the transmitting and receiving stations is stored in the counter 49. The maximum for the entire scanning process involves 512 shifting steps, corresponding to the total number of stages in the shift registers 610 and 620. The maximum time required for this amounts to 512 times 16 μs, that is to say approximately 8.2 ms. The entire synchronisation of clocktime differences of up to 5 seconds may therefore be performed in 8.2 ms. Since this time of 8.2 ms is less than the pulse length of the pseudo-static signal of 10 ms it is possible for the switches 54 and 55 to remain open during one complete scanning cycle. The pseudo-statistical pulse signal on conductor 82 delivered by the pulse generator 5 may be produced either especially for synchronisation purposes and/or a separate coding pulse routine may be transferred additionally at the same bit rate to the shift registers or the pseudo-statistical pulse signal may be formed by the coding pulse routine. Since the coding pulse routine bits must be available for decoding at the receiving station at the correct time defined by the synchronisation operation, the data stored in the counter 49 of the time difference store 62 will also be used after synchronisation in order to call up the time corrected coding pulse bits from the shift register 620 so that decoding may be performed therewith. This is achieved by circulating the contents of the delay shift register 620 while the switch 55 is open and the switch 63 is closed and while the switch 53 is set to the T _M cycle and the switch 52 is closed, the number defined in the counter 49 being reset to zero and on reaching zero the bit present at that position being passed through an OR network 51 and an AND network 67 to the store position 69 in the form of the required coding pulse bit. The store position 69 is connected through the conductor 81 to the mixer 8 (FIG. 1). This bit corresponds with the time position, defined by means of the counter 49, which corresponds with the received signal. While the counter 49 counts backwards a second counter 50 counts forward so that the number thus defined is once again stored in the counter 50 after the counter 49 is reset. The switch 55 is closed after the required coding pulse bit is delivered and the new bit of the pseudo-statistical pulse sequence is fed into the shift registers. The clocktime difference number stored in the counter 50 is then used to deliver the "correct" bit at the cycle T _M (cycle period 16 μs). During transmission, the pulse routine obtained from position S in the middle of the delay shift register 620 is transmitted and corresponds to the normal clocktime. This system offers the advantage that neither the clock nor the coding pulse generator need be operated at a speed higher than normal and that it is not necessary for the receiving station's clock to be either advanced or retarded. However this system is generally more suitable for synchronising smaller clocktime differences.

Different logic circuits for the time correcting means 4 (FIG. 1) are illustrated in the following drawings. The logic circuits are coupled to the register 14 (FIG. 2) and together with preselected stages thereof form the time correcting means 4.

Referring now to FIG. 16, the period T of a timing signal at position P ₁ at the output of a state U ₁ of the register 14 (line a) is doubled in the next state U ₂ forming a pulse train of period T ₁ shown at line c which appears at the output of the aforementioned stage U ₂ or at the output of an OR gate 84 at position P ₃ . However an additional pulse or pulses may be inserted in the pulse train shown on line c by applying a signal E, line b to a first input of an AND gate 83 whose second input is connected to the output of stage U ₁ supplying the pulse train of period T. The output of the AND gate 83 is connected to a first input of OR gate 84 whose second input is connected to the output of stage U ₂ . The pulse train at the output of OR gate 84 at position P ₃ is fed to an AND gate 85 whose output is connected to stage U ₃ at the output of which the timing pulse train shown in line e will appear. A suppression pulse U (line d) may be applied to position P ₄ at the second input of the AND gate 85 to suppress one pulse of the timing pulse train shown in line c. The E pulses fed in at P ₂ therefore cause the clock to advance and the U pulses fed in at P ₄ result in retarding the clock.

FIG. 17 shows a multi-stage time correcting means 4 coupled to the register 14. The time correcting means as shown is however suitable only for advancing the clock in a manner explained with reference to the timing pulse diagrams illustrated at lines a to c of FIG. 16. Each pulse applied to an input n _Q is followed by an advance of the clock by one cycle of the output of the stage U ₁ . Each pulse applied to an input n _B is followed by an advance of the clock by a time corresponding to one cycle of the output of stage U ₃ and so on. A pulse applied at n _B results in a clock time advance which is four times as large as that produced by a pulse applied to the input n _Q because inputs n _Q and n _B are separated by two binary stages of the register 14. Furthermore, a pulse applied to an input n _W results in a clocktime advance which is 16-times as large as that produced by a pulse applied to the input n _Q and a pulse applied to n _BL results in a clocktime advance which is 64-times as large as that obtained at n _Q . It is therefore possible by applying a pulse to any one of the different inputs coupled via gates to different stages of the register 14 to obtain small, medium and long time advances in the shortest possible time. Block time advances of substantial magnitude may also be obtained in a short time by adopting this procedure. The required time advance may also be obtained from the time difference store 62 which contains binary step-down counting stages 88 to 94 and the stored time difference may be fed into the clock and into the register 14.

FIG 18 shows a simple synchronisation circuit which may with advantage be employed for telex transmission subject to relatively small deviations between the transmission and receiving station clocks. The coding pulse routine of the coding pulse generator 5 is applied through the conductor 81 to a delay line shift register 95, each stage corresponding to one data bit and the word length T _W corresponding to the length of a telex character. The shift register 95 provides outputs 96, 97, 98, 99 and 100 which are connected to individual stages of the register spaced one telex character apart. The procedure which accompanies synchronisation of the receiving station is such that at first the receiving station's clock and the coding pulse routine applied over conductor 81 is synchronised with the starting pulse of the received signal. If the clocktime deviation is small, in the order of 0.1 second, the relative phase of the coding pulse routines will represent a distance of no more than one or two complete teleprinter characters. Scanning the shift register 95 with a switch 101 to the left or right will rapidly define the position at which clear language text appears on the conductor 102. Synchronisation may be performed fully automatically by means of a clear language text detector. The clear language text detector may for example respond to letters or characters such as "E" or "space" which occur at a more than average rate thus actuating the switch 101 until clear text appears.

If the synchronising signal contains time data-for example seconds -- as in the signals illustrated in FIGS. 5, 6 and 9, it is possible for the receiving station's clock to be reset in the shortest possible time and at the correct digit position by addition or subtraction.

FIG. 19 shows part of a synchronising system employed for multiple subscriber stations. The time difference between the transmitting station's clock and the receiving station's clock, the time of which is stored in the store 1 (FIG. 1) or the coding pulses generated by generator 5 controlled thereby and the received phase difference between the signal on line 148 ¹ obtained from the time comparison means 61, may be stored in the time difference store 62 via the conductor 131. The detected clock deviation may be corrected by the time correcting means 4 through the conductor 220, the network 63 and the conductor 129. The stored time difference value may be utilised for resetting the clock to its original position after transmission has been completed (via conductor 220, network 63, conductor 129) and it may be stored in further time difference stores 106 or 107 or 108. Each of these additional stores is associated with a different subscriber station, for example store 106 is associated with station A, store 107 is associated with station B and store 108 is associated with station C. If communication is first established with station A, the detected clocktime difference value is stored in the store 106. When changing over to communicate with station B the aforementioned clocktime difference value remains stored in store 106 and the clocktime difference value with station B is detected and stored in store 107 and so on. If the time difference values for all stations of the network are detected and stored, repeated communication with all stations is possible without any fresh synchronisation by using the stored time difference values since each time the transmission station is connected to a subscriber station through a switch 105, an AND gate 109 and a conductor 111, the clocktime of the subscriber station will be modified by the stored value in the appropriate store 106, 107, 108, etc.

In this connection it should be mentioned that coding means of the kind heretofore described are also suitable for transmitting encoded data blocks. Each data block may contain 500 bits and these may be transmitted for example in a half second. Each data block is provided with an initial block character, for example 1111 and with a block number. This block number may be the time in seconds of the clock at the beginning of block transmission. It is of course essential for block lengths of one-half second for the time clock to provide signals representing one-fourth seconds to ensure that each new block is provided with a new time number. In data transmission technology it is common practice for blocks to be stored briefly at the transmitting station so that they can be re-transmitted on interrogation. Interrogation is obtained by means of the block number whereupon the stored block is re-transmitted but with a new block number or a new block number time.

FIG. 20 shows the manner in which different data batches, depending on the date-clocktime, can be transferred from the secret code store 3 to the modulo-2 mixer 18. The secret code data is stored in 10-digit shift registers 123, every 4 shift registers forming a shift register batch in which the 4 binary numbers disposed at the same level in the horizontal direction together form a binary encoded secret code decimal number. Each shift register batch therefore contains 10 secret code decimal numbers. The contents of each shift register 123 may be recirculated over a feedback conductor. The output of each shift register is coupled to a different stage 122 of a shift register in which data may be shifted to the right by pulses applied to a shift line 200. The secret code decimal number stored in the shift register batches and originally fed in at a predetermined initial position, may be shifted to positions in response to the date-clocktime numbers by means of pulses applied to the shift line 124. Accordingly, the secret code decimal numbers are retained but their position in the shift registers will be determined by the associated clocktime decimal number control being provided by the binary stages of a date-clocktime counter 26. The secret code decimal numbers in the shift register batch on the extreme right are shifted by 7 steps, those of the second shift register batch by 0 steps, those of the third shift register batch by 5 steps and those of the shift register batch on the extreme left by 2 steps, corresponding to the associated decimal numbers of the date-clocktime indication. The secret code combination used for encoding, transferred to the shift register stages 122 at any one time is unique and is determined by the date-clocktime.

Practically all the synchronisation methods and apparatus described above may be employed not only for compensating clocktime differences between transmitting and receiving stations but may also be used for the automatic compensation of signal transfer times. Signal transfer times are usually in the order of 10 to 100 ms but in some circumstances may be longer. The signal transfer time is included when measuring the difference in time between the clocks at the transmitting and receiving stations and is therefore automatically taken into account.

In the foregoing description and in the ensuring claims reference is made to continuously setting the coding pulse generator 5 by pulses generated by the clock so that the output pulses from the coding pulse generator are continually influenced by the clocktime. However the construction of the digital electronic clock as described with reference to FIG. 2 is such as to provide incremental changes of a one-fourth second and in consequence the term continuous change in relating to the setting of the coding pulse generator is taken to include within its meaning such incremental changes and furthermore at least one change in time during transmission of a message. For example if a short message is transmitted over 1 second then the clock provides at least two different clock times within that period.