Description:
The invention relates to an apparatus for producing tones of a preferably equal-tempered musical scale, the apparatus comprises a frequency converter an input of which is connected to the input of a divider chain to which the signal from an oscillator may be applied. Outputs of given dividers are connected to inputs of a gate circuit the output of which is connected to an output of the frequency converter. A lower tone of the octave is obtained at this output.
Such an apparatus is described in British Patent Specification No. 1,264,143. In this apparatus the outputs from the dividers required to compose the desired tones are applied to the inputs of a number of gate circuits equal to the number of tones. Thus, there appear at the outputs sequences of pulses in which the pulses are irregularly distributed, thereby producing a highly unpleasing sound, although the pitch is correct. To avoid this disadvantage a master oscillator having a comparatively high frequency is used, and the signals which appear at the outputs of the gate circuit are each applied to a series of dividers-by-two, the distribution of the pulses becoming more regular after each division by two, so that the output signal from the divider chain the pitch of which corresponds to the highest tone desired in the musical instrument has a pleasing sound.
In this specification the term "frequency" means "pulse recurrence frequency," i.e., the number of pulses per second. The sequence of the pulses need not consist of pulses which are strictly regular in time. The extent of the irregularity in time determines whether or not the resulting pulse train is perceived subjectively as an acceptable tone.
According to the invention, for each tone of the octave there is provided a frequency converter. The outputs of dividers connected to inputs of a gate circuit causes the appearance at the output of this gate circuit of a tone which has a frequency which is next lower than the frequency of the tone at the input of the divider chain. All the frequency converters being connected in series.
This provides the advantage that the frequency converters may take the form of separate units, with a consequent reduction in cost, because larger quantities of the standardized units may be manufactured and only one type need be kept in stock. Such a unit may, for example, be an integrated circuit. If in an embodiment according to the invention the output signal is lower than the input signal by a semitone of the identical-tempered scale, all the units are equal.
Although the dividers of a divider chain may be any suitable kind of dividers, for example, dividers-by-ten, it is of particular advantage to use a chain of dividers-by-two.
Thus, a frequency converter may be provided with a chain of dividers-by-two to which an input signal is applied. Each divider-by-two has an input and at least one output. A first output of each divider-by-two is connected to the input of a following divider-by-two, while at the outputs of the dividers-by-two there are produced trains of pulses having a mark-to-space ratio of substantially 1:1. The chain comprises groups of successive dividers-by-two the output pulse trains of which correspond to pulse trains of which the desired pulse train at the output of the frequency converter consists, and groups whose pulse trains which correspond to the output pulse trains do not form part thereof, each group consisting of at least one divider-by-two, according to the invention the input of the frequency converter is connected to the input of the first group of dividers-by-two and also to a first input of a first gate circuit of a chain of inverting gate circuits. The input of each of these gate circuits is connected to the output of a following one. The desired output signal appears at the output of the first gate circuit, while an output of each group of dividers-by-two is connected to the inputs of a following gate circuit. If the last group comprises only a single divider-by-two the output pulse train of which corresponds to a train present in the desired pulse train, the outputs of the last two groups are connected to the inputs of the last gate circuit, while the signals at the input of the divider chain and at the first input of the first gate circuit are inverted with respect to one another.
This provides the advantage that the signal connections between the dividers-by-two and between the dividers-by-two and the gate circuits and between the gate circuits do not cross one another, which appreciably facilitates manufacture of the unit in integrated-circuit form.
An additional advantage is provided in another embodiment of a frequency converter according to the invention in this embodiment a number of additional outputs which each are connected to an output of one of those dividers-by-two which, as the case may be after extension of the divider chain, produce musically satisfactory octave tones. This is due to the fact that part of the dividers-by-two are simultaneously used to produce satisfactory tones of the musical instrument.
Obviously the term "gate circuit" as used in this specification includes circuits which for some reason or other, for example for reasons of integrated-circuit technology, are divided into at least two separate gates, as the case may be with the inter-position of inverters.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which:
FIG. 1 shows a known circuit arrangement,
FIG. 2 shows a circuit arrangement according to the invention for a 12-tone scale,
FIGS. 3 and 4 show two frequency converters according to the invention for mean-tone intonation,
FIG. 5 shows a frequency converter according to the invention for an equal-tempered 12-tone scale,
FIG. 6 shows such a frequency converter including a divided gate circuit,
FIG. 7 shows an integrated circuit for a frequency converter as shown in FIG. 5 according to the "injection feed" method,
FIG. 8 shows an integrated circuit for a frequency converter as shown in FIG. 5 according to the "miniwatt" technology, and
FIGS. 9 and 10 show the pulse trains at the inputs and outputs of gates G7 and G6 of FIG. 5.
Referring now to FIG. 1, the signal from an oscillator G is applied to an inverter I a chain of dividers-by-two D1 to D11. The outputs of these dividers-by-two and the inverter I are connected to the input of those gate circuits A1 to A11 at the outputs of which the desired tones are produced. The outputs of the gate circuits A1 to A11 are each connected to a sequence of dividers-by-two C1 to C9 . . . B1 to B9 which serve to equalize the pulse intervals except those of the tone C, the pulse sequences of which are regular in any case. The output signals from these chains of dividers-by-two are applied to succeeding chains of dividers-by-two C10 to C15 . . . B10 to B15, respectively. The desired tones of the musical instruments are derived from the outputs of the latter divider chains. Obviously the numerous crossings which occur in the connections between the first chain of dividers-by-two D1 to D11 and the gate circuits A1 to A11 will give rise to difficulty in manufacture, because crossings are expensive both in printed circuits and in integrated circuits.
FIG. 2 shows a circuit arrangement according to the invention in which the signal from an oscillator G is applied to an input of a first frequency converter C which comprises a divider chain and at least one gate circuit. The outputs of the dividers required to compose a desired tone are connected to inputs of the gate circuit the output of which is connected to an output of the frequency converter at this output a tone is obtained which in the scale has a frequency next lower than the frequency of the tone applied to the input of the frequency converter. The output of this first frequency converter C is connected to the input of a second frequency converter B which also comprises a divider chain and at least one gate circuit. The output of this second frequency converter B in its turn is connected to the input of a third frequency converter BES, (Bes = B flat) and so forth. To produce a 12-tone scale twelve frequency converters are provided which all are connected in series.
These frequency converters may be designed for all the intervals of the various intonations, such, for example, as just intonation, mean-tone intonation and equal-tempered intonation for a 31 tone scale having a smallest interval equal to √ 2, and as a matter of fact also for a twelve-tone scale having a smallest interval equal to √ 2.
FIGS. 3 and 4 show circuit diagrams for frequency converters for a scale according to the mean-tone intonation, in which the intervals between the pairs of successive tones have the following ratios, the left-hand column showing the numbers according to the decimal system and the right-hand column showing the numbers according to the binary system.
Decimal binary (15 bits) B/C = 0.934 593 0.111 011 110 100 001 B flat/B = 0.957 023 0.111 101 010 000 000 A/B flat = 0.934 593 0.111 011 110 100 001 A flat/A = 0.957 023 0.111 101 010 000 000 G/A flat = 0.934 593 0.111 011 110 100 001 F sharp/G = 0.934 593 0.111 011 110 100 001 F/F sharp = 0.957 023 0.111 101 101 000 000 E/F = 0.934 593 0.111 011 110 100 001 E flat/E = 0.957 023 0.111 101 010 000 000 D/E flat = 0.934 593 0.111 011 110 100 001 C sharp/D = 0.934 593 0.111 011 110 100 001 C/C sharp = 0.957 023 0.111 101 010 000 000
If the A flat is replaced by the G sharp, the intervals will be:
G/A sharp = 0.934 593 0.111 011 110 100 001 G/G sharp = 0.957 023 0.111 101 010 000 000
As the above Table shows, in this intonation there are only two intervals, i.e., the interval 0.111 011 110 110 001 and the interval 0.111 101 010 000 000 in the binary system, so that the production of the tones according to the mean-tone intonation requires only two types of frequency converters.
FIG. 3 shows a possible design for the first type. The signal from an oscillator is applied to the input E of the frequency converter which comprises a chain of dividers-by-two d1 to d18 which each are provided with one input and a first and a second output. The first output of each of the dividers-by-two d1 to d17 is connected to the input of the next divider-by-two d2 to d18 respectively, while pulse trains having a mark-to-space ratio of substantially 1:1 appear at the outputs of the dividers-by-two. The chain comprises groups of successive dividers-by-two d1,d2,d3 ; d5,d 6,d 7,d8 ;d 10 ;d15 respectively whose pulse trains which correspond to the output pulse trains (the digits one) form part of the pulse train at the output of the frequency converter, and groups d4 ; d9 ; d11, d12, d13, d14 ; respectively whose pulse trains which correspond to the output pulse trains do not form part of the desired pulse chain at the output of the frequency converter (the digits zero). This signal is applied to the input of the first group of dividers-by-two d1 to d3 via an inverter stage I and also to a first input of a first inverting gate circuit G1. The first output of each divider-by-two of the divider chain d1 to d7 is connected to the input of the respective next divider-by-two d2 to d18. The second output of each of the dividers-by-two of the first group d1 to d3 is connected to an input of a second inverting gate circuit G2 the output of which is connected to a second input of the first inverting gate circuit G1. The second output of each of the dividers-by-two of the second group, which comprises a single divider d4, is connected to the input of a third inverting gate circuit G3 the output of which is connected to a fourth input of the second inverting gate circuit G2. The second outputs of the dividers-by-two of the next group d5 to d8 are all connected to an input of a fourth inverting gate circuit G4 the output of which is connected to a second input of the third inverting gate circuit G3. The second output of the next group, which comprises a single divider-by-two d9, is connected to a first input of a fifth inverting gate circuit G5 the output of which is connected to a fifth input of the fourth inverting gate circuit G4. The second output of the next group, which also comprises a single divider-by-two d10, is connected to a sixth input of a fifth inverting gate circuit G6 the output of which is connected to a second input of the fifth inverting gate circuit G5. The second outputs of the last two groups of dividers-by-two which comprise the dividers-by-two d11 to d4 and the single divider-by-two d15, respectively, are all connected to an input of a seventh inverting gate circuit G7 the output of which is connected to a second input of the sixth inverting gate circuit G6. Thus there is produced at the output of the first gate circuit G1 a tone the frequency of which is 0.934 593 times that of the input signal or, expressed in the binary system and assuming the input frequency to be 1.000 000 000 000 000, a tone having a frequency equal to 0.111 011 110 100 001 times that of the input signal.
FIG. 4 shows a frequency converter the frequency of the output signal of which is equal to 0.957 023 times the frequency of the input signal, which in the binary system, again assuming the input frequency to be 1.000 000 000 000 000, is 0.111 101 010 000 000. In a manner similar to that shown in FIG. 3, the outputs of those dividers-by-two d1 to d4, d6 and d8 respectively which form groups the output pulse trains of which correspond to the pulse trains obtained in the signal at the output of the frequency converter, and the outputs of those dividers-by-two d5 and d7 which form groups the output pulse trains of which correspond to the pulse trains which are not contained in the signal at the output of the frequency converter, are connected to inputs of respective inverting gate circuits G2 to G5 the outputs of which are connected to inputs of the preceding inverting gate circuits G1 to G4. Since the last seven zeros do not contribute to the pulse train at the output of the gate circuit G1, the second inputs of the dividers-by-two d9 to d15 are not connected as the last group of dividers-by-two of which the pulse trains form part of the pulse train in the desired output signal consists of only one divider-by-two d8 the output thereof is jointly connected with the output of the preceding group of "O"'s consisting of divider d7 to the input of the inverting gate G5. If the last group of dividers-by-two the pulse trains of which correspond to pulse trains contained in the desired signal should have exceeded unity, these outputs only should have been jointly connected to an inverting gate circuit. Musically satisfactory frequencies which mutually differ in pitch by an octave are produced at the outputs of the dividers-by-two d8 to d18. In this circuit arrangement according to the invention the dividers-by-two d1 to d9 at the same time perform the functions of the equalizing dividers C1 to C9 . . . B1 to B9 of FIG. 1. The the dividers d8 to d18 also have the functions of the octave dividers C10 to C15. It is true that the output frequencies of the latter dividers normally are inaudible, however, they may at will be used to produce a vibrato or a tremolo, or to control, for example, an electronic "Leslie" circuit, so that from an oscillator set comprising the master oscillator G together with twelve frequency converters all the musically satisfactory frequencies which may be produced in an electronic musical instrument are obtainable. Obviously, as an alternative the oscillator frequency may be so high that the frequency at the output of the divider d18 of the final frequency converter is the lowest frequency desired in the musical instrument. Naturally, as a further alternative the frequency of the oscillator G may correspond to the frequency of a tone in the octave other than C. If desired, the oscillator G may be tunable in steps or continuously.
FIG. 5 shows a possible structure of a frequency converter for the intervals of an equal-tempered twelve-tone scale. Starting from a frequency of 1.000 000 000 000 000 in the binary system (1.000 000 in the decimal system) the interval is substantially equal to 0.111 100 011 01 when the outputs of the first eleven dividers-by-two d1 to d11 are used, to 0.111 100 011 010 001 when the outputs of the first fifteen dividers-by-two d1 to d15 are used, and to 0.111 100 011 010 000 111 when the outputs of all the eighteen dividers-by-two d1 to d18 are used. If 11 dividers-by-two are used, with C as the key, the frequency deviation at the output of the final frequency converter DES (D flat) will be about 330 times 10-6. The use of 15 dividers-by-two reduces this deviation to about 46 times 10-6, and the use of 18 dividers-by-two to only about 1.3 times 10-6. Even the frequency deviation in the circuit comprising 15 dividers-by-two is so small as to be negligible. A severer criterion is the deviation of the fifths, because starting from the fifth F-C, which interval is 1.49860 in the circuit comprising eleven dividers, and descending, an abrupt variation occurs in this value which begins at the interval C-G. In the circuit comprising eleven dividers the variation is equal to 1.49810. In the circuit comprising 15 dividers, these values have become 1.49827 and 1.49834 respectively, so that the difference is no longer perceptible. Hence for this reason the provision of an additional gate circuit and its connections to the dividers d16 to d18 is unnecessary. The circuit comprising eleven dividers-by-two d1 to d11 requires the use of five gate circuits G1 to G5, that comprising 15 dividers D1 to D15 requires the use of seven gate circuits G1 to G7, and that comprising eighteen dividers d1 to d18 requires the use of eight gate circuits G1 to G8. The Figure shows the connections for these three cases, the additional connections required for the cases of 15 and 18 dividers being shown by dashed lines and dot-dash lines respectively.
FIG. 6 shows another possible structure of the circuit arrangement of FIG. 5, the various gate circuits each comprising two gates and an inverter stage interconnected between the gates wherein one of the two gates as shown in parentheses may function merely as an amplifier permitting a delay equivalent to a gate. Although for certain purposes it may be desirable to use such a structure, for integrated circuits the arrangement of FIG. 5 can be used in which there are crossings in the connections between the dividers-by-two d1 to d11, d15 and d18, between these dividers and the gate circuits G1 to G5, G7 and G8, and between these gate circuits enabling a particularly advantageous integrated-circuit technology with increased yield to be used, as is shown in FIGS. 7 and 8 which each show an integrated circuit according to the invention made by a different method.
FIG. 7 shows the manner in which a frequency converter according to the invention may be constructed as an integrated circuit which is manufactured by the "injection feed" method as described in British Patent Application No. 23699-72 corresponding to U.S. patent application Ser. No. 253,348, filed May 15, 1972. In this case the circuit comprises a heavily doped n-type (n+) silicon substrate on which a lightly doped n-type layer is provided which forms the common emitter for all the npn transistors in the circuit. The bases for the various transistors are provided by p-type diffusion into the n-type layer and subsequently the collectors are produced by n-type diffusion into the resulting p-type regions. The p-type diffusion simultaneously forms the injecting layer which together with the n-type layer situated between this injecting layer and the p-type regions provides the supply to the transistors. A pattern of leads is provided on the insulating silica layer produced by the diffusions, which pattern appropriately interconnects the various regions. The dividers-by-two are designated in the Figure by d1 to d18. These dividers-by-two may have any suitable form, for example that described in the aforementioned British Patent Specification No. 1,264,143 (PHN.2989), FIGS. 6 and 7, from which it is evident that the signal, depending on its desired form, may be taken from the point at which it is produced, for example, from the point C or D for a pulse having a mark-to-space ratio of 1:1.
The positive supply voltage is applied to the dividers-by-two d1 to d18 via a lead pattern 2. The dividers-by-two are connected to one another by leads 3. Gate circuits G1 to G7 take the form of transistors T1 to T7, while the transistors which are connected to dividers-by-two are as far as possible located near these dividers to simplify the structure of the integrated circuit. The transistors are interconnected by a pattern of leads 4. The Figure shows that the various connections do not cross, with a consequent increase in yield. The frequencies suitable for use in the musical instrument may be taken from the dividers-by-two d8 to d18 via connections 8 to 18, while the input is denoted by E and the output by U.
FIG. 8 shows a frequency converter manufactured according to the "miniwatt" technique. This is a conventional integrated-circuit technology in which a pattern of heavily doped n-type regions, one of the purposes of which is to form low-resistance collector connections, is formed in a p-type silicon substrate and then an epitaxial n-type layer is provided. The n-type layer is divided into isolated islands by a pattern of p-type diffusions and subsequently, to form inter alia transistors, p-type diffusions are provided in the islands to form the bases for the transistors and finally n-type diffusions are provided in the diffused p-type regions to form the emitters. On the layer of silica produced in these diffusion operations a pattern of leads is provided which appropriately interconnects the regions. In a manner similar to that described with reference to FIG. 7 the dividers-by-two d1 to d18 may consist of any desired divider-by-two circuit. The dividers-by-two d1 to d18 are interconnected by a lead pattern 3, and the gate circuits G1 to G7 are connected to one another and to the dividers-by-two by a lead pattern 4. As the Figure clearly shows, crossing points are avoided in this embodiment also.
The positive supply voltage is applied via a lead pattern 2 and the negative supply voltage is applied via a lead pattern 5.
The advantage of the circuit arrangement which includes inverting gate circuits is that the positions in time of the trailing edges of the substrahend pulse and the minuend pulse are equal. Because the subtrahend pulse always is derived from dividers having a lower output frequency, care is taken to ensure that the pulse width of this output pulse is reduced by combining it with the output pulses from the dividers situated between the output of the subtrahend-pulse divider and the divider a pulse from which is to be suppressed by the subtraction. Thus, a sequence of subtrahend pulses is obtained which have a pulse width which is about twice that of the minuend pulse. Owing to the fact that the output pulses of the successive dividers may be delayed in time the subtrahend pulses will be slightly delayed with respect to the minuend pulses, however, this provides no difficulty, because substantially a full width of the minuend pulse is available to accommodate the delay of the subtrahend pulse, so that this delay is no longer of any importance. This is illustrated by FIG. 9 which shows how for, for example, the gate circuit G7 of FIG. 5 in the case of 15 dividers the pulse width of the divider D15 is reduced, by combining it with the pulses from the dividers d12 to d14, to the pulse width of the shortest of these pulses, i.e., to the width of the pulse from d12, after which the pulses from the divider d11 are removed from this signal.
FIG. 9 shows the waveforms of the various pulse trains which occur at the inputs and the outputs of the gates G6 and G7 of FIG. 5. In In FIG. 9, f12, is the pulse train which appears at the output of the divider d12, f13, the pulse train which appears at the output of the divider d13, f14, the pulse train which appears at the output of the divider d14 and f15, the pulse train which appears at the output of the divider d15. Because the gate circuit G7 is a NAND-gate, at its output the pulse train f7 appears which, as the Figure clearly shows, has the pulse width of the divider having the highest frequency, i.e., the divider d12, and the frequency of the divider having the lowest frequency, i.e., the divider d15 ; f11 ' is the pulse train at the second output of the divider d11 and is combined in the NAND gate G6 with the pulse train f7 which appears at the output of G7, so that at the output of the NAND-gate G6 there appears a pulse train f6, the pulse train f7 subtracting a pulse from the train f11. The Figure clearly shows that only if the pulse train f7 has a delay equal to the pulse width of the pulse train f11 ', residues in the form of spikes of the minuend pulse of the train f11 ' will be left. A delay of the magnitude does not occur in practice.
In the aforedescribed circuit arrangements the dividers are NAND dividers which divide at the ascending edge with the use of a second output of the divider-by-two, the gate circuits comprising NAND-gates. As an alternative the NAND dividers which divide at the ascending edge may be replaced by NAND dividers which divide at the descending edge or by NOR dividers of either type. Furthermore the NAND gates may be replaced by NOR gates. The dividers may have single outputs. The following Table gives a number of possible combinations.
TABLE
Type of the dividing type of output used at gates in each dividers used divider 1) NAND dividers ascending NAND gates 2nd edge 2) NOR dividers descending NOR gates 2nd edge 3)NAND dividers ascending NOR gates 1st edge 4)NOR dividers descending NAND gates 1st edge 5) NAND dividers descending NAND gates 1st edge 6) NOR dividers ascending NOR gates 1st edge 7) NAND dividers descending NOR gates 2nd edge 8) NOR dividers ascending NAND gates 2nd edge
FIG. 10 shows pulse trains which correspond to those of FIG. 1 for the case in which the circuit arrangement of FIG. 7 comprises NOR dividers which divide at the descending edge and the second outputs of which are used, and NOR-gates.