This invention relates to method and apparatus for controlling the display of a plurality of different segments of information on a processor read-out device and more particularly to a system for controlling the operation of a segmented cyclically refreshed display which may display information in a plurality of different modes.
In display systems which utilize display devices such as cathode ray tubes (CRTs) which do not have storage capability, an external storage device must be provided. Information is read-out from the storage device in some predetermined sequence and utilized to refresh the display on the display device. Normally there is a one-to-one correspondence between character storage positions in the memory device and character display positions on the display device. Where a plurality of display devices are being refreshed from a single memory, separate memory positions are required for each character which appears on each display device.
While for many applications the system described above is adequate, it can lead to the redundant storage of information where a given unit of information, such as for example a newswire or a stock morket ticker, is to be displayed on a number of the display devices being refreshed from the memory. Where the data is displayed in a common position on all of the display devices, the problem indicated above has in the past been solved by the use of suitable gating circuits. However, where a segmented display is provided, and the user is given the option of displaying a particular type of information in different areas or segments of the display, the problem of optimum utilization of memory becomes more complicated.
Further, the characters to be displayed on a given display device have normally been stored in sequential, or at least related (i.e. position separated by uniform number of characters from each other) positions in memory so that a fixed clocking arrangement may be utilized to read-out from the memory and distribute the read-out characters to the appropriate display device. However, with a segmented display where some stored segments of information are displayed in different segment positions, or even in the same segment position, on a number of different display devices, while, during the same refresh of the displays, information to be displayed in each of the other segments of the displays are derived each from a different memory segment, the ordering of the memory to permit sequential read-out for each display device is no longer possible. Where the operator is further given the option of displaying information in a plurality of different modes, with it being possible to display a given item of information in different segment positions in different modes, and also being possible to display different types and items of information in each of the modes, there is no way to efficiently store the information required for the various modes in any predetermined order.
With a segmented display in general, and with a multi-mode segmented display in particular, a need therefore exists for a new approach to the obtaining of information from memory to refresh the display. This approach should ideally permit each item of informa-tion which is to be displayed on one or more display devices to be stored in memory only once, and should provide maximum flexibility in the assignment of memory areas or segments to control the display of information on one or more segments of associated display devices.
With display devices of the type indicated above, a keyboard or other data entry device is normally provided to permit the operator to request data in a given display segment, to alter the data displayed in that segment, or to perform various editing, mode selection or other functions. A visible entry marker on the display normally indicates the position on the display at which a new character will appear or at which an editing function will commence. The control system stores an indication of the position of the entry marker and causes functions called for by the keyboard to be commenced at the indicated position in the corresponding memory segment. When, in a system of the type indicated above, there is a change in the mode of display, a determination must be made of the position in which the entry marker is to be placed in the new display mode. If the entry marker always was positioned in the first character position of the first segment of the display, this would be a relatively simple operation. However, there are various types of displayed information over which the operator has no control. These types of information are generally referred to as common displays and includes such items as newswire, stock market ticker, and other information generated from a common source. When a new mode is selected, a determination must be made as to the segments which contain common displays and the entry marker placed in the first character position of the first segment which does not contain a common display. If all segments are common, then no entry marker is displayed for the particular mode of operation. In addition, the operator may be given the capability of indicating a particular type of display in which he would like the entry marker to be positioned. In order to perform this function, the system must have the capability of determining the type of display appearing in each of the segments and of position-ing the entry marker in the first character position of the first segment or next segment containing the desired type of information.
There may also be applications where more than one segment of the display will be required in order to display a particular type of information. When two or more segments are chained together in this way, a way must be provided so that, for example, when an entry marker is homed or some other similar function is performed, the system will know to return to the first of the chained segments.
Another problem which may arise with a multi-mode display is that the information displayed in a given segment for a given mode may be periodically updated. With common displays such as newswire this of course occurs continuously with appropriate changes being made in the storage segment containing this information. However, in order to conserve memory, a particular memory segment may be utilized to store different types of information for different display modes. Where one of the types of information is periodically updated, such as for example, displays of stock quotations, it would be preferrable if this information could be retained and the updating of this information continued during the period that the information is not being displayed. However, if the particular memory segment is being utilized to display a different type of information in the newly selected display mode, then the memory segment must be cleared and the update inhibited. Means for performing these functions should thus be provided.
Finally, the operator should be provided with a capability for changing the types of information and/or the arrangement of information which is displayed in each of the various modes. The system must thus have the capability of responding to mode change requests and for performing the necessary memory updates.
While the requirements indicated above exist particularly for cyclically refreshed display devices, many of the requirements would exist equally for other processor read-out devices when operating to present multi-mode segmented information. Thus, where appropriate in the discussion to follow, the term display may be considered to generically apply to processor read-out devices.
It is therefore a primary object of this invention to provide a new approach to the controlling of a segmented information presentation and more particularly to the controlling of a multimode segmented display.
A more specific object of this invention is to provide an approach of the type indicated above which permits each item of information to be displayed to be stored only once in a memory device and to permit maximum flexibility in the assignment of memory segments for storing information to be displayed on a given display device in a given mode.
Another object of this invention is to provide an approach of the type indicated above which permits entry markers to be positioned in a segment containing a desired type of information but prevents the positioning of an entry marker in a common segment.
Another object of this invention is to permit two or more segments to be chained together for the display of common informa-tion and to effect the various controls required by such chaining.
Still another object of this invention is to permit memory segments to be utilized to store different types of information for different modes of operation of a given display device while permitting information to be saved, and if appropriate updated, when the display is in a mode which does not require the use of the memory segment for either type of information which it is adapted to store.
A still further object of this invention is to provide a system and approach of the type indicated above with the capability on the part of the operator of varying the type and arrangement of information which is to be displayed in each of the available modes.
SUMMARY OF INVENTION
In accordance with these objects this invention provides a system for displaying a plurality of different segments of information on a cyclically refreshed display device such as a cathode ray tube (CRT). An addressable memory means is also provided for storing a plurality of segments of information. The memory addresses of the segments presently being displayed are stored by a suitable means. The contents of a selected segment of the memory is read-out to refresh a segment of the display device. When refresh from a given memory segment is completed, the addresses stored in the memory address storing means are utilized to determine the address of the selected memory segment to be utilized to refresh the next segment of the display device. The memory address storing means stores the addresses of the segments presently being displayed on each of the plurality of display devices. In addition, a means is provided for storing the memory addresses of the segments to be displayed in each of the modes for each of the display devices. When a new mode is selected by a suitable mode selecting means, the memory addresses for the segments for the new selected mode are transferred into the positions for the given display device in the means for storing the memory addresses of the segments presently being displayed.
An entry marker is displayed to indicate the display position where new information is be displayed or an editing function may begin. When a new mode is selected, a determination is made by a suitable means of the first segment in the new mode which is not a common segment and an indication of the memory address of this position is stored in a suitable means. When there is a mode change, a means is also provided for determining if any memory segment utilized to store information in more than one mode contains information in the previous mode which is to be saved and a means is provided for determining if the segment containing saved information is to be utilized in the new mode. If the segment is to be utilized in the new mode, a means is provided for clearing the segment.
Means are also provided for indicating segments containing related information including means for indicating the first and last segments of a chain of segments containing related information. Finally, means are provided for generating a form on the display for setting up a new mode, and means are provided in the system for generating the various segment address indications and information type indications required for the new mode and for storing these indications in the appropriate storing means.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.
IN THE DRAWINGS
FIG. 1 is an illustration of an exemplary display for a preferred embodiment of the invention.
FIGS. 2-5 are diagrams illustrating various ways in which the display may be segmented for a preferred embodiment of the invention.
FIGS. 6A-6B, when combined, form a schematic block diagram of the system of a preferred embodiment of the invention.
FIG. 7 is a diagram of a keyboard layout suitable for use in the embodiment of the invention shown in FIGS. 6A-6B.
FIGS. 8A-8B, when combined, form a diagram illustrating the information contained in a device control area of the memory shown in FIG. 6A.
FIG. 9 is a diagram illustrating a portion of the information contained at the beginning of one of the operating segments of the memory shown in FIG. 6A.
FIGS. 10A-10B, when combined, form a generalized flow diagram of the operations performed by the system in response to various inputs from a keyboard.
FIG. 11 is a flow diagram of the operations involved in displaying the stored information.
FIG. 12 is a flow diagram of the operations involved in changing the type of information or arrangement of information displayed for one or more of the modes at a given display device.
FIG. 13A is an illustration of the mask displayed for mode set-up initial assignment.
FIG. 13B is an illustration of an exemplary mask displayed for mode set-up change.
FIGS. 14A-14F, when combined as shown in FIG. 14, form a detailed flow diagram of the operations performed when a mode or function key is depressed on a keyboard.
FIGS. 15A-15B, when comvined, form a schematic block diagram of an illustrative control unit sutiable for use as the control unit shown in FIG. 6B.
DESCRIPTION OF DISPLAY
FIG. 1 is an illustration of a typical display which might appear on the face of a cathode ray tube screen or the screen of a similar display device utilizing the teachings of this invention. The particular display shown in FIG. 1 is for a stock market information system. For purposes of illustration, the discussion to follow will be primarily with respect to such a system. FIG. 2 is a diagram of the format of the display shown in FIG. 1. From FIGS. 1 and 2 it is seen that with this display format, three lines are utilized to display New York Stock Exchange (NYSE) ticker, three lines for American Stock Exchange (ASE) ticker. A three line inter-segment space (ISS) is provided followed by six lines of quote information relating to a particular stock, another three line ISS, and six lines which will be assumed to be management information generated either at the display itself for storage in the system or generated at some other terminal of a user system. The last six lines might also be newswire information from a newswire service. As may be best seen in FIG. 2, the lines of the display are normally 40 characters wide the lines extending from a character five to a character 44 position. However, in order to provide maximum dwell time on the display for a moving ticker, the full 48 possible characters are utilized for each ticker line. Circuitry for controlling the width of the lines is shown in copending application Ser. No. 178,691 filed Sept. 8, 1971 on behalf of Francis E. Albrecht, et al. and entitled "Raster Control Device," while patent application Ser. No. 178,690 filed Sept. 8, 1971 on behalf of Francis E. Albrecht, et al. and entitled "Method and Apparatus for Generating a Traveling Display" discloses circuitry for causing the moving of the lines of the ticker display. Both of the above applications are assigned to the assignee of the present application.
The individual characters of the display shown in FIG. 1 are formed by selectively intensifying various ones of seven idex points appearing on each of five strokes. The characters are thus formed in a 5 × 7 matrix of 35 index points. Each of the lines is formed of a number of strokes required for the given number of characters. Circuitry for generating characters of the type indicated above is shown in U.S. Pat. No. 3,500,327 issued Mar. 10, 1971 to R.D. Belcher, et al, entitled "DATA HANDLING APPARATUS" and assigned to the assignee of the present application. It should also be noted that the display contains an entry marker 10. This mark is formed by intensifying all 35 of the index points for the given character position. The entry marker indicates the character position on the display at which a new character received by the system will be stored and displayed or at which a requested editing function will commence. More will be said about the entry marker in the discussion to follow.
As will be more apparent from the discussion to follow, the 24 lines of the display shown in FIGS. 1 and 2 are divided into 8 three-line segments. With the display format shown in FIG. 2, the first three-line segment displays NYSE ticker, the second three-line segment ASE ticker, the third three-line segment is an ISS segment which contains a blank line followed by a line containing spaced dot indications, and a third line which is also blank. The fourth and fifth segments are utilized for a quote display, the sixth segment for ISS, and the seventh and eighth segments for management information system (MIS) information.
The format shown in FIG. 2 is only one of the many formats or modes in which the eight segments of the display may be utilized. In FIG. 3, the first three segments are utilized in the same manner as in FIG. 1. However, the last five segments of the display are chained together to form a 15 line area for displaying MIS information. In FIG. 4, all eight segments of the display are chained together for displaying MIS information while in FIG. 5 the 48 character ticker display in the first two segments has been replaced by a normal 40 character, six line (two segment) area which may be utilized, for example, to display quote or MIS type information. In addition to varying the size of the segment groups or areas for various modes, the information displayed in each segment of the display may also be varied for different modes. Thus, the first segment group in a display such as that shown in FIG. 5 may contain a first type of quote information in one mode, the second segment group a second type of quote information, and the third segment group MIS information, while in a second mode, the first segment group could contain MIS, the second segment group a first type of quote information, and the third segment group newswire. A display is thus provided with the potential for an almost unlimited variation in the available modes of display. The discussion to follow will describe how thse various modes are generated and controlled.
FIGS. 6A and 6B form a general circuit diagram of a system of a preferred embodiment of the invention. The system is utilized to control the operation at a plurality of terminals 12 (FIG. 6B) each of which consists of a display device 14 and a keyboard 16. Each of the displays 14 is adapted to display information of the type shown in FIGS. 1-5.
Information for controlling and refreshing the display on each of the display devices 14 is contained within a random access memory 18 which may, for example, be a magnetic core matrix array. Memory 18 is divided into a number of areas. The first few address positions of memory 18 form a port buffer area 18A where information from one of the keyboards 16 or from some other external device may be temporarily stored. The second group of memory segments are the control segments 18B. There is a control segment 18B for each of the display devices 14. FIG. 8 is a detailed diagram of the control area for one such device. Generally, referring still to FIG. 6A, the control segment area for each device includes an area 20 containing the segment addresses in memory 18 for the segments being utilized to refresh each of the eight segments of the display for the given device. Area 22 of control area 18B is generally only one word and contains an indication of the position of the entry marker 10 including the segment address of the marker. Area 24 contains a keyboard indirect jump address (KIJA) and various save words. The functions of the words in this area will be described later. Area 26 of the control segment contains various screen format words, each of which indicates the types of information in each segment for various modes of operation of the display device. Area 28 contains the segment addresses for all four modes of the display device, the segment addresses for one of these modes also appearing in area 20.
Segments 18C of memory 18 are common segments which contain items such as ticker, newswire, and the like. Information in these segments may be displayed on any display device but may be displayed in only one form and may not be altered. The remaining segments, segments 18D, of the memory are operating segments which may be assigned to individual ones of the display devices and which may contain quote, MIS, or other types of information to be displayed on the devices.
The information in memory 18 is read-out under control of addressing signals received on lines 30 from memory address circuit 32. Addressing information is applied to circuit 32 through line 34 from OR gate 36. Information is received at OR gate 36 through line 38 from control unit 40 and through lines 42 from word counter 44 and segment number registers 46. Control unit 40 performs various processing operations and generates various address and information outputs to memory 18. Control unit 40 would normally be a program-controlled special purpose or general purpose processing unit. An illustrative special purpose unit for performing some of the functions required of control unit 40 is shown in FIGS. 15A-15B and described later.
As will be seen in more detail later, each addressable position in memory 18 has a word address which is normally divided into two characters. The system includes a display clocking circuit 48 (FIG. 6B). This circuit includes a character clock counter 50 which is in synchronism with the rate at which a display device 14 moves past display character positions, and which normally resets to zero after reaching a count of 40 (special control circuit is provided for handling ticker lines as described in beforementioned copending application Ser. No. 178,691), a line clock counter 52 which is incremented by a line clock on line 53 when the character counter resets to zero and is itself reset after reaching a count of 24, and a segment clock counter 54 which is incremented by a segment clock on line 55 generated each time the line clock counter resets to zero. The segment clock counter resets to zero itself after reaching a count of eight. In addition, as will be seen shortly, N number of devices are scanned for each character count. A device clock line 56 is thus provided to increment a device clock counter 57. This counter resets to zero after reaching a count of N, N being the number of terminals in the system, and generates a character clock on line 51 when it resets. Device clocks appear on output lines 60 from counter 57, character clocks appear on output line 62 from counter 50, line clocks appear on output lines 64 from counters 52, and segment clocks appear on output lines 66 from counters 54. No attempt has been made to connect the various clock lines to the points in the circuit at which they are utilized. Instead, suitably numbered and labeled lines appear at each of these points.
Character clock line 51 is connected through divide-by-two circuit 68 to generate word clocks on line 70. The word clocks on line 70 are applied to increment word counter 44, word counter 44 being utilized to indicate the word position in each segment 18C or 18D which is being read-out at any given time to refresh displays 14. Registers 46 contain the segment addresses in areas 18C or 18D of memory 18 of the segments which are being read-out from at any given time to refresh the displays on corresponding devices 14. There is a segment register 46 for each device. The appropriate one of the device clocks 60 is applied to control the read-out of each of the registers 46 onto lines 42. Thus, during device clock time 1, the contents of the first of the registers 46 is read-out onto lines 42 to cause the word indicated in register 44 of the address segment to be read-out from memory 18.
When all of the words for the segment indicated by the addresses in registers 46 have been read-out, control unit 40 generates address outputs on lines 38 to cause the next segment address in the area 20 of the control segments for each of the display devices to be read-out through lines 72 to the appropriate register 46. The control unit also generates a signal on line 74 at this time to condition gate 76 to pass these address signals. The address of the memory segment which is being utilized to control the display on the segment of each display device 14 which is being refreshed at any given time is thus stored in the register 46 for the device.
The words read-out from segments 18C and 18D of memory 18 are applied through line 80 and buffer and control circuit 82 to character generator 84. Buffer and control circuit 82 takes account of the fact that two characters are read-out during each cycle and assures that the proper one of these characters is applied to the character generator at any given time. Character generator 84 may be any one of a variety of devices which are capable of accepting information in a transmission and storage code, such as the seven bit ASCII code, and of converting the received character into the corresponding 35 bit video character required for display.
The video output code on line 86 from character generator 84 is applied through OR gate 88 to multiplex control circuit 90. This circuit also has as an input device clock line 60. Circuit 90 is operative to cause each character generated by generator 84 to be applied through transmission line 92 to control the display on the appropriate one of the display devices 14.
When information is read-out of memory 18 under control of address inputs from control unit 40 on lines 38, the information is passed through lines 93 to be stored in memory data register (MDR) 94. The information in MDR 94 may be either passed to control unit 40 or be restored in memory 18 through lines 95 under control of unit 40. Unit 40 may also store information in memory 18 by applying the information through lines 97 to MDR 94.
As was indicated previously, the control segments 18B for each device include an area 22 containing the address at which the entry marker is located for the given device. During the frame retrace time of each display device refresh cycle, the contents of area 22 for each device are read-out through lines 96 into the corresponding register of entry marker registers 98. The contents of the registers 98 are compared in circuit 100 with clock signals from circuit 48. When the clock indicates that the display for a given device is at the position containing the entry marker for that device, circuit 100 generates an output on line 102 which triggers special character generator 104 to generate the entry marker symbol (a video code in which all 35 index points are energized for the mark shown in FIG. 1) on lines 106. The signals on line 106 are applied through OR gate 88 to multiplex control 90 to be distributed to the proper display device.
FIG. 7 illustrates a keyboard layout suitable for use with the keyboards 16 shown in FIG. 6B. From FIG. 7 it is seen that the keyboard includes a complete set of alphabetic keys 110, a complete set of numeric keys 112, a group of editing keys 114, a group of fraction keys 116, four mode selection keys 118, an MIS function key 120, a quote function key 122, a mode set-up request key 124, a mode set-up transmit key 126, additional keys 128 which may be utilized to perform other special functions, a clear key 130, a home key 132, a transmit key 134, a print key 136, and a monitor key 138. The depression of any one of these keys causes an appropriate code to be applied through transmission line 140 (FIG. 6B) and a suitable I/O interface unit 142 to control unit 40. The manner in which these various coded inputs to control unit 40 are utilized will be described shortly.
DETAILED DESCRIPTION OF MEMORY CONTENT
FIGS. 8A-8B form a diagram illustrating the contents of the control portion 18B of memory 18 for a given display device. From this figure, it is seen that the first four words of this area contain display control words each of which contains two segment addresses in memory 18 for segments whih contain the information which is being displayed in the indicated segment positions on the display device. Thus, the first control word contains the segment addresses of the information displayed for the first and second segments of the display device. With the display configuration shown in FIG. 1, segment 1 contains the segment address in common segment area 18C at which NYSE ticker information is stored. The segment two address is the address in common segment address area 18C of the segment containing ASE ticker information. The address is the first character position of the second control word is the address of the segment containing the inter-segment space (ISS) information. Since segment six of the display also contains ISS information, the memory segment address in the second character position of display control word three would be the same as that in the first character of the second control word. The first four words shown in FIG. 8 are the words in area 20 shown in FIG. 6A. It is from these words that the characters stored in the register 46 for the device are derived.
Display control word five contains the address in the display at which the entry marker 10 is to be displayed. It is seen that this address includes both a display segment address, a display bit address and a display word address. The fifth display control word corresponds to the area 22 shown in FIG. 6A. It should be noted that the display control word also contains five bits which may be utilized to indicate the nature of an indicator character to be displayed in a predetermined position of the display. This character is flashed to tell the operator that some change has occurred either in the display presently on the screen or in the display for one of his other modes. The character contained in these bits may be varied to vary the character displayed in this predetermined position of the display.
The next word, the sixth word of the control area, is the keyboard indirect jump address (KIJA). The function of this word will be described later. The next word of the display contains two characters which are the segment save addresses. Again, the function of these characters will be described later. The sixth and seventh words of the display are represented by area 24 shown in FIG. 6A.
The eighth, ninth, tenth and eleventh words of the control area are the screen format words. The first character of each of these words is utilized to indicate the type of information stored in each two segment area of the display for each of the four possible modes of display of the device. For purposes of the present invention, it will be assumed that there are only three types of functions, common functions such as ticker and newswire which are the same for all displays and may not be altered by the operator, quote type displays which permit the operator to select the particular item of information on which he wishes information but in which the operator may not make changes, and MIS type displays over which the operator has full control. Two bits are utilized to indicate the type of function displayed in each of the three two-segment groups for each of the four modes. In addition, the second character of the first screen format word contains the screen format word for the mode of display currently being viewed (the current mode word) and the second character of the second screen format word contains the screen format word for the most recent previously viewed mode (the previous mode word). The four screen format words form area 26 of memory shown in FIG. 6B.
The final control area, area 28, of the control portion of memory for the given device contains the four display control words utilized for each of the four possible modes of the display device. As will be seen later, when a particular mode is selected for display, the words for that mode contained in area 28 of the memory are transferred into the four word positions of area 20.
FIG. 9 illustrates the first two words of each of the operating segments in 18D of memory 18. These words are utilized for control purposes. The first of these words contains a display segment pointer (bits 1-3 of the first character) which indicates the relative position of the segment in the eight segments displayed for the selected mode. The second character of this word contains an indication of entry marker position within the segment. It should be noted that it is necessary to store this information within the operating segment since the operator may be working in a different display segment or in a different mode from that in which the memory segment is utilized and the entry marker address in area 22 of memory only contains information as to the entry marker position for the segment presently being worked in. When the operator indicates that the display entry marker is to be in the given segment, the stored entry marker address is utilized to obtain the address stored in area 22 of memory.
The second word of the segment contains information in the first character position and in bits 1-4 of the second character position which are of no concern with respect to the present invention. Bits 7 and 8 of the second character are the first segment bit and last segment bit which are utilized in a manner to be described later for chaining segments together. Bit 6 is the A2 control bit which is utilized to inhibit update of a quote/MIS type segment when the segment is being used for the MIS function. Bit five is not utilized in connection with the present invention.
GENERAL DESCRIPTION OF OPERATION
FIGS. 10A-10B form a flow diagram illustrating the functions which are performed when various keys on a keyboard 16 are depressed. Referring to these figures, assume initially that the operator depresses a key such as one of the alpha-numeric keys 110, 112 or an editing key 114, 130, 132, 136 or 138. Under these conditions, the system would branch from step 150, through step 152 (FIG. 10B), to step 154. When control unit 40 determines that an editing or data entry key has been depressed, it determined the address of the current mode word for the device generating the request, the address of entry marker address portion 22 for the device, and the address of such other control words as it may require. It then generates address outputs on lines 38 causing these characters to be read-out from memory through line 93 in to MDR 94. Finally, it retrieves the required words from MDR 94 and stores them in appropriate registers in the control unit. It should at this point be noted that memory 18 may be accessed at a rate which is normally about 10 times the rate at which characters are required to refresh displays 14. Thus, many memory accessed may be performed for various control and other functions between each access to the memory under control of lines 42 for purposes of refreshing the display.
The control unit then decodes the received input function (step 156). During step 158 the control unit utilizes the retrieved function word (i.e., the current mode word) to determine if the requested function is a valid function for the segment type in which the entry marker is positioned. For example, if the current mode word indicates that all segments are common segments, then any data entry or editing function would be invalid. Similarly an attempt to edit text in a quote segment would be recognized by this system as being an invalid input. If the control unit determines that the attempted data entry function is invalid during step 158, the system ignores the input (step 160). Alternatively, the control unit could, during step 160, send an error message to memory 18 for display on the requesting device.
If the requested operation is valid, the system branches to step 162 during which a determination is made of the segment which contains the entry marker. This determination is made from the entry marker information retrieved from portion 22 of the memory control area. The control unit then branches to a suitable microprogram for performing the requested function (step 164). The function may be performed in a standard manner and the operations required to perform this step do not form part of the present invention.
There are some functions, such as the clear function called for by key 130 (FIG. 7) or the home entry marker function called for by key 132, which may require that the function performing micro-program operate within more than one segment where two or more segments are chained together for display purposes. Thus, during step 166, the system tests to determine if the function is of a type which may involve more than one segment. If the function is of this type, when the operating micro-program reaches the end of a segment, it utilizes the chaining bits in bit positions seven and eight of the second control word in each segment (see FIG. 9) to determine if all required segments in the chain have been looked at (step 168). If all segments in the chain have not been looked at, the system branches back to step 164 with the CU continuing to perform the function in the next segment.
When, either as a result of an indication during step 166 that only one segment is involved, or as a result of an indication during step 168 that all segments have been looked at and the function is complete, it is determined that the function is in fact complete, the system branches to step 170. During this step, the control unit determines the new position of the entry marker as a result of the function performed, stores this address in the control unit entry marker register, and then transfers this address both to the entry marker word in area 22 of memory 18 and to the first word of the operating segment or segments involved in the operation. When more than one segment has been involved in the operation, step 170 may involve erasing the entry marker from the segment where it was originally indicated as being and placing an entry marker indication in the new segment where it is located. With the completion of step 170, the control unit has completed the operations required by the depression of a data entry or editing key and is ready to accept a new input.
If as a result of key depression step 150, it is determined that MIS key 120 or the quote key 122 on keyboard N has been depressed, then there will be a yes output from function-key-depressed step 174 (FIG. 10A). When MIS key 120 is depressed, it is desired to move the entry marker to the home position of the first MIS segment following the segment at which the entry marker is presently positioned. Similarly, when quote key 122 is depressed, it is desired to move the entry marker to the first segment containing quote type information following the segment at which the entry marker is presently positioned.
To accomplish the functions indicated above, the first step in the operation, step 176, is to read the current mode screen format word from section 26 (FIG. 8A) of memory 18 into a register of control unit 40. As indicated previously, this is a two step operation which involves reading the word out into MDR 94 and transferring the word from MDR 94 into control unit 40.
The next step in the operation, step 178, is to determine the function (i.e. MIS or quote). The current mode word in control unit 40 is then scanned, starting with the segment following that at which the entry marker is presently positioned, to find the next display segment with the desired function (step 180). This step will be described in greater detail later. Basically, it involves looking at the two bit code in the current mode word for each segment, starting with the segment following that in which the entry marker is presently positioned, and selecting the first segment located having the desired code.
When the desired segment is located, the address of the home position for this segment is determined by the control unit and the new entry marker address is stored in area 22 of the control area for the device (step 182). From FIG. 8A it is seen that area 22 is the fifth display control word and is the word which identifies the position of the entry marker. In addition, during step 182, the pointer in the first control word of the segment originally containing the entry marker will have the entry marker moved to the home position and the entry marker control word of the segment to which the entry marker was moved will also point to the home position. These operations having been completed, the system is ready to accept a new keyboard input.
Assume now that one of the four mode keys 118 (FIG.7) is depressed. The depression of one of these keys is operative to change the display mode for the device. Assume, for example, that the four modes are those shown in FIGS. 2, 3, 4 and 5. Then, if the display is initially in mode one with a display of the type shown n FIG. 2, and the mode two button is depressed, the mode of display would switch to that shown in FIG. 3.
Referring now to FIG. 10A, if from step 150 it is determined that a mode key is depressed, there is a yes output from step 190. During step 192, the display words for mode M in area 28 of the control segments for the given device are transferred into area 20, the current display control word area of the memory. During step 194, the current mode word in the first screen format word of area 26 in the control area for the given device is transferred to the previous mode word position in the same area, and the screen format word for the selected mode (for example, the mode two screen format word) is transferred to the current mode word position. Steps 192 and 194 thus set up the memory control area for the new display mode.
As indicated previously, a given memory segment of the operating segments 18D may be utilized to store either quote or MIS information for different display modes. If the area is being utilized to store quote information, the system would like to continue to update the stored information with any changes in the quotes during the period of time that the quote is not being displayed in order that the most current information will be available for display when the quote displaying mode is again selected. However, this can be done only if the segment is not being used as an MIS segment in the new display mode. During step 196 the system tests to determine if the previous mode word contains a quote segment and stores the address of this segment in one of the two save addresses in the second word of area 29. The system then tests to determine if the segment at the stored address is being utilized to store MIS information in the current mode, the current mode word being utilized in this determination. If the segment is being utilized for MIS in the current mode, the segment is cleared and the A2 bit (FIG. 9) in the second control word of the segment is marked to inhibit updating. These operations will be described in greater detail later.
During step 198 a determination is made as to the number of segments which are chained together in the new display mode and the chaining bits, bits seven and eight of the second control word in each chained segment, are properly marked to indicate the relationship between the segments.
The final step in the mode changing operation, step 200, involves determining the position for the entry marker in the new mode and storing an indication of the new entry marker position. Basically, this involves locating the first non-common segment of the display and storing in area 22 of the control area for the memory the home position address of this segment. The pointer bits in the control words of the various involved segments are also set to indicate the proper addresses. Step 200 having been completed, the system is ready to display information in the new mode.
FIG. 11 is a flow diagram illustrating the manner in which the system of this invention operates to control the segmented displays. Referring now to FIG. 11, it is seen that at segment X clock time (box 210), the segment X address in the display control word area 20 for each device is read into the corresponding segment register 46 (step 212). Thus, when X is one, the segment one address in the first control word of each of the control areas 18B is read into the corresponding segment register 46.
The system then branches to step 214 during which each of the displays 14 is refreshed from the segment 18C or 18D indicated in the segment register 46. Thus, assuming that device one has NYSE ticker displayed in its first segment as shown in FIG. 1, during device one clock time the system would read-out the first character in the NYSE ticker segment of the common segments 18C and the video code for this character would be distributed through multiplex control 90 to the display 14D. If the second display 14B was also displaying NYSE ticker in its first segment, during device two clock time this same ticker character would be read-out and its video code applied to display 14B. When the first and second character for each display 14 has been read-out and refreshed on the display, the count in word counter 44 would be incremented and the second word for each of the segments indicated by the registers 46 read-out in sequence.
As this sequence of operations is being performed, the display clocks from clock circuit 56 are being compared in compare circuit 100 with the entry marker positions indicated in registers 98. When the clock count is the same as the count for a stored entry marker position, which it would not be for a segment displaying common information such as NYSE ticker, then compare circuit 100 generates a positive output on line 102, which is the equivalent of a yes output from flow diagram box 216. This results in the display of the entry marker (step 218) by energizing special character generator 104. The resulting entry marker code (all 35 bits energized) is passed through OR gate 88 and multiplex control 90 to the screen of the indicated device. The marker 10 of FIG. 1 is in this manner generated.
At the same time, the system is also testing to determine if the end of the segment has been reached (step 220). When clock circuit 56 indicates by its character and line clock count that the end of a segment has been reached, control unit 40 generates an output on line 74 and also applies addressing signals through lines 38 to memory address circuit 32 to cause the next segment address for each of the devices to be stored in the registers 46. If X is determined not equal to XN during step 222, XN being the last segment, segment eight for the example chosen, then the segment address is merely incremented (step 224). Thus, if X was initially one, then X is incremented to two during step 224 and the system returns to step 212 to cause the new egment for example segment two, of each display device to be refreshed. It should be noted that the retrace of each line on the display screen requires approximately six character times. Thus, six character display times, or approximately 60 memory cycles, are available for transferring the new segment information from memory 18 into registers 46. This transfer may thus be effected without in any way delaying the display.
If during step 222 it is determined that X is equal to XN (for example, the eighth segment of the display is the one being refreshed) then X is reset equal to X0 (i.e., X is set to one for the example given) during step 226 and the system returns to step 212 to cause the refreshing of a new frame of the display to commence.
It is thus seen that a means has been provided for cyclically refreshing the display of a segmented display with information derived from various segments of a memory. Since segments may be randomly read-out from the memory from addresses indicated in control registers, the segments utilized for refreshing the display on a given device need not be consecutive and in fact need have no relation at all to each other, and the same segment may be utilized to refresh more than one segment of a given display (i.e. the ISS segments) or to refresh the same or different segments on various display devices during a given frame. A highly efficient and versatile display system is thus provided.
OPERATION FOR MODE SET-UP
FIG. 12 is a flow diagram of the operations required for mode set-up. Mode set-up may occur under one or two different conditions. Initially, the operator performs mode set-up initial assignment to select the information which will be displayed in the four different modes for his display device. At a later time, the operator may decide that he wishes to change the information displayed or the format for one or more of the display modes. Under this second condition, the operator will execute a mode set-up change. Since the operations for mode set-up initial assignment and mode set-up change are substantially the same, except for the mask which is provided, the operations under these two different conditions will be described together.
Referring now to FIG. 12, if mode set-up is desired (step 221) then the entry marker is moved to an MIS field (step 223). If the entry marker is not already positioned at an MIS field, this may most easily be accomplished by depressing MIS key 120 (FIG.7) on the keyboard. If the first field of the display is an MIS field, this may also be accomplished by depressing home key 132.
When the entry marker is in an MIS field, a mode set-up mask is requested from the control unit by depressing mode set-up request key 124 (step 225). The mask for mode set-up initial assignment will be in the form shown in FIG. 13A with three tab points, one for each of the three possible segment areas of memory being provided on each of four lines. Each line represents a different mode of the display. To the right of the mask are the abreviations utilized to indicate five different types of information which may be displayed in the segments. The code TKR written at one of the tab points would cause the NYSE and ASE tickers to be displayed in the segment area. This is the information displayed in the first segment of FIG. 1. The code NEWS at a tab point would cause newswire to be displayed in the corresponding segment. If more than one newswire is available in the system, then additional codes would be required to permit the operator to select the particular service he desired. MIS has the significance previously ascribed to it and would permit this type of information to be displayed in the selected segment area. QTE stands for quote while SW1 stands for stock watch. With stock watch a ticker line display is generated for a single stock showing either price alone or price and volume for a given number of the most recent transactions. It is obvious that the system could be provided with the capability for selecting other types of information for display in each of the segments as well and that the types of information available would be different for non-stock market applications.
FIG. 13B illustrates how the mask might look after being filled in with modes 1-4 being the forms shown in FIGS. 2-5 respectively. When the system is performing a mode set-up change rather than a mode set-up initial assignment, the mask returned would be as in FIG. 13B with the items presently being displayed in each of the segments being indicated.
It should be noted that even though there are eight segments on the display, the mask provides space for indicating the contents of only three segments. The reason for this is that for the illustrative embodiment of the invention, segments 1 and 2, 4 and 5 and 7 and 8 are always chained together. Except in the case where two adjacent groups of these segments contain MIS information, segments 3 and 6 are always ISS segments. Where adjacent groups of segments contain MIS, as shown in FIGS. 3 and 4, the ISS segment between these groups of segments is replaced by an MIS segment. Thus, the three segment designations provided for in the mask are adequate to fully characterize the display.
Once the mode set-up mask is displayed on the screen, the operator either fills in all of the blanks if he is performing mode set-up initial assignment or changes items to be displayed in selected fields if he is performing a mode change (step 227). In the latter event, the user tabs to each item to be changed, keys a plus sign before the field to identify it as a change, and then keys in the new segment type identifier.
When the filling in of the mask or the changing of the mask has been completed, the operator visually verifies to be sure that the material keyed in is in accordance with his desires (step 228) and then depresses the mode set-up transmit key 126 (step 230). This step may cause the mask to be transmitted to a larger central processing unit where segment assignments, screen format words, and the like for the new more or modes are generated and then returned for storage in memory 18. However, for the illustrative embodiment of the invention shown in the figures, it will be assumed that control unit 40 contains circuitry for performing these functions. Thus, when key 126 is depressed, the control unit performs various checks to assure that all rules for display segment assignment have been followed (step 232). If the control unit determines that there is an error in the mode set-up, it regenerates the display at the initiating device with the error data blanked out (step 234). The operator may then re-enter the correct data.
If the control unit verifies the mode set-up, it will perform routines to generate the required screen format words and store these words in area 26 of memory and generate the various mode display words and store these words in area 28 of memory (step 236). The CU may also cause a "mode selection accepted" or similar message to appear on the screen of the mode set-up generating device. When step 236 has been completed, all the information required for the new mode set-up is stored in the system and the system may resume normal operation.
DETAILED DESCRIPTION OF OPERATION WITH FUNCTION KEY OR MODE KEY INPUT
FIGS. 14A-14F when combined form a more detailed flow diagram of the operations which are performed when a function key or a mode key is depressed. Referring now to FIG. 14A it is seen that when a determination is made that a mode or a function key is depressed, a determination is first made as to whether it is a mode or a function key (step 240). Assume initially that one of the two function keys 120 or 122 on a keyboard 16 have been depressed. Under these conditions, the operation branches to step 242 during which the current mode word is read from area 26 of memory 18 into an appropriate register in control unit 40. It should be noted that this is the same as step 176 of FIG. 10. A determination is then made as to whether the function key depressed was quote key 122 (step 244). If the function is quote, a bit is set in a control unit register (step 246). If, during step 244, it is determined that the MIS rather than the quote function is requested, step 246 is by-passed and the system branches directly to step 248.
During step 248 a determination is made as to the segment to be checked first. As will be seen shortly, two bits are stored in a last two-bit position of the register in the control unit storing the current mode word to indicate the segment which is to be checked first during an entry marker position determination. Assume that the indicated segment to be checked next is the first segment. Under this condition, the system branches to step 250A during which a determination is made as to whether the first segment is common. This is done by checking the code for the first segment in the CU register storing the common mode word. If the first segment is common, as it would be for example if ticker was being displayed in this segment as in FIG. 1, then the system branches to step 252A to determine if all segments have been checked. If all segments have been checked, as would be the case if, for example, the first segment check had been the second segment, then step 258 generates an output which causes the system to return to its normal job control program.
If, as would be the case for the example chosen, step 252A generates an indication that all segments have not been checked, the system branches to step 250B to check if the second segment is common. If the second segment is common the system branches to step 252B to determine again if all segments have been checked. Again, if all segments have been checked, the system returns to its job control program while if all segments have not yet been checked, the system goes on to step 250C to determine if the third segment is common. If the third segment is common, the system branches to step 252C, the alternative outputs from which are either a return to the system job control program or a branch to step 250A.
Since the steps 254 for determining the segment containing the desired function are the same except for circled items regardless of which segment is found to be not common, these steps will be shown and described in detail only with respect to the first segment, it being understood that what is said for this first segment will apply equally with respect to the remaining segments. If the first segment is not common, the system branches to step 256A to determine if the first segment is a quote. This again may be determined from the two-bit code for the first segment portion of the stored current mode word. Regardless of whether the answer to step 256A is yes or no, the next step in the operation is to determine if the mode key is depressed (step 258A or step 260A). The reason for this, as will be seen later, is that the functions required in block 254A are performed at the end of the operations required when a mode key is depressed as well as being performed when a function key is depressed. Assuming that the function in segment one is quote and that the mode key is not the input, the next step in the operation is to determine whether the desired function (i.e., the function key depressed) is a quote (step 262A). If the segment contains quote information, but the required function is not a quote, then the system returns to step 252A to either terminate the operation or go on to check the next segment. If the function requested is quote, then the system branches to step 264A to store a quote indication at the KIJA address in area 24 of the control portion of memory for the given device.
If during step 256A it is determined that the function stored in the first segment is not quote, the function must be MIS since the only three types of functions in the system are common, quote and MIS, and a determination has been made that the segment is neither common nor quote. Under these conditions, the system branches from step 260A to step 266A to determine if the function key depressed was the MIS function key 120. If this key was not depressed, then the system returns to step 252A to either return to the normal system job control program or go on to check the next segment. If the requested function was MIS then the system branches to step 268A to store an MIS indication at the KIJA address.
From step 264A or step 268A the system branches to step 270A. During this step a pointer is stored to indicate the segment in which the entry marker is to be positioned. The system then branches to step 272A during which segment two is indicated in the last two-bit positions of the register storing the current mode word as being the first segment to be checked the next time that step 248 is performed.
As indicated previously, except for the circle numerals 1 and 2 in steps 270A and 272A respectively, the operations in boxes 254B and 254C are identical to those illustrated for box 254A. In box 254B the circled numbers would each be one greater, while a box 254C the number for step 270C would be a 3 and the number for step 272C a 1.
From step 272A, B or C, the sytem branches to step 274 during which a determination is made as to the memory address of the segment which will contain the entry marker. During step 276 the entry marker is moved to the home position in this segment, and during the following step 278 the determined new entry marker address is stored both in area 22 of the control portion 18B of memory and in the control word entry marker positions for the segment in which the entry marker is now positioned. The entry marker is also removed from the position in which it was previously located. When step 278 has been completed, the system returns to its normal job control program.
If during step 240 a determination is made that one of the mode keys 118 is depressed, the system branches from step 240 to step 280 (FIG. 14B). During step 280 the current mode word in area 26 of memory 18 for the given device is transferred to the previous mode word location. From FIG. 8A it is seen that this involves moving the word down one word position.
The next step in the operation (step 282) is to determine the new mode address. This is the address of the screen format word for the new mode which has been selected. During step 284 the determined new mode word is retrieved from storage, stored in MDR 94, and transferred from MDR 94 into the current mode word location for the given device.
Step 276, the next step in the operation, involves the determining and storing of the addresses of the display stack segment addresses for the new mode. These are the addresses of the display words in area 28 of memory for the given device for the new mode which has been selected.
From step 286 the system proceeds to step 288 during which the previous mode word in area 26 of memory is retrieved and stored in a register in the control unit. As will be seen shortly, this word is utilized to determine if any of the segments in the previous mode were storing quote information and to cause the address or addresses of these segments to be saved. The operations which are involved in performing this step (step 290) are identical for the three possible display segments and are therefore shown in detail only for the first segment. The first step in operation 290A, step 292A, is to determine from the previous mode word whether segment one is a quote segment. Step 292B (not shown) would determine whether segment two was a quote segment and step 292C (not shown) would determine whether segment three was a quote segment. If segment one is not a quote segment, then the system branches to step 292B. If segment one is a quote segment, the system branches to step 294A during which the first quote segment address is retrieved for this quote. During step 296A, the quote address save words in area 24 of memory for the given device are read out, and during step 298A the system tests to determine whether the address retrieved during step 294A is stored in one of the save address characters read-out during step 296A. If the quote address read out during step 294A is already saved in one of the save address positions of memory, then it need not be saved again and the system branches to step 292A. If the quote address determined during step 294A is not already saved, then the system branches to step 300A during which a clear save word is located. During step 302A the address determined during step 294A is stored in the clear save address determined during step 300A. The system then branches to step 292B to determine if the second segment contains a quote the address of which should be stored. When a determination is made either that there is no quote to be stored or that the quote has been stored, the system branches to the operations in box 290C to determine if segment three in the previous mode contains a quote the address of which should be stored. When the operations required by box 290C have been completed, the system branches to step 304 (FIG. 14C). During step 304 the addressed of the display stack segment addresses determined during step 286 are utilized to control the writing of the display words at these addresses into the display control word addresses in area 20 of the memory for the given device.
From step 304 the system branches to step 306. Step 306 is the first step in the operation which determines whether the segment addresses saved during operation 290 are to be utilized in the current mode. As indicated previously, if the segments are to be utilized in the current mode the segment must be cleared and updating of the segment inhibited. During step 306 the current mode word in area 26 of memory for the given device is retrieved and stored in a register in control unit 40. During step 308, the two quote save address words in area 24 of memory for the given device are retrieved and also stored in suitable registers in the control unit.
The system then proceeds to step 310 to determine if there is an address stored in the first save address position. If this position is clear, the system branches to step 312 to determine if the second save address is clear. If the second save address is also clear, then the operations for determining if a save address is to be cleared are not required and the system branches to step 314 (FIG. 14E), the first step of the next subroutine.
If the first save address is not clear, the system branches from step 310 to step 316. During this step a flag bit, which is the last bit in the control unit register storing the current mode word, is set to indicate that the first save word address has been looked at. If the second save address is found not to be clear during step 312, the system branches to step 318 during which the flag bit is reset to indicate that both save addresses have been looked at.
From step 316 or step 318 the system proceeds to step 320 during which a determination is made as to whether the segment at the address indicated in the save address word is employed in the new mode. This step is accomplished by comparing the address in the save address word against the segment addresses in the display control words in area 20 of memory 18 for the given display word. If the save address is not employed in the new mode, the system branches to step 322 during which a determination is made as to whether both save addresses have been looked at. If the flag bit is a one indicating that both save addresses have not been looked at, the system branches from step 322 to step 312. If the flag bit is zero indicating that both save addresses have been looked at, the system branches from step 322 to step 314 to commence the next subroutine.
If the segment at the save address is being used in the new mode, the system branches from step 320 to step 324. During this step the current mode word is utilized to determine if the segment in question is being utilized for quote in the new mode. If the segment is being utilized for quote in the new mode, then the address may continue to be saved and updated and the system returns to step 322. If the segment is not being utilized for quote in the new mode, the system branches from step 324 to step 326 during which the address stored in the save address position is cleared. During step 328 the A2 control bit (bit 6 in the second control word of FIG. 9) for the segment indicated by the save address is set to inhibit updates to the segment, and during step 330 the remainder of the segment is cleared. The system then returns to step 322 to determine if both save addresses have been looked at.
A sequence of operations has therefore just been described which permits the address of a quote-containing segment to be saved for updating if the segment is not being utilized for a non-quote function in the new mode and for clearing the segment and the save address if the segment is being utilized for a non-quote function (i.e. MIS) in the new mode.
Referring now to FIG. 14E, with step 314 the system starts the operations required to determine the segments in the selected mode which are chained together and to effect the chaining of the related segments. During step 314 a flag is set in the control unit registers storing the current mode word to indicate that all segments are common. This is a test flag which will be reset if the condition indicated thereby is not correct.
From step 314 the system branches to step 340. During this step the current mode word is checked to determine if the first segment is common. If the first segment is not common, the system branches from step 340 to step 342 (FIG. 14F). During step 342 the current mode word is checked to determine if the first segment is an MIS segment. If the first segment is not an MIS segment, it must be a quote segment since it has been previously determined (during step 340) that it is not a common segment. From previous discussion, it is apparent that a quote segment consists of two display segments. Thus, the first two segments must be chained together.
To accomplish this, the system branches from step 342 to step 344 during which the address of the first segment, as indicated by the display control word, is retrieved and stored in a suitable register in the control unit. During step 346, the values 000 and 001 are set up as the first and last display entry marker pointer bits in a suitable register in the control unit. These bits indicate that the first and second display segments are the first and last segments of the chain.
During step 348, the address of program step 350 (indicated as 13) is set up in a suitable register in the control unit as the return address for the pointer bit entry subroutine which starts with step 352 (FIG. 14D), and the system then branches to step 352.
During step 352 the entry marker address for the first segment in the chain (see FIG. 9) is stored in a suitable control unit register. The control unit then causes the display segment pointer portion of this word, bits 1-3 of the first character of this word, to be cleared (step 354) and the new value which would be the value set up as the first value during step 346, 000 in this instance, is stored in these bit positions (step 356). This latter operation may be accomplished by ORing the new bits with the 000 already stored in the position.
During step 358, the system tests to determine if the pointer bits have been stored for all segments (i.e., the pointer bit value entered is compared against the last display entry marker pointer bits stored in the CU register). If the last segment of the chain has not been reached, the segment address is incremented during step 360, the pointer value is incremented during step 362, and the system returns to step 354. It is noted that step 360 assumes chained segments are stored in successive segment addresses in memory 18. If the control unit cannot assure that chained segments will be set up in this way during mode setup, then incrementing step 360 would be replaced by a step wherein the next segment address is retrieved from the display control word in area 20 of memory for the given device. With only two segments chained together, the second time step 358 is reached, it generates an indication that the pointer bit has been stored in the final segment of the chain and the system branches to step 364. During step 364, the return word stored during step 348 is utilized to control the branching of the system to step 350 (FIG. 14F).
During step 360, the address of the first segment is again retrieved and stored in a suitable register and, during step 366 the address of the second segment is retrieved and stored in a register. During step 368 an address which causes a return to step 370 (indicated as 16) is set-up in a suitable register in the control unit. The system then branches to step 372 (FIG. 14D) which is the first step of the subroutine which stores the chaining bits.
During step 372 the address of the second control word in the first segment of the chain is stored. During the following step 374 the chaining bits in positions seven and eight of the second character of this word are set to indicate that the segment is the first segment of a chain. This is accomplished by setting bit eight to zero and bit seven to one.
The segment address is then incremented during step 376 (as with step 360 this assumes sequential segments in a chain). During step 378 the system checks to determine if the segment now being looked at is the final segment of the chain. If this segment is not the final segment of the chain, the system branches to step 380 during which the chaining bits of this segment are set-up to indicate that it is neither the first nor the last segment of a chian. This is accomplished by setting both chaining bits to one.
From step 380 the system returns to step 376, incrementing the segment indication to cause the next segment in the chain to be looked at. When during step 378 it is determined that the final segment of the chain has been reached, as would be the case for the first time step 378 is being performed when the step is entered from step 368, the system branches to step 382. During step 382 the chaining bits of the segment then being looked at are set up to indicate that it is the last segment. This is done by setting bit eight to one and bit seven to zero.
The system then retrieves the current mode word during step 384 and resets the all-segments-common flag which was set during step 314 (step 386). During the next step in the operation, step 388, the system retrieves the return address stored during step 368 and utilizes this stored address to return, in this instance, to step 370 (FIG. 14E).
The system may branch to step 370 either from step 340 when the first segment is determined as being common or from step 388. During step 370 the current mode word is tested to determine if the second segment is common. If the second segment is determined not to be common, the system branches to step 390 to determine if the second segment is an MIS segment. If the second segment is an MIS segment then the system branches to step 392 to determine if the third segment is an MIS segment. The determinations during steps 390 and 392 are made by use of the current mode word. If, during step 390, it is determined that the second segment is a quote rather than an MIS segment, or if, during step 392, it is determined that the third segment is not an MIS segment, then the system branches to step 394. It should be noted that under either of the conditions indicated above, the fourth and fifth segments are chained together but the chain does not extend beyond the fifth segment. During step 394 the address of the fourth segment is retrieved by use of the display control words in area 20 of memory and during the following step 396 the values 003 and 004 are set-up as the first and last entry marker pointer bits respectively. Step 396 is the equivalent to step 346 except that it is for the center group of segments rather than for the top group of segments. During step 398 the address of step 400 is set-up as a return address in a suitable control unit register and the system then branches to step 352 to cause the chain pointer bits to be recorded in the memory segments utilized for the display of the fourth and fifth display segments. When the recording of these pointer bits has been completed, the system branches from step 364 to step 400 during which the address of the fourth segment is retrieved and stored under control of display control words in area 20. During step 402 the memory address of the segment utilized to refresh the fifth display segment is retrieved and stored. During step 404, the address of step 406 (indicated as 17) is set-up as a return address in a suitable control unit register and the system then branches to step 372 (FIG. 14D) to record the chaining bits in the appropriate bit positions of the segments whose addresses were retrieved during steps 400 and 402. When step 388 is again reached, the system branches to step 406.
It may be seen that step 406 can also be reached, if during step 370, it is determined that the second segment is common. During step 406 the current mode word is utilized to determine whether the third segment is common. If the third segment is common, then the system branches to step 408 to determine if all segments are common. This is accomplished by checking the flag bit which was set during step 314 to determine if it has been reset. If the flat bit has not been reset, then all segments are common and the system branches to step 410 during which the display entry marker in area 22 of memory for the given device is cleared. This step is required since, with all segments common, there is no entry marker. From step 410 the system returns to its normal job control program.
If, during step 408, it is found that, as with for example the display shown in FIG. 1, at least one group of segments is not common, the system branches from step 408 to step 412. During step 412 the last two bits in the registers storing the current mode word are set to indicate the first segment as the first segment to be checked. The system then branches to step 348 (FIG. 14A). It will be remembered that this is the first step of the subroutine which is utilized to determine and store the locations of the entry marker both in area 22 of the device control area and in the entry marker control word (i.e., the first control word) of each segment utilized in the display. When the writing of the entry markers is completed, the required operations when a mode key is depressed are completed and the system returns to its job control program.
Returning now to FIG. 14F, it is seen that, if during step 342, it is determined that the second segment is an MIS segment, the system branches to step 414. During this step a determination is made as to whether the second segment is an MIS segment. If the second segment is not an MIS segment, then only segments one and two are chained together and the system branches to step 344. If the second group of segments (i.e., segments four and five) are MIS segments, then at least the first five segments of the display are to be chained together and the system branches to step 416 to determine if the third group of segments are also MIS segments. If the third group of segments are not MIS segments, then the operations required to chain together the first five segments are to be performed and the system branches to step 418. During step 418 the address of the first segment of the chain is retrieved. During step 420, 000 is set-up as the first display segment of the chain and 004 (i.e., the fifth segment) is set-up in a suitable CU register as the last display segment of the chain. The system then proceeds to step 422 where step 424 is set-up as a return address for the pointer-bit-generating subroutine. The system then branches to step 352 (FIG. 14D) to cause the pointer bits to be recorded in each of the five memory segments utilized to refresh the first five display segments. When this subroutine has been completed, the system returns to step 424 during which the first segment address is retrieved. During step 426 the fifth segment address, the address of the last segment in the chain, is retrieved and step 406 (indicated as 17) is set-up as the subroutine return address during step 428. The system then branches to step 372 (FIG. 14D) to cause the chaining bits for the five segments involved in the chain to be recorded.
If during step 416 it is determined that the third group of segments are also MIS segments, then a display of the type shown in FIG. 4 is to be generated with all eight segments of the display being chained together. Under these conditions, the system branches from step 416 to step 430. During step 430, the address of the memory segment utilized to refresh the first display segment is retrieved and during the following step 432, 000 and 007 are set-up as the first and last pointer bit numbers respectively. During step 434 the address of step 436 (indicated as 20) is set-up as the return address and the system then branches to the pointer bit generating subroutine starting with step 352. At the end of this subroutine, the system returns to step 436 to retrieve the first segment address. During the following step 438, the address of the memory segment utilized to refresh the eighth display is retrieved and during step 440 the address of step 408 (indicated as 18) is set-up as the return address for the chaining bit generating subroutine. The system then branches to the chaining bit generating subroutine starting with step 372.
There are two other possible chaining bit configurations. The first occurs when, during step 392 (FIG. 14E), it is determined that the third group of segments are MIS segments. Under these conditions a display of the general type shown in FIG. 3 is being generated and the last five segments, segments four through eight, are to be chained together. Under these conditions, the operations indicated in steps 492, 494, and 496 are performed before the system branches to the pointer bit generating subroutine. On returning from the pointer bit generating subroutine, the system performs steps 498, 500 and 502 before branching to the pointer bit generating subroutine. The return from the pointer bit generating subroutine is to step 408.
The final possible chaining condition occurs when, during step 406, it is determined that the third segment is not common. Under this condition the seventh and eighth segments are to be chained together. To accomplish this, the system branches from step 406 to perform the steps indicated in the boxes for steps 504, 506 and 508 before branching to the pointer bit generating subroutine. These steps are substantially the same as steps previously indicated and will not be described again in detail. On returning from the pointer bit generating subroutine, the system performs steps 510, 512 and 514 before branching to the chaining bit generating subroutine. Again these steps are substantially identical to steps previously described and will not be described in detail at this point. The return from the subroutine is again to step 408.
From the flow diagrams and descriptions provided above, it is believed that a programmer or logic designer ordinarily skilled in the art could provide software or hardware respectively for implementing the required functions. As indicated previously, these functions could be implemented either exclusively in hardware, exclusively in software, or in some combinations of hardware and software. The choice of a particular means of implementation would depend on various economic and other considerations and, except for where otherwise indicated, the specific means for implementing the functions do not form part of the present invention.
DETAILED DESCRIPTION OF CONTROL UNIT
In order to further assist one skilled in the art in utilizing the teachings of this invention, FIGS. 15A-15B illustrate, in block diagram form, control unit hardware suitable for use in control unit 40 for implementing most of the functions indicated above.
Referring now to FIG. 15B, it is seen that a signal on line 600 from input/output interface 142 (FIG. 6B) is connected as the information input to input decoder 602. Control unit 40 periodically scans each of the terminal devices 12A to determine if a key is depressed. When the control unit finds that a scanned keyboard has an input, this input is passed through a suitable interface for the device to input decoder 602. Since the control unit knows which device it is polling at the time the input is received, it knows the device which generated the input. The particular circuitry for generating the polled messages and for receiving the poll responses does not form part of the present invention and will not be described herein. Circuitry generally suitable for performing these functions is described in copending application Ser. No. 27,877 entitled "AUTOMATIC POLLING SYSTEMS" filed Apr. 13, 1970 on behalf of F. Gallagher, et al. and assigned to the assignee of the instant application.
Circuit 602 decodes the input character and generates an output on an appropriate one of four lines 604 if a mode key 118 is depressed, generates an output on line 606 if MIS key 120 is depressed, generates an output on line 608 if quote key 122 is depressed, generates an output on an appropriate one of the lines 610 if one of the editing keys 114, 130, 132, 134, 136, 138, etc. is depressed, generates an output on the appropriate line or combination of lines 612 if a data entry key 110 or 112 is depressed, generates an output on line 614 if mode set-up request key 124 is depressed, and generates an output on line 616 if mode set-up transmit key 126 is depressed. Mode select lines 604 are ORed together in gate 618. A signal thus appears on output line 620 from OR gate 618 whenever a mode select operation is being performed. MIS and quote lines 606 and 608 are the inputs to OR gate 622. A signal thus appears on output line 624 from this OR gate when a function key has been depressed. Editing lines 610 and data entry lines 612 are the inputs to OR gate 626. A signal thus appears on editing or data entry output line 628 from OR gate 626 when either a data entry or an editing function is being performed.
Before describing the manner in which the circuit of FIGS. 15A-15B operates to perform the various functions required of it, reference should be made to directories 630. These are a group of circuits in which are stored the addresses in memory 18 at which various information for each of the devices is stored. Thus, directory 631 stores the address of the save address word (area 24) for each device. Directory 632 stores the addresses of the segment address stacks (i.e., the mode display words in area 28) for each device. Directory 633 stores the addresses of the display control words in area 20 of memory. Directory 634 stores the addresses in memory of the previous mode words in areas 26 of memory, directory 635 the addresses of the mode words or screen format words in areas 26 of memory, and directory 636 the address of the current mode word in this area of memory. Directory 637 stores the addresses of the entry marker words in area 22 for each of the devices. One input to each of the directories is a device clock on line 640 which serves as the address input to each of the directories. Each directory is energized to generate an output when it receives signals of both upper and lower inputs or, for the four directories which have center inputs, when the center input line is energized. Suitable gating circuitry is provided within each directory to implement the above.
Assume initially that the input to decoder 602 is an editing or data entry input. From FIG. 10B it is seen that the first step in the operation under these conditions is to determine the control area address for the device and to read the current mode word, etc., into the control unit. This is accomplished by applying the signal on editing or data entry line 628 through OR gate 642 and line 644 to one of the conditioning inputs of current mode word directory 636 and by also connecting line 628 as one of the conditioning inputs to entry marker word directory 637. For purposes of the following discussion the control unit will be assumed to contain a clock which starts running when an input is received, stops when the operations required for the input are completed, and generates clocks at a rate which is synchronous with the rate at which memory 18 may be accessed. It should be noted that once approximately every ten cycles of the memory, access to the memory will be required in order to refresh the display. Some suitable means, such as for example a suppressing of the clock circuit during that time interval, will be provided. This means does not specifically form part of the present invention and will not be described further.
At C1 time of the control unit clock a signal appears on line 646 fully conditioning the current mode word directory to apply the current mode address for the device indicated on line 640 through lines 648 OR gate 650 (FIG. 15A) and lines 38 to address memory 18 causing the desired word to be read-out into MDR 94 (FIG. 6A). At C1 time of the control unit clock a signal also appears on line 652 conditioning gate 654 (FIG. 15A) to pass the contents of MDR on line 95 through lines 656 to mode word register 658. At C2 clock time of the CU, a signal appears on line 660 fully conditioning entry marker word directory 637 to generate an address output on lines 648 which are likewise applied to cause the entry marker word for the service-requesting device to be stored in MDR 94. The C2 clock signal is also applied to line 662 (FIG. 15B) to condition gates 664 to pass the entry marker data on lines 95 at this time through lines 666, OR gates 668, and lines 670 to be stored in entry marker or save address register 672. The operations required by step 154 are in this manner effected.
The decoding of the function, step 156, is accomplished in decoder 602. The next step in the operation, step 158, is performed by valid function test circuit 674 (FIG. 15B). The inputs to this circuit are the decoder output lines 610 and 612 indicating the function to be performed, output lines 676 from mode word register 658, and output lines 678 from entry marker register 672. Circuit 674 assures that, for example, an attempt is not made to change a common segment. If the requested function is invalid, nothing further happens (step 160 of FIG. 10B).
If circuit 674 determines that the requested function is valid, it applies a signal through line 690 to execution unit 692. Execution unit 692 also receives inputs on lines 610 and 612 from decoder 602, on lines 678 from EM register 672 and from MDR 94 through lines 95. When required, execution unit 692 may request information by sending an address signal through line 694 and OR gate 650 to address the memory 18 or a signal on line 694 may be utilized to cause information generated by the execution unit to be stored in memory. The execution unit passes such information through lines 696 OR gates 688 and lines 97 to the MDR. One of the functions of execution 692 is to update the entry marker and to store the updated entry marker in area 22 of the appropriate control segment 18B, etc. Execution unit 692 thus has outputs on lines 698 which are applied through OR gates 668 and lines 670 to cause updated entry markers to be stored in register 672. At suitable times, these entry marker addresses are applied through lines 678 to gate 700. Gate 700 is conditioned at these times by a signal from the execution unit on line 702 which is passed through OR gate 704 and line 706 to the conditioning input of gate 700. The outputs from gate 700 are applied through lines 708 and OR gate 688 to the MDR. The various functions described above for execution unit 692 implement the functions 162-170 shown in FIG. 10B.
Assume next that a function key, MIS or quote, is depressed on one of the keyboards. Under these conditions, OR gate 622 is generating an output on line 624 which is applied through OR gate 642 as one of the conditioning inputs to current mode word directory 636. At C1 time this directory is fully conditioned to generate an address output which causes, in the manner previously indicated, the current mode word to be stored in register 658. The first step, step 176, indicated in FIG. 10A, is in this manner accomplished. The second step (step 178) in the operation, determining the function, is performed by decoder 602.
The next two steps in the operation, steps 180 and 182, are performed by function-mode entry marker position determining circuit 712 (FIG. 15A). Two of the inputs to this circuit are MIS and quote lines 606 and 608. The current mode word in register 658 has its first six bits applied to segment test circuit 714. This circuit generates outputs on an appropriate one or more of the lines 715 depending on whether segment groups one, two or three are storing quote type information, and outputs on appropriate one or more of the lines 716 depending on whether one or more of the segment groups contains common type information. The lines 715 and 716 are two additional sets of inputs to circuit 712. The last two bits in register 658 at this time indicate the first segment to be checked during this operation. These bits are applied through lines 718 to first-segment-to-check decode circuit 720. The output from circuit 720 is applied through lines 722 as another input to circuit 712. MDR output line 95 is another input to circuit 712. With a function key depression, these are the only inputs required to circuit 712. An additional input to be discussed later is utilized when the circuit is performing entry marker position determinations for a mode key depression.
From the inputs applied thereto, circuit 712 determines the segment having the desired function and the entry marker position for this segment. The address in memory 18 of the segment is obtained by applying a signal through line 723. OR gate 725 and line 727 to access the display control words for the device. The words are applied to circuit 712 through lines 95. The circuit then generates outputs on lines 724 which are applied through OR gates 668 to store the desired entry marker address in register 672. The final step in the operation involves an output from circuit 712 on line 726 which causes the address at which the entry marker address is to be stored to be read-out through OR gate 650 to address memory 18, and a signal on line 728 which is passed through OR gate 704 to condition gate 700 to pass the entry marker address in register 672 through OR gate 688 to the MDR. The required entry marker repositioning is in this manner effected.
Assume now that one of the mode keys 118 on a keyboard 16 is depressed. Under these conditions, the signal on mode line 620 is applied through OR gate 642 at C1 time to fully condition the current mode word directory to apply the address of the current mode word to the memory address circuit. This causes the current mode word to be read-out into MDR 94 and also causes this word to be stored in register 658 in the manner previously indicated. The reading of the current mode word into register 658 has no effect at this time. The C1 clock pulse is delayed by half a clock time and then applied through line 740 as one of the conditioning inputs to previous mode word directory 634. The signal on line 620 fully conditions directory 634 to apply the address of the previous mode word to the memory address register at this time. This causes the current mode word stored in the MDR to be written back into the previous mode word position. Step 280 of FIG. 14B is in this manner accomplished.
At C3 clock time a signal is applied through line 742 to one of the conditioning inputs of mode word directory 635. The other conditioning input to this directory is the energized one of the lines 604. In addition to serving as a conditioning input, the line 604 also serves as an addressing input to mode word directory 635. The address of the desired mode word is thus applied through lines 648 and OR gate 650 to the memory address circuit. Step 282 of FIG. 14B is accomplished in this manner. The C3 clock is delayed by half a clock time and applied through lines 646 to cause the current mode word address to be applied to the memory address circuit 32. The mode word which was read into MDR at C3 time is thus stored in the current mode word position of memory 18. Step 284 of FIG. 14B is thus accomplished.
At clock times C4, C5, C6 and C7 conditioning inputs are applied to the segment address stack directory 632, the additional addressing and conditioning inputs to this stack being derived from the energized one of the lines 604. The outputs from directory 632 are the successive addresses for the four mode display words of the new selected mode. These words are read in succession into the MDR 94. Each of the clock pulses C4-C7 is delayed by half a clock time and applied through line 746 as a conditioning input to display control word directory 633. This directory is fully conditioned by the signal on line 620 at this time. Thus, each of the mode display words which is read into the MDR is stored in the corresponding word position of the display control word area 20 for the given device. Steps 286 and 304 of FIGS. 14B and 14C are in this manner accomplished.
At C8 time a signal is again applied to line 740 causing the previous mode word for the device to be read-out into the MDR. The C8 clock signal is also applied through line 652 to condition gate 654 to pass the contents of MDR to mode word register 658. Step 288 of FIG. 14B is thus accomplished.
During C9 time a signal is applied through line 748 as one conditioning input to save word directory 631. The signal on mode line 620 fully conditions this directory to pass the address of the save word for the device to memory address circuit 32. At C9 time a signal also appears on line 662 conditioning gate 664 to pass the word at the same address, which has been read-out into the MDR, through OR gate 668 to entry marker or save address register 672.
The contents of register 672 on lines 678 are connected as one set of inputs to test-for-quote-in-segment-and-save-quote-address circuit 750 (FIG. 15A). Another set of inputs to this circuit are the three quote output lines 715 from segment test circuit 714. One or more of these lines will be energized depending on whether quote type segment groups are indicated as having been contained in the previous mode. Circuit 750 is energized by a C10 clock signal on line 752. Circuit 750 performs the functions indicated within the boxes 290A, 290B and 290C in FIG. 14B. It thus determines if any of the segment groups in the previous mode were quote segments, determines if the address such as the memory address for the quote segment has previously been stored, and stores the address through lines 754 and OR gate 668 in save register 672 if the address has not previously been stored. Current segment addresses required for making some of the above determinations are obtained through lines 95 in response to memory access requests applied through line 755, OR gate 725 and line 727 to Display Control Word directory 633.
At C11 time signals again appear on lines 646 and 652 causing the current mode word to be stored in mode word register 658 in the manner previously described. Step 306 of FIG. 14C is in this manner accomplished. Since the save words were stored in register 672 during the previous operation, step 308 has already been performed. The save address in register 672 is applied through lines 678 as one set of inputs to test-for-segment-use-in-new-mode circuit 756 (FIG. 15A). Quote lines 715 are a second set of inputs to circuit 756. A C12 signal on line 758 conditions circuit 756 to perform the functions 310-330 indicated in FIG. 14C. Basically, this circuit determines whether the segment at the save address is being utilized in the new mode for a non-quote function. If the saved address is being used in the new mode for a non-quote function, circuit 756 generates an output on line 760 which clears the save address. Circuit 756 also generates outputs on lines 762 and 764 which are effective to cause the A2 bit for the segment to be marked to inhibit updating of the segment and to clear the data stored in the segment. If the memory does not have a segment clear capability, the segment clear operation may be effected by successively addressing the words of the segment and writing zeros into these words from a cleared MDR. As with circuit 750, required segment addresses are obtained by circuit 756 through lines 95 in response to address requests on line 765. Line 765 is connected through OR gate 725 to access Display Control Word directory 765. At C13 time a signal appears on line 748 causing the save word address in memory to be accessed and a signal appears on line 766 which signal is passed through OR gate 704 to condition gate 700 to pass the save address information in register 672 to MDR for writing into the accessed save address position.
At the beginning of C14 time the current mode word is stored in register 658. This word is applied to segment test circuit 714. The resulting outputs on lines 715 and 716 are applied as inputs to first and last segment of chain determining circuit 770. At C14 time a signal is applied through line 772 and OR gate 774 to condition circuit 770 to make the first and last segment of chain determinations required starting with step 340 of FIG. 14E. This circuit generates outputs on line 776 to address memory for required information and receives the information from MDR over lines 95. The information determined by circuit 770 is applied through lines 780 to be utilized by pointer bits writing circuit 782 and chaining bits writing circuit 784. Pointer bits writing circuit 782 performs the pointer bit writing function of subroutine steps 352-364 (FIG. 14D) while circuit 784 performs the chaining bits writing function of steps 372-388 (FIG. 14D). When circuit 770 has set up a first chain, it generates an output on line 786 which energizes circuit 782. Circuit 782 generates addressing outputs on lines 788 to permit the storage of pointer bit information appearing on lines 790 in memory 18. When circuit 782 has completed its function, it generates an output on line 792 which energizes circuit 784 to perform its functions. This circuit generates addressing outputs on lines 794 which cause chaining bit information appearing on lines 796 to be stored in memory. When circuit 784 has completed its function, it generates an output on line 796 which is applied as one input to AND gates 798 and 800. If all eight segments have not yet been checked, there is no signal on output line 802 from circuit 770 at this time and invertor 804 generates an output which fully conditions AND gate 798 to generate an output on line 806. This signal is applied through OR gate 774 to condition circuit 770 to determine the first and last segments of a new chain.
When all segments in the new mode have been checked, a signal appears on line 802 which, when a signal also appears on line 796, fully conditions AND gate 800 to generate an output on line 808. The signal on line 808 is applied to the last two bit positions of the current mode word stored in mode word register 658 to set these bits to point to the first segment. The signal on line 808 is also applied to enable circuit 712 to determine entry marker positions and store entry marker positions for the new mode. Circuit 712 operates to perform these functions in the same way in which it operated when a function key was depressed. When this operation has been completed, all functions required when a mode key has been depressed are finished and the circuit is ready to accept a new input.
When a mode set-up request key 124 is depressed, decoder 606 generates an output on line 614 which conditions mode set-up mask generator 820 (FIG. 15B) to generate outputs on lines 822 which are passed through OR gate 688 to be stored in memory 18. Circuit 820 need not generate address outputs since the mask is stored at positions indicated by the device entry marker. Since, when the masks are filled in, a different mask exist for each device, a mask store 824 is provided which receives a device clock over line 826 causing it to supply the proper mask to the mask generator at any given time.
When the mask has been properly filled in and is visually verified, the operator depresses mode set-up transmit key 126. This causes decoder 602 to generate an output on MSU transmit line 616 which signal is applied as a conditioning input to MSU verify circuit 830 (FIG. 15A). This circuit or other circuitry within the system causes the generated mask to be read-out and applied to circuit 830 over lines 95. Circuit 830 checks to determine that all mode set-up rules have been followed and generates an output on line 832 if these rules have been followed. If the mask is invalid, circuit 830 generates an output on line 834 which triggers error message generator 836 to generate an error message on lines 838. The signals on lines 838 are applied through OR gate 688 to be stored in memory 18 at addresses indicated on lines 840.
The verified signal on line 832 conditions circuit 842 to generate mode word and segment address stacks for the new mode. This is a relatively complex circuit which has many inputs and outputs only a few of which are shown in the figure. Outputs from this circuit are stored in memory through lines 844 and are also stored in mode word directory 635 through lines 846 and in segment address stack directory 632 through lines 848.
A circuit has thus been provided for controlling the generation and display of information on segmented display devices in a variety of different modes. While for the preferred embodiment of the invention described above, each display has been provided with eight segments, and it has been possible to display up to three different types of information on these displays simultaneously, it is apparent that these values are merely illustrative and that a greater or lesser number of segments and/or different types of display might be available with each device while still remaining within the scope of the invention. Similarly, the variety of types of information available for display may be greater necessitating, for example, more bits in each of the mode words to distinguish the type of information being displayed in each segment and the number of different modes available at each display device might also be varied.
Various alternatives in the hardware and software of the invention have been indicated throughout the discussion and, as has also been previously been indicated, the mix between hardware and software may very for different applications of the invention. Further, while a single memory 18 has been shown in FIG. 6A for storing both display and control information, separate register or storage devices might be provided for each of these functions. Directories 630 might also be stored in a selected area of memory 18 or in a separate device as shown. Thus, while the invention has been particularly shown and described above with reference to a preferred embodiment of the invention, it is apparent that the foregoing and other changes in form and details may be made therein by those skilled in the art without departing from the spirit and scope of the invention.