Description:
BACKGROUND OF THE INVENTION
This invention relates to an identification circuit and more particularly an identification circuit for use in a remote unit which must identify itself to other remote units or to a central unit.
From the vast worldwide teletype network to a simple centralized terminal network, it sometimes is necessary that each machine identify itself whenever it is communicating with another machine or with the central unit. In the past, teletype machines have been primarily mechanical devices and the identification message transmission has been accomplished primarily by mechanical means. These mechanical means include a cylinder device having 21 rows of prongs extending therefrom where some of the prongs have been removed in a programmed manner. Upon command, the cylinder device turns one revolution and the prongs interact with detector means which detect the programmed identification message. The message is then transmitted out by the teletype machine. Because an entire revolution of the cylinder is necessary, the transmitted message will always be 21 characters long, although in many instances, only a few characters of information need be sent. Further, it becomes very difficult to reprogram the cylinder if this ever becomes necessary.
Modern technology has provided the nonmechanical teletype machines, such as the thermal printing device now in wide use. For these primarily nonmechanical devices, it is desirable to avoid the use of the mechanical cylinder described above. Further it is desirable to be able to provide an identification circuit which can be easily programmed and which can be easly reprogrammed, if necessary, directly at the point of use.
SUMMARY OF THE INVENTION
In accordance with one preferred embodiment of this invention, there is provided identifying means associated with a remote unit for transmitting a coded identification signal identifying the remote unit. The coded signal includes a given number of N bit characters where the given number is between 1 and M. The identifying means comprises matrix means having N+1 columns and M rows. There is an intersection of each row and each column. Electrical connections are capable of being made between any of these intersections to cause a signal applied to a row to appear on a column. A first sub-matrix of N columns and M rows is assigned to develope the coded identifying signal and a second sub-matrix of one column and M rows is assigned to develope a stop signal. The identifying means further includes logic means for applying a signal to each of the matrix rows, one at a time. It also includes first means for providing as the coded identification signal the signals electrically appearing on the N columns of the first sub-matrix and second means responsive to one of either a signal appearing on to the one column of the second sub-matrix or Mth row of said matrix for providing a stop signal. The logic means further includes means responsive to the stop signal for causing the signal applied to the matrix rows to cease upon the occurrence of the stop signal .
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a block diagram of a remote unit including the identification circuit of this invention;
FIGS. 2A, 2B and 2C show respective circuit blocks used in the block diagram showing the indentification circuit;
FIG. 3 is a block diagram of the identification circuit of the present invention;
FIG. 4 shows a series of waveforms useful in understanding the operation of the identification circuit shown in FIG. 3;
FIG. 5 is a perspective view of the portion of the printed circuit board having the matrix of the identification circuit thereon; and
FIG. 6 is a plan view of the printed wiring on the printed circuit board of FIG. 5.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 1, a block diagram of a remote unit, such as data terminal 10, is shown. Data terminal 10 includes keyboard 12, keyboard interface logic 14, printer 16, output circuit 18 and identification circuit 20. Keyboard 12 may be a state of the art alpha-numeric keyboard which provides a seven bit code when one of the keys thereof (not shown) is depressed. A code such as ASCII may be employed for this purpose. In addition keyboard 12 will include a SEND key which may be depressed prior to depressing the keys representing the message.
The seven bit code, representing the depressed key, is applied, in parallel, over wires 22 to keyboard interface logic 14, where it is processed by having a parity bit inserted and is serially sent over wire 24 to output circuit 18. Output circuit 18 then transmits the signal through wire 28 to the designated destination point, which may be another terminal (not shown) or a central unit (not shown). The signal from keyboard interface logic 14 is also sent in parallel over lines 26 (only one of which is shown) to printer 16 for causing the printing of a character manifested by the signal.
It is also possible for the central unit to poll data terminal 10. This may be accomplished by the central unit sending an ENQUIRY signal over line 28 to output circuit 18. Logic included within printer 16 decodes the ENQUIRY signal and provides an ENQUIRY flag signal to line 30 which is coupled to identification circuit 20.
Whenever the SEND key of keyboard 12 is depreesed, a SEND signal will be applied through line 32 to identification circuit 20. Whenever identification circuit 20 receives either the SEND signal or the ENQUIRY flag signal, it becomes active and transmits a logic 1 ENQ signal and a logic 1 PT IN signal to keyboard interface logic 14. After a short time it transmits the first seven bit character of the identification signal on lines B1 through B7 to keyboard interface logic 14 and a short time later, a logic 1 ENQ STB pulse signal is sent to keyboard interface logic 14. The seven bit code is operated upon in keyboard interface logic 14 in the same manner as the seven bit code from keyboard 12 and sent over lines 24 and 26 to the output circuit 18 and printer 16 respectively. In response to the first character being sent to keyboard interface logic 14, and RST signal is sent to identification circuit 20. The RST signal causes the second character of the identification signal and another ENQ STB pulse to be transmitted over lines B1 through B7. It should be noted that during this time, a clock signal is also being sent from keyboard interface logic 14 to identification circuit 20. After the entire identification message has been sent from identification circuit 20 to keyboard interface logic 14, the logic 1 ENQ and PT IN signals return to logic 0 and normal operation resumes.
Referring now to FIG. 2A, thre is shown a block 40 which is used to represent a flip-flop (F--F) circuit in FIG. 3. Flip-flop 40 has five inputs labeled S, J, C, K and R and two outputs labeled Q and Q. In the reset state of flip-flop 40, the Q output is at logic 0 (zero volts or ground potential) and the Q output is at logic 1 (positive potential). Whenever the signal applied to the S input of flip-flop 40 goes from logic 1 to logic 0, the state of flip-flop 40 changes to the set state if not already there; that is, the Q output becomes logic 1 and the Q output becomes logic 0. Similarly, when the signal applied to the R input goes from logic 1 to logic 0, the state of flip-flop 40 assumes the reset state, if not already there; that is, the Q output becomes logic 0 and the Q output becomes logic 1. It should be noted that both the S and the R inputs to flip-flop 40 are independent of any clock signal applied to flip-flop 40.
When a clock signal applied to the C input of flip-flop 40 becomes logic 1 while the J input is logic 1, flip-flop 40 will assume a set state on the rising edge of the clock pulse. Similarly, if the K input is logic 0, flip-flop 40 will assume the reset state upon the leading edge of the logic 1 clock pulse.
Referring now to FIG. 2B, the block diagram of the monostable multivibrator (M. M. V.) 42 is shown. Monostable multivibrator 42 includes S and I inputs and Q and Q outputs. Whenever a logic 1 signal is applied to the S input of monostable multivibrator 42, the Q output goes from logic 0 to logic 1 for a predetermined fixed time and then returns to logic 0 and Q output goes from logic 1 to logic 0 for that fixed time and then returns to logic 1. Monostable multivibrator 42 can be selected to respond to either the leading or trailing edge of the logic 1 signal. However if a logic 0 is applied to the I input of monostable multivibrator 42, any change at the S input is ignored. The fixed time of the pulse at the Q output or the Q output is controlled by the value of resistance (not shown) and capacitance (not shown) which is coupled to monostable multivibrator 42.
Referring now to FIG. 2C, a latch circuit 44 is shown which has S and R inputs and Q and Q outputs. Whenever a signal goes from logic 0 to logic 1 at the S input, the Q output will simlarly go from logic 0 to logic 1, if not already there. Similarly, whenever the voltage at the R input goes from logic 0 to logic 1, the Q output goes from logic 1 to logic 0, if not already there.
Referring now to FIGS. 3 and 4, a detailed block diagram of identification circuit 20 and waveforms useful in understanding that block diagram are shown. The heart of identification circuit 20 is a matrix 46 which has 21 rows labeled 1, 2, 3, . . . i . . . and 21 and eight columns labeled A, B, . . . G, H. It is possible to have an electrical connection between any row and column intersection by inserting a conductor between a coupling terminal connected to a row, such as terminal 48, and a coupling terminal coupled to a column, such as terminal 50. The conductor may be a diode which is poled to conduct from the column terminal 50 to the row terminal 48, such as diode 52. Each of the twenty-one rows represent one character and each of the first seven columns A through G represent the individual bits of the character. The eighth column H is assigned to a stop bit, and a diode, such as diode 54, will couple the eighth column to the row manifesting the last character of the identification code.
Normally each row and each column are at a positive potential. However during the time the identification code is being transmitted, the rows are set to ground potential, one at a time, so any column of the matrix coupled through a diode to the ground potential row assumes ground potential. This ground potential is detected by the inverter gates 56, 58 . . . 59 coupled to the columns A through G and inverted to represent a logic 1 bit. In this manner whenever a logic 1 is desired, a diode is inserted, and whenever a logic 0 is desired, no diode is inserted.
The logic circuitry associated with matrix 46 will now be described with reference being invited to the waveforms shown in FIG. 4 to more easily follow the described operation. Upon application of power to identification circuit 20, upsequencing circuit 60 applies a 100 millisecond logic 0 reset pulse to the R inputs of printer inhibit flip-flop 62 and I. D. inhibit flip-flop 64 and through NAND gate 66 and inverter 68 to the R input of I. D. start flip-flop 70. As previously explained, a logic 0 applied to the R input of a flip-flop unconditionally resets the flip-flop and thus flip-flops 62, 64 and 70 are all reset. This is the initial condition which allows identification circuit 20 to properly respond to either the SEND signal or ENQUIRY flag signal.
The SEND signal and ENQUIRY flag signal are applied over lines 32 and 30 respectively to the two inputs of OR gate 72. The output of OR gate 72 is applied to the S input of I. D. state monostable multivibrator 74. The IDSM signal is taken from the Q output of I. D. start monostable multivibrator 74 and applied to the C input of I. D. start flip-flop 70. The IDSM signal is a 50 millisecond logic 0 pulse, and has a leading edge at the time of the leading edge of the ENQUIRY flag signal or SEND signal.
The trailing (rising) edge of the IDSM logic 0 pulse causes ID start flip-flop 70 to become set because the J and K inputs thereof are at logic 1, or +V volts. At this time the IDSF signal at the Q output becomes logic 1 and the IDSF signal at the Q output becomes logic 0. The logic 0 IDSF signal is applied to an enable (E) input of shift register 76 which will be described in detail hereinafter. The IDSF signal is applied to the S input of S. R. load monostable multivibrator 78 and to the R input of ENQ latch 80. The leading edge of the IDSF signal applied to S. R. load monostable multivibrator 78 causes the SRL signal at the Q output thereof to become logic 0 for approximately 50 microseconds. The SRL signal is applied to the S input of ENQ latch 80 and the load (L) input of shift register 76.
The leading edge of the SRL signal sets ENQ latch 80, thereby causing the ENQ signal at the Q output thereof to become logic 1 and the ENQ signal at the Q output thereof to become logic 0. The logic 0 ENQ signal is applied to the S input of printer inhibit flip-flop 62, thereby setting it and causing the Q output thereof to become logic 0. This is the PT IN signal which applied to keyboard interface logic 14 in FIG. 1 to inhibit the printer from printing the identification code. In certain situations it may be desirable to have the printer print the identification code and in this event the PT IN signal may be disconnected from keyboard interface logic 14.
Also, the ENQ signal from ENQ latch 80 is applied to keyboard interface 14 shown in FIG. 1 to indicate that identification circuit 20 will be transmitting information thereto and to cause the keys on keyboard 12 to be locked out. This condition will remain so long as the ENQ signal is logic 1. During this time the RST signal from keyboard interface logic 14 is logic 0. This signal is applied through inverter 81, where it becomes a logic 1 and then is applied to one input of NAND gate 82. The ENQ signal from ENQ latch 80 is applied to the other input of NAND gate 82. At the time the ENQ signal becomes logic 1, the output of NAND gate 82 becomes logic 0. This causes the S. R. clock monostable multivibrator 84 to be triggered, causing the Q ouput thereof, or SRC signal, to become logic 1 for approximately three microseconds and the Q output, or SRC signal, to become logic 0 for about three microseconds. The SRC signal is applied to the clock (C) input of shift register 76 and this causes a logic 0 to be applied from the first stage of shift register 76 to the first row of matrix 46 as will be explained in more detail hereinafter. The SRC signal is applied through twenty microsecond delay circuit 86 to ENQ STB monostable multi-vibrator 88, causing a 50 microsecond logic 0 pulse to be provided from the Q output thereof as the ENQ STB signal. This signal is applied to keyboard interface logic 14.
Shift register 76 is a twenty-one flip-flop stage shift register which has the Q output of each stage coupled to a respective one of twenty-one rows of matrix 46. When the IDSF signal applied to the enable input of shift register 76 becomes logic 0 shift register 76 is ready to be initially loaded. When the SRL signal applied to the load (L) input of shift register 76 becomes logic 0, and the first SRC logic 1 signal is applied to the clock input of shift register 76 the first stage of shift register 76 becomes reset and the second through twenty-first stages become set. Thus, after the SRC signal returns to logic 0, the first stage stores a logic 0 bit and the remaining stages store logic 1 bits. On each subsequent logic 1 SRC clock pulse, the logic 0 bit is shifted one stage towards the twenty-first stage. Thus after the first SRC logic 1 pulse, the first row of matrix 46 is at logic 0, or 0 volts.
Because only the Gth column of matrix 46 is coupled to the first row through diode 52, the B7 signal from the output of inverter 59 will be logic 1 and the B1 through B6 signals will be logic 0. The B1 through B7 signals are applied to the keyboard interface 14 shown in FIG. 1. After a delay caused by a delay circuit 86, the logic 0 ENQ STB signal is also applied to keyboard interface logic 14. During the time the ENQ STB signal is logic 0, the state of B1 through B7 signals is sampled in keyboard interface logic 14 and processed for transmission as the first identification code character.
After this occurs, keyboard interface logic 14 transmits a logic 1 RST signal to identification circuit 20. This signal is applied through inverter 81 and causes a logic 0 signal to be applied to NAND gate 82. This, in turn, causes the output of NAND gate 82 to become logic 1 for the duration of the RST signal. When the output from NAND gate 82 returns to logic 0, S. R. clock monostable multivibrator 84 is again triggered and a second logic 1 SRC pulse signal is provided to the clock input of shift register 76. This causes the second state to become reset, all others being set, thereby causing the logic 0 to be applied to the second row of matrix 46. Again the SRC signal is delayed by delay circuit 86 and the ENQ STB signal is transmitted to keyboard interface logic 14 and the state of B1 through B7 signals is sampled. This represents the second character of the identification code signal.
The output of inverter 81 is also applied to the S input of I. D. inhibit flip-flop 64 and one input of NAND gate 90. The other input of NAND gate 90 is coupled to the clock signal from keyboard interface logic 14. The duration of the RST signal is approximately one clock time. The leading edge of the logic 0 signal applied to the S input of I. D. inhibit flip-flop 64 causes it to assume the set state. It will remain set until the first clock pulse after the logic 0 at the S input is removed because the J and K inputs therof are at logic 0 (grounded). Thus, the ID IN signal at the Q output of I. D. inhibit flip-flop 64 becomes logic 0 for two clock times. This logic 0 signal is applied to the inhibit input of I. D. start monostable multivibrator 74 to inhibit it from processing any further SEND or ENQUIRY signals during the time a character is being sent to keyboard interface logic 14. The ID IN signal is also applied to the clock input of printer inhibit flip-flop 62 and the J and K inputs thereof are set at logic 0.
When the keyboard interface logic 14 receives the second ENQ STB signal it sends another RST signal to interface circuit 20 and the same events just described occur again. This continues until just prior to shift register 76 applying a logic 0 signal to the ith row of matrix 46. Diode 54 connects the ith row to the Hth column. As previously explained, the Hth column of matrix 46 is assigned to a stop bit that is diode 54 placed to connect the Hth column to the ith row when the ith row contains the last character of the identification code. This causes the Hth column of matrix 46 to become logic 0 when a logic 0 is applied to the ith row.
The Hth column of matrix 46 is coupled to one input of NAND gate 92, and the other input of NAND gate 92 is coupled to the twenty-first row of matrix 46. Normally both of the inputs to NAND gate 92 are logic 1, so the output thereof, which is the STOP signal, is logic 0. However when the Hth column becomes logic 0, the output of NAND gate 92, and thus, the STOP signal, becomes logic 1. The STOP signal is applied as one input to NAND gate 94 and the second input of NAND gate 94 is coupled to the RST signal. When both the STOP signal and RST signal are logic 1, the output of NAND gate 94, which is the RST. STOP signal, becomes logic 0. The RST. STOP is applied to one input of NAND gate 66, the other input thereof being logic 1 from upsequencing circuit 60. The logic 0 RST. STOP signal causes the output of NAND gate 66 to become logic 1 and this is inverted to logic 0 at the output of inverter 68. The logic 0 from inverter 68 is applied to the R input of I. D. start flip-flop 70 to reset it and cause the IDSF signal to become logic 0 and the IDSF signal to become logic 1. This, in turn, causes the ENQ latch 80 to be reset and the ENQ signal becomes logic 0 and the ENQ signal becomes logic 1. The logic 1 ENQ thus allows the printer inhibit flip-flop 62 to be reset at the trailing edge of next ID IN logic 0 signal from I. D. inhibit flip-flop 64. The logic 0 ENQ signal indicates to keyboard interface logic 14 that identification circuit 20 is finished sending the ientification code.
It should be noted that the twenty-first stage output of shift register 76 is coupled to the input of the first stage thereof. This is provided so that, if NAND gate 92 does not sense the logic 0 being applied to either the Hth column or the twenty-first row, the logic 0 is recirculated. In this manner, the logic 0 from shift register 76 is never lost.
Reference is now made to FIGS. 5 and 6 in which FIG. 5 shows a perspective view of a portion of printed circuit board 100 upon which identification circuit 20 may be constructed and specifically that portion having matrix 46 thereon and FIG. 6 shows a top plan view of printed circuit board 100 without various elements affixed thereto. Printed circuit board 100 may be a state of the art printed circuit board which includes a substrate 102 having a plurality of holes thereon and further having printed wiring, such as wire 104, connecting certain of the holes.
In FIG. 5, certain of the integrated circuit logic components such as 106, 108 and 110 are shown. These may be placed in any desired location on printer circuit board 100 and interconnected to form the circuit shown in FIG. 3. Also shown in FIG. 5 are sixteen strips, such as strips 112, 114, 116 and 118, which form the matrix 46. Each of the strips have twenty-one holes into which one end of a circuit element may be inserted. Each of the holes of alternate ones of the strips, such as strips 112 and 116, are connected to different rows of matrix 46. Each of the holes of the remaining strips, such as strips 114 and 118 are respectively connected to one of the columns of matrix 46, with all of the holes of strip 114 being connected to the first column, all of the holes of strip 118 being coupled to the second column, and so forth.
A connection between a row and a column may be made by inserting a diode between adjacent strips, such as inserting diode 120 between strips 112 and 114. Diode 120 being inserted in the first holes of the strips 112 and 114 would thus connect the first column with the first row of matrix 46. If one desired, for instance, to connect the second column with the third row, diode 122 would be inserted between strips 116 and 118 in the third holes from the top. If the message is only eight characters long, a diode 124 is inserted between strips 126 and 128 in the eighth holes from the top, as shown in FIG. 5.
The plan view of FIG. 6 is taken looking from the top in FIG. 5 with the circuit components and strips removed. The solid lines such as lines 104, 130 and 132, represent printed wiring and the broken lines, such as line 134, represent printed wiring on the opposite side of board 100. Printed circuit board 100 has sixteen columns, such as columns 136, 138, 140 and 142, with twenty-one holes in each column, such as holes 144, 146 and 148. Each of the holes has printed wire around the inner circumference thereof, as indicated by the solid line thereat. The strip 112, shown in FIG. 5, is positioned on printed circuit board 100 so that the twenty-one holes thereof are in alignment with the twenty-one holes of column 136 and are electrically connected thereto by, for instance, soldering. Similarly the holes of strips 114, 116 and 118 are aligned with the holes of columns 138, 140, 142 of printed circuit board 100 and electrically connected thereto.
Each of the holes of alternate columns, such as columns 138 and 142 are respectively electrically connected together by printed wires such as wires 130 and 150. Corresponding holes of the remaining columns, such as holes 146, 152 and 154, are connected together by printed wire on the opposite side of printed circuit board 100, such as by printed wire 156.
Each of the printed wires, such as wires 130 and 150 are connected to logic elements (not shown) which would correspond to the inverters 56, 58 and 60 shown in FIG. 3, Each of the printed wires such as wires 134 and 156 are connected to outputs of the shift register 76 of FIG. 3. Thus, to make the first row to first column connection, it is necessary to couple holes 146 and 148 together and this is accomplished by diode 120 shown in FIG. 5.