Title:
COLOR DISPLAY SYSTEM
United States Patent 3771155
Abstract:
An improved color display system in which the display screen of a cathode-ray tube is divided into an appropriate number of areas each for displaying a character, symbol or picture element in two or more colors, the whole screen of the cathode-ray tube expressing a definite piece of information.


Inventors:
Hayashi, Yukitaka (Hitachi, JA)
Yasuda, Isao (Hitachi, JA)
Hamada, Nagaharu (Hitachi, JA)
Application Number:
05/178928
Publication Date:
11/06/1973
Filing Date:
09/09/1971
Assignee:
Hitachi, Ltd. (Chiyoda-ku, Tokyo, JA)
Primary Class:
Other Classes:
345/549, 715/860
International Classes:
G09G5/02; (IPC1-7): G06F3/14
Field of Search:
340/324A,324AD
View Patent Images:
US Patent References:
3685038VIDEO DATA COLOR DISPLAY SYSTEM1972-08-15Flanagan
3668686CONTROL APPARATUS1972-06-06Strohmeyer
3516122APPARATUS FOR MAKING INTEGRAL CONTAINERS HAVING PARALLEL VERTICAL WALLS1970-06-23Owen
3505665DISPLAY SYSTEM1970-04-07Lasoff et al.
3396377Display data processor1968-08-06Strout
3351929Data converter1967-11-07Wagner
Primary Examiner:
Trafton, David L.
Claims:
We claim

1. In a color display system of the raster scan type for displaying information supplied by a processor, the improvement comprising at least two refresh memories for storing character symbol codes supplied by said processor and color codes for determing the color of at least one of said character and symbol, said character/symbol codes and said color codes being stored independently of each other in said refresh memories, a character/symbol generator for converting the character/symbol codes in said refresh memories into video signals, a color decoder for decoding the color code from each refresh memory into color signals, a control device for timing the application to the color display unit of said video signals and the color signals from said color decoder corresponding to said video signals, and a priority circuit for giving priority to a color video signal with respect to the other color video signals in a predetermined order of said refresh memories, said color video signal resulting from the combination of said video signal and color signal.

2. A color display system according to claim 1, wherein said character/symbol generator converts said character/symbol codes supplied by said refresh memories into video signals which are chronologically divided.

3. A color display system according to claim 1, further comprising a cursor control circuit for displaying a cursor in a specific color on the color display screen, said color designating the position of display of information to be altered.

4. A color display system according to claim 1, further comprising a cursor control circuit for displaying information in a specific color on the color display screen, said color designating the position of display of information to be altered.

5. A color display system according to claim 1, wherein said priority circuit includes means for inverting the video signal of one of said refresh memories and providing an inverted video signal and means for combining the inverted video signal with the color video signals of another of said refresh memories.

6. A color display system according to claim 5, wherein the combining means includes AND gate means.

7. In a color display sytem of the raster scan type for displaying information supplied by a processor, the improvement comprising at least two refresh memories for storing character symbol codes supplied by said processor and color codes for determining the color of at least one of said character and symbol, said character/symbol codes and said color codes being stored independently of each other in said refresh memories, a character/symbol generator for converting the character/symbol codes in said refresh memories into video signals, a color decoder for decoding the color code from each refresh memory into color signals, a control device for timing the application to the color display unit of said video signals and the color signals from said color decoder corresponding to said video signals, and a priority circuit for giving priority to a color signal from said color decoder with respect to the other color signals from said color decoder in a predetermined order of the colors.

8. A color display system according to claim 7, further comprising a cursor control circuit for displaying a cursor in a specific color on the color display screen, said color designating the position of display of information to be altered.

9. A color display system according to claim 7, further comprising a cursor control circuit for displaying information in a specific color on the color display screen, said color designating the position of display of information to be altered.

10. A color display system according to claim 7, wherein said character/symbol generator converts said character/symbol codes supplied by said refresh memories into video signals which are chrono-logically divided.

11. A color display system according to claim 7, wherein said priority circuit includes a plurality of AND gate means.

12. A color display system according to claim 11, wherein said priority circuit provides color priority in the order R, M, Y, W, C, B and G.

Description:
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a color display system.

2. Description of the Prior Art

In a conventional color display system where a unit cell of a memory has the close relationship with a unit display area on the screen, a change in the color in the midst of consecutive characters, symbols or picture elements results in creation of a space as large as a unit display area at the point of such a change, even though the conventional display of a table is in no way adversely affected by the space. On the contrary, such a space as large as one character is even useful and often formed intentionally. In certain fields of applications, therefore, the conventional display unit serves the purpose quite well.

At a time when information which requires processing on a computer is both complicated and increasing in volume, it is necessary for a display unit to be equipped with functions to display colorful graphs in order to simplify and improve the efficiency of communication between operators and the machine. FIG. 1 shows part of a skeleton of a power substation, in which the three states of energization, cut-off and failure of a breaker, transformer, resistor, etc. are displayed in red, green and white respectively, while indicating the intermediate lines in yellow.

It is easy to understand that it is impossible to display this skeleton in a state of high density as shown in FIG. 1, in the conventional display unit which develops a one-character space, and in which the skeleton becomes very loose.

One method of overcoming this difficulty consists in storing color codes and character/symbol codes separately, which are displayed in a proper timing. This makes possible simultaneous indication of two or more characters, symbols or picture elements without any space in a unit area in a single color.

However, it is impossible, even by this method, to display two or more characters, symbols or picture elements in two or more colors in a unit area.

SUMMARY OF THE INVENTION

An object of this invention is to overcome the problems encountered by the conventional display unit and provide a color-display unit which is capable of displaying two or more characters, symbols or picture elements in a unit area in two or more colors.

More specifically, the device according to the invention is provided with two or more sets of refresh memories for storing character/symbol codes processed in a processor and color codes which determine display colors, and the color codes correspond to the character/symbol codes stored in the refresh memories. Information stored in the refresh memories is read into a character/symbol generator, the character/symbol codes being converted into video signals, while applying the color codes to the cathode-ray tube after being decoded.

Another object of the invention is to provide a color display device with a priority circuit for giving priority to one of two or more pieces of information in two or more colors which may be included in one display area, in order to prevent the colors from being mixed at the boundary, which often results in indication of information in a wrong color.

Still another object of the invention is to provide a color display unit having at least two sets of refresh memories comprising a color memory and a data memory for the purpose of displaying information in two or more colors in each unit display area on the display screen, in which a cursor or information to be displayed is controlled at a specific color thereby to change, eliminate or insert the information for selection of refresh memories. The cursor mentioned above means a bright line for designating a display position or display area on the display screen of, say, a cathode-ray tube.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a skeleton diagram displayed by the color display system according to the invention.

FIG. 2 is a diagram showing an embodiment of the invention.

FIG. 3 is a diagram showing an example of information stored in the refresh memory shown in FIG. 2.

FIG. 4 is a diagram showing another embodiment of the invention.

FIG. 5 is a diagram for explaining the embodiment shown in FIG. 4.

FIG. 6 is a diagram for explaining another embodiment of the invention.

FIG. 7 is a diagram showing a part of the circuit of FIG. 6 in detail.

FIG. 8 is a diagram illustrating the problems in color display.

FIG. 9 is a diagram showing an example how mixture of colors is prevented according to an embodiment of the invention.

FIG. 10 is a diagram showing another embodiment of the inVention for preventing the mixture of colors, in which is shown a modified circuit corresponding to the circuit shown in FIG. 7.

FIG. 11 is a diagram showing still another embodiment of the invention for preventing mixture of colors.

FIG. 12 is a diagram showing the embodiment of FIG. 11 more in detail.

FIG. 13 is a diagram showing an embodiment of the invention in connection with a cursor display.

FIGS. 14a and 14b are diagrams showing a part of the device of FIG. 13 in detail.

FIG. 15 is a diagram showing another embodiment of the invention in connection with cursor display.

FIGS. 16a and 16b are diagrams for explaining in detail a part of the device illustrated in FIG. 15.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will now be explained in detail with reference to the accompanying drawings. An embodiment of the invention is shown in FIG. 2, in which the reference numeral 1 shows a data processing system, numeral 2 a display control device, and numeral 3 a display unit such as a viewer.

The data processing system 1 produces an output in every 10 bits comprising 7 bits of character symbol (including picture elements constituting a picture) and 3 bits of color signal. The control device 2, on receipt of the output from the data processing system 1, decodes the data to display a data at a predetermined position on the display unit 3.

More in detail, numerals 20 and 20' of the control device 2 show buffer registers which adjust the timing of data transfer from the data processing system 1 to the refresh memories 21 and 21' in accordance with the conditions of the refresh memories 21 and 21'.

The refresh memories 21 and 21' in this embodiment, which store character signals of 7 bits and color codes of 3 bits, have functions to refresh the data for display and comprise MOS dynamic shift registers. Numeral 22 shows a character/symbol generator which decodes only character and symbol codes selectively among the codes of, say, 10 bits and converts them into video signals for scanning on the display unit 3. Numeral 23 shows a color-code decoder for identifying color codes which are divided into the three primary colors by means of the color encoder 24 which in turn produces signals of red (R), green (G) and blue (B). Numerals 25R, 25G and 25B show flip-flops of the D type for setting the color signals of red, green and blue respectively. Numerals 26R, 26G and 26B show AND circuits to which color signals and video signals corresponding to the respective colors are applied. Numeral 27 shows a deflection control circuit for controlling the position of data display.

Numeral 28 shows a timing control circuit which adjusts the timing of data transfer from the refresh memories 21 and 21' or the processing system 1, the timing of generation of video signals from the character/symbol generator 22 and the timing of operation of the deflection control circuit 27 for indicating a desired data at a desired position. Numeral 28' shows a binary counter which reverses its operation at every field by means of the timing control circuit 28 to decide from which of the two sets of refresh memories information should be read out. Referring to the refresh memories 21 and 21', numeral 21a shows a memory for character/symbol codes of the refresh memory 21, numeral 21b a memory for color codes thereof, numeral 21'a a memory for character/symbol codes of the other refresh memory 21', and numeral 21'b a memory for color codes thereof. Numerals 29a, 29b, 29'a and 29'b show AND gates respectively for controlling the transfer of information stored in each memory by means of the binary counter 28'.

The operation of the device described above will be now explained. Data is processed in the processor 1. Characters, symbols and colors processed in the processor 1 are encoded and applied, through the timing buffer registers 20 and 20', to the refresh memories 21 and 21' respectively so that they are stored in these memories in parallel with each other. Among the encoded data, character and symbol codes are decoded by the character/symbol generator 22 for conversion into a series of video signals. On the other hand, color codes are read by the color code decoder 23. The color signals thus read are divided into the three primaries by the color code encoder 24 which produces output signals R, G and B corresponding to each color, thereby setting the flip-flops 25R, 25G and 25B of the D type. Output signals from these flip-flops, combined with the output signals from the character/symbol generator, are applied to the AND circuits 26R, 26G and 26B so that a video signal is displayed in a desired color on the display unit 3.

Now let us discuss the character/symbol code memories 21a and 21'a of the refresh memories 21 and 21' respectively. Information stored in the memories 21a and 21'a is alternately read at every field. In other words, the timing control circuit 28 causes the binary counter 28' to reverse its operation at every other field, so that the AND gates 29a and 29b are opened for a certain period and the AND gates 29'a and 29'b are opened for the remaining period to read out the information stored in the refresh memories.

Now, assume that the output of the binary counter 28' is applied to the AND gates 29a and 29b. Character/symbol codes are read from the memory 21a in the refresh memory 21 and color codes from the memory 21b at predetermined intervals through the timing control device 28. The character/symbol codes, together with the output from the binary counter 28', are applied to the AND gate 29a, the output of which is applied to the character/symbol generator 22. On the other hand, the color codes, together with the output from the binary counter 28', are applied to the AND gate 29b, the output of which is applied to the color code decoder 23. The character/symbol codes applied to the character/symbol generator 22 are converted into video signals. Out of the color codes applied to the color code decoder 23, one of a designated color is read and divided into the three primary colors by the color encoder, which are latched respectively to the flip-flops 25R, 25G and 25B. The information stored in the flip-flops 25R, 25G and 25B are applied, together with the video signals from the character/symbol generator 22, to the AND gates 26R, 26G and 26B, the outputs of which are applied to the display unit 3. Information is displayed in color at a predetermined position on the display unit 3 by means of the deflection control circuit 27 which is controlled by the timing control circuit 28. Information stored in the refresh memory 21' is read out for display in quite the same manner. Between the information signals in the memory 21a and the one in the memory 21'a, there is such a relationship that the former is displayed in the form of color signals stored in the memory 21b and the latter in the form of color signals stored in the memory 21'b, transfer between which is effected every 1/16 second. As a result, to the naked tye of a human being, information is displayed on the screen of the display unit 3 as if the information in the memory 21a and the one in the memory 21'a are displayed at the same time.

To make it easier to understand the embodiments of the invention, an example of information stored in the refresh memories 21 and 21' of FIG. 2 is shown in FIG. 3. It will be seen from this drawing that the area (j, k) in FIG. 1 corresponds to the memory adress of block j and NO. k which is hereinafter referred to as (j, k)M. In a scanning of one field, (j, k)M to (j, k+12)M read from 21a are displayed at (j, k) to (j, k+12) respectively on the viewer 3 in the color (white, showing a failure, in this case) designated by 21b. In the scanning of the next field after j+1 to j+m are displayed in sequence, (j, k)'M to (j, k+12)'M read from 21'a are displayed respectively at (j, k) to (j, k+12) on the viewer 3. The latter display is superposed on the preceding one, and its color is designated by 21'b independently of 21b. For example, at (j, k+4) and (j, k+7) in FIG. 1, the white "-" of the preceding field is displayed crossed with the red " ," while, at (j, k+11), the white "--" is displayed superposed on the yellow character "X." If the field scanning is repeated at every 1/60 second, character/symbol information from one memory is displayed at every 1/30 second.

Besides the above-described method in which the character/symbol generator is used by chronologically dividing its operation for each field, it is obvious that the invention is effective with character/symbol generators as many as the refresh memories.

Further, there is another method of using the character/symbol generator by time division. An embodiment of this method will be explained in detail below with reference to FIGS. 4 and 5. Referring to FIG. 4, numerals 21 and 21' show refresh memories, numerals 220 and 220' latch registers for adjusting the variations in the output of 220 and 220', numeral 230 a switching gate for applying the character/symbol codes from the two refresh memories at an appropriate timing, numeral 231 a color switching gate for producing as an output the color codes from the two refresh memories at an appropriate timing, numerals 241 to 243 pattern latch registers which temporarily receive and hold for a certain period of time the dot patterns of the character/symbol codes read out, numerals 251 and 252 a multiplexer for converting the dot patterns read in parallel into series video signals, and numerals 261, 262 and 263 show OR circuits. The other parts with like numerals show like parts in FIG. 2.

The operations of this embodiment will be explained with reference to a time chart therefor shown in FIG. 5. Information processed in the data processing system 1 is stored, as in the embodiment of FIG. 2, in the refresh memories 21 and 21' in such an orderly manner as shown by (a) and (b) of FIG. 5. Assuming that the character/symbol code (D1-A) of the refresh memory 21 and the data code (D1-B) are displayed superposed on each other in the same unit area of the cathode-ray tube, the character/symbol codes (D1-A) and (D1-B), like (c) and (d) of FIG. 5, are read into the latch registers 220 and 220' simultaneously with color codes. Suppose it takes 500 ns to operate the character/symbol generator 22 and that it takes 1 μs display given information in a unit area of the CRT screen. Also suppose it takes 500 ns to transfer the switching gate 230. (The time required for operation of the switching gate 230 must not exceed 500 ns or the time required to operate the character/symbol generator.) The character/symbol code (D1-A) is read into the character/symbol generator 22 during the first 500 ns and the code (D1-B) during the second 500 ns, through the switching operations of the gate 230, as illustrated in (g) and (h) of FIG. 5. All the timings for these operations are provided by the timing control circuit 28. The signal (D1-A) read into the character/symbol generator 22 during the first 500 ns is converted into the video signal (P1-A) and latched to the output latch register 241. During the next 500 ns, the signal (D1-B) is taken into the character/symbol generator 22 where it is converted into the video signal (P1-B) and latched to the output latch register 243. At the same time, information stored in the output latch register 241 or the signal (P1-A) is latched again to the output latch register 242. This is to temporarily maintain the signal (P1-A) in the latch register 242 from the output latch register 241 as a result of the character/symbol code (D2-A) being taken into the character/symbol generator 22 for display in the next unit area of the refresh memory 21 whose display continues for 1 μs. In other words, the information stored in the output latch register is latched in the manner as shown by (i) to (k) of FIG. 5. The video signals (P1-A) and (P1-B) latched to 242 and 243 are respectively converted into more serial signals by the multiplexers 251 and 252 and applied to the AND circuits 26R, 26G and 26B and 26R', 26G' and 26B'. The output of these AND circuits is applied to the OR circuits 261, 262 and 263 for display on the cathode-ray tube. The control of color signals is effected in the same manner as described with reference to the embodiment of FIG. 2, the only difference being in that they are controlled taking the time relationship with the character/symbol code. In this embodiment, a color is identified by the color decoder 23 by means of the timing of switching the character/symbol code to be applied to the color encoder 24. It is possible, with this construction, to display information in a plurality of colors in a unit display area. This method also makes possible display with less flickers than the embodiment of FIG. 2.

Another emodiment of the invention will be now explained with reference to FIGS. 6 to 9. FIG. 6 shows a color display unit comprising 2 sets of refresh memories each capable of displaying information in two colors in its unit display area. Numeral 10 shows a color code control circuit for distinguishing between a color code and a data code. Numeral 200 shows a memory selector circuit for distributing color codes and data codes from the color code control circuit 10 between the memories. Numerals 21 and 21' show refresh memories, numerals 22 and 22' character/symbol generators, numerals 70 and 80 color flip-flops, numerals 90 and 100 color control gates, numeral 28 a timing control circuit, numeral 27 a deflection control circuit, numeral 13 a color driving circuit, and numeral 3 a color CRT.

The operations of this embodiment will be explained now with reference to FIG. 6. Information supplied by a computer or other external device enters the device of the invention in series of words (which usually comprises 8 bits). This information includes control data for designating a refresh memory for storage purposes, color codes for designating a display color and data codes for specifying characters and symbols to be displayed. This composite information is applied to the color code control circuit 10 wherefrom color codes and data codes are sent out separately. The output of the color code control circuit 10 is applied to the memory selector circuit 200 for selection of a refresh memory to store the signal involved. The output of the memory selector circuit 200 is applied to and stored in the refresh memories 21 and 21'. The color and data codes stored in the refresh memories are read out in synchronism with the motion of electron beams of the color CRT. The color codes, after being timed by the color flip-flops 70 and 80 respectively, are applied to the color control gates 90 and 100 respectively. The data codes, by contrast, are applied to the character/symbol generators 22 and 22' and after being converted into character/symbol signals (video signals), are applied to the color control gates 90 and 100. The color control gate 90, which receives the outputs R1, G1 and B1 from the color flip-flop 70 and the character/symbol signal V1, functions as an AND circuit, while the color control gate 100 receives the outputs R2, G2 and B2 of the color flip-flop 80 and the character/symbol signal V2 to function as an AND gate, producing outputs R1V, G1V, B1V, R2V, G2V and B2V to drive an electron gun. The outputs from the color control gates 90 and 100 are applied to the color driving circuit 13 which acts as an OR gate and applies its output to the color CRT 3, whereby an electron gun is driven by a deflection signal produced from the deflection control circuit 27 for display on the CRT screen. The color control gates 90 and 100 and the color driving circuit 13 of FIG. 6 are shown more in detail in FIG. 7. In FIG. 7, numerals 91 to 93 and 101 to 103 show AND gates, and numerals 131 to 133 OR gates. As already explained, the color codes R1, G1, B1, R2, G2 and B2 and character/symbol signals V1 and V2 are applied respectively to the AND gates 91 to 93 and 101 to 103, and as a result the outputs are produced in the form of the signals R1V, G1V, B1V, R2V, G2V and B2V. These signals are applied to the OR circuits 131 to 133 of the color driving circuit 13 which produces an output to be applied to the color CRT 3.

In this embodiment mentioned with reference to FIGS. 6 and 7, there is a disadvantage as explained below. An example of information displayed on the color display unit of FIG. 6 is shown in FIG. 8. FIG. 8(a) shows an example of a power flow chart. Information displayed in the areas (K, j+1), (K+1, j+5) and (K+2, j+5) are enlarged in FIGS. 8(a), 8(b) and 8(c). In the case of display of FIG. 8(b), the color of character H is mixed with the background color, while in the display of FIGS. 8(c) and 8(d), the difference in two colors causes them to be mixed with each other at their crossings.

Another embodiment of this invention will be explained with reference to FIG. 10 which is intended to provide a display without any color mixture as mentioned above. FIG. 10 shows a modified circuit corresponding to the circuit shown in FIG. 7. In FIG. 10, like parts are marked with like numerals as in FIGS. 6 and 7. Numeral 15 shows a priority circuit, provision of which makes possible clear display of information in a plurality of colors (two in this embodiment) in a single unit area. The priority circuit of the embodiment comprises an inverter 150 and AND gates 151 to 153. As in FIG. 6, informations stored in the refresh memories 21 and 21' are applied to the color flip-flops 70 and 80 and character/symbol generators 22 and 22' respectively. The outputs R1, G1 and B1 of the color flip-flop 10 and the output V1 of the character/symbol generator 22 are respectively applied to the AND gates 91, 92 and 93 of the color control gate 90. The outputs R2, G2 and B2 of the color flip-flop 80 and the output V2 of the character/symbol generator 6 are applied to the AND gates 101, 102 and 103 of the color control gate 100. The output V1 of the character/symbol generator 22 is also applied to the priority circuit 15 for the purpose of giving priority to the color signals R1, G1 and B1 and character signal V1. The outputs of the AND gates 91, 92 and 93 of the color control gate 90 are applied to the OR gates 131, 132 and 133 of the color driving circuit 13 respectively. On the other hand, the outputs of the AND circuits 101, 102 and 103 of the color control gate 100 are applied to the AND gates 151, 152 and 153 of the priority circuit 15. The signal V1 is applied through the inverter 30 of the priority circuit 15 to the AND gates 151, 152 and 153. The outputs of the priority circuit 15 are expressed in the following logical equations:

RV = R1 × V1 + R2 × V1 × V2 (1) GV = G1 × V1 + G2 × V1 (2) mes. V2

BV = B1 × V1 + B2 ×V1 × V2 (3)

These outputs are applied to the OR gates 131, 132 and 133 of the color driving circuit 13 to which the output of the color control gate 90 is also applied. The outputs from the OR circuit are applied in the form of color video signals RV, GV and BV to the color CRT 3 for display thereon. This embodiment is so constructed that the video (character/symbol) signal V1 of a memory to which priority is given is inverted by the inverter 150 to obtain a logical product from its combination with a color video signal of the other memory, making it possible to display information without any color mixtures in one unit display area. Thus, the infomation such as shown in FIGS. 8(b), 8(c) and 8(d), like the information of FIGS. 9(a), 9(b) and 9(c), is displayed independently.

In this embodiment, the priority circuit is inserted between the color control gate and the color driving circuit. However, the invention is not limited to such an arrangement, but may be applied to a construction in which the video signal V1 for deciding on the priority may be used to prohibit the application of the video signal V2 to the color control gate 100, or the signal V1 may be applied as one of three inputs to the AND gate of the color control gate 100 for prohibition of color mixture.

Another embodiment of the invention will be explained in connection with prevention of color mixture with reference to FIG. 11. This embodiment is such that color signals are given priority by types. In other words, priority is determined according to the color of information displayed. In the figure, like parts are marked with identical numerals with FIGS. 6, 7 and 10. Numeral 16 shows a decoder which, after converting into a single color the video signals R1V, G1V and B1V and the video signals R2V, G2V and B2V produced from the color control gates 90 and 100 respectively, acts as an OR gate and produces outputs in the form of color video signals RV, GV, BV, YV, MV, CV and WV shown by the following equations:

RV1 = R1V × G1V × B1V + R2V × G2V × B2V (4) GV1 = R1V × G1V × B1V + R2V × G2V (5) mes. B2V

BV1 = R1V × G1V × B1V + R2V × G2V × B2V (6) YV1 = R1V × G1V × B1V + R2V × G2V (7) mes. B2V

MV1 = R1V × G1V × B1V + R2V × G2V × B2V (8) CV1 = R1V × G1V × B1V + R2V × G2V (9) mes. B2V

WV1 = R1V × G1V × B1V + R2V × G2V × B2V (10)

Numeral 17 shows a priority circuit which produces its outputs in order of predetermined priority. If, for example, priority is given in order of R, M, Y, W, C, B and G, the logical equations according to which outputs are produced from the priority circuit 17 are as follows:

Rv2 = RV1 (11) MV2 = RV2 × MV1 (12)

YV2 = MV2 × YV1 (13) WV2 = YV2 × WV1 (14)

CV2 = WV2 × CV1 (15) BV2 = CV2 × VB1 (16)

GV2 = BV2 × GV1 (17)

The priority circuit is shown more in detail in FIG. 12, from which it will be seen that the circuit comprises AND circuits.

Numeral 18 shows an encoder which combines into the three color video signals RV, GV and BV the seven video signals which were placed in order of priority, the signals RV, GV and BV driving the color CRT 3. This will be expressed in the following equations:

RV = RV2 + MV2 + YV2 + WV2 (18) GV = GV2 + YV2 + CV2 (19) BV = BV2 + MV2 + CV2 (20) 2

The color signals R1, G1, B1, R2, G2 and B2 and the video signals V1 and V2 which are applied from the memories to the color control gates 90 and 100 functioning as AND gates. The outputs of the gates 90 and 100 in the form of color video signals R1V, G1V, B1V, R2V, G2V and B2V are applied to the decoder 16. These signals are converted into the seven color video signals RV1, GV1, BV1, YV1, MV1, CV1 and WV1 by the decoder 16 to be applied to the priority circuit 17 which place the input signals in the predetermined order of priority. The seven color video signals which left the priority circuit 17 are converted again into RV, GV and BV by the encoder 18 and applied to the color CRT 3. In this way, the color CRT 3 displays information without any mixture of two colors in a unit display area.

Another embodiment of the invention in connection with cursor control will be now explained. In FIG. 13, the numeral 1000 shows an input/output control circuit for controlling information inputs from external devices (as computers) and outputs to external devices. Numeral 21 shows a first refresh memory consisting of a first data memory and a first color memory. Numeral 21' shows a second refresh memory consisting of a second data memory and a second color memory. Numeral 22 shows a character/symbol generator which receives character/symbol codes from the first refresh memory 210 and produces video signals as an output. Numeral 13 shows a color driving circuit which, on receipt of the output of the character/symbol generator 22 and the first color code, produces color video signals that establish a relationship between color codes and video signals. Numeral 22' shows a character/symbol generator which receives the second data code and produces character/symbol signals, and numeral 790 a color control circuit for producing color video signals on receipt of the output from the character/symbol generator 22' and the second color code. Numeral 28 shows a timing control circuit which sends a timing signal to each circuit. Numeral 27 shows a deflection control circuit, numeral 4 a cursor display control circuit, and numeral 13 a color driving circuit which receives output signals from the cursor control circuits 790 and 800 and the cursor display control circuit 4 and combines them into a color video signal for driving an electron gun. Numeral 3 shows a color CRT.

Actual interconnections of components of the cursor display control circuit 4 and those of the color driving circuit 13 are shown in FIGS. 14(a) and 14(b) respectively. The embodiment of FIG. 13 is intended to select an appropriate refresh memory in case of change, elimination or addition of information according to the cursor color. For example, assuming that information is displayed on the screen of the color CRT 3, the cursor is made green in color if that information is displayed through the data of the first refresh memory 21, while the cursor color is made blue if it is displayed through the data of the second refresh memory 21'. When there is no data stored in the memories, the cursor color is made, say, red so as to indicate that it is possible to write in any of the refresh memories.

The operations of this embodiment will be now explained with reference to FIGS. 13 and 14. Information is distributed, for storage purposes, between the data memory and color memory of the refresh memories 21 and 21' and converted into the video signals by means of the character/symbol generators 22 and 22'. The information stored in the color memory and the outputs of the character/symbol generators 22 and 22' are applied to the color control circuits 800 and 790 respectively, which in turn apply color video signals RV1, GV1, BV1, RV2, GV2 and BV2 to the color driving circuit 13.

The cursor display control circuit 4 also applies three types of signals to the color driving circuit 13. Explanation will be made in detial now of this cursor display control circuit with reference to FIG. 14a. Numerals 41 and 42 show flip-flops, and numerals 43 to 47 AND gates. To the AND gates 43 and 44 are applied the character agreement signal CRSROK from the timing control circuit 28 (shown in FIG. 13) and the outputs V1 and V2 from the character/symbol generator 22 and 22'. The outputs from the AND circuits 43 and 44 are set in the flip-flops 41 and 42. In other words, absence of any video signal at the display position designated by the cursor causes a flip-flop corresponding to the data memory involved to be set. This flip-flop is reset by the cursor transfer signal CRSRSHFT produced from the timing control circuit 28. The signal which is produced from the timing control circuit 28 for indicating the scanning line for cursor display (the 10th scanning line RST10 in this embodiment), together with the outputs from the flip-flops 41 and 42, is applied to the AND gates 45 to 47. The AND gate 45 receives the signals CRSROK and RST10 and outputs from the flip-flop 41 and produces the cursor control signal CRSR1 in the presence of data in the refresh memory 21. The AND circuit 46, by contrast, receives the signals CRSROK and RST10 and outputs of the flip-flop 42 and produces the cursor control signal CRSR2 in the presence of data in the refresh memory 21'. The AND gate 47, which receives the signals CRSROK and RST10 and the outputs from the flip-flops 42 and 43, produces the cursor control signal CRSRO in the absence of data in any of the refresh memories.

These cursor control signals are produced as an output from the cursor display control circuit 4 as shown in FIG. 13. The color driving circuit 13 receives the cursor control signals CRSR1, CRSR2 and CRSR0, color video signals RV1, GV1, BV1, RV2, GV2 and BV2 and outputs from the character/symbol generator, and applies to the color CRT final signals RV, GV and BV for driving an electron gun. The color driving circuit 13 will be explained specifically with reference to FIG. 14b. In this drawing, the reference numerals 131 to 135 show OR gates and numerals 136 to 141 AND gates with inhibiting input terminals (indicated by 0). The OR gates 131, 132, 136, 137, 138, 139, 140 and 141 produce output (CRSR1 + CRSR2), (V1 + CRSR1 + CRSR2), RV1. (CRSR1 + CRSR2), GV1. (CRSR1 + CRSR2), BV1. (CRSR1 + CRSR2), (V1 + CRSR1 + CRSR2). RV2, GV2. (V1 + CRSR1 + CRSR2) and BV2. (V1 + CRSR1 + CRSR2). The outputs of the OR gates, that is, the final signals RV, GV and BV are as shown in the following logical equations:

RV = CRSR0 + (CRSR1 + CRSR2) × (RV1 +V1× RV2) (21)GV = CRSR1 + (CRSR1+ CRSR2) × (GV1 + V1 × GV2) (22)

BV = CRSR2 + (CRSR1 + CRSR2) × (BV1 + V1 × BV2) (23)

The reason why RV2, GV2 or BV2 is multiplied by V1 is to prevent color mixture at the crossing of the data codes of the memories 21 and 21'. Also, the color video signals representing display information are multiplied by (CRSR1 + CRSR2) in order to prevent color mixture at the portion where the cursor and information overlap each other. The outputs RV, GV, BV, etc. of the color driving circuit 13 which satisfy the equations (21), (22) and (23) are applied to the color CRT, so that the beam from each electron gun is deflected by a deflection signal from the deflection control circuit 27.

As a result, information is displayed on the screen of the color CRT3, while the cursor moves at the timing controlled by the cursor shift signal CRSRSHFT, displaying a specific color indicating which refresh memory stores information for each display area.

Another embodiment of the invention will be now explained in connection with cursor control. In the preceding embodiment, it is easily known which memory develops information when one of the memories is involved in display in the display area. If data codes from both of the memories take part in display in one unit area, the cursor consists of a mixture of colors of, say, green and blue. This indicates a display by both of the memories but causes confusion when changing the information stored in one of the memories. The embodiment shown in FIG. 15 is aimed at obviating this disadvantage. According to this embodiment, the character and symbol at the positions designated by the cursor are displayed in colors corresponding to the memory involved, so as to make it clear which memory designates the character and symbol. In FIG. 15, like parts are marked with like numerals as in FIG. 13. Numeral 4' shows a cursor control circuit and numeral 13' a color driving circuit. The cursor control circuit 4' and color driving circuit 13' are shown more in detail in FIGS. 16a and 16b respectively.

The operations of this embodiment will be now explained with reference to FIG. 16. As already explained, the color video signals RV1, GV1, BV1, RV2, GV2 and BV2 from the color control circuits 790 and 800 are applied to the color criving circuit 13'. The output of the cursor control circuit 4' is also applied to the color driving circuit 13'.

The cursor control circuit 4' will be now explained with reference to FIG. 16a. In this figure, the reference numerals 401 and 402 show flip-flops and numerals 403 to 409 AND circuits. The character agreement signal CRSROK from the timing control circuit 28 shown in FIG. 15 and the outputs V1 and V2 from the character/symbol generators 22 and 22' are applied to the AND gates 403 and 404. The outputs of the AND gates 403 and 404 are set in flip-flops 401 and 402 respectively, which are reset by the cursor shift signal CRSRSHFT produced from the timing control circuit 28. The output V1 of the character/symbol generator 22 and the output of the flip-flop 401 are applied to the AND gate 405 which produces as an output the video signal M1V representing the data code at the cursor position. The signal ORSROK and the output from the flip-flop 401 are applied to the AND gate 406 which produces a signal MEM1 indicating that there is at the cursor position a video signal from the refresh memory 21. The output from the flip-flop 402 and the signal CRSROK are applied to the AND gate 407 which produces the signal MEM2 indicating that there is a video signal from the refresh memory 21' at the cursor position. The signals V2 and M1V and the output of the flip-flop 402 are applied to the AND gate 408 with an inhibiting input terminal receiving the signal M1V, the AND gate 408 producing as an output the video signal M2V from the refresh memory 21' correspondingly to the cursor position. The signal CRSROK and the output RST10 from the timing control circuit 28 are applied to the AND gate 409 which produces the cursor control signal CRSR. This signal is applied from the cursor control circuit of FIG. 15 to the color driving circuit 13'.

The color driving circuit 13' will be now explained with reference to FIG. 16b. Numerals 1301 to 1305 show OR gates, and numerals 1306 to 1311 AND gates with inhibiting input terminals (marked with 0). The OR gates 1301 and 1302 produce outputs (CRSR + MEM1) and (CRSR + VI + MEM2)respectively, while the AND gates 1306, 1307, 1308, 1309, 1310 and 1311 produce outputs RV1 × (CRSR + MEM1), GV1 × (CRSR + MEM1), BV1 × (CRSR + MEM1), RV2 × (CRSR + V1 + MEM2), GV2 × (CRSR + V1 + MEM2) and BV2 × (CRSR + V1 + MEM2) respectively. The outputs of the OR circuits 1303 to 1305 or the final signals RV, GV and BV are expressed in the following equations:

RV=CRSR+(CRSR+MEM1)×RV1+(CRSR+V1+MEM2)×RV2 (24) GV=M1V(CRSR+M EM1)×GV1 +(CRSR+V1+MEM2 )×GV2 (25)

BV=M2V+(CRSR+MEM1)×BV1+(CRSR+V1+MEM2)×BV2 (26)

The reason why a color video signal is inhibited by CRSR is to prevent color mixture due to an overlapping of the cursor and the display information. In this case, the cursor is always indicated in red through the signal RV. The outputs RV, GV and BV from the color driving circuit 13' shown in FIG. 16(b) are identical with the outputs RV, GV and BV of the color driving circuit 13' of FIG. 15. The outputs of the color driving circuit 13' are applied to the color CRT 3, so that deflection signals from the deflection control circuit 27 cause the electron beam from each electron gun to be deflected, thus displaying information on the screen of the color CRT 3 in a color indicating the data memory in which the information is stored.

It will be understood from the above description that according to the invention the color of the cursor or the character at the position designated by the cursor is differentiated according to the memory involved, making it very easy to select a refresh memory in alternation, removal or addition of display information at a display position on the screen by means of a keyboard on the like.