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Title:
ELECTRONIC DEFECT DETECTING APPARATUS
United States Patent 3746784
Abstract:
An assembly for detecting defects in articles of manufacture such as, for example, glassware is disclosed herein and includes a semi-diffused light source positioned adjacent one side of and optically distant from a glassware sample for illuminating the latter. A video camera is positioned on the other side of and scans the illuminated sample so as to produce a video signal indicative of the difference in refraction characteristics thereof, and thereby indicates the presence or absence of defects in the glassware sample. In the event there is a defect, an electrical processing circuit, connected with the video camera and responsive to the video signal, is provided for actuating a glassware reject mechanism.


Application Number:
05/171894
Publication Date:
07/17/1973
Filing Date:
08/16/1971
Assignee:
Ball Corporation (Muncie, IN)
Primary Class:
Other Classes:
250/223B, 250/559.08, 250/559.46, 348/133
International Classes:
G01N21/88; G01N21/90; (IPC1-7): H04N7/18
Field of Search:
250/219DF,219WD 178
View Patent Images:
US Patent References:
3647961T.V. -AIDED FLAW DETECTION USING ROTATING IMAGE TECHNIQUESMarch 1972Blitchington et al.
3579249FEATURE COUNTER HAVING BETWEEN LIMITS AMPLITUDE AND/OR WIDTH DISCRIMINATIONMay 1971Dewey et al.
3560096N/AFebruary 1971Watson et al.
3049588Quality control systemAugust 1962Barnett
2798605Electronic inspection apparatusJuly 1957Richards
Primary Examiner:
Britton, Howard W.
Claims:
What is claimed is

1. A device for detecting defects in glassware comprising: a light source for providing light rays to illuminate a glassware sample; camera means for scanning said illuminated sample and producing for each scan line a video signal indicative of the difference in the refraction characteristic of that portion of said sample then scanned including indications of the leading and trailing edges of said sample; and electrical circuit processing means connected to said camera means and responsive to said video signal for producing an output signal indicative of a defect in said sample in the even that said video signal includes a predetermined refraction characteristic, said electrical circuit processing means including means for suppressing a predetermined portion of a video signal received from said camera means during each said scan line, including suppression of said indications of said leading and trailing edges, whereby said output signal indicative of a defect in said sample is produced only during the predetermined unsuppressed portion of a received video signal.

2. A device for detecting defects in glassware comprising: a light source for providing light rays to illuminate a glassware sample; camera means for scanning said illuminated sample and producing a signal indicative of the difference in the refraction characteristic of that portion of said sample then scanned including signals indicative of the leading and trailing edges of said sample; signal detector means connected to said camera means and responsive to said signal for producing a pulsed signal for each sudden change in refraction of said illuminated sample; and means connected to said signal detector means for suppressing predetermined ones of said pulsed signals during each scan line, including said signals indicative of said leading and trailing edges of said sample, and for producing second pulsed signals in response to the remaining ones of said pulsed signals.

3. A device according to claim 2 wherein said signal detector means includes a comparator circuit setup with hysteresis whereby to enhance the quality of said pulsed signal.

4. A device according to claim 2 including signal timing means synchronized with the scan of said camera means for preventing said signal detector means from producing said pulsed signals during predetermined scanning periods of said camera means, said signal timing means including at least one multivibrator circuit having a capacitor circuit which charges substantially faster than it discharges whereby to attain high duty operation.

5. A device for detecting defects in glassware comprising: a light source for providing light rays to illuminate a glassware sample; camera means for scanning said illuminated sample and during each horizontal scan line producing a first edge signal indicative of one edge of said sample, a second edge signal indicative of an opposite edge of said sample, and a defect signal in the event there is a defect in said sample; signal detector means connected to said camera means for producing a pulsed signal in response to each of said first edge signals, second edge signals and defect signals; signal timing means synchronized with the scan of said camera means and connected to said signal detector means for preventing said signal detector means from producing said pulsed signals for a predetermined period of time during the beginning of the horizontal and verical scan of said camera means and for a predetermined period of time during the end of the horizontal and vertical scan of said camera means; and edge detector and removal means connected to said signal det ctor means and said signal timing means for suppressing those pulsed signals representative of said first and second edge signals and producing an output pulse in response to those pulsed signals representative of said defect signals.

6. A device for detecting defects in an article comprising: a source of radiation for providing radiation to said article; detection means for scanning said radiated article and during each horizontal scan producing a first edge signal indicative of one edge of said article, asecond edge signal indicative of an opposite edge of said article and a defect signal in the event there is a defect in said article; signal detector means connected to said detection means for producing a pulsed signal in response to each of said first edge signals, second edge signals and defectsignals; signal timing means synchronized with the scan of said detection means and connected to said signal detector means for preventing said signal detector means from producing said pulsed signal for a predetermined period of time during the beginning and end of the horizontal and vertical scan of said detection means; and edge detector and removal means connected to said signal detector means and said signal timing means for suppressing those pulsed signals representative of said one and opposite edges of said article.

7. A device for detecting defects in an article comprising: a light source providing light rays for illuminating said article, said light source including masking means for allowing only those light rays emanating from the periphery of said light source to illuminate said article; detection means for detecting said illuminated article and producing a signal representing said article; and electrical circuit processing means connected to said detection means and responsive to said signal for producing an output signal in the event there is a defect in said article.

8. A device for detecting defects in an article comprising a source of semi-diffused light positioned adjacent said article; lens means positioned between said semi-diffused light source and said article for directing the light rays emanating from said source onto said article in the same manner as if said source were substantially futther from said article; detection means for detecting said article and producing a signal indicative of the difference in illumination intensity thereof; and electrical circuit processing means connected to said detection means and responsive to said signal for producing an output signal inthe event there is a defect in said article.

9. A device for detecting defects in an article comprising: a radiation source for providing radiation to said article; detection means for scanning said article and during each scan line producing a first edge signal indicative of one edge of said article, a second edge signal indicative of a second edge of said article, and defect signals in the event there are defects in said article; and an electrical processing circuit including edge detector and removal means connected with said detection means for suppressing said first and second edge signals during each scan and providing output pulses in response to said defect signals.

10. A device according to claim 9 whereinsaid edge detector and removal means includes gating means providing said output pulses in response to said defect signals and inhibiting means connected to said gating means for preventing said gating means from providing output pulses in response to said first and second edge signals.

11. A device according to claim 10 wherein said inhibiting means includes first pulse producing means responsive to a first edge signal for producing a first inhibiting signal of predetermined duration, said first inhibiting signal preventing said gating means from providing an output pulse in response to a first edge signal, and second pulse producing means responsive to a second edge signal for producing a second inhibiting signal of predetermined duration, said second inhibiting signal preventing said gating means from providing an output pulse in response to a second edge signal.

12. A device according to claim 10 wherein said inhibiting means includes pulse producing and delay means receiving a second edge signal appearing on a given scan line and producing an inhibiting signal a predetermined period of time after receipt of said second edge signal for preventing said gating means from providing an output pulse in response to a second edge signal appearing on the scan line directly following said given scan line.

13. A device according to claim 12 wherein said pulse producing and delay means includes at least one RC network responsive to the second edge signal appearing on said given scan line for providing said predetermined period of time.

14. A device according to claim 12 wherein said pulse producing and delay means includes a first RC network responsive to the second edge signal appearing on said given scan line for providing a first increment of time, and a second RC network responsive to said first RC network forproviding a second increment of time, said first and second increments of time comprising said predetermined period of time.

15. A pulse removal circuit for use with scan detector means which provides a detection pulse in response to detected subject matter, said pulse removal circuit comprising: means adapted to receive a detection pulse for producing an output pulse in response thereto; and delayed pulse producing means adapted to recive a detection pulse appearing on a given scanline and producing a signal of predetermined duration a predetermined period of time after the receipt of said detection pulse, said signal being applied to said output pulse producingmeans for preventing said output pulse producing means from producing an output pulse in response to a detection pulseappearing on the scan line directly following said given scan line.

16. A pulse removal circuit according to claim 15 wherein said delayed pulse producing means includes a first RC network responsive to the detection pulse appearing on said given scan line for providing a first increment of time, and a second RC network responsive to said first RC network for providing a second increment of time, said first and second increments of time comprising said predetermined period of time.

17. A pulse removal circuit according to claim 16 wherein said delayed pulse producing means includes a comparator connected to said second RC network and responsive to the end of said second increment of time for producing said signal of predetermined duration.

18. An assembly according to claim 16 including reject means movable between a reject position and a non-reject position and means for moving said reject means from said non-reject position to said reject position in response to a reject signal provided during a given period of detection.

19. An assembly according to claim 18 wherein said last-mentioned means includes means for maintaining said reject means in said reject position in response to a reject signal provided during a given period of detection and for moving said reject means from said reject position to said non-reject position in the absence of a reject signal during a given period of detection.

20. An assembly for successively detecting a plurality of articles for defects, said assembly comprising: means for detecting said articles and providing a logic signal in the event that during a given period of detection only one complete article is detected and that a defect is detected in said article, and that during a directly preceding period of detection there was no article, more than one article, or less than one complete article detected; and means connected to said last-mentioned means for providing a reject signal in response to said logic signal.

21. An assembly for successively detecting a pluralityof articles for defects comprising: means for detecting each of said articles and providing a defect signal in the even that there is a defect in one of said detected articles, means for providing a logic signal in the event that one and only one complete article is detected; and means connected to said last-mentioned means for providing a reject signal in the even that said defect signal and said logic signal are present during a given period of detection and that said logic signal was not present during a directly preceding period of detection.

22. An assembly for successively detecting a plurality of glassware articles for defects, said assembly comprising means for providing an instantaneous flash of light rays for illuminating each of said glassware articles; lens means positioned between said last-mentioned means and said article for directing the light rays onto said article in the same manner as if said source were substantially further from said article; video camera means for scanning said instantaneously illuminated article and during each horizontal scan producing a first edge signal indicative of one edge of said article, a second edge signal indicative of an opposite edge of said article and a defect signal in the event there is a defect in said article; signal detector means connected to said video camera means for producing a pulsed signal in response to each of said first edge signal, second edge signal, and defect signal, said signal detection means including a comparator circuit setup with hysteresis whereby to enhance the quality of said signal; signal timing means synchronized with the scan of said camera means and connected to said signal detector means for preventing said signal detector means from producing said pulsed signals for a predetermined period of time during the beginning of the horizontal and vertical scan of said camera means and for a predetermined period of time during the end of the horizontal and vertical scan of said camera means, said signal timing means including at least one multivibrator circuit having a capacitor which charges substantially faster than it discharges whereby to obtain high operational duty; edge detector and removal means connected with said signal detector means and said signal timing means for suppressing those pulsed signals representative of said first and second edge signals and producing an output pulse in response to those pulsed signals representative of said defect signals; logic and classification means connected with said edge detector and removal means and said signal timing means and including circuit means for producing a first logic signal in the event that a single complete article is detected during a given period of detection and a second logic signal in the event that no article, less than one complete article or more than one complete article was detected during the directly preceding period of detection said logic and classification means producing a logic outputsignal in response to the presence of said output pulse, first logic signal and said second logic signal during said given period of detection; and reject gate activating means forproducing a gate activating signal in response to and a predetermined period of time after the production of said logic output signal.

23. A device for monitoring articles for predetermined characteristics comprising: camera means for scanning said articles and producing a video signal including components indicative of said characteristics if present and including components indicative of the leadingand trailing edges of said articles; and electrical circuit processing means connected to receive said video signal and responsive to said components thereof providing a signal indicative of the presence of said predetermined characteristics, said electrical circuit processing means including means for eliminating said components occurring during each scan line indicative of said leading and trailing edges of said article.

24. A device for monitoring articles for defects comprising: a radiation source for providing radiation to the then monitored article; means for scanning said articles and producing a video signal indicative of predetermined characteristics if present within that portion of said articles then scanned including indications of the leading and trailing edges of said articles; and electrical circuit processing means connected with said scanning means, said processing means including means for suppressing a predetermined portion of said video signal when received from said scanning means, including suppression of said indications of said first and second edges of said articles appearing on said scan line, and said processing means producing an output indicative of a defect in said article in response to an unsuppressed said video signal received from said scanning means.

Description:
BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to an assembly for detecting defects in articles and more particularly to an assembly for electrically and automatically detecting defects in articles.

2. Description of the Prior Art

It is often times necessary to monitor articles to assure product quality. It is readily apparent, for example, to those having knowledge in the manufacturing of glassware that finished glassware products may not be perfectly formed and may therefore, in some instances, not be entirely suitable for some uses. By providing monitoring or inspection devices to eliminate the articles which are not entirely suitable and therefore considered defective for at least a particular use, product quality can be enhanced. "Spikes," which are sharp glass projections formed in the glassware, and "birdswings," which are found generally in flask-type bottles and which comprise thin pieces of glass extending across opposite inner walls thereof, are examples of items for which glassware is often inspected and the glassware rejected if present. Obviously, monitoring or inspection systems and the degree of reliability inherent in any given system for monitoring unwanted characteristics in finished glassware products are often important in achieving quality of the product.

Heretofore, monitoring systems for detecting defects in glassware have taken various forms ranging from, for example, mere visual inspection utilized in the slow production of glassware to complex electronic detection utilized in the more rapid production thereof. It has been found, however, that none of the monitoring systems presently being used are completely satisfacotry in providing a system that has the necessary accuracy, reliability and/or speed required for today's typical modern methods of mass production.

SUMMARY OF THE INVENTION

This invention provides a heretofore unavailable improvement over known monitoring systems in that it provides for a more dependable and accurate assembly for rapidly monitoring and detecting predetermined characteristics in articles such as, for example, glassware. Briefly, the assembly, constructed in accordance with the present invention, generally comprises means for detecting an article and producing a video signal including components indicative of said characteristics if present and electrical circuit processing means connected to receive said video signal and responsive to said components thereof for providing a signal indicative of the presence of said predetermined characteristics.

Accordingly, an object of the present invention is to provide a new and improved apparatus for monitoring for and detecting defects in articles of manufacture, such as glassware, which apparatus is more dependable and accurate than those found in the prior art.

Another object of the present invention is to provide a new and improved apparatus for electronically monitoring for and detecting defects in articles of manufacture, such as glassware.

Yet another object of the present invention is to provide an apparatus of the last-mentioned type which takes up a relatively small amount of space.

Still another object of the present invention is to providea provide a and improved apparatus utilizing video signals and associated electronic components for monitoring and detecting defects in articles of manufacture, such as glassware.

Yet another object of the present invention is to provide an apparatus for detecting defects in articles of manufacture, such as glassware, which apparatus utilizes new and improved electronic circuit components associated therewith.

A further object of the present invention is to provide a new and improved assembly for monitoring and detecting defects in articles of manufacture, such as glassware, as the articles are moved along a conveyor and removing the detective articles.

These and other objects and features of the present invention will become more apparent from a reading of the following decriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a partial perspective view and partial block diagram of an electronic video defect detection assembly constructed in accordance with the present invention and preferably provided for detecting defects in a train of glass bottles transported along a conveyor mechanism;

FIG. 2 is a front view of a standard television monitor screen which may comprise part of the electronic video assembly illustrated in FIG. 1;

FIG. 3 is a block diagram of the various components making up the electronic video assembly;

FIG. 4 is a detailed schematic of one embodiment of a signal timing circuit utilized with the electronic video assembly of FIG. 1;

FIG. 5 is a detailed schematic of a video detector circuit utilized with the electronic video assembly of FIG. 1;

FIG. 6 is a detailed schematic of an edge detector and removal circuit utilized with the electronic video assembly of FIG. 1;

FIG. 7 is a detailed schematic of one embodiment of a logic and classification circuit and reject gate activator circuit utilized with the electronic video assembly of FIG. 1;

FIG. 8 is a detailed schematic of a second embodiment of a logic and classification circuit and reject gate activator circuit utilized with the electronic video assembly of FIG. 1; and

FIG. 9 is a detailed schematic of a second embodiment of a signal timing circuit utilized with the electronic video assembly of FIG. 1.

DETAILED DESCRIPTION

Turning now to the drawings, wherein like components are designated by like reference numerals throughout the various figures, an electronic video detect detection assembly, constructed in accordance with the present invention, is illustrated in FIG. 1 and is generally designated by the reference numeral 10. Also illustrated in this figure is a conveyor mechanism 12 positioned between various components of assembly 10 for transporting a train of glassware, such as, for example, glass bottles 14 past the assembly in the direction indicated by arrow 16.

As each bottle passes the assembly it is detected for defects or abnormalities generally, such as, for example, spikes or birdswings referred to hereinabove. In the event a detected bottle is detective, the electronic video assembly actuates a reject gate 18, positioned downstream from the assembly, for directing the defective bottle away from the conveyor mechanism and to a reject platform 20. In this manner, only the acceptable bottles are allowed to reach their ultimate destination on the conveyor mechanism for further processing. While a reject gate and platform are illustrated, it should be understood that any suitable reject means for removing a defective bottle from the conveyor may be provided. For example, a push-out arm (not shown) may be utilized for pushing the defective bottle off the conveyor mechanism.

As illustrated in FIG. 1, the electronic video assembly includes a semi-diffused light source 22 positioned on one side of and in close proximity to conveyor mechanism 12 for illuminating each of the glass bottles 14 as it passes thereby. In this regard, it should be noted that a more uniform distribution of light rays would be obtained if the semi-diffused light source were positioned further away from the passing bottles, such as, for example, two to ten feet therefrom. This, however, is not practical when the electronic video assembly is utilized in the typical glass manufacturing plant where space is at a premium. Accordingly, to remedy this problem, an optically-distant producing lens 24 may be mounted between light source 22 and conveyor mechanism 12. In this manner, the light rays emanating from the source are directed onto and through the passing bottles as if the light source were substantially further therefrom, such as, for example, two to ten feet, thereby providing more uniform light distribution.

A video camera 26, positioned on the opposite side of conveyor mechanism 12 and in alignment with semi-diffused light source 22, is provided for scanning each passing illuminated bottle so as to produce a representative standard video signal which, if desired, may be applied to a standard video monitor or display tube 28. In this regard, it should be noted that sudden changes in the refraction characteristics of the glass bottle being detected causes the light passing through these regions to be deflected in radically different directions compared to the surrounding material. As a result, those regions where the glass changes thickness rapidly appear darker than those regions displaying uniform thickness. Accordingly, the image of the detected bottle on a screen 30 (FIG. 2) of display tube 28 includes dark areas representing the rapid change in thickness of the detected bottle's leading and trailing edges, hereinafter referred to as edge 1 and edge 2, abnormalities such as the birdswing defects illustrated in FIG. 2, and any foreign objects on or in the bottle.

It is to be understood that the video display tube 28 is not required for the operation of electronic video assembly 10. However, it is of great help in initially calibrating the assembly and, in addition, will be of great assistance in understanding the operation thereof, as will be seen hereinafter.

The video signal produced by camera 26 is also directed to processing electronics, indicated by the reference numeral 32, which act upon the video signal to extract the dark areas. These dark areas are ultimately classified as edge signals, representing edge 1 and edge 2 of the detected bottle, and defect signals representing birdswing defects, spikes, or other abnormalities. If these classified signals meet certain criteria to be described hereinafter, the processing electronics produce a reject signal which is applied to reject gate 18 for actuating the reject gate and deflecting the defective bottle to reject platform 20.

Before turning to the description of processing electronics 32, attention is directed to another problem solved by the present invention. Specifically, it has been found that the movement of bottles 14 past camera 26 tend to slightly distort the camera's output video signal causing, for example, a blurred image to appear on screen 30 of the video pick-up tube. While the blurred image per se is of no consequence, the reason for the same, that is, the video distortion, can lead to slight inaccuracies in the detection of defects. Therefore, in accordance with the present invention, semi-diffused light source 22 may be provided with a strobe mechanism 33 for energizing and instantaneously thereafter de-energizing the light source in response to the appearance of a bottle 14. This is accomplished by positioning a photoelectric detecting deivce, such as photocell 35, between camera 26 and the passing bottle in direct alignment with light source 22 and connecting the device to the strobe mechanism for initiating the latter (only once) upon detection of each bottle. Since, for each passing bottle, the light source remains energized for a period of time (period of detection) substantially shorter than a single scan frame, camera 26 effectively sees a motionless object. Accordingly, video signal distortion caused by the moving bottles is eliminated.

While on the subject of light source 22, attention is briefly directed to a possible modification thereof. Specifically, a black mask 37, constructed, for example, of ordinary black construction paper, may be centrally positioned to the face of light source 22, as illustrated by dotted lines in FIG. 1, so that only a slight peripheral portion of the light source's face is exposed. The light rays emanating from the peripheral portion, if desired, may then be polarized and directed toward the passing bottle. By utilizing this type of black mask approach, the illumination effect on the passing bottles is a reversal of the effect described above. In other words, the edges and defects of each illuminated bottle appear bright while the remaining portion thereof appears dark, the same effect appearing on screen 30 of display tube 28. It has been found that by using the white-on-black approach, as opposed to the black-on-white approach, greater monitoring and detecting accuracy can be achieved. However, so as not to further complicate the description of the present invention, it will be assumed that the black-on-white approach is being followed, it being readily apparent that both approaches are contemplated by the present invention.

Turning now to FIG. 3, attention is directed to the block diagram of processing electronics 32, which processing electronics includes a signal timing circuit 34, a video detector circuit 36, an edge detector and removal circuit 38, a logic and classification circuit 40, and a reject gate activator circuit 42.

As illustrated in this figure, horizontal and vertical synchronization pulses which comprise part of the composite video signal developed by camera 26 are applied to the signal timing circuit which, in response thereto, produces eight complex signals, hereinafter referred to as HLEAD, HLEAD, HTRAIL, HTRAIL, VLEAD, VLEAD, VTRAIL, and VTRAIL. These signals, as will be described in more detail hereinafter, are provided mainly as reference signals for the overall operation of electronic video assembly 10 and, therefore, various ones thereof are applied to video detector 36, edge detector and removal circuit 38 and logic and classification circuit 40.

Attention is now directed to video detector circuit 36 which, as illustrated, receives the video portion of the video signal produced by the camera 26. The video detector circuit, which includes a high pass filter, buffer amplifier, and gated comparator, as will be seen hereinafter, responds to the video signal so as to produce a plurality of negative going spiked pulses 44 (dark spot signals), each of which represents a dark spot on the detected bottle and, therefore, on screen 30 of FIG. 2. In other words, as camera 26 scans an illuminated bottle 14, the right-hand spiked pulse illustrated in FIG. 3 represents the first appearing dark spot or the leading edge (edge 1) of the bottle while the left-hand spiked pulse represents the last-appearing dark spot or trailing edge (edge 2) thereof. In addition, in the event there is a birdswing such as the one illustrated in FIG. 2 or other defects positioned between the two edges, a third spiked pulse or dark spot signal will be produced by the video detector circuit. In this regard, it is to be understood that while the defect illustrated is that of a birdswing, the present invention contemplates any type of abnormalities which would cause an abrupt change in refraction of the light rays passing through the detected bottle or, in the case of an opaque object, a change in the reflection characteristics thereof.

The negative going spiked or dark spot pulses 44 produced at the output of the video detector 36 are applied to edge detector and removal circuit 38 which, as will be described with respect to FIG. 6, suppresses the spiked pulses representing edge 1 and edge 2 of the detected bottle and produces a negative going anomaly pulse 46 representing a defect such as the birdswing. In addition, the output of circuit 38 includes a negative pulse signal 48, hereinafter referred to as WIDE; a positive pulsed signal 50, hereinafter referred to as EDGE 1; a negative pulsed signal 52, hereinafter referred to as EDGE 2; and a positive pulsed signal 53, hereinafter referred to as FFSET.

All four of the output signals, along with defect pulse 46, are applied to logic and classification circuit 40 which utilizes these signals to produce a reject signal 54 at its output if the following requirements are met: firstly, that a bottle, or other article under observation, is, in fact, being detected during a given period of detection; secondly, that a complete bottle and not more or less than one bottle is being detected; and thirdly, that an abnormality such as a birdswing is detected. The remaining requirements for producing a reject signal are related to the status of detection during a period of time directly prior to the given period of detection. Specifically, during this prior period of bottle has no part of a bottle or article must have been detected, which is generally the case if the articles are spaced apart a sufficient distance or if the strobe mechanism 33 and photoelectric device 35 are utilized, only one edge of a bottle has been detected (referred to as 1/2 of a bottle), or three edges of two bottles have been detected (referred to as 1 1/2 bottles). It is readily apparent that the 1/2 bottle situation would exist for the first bottle to be detected or if the bottles are positioned a sufficient distance apart on the conveyor mechanism. On the other hand, the 11/2 bottle situation will exist if the bottles are positioned too close to each other. In this regard, the bottles should never be positioned so close that four edges can be detected simultaneously.

At first glance, the last set of requirements, that is, those related to the period of time prior to the given period of detection, do not appear to be necessary in providing the aforedescribed reject signal. However, as will be seen hereinafter, adding these requirements enhances the logic scheme and thereby provides more accurate means of defect detection.

It should be readily apparent that by utilizing strobe mechanism 33 and appropriately positioning photocell 38 so that the strobe mechanism energizes source 22 at a point in time when one complete bottle and only one bottle may be detected, the 1/2 bottle and 1 1/2 bottle situation will not occur since the source is inactive during these periods of time. Therefore, the components otherwise required for detecting these situations may be dispersed with when the strobe mechanism is used, as will be seen hereinafter with respect to FIG. 8.

When the above-stated requirements are met, logic and classification circuit 40 produces reject signal 54 which is applied to the reject gate activator circuit 42. If the reject gate 18 is in its non-reject position, circuit 42 will produce a gating signal 56 which is applied to the reject gate for moving it to the reject position. On the other hand, if the reject gate is already at its reject position, which will be the case if the directly preceding bottle were defective, then no pulse would be applied to the reject gate and it would remain in its reject position for deflecting the defective bottle onto reject platform 20. However, if during the given period of detection, the reject gate is in its reject position and the bottle being detected has no defect, a second gating signal 58 would be applied to the reject gate for moving the same back to its non-reject position so that the detected bottle may move freely past the reject platform. As stated hereinabove, the reject gate 18 may be replaced with a push-out arm. In this case, only one gating signal for actuating the push-out arm would be required, as will be seen hereinafter with respect to FIG. 8.

With assembly 10 generally described in the above manner, attention is now directed to the various detailed circuits making up the assembly and particularly FIG. 4 which illustrates one embodiment of that portion of signal timing circuit 34 which is responsible for producing the aforestated signals, HLEAD HLEAD, HTRAIL, and HTRAIL. Generally speaking, this circuit includes a pair of accurate, high duty factor monostable multivibrator circuits 60 and 62 which are triggered into their metastable state at the beginning of each horizontal scan line by a transistorized triggering circuit 64 which, in turn, is actuated by the horizontal synchronization signals from camera 26.

The monostable multivibrator circuit 60, which is in its metastable state for an independently adjustable length of time, is adjusted to time out shortly after the beginning of each horizontal line. While in its metastable state, the output of circuit 60 provides a +5 volt signal, hereinabove referred to as HLEAD. The multivibrator circuit 62, which is also in its metastable state for an adjustable length of time is adjusted to time out slightly before the end of each of the horizontal scan lines and, while in its metastable state, produces a +5 volt signal at its output, hereinabove referred to as HTRAIL. In addition, a pair of high-gain amplifier transistors 66 and 68 are respectively connected to the outputs of multivibrator circuits 60 and 62 and provide, at their respective outputs, the aforestated signals, HLEAD and HTRAIL. As will become apparent below, the signals HLEAD and HTRAIL are low when HLEAD and HTRAIL are high, that is, they are low when the multivibrators are in their metastable state and they are high, that is, +5 volts, after the multivibrator circuits have timed out.

Operationally, a horizontal synchronization pulse representing the beginning of a given horizontal scan line is differentiated by the combination of capacitor 70 and resistor 72 and is thereafter applied to the input of trigger circuit 64 which includes a NPN transistor 74 and biasing resistors 76 and 78. As illustrated in FIG. 4, the transistor 74 is tied across the positive 5 volt logic supply 80 and ground so as to produce a 5 volt negative going pulse 82 in response to the differentiated horizontal sychronization signal. Pulse 82 is simultaneously applied to multivibrator circuits 60 and 62 through diodes 84 and 86 respectively for triggering the multivibrator circuits into their metastable state.

The multivibrator circuit 60 includes a high input impedance comparator 88, associated resistors 90, 91, 92 and 94, diode 96 and capacitor 98. Multivibrator circuit 62, in like manner, includes a high input impedance comparator 100, associated resistors 102, 104, 106 and 108, associated diode 110 and associated capacitor 112.

The comparators 88 and 100 are driven by a positive 15 volt DC power supply 114, which is connected to ground through a filter capacitor 116, and a negative 15 volt DC power supply 118. In addition, the inputs of comparators 88 and 100 are respectively connected to potentiometers 120 and 122 which, in turn, are connected to another +5 volt DC logic supply 123, the pots being utilized to adjust and fix the duration in which the multivibrator circuits are in their metastable states.

Before going further, it should be noted that the resistor 94 and capacitor 98, associated with comparator 88 are connected so that the capacitor will charge quickly through the resistors 90 and 92 and diode 96, upon triggering the comparator 88, while, on the other hand, being discharged quite slowly through resistor 94. In this manner, the multivibrator circuit is capable of obtaining extremely high duty operation. The multivibrator circuit 62, which is connected up in the same manner as circuit 60, will, of course, provide the same high duty operation.

After the multivibrator circuits have been triggered and while they are in their metastable state, they provide positive 5 volt outputs which, as stated above, represent HLEAD and HTRAIL. In addition, these 5 volt outputs applied through resistors 130 and 132 respectively to the base of each of the high gain NPN transistors 66 and 68 which, as illustrated in FIG. 4, are connected across the 5 volt logic supply 80 and ground. Upon receiving the outputs from multivibrator circuits 60 and 62, the transistors are turned on so as to direct the current developed by logic supply 80 through resistors 96 and 104 directly to ground. Accordingly, the signals HLEAD and HTRAIL, which are connected across the transistors 66 and 68 respectively are substantially lower than the 5 volt logic supply and, therefore, are in their low states. On the other hand, when the multivibrator circuits time out, the transistors are turned off causing HLEAD and HTRAIL to be driven high by logic supply 80.

It is to be understood that electronic video assembly 10 includes a circuit, substantially identical to the circuit illustrated in FIG. 4, for producing the aforestated signals, VLEAD, VLEAD, VTRAIL and VTRAIL. The only substantial differences between these circuits reside in the manner in which they are triggered and the periods of timing in which they operate. Specifically, the V or vertical circuit is triggered by a vertical synchronization pulse so as to trigger its multivibrator circuits (analogous to circuits 60 and 62) into their metastable states. The particular circuit analogous to multivibrator circuit 60, that is, the circuit producing VLEAD and VLEAD, is adjusted to time out slightly after the beginning of vertical scan while the circuit analogous to circuit 62, that is, the circuit producing VTRAIL and VTRAIL, is adjusted to time out slightly before the end of the vertical scan. In this manner, VLEAD and VTRAIL are high when the multivibrator circuits are in their metastable state and VLEAD and VTRAIL go high when the multivibrator circuits time out.

As will be described in more detail below, when any of the signals, HLEAD, HTRAIL, VLEAD and VTRAIL, are low, video detector 36 is inhibited from responding to the video output of camera 26, thereby effectively creating a limited field of detection. This may be best exemplified by screen 30 of video display tube 28 shown in FIG. 2 which illustrates a window 140, shown by dotted lines, provided around the detected bottle 14. The area within the window represents the field of detection of video assembly 10 while the area surrounding the window represents the time in which VLEAD, VTRAIL, HLEAD and HTRAIL are high. The reasons for providing these time periods prior to and directly after effective scan detection will become apparent hereinafter. Briefly, however, they are provided as references for the operation of the remaining circuitry.

Turning now to FIG. 5, attention is directed to the detailed circuitry representing video detector circuit 36. As stated above, this circuit, which includes a high pass filter 142, a buffer amplifier circuit 144 and a gated comparator circuit 146, is provided for producing negative going spiked pulses or dark spot pulses 44 in response to the video portion of the video signal provided by camera 26. As also stated above, these negative going pulses are representative of the radically changing characteristics in refraction of the glass bottle being detected such as, for example, the edges of the bottle or defects which may appear therein.

As illustrated in FIG. 5, the video from camera 26 is first applied to high pass filter 142 which is an RC filter comprising resistors 145, 146 and 148 and capacitors 150 and 152, all of which combine to ground the lower frequency noise signals making up a part of the incoming video. In this manner, only the higher frequency information signals are applied to the input of buffer amplifier 144 which, as ihlustrated in FIG. 5, includes a comparator 154 tied across and operated by a positive 15 volts DC power supply 156 and a negative 15 volts DC power supply 158, a capacitor 160 and a resistor 162, the latter two of which are connected in parallel and across the comparator. A variable pot 164 is also provided with buffer amplifier circuit 144 and is connected to the input of comparator 154 through resistor 166 for adjusting the operation of the comparator.

Buffer amplifier circuit 144 cooperates with high pass filter 142 so as to tailor the incoming video signal so that sharp transitions appear at the output of the comparator as large spikes such as, for example, spike signal 168, while slow transitions cause little, if any, response. In this manner, the portions of the incoming video signal representing dark transitions in the detected bottle are enhanced and provide a suitable signal for comparator circuit 46. The situation would, of course, be reversed if the aforedescribed black mask is utilized.

The spiked signals 168 are applied through a filter amplifier stage comprising series connected resistors 170 and 171 and grounded capacitor 173 to the input of comparator circuit 146, the latter of which includes a high gain voltage comparator 172 which is also operated by DC power supplies 156 and 158, filter capacitor 174 and potentiometer 178 which is connected to the input of the comparator for providing adjusted to its operation. It should be noted that pot 178 may be set up with hysteresis so that a sufficiently large positive signal causes the comparator to switch negative whereupon a sufficiently larger negative signal causes it to switch positive again. Accordingly, a higher quality signal is attained at the output of the comparator.

Because comparator 172 may be of the type which operates on +12 volts DC and -6 volts DC, a +3 `volt zener diode 180 and associated capacitor 182 are connected between the positive 15 volt power supply 156 while a +9 volt zener diode 184 and associated capacitor 186 are connected between the comparator and the negative 15 `volt supply 158. In this manner, only positive 12 volts and negative 6 volts are applied thereto.

The comparator 172, cooperating with a +5 volts DC logic supply 190 connected to its output through a resistor 192, responds to the spiked pulse 168 to produce a +5 volt to zero going pulse, hereinabove referred to as negative going spiked pulse 44. As stated above, this pulse appears at every sufficiently dark spot (or light spot) on the detected bottle as the latter is scanned by camera 26. In this regard, the two potentiometers 164 and 178 determine what is sufficiently dark (or light).

As illustrated in FIG. 5, the signals, HLEAD, HTRAIL, VLEAD and VTRAIL, produced by the signal timing circuit 34, are applied to the comparator 172 through a NAND gate 194 and inverter 196. Operationally, if any one of these signals applied to the NAND gate goes low, a high signal is applied to the input of inverter 196 which, in turn, applies a low signal to the comparator for inhibiting its operation. In this manner, during the period when the horizontal multivibrator circuit 60 of FIG. 4 and its associated vertical multivibrator circuit are in their metastable states and during the period after which the horizontal multivibrator circuit 62 and its associated vertical multivibrator circuit time out, the comparator 172 (FIG. 5) is inhibited from providing a pulse 44 regardless of a detected change in light intensity by camera 26. Accordingly, the aforedescribed window of detection 140, illustrated in FIG. 2, is provided.

Turning now to FIG. 6, attention is directed to the edge detector and removal circuit 38 which, as stated previously, is provided for detecting the edges of the bottle being scanned by camera 26 and for suppressing or removing from further processing those dark spot pulses 44 representative thereof. Briefly, this is accomplished by applying pulses 44 produced at the output of video detector 36 to one input of a NAND gate 200 through an inverter 202 and lead 204. As will be seen below, the NAND gate is inhibited from producing an output pulse in response to those input pulses representing the leading edge (edge 1) and trailing edge (edge 2) of the bottle being detected while, on the other hand, producing an output pulse, hereinabove referred to as defect pulse 46, on lead 206 in response to those dark spot pulses representing a birdswing, spike or other such defect in the detected bottle.

More specifically, the first pulse 44 appearing on a given scan line after the end of the leading horizontal timing period, that is, the period when HLEAD is high, is classified as the leading edge, or edge 1, of the bottle being detected. This first pulse is applied through inverter 202 to one input of a two input NAND gate 208 which, in response thereto, applies a low signal to a high duty factor monostable multivibrator circuit 210 through a diode 212 for triggering the multivibrator circuit into its metastable state.

Monostable multivibrator circuit 210, which is substantially identical in function to the previously described monostable multivibrator circuits and which includes a comparator 214, resistors 216 and 218, diode 220 and quick charging and slow discharging capacitor 222, is driven by a positive 15 volt DC power supply 224 through a voltage stabilizing zener diode 226 and a negative 15 volt DC power supply 228 through a voltage stabilizing zener diode 210, both of the power supplies being grounded through filter capacitors 232 and 234.

Upon being triggered into its metastable state by the initial dark spot pulse 44, circuit 210 cooperates with a 5 volt logic supply 236 connected to the output of comparator 214 through a resistor 238 for producing a low voltage signal, hereinafter referred to as EDGE 1 for the duration that the multivibrator circuit is in its metastable state. In this regard the time in which the circuit is in its metastable state depends upon a potentiometer 240 connected at one end to the input of comparator 214 and at the other end to a positive 5 volt DC power supply 242.

Output signal EDGE 1 is applied to a second input of NAND gate 200 through lead 244 and inhibits the NAND gate from producing an output signal in response to the aforementioned first dark spot pulse 44 which is also applied to the NAND gate via lead 204, as stated above. In this manner, the dark spot pulse representative of the first edge of the bottle being detected is removed from further processing.

The output signal EDGE 1, in addition to being applied to NAND gate 200 is applied to the input of a two stage flip-flop 248 formed by dual NAND gates 250 and 252 which, in response to the signal, is triggered into its set state and provides a low signal, via lead 254, back to the otherwise free input of gate 208. In this manner, the gate is inhibited from allowing further dark spot pulses to reach multivibrator circuit 210. Therefore, only the first dark spot pulse 44 (leading edge pulse) on any given scan line will initiate the EDGE 1 signal. In this regard, it is to be noted that the output of gate 250 of the dual gate flip-flop is also applied to NAND gate 200, via lead 256. In this way, NAND gate 200 is inhibited prior to the appearance of EDGE 1 and the setting of flip-flop 248 for preventing the first dark spot pulse, applied through lead 204, from triggering the NAND gate in the event it reaches the latter before the EDGE 1 signal.

As stated above, flip-flop 248 is triggered into its set state by the first dark spot pulse 44 appearing on a given scan line and remains in this state for the entire scan line period. During the beginning of the next scan line when HLEAD goes low (during HLEAD time), the flip-flop is reset by HLEAD which, as illustrated, is applied to gate 252 of the flip-flop. In this manner, the flip-flop is again ready to be triggered by the first dark spot pulse appearing on this next following scan line.

Attention is now directed to the manner in which edge detector and removal circuit 38 detects the trailing edge, or edge 2, of the bottle being detected and removes the dark spot pulse 44 representative thereof from further processing. In this regard, it is to be noted that the last dark spot pulse appearing on any given horizontal scan line is classified as the trailing edge, or edge 2, of the bottle. As will be seen below, this pulse is detected on a particular horizontal scan line and initiates a timed delay signal, hereinafter referred to as EDGE 2, which appears on the following horizontal scan line and which inhibits NAND gate 200 for a predetermined period during which the trailing edge dark spot pulse on that following line appears at the NAND gate. In other words, the circuitry required for eliminating the trailing edge dark spot pulse is a memory circuit which remembers where the trailing edge, or edge 2, of the bottle being detected occurred on a previous line for suppressing a similar pulse on the following line.

The circuitry required to accomplish edge 2 suppression comprises a first transistorized triggering circuit including transistor 260, biasing resistors 262 and 264, diode 266 and an RC network including capacitor 268 and resistor 270 connected between the collector of transistor 260 and ground. Also included are comparator 272 driven by the aforestated positive and negative 15 volt power supplies 224 and 228 through voltage limiting zener diodes 226 and 230, a second transistorized triggering circuit including transistor 274, biasing resistors 276, 278 and 280 and diode 282, which triggering circuit is also connected to the 5 volt logic supply and a second RC network, identical to the previously referred RC network, and including capacitor 284 and resistors 286 and 288. The circuit further includes filter capacitors 290, 292, 294 and 296.

Operationally, each dark spot pulse 44 produced at the output of video detector circuit 36 is applied, via lead 300, through a limiting resistor 302 and diode 266 to the base of transistor 260 for triggering the transistor into its conductive state. This, in turn, allows capacitor 268 to charge to the 5 volt logic supply 236 and thereafter discharge through resistor 270. Accordingly, the voltage appearing at junction A connected between the capacitor and resistor and also one input of comparator 272 is a function of the time that has elapsed since the last dark spot signal reached the base of transistor 260.

It is to be noted that the HLEAD signal, provided by signal timing circuit 34, is also applied to comparator 272. In this manner, during the period in which HLEAD is low, that is, during the period when the electronic video assembly is detecting, the comparator is inhibited from going low. However, during the HLEAD time, that is, when HLEAD is high, the comparator output will be low as long as the voltage at a junction B is lower than the voltage at junction A, junction B being connected to the second-mentioned RC network and the otherwise free input of comparator 72. In other words, the comparator 272 is triggered into its low state at the beginning of the HLEAD time and remains in that state so long as the voltage at point A is greater than the voltage at point B. During this time, the transistor 274, which is connected to the output of comparator 272 through diode 282 and a limiting resistor 310, is maintained in its conductive state so that capacitor 284 begins to charge through the 5 volt logic supply 236. As the capacitor charges, the voltage at point B increases while the voltage at point A decreases due to the discharging or decaying of capacitor 268. At a certain point during this process, the voltage junctions A and B will be equal, which, in turn, will return the comparator 272 to its initial high-level state and thereby turn off transistor 274 so that the capacitor 284 begins to discharge. Accordingly, during HLEAD time, the voltage at point A is transferred to point B. Since, as stated above, the voltage at point A is a function of the time which has elapsed since the last dark spot pulse, the voltage at point B is also a function thereof. Further, since this last pulse was the last pulse appearing on the previous horizontal scan line and, therefore, classified as the edge 2 representative pulse, the voltage at point B is a function of the time which has elapsed since edge 2 or the bottle's trailing edge was detected on the particular horizontal scan line.

A comparator 312, which is ultimately responsible for producing the aforestated EDGE 2 signal and which is also driven by the positive and negative 15 volt DC power supplies 224 and 228, has one input connected to point B while the other input is connected to a 5 volt DC to ground potentiometer 314, the latter input also being grounded through filter capacitor 316. The comparator compares the voltage at point B with the adjustable voltage appearing across potentiometer 314. When the voltage at point B decreases, due to the discharging of capacitor 284, to a point less than that of the constant voltage across the potentiometer, the comparator output goes low so as to produce the EDGE 2 signal. This signal, which is maintained for a predetermined period of time, is applied, through lead 318, to the otherwise free input of NAND gate 200 so as to inhibit the NAND gate.

It should be readily apparent from the above description that the time in which comparator 312 goes low to produce EDGE 2 is dependent upon the voltage tapped off of adjustable potentiometer 314. This voltage is set so that the EDGE 2 signal is initiated slightly before the appearance of the dark spot pulse 44, representing the trailing edge, or edge 2, of the bottle being detected. In this way, gate 200 is inhibited from responding to this dark spot pulse. This operation repeats itself during each horizontal scan of camera 26, that is, each edge 2 pulse 44 on a given horizontal scan line triggers the aforedescribed memory circuit for initiating the EDGE 2 signal during the following horizontal scan line so as to thereby suppress the dark spot pulse appearing on that scan line.

As stated above, each dark spot pulse 44 is applied to transistor 260 via lead 300 for initiating edge 2, or trailing edge, suppression while being simultaneously utilized for initiating edge 1 suppression. However, it has been found that a second circuit, substantially identical to video detector circuit 36 (FIG. 5), may be provided for suppling the edge 2 initiating dark spot pulse 44. In this way, this second circuit may include a reduced bandwidth (i.e., less filtering) and, therefore, a higher quality pulse 44 for increasing the reliability of edge 2 suppression. This latter circuit would, of course, also be connected for receiving the video output from camera 26.

It should be equally readily apparent from the above description that NAND gate 200 is inhibited from producing any pulses for a predetermined period during and after the appearance of the first dark spot pulse (leading edge) and for a period before, during and after the appearance of the last dark spot pulse (trailing edge) on a given horizontal scan line. Accordingly, any pulse which appears at the output of this gate is caused by noise or some defect in the detected bottle such as, for example, a birdswing and, as stated above, is classified as a defect pulse 46.

As stated above, with respect to FIG. 3, EDGE detector and removal circuit 38 also provides at its output an EDGE 1 signal 50, and EDGE 2 signal 52, FFSET signal 53 and a WIDE signal 48, all of which are applied to the logic and classifications circuit 40, for reasons to be described hereinafter. The EDGE 2 output signal is provided by tapping off of the output of comparator 312 via lead 318 while the EDGE 1 output signal is provided by tapping off of the output of multivibrator circuit 210 and inverting the EDGE 1 signal by inverter 340, as illustrated in FIG. 6.

The WIDE output signal is produced by a second high duty factor monostable multivibrator circuit 342, which is substantially identical to the monostable multivibrator circuit 210 and which includes comparator 344, resistors 346 and 348, diode 350 and quick charging and slow discharging capacitor 352. The input of comparator 344 is connected to the output of gate 208, via lead 354 and diode 355, so that the monostable multivibrator circuit is triggered into its metastable state for providing WIDE by the same pulse that triggers monostable multivibrator circuit 210, that is, by the leading edge dark spot pulse 44. Circuit 342 remains in its metastable state for an adjustable length of time dependent upon the position of a potentiometer 356 also connected to the input of comparator 344. This length of time is normally set so that the multivibrator circuit times out slightly after the appearance of the trailing edge dark spot pulse 44, that is, slightly after the trailing edge of the bottle has been detected. As will be seen hereinafter with respect to FIG. 7, the WIDE, EDGE 2 and FFSET output signals cooperate to determine whether more than one bottle is being detected, while the EDGE 2 and EDGE 1 signals cooperate to determine whether only one edge of a bottle is being detected. In this regard, it should be noted that the produciton of the WIDE signal would not be necessary if the aforedescribed strobe mechanism and associated photocell were to be used in lieu of the 1 1/2 and one-half bottle detection situation, as stated hereinabove.

Turning now to FIG. 7, attention is directed to the detailed circuitry making up one embodiment of the logic and classification circuit 40. As briefly stated previously, this circuit is provided for applying a reject signal 54 to the reject gate activator circuit 42 (also illustrated in detail in FIG. 7) in the event certain requirements are met. As will be seen hereinafter and as stated above, these requirements take into account certain conditions which exist during a given period of detection (one scan frame) as well as certain conditions which existed during the directly preceding period of detection.

One of the requirements necessary for producing the aforestated reject signal at the output of logic and classifications circuit 40 is that, during the given or current period of detection, the bottle being detected includes a defect such that the aforestated defect pulse 46, provided at the output of edge detector and removal circuit 38, appears on at least three of four consecutive horizontal scan lines. By providing that a defect pulse must appear on three of four consecutive horizontal scan lines, defect detectivity is maximized while noise susceptibility is minimized. The circuitry necessary for determining whether such a condition has been met comprises a shift register 400 including four connected flip-flop stages, 402, 404, 406 and 408, a group of logic NAND gates including three-input NAND gates, 410, 412, 414, and 416, and four-input NAND gate 418, and an integrated circuit in the form of a D flip-flop 420.

Operationally, each of the defect pulses 46 produced during the given period of detection is applied to the first flip-flop stage 402 of shift register 400 which sets the flip-flop stage for producing a high output signal pulse. This high output pulse is applied to one input of each of the three-input NAND gates, 410, 412 and 414, via lead 422. As illustrated in FIG. 7, the HTRAIL signal derived from signal timing circuit 34 is applied to the clock input of the various flip-flop stages. In this manner, during the HTRAIL time, that is, when the HTRAIL signal is high, the contents in the various flip-flop stages are shifted forward. Accordingly, the high output signal produced at flip-flop stage 402 during a given horizontal scan line is shifted to the second flip-flop stage 404 at the end of that scan line, and so on. As illustrated, the output of flip-flop stage 404 is connected to an input of each of the NAND gates, 410, 412 and 416, via lead 424, the output of flip-flop stage 406 is applied to an input of each of the NAND gates, 410, 414 and 416, via lead 426, and the output of the last flip-flop stage 408 is applied to an input of NAND gates 412, 414 and 416, via lead 428.

It should be readily apparent that if three defect pulses 46 are produced during any four consecutive horizontal scan lines, one of the four NAND gates, 410, 412, 414 and 416, will go low at its output and, since the output of these NAND gates are connected to the inputs of four-input NAND gate 418, the latter will go high. This situation is classified as "defect detected."

The D flip-flop 420, which is driven by a 5 volt DC logic supply 430 and which is reset by the VLEAD signal derived from the signal timing circuit 34, is connected to the output of NAND gate 418. In this manner, when the output of NAND gate 418 goes high, the flip-flop is set true, that is, the Q output goes high (5 volts DC) while the Q output is low. Accordingly, the D flip-flop remembers that a defect such as, for example, a birdswing was classified during the given period of detection. As will be seen hereinafter, the Q and Q outputs of D flip-flop 420 are applied to a JK flip-flop 432 which includes three-input AND gates, 434 and 436, respectively connected to its J and K inputs, and which ultimately provide the aforestated reject signal 54.

Another condition which must be met during the given period of detection is that a bottle, in fact, is being detected. While this may appear self-evident and unnecessary in view of the foregoing, it should be realized that the aforedescribed logic circuitry responsive to the defect pulses 46 will not always indicate the presence of a bottle, that is, when there is no defect in the bottle being detected, a defect pulse 46 will not be generated and, therefore, will not indicate the presence of the bottle. Accordingly, the logic circuitry required to determine the presence of a bottle is necessary and includes a three-count counter 438 comprising two JK flip-flops, 440 and 442, which are driven by 5 volt DC logic supply 430 and two NAND gates, 444 and 446.

Operationally, the EDGE 1 signal, which, as stated above, represents the leading or first edge of the bottle being detected, is applied to the input of JK flip-flop 440. The two JK flip-flops are connected together so that if three EDGE 1 signals occur during the given period of detection the Q outputs of these flip-flops go high, driving the NAND gate 444 low and the NAND gate 446 high. Accordingly, if a high signal appears at the output of NAND gate 446, a bottle has been detected; and if a low signal appears at the output thereof, no bottle has been detected.

Another condition determined and indicated by logic and classification circuit 40 is whether one complete bottle, and only one bottle, is being detected or whether one-half bottle, that is, only one edge of a bottle or 1 1/2 bottles, that is, three edges of two bottles are being detected. The circuit utilized to determine and indicate these conditions includes NAND gates 448, 450, 452 and 454, three-count counter 456 comprising two interconnected JK flip-flops 458 and 460, and output NAND gate 462.

Operationally, in order to determine whether 1 1/2 bottles are being detected, the aforestated WIDE signal, FFSET signal and EDGE 2 signal, all of which are derived from the output of edge detector and removal circuit 38, are applied to the inputs of the three-input NAND gate 448. As stated above, the WIDE signal is a low signal which is initiated by the detection of the leading edge, or edge 1, of the bottle being detected and which remains in this low state for a period of time slightly longer than the width of the bottle, thereafter going high. The FFSET signal, as stated above, is a high signal which remains high for the entire horizontal scan line, and the EDGE 2 signal is a low signal during the period in which the last or trailing edge is detected. If the EDGE 2 signal is still high, that is, if the last or trailing edge has not been detected after the WIDE signal goes high and while the FFSET signal is still high, a low pulse will be produced at the output of NAND gate 448 and, therefore, initiates a high pulse at the output of NAND gate 450 which, as illustrated in FIG. 7, is connected to the output of gate 448. This means that the EDGE 2 signal has been encountered a substantially longer time after it should have been detected (as evidenced by WIDE going high before the appearance thereof) and, therefore, means that 1 1/2 bottles are in fact being detected.

In order to determine whether only one-half bottle is being detected, the EDGE 2 signal is also applied through NAND gate 452, which acts as an inverter gate, to one input of NAND gate 454, which NAND gate also receives, at its other input, the EDGE 1 signal. If EDGE 2 and EDGE 1 occur at the same time, that is, if the same dark spot pulse 44 initiates both of the circuits of FIG. 6, providing EDGE 1 and EDGE 2, then this pulse represents both the first appearing pulse (leading edge) and the last appearing pulse (trailing edge) and, therefore, indicates the presence of one edge or one-half bottle. In the event this occurs, a low pulse is produced at the output of NAND gate 454, which is applied to NAND gate 450 so as to produce a high pulse signal at its output.

Accordingly, if either 1 1/2 bottles are being detected or only one-half bottle is being detected, NAND gate 450 will apply a high pulse signal to the input of three-count counter 456. If three of these high pulsed signals appear during a period of detection, the counter 456 will go high, driving the NAND gate 462 low.

As illustrated in FIG. 7, the outputs of NAND gates 446 and 462 are connected to the inputs of a NAND gate 464 which, in turn, is connected to the inputs of a NAND gate 466. The output of NAND gate 466 is connected to a D flip-flop 468 and also to an input of each of the AND gates, 434 and 436. Operationally, if the output of NAND gate 462 is low, that is, if either 1 1/2 bottles or one-half bottle is detected, or if the output of NAND gate 446 is low, that is, no bottle is detected at all, NAND gate 464 is driven high and NAND gate 466 is driven low. This last-mentioned low signal is applied to the input of D flip-flop 468 which, as illustrated, is also connected to the VTRAIL signal. Accordingly, during the VTRAIL time, that is, when VTRAIL is high, this low signal is shifted to the output of the D flip-flop so that the output remains in that state until VTRAIL goes high again. In this manner, during a given period of detection, the output of flip-flop 468 designates whether 1 1/2 bottles, one-half bottle or no bottle was detected during the preceding period of detection. For reasons to be explained hereinafter, the output of D flip-flop 468 is applied to the respective inputs of AND gates 434 and 436.

The output from NAND gate 466, in addition to being applied to the D flip-flop 468, is also applied to respective inputs at AND gates 434 and 436. This signal, as stated above, designates whether one, and only one, bottle is being detected or whether no bottles, one-half bottle or 1 1/2 are being detected during the given period of detection.

Briefly summarizing the above, if, during the given or current period of detection, one, and only one, bottle is detected, a high signal is appplied from the output of NAND gate 466 to respective inputs of AND gates 434 and 436. If, during this same period of detection, there is a defect in the bottle being detected, a high signal is applied from Q output of flip-flop 420 to another input of AND gate 434, while a low signal is applied from the Q output of the same flip-flop 420 to another input of AND gate 436. Finally, if, during the period of detection directly preceding the given or current period of detection, either no bottle was detected, one-half bottle was detected or 1 1/2 bottles were detected, a low signal is applied, during the given period of detection, to the remaining inputs of AND gates 434 and 436.

Attention is now directed to the manner in which the reject decision JK flip-flop 432 responds to the signals applied to the inputs of AND gates 434 and 436. Specifically, if one, and only one, bottle is being detected during the given period of detection, if the bottle being detected contains a defect and if, during the directly preceding period of detection either no bottles, 1 1/2 bottles or one-hlaf bottle were detected, the Q output of flip-flop 432 goes high and the Q output goes low. The flip-flop remains in this state during the detection of subsequent bottles so long as the aforestated conditions remain the same. However, if a subsequently detected bottle does not contain a defect but the other conditions remain the same, the flip-flop will change states, that is, the Q output will go low and the Q output will go high. In other words, for the JK flip-flop 432 to change states, one of two successively detected bottles must contain a defect while the other does not and, further, all of the other aforestated condtions must be met. As will be seen hereinafter, it is this change in states of flip-flop 432 which comprises the aforestated reject signal 54 and which initiates the reject gate activator circuit 42.

Attention is now directed to the reject gate activator citcuit 42 comprising a first conventional monostable multivibrator circuit 500 which is driven by a 5 volt DC logic supply 502, a second conventional monostable multivibrator circuit 504 which is driven by a 5 volt DC logic supply 506 and which is connected to the output of circuit 500 and to NAND gates 508 and 510. Because the multivibrator circuits are conventional, a component description thereof will not be necessary.

Operationally, when the JK flip-flop 432 changes states, the monostable multivibrator circuit 500 is triggered into its metastable state and remains in this state until the bottle being detected reaches reject gate 18 (FIG. 1). When circuit 500 times out, monostable multivibrator circuit 504, which isconnectd to the output thereof, is triggered into its metastable state and remains in this state for a period of time which is sufficient to move the reject gate either from its non-reject position to its reject position or from its reject position to its non-reject position. During this period of time, a high signal is applied from the output of circuit 504 to one input of each of the NAND gates, 508 and 510. As illustrated in FIG. 7, the Q output of flip-flop 432 is also connected to the otherwise free input of NAND gate 508 while the Q otuput is connected to the otherwise free input of NAND gate 510. Accordingly, during the period of time when circuit 504 is in its metastable state, if the Q output of flip-flop 432 is in its high state, the NAND gate 508 will provide the aforedescribed gate actuating signal 56 to reject gate 18 for moving the same from its non-reject position to its reject position. On the other hand, if, during the period when circuit 504 is in its metastable state, the Q output is high, the NAND gate 510 will provide the aforedescribed pulse 58 for moving the reject gate from its reject position to its non-reject position. In this manner, it takes a defective bottle to move the reject gate from its non-reject position to its reject position and it takes a non-defective bottle to move the gate back to its non-reject position.

With electronic video defect detection assembly 10 constructedand operated in the aforedescribed manner, attention is now directed to FIG. 8 which illustrates a second embodiment 600 of the logic and classification circuit, which embodiment can be utilized in lieu of logic and classification circuit 40 in the event strobe mechanism 33 and photocell 35 are provided. As seen in this figure, embodiment 600 includes substantially the same circuitry, that is, shift register 400 and NAND gates 410 to 418, for classifying a defective bottle as the aforedescribed circuit 40 of FIG. 7. In addition, a selection switch 602 may be connected between the shift register and NAND gates for selectively choosing the number of scan lines in which a defect appears during any given period of detection must appear before a defect is classified. For example, instead of classifying a bottle as defective after defect pulses have appeared on three of four consecutive scan lines, the operator may wish to classify a bottle as defective in the event a defect pulse appears on two of three consecutive scan lines, three of three consecutive scan lines, and so on.

As illustrated in FIG. 8, logic and classification circuit 600 does not include the aforedescribed circuitry required for determining whether one complete bottle, and only one bottle, is being detected during the given period of detection or that no bottles, 1 1/2 bottles or one-half bottle was detected during the previous period of detection. Rather, circuit 600 includes circuitry 604 responsive to an output signal from previously described photocell 35 for initiating strobe mechanism 33 when the former detects the presence of a moving bottle. Specifically, circuitry 604 includes a double inverted amplifier comprising a pair of series connected NAND gates, 606 and 608, 5 volt source 610 and voltage limiting diode 612 which receives, amplifies and conditions the output signal from photocell 35. This signal is then provided for setting the first of two flip-flops, 614 and 616. The VLEAD signal from signal timing circuit 34 is also applied to flip-flop 614 and, upon receipt thereof, flip-flop 614 resets, causing its Q output to produce a signal for firing strobe mechanism 33. In this manner, the strobe is not fired in the middle of a scan frame, even though the photocell may have detected a bottle at that time, but rather waits until the beginning of the next scan frame.

As illustrated in FIG. 8, the Q output of flip-flop 614 is connected to flip-flop 616. In this way, upon being reset, flip-flop 614 sets flip-flop 616 which has its output connected to one input of a NAND gate 618, the other input of which is connected to receive the defect classification signal from NAND gate 418. Accordingly, the defect signal classification circuitry is synchronized with the strobe mechanism so that a reject signal is produced at the output of gate 618, only if a defect is actually classified and flip-flop 616 has been set (the strobe has been fired).

In the event of a defective bottle and with the above-stated conditions met, the reject signal is provided at the output of gate 618 and is applied to the first of a series of conventional multivibrator circuits, 620, 622, 624 and 626, all of which make up a second embodiment 630 of reject gate activator circuit 42. Upon receipt of the aforestated reject signal, multivibrator 620 is driven to its metastable state and remains there for a predetermined period of time. After the timing out of multivibrator 620, multivibrator 622 goes to its metastable state for a predetermined period of time. This continues down the line until multivibrator 624 times out, whereupon the output signal from this last multivibrator is provided for initiating a defective bottle reject means such as, for example, the aforedescribed push-out arm, thereby removing the defective bottle from the conveyor mechanism 12.

It should be readily apparent that the overall time required for all of the multivibrators to time out is the same as the time required for the defective bottle to reach the push-out arm from the detection point. In this regard, it should be noted that the timing periods for the multivibrators can be adjusted by a potentiometer 632 and associated direct current amplifier circuit 634 which respectively operate on 5 volt and 15 volt power supplies.

Turning to FIG. 9, attention is directed to a second embodiment 650 of the aforedescribed horizontal and vertical signal timing circuits 34. The two circuits ultimately operate in the same manner for providing the eight reference signals, HLEAD, HLEAD, HTRAIL, HTRAILS, VLEAD, VLEAD, VTRAIL and VTRAIL. However, embodiment 650 uses standard integrated multivibratorcircuits 652, 654, 656 and 658 in lieu of the compacitors 88 and100 and respectively associated transistor amplifiers 66 and 68 comprising part of the multivibrator circuits of embodiment 34 (FIG. 4).

Specifically, as illustrated in FIG. 9, the horizontal synchronization pulses provided from camera 26 are applied to the inputs of multivibrator circuits 652 and 654 through an amplifier stage 660 which is driven by a 5 volt supply 662. On the other hand, the vertical synchronization pulses provided from camera 26 are applied to the inputs of multivibrator circuits 656 and 658 through an amplifier stage 664 which is also driven by supply 662.

The multivibrator circuits 654 and 652, which are driven into their metastable staes for a predetermined period of time by a horizontal synchronization pulse, are respectively responsible for the procudtion of HLEAD, HLEAD, and HTRAIL, HTRAIL, while circuits 658 and 656, which are driven into their metastable states for a predetermined period of time by a vertical synchronization pulse, are respectively responsible for the production of VLEAD, VLEAD, and VTRAIL, VTRAIL. In this regard, the timing of each of the multivibrator circuits, 652, 654, 656 and 658, may be adjusted by respectively connected potentiometers, 666, 668, 670 and 672.

Although various embodiments of the present invention have been illustrated and described, it is anticipated that various changes and modifications will be apparent to those skilled in the art, and such changes may be made without departing from the scope of the invention as defined by the following claims.