Bouchard, Richard J. (Amherst, NH)
Sanders, William R. (Palo Alto, CA)

05/077490

05/01/1973

10/02/1970

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Sanders Associates, Inc. (South Washua, NH)

345/160

345/168

G06F3/023; G06F3/14

340/324A,365 315/18 235/197,198

Caldwell, John W.

Curtis, Marshall M.

What is claimed is

1. Keyboard operated display apparatus in which an operator causes the displacement of a visible cursor marker on a cathode ray tube screen by actuating the keyboard keys in a selected sequence so as to form a pattern on the screen, said apparatus comprising:

2. The invention according to claim 1 wherein said keyboard further includes a switch having first and second states which enable and inhibit, respectively, the visible display of vectors by said vector display means in response to the actuation of said vector keys.

3. The invention according to claim 2 wherein said vector and cursor display means include

4. The invention according to claim 3 and further including

5. The invention according to claim 4 wherein said unblank circuit includes an unblank gating net which receives said vector draw signal to produce said intensity control signal.

6. The invention according to claim 5

7. The invention according to claim 1 wherein said vector and cursor display means includes

8. The invention according to claim 7 and further including

9. The invention according to claim 8 wherein said unblank circuit includes an unblank gating net which receives said vector draw signal to produce said intensity control signal.

10. The invention according to claim 9

11. Display apparatus as set forth in claim 2

BACKGROUND OF THE INVENTION

This invention relates to novel and improved display apparatus and in particular to display apparatus for displaying graphics under the control of an operator in real time (i.e., a relative short response time).

It is known to control the display of alphanumeric characters in real time on a display screen, such as the screen of a cathode ray tube (CRT), by means of keyboard entry devices. For example, U.S. Pat. No. 3,501.746 to Michael K. Vosbury discloses an alphanumeric character type display which can be controlled by operation of a keyboard to not only display characters but also to perform various editing operations so as to modify the displayed data. The editing may take the form of insertion or deletion of various displayed characters, changes in location of selected characters or groups of characters. Thus, displayed textual data may be modified for correction or updating purposes. As pointed out in the Vosbury patent, this editing feature is useful for correcting errors made by a keyboard operator at a data entry point as well as to correct or update data stored in a digital information system. Another useful editing feature described in the Vosbury patent is the use of a pair of "delimiting character" codes to protect alphanumeric codes which are located between the delimiting codes from alteration by the keyboard operator. This guarded or protected data feature is useful in overlay applications in which, by way of example, the data format of a standard form is protected by the delimiting codes.

It is also known to display graphics on a display screen. In one known system, a keyboard operator enters a graphical pattern in a computer system by specifying it in equation form as one variable being equal to a function of another. The computer system then formats the entered function into a sequence of line segment codes. The operator must then request display of the function on a display screen associated with his keyboard. The function then appears on the screen as a strung together sequence of the line segments. One of the advantages of this system is that the line segment codes can be prepared in formats which are compatible with alphanumeric codes. This type of graphical display apparatus finds limited use since it required a painstaking entry of the graphical pattern in alphanumeric text, requiring special knowledge and skill of the operator.

In a further type of graphical display, graphics may be generated in real time on the display screen by use of either the alphanumeric keyboard or by use of a light responsive device. This type of display system generally requires point-to-point vector or line drawing and therefore requires more bits in the code to describe a vector. Thus, each vector requires four codes to describe its end points, two codes for the coordinates of each end point. This, of course, requires substantial hardware which, though justified where accuracy is desired, is hardly justified in cases where accuracy is not critical.

BRIEF SUMMARY OF INVENTION

An object of the present invention is to provide novel and improved graphical display apparatus.

Another object of the invention is to provide display apparatus in which either graphics and/or alphanumerics can be entered onto a display screen in real time.

Still another object is to provide a novel and relatively inexpensive graphical display in which a relatively unskilled operator may create graphical images on the display screen in real time.

Yet another object is to provide a novel graphical display in which a graphical keyboard is employed to enter incremental line segments for display upon a display surface.

Graphical display apparatus embodying the invention includes a keyboard having keys labeled with differently sloped incremental vectors or line segments. Actuation of the keyboard keys provides codes indicative of the slopes (directions) of the corresponding vectors to a display tracer. The display tracer responds to the codes to trace a pattern upon the display screen which consists of a strung together sequence of the incremental straight line segments or vectors.

In a preferred embodiment, the display screen is the screen of a cathode ray tube and the tracer comprises the cathode ray tube deflection coils, intensity control and associated display circuits. The codes are coupled from the keyboard by way of a refresh memory and editing control therefor to the display circuits which develop X and Y deflection voltages and an intensity control signal for the cathode ray tube.

According to one feature of the invention, a cursor is employed to indicate the memory storage location where the next incoming code will be stored. The display circuits respond to the addressing of the cursor indicated storage location to visibly display a cursor marker on the screen. As each vector key is actuated, the display circuits display the cursor marker at a screen location which is displaced from its most previous screen location in a direction corresponding to the vector slope of the actuated key.

In a further aspect of the invention, the keyboard includes means for conditioning the display circuits to displace the cursor marker on the CRT screen in response to each actuated vector key without visibly tracing the vectors associated with the actuated keys.

BRIEF DESCRIPTION OF THE DRAWING

In the accompanying drawings like reference characters denote like structural elements; and

FIG. 1 is a perspective view of a display console and graphics keyboard apparatus embodying the invention;

FIG. 2 is a block diagram of display apparatus embodying the invention;

FIG. 3 is a block diagram illustrating the encoding mechanism for the graphics keyboard;

FIG. 4 is a timing diagram illustrating the display timing cycle employed by the illustrated embodiment;

FIG. 5 is a block diagram of the display circuits embodying graphical display apparatus of the invention; and

FIG. 6 is a block diagram in part and a logic diagram in part of the unblank control mechanism of the FIG. 5 display circuits.

DESCRIPTION OF PREFERRED EMBODIMENT

It is contemplated that graphical display apparatus embodying the invention may be employed in any suitable display system in which a tracing means is employed to trace an image on a display surface. However, by way of example, the invention is herein illustrated as embodied in a cathode ray tube (CRT) display system design which incorporates many of the features described in the aforementioned Vosbury patent.

Referring now to FIG. 1 there is shown a display console having a CRT display surface 10 and keyboard entry means illustrated as a alphanumeric keyboard unit 11a and a graphical keyboard unit 11b. Each of the keyboard units includes encoding devices which respond to the actuation of the keys to provide coded binary signal or bit patterns to an editing and memory control unit 22 via an OR network 21 as shown in FIG. 2. The editing and memory control unit, for example, may be similar to the one described in the aforementioned Vosbury patent. The control unit 22 includes an I/O section (not shown) which receives the incoming codes from the keyboard units as well as controls the incoming and outgoing codes to an information storage device, shown as a computer 23. The control unit I/O section, thus, performs the customary handshaking routines of handling data requests. Since disclosure of these routines are unnecessary to an understanding of this invention, they are not illustrated herein and will be omitted from the following description.

The editing and control unit 22 is shown to include an addressing unit 22a for addressing the storage locations of a refresh memory 24 on a refresh basis. Control unit 22 also includes a write section 22b which responds to the incoming codes from the keyboard units to write them into those addressed storage locations which are indicated or pointed to by a cursor indicator 22c. That is, an incoming code is written into a storage location which is indicated by the cursor when such cursor indicated location is addressed. The cursor indicator may take any of several forms as, for example, a cursor counter (not shown), the contents of which point to the memory storage location where the incoming code is to be stored. As each incoming code is stored, the cursor counter value would then be changed so as to point to another storage location. On the other hand, the cursor indicator could be a unique code which occupies a storage location indicative of the location where the next incoming code will be stored. As each incoming code is stored in the cursor indicated location the cursor code is then stored in another storage location. This latter type of cursor indicator is assumed to be employed in the illustrated embodiment. The cursor indicator 22c then includes the circuitry in the control unit 22 which enables the write section 22c to write an incoming code in the storage location occupied by the cursor code.

The control unit 22 further includes a read unit 22d which reads the addressed storage locations so as to present the stored codes to a data register 25. The data register 25 is shown as connected in a loop with the control unit and memory such as would be the case in a recirculating memory of the type mentioned in the Vosbury patent. The codes in the data register 25 are interpreted by the display circuits 26 which provide the X and Y deflection signals and the unblank or intensity control signal to CRT 27 so as to modulate the intensity of the electron beam of the CRT thereby tracing a selected pattern on the screen 10. The display circuits 26 also respond to the addressing of the cursor indicated storage location to visibly display a cursor marker on the CRT screen 10 so as to give a visual indication of where the next entered vector or alphanumeric character will be displayed.

The control unit 22 includes many of the editing features discussed in the Vosbury patent, such as insertion or deletion of various displayed characters and changes in location of selected characters or groups of characters. Some of the control codes, which control these operations as well as others, can be inserted into the stored code sequence from the alphanumeric keyboard unit 11a. Thus, in FIG. 1 keyboard unit 11a is shown to have keys labeled vt (vertical tab), ht (horizontal tab), cr (carriage return) and h (home). The home code always signals the display circuits to return the visible cursor from its current location to the upper left hand corner of the screen 10.

Referring again to FIG. 1, the graphical keyboard 11b includes a set of incremental line segment keys 12, each of which is associated with or labeled by differently sloped ones of a set of line segments. In the indicia design shown in FIG. 1, the keys 12 are not themselves actually labeled but are located adjacent the outside points of the line segments set which is arranged in a star type pattern. It will be appreciated that other indicia layouts may be employed in other embodiments of the invention. Although any number of line segment direction or slopes may be employed, only sixteen such slopes are used in the illustrated design.

To create a desired image the keyboard operator merely depresses the keys 12 in a desired sequential pattern. As each key 12 is depressed the display circuits respond to trace a line segment of corresponding direction on the CRT screen 10 and to trace a cursor marker at the end point thereof. As the next selected key 12 is depressed the display circuits trace another incremental line from the end point of the previously traced line segment and trace the cursor marker at the end point thereof, and so on. Thus, as each vector key is depressed, the cursor marker is displayed at a screen location which is displaced from its most previous screen location in a direction corresponding to the slope of the associated vector key.

The use of 16 slopes (or less) is desirable since the different slopes can be encoded with only four binary bit positions. If two other bit positions are employed for segment length and unblank (visible), the resulting six bit total is compatible with the seven bit ASC11 code which is frequently employed by alphanumeric keyboard encoding units. Consequently, the line segment or vector codes can be processed by the same display circuits which are used to process the alphanumeric codes. In FIG. 3, the graphical keyboard is shown to provide in response actuation of its keys a seven bit code on signal leads KB1-KB7. A slope encoder 17 responds to the actuation of the keys 12 to provide the four least significant bits indicative of a vector slope on leads KB1-KB4. The bit position KB5 and KB6 are employed to denote line segment or vector visibility (unblank) and vector length respectively. The seventh bit (lead KB7) is always the complement of bit six so as to define the set of vector codes.

Vector length in the illustrated embodiment is controlled by means of graphical key 13a and associated signal lamp 13b to be of either one unit length or two unit lengths. To effect this control, the keyboard switch 13a is shown in FIG. 3 to trigger or toggle a flip-flop 18 upon each closure or depression thereof. The Q output of the flip-flop 18 is employed to determine the bit value of bit position KB6 as well as to control the driving power for the signal lamp circuit 13b. For instance, if lamp 13b is turned on, the Q output of flip-flop 18 is high and the KB6 bit position would have a bit value of 1. This condition corresponds to a vector of 2 units. For the other condition where the Q output of flip-flop 18 is a 0, the lamp 13b is turned off and the vector length will be interpreted as one unit.

Vector visibility is also controllable by the keyboard operator by means of a vector visibility key 14a and indicated by an associated signaling lamp 14b. As shown in FIG. 3 the vector visibility function employs circuitry which is similar to that employed for the vector length function. In this case, however, a flip-flop 19 is triggered by the vector visible switch 14a and its Q output is coupled to the bit position KB6 as well as to the driving circuits for the signal lamp 14b. For the condition where signal lamp 14b is turned on, the vector trace will be visible. When the lamp 14b is turned off, the vector trace will be invisible. The use of invisible vectors is important for the gross positioning of the CRT beam as well as for the "hidden lines" feature of the invention. In gross positioning the CRT beam may be moved from one location on the screen to another with the beam blanked or turned off. The hidden lines feature which is useful to construct three dimensional views, such as the cube shown on the display screen 10, is controllable by a hidden lines key 16 on keyboard 11b. Depression of key 16 causes a flip-flop 20 to toggle and provide a signal level on its Q output. The signalling level is coupled to the CRT display circuits so as to cause all vectors traced as invisible vectors to be displayed as dashed lines. Accordingly, the keyboard operator could view the cube either with or without its hidden lines by merely operating the key 16.

The graphical keyboard 11b also includes another control key 15a, designated as Mode, and associated lamp 15b designated as Vector. The purpose of this key and associated lamp is to control the operating mode of the display system between an alphanumeric mode and a vector mode. When the lamp 15b is on, the display circuits interpret the inputted ASC11 codes as vector codes so as to trace a graphics pattern. On the other hand when the lamp 15b is turned off, the inputted ASC11 codes are interpreted as alphanumeric codes so as to trace alphanumeric symbols upon the CRT screen.

The principle of the mode control is as follows. All the character codes to be displayed are stored in the refresh memory of the display system. The display circuits respond to the characters as they are read out of the refresh memory to trace a corresponding symbol upon the CRT screen. When a mode control character is encountered in the read out sequence, the display circuits respond thereto to change their interpretive mode for the next succeeding characters in the sequence. Thus, if the system is in an alphanumeric mode and a mode control character is detected, the system changes over to the vector mode. On the other hand if the system is in the vector mode and a mode control character is detected, the system switches over to the alphanumeric mode. Thus, the display system changes from one to the other of the vector and alphanumeric modes whenever a mode control code is detected.

The mode control codes are entered into the display refresh memory by means of the aforementioned mode key 15a. To this end, key 15a is shown in FIG. 3 to couple V _cc to the slope encoder 17 as well as to the reset R terminals of the flip-flops 18 and 19 so as to produce a unique code which is indicative of a mode change. This unique code is responded to by the display circuits to provide mode control signal levels which are discussed later. Suffice it to say here that one of those mode signal levels V (Vector mode) is operable to turn the driving circuits for lamp 15b on during the vector mode and off during the alphanumeric mode.

The mode control is also useful to switch from the vector mode to the alphanumeric mode for gross positioning when it is desired to use the hidden lines feature so that the gross position moves are not visible. In the alphanumeric mode, gross positioning can be achieved by use of horizontal tab (ht), vertical tab (vt), carriage return (cr) and home (h). The use of the vertical tab, horizontal tab and carriage return functions to gross position the electron beam is self explanatory. As mentioned previously, the home character always returns the display cursor, and hence the electron beam, to the upper left hand corner of the CRT screen. In addition, the appearance of a home code in the stored code sequence is always interpreted by the display circuit in such a way as to cause the system to switch to the alpha-numeric mode, if in the vector mode. The remainder of these control codes and a null code are detected by the display circuits when in the vector mode but are not responded to. For this reason, these codes are hereinafter referred to as NO-OP codes when they appear during the vector mode.

Turning again to FIG. 2, the display system operates under the control of a timing pulse distributor or clock 28. Germane to the present invention is the timing cycle of the normal alphanumeric operating mode. This timing cycle is shown in the timing diagram of FIG. 4 to be a 21 microsecond interval with timing pulses T1 through T21 occurring during like numbered time slots. In order to save space on the drawing only three of these timing pulses T1, T2 and T3 are shown in FIG. 4. The remainder of the timing information shown in FIG. 4 will be discussed and referred to in the following description of the display circuits.

Referring to the display circuit block diagram of FIG. 5 the data register 25, previously shown in FIG. 2, has been reproduced for convenience. When each code from the refresh memory has serially entered the data register 25, a new timing cycle is commenced. The code in register 25 is then loaded into a buffer register 30 and during the time slots T1 through T8 is serially transferred back to the control unit 22 in FIG. 2.

Although the display circuits may employ any suitable character generation scheme, the illustrated display circuits in FIG. 5 employ the racetrack character generation technique. A character generator of this type is described in U.S. Pat. No. 3,423,636 to Bouchard, et al. In brief, a racetrack display apparatus has two subsystems which operate in synchronism with one and another. A deflection subsystem develops positioning voltages which move the CRT beam to a position on the screen where the next character is to be formed. Each time the beam arrives at a new position, the deflection subsystem develops a pair of deflection voltages for deflecting the beam to trace at that position a pattern having all the strokes required to form all the characters the system is capable of displaying. Simultaneously, an unblanking subsystem processes the incoming character code and develops a succession of unblanking signals timed to turn the beam on only when the deflection subsystem produces the voltages for tracing the stroke needed to form the identified character.

In FIG. 5 an alphanumeric code processor 29 decodes the character codes contained in buffer register 30 so as to produce for each code at its output a data stream during the time slots T1 through T21. As shown in FIG. 4, this data stream consists of a synch bit during slot T1, a gross positioning code during slots T2 through T4, an unused slot T5 and the unblank data stream from slots T6 through T21. For the alphanumeric mode the data stream is gated via an AND gate 33 and OR gate 35 to a data bus 36. For this gating, the AND gate 33 is enabled only during the alphanumeric mode by the A/N control level.

During time slots T2 through T8, the bits in like numbered time slots are gated into a position and vector register 37. When register 37 has received the bits in slots T2 through T4, the position code is decoded by a decoder 38. The output of decoder 38 is then applied to a gross positioning device 39. The gross positioning device 39 includes X and Y counters which respond to the position code to change their respective count values to the character space row (x) and column (Y) at which the current character is to be traced. Not shown separately but included in the gross positioning device 39 are digital to analog converters which convert the count of digital outputs to X and Y analog gross deflection signals. The X and Y gross deflection signals are applied to the CRT X and Y deflection coils via summation amplifiers 40 and 41, respectively, to deflect the beam to the designated character space.

During the interval from T6 to T21 a racetrack generator 42 provides to an X and Y ramp generator 43 over 6 leads a sequence of digital numbers (groups of digital signals). This sequence of digital numbers causes the ramp generator 43 to produce a pattern of X and Y deflection voltages having all the strokes required to form all the characters the system is capable of displaying. These X and Y voltages are summed in summing amplifiers 40 and 41 with the gross positioning deflection signals and then applied to the CRT deflection coils.

Simultaneously with the generation of the racetrack pattern during the interval T6 through T21, the unblank data stream is passed from the data bus 36 via an unblank control 44 to unblank (or make visible) only those ones of the racetrack strokes which are required to form the currently designated character. The alphanumeric operating mode continues for successive character codes during successive 21 microsecond intervals.

Whenever a mode character is encountered by mode decoder 31, the mode flip-flop 31 changes its state and the condition of the A/N and V control levels. AND gate 33 becomes disabled and AND gate 34 becomes enabled to pass the character codes contained in data register 25 to the data bus 36 during the time slots T1 - T8 via OR gate 35.

Before discussing the operation during vector mode, the operation during the cycle when the mode character is detected deserves some attention. The mode flip-flop 32 is shown to change its state during a time slot T5 so as to prevent the gating of the unblank data stream from processor 29 to the data bus 36. The mode control level V at register 37 prevents decoder 38 and counters 39 from responding to the position bits which were loaded into the position register 37 during time slots T2 through T4. Thus, in the illustrated embodiment the mode flip-flop 32 is assumed to control all of the illustrated functional blocks. However, this need not be the case. For example, if the register 37, unblank control 44 and other display circuits are located some distance away from the processor 29, it might be necessary to detect the mode of change not only at the output of the buffer register 30 but also at the display circuits themselves. One way of doing this is for the mode decoder 31 to provide a decoded mode signal to the processor 29. The processor 29 would respond to such a mode signal to insert a 1 bit in time slot 5 of the data stream. The data stream would then, as in the normal alphanumeric mode, be gated on to the data bus 36. Another mode decoder would then be located with the display circuits and arranged to detect the presence of a 1 bit in bit position 5 of the position register 37. A detected 1 bit in time slot 5 would be responded to so as to inhibit the operation of all the functional block in the display circuits for the remainder of the current timing cycle. For this type of arrangement, the mode flip-flop 32 at the location of processor 29 and decoder 31 would not be clocked until a later time in the 21 microsecond cycle.

Turning now to the vector mode, the vector code is gated onto the data bus 36 during time slot T1 - T8 as discussed previously. During time slots T2 through T8 the vector code is gated into the position and vector register 37. The vector slope bits are decoded by decoder 38 and applied over eight control leads to the X and Y ramp generators 43.

In the vector mode, the ramp generators 43 are normally held in a discharged condition and are enabled to respond to the vector slope information only during a vector trace interval. In FIG. 4 the vector tracing interval is shown to occur during time slots T11 and T12, for a vector of one unit length, and also during time slots T17 and T18 for a vector of two units length. In any event, a Vector Draw signal is shown to be applied to ramp generator 43 so as to enable it to respond to the vector slope information and provide at its output X and Y vector slope deflection signals. This Vector Draw signal is produced by the unblank control 44 during the time slots T11 and T12 and time slots T17 and T18 under the control of the vector length bit as will be discussed later.

When a unit vector has been traced at the end of time slot T12 and/or T18, the counters 39 are enabled to respond to the vector slope information and the X and Y ramp generators 43 are reset. Thus, as the ramp generator 43 traces each unit vector, it is reset and the counters 39 are changed in count value to hold the beam at the new CRT screen location (the end point of the just traced unit vector). To effect the foregoing operation, the slope information from decoder 38 is shown in FIG. 5 to be further applied to the gross positioning counter 39 which also receives the Vector Draw signal.

Referring to FIG. 6, the unblank control 44 will be described. A video circuit 45 processes the unblank signals received from an OR network 46 to provide an intensity control signal to the CRT. The OR network 46 serves to combine the unblank signals from the various operating modes to produce an unblank signal over a single lead to the video circuit 45. Thus, in the alphanumeric mode the unblank data stream from data bus 36 (FIG. 5) is gated via AND gate 47 as one input to the OR gate network during time slots T6 through T21. In the vector mode the AND gate 47 is disabled and the unblank signal is received from the output of AND gate 48.

Before describing the vector unblank circuit in detail, it is well to note the function of the cursor. The cursor is a marker which indicates the location in a stored code sequence where the next code to be entered will be placed. In the illustrated embodiment, the cursor is identified by the three higher order bits 5, 6 and 7 being 1's. A decoder 49, which receives these three bits from the position and vector register 37 (FIG. 5) provides a cursor signal level C for the duration of the current code interval. This C signal is employed to set a cursor present flip-flop FF61. The Q output of FF61 is employed to inhibit a vector trace for this code interval and the Q output sets a "save the cursor" flip-flop FF54. FF61 is then reset during time slot 21. However, FF54 saves the cursor for the next ensuing code interval when it will be employed to enable a trace of a visible cursor marker. The decoder 49 also provides at its output the signal levels 5, 5, and 6 for the duration of a current code interval. As pointed out previously, bit 5 is the unblank bit. When it has a 1 value, the current vector code will be unblanked or made visible. Bit six is the length bit and its values of 0 and 1 correspond to short and long vector lengths, respectively.

During each code interval, a Vector Draw signal is provided at least once, during time slots T11 and T12, by means of OR gates 50 and 70. When the length bit 6 is a 1 an AND gate 51 is enabled to further couple the timing signals T17 and T18 to the OR gate 50 so as to provide a second Vector Draw signal, the signals T17 and T18 being combined in an OR gate 71. Thus, Vector Draw is always a 1 during time slot T11 and T12 and is also a 1 during time slot T17 and T18 when the length bit 6 is a 1.

The Vector Draw signal is coupled as one input to an AND gate 52 the output of which is coupled to the Vector mode AND gate 48. Whenever AND gate 52 is enabled by its other inputs, the Vector Draw signal will be passed to the Vector mode AND gate 48. It is convenient to first describe the operation of the FIG. 6 unblank control in terms of its response to a visible vector code sequence only and then to consider the cursor and its relation to NO-OP codes, hidden lines and gross positioning operations. When the current code is a Vector code which is not preceded by a cursor and which is to be displayed or made visible (bit five equals 1), both the AND gates 48 and 52 will be enabled to pass the Vector Draw signal via OR gate 46 to the video circuits 45. The enabling of AND gate 48 will be discussed first. The enabling of AND gate 48 is controlled by the output of another AND gate 53. The AND gate 53 is controlled to a large extent by the Q output of save the cursor FF54 (flip-flop 54). For the vector code only assumption, the Q output of FF54 will be a 1 which partially enables AND gate 53 via OR gate 55. The Q output of FF54 is also applied via an OR gate 56 to partially enable an AND gate 57. The AND gate 57 is fully enabled by the unblank bit 5 which it receives via an OR gate 59. The output of AND gate 57 is then passed via an OR gate 58 to wholly enable AND gate 53. This, in turn, enables the vector mode AND gate 48.

Turning now to the four enabling inputs for AND gate 52, one of these inputs is the Vector mode signal level which is always a 1 for the Vector mode. The unblank bit 5 is also an enabling signal which is coupled to AND gate 52 by means of an OR gate 60. Another enabling input to AND gate 52 is the output Q of the cursor present FF61. Since by assumption the current code is a Vector code the Q output of FF61 is a 1 and partially enables the AND gate 52. The other enabling input to AND gate 52 is provided by an OR gate 63 which senses a 1 at the Q output of a NO-OP flip-flop FF62. The NO-OP FF62 is set by a NO-OP signal only when the current code is a carriage return, vertical tab, horizontal tab, home or null character and is reset at all other times. The NO-OP signal is provided by decoder 49 when it detects these NO-OP codes. Thus, the AND gate 52 is fully enabled by all of its inputs when the current code is a Vector code which is to be displayed as a visible vector. Thus, the Vector Draw signal will be passed by both of the AND gates 52 and 48 to the video circuit 45 via OR gate 46.

As pointed out previously, a cursor code sets FF61 which in turn inhibits the passage of the Vector Draw signal by means of its Q output being coupled to AND gate 52. The FF61 is reset on time slot T21 such that its Q output will partially enable AND gate 52 during the next code interval. Also during the next code interval, save the cursor FF54 has its Q output coupled via OR gates 60 and 63 to wholly enable AND gate 52 to pass the Vector Draw signal to AND gate 48. The AND gate 48, thus enabled by the Vector Draw signal, will respond according to what kind of code and/or operating mode prevails for the code interval following the cursor code, e.g., null or space, visible vector, invisible vector codes, or hidden lines. These operating modes will now be described.

Null After Cursor Code

A null (all 0's) may occur, for example, at the end of the entire vector code sequence or of a portion thereof. In such case the cursor will occur during this code interval as a blinking and chopped vector on the CRT screen. When a null code is encountered, the NO-OP FF62 is set by means of a NO-OP control signal from decoder 49. The Q output of FF62 is then applied via an OR gate 67 to enable an AND gate 66.

The AND gate 66 is arranged to pass a chopped version of the Vector Draw signal. To this end, the Vector Draw signal is shaped by a shaper 65 so as to compress its pulse width to about two-thirds the width of two consecutive time slots. For instance, shaper 65 delays the leading edge of the Vector Draw signal for one third of the two time slot duration but does not delay the trailing edge. The output of shaper 65 is, then, a chopped Vector Draw signal and will be so referred to hereinafter. The chopped Vector Draw signal is passed by the enabled AND gate 66 via OR gate 58 to AND gate 53. The other input to AND gate 53 is gated on or enabled for three frames and then gated off for three frames of the refresh period by means of a blink counter 68 which is synchronized to the refresh memory control by means not shown. This blinking rate of one sixth the refresh rate is slow enough so that the chopped vector appears as a blinking vector on the CRT screen. The AND gate 53 then passes the chopped Vector Draw signal to the AND gate 48 when it is blinked by blink counter 68. The blinked and chopped unblank signal is, in turn, applied to the video circuit 45 via OR gate 46. The cursor is then displayed as a blinking and chopped vector when a null code succeeds a cursor code. The displayed cursor vector has a slope determined by its four least significant bits (all 0's for a null code) which for one system design is a vertical vector.

Visible Vector Code After Cursor Code

For this case, bit five = 1 and the visible vector will be caused to blink as a full length vector. To this end, AND gate 57 will be enabled via OR gate 59 and the Q output of the NO-OP FF62 via OR gate 56. The output of AND gate 57 is then applied via OR gate 58 to enable the blinking AND gate 53 to thus cause the visible vector which succeeds the cursor code to blink.

Invisible Vector Code After Cursor Code

As explained previously, the hidden lines key may be employed for three dimensional graphics to display the hidden lines of an object as dashed lines, as for example, the dashed lines of the cube in FIG. 1. For such case, the operator would depress the hidden lines key and then insert the desired codes for the dashed lines effect. A subsequent depression of the hidden lines key would then remove the visible display of these lines.

Assume that the operator has depressed the hidden lines key 16 so that HL = 0. Considering first the case of invisible vector codes in memory, bit five=0 An AND gate 64 senses these conditions to enable AND gate 52 to pass the Vector Draw signal to AND gate 48. The output of AND gate 64 also is passed by OR gate 67 to enable AND gate 66 to pass the chopped Vector Draw signal via OR gate 58 to AND gate 53. For the case where the cursor does not precede the invisible vector code, the Q output of save the cursor FF54 will enable AND gate 53 on a nonblinking basis so that the invisible vector will be displayed as a chopped vector. If the cursor did precede an invisible vector code, the vector defined by the invisible vector code will be blinked. So long as the hidden lines and vector invisible keys remain in this condition, the vector codes inserted will be displayed as dashed lines.

When the hidden lines key is subsequently depressed (HL = 0), the hidden lines will not be displayed since AND gate 64 will not be enabled to enable AND gate 52. However, it is to be noted that if the cursor code were stepped through the hidden line code sequence, the vector preceded by the cursor would be displayed since FF54 would enable AND gate 52. Also for this case, HL and 5 will enable an AND gate 69 which will condition AND gate 53 to be gated on and off by the blink counter. Hence, where the cursor precedes a hidden vector with HL = 0 or off, the hidden vector appears as a full length blinking vector.

NO-OP Codes-Editing

The NO-OP codes are useful for the purpose of formating an equivalent alphanumeric hard copy of the vector image. That is, the vector image can be converted to an alphanumeric equivalent by appropriately removing the Vector mode codes from the sequence. For the case where the number of codes in the sequence is less than the number of codes in an alphanumeric line, the NO-OP codes are not needed. However, if the number of codes in the sequence is greater, the tab and carriage return characters are useful to assure that the alphanumeric print out does not get hung up at the end of a character line, as in teletype print-out, but rather appears as a group of character lines. This group of character lines can then be saved for display at a future time as by teletype print-out or by a photograph of the CRT screen. In addition, by allowing the NO-OP codes to be a part of the vector code sequence, advantage can be taken of the alphanumeric editing features to delete or move portions of the vector code sequence (i.e., a portion of the graphical picture). Moreover, the CRT beam can be gross positioned by switching from the vector mode to the alphanumeric mode to use the tab and/or carriage return characters. This type of gross-positioning avoids the display of hidden lines for such moves.

When a NO-OP code appears in the code sequence, FF62 becomes set such that its Q output no longer enables AND gates 52 and 57. If the previous code was not a cursor code, AND gate 52 will not be enabled and the Vector Draw signal will therefore not be passed. The beam then would remain blanked and at its present position. On the other hand, if the previous code had been a cursor code, AND gate 52 will be enabled by the Q output of the save the cursor FF54 by way of OR gate 60 and 63. The chopped Vector Draw signal would then be coupled via AND gate 66 and OR gate 58 to AND gate 53. As previously mentioned, the blink counter will then enable AND gate 53 (and hence AND gate 48) every other three frames so as to blink the cursor. This feature then gives a visual indication to the graphical display operator that a NO-OP code is in the stored code sequence. To distinguish between NO-OP codes, each is traced as different ones of the vector slopes by interpreting the least four significant bits of the NO-OP code as a vector code as previously pointed out for the null code.

There has thus been described graphical display apparatus in which an operator can generate graphical images on a CRT screen in real time. It is apparent that the logic diagram schemes shown throughout the drawings are illustrative of one embodiment and that other designs and schemes may be employed. In addition, the logic schemes may also be implemented by means of a sequence of instructions in a stored program computer apparatus. That is, the display circuits may be implemented in stored program computer apparatus, as well as, in hard wired logic.