Stoddard, Robert D. (Reeds Ferry, NH)
Schumacher, Arnold (Cricket Hill, NH)
Conley, Grant W. (Milford, NH)
Williams Jr., Roy M. (Nashua, NH)

04/818015

05/23/1972

04/21/1969

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Sanders Associates, Inc. (Nashua, NH)

345/472

345/1.100

G09G1/08; G09G1/10; G09G1/06; G06F3/14

340/324A 315/18

2875951	Synchronization of display means to specific microsecond interval	March 1959	Schreiner
3311908	Cathode ray tube display device employing constant velocity beam deflection	March 1967	Halsted et al.
3315120	Differential delay-line amplifier	April 1967	Yanishevsky
3329948	Symbol generating apparatus	July 1967	Halsted
3364479	Line drawing system	January 1968	Henderson et al.
3510865	DIGITAL VECTOR GENERATOR	May 1970	Callahan et al.
3540032	DISPLAY SYSTEM USING CATHODE RAY TUBE DEFLECTION YOKE NON-LINEARITY TO OBTAIN CURVED STROKES	November 1970	Criscimagna et al.

Habecker, Thomas B.

Curtis, Marshall M.

What is claimed is

1. The combination comprising:

2. The invention according to claim 1

3. The invention according to claim 2 wherein the register further includes a control register portion coupled to said data source for receiving said instructions; and

4. The invention according to claim 3

5. The invention according to claim 7

6. The combination comprising

7. The invention according to claim 6

8. The invention according to claim 7

9. The invention according to claim 8

10. Display apparatus comprising

11. The invention according to claim 10

12. The invention according to claim 11

13. The invention according to claim 12

14. The invention according to claim 13

15. The invention according to claim 14

16. The invention as set forth in claim 11

BACKGROUND OF THE INVENTION

This invention relates to information systems and in particular to techniques and apparatus for providing display of information.

One type of present day information system employs a cathode ray tube (CRT) type indicator which is driven by a suitable signal source of X, Y and Z modulation. The signal source in some applications takes the form of a simple video source including sweep controls, such as radar or television. In other applications, the signal source takes the form of a digital computer which controls the visual presentation of symbolic data (alphanumeric, lines, conics and the like) on the CRT screen. In some applications the digitally generated symbolic data can be mixed with video under the control of the computer.

In many computer controlled display systems, the computer has stored in its memory an instruction set indicative of a symbolic set to be displayed. The instruction set is applied at a suitable refresh rate to a display generator which responds to the instructions to generate the X, Y and Z modulation indicative of the set of symbols. The X, Y and Z modulation is then applied to the CRT indicator to present a visual display of the symbol set. The computer generally responds to various input devices, such as keyboards, light guns, sensing devices, and others so as to update the instruction set in real time (i.e., a relatively short response time).

Computer controlled display systems have generally employed various types of CRT indicators. Where large amounts of data are to be presented at one time, high speed indicators (on the order of 500,000 inches per second writing rate) have been employed. In other cases, CRT projection type indicators (on the order of 250,000 inches per second) have been employed. In still other cases, CRT hard copy indicators (on the order of 5,000 to 10,000 inches per second) have been employed. In general, each such display has required a separate display generator and a separate refresh channel to the computer memory. Because of this, multi-station display environments have not been able to efficiently monitor data on a real time basis.

Multi-station real time display system environments, such as automatic checkout systems, human factor study systems, simulation systems, educational training systems, avionic systems and others, generally require different visual presentations of the data content for different purposes. For instance, an automatic checkout system for an aircraft may require that a large amount of dynamically changing data be displayed on a single indicator at one station. For this purpose, a high speed indicator may be employed. At another station, only a portion of the data may be required to be displayed on a CRT projection type indicator. At still other stations, a portion of the data may be required to be displayed on a CRT hard copy unit.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide novel and improved techniques and apparatus for generating information at variable rates.

Another object is to provide display apparatus capable of operating plural display indicators which have different writing rate capabilities.

Yet another object is to provide display apparatus in which plural display indicators having different writing rates share a single display generator.

Still another object is to provide a character generator capable of dynamically shifting over a wide range of generating rates.

Briefly the display apparatus of the invention is embodied in a computer controlled display generator which responds to an instruction set provided by a computer to generate driving energy at different rates for one or more display indicators. The display generator includes function generator means responsive to the instruction set to generate the driving energy at selected generating rates. A display selector means also responsive to the instruction set couples the generated driving energy to a selected one or ones of the display indicators.

The function generator is embodied in apparatus having means for producing X and Y axis modulation signals. Rate varying means is coupled to the X and Y signal producing means to vary the rate at which the X and Y signals are produced. In one embodiment, the rate varying means produces timing signals at a selected one of plural frequencies. The producing means receives these timing signals and operates at the selected frequency to generate constant currents of different values each having a time duration which is a function of the selected frequency. In this embodiment, the producing means further includes a ramp generator having a plurality of capacitors and switching means responsive to the timing means to selectively couple said capacitors across one another in combination. Each of the combinations corresponds to a different timing signal frequency such that the same change in voltage is produce for any one of the constant currents at all operating frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings like reference characters denote like structural elements, and

FIG. 1 is a block diagram of a computer controlled display apparatus embodying the present invention;

FIGS. 2A and 2B are block diagrams in part and circuit schematic diagrams in part of a variable rate character generator further embodying the invention;

FIG. 3 is a waveform diagram of various ones of the timing signals produced and employed in the FIGS. 2A and 2B character generator embodiment.

DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIG. 1 an information display system embodying the invention is illustrated as including a digital computer 10 associated with an interface unit 11 by way of which computer 10 communicates with various input - output (I/O) devices 12 and display generation apparatus 13 (shown below the dashed line). In FIG. 1, communication buses or data flow paths are illustrated as single lines. However, it is to be understood that each such bus or path may consist of a large number of conductors. For example, the DATA BUS consists of a number of conductors equal to the number of bits in a word. In addition where such a bus or path is applied as an input to a gate, it is assumed that the gate actually consists of a number of gates equal to the number of bits carried by the bus or path, such that each bit is applied to a different gate.

The computer 10 has a memory in which is stored in digital form instructions for producing various patterns of X, Y and Z modulation for application to plural display indicator channels 20. Although only two such channels designated D1 and D2 are illustrated, it is to be understood that many more channels may be employed. The illustrated display indicators are, for the purpose of example, considered to be CRT type indicators having different beam deflection speed ranges. Thus, indicator D1 has a deflection (writing) speed of W1 and D2 has a writing speed of W2.

The display generation apparatus 13 fetches the instructions from the memory of computer 10, processes the instructions, generates X, Y and Z modulation, and selects which one of the display indicators D1 or D2 is to be connected to receive the X, Y and Z modulation.

Each set of instructions in the memory of computer 10 is updatable by means of a stored program contained therein and by means of various peripheral devices 12, for example, light guns, tape or card reader devices, keyboard devices and the like. The updating or current sensor data is coupled via an interface unit 11 to computer 10 where it is processed according to the stored program to update the instruction set.

The display generator 13 includes a register section 14, a timing and logic control section 15, a function generator 16 and a display selector 17. The instructions are fetched from the memory of computer 10 under the control of the timing and control section 15. To this end, the register section 14 includes a control register means 14-3 for receiving the instructions from computer 10 via a DATA BUS and interface unit 11. The timing and control section 15 then processes or interprets the received instructions. The instructions may require data contained therein to be loaded into various ones of the registers in section 14 and/or may require various beam deflection patterns to be generated. The timing and logic section 15 responds to the instructions to cause the data to be loaded into the specified registers as well as to cause the function generator 16 to generate the specified beam deflection patterns and the display selector 17 to select one of the indicators D1 or D2 to receive the generated beam deflection pattern. For this purpose a CONTROL BUS is shown in FIG. 1 to receive control information from control section 15 and to translate such information to various ones of the registers in section 14, or to the function generator 16 or to the display selector 17, as required. In addition, the CONTROL BUS is adapted to receive other control signals from the various parts of the display generator 13 and to translate such other control signals to the timing and logic section 13. These other control signals may represent response status information, such as end of character and end of line generation by the function generator.

Although the control register 14-3 is illustrated as a single block, it is to be understood that the control register may include a number of registers. For example, the control register may include a memory data register for receiving incoming instructions from the computer 10, an instruction register for holding a current instruction while it is being processed and a memory address register for holding the address of the next instruction to be fetched. In addition, the control register may include other registers associated with the modification of the memory address register and still other registers associated with the timing, frame synchronization, and the operation mode of the display generator 13.

Each beam deflection pattern to be applied to either of the CRT indicators D1 and D2 must be repetitively generated (refreshed) in order to present a continuous (non-flickering) visual display. By way of example for a 60 hertz refresh rate, display generator 13 must fetch the set of instructions from computer 10 and process them to generate X, Y and Z modulation 60 times every second or once every 16.6 milliseconds. To this end, the display generator 13 includes a frame sync or refresh generator (not shown) which provides a refresh clock or sync signal to operate the control section 15 and hence, the display generator at a 60 hertz rate or other suitable rate.

A feature of the present invention is that the display generator 13 can be time shared by the different writing rate indicators D1 and D2 in contrast to prior art systems where separate display generators are required for each such indicator. To this end, the register section 14 includes a display select register 14-4, a speed register 14-2 as well as an X, Y and Z register means 14-1. The register means 14-1 is employed in the conventional manner as a buffer and holding register means for the X, Y and Z data indicative of a particular symbol (either alphanumeric, line, or conic) or of a simple beam deflection positioning move in which the beam is ordinarily blanked. The display select register 14-4 is employed to hold a digital number or bit field indicative of the display indicator D1 or D2 to be selected. The speed register 14-2 is employed to hold a bit field indicative of the writing rate for the selected indicator and as such controls the rate at which the X and Y deflection signals and the Z unblanking signal are generated. That is, the slopes of the X and Y beam deflection voltages are determined, in part, by the bit field of the speed register 14-2.

A typical operational sequence would be to first load the display select and speed registers 14-4 and 14-2, respectively. When the loading operation has been completed, the timing section 15 transmits a data transfer signal DTS by way of the CONTROL BUS to AND gates 18-4. The DTS signal enables AND gates 18-4 to pass the display select bit field to the display selector 17. The display selector 17 is, for example, a crossbar type switch which responds to the display select bits to connect one of the indicators D1 or D2, say D1, to the output of the function generator 16.

The DTS signal also enables AND gates 18-2 to pass the writing rate bit field to the function generator 16. The writing rate bit field conditions the function generator to generate X, Y and Z signals corresponding to the X, Y and Z digital data at a specific generating rate corresponding to the value W1 of the field. The X, Y and Z data for a desired symbol are then loaded into the X, Y and Z register means 14-1. After this loading operation is staticized, the timing and control section 15 transmits a symbol start signal SSS to enable AND gates 18-1 to pass the X, Y and Z data to the function generator 16. The function generator 16 then responds to the X, Y and Z digital data to produce X, Y and Z modulation at a rate determined by the numeric value W1 of the writing rate bit field as pointed out above.

When the symbol has been generated, the function generator 16 transmits an end of symbol signal EOS to control section 15 via the CONTROL BUS to signify that X, Y and Z data for the next symbol may now be received. The control section 15 responds thereto to load the X, Y and Z register 14-1 and to issue another symbol start signal SSS. This operation continues until X, Y and Z modulation has been generated for all the symbols contained in a current instruction set. This symbol generation then continues repetitively at the refresh rate.

As pointed out previously, while a particular instruction is being processed, other instructions in the set may be updated or made current. For example, suppose indicator D1 is displaying a symbol set and an operator at indicator D2 requests via I/O devices 12 (for example a keyboard) that the information be presented to D2. The computer 10 responds to this request to format a new display select instruction and a new writing rate instruction for loading register 14-4 and 14-2. These new instructions are then inserted into the instruction set to replace the former D1 and W1 values. When these instruction locations are again addressed, the display generator 13 responds to the new values D2 and W2 to select display D2 and conditions function generator 16 to operate at the W2 rate.

It is to be understood that the foregoing operational sequence is exemplary and that many other modes are possible. For instance, a current instruction set could be updated so as to cause the display generator to access an entirely different instruction set in another segment of the computer memory. A significant advantage of the FIG. 1 embodiment is that the display indicators D1 and D2 can time share the display generator 13 so as to present common or unique sets of symbols and/or video images on both indicators for simultaneous visual observation. This, of course, involves appropriate formatting and interleaving of the instruction set so as to provide display select instructions at appropriate points in the refresh cycle so as to couple the proper indicator channel to the function generator 16 and/or to a video (either radar or television) source (not shown) at the proper times. Graphic or video data can be mixed with graphic or symbolic data for display on a common CRT screen by producing the symbol set during the normal end of sweep dead time interval for the case of radar or during the vertical retrace interval for the case of television. In addition, the symbol set can also be produced on an asynchronous basis by sweep stealing (radar) or line stealing (television) in order to present large amounts of symbolic data. These video mixed mode options are unnecessary to an understanding of the present invention, and are therefore not specifically illustrated.

Although the function generator 16 may include any type of symbol generator, such as a line (or vector), conic, character and other types of symbol generators, the invention is herein illustrated in FIGS. 2A and 2B in a character generator embodiment. For an example of a line generator embodiment reference is made to a co-pending application entitled Variable Rate Line Generator, Ser. No. 817,786, filed Apr. 21, 1969, by Robert D. Stoddard, Arnold Schumacher and John R. Longland and assigned to the assignee of the present application.

Referring next to FIGS. 2A and 2B, the variable rate character generator embodiment of the invention is shown to include in FIG. 2B a character stroke gate array 50, X and Y ramp generators 52X and 52Y, respectively, and in FIG. 2A a clock or timing signal producing means 60 (below the dashed line). In FIG. 2A the clock signal producing means responds to a symbol start signal, designated as character start (CS), from the CONTROL BUS, to produce a master stroke timing signal T _s , the frequency of which is a function of the speed or writing rate bit field provided by a portion 14-2a of register means 14-2 of FIG. 1. The frequency of timing signal T _s is also a function of a size bit field which is provided by another portion 14-2b of register 14-2 of FIG. 1. The timing signal producing means also produces a number of stroke timing pulses and a character draw (CD) timing signal. As shown in the common time base waveform diagram of FIG. 3, the CS, T _s and CD signals serve to apportion the operation of the character generator into a set up time t ₀ to t ₃ followed by a character trace time t ₃ to t ₆ . Although only three stroke timing pulses are shown in FIG. 3 the clock signal producing means provides one such stroke pulse during each period of the timing signal T _s .

In FIG. 2B the character gate stroke array 50 receives X, Y and Z coded character data from register means 14-1, diciphers the coded data and, in combination with X and Y ramp generators 52X and 52Y, provides X and Y axis stroke deflection signals V _x and V _y and a Z axis unblanking signal V _z . At each character location on the display indicator screen, the CRT beam is deflected in a pattern determined by the V _x and V _y deflection signals and unblanked in accordance with the V _z unblank signal. Thus, the stroke gate array 50 generates or writes a character on the face of the CRT according to the cursive writing technique by generating a unique set or pattern of strokes (vectors or lines) which together make up the character.

The array 50 includes a decoder (not shown) for decoding the character data and a buffered stroke gate array (not shown) of which different stroke gates receive different ones of the stroke pulses. The decoded character data enables a unique set of the stoke gates such that a particular sequence of the stoke pulses are selected. The occurrence of each of the selected stroke pulses signifies a change in stroke or vector direction such that the time difference between successive selected strokes constitutes the tracing time of a stroke. The outputs of the stroke gates are buffered under the control of the stroke timing signal T _s and applied to a current generator (not shown). The current generator responds to the T _s clocked buffering of each selected stroke pulse to produce constant currents Ix and Iy, the values of which correspond to the X and Y components of the stroke. Thus, the currents Ix and Iy for each character are essentially a sequence of constant currents, the values of which, though independent of the frequency of timing signal T _s , are changeable upon the occurrence of the selected stroke pulses. That is, the values of Ix and Iy are the same for a given stroke for any of the writing rates. The stroke gate array also contains means (not shown) for producing the Vz unblank signal in synchronism with the stroke currents Ix and Iy and for producing an end of character (EOC) signal upon the generation of the last stroke of a selected character. For a more specific description of a stroke gate array which could be employed, reference is made to a co-pending application Ser. No. 665,116, filed Sept. 1, 1967, for Richard Bouchard, entitled CHARACTER DISPLAY SYSTEM U.S. Pat. No. 3,533,096 issued Oct. 6, 1970 and assigned to the present assignee.

The Z axis unblank circuitry is not shown in FIG. 2B since it is unnecessary to an understanding of the present invention. Suffice it to say here, that the array 50 includes Z axis circuitry which responds to the start and end of the various strokes to selectively unblank the CRT beam so as to trace the character.

The stroke currents Ix and Iy are applied to X and Y ramp generator sections 52X and 52Y respectively. The ramp generator sections 52X and 52Y are substantially identical and like components are designated by like reference numerals followed by alphabetic characters X and Y to indicate corresponding locations in the X and Y sections, respectively. Consequently, only the X ramp generator section 52X will be described in detail.

The X ramp generator 52X includes a bank of capacitors comprised of capacitor 53X and plural capacitors 54X. The capacitor 54X is connected between the Ix stroke current lead and circuit ground. The capacitors 54X have separate serially connected switches, designated collectively as 55X, which are selectively operable to connect capacitors 54X in various combinations in circuit between the Ix current lead and circuit ground. The switches 55X, for example, may be transistor type switches. The X ramp generator 52X further includes a discharge switch 56X which is open during character trace time intervals and closed during set-up intervals. It is to be noted that discharge switch 56X is shown as ganged with discharge switch 56Y to illustrate that both the X and Y capacitor banks are discharged at the same time. Like the switches 55X, the switch 56X may be of a transistor type, but is shown as a simple switch for ease of description.

The discharge switches 56X and 56Y are driven by discharge switch driver gates 51. The discharge gates 51 respond to the trailing edge of the CD signal (end of character trace period) at time t ₆ to close switches 56X and 56Y and to the leading edge thereof (start of character trace) at time t ₃ to open switches 56X and 56Y. The capacitor switches 55X and 55Y are driven by switch driver gates 57.

The switches 55X and 55Y are driven by switch driver gates 57 which are selectively enabled by the decoded rate or speed bit field. The switch driver gates 57 also respond to a driver enabling signal DES on lead 58. The DES signal conditions driver gates 57 to close all of the switches 55X and 55Y at the end of a character trace to assure that all of the capacitors 54X and 54Y are discharged. The DES signal enables the gates 57 during the set-up time t ₀ to t ₃ (FIG. 3) to open selected ones of the switches 55X and 55Y in response to the decoded rate field.

To summarize the foregoing discussion, the charging interval Δ t for a particular stroke is selected according to the writing rate or speed bit field. In addition, the capacitance value is also selected as a function of the writing rate such that the same amount of beam deflection energy is produced for any particular stroke for all writing rates. That is, the values of both C and Δ t in the charging relation (equation 1) of C Δ V = I Δ t are each varied in accordance with the writing rate so as to insure a constant value of Δ V (voltage change) at all writing rates for any one particular value of current I. The effect of this is that the slope s of the beam deflection increments Δ Vx and Δ Vy change from one writing rate to another for a particular stroke. Thus, for a selected writing rate or charging interval Δ t, the stroke gate array 50 and the ramp generators 52X and 52Y produce beam deflection signals Vx and Vy consisting of a succession of analog voltage ramps, each of which corresponds to a particular stroke and all of which form the character called for by the character code. When the writing rate (Δ t) is changed for this particular character, the slopes of the analog ramps also change, but the voltage changes Δ V do not change.

For one example of the character generator embodiment employing a two bit character size code, a three bit speed code six capacitors each for 54X and 54Y, and a maximum 22 stroke per character capability, Table I shows the maximum writing time in microseconds (Usec) for selected sizes and speeds. It is noted that one dit equals the amount of displacement caused on the display surface area by changing either the X OR Y coordinate data one least significant bit. ------------------------------------------------------------ --------------- TABLE I

CHARACTER WRITING RATES

(Maximum Tracing Time for a 22 Stroke Character)

Character Size 1 2 3 4 Size Code 00 01 10 11 Nominal Character Height 16 Dits 32 Dits 48 Dits 64 Dits ____________________________________________________________ ______________ Speed Speed Range Code μsec μsec μsec μsec ____________________________________________________________ ______________ 1 000 3.3 6.6 9.9 13.2 2 001 6.6 13.2 19.8 26.4 4 010 13.2 26.4 39.6 52.8 8 011 26.4 52.8 79.2 105.6 16 100 52.8 105.6 158.4 211.2 32 101 105.6 211.2 316.8 422.4 64 110 211.2 422.4 633.6 844.8 ____________________________________________________________ ______________

The timing signal producing means 60 (FIG. 2A) will now be described in detail. In the description, which follows, a number of J-K flip-flops are employed. Briefly, a J-K flip-flop is one which yields a predictable output for every possible combination of input signal levels. The J-K flip-flop exhibits the properties reflected in the following Truth Table wherein t _n represents the bit time before a clock pulse, t _n + 1 represents the bit time after a clock pulse and Q _n represents the state of the flip-flop during the t _n bit time. ------------------------------------------------------------ --------------- TRUTH TABLE

t _n t _n + 1 J K Q _{n +} 1 ____________________________________________________________ ______________ 0 0 Qn 0 1 0 1 0 1 1 1 Qn ____________________________________________________________ ______________

For the purpose of the following description, the convention of positive logic is arbitrarily adopted wherein the binary "1" and "0" signal levels correspond to the most positive (HI) and most negative (LO) signal levels, respectively. With reference to the above TRUTH TABLE, if "0" signal levels are applied to both J and K input terminals, the flip-flop remains in its pre-existing state Qn, i.e., there is no change in the state of the flip-flop. If "1" signal levels are applied to both the J and K input terminals, the state of the flip-flop is reversed from the pre-existing state, i.e., the flip-flop acts as a triggerable flip-flop. If "0" and "1" signal levels are applied to the J and K terminals, respectively, the Q output assumes a "0" level. Finally, if "1" and "0" levels are applied to the J and K terminals, respectively, the Q output assumes a "1" level. In addition, each of the illustrated J-K flip-flops includes a preset (R) input terminal which when driven LO ("0" level), sets the flip-flop in a DC manner (independently of the clock rate) to the Q = "1" state.

When it is desired to trace a character, the timing and logic control 15 (FIG. 1) transmits a negative going character start CS pulse to the CONTROL BUS. In the FIG. 3 waveform diagram, the leading edge of the CS pulse occurs at time t ₀ . Referring now to FIG. 2A, the CS pulse is received by the character generator at the R input of a character busy flip-flop FF1. The character busy flip-flop FF1 is operable to provide a "1" level character busy CB signal at its Q output for the duration of the set-up and character trace times and a "0" level signal at all other times. To effect this operation, the flip-flop FF1 has its J terminal grounded ("0" level) and its K terminal connected to receive the end of character EOC signal at the termination of the character trace. The clock terminal C of FF 1 receives a synchronizing clock signal C _s from the timing and logic control section 15 (FIG. 1) via the CONTROL BUS. Prior to receipt of the CS pulse and specifically at the end of the previous character trace, the EOC "1" signal pulse places FF1 in a condition where its outputs Q and Q (CB and CB, respectively) are "0" and "1" levels, respectively. That is, after the EOC signal returns to the "0" level, succeeding C _s clock pulses effect no switching of the flip-flop (both J and K are "0"). When the character start CS signal drives the R input to the "0" level, the FF 1 Q and Q outputs become "1" and "0" levels, respectively. The duration of the CS pulse is sufficient to permit FF 1 to switch. When the C _s pulse terminates, succeeding C _s clock signals do not switch FF 1 since both the J and K inputs are receiving "0" levels. The Q or CB signal is coupled to a Preset Line which is coupled to various parts of the timing signal section 60 as illustrated by the dashed lines, the dashed lines being broken to simplify the drawing. The waveform of the CB signal is illustrated in FIG. 3.

The "1" level Q output or CB signal initiates an oscillator 61 to produce clock signal CPO. The oscillator 61, for example, may be a blocking type oscillator. The CPO clock signal is divided by a speed frequency divider 62 which is programmable in accordance with the decoded bit field of the speed or writing rate register 14-2a. For this purpose a decoder 63, which may be of a conventional type, is provided. The output of the speed frequency divider 62 is a clock signal CPA, the waveform of which is shown in FIG. 3. The CPO clock signal waveform is not shown in FIG. 3 in order to simplify the drawings. The speed frequency divider 62, for example, may include a binary counter and an output gate array which is programmable in accordance with the decoded speed bit field so as to divide the CPO clock signal by various powers of two. For the previously mentioned three bit speed field example, the speed frequency divisers would be 1, 2, 4, 8, 16, 32, and 64.

The CPA clock signal is utilized to drive a size frequency divider 75 as well as a number of flip-flops and gates. The size frequency divider 75 is programmable in accordance with the size bit field provided by register portion 14-2b. This size bit field is decoded (by means not shown). The output of divider 75 is delayed before application to a clock control unit 66. To this end the output of divider 75 is applied as one input to NAND gate 65. Another input of the NAND gate 65 receives the CPA clock signal. A third input of NAND gate 65 is coupled to the Q output of flip flop FF 3. By definition, a NAND gate is one in which its output is a "0" level only when all of its inputs are "1" levels. When any one or more of a NAND gates inputs is a "0" level, the output is "1" level.

The NAND gate 65, then, is operable to pass the output of divider 63 only when both the CPA signal and the Q output of FF 3 are both "1" levels. The CPA clock signal, of course, is periodically a "1" level signal in coincidence with the slower frequency output of divider 75. For example, a size division by a factor of 2 produces a "1" level of the size divided signal in coincidence with every other "1" level of the CPA signal. The NAND gate 65 is inhibited by the Q output of FF 3 in order to institute a delay into the timing signal apparatus 60 to thereby provide the set-up time (FIG. 3).

To effect the set-up delay, the CPA signals are further applied to a programmable delay 64 which is operable to produce a "1" signal pulse at its output after a delay which is triggered by the receipt of the clock signal CPA. The delay 64, for example may include a ring counter which is clocked at the CPA rate and gating arrangement which is programmed by the decoded speed bits to respond to an output of one of the counter stages to produce the one signal pulse output of the delay section 64. It is noted that the programmable delay section 64 is preset by the CB signal to assure that the ring counter is clear before a new character is generated. The output waveform of delay 64 is designated in FIG. 3 as FF 2 J. The waveform diagram in FIG. 3 is broken between times t ₀ and t ₁ to illustrate that the set-up time is variable in accordance with the writing rate or speed bit field.

The "1" signal level of the delay section 64 is applied directly to the J input of a flip-flop FF 2 and by way of an inverter 67 to the K input of FF 2. Both FF 2 and FF 3 are clocked by the CPA signal and both are preset by the CB signal so as to drive their respective Q outputs to "0" levels at time t ₀ when the character start CS signal is received by FF 1. The waveforms of the CPA clock signal and of the J input of the FF 2 flip flop are shown in the waveform diagram of FIG. 3. Thus, so long as the output of delay 64 (FF 2 J waveform in FIG. 3) is a "0" level, the J inputs to both flip-flops FF 2 and FF 3 are "0" levels and their corresponding outputs are also "0" levels as illustrated prior to t ₁ in FIG. 3. During the next bit time (negative going edge of CPA) after the output of delay 64 becomes a "1" level, flip flop FF 2 switches and its output Q assumes a "1" level as shown at time t ₂ in FIG. 3.

The next trailing edge of the CPA clock occurs at time t ₄ and switches FF 3 to provide a "1" level signal at its Q output. This "1" level signal enables NAND gate 65 to produce the clock signal T _s , the complement T _s of which is illustrated in the waveform diagram of FIG. 3. The clock signals T _s are illustrated, by way of example, for a size division of 2. The T _s clock signal are applied to the clock control unit 66 which responds thereto to provide the stroke timing pulses and the stroke timing signal T _s as positive going waveforms. That is, unit 66 inverts the T _s signal to provide the complement T _s . The signal T _s has the same period as the T _s clock signal and (though not so illustrated) may be shaped as by narrowing.

Referring again to the time t ₂ (FIG. 3), the FF 1 Q output "1" signal level is shown in FIG. 2B to be further applied as an input to a NAND gate 68. Another input of the NAND gate 68 receives the Q output of FF 3. The FF 3 Q output is also a "1" level the time t ₂ and remains so until time t ₄ . The NAND gate 68 has another input which is clocked by the CPA signal such that it produces a negative going pulse interval from time t ₃ to t ₄ , designated as a character write CW signal in FIGS. 2B and 3. The CW pulse signal is applied to the R input of another flip-flop FF 4. The FF 4 flip flop responds to the character write CW signal to drive its Q output to a "0" level. The Q output is inverted by an inverter 69 to provide the character draw CD signal as shown in FIGS. 2B and 3. The FF 4 flip-flop has its K terminal grounded ("0" level) and its J input connected to receive the EOC signal. Since EOC is also a "0" level for the duration of the character set-up and trace times, the clock signal T _s does not cause FF 4 to change states while the character is being traced. Thus the character draw CD signal remains a "1" level for the duration of the character trace interval. Since the EOC signal assumes a "1" level in response to the end of character EOC signal, the FF 4 flip-flop will then switch on the next T _s trailing edge to thereby drive its Q output to the "1" level and terminate the character draw signal. The T _s timing signal can be utilized to terminate the character draw signal in so far as there is a switching delay associated with flip flops FF 1 and FF 2 before the timing signal T _s terminates.

Referring again to time t ₁ (FIG. 3) , the output of delay unit 64 is further employed to enable the switch driver gates 57 which drive switches 55X and 55Y. To this end, the output of delay 64 is coupled to the S input of a two NAND gate 70a. The output of NAND gate 70a and the output of another two input NAND gate 70b are cross coupled to one input of the other. The remaining input of gate 70b receives an input R. The R input is coupled by way of a differentiator 71 to receive the CD signal from the output of inverter 69. The output of gate 70a (also designated as driver enabling signal DES) is further coupled via lead 58 to condition the switch driver gates 57.

The NAND gates 70a and 70b operate as follows. Assume that prior to time t ₁ (FIG. 5) the outputs of NAND gates 70a and 70b are "0" and "1" respectively. Also prior to time t ₁ the S input is a "1" (the inverted "0" output of delay 64). Finally, the differentiator 71 provides a "0" at the R input of gate 70b. At time t ₁ the inverted output of delay 64 becomes a "0" and NAND gate 70a switches to provide a "1" signal value of DES to the switch driver gates 57. The switch driver gates 57 responds to the "1" signal level to open selective ones of the switches 55X and 55Y. At time t ₃ , the differentiator 71 responds to the rising edge to provide a below ground signal to the R input. However, NAND gate 70b does not respond thereto since both of its inputs must go positive in order for it to switch. Thus, the outputs of both NAND gates 70a and 70b are "1"'s at time t ₁ and remain so until time t ₆ . At time t ₆ , the differentiator 71 responds to the falling edge of the CD signal to provide a positive going "1" pulse signal to the R input of NAND gate 70b. The NAND gate 70b then switches at this time to provide a "0" at its output. The duration of the differentiated pulse at the R input is sufficient to span the negative going transistion which occurs at the S input due to the resetting of the delay 64 by the CB signal. Thus, just after time t ₆ the S input becomes a "1" and the R input becomes a "0" when the differentiated positive going pulse terminates. The NAND gate 70a switches at this time to provide a "0" at its output. The "0" level value of DES causes the switch driver gates 57 to close all of the switches 55X and 55Y to assure complete discharging of the capacitors 54X and 54Y.

To summarize the character generator operation, the timing signal producing means 60 produces timing signals CD, T _s and the stroke timing pulses at a rate or frequency which is a function of the numeric value of the speed or writing rate number (set of digital data). The character generating array 50 and ramp generators 52X and 52Y respond to these timing signals to produce the X, Y and Z modulating signals at a rate corresponding to the speed bit rate.

There has been described a computer-controlled display generator capable of producing X, Y and Z modulating signals at variable rates. In the illustrated embodiment the generating rate has been shown as dependent on symbol size and display indicator writing rate. However, it is to be understood that the variable generating rate techniques can be employed in various other manners. For example, the code contained in register 14-2a could represent parameters other than indicator writing rates. Thus, if both the 14-2a and 14-2b register code represented variable sizes, one could be employed to vary the capacitor banks 52X and 52Y and the other one to vary the frequency of the timing signals. Such a scheme could then present characters in different size ranges with the character size in each range being further variable within its range.

The display generator is capable of being time-shared by plural display indicators having different writing rates as in a multistation display environment. Though illustrated with a cursive writing techniques, the variable rate character generator technique is equally applicable to raster scan, dot generating and other writing techniques. Although the illustrated embodiments have been described as driving CRT type indicators, the invention is also applicable to any type indicator which responds to modulating drive energy in three directions. Thus, display generator apparatus embodying the present invention can be employed to drive X-Y plotter mechanisms having a marking (or imaging) instrument, such as pin, knife, photohead and the like. In such mechanisms, the X and Y signals move the imaging instrument in a plane parallel to the imaging medium (paper, photographic film, and others), while the Z axis signal provides the pin up and down (light beam on and off) information to trace patterns on the medium. The immediately above comments are also applicable to milling machine mechanisms, where the marking instrument is a tool which is urged against and away from a work piece by the Z axis modulation. Of course, the instruction set need not be repeated or refreshed for either of the plotter or milling mechanism applications. In addition, where it is desired not to operate in real time, the X, Y and Z axis signals for the plotter or milling maching applications can be formatted in an appropriate numerical control code for storage on a paper or magnetic tape which is later read by the plotter or milling mechanism.