Title:
ENTRY MARK SYSTEM FOR ENTRY AND DISPLAY OF NUMBERS
United States Patent 3657529
Abstract:
A calculator having an input register for receiving an input number, an auxiliary register and a decimal point position memory for storing numerical data and showing the number of digits below the decimal point position. Entry mark setting means are provided to set all 1's signals into the "one's" digit position of the auxiliary register corresponding to the contents of the decimal point position memory. Additional means are provided to set code bits specified by a keyboard into the same digit position of the input register as that of the entry mark consisting of all 1's signals in the auxiliary register by using the entry mark as a time slot signal for number entry.
US Patent References:
Calculator decimal point alignment apparatus
Scuitto et al. - February 1968 - 3375356
Circuit for displaying the decimal location in electronic type arithmetical computing devices, particularly in connection with digital data readout devices on decimal indicators
Rinaldi - December 1967 - 3358125
NUMBER DISPLAY SYSTEM ELIMINATING FUTILE ZEROS
Sakoda et al. - October 1970 - 3537073
Computation with variable fractional point readout
Simpson - July 1968 - 3391391
CALCULATORS
Chow et al. - February 1969 - 3430226
Calculator decimal point alignment apparatus
Scuitto et al. - February 1968 - 3375356
Circuit for displaying the decimal location in electronic type arithmetical computing devices, particularly in connection with digital data readout devices on decimal indicators
Rinaldi - December 1967 - 3358125
NUMBER DISPLAY SYSTEM ELIMINATING FUTILE ZEROS
Sakoda et al. - October 1970 - 3537073
Computation with variable fractional point readout
Simpson - July 1968 - 3391391
CALCULATORS
Chow et al. - February 1969 - 3430226
Application Number:
05/005494
Publication Date:
04/18/1972
Filing Date:
01/26/1970
View Patent Images:
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd. (Kadoma, Osaka, JA)
Primary Class:
Other Classes:
345/168
International Classes:
G06F3/027; G06F3/14; G06F15/02; G09G3/00; H03K21/08; H03K21/00; G06F3/00; G06F7/38
Field of Search:
235/159,160,156,61DP,92EA,92SH,92PL 340/337,324
US Patent References:
Primary Examiner:
Botz, Eugene G.
Assistant Examiner:
Gottman, James F.
Claims:
What is claimed is
1. In a calculator having a multi-register dynamic loop having an input register for receiving input numbers except for the least significant digit position and an auxiliary register having digit positions corresponding to those of said input register, the least significant digit position of said auxiliary register being used as means for memorizing a decimal point position which stores numerical data in binary forms showing the number of digits below the decimal point position, the improvement comprising:
2. The improvement defined in claim 1 and further comprising right-shifting means operatively coupled to said auxiliary register for successively setting other binary data into the digit positions of said auxiliary register except for the least significant digit position so that said entry mark in said auxiliary register is shifted right by one digit position, said other binary data being obtained by subtraction of binary one from the previous data in each digit position of said auxiliary register except for the least significant digit position.
3. In a calculator having an input register for receiving input numbers, an auxiliary register having digit positions corresponding to those of said input register and means for memorizing a decimal point position which stores numerical data in binary forms showing the number of digits below the decimal point position, the improvement comprising:
4. The improvement defined in claim 3 and further comprising right-shifting means operatively coupled to said auxiliary register for successively setting other binary data into the digit positions of said auxiliary register so that said entry mark in said auxiliary register is shifted right by one digit position, said other binary data being obtained by subtraction of binary one from the previous data in each digit position of said auxiliary register.
5. In a calculator having an input register for receiving input members, an auxiliary register having digit positions corresponding to those of said input register, means for memorizing a decimal point position which stores numerical data in binary form showing the number of digits below the decimal point position, a plurality of multi-cathode numerical indicator tubes corresponding to the number of digit positions of said input register to be displayed, each of said plurality of numerical indicator tubes having the cathodes thereof for connection to the output terminals of a decoder-driver, a buffer register for storing the information to be displayed temporarily and coupled to said input register, the output terminals of said decoder-driver being adapted to be selected by output signals of said buffer register, a plurality of selection switches for being coupled to an anode selection counter and having their one ends connected to a plurality of anodes of said numerical tubes, respectively, each of said anodes of said numerical tubes being driven in scanning by the anode selection counter through said plurality of anode selection switches in the direction of most to least significant digit positions and at the same time the contents of the digit position of said input register corresponding to the selected anode selection switch being transferred to said buffer register and a zero suppress control switch having one end connected to the other ends of said plurality of anode selection switches and the other end thereof being for connection to an anode power supply, the improvement comprising:
6. The improvement defined in claim 5 wherein said zero suppress signal detecting means detects a signal indicating that a digit position of said auxiliary register is full of zeroes.
7. The improvement defined in claim 5 and further comprising right-shifting means operatively coupled to said auxiliary register for successively setting other binary data into the digit positions of said auxiliary register so that said entry mark in said auxiliary register is shifted right by one digit position, said other binary data being obtained by subtraction of binary one from the previous data in each digit position of said auxiliary register.
1. In a calculator having a multi-register dynamic loop having an input register for receiving input numbers except for the least significant digit position and an auxiliary register having digit positions corresponding to those of said input register, the least significant digit position of said auxiliary register being used as means for memorizing a decimal point position which stores numerical data in binary forms showing the number of digits below the decimal point position, the improvement comprising:
2. The improvement defined in claim 1 and further comprising right-shifting means operatively coupled to said auxiliary register for successively setting other binary data into the digit positions of said auxiliary register except for the least significant digit position so that said entry mark in said auxiliary register is shifted right by one digit position, said other binary data being obtained by subtraction of binary one from the previous data in each digit position of said auxiliary register except for the least significant digit position.
3. In a calculator having an input register for receiving input numbers, an auxiliary register having digit positions corresponding to those of said input register and means for memorizing a decimal point position which stores numerical data in binary forms showing the number of digits below the decimal point position, the improvement comprising:
4. The improvement defined in claim 3 and further comprising right-shifting means operatively coupled to said auxiliary register for successively setting other binary data into the digit positions of said auxiliary register so that said entry mark in said auxiliary register is shifted right by one digit position, said other binary data being obtained by subtraction of binary one from the previous data in each digit position of said auxiliary register.
5. In a calculator having an input register for receiving input members, an auxiliary register having digit positions corresponding to those of said input register, means for memorizing a decimal point position which stores numerical data in binary form showing the number of digits below the decimal point position, a plurality of multi-cathode numerical indicator tubes corresponding to the number of digit positions of said input register to be displayed, each of said plurality of numerical indicator tubes having the cathodes thereof for connection to the output terminals of a decoder-driver, a buffer register for storing the information to be displayed temporarily and coupled to said input register, the output terminals of said decoder-driver being adapted to be selected by output signals of said buffer register, a plurality of selection switches for being coupled to an anode selection counter and having their one ends connected to a plurality of anodes of said numerical tubes, respectively, each of said anodes of said numerical tubes being driven in scanning by the anode selection counter through said plurality of anode selection switches in the direction of most to least significant digit positions and at the same time the contents of the digit position of said input register corresponding to the selected anode selection switch being transferred to said buffer register and a zero suppress control switch having one end connected to the other ends of said plurality of anode selection switches and the other end thereof being for connection to an anode power supply, the improvement comprising:
6. The improvement defined in claim 5 wherein said zero suppress signal detecting means detects a signal indicating that a digit position of said auxiliary register is full of zeroes.
7. The improvement defined in claim 5 and further comprising right-shifting means operatively coupled to said auxiliary register for successively setting other binary data into the digit positions of said auxiliary register so that said entry mark in said auxiliary register is shifted right by one digit position, said other binary data being obtained by subtraction of binary one from the previous data in each digit position of said auxiliary register.
Description:
This invention relates to a digital data processor into which numbers are entered from an input system, and more particularly, to the improvement of a system for carrying out number entry into a digital data processor, for example, a system for entering numbers into an electronic desk calculator by the use of a 10-key figure keyboard while a decimal point is being fixed at the position specified by pre-set decimal point setting means, such as a decimal point selection switch.
A conventional electronic desk calculator into which numbers are set by the use of a 10-key figure keyboard does not fix the decimal point in the position specified by means of decimal point setting means such as a decimal point selection switch when it has numbers set thereinto. When numbers are set into such an electronic desk calculator, numbers are set into the input register in the position of the least significant digit after the contents of the input register has been left-shifted in accordance with the keyboard handling.
The position of the decimal point is tracked by a decimal point counter which is cleared to zero prior to the number entry and which counts whenever a digit is sent from the keyboard after the decimal point key is depressed. In such a manner, the decimal point counter indicates the position of the decimal point and does not necessarily agree with the decimal point position specified by means of a decimal point setting means such as a decimal point selection switch. In advance of the start of arithmetic operations, such as addition, subtraction, multiplication, or division initiated by the corresponding instructions from the function keys, the numbers in the input register have to be normalized to make the decimal point position in the input register consistent with the decimal point position specified by the decimal point setting means by shifting the contents of the input register and tracking the decimal point on the input register by the decimal point counter. Only then can the arithmetic operation be executed. During the normalization of the contents of the input register, overflow of the contents of the input register might occur by left-shifting the contents of the input register. On the other hand, when the numbers are set into the input register, overflow of the contents of the input register does not occur. Therefore, when numbers are set into such an electronic desk calculator, it is inconvenient to handle the electronic desk calculator. Besides, such a calculator has to have both a decimal point counter and a controlling circuit and therefore becomes complicated and expensive.
Another conventional electronic desk calculator into which numbers are set by the use of a 10-key figure keyboard suppresses the display of the leading nonsignificant zeroes of the contents of the display register which holds the input number or the result of the arithmetic operation. On the other hand, such an electronic desk calculator does not suppress the display of the trailing nonsignificant zeroes below the decimal point position. Therefore, it is inconvenient to handle the electronic desk calculator during a number entry operation. Take an example of a case of the number entry operation of the number 12.001 into the input register having a ten digit capacity with the decimal point position specified as being at digit 5. In other words, when there are 5 digits capacity below the decimal point position, the contents of the input register are 00012.00100. The indicator displays 12.00100 suppressing the leading nonsignificant zeroes. However, it is difficult for such an electronic desk calculator to distinguish between 12.0010 and 12.001 which initially enters the calculator.
It is an object of this invention to provide a digital data processor such as an electronic desk calculator into which numbers are set by the use of a 10-key figure keyboard, while a decimal point is fixed at the position specified by means of decimal point setting for easy handling and avoidance of misoperation.
It is another object of this invention to provide a digital data processor into which numbers are set while a decimal point is being fixed at a specific position.
It is a further object of this invention to provide a digital data processor having a simple construction into which numbers are set while a decimal point is being fixed at a specific position.
It is a further object of this invention to provide a digital data processor using a register as the means for specifying the figure entry position into the input register, said register being not commonly used for the number entry operation.
It is a further object of this invention to provide a digital data processor using a novel entry mark setting system and/or a novel entry mark shifting system.
These objects are achieved by digital data processor according to the invention which comprises:(1) a circulating register which has an input register for receiving input data and an auxiliary register; (2) decimal point position memory means which stores numerical data corresponding to the specific decimal point position and which storage is carried out by the sign part of the auxiliary register; (3) left-shifting means for shifting the contents of the input register left by one digit position; (4) entry mark setting means which is coupled to the auxiliary register and which successively sets binary data into every digit position of the auxiliary register in a direction from the lowest digit to the highest digit so that an entry mark consisting entirely of 1's signals is set into the "one's" digit position of the auxiliary register, said binary data being obtained by successive subtraction of one from the contents of the decimal point position memory means at every digit; (5) right shifting means which is coupled to the auxiliary register and successively sets other binary data into the every digit position of the auxiliary register so that the entry mark in the auxiliary register is shifted right by one digit, the said other binary data being obtained by subtraction of one from the previous data of each digit position of the auxiliary register; and (6) input circuit means which is coupled to the input register and which puts the input figure into a digit position the same as that of the entry mark.
The auxiliary register is mainly used as a multiplier-quotient register in multiplication or division operations and contains no data to be processed during a number entry operation.
When the first figure of an input number is detected during number entry, the entry mark setting means sets an entry mark into the one's position of the auxiliary register. The input circuit means puts the input figure into the same digit position of the input register as that of the entry mark whenever a new figure of the input number is detected.
Before the decimal point of the input number is set in, the left-shifting means shifts the contents of the input register left by one digit position and after the decimal point of input number is set in, the right shifting means shifts the entry mark in the auxiliary register right by one digit position in advance of the entry of the input figure into the input register. Thus, the input number is put into the input register and the decimal point position is fixed.
These and other features will be readily apparent to those skilled in the art from an examination of the following specification and accompanying drawings, wherein:
FIG. 1 is a block diagram of an electronic desk calculator having three registers which are serially arranged by a time division method, each of said three registers being of 16 digit capacity in accordance with the invention;
FIG. 2 is a diagram showing the clock pulses in the electronic desk calculator shown in FIG. 1;
FIGS. 3a -3c are diagrams showing the sequence of the output pulses from the control circuit in the electronic desk calculator shown in FIG. 1;
FIG. 4 is a flow chart for explaining the operations of the electronic desk calculator shown in FIG. 1 in accordance with the invention;
FIGS. 5a-5e are diagrams showing the numbers in the input register for explanation of the operations of the electronic desk calculator shown in FIG. 1 in accordance with the invention;
FIG. 6 is a block diagram of a display system of the electronic desk calculator shown in FIG. 1 in accordance with the invention; and
FIGS. 7a-7e are diagrams showing the figures in the display tubes for explanation of the operations of the display system shown in FIG. 6 in accordance with the invention.
The following description will, for convenience, be of an electronic calculator having three registers, each of which is of 16 digit capacity and holds numbers in BCD code.
Referring to FIG. 1, which shows a specific embodiment of the invention, a circulating register consists essentially of shift registers 1 and 4, INHIBIT gates 2 and 5 and OR gates 3 and 6. A left-shifting means consists essentially of a shift register 31, AND gates 29, 39 and 40, the INHIBIT gate 2 and OR gates 17, 28 and 30. An entry mark setting means consists essentially of the shift register 31, a full adder 33, a 1-bit delay circuit 36, AND gates 27, 29, 34 and 38, INHIBIT gates 5, 32 and 37 and OR gates 6, 28, 30 and 35. A right-shifting means consists essentially of the shift register 31, the full adder 33, the 1-bit delay circuit 36, AND gates 29, 34, 38 and 44, INHIBIT gates 5, 32 and 37 and OR gates 6, 28, 30 and 35. An input circuit means consists essentially of a key board 8, a code-converter 18, AND gates 23, 24, 25, 26 and 41, the INHIBIT gate 2 and OR gates 3, 16 and 17.
The output signal of a 188-bit serial shift register 1 is fed to a 4-bit serial shift register 4 through an INHIBIT gate 2 and an OR gate 3. The output signal of the 4-bit shift register 4 is fed to the input terminal of the 188-bit shift register 1 through an INHIBIT gate 5 and an OR gate 6 so that the two shift register constitute a 192-bit circulating register. In FIG. 1, the means to clear the circulating register are not shown.
Referring to FIG. 2, CL is the master clock pulse which is supplied to the 188-bit shift register 1, the 4-bit shift register 4, and other circuits.
T 1 , T 2 , T 4 and T 8 represent the clock pulses specifying the timing of the output signals from the 188-bit shift register 1 corresponding in accordance with the code "1," the code "2," the code "4" and the code "8," respectively.
T A , T B and T C are the clock pulses specifying the timing of the output signals of the 188-bit shift register 1 corresponding in accordance with the contents of the first register, the second register and the third register, respectively. T-0, T-1, T-2. . . T-15 are the clock pulses specifying the timing of the output signals of the 188-bit shift register 1 correspondingly in accordance with the first digit, the second digit, the third digit and so on up to the 16th digit from the least significant digit. A reference character T-0 shows the time from T-1 to T-15. These clock pulses are supplied from a clock pulse generator 7 in FIG. 1.
As indicated in the above description, the 192-bit circulating register has three registers arranged in series of bits, in time division series of register and in series of digits.
The first register is an auxiliary register which is mainly used as a multiplier-quotient register in multiplication or division operations and contains no data to be processed during a number entry operation. The second register mainly holds an addend, a subtrahend, a multiplicand or a divisor during arithmetic operation and is used as an input register during number entry. The third register usually operates as an accumulator. The least significant digit of each register except the auxiliary register holds the sign of each register.
The least significant digit of the auxiliary register is used as means for memorizing a decimal point position. The decimal point position is defined by depression of a key for the entry of figures when the calculator is in "decimal point position setting mode." The "decimal point position setting mode" is set by selective depression of a mode switch.
When a key of the key-board 8 for the entry of figures is depressed, an instruction pulse whose pulse width is equal to the time necessary for the circulating register to cycle one round appears at the output terminal 10 of the control circuit 9 connected to the key-board 8 for the entry of figures. And the output signal of an AND gate 15 becomes logically "1" at the time of T-0 and TA. Only when the output signal of the AND gate 15 is logically "1" is any output signal from the output circuits 19, 20, 21 and 22 of the code-converter 18 set into the least significant digit of the first register in the circulating register through any of the AND gates 23, 24, 25 and 26, and through the OR gate 3, gates 23-26 being controlled by the output signal of the OR gate 16. At the same time, the INHIBIT gate 2 is closed by the control of the output signal of the AND gate 15 through the OR gates 16 and 17 and the signal recirculation in the circulating register is stopped.
Information from the key-board 8 for the entry of figures is converted into a binary coded decimal (BCD) signal by the code-converter 18. The output circuits 19, 20, 21 and 22 are provided with the output signal from the code-converter 18 corresponding to the code "1," the code "2," the code "4" and the code "8," respectively. Each output signal from the code-converter 18 enters the specified bit position of the least significant digit of the first register through any of the AND gates 23, 24, 25 and 26 and through the OR gate 3 when the output signals from the output circuits 19, 20, 21 and 22 of the code-converter 18 are coincident with clock pulses T 1 , T 2 , T 4 and T 8 , respectively, at the time specified by the output signal of the OR gate 16.
The following example shows the operation of decimal point position setting of "3" which means three digits capacity to the right of the decimal point. By depression of the key specifying "3" on the key-board 8 for the entry of figures, the output signals of the output circuits 19 and 20 of the code-converter 18 are set into the least significant digit of the first register through the AND gates 23 and 24 at the time of T-0 and TA. Thus, the least significant digit of the first register holds "3" in BCD form. For number entry operation, the mode of the calculator is switched to "normal" from "decimal point position setting."
When a key on the key-board 8 for the entry of figures is depressed, instruction pulses are generated at each of output terminals 11, 12, 13 and 14 of the control circuit 9 connected to the key-board 8.
Referring to FIG. 4, in the action step (a), a test is made to determine whether this depression of the key of the key-board 8 is just after the arithmetic operation. In the action step (b), the entry mark is set into the first register. The entry mark is a marker signal and is used to specify the digit position of the second register into which the number is to be entered. The new figure is set into a digit position of the second register corresponding to the entry mark position of the first register.
The operation of the action step (b) is carried out by the instruction pulse from the output terminal 11 of the control circuit 9 shown in FIG. 1. In the action step (c), a test is made to determine whether the decimal point key of the key-board 8 for the entry of figures has been depressed previously. In the action step (d), the entry mark in the first register is right-shifted by one digit position. The operation of the action step (d) is carried out by the instruction pulse from the output terminal 12 of the control circuit 9. In the action step (e), the new data corresponding to the specified key of the key-board 8 for the entry of figures is set into a digit position of the second register at a position corresponding to the entry mark digit position of the first register. The operation of the action step (e) is carried out by the instruction pulse from the output terminal 13 of the control circuit 9. In the action step (f), the contents of the second register are left-shifted by one digit position. The operation of the action step (f) is carried out by the instruction pulse from the output terminal 14 of the control circuit 9. The test operations in the action step (a) and (c) are carried out with other operations at the same time. In FIG. 1, the test circuits for the above are not shown.
FIGS. 3(A), (B) and (C) show the time relations among the instruction pulse sequences depending upon the combination of the action steps of the flow chart shown in FIG. 4. The length of the instruction pulse is equal to the time necessary for the circulating register to cycle one round. Each instruction pulse starts at T-0 and terminates at T-15.
FIG. 3(A) shows the case when the key of the key-board 8 for the entry of figures is depressed just after the arithmetic operations. FIG. 3(B) shows the case of depression of two figure entry keys in succession. FIG. 3(C) shows the case of depression of the figure entry key after depression of the decimal point key.
The following description explains the operation of the circuits for each action step in FIG. 4.
When the instruction pulse is generated at the output terminal 11 of the control circuit 9, the output signal of the 188-bit shift register 1 is put into the 4-bit shift register 31 through the AND gate 29 and the OR GATE 30 at the time of T-0 and T A as the AND gate 27 becomes logically "1" at the time of T-0 and T A and the output signal of the AND gate 27 closes the INHIBIT gate 32 and opens the AND gate 29 through the OR gate 28. That is, the contents of the least significant digit of the first register are put into the 4-bit shift register 31, but the least significant digit of the first register does not lose the data.
The output signal of the 4-bit shift register 31 is fed to the input terminal Y of the full adder 33. As there is no input signal at the input terminals X and Z of the full adder 33, the output signal from the output terminal S of the full adder 33 is therefore the same signal as the input signal to the input terminal Y of the full adder 33 and is fed to the input terminal of the 4-bit shift register 31 through the INHIBIT gate 32 and the OR gate 30. Thus, a circulating register including the 4-bit shift register 31 and the full adder 33 is formed. Then, the circulating register holds the same signal as that of the least significant digit of the first register in the main circulating register. Next, at the time of T-1 and T B , a "1111" signal is added to the contents of the circulating register including the 4-bit shift register 31 and the full adder 33 as the AND gate 34 having one input signal feed from the OR gate 35 connected with the output terminal 11 of the control circuit 9, becomes logically "1" at the time of T-0 and T B and the output signal of the AND gate 34, which is equal to "1111" at each time T B of T-0 is fed to the input terminal X of the full adder 33. But, the addition of "1111" to the contents of the circulating register is equivalent to the subtraction of "0001" from the contents of the circulating register because the carry output terminal C of the full adder 33 is connected to the input terminal Z of the full adder 33 through the 1-bit delay circuit 36 and the INHIBIT gate 37 and the input signal to the input terminal Z of the full adder 33 from carry output terminal C is inhibited at the time of T 1 by means of the INHIBIT gate 37. And the output signal from the output terminal S of the full adder 33 enters the 192-bit circulating register through the AND gate 38 and the OR gate 6 at the time of T-1 and T B while the INHIBIT gate 5 is closed. The output signal from the output terminal S of the full adder 33 is set into the first register in the 192-bit circulating register. After the above operation at the time of T-1 and T B , the circulating register including the 4-bit shift register 31 and the full adder 33 holds the result of the previous subtraction till the next subtraction operation at the time of T-2 and T B . At the time of T-2 and T B , T-3 and T B , . . . T-15 and T B , the same operations explained above are repeated.
The following example shows the case when the least significant digit of the first register holds "3," that is, "0011." After the above operations, the first digit of the first register holds "0011;" the second digit, "0010;" the third digit "0001;" the fourth digit, "0000;" the fifth digit, "1111; " the sixth digit, "1110" and so on.
The "1111" is used as the entry mark for the entry of a figure and the fifth digit holds the entry mark. The foregoing is the explanation of the entry mark setting operation into the first register. The following description is of the conventional left-shifting operation of the contents of the second register.
When the instruction pulse is generated at the output terminal 14 of the control circuit 9, the signal of each digit of the second register is fed into the 4-bit shift register 31 from the 188-bit shift register 1 through the AND gate 29 and the OR gate 30 as the AND gate 39 becomes logically "138 at the time of T-0 and T B and the INHIBIT gates 2 and 32 are closed by the output signal of the AND gate 39 through the OR gates 17 and 28, respectively. At the same time the previous contents of the circulating register including the 4-bit shift register 31 and the full adder 33 are transferred to the 192-bit circulating register at the one digit higher position in the second register than before through the AND gate 40 and the OR gate 3. The signal of each digit of the second register is held in the circulating register including the 4-bit shift register 31 and the full adder 33 till the next "store and transfer" operation. The following description is of the number entry operation into the second register that is the input register of the calculator. time,
The flip-flop circuit 42 is a JK flip-flop circuit controlled by clock pulse CL (cf. FIG. 2) and is set to "1" at the time of T C . The flip-flop 42 is reset to "0" at the time of T A by the control of the INHIBIT gate 43 whenever the output signal of the 188-bit shift register 1 corresponding to each digit position of the first register is not "1111." That is, when the first register holds the entry mark in any digit position, the output signal of the flip-flop 42 remains "1" at the succeeding time corresponding to the second register. When the instruction pulse is generated at the output terminal 13 of the control circuit 9, the information specified by the depression of the key of the key-board 8 for the entry of figures is converted into the BCD code signal by the code-converter 18 and is set into the 192-bit circulating register at the position of the specified digit position of the second register through any of the AND gates 23, 24, 25 and 26 by the control of the output signal of the OR gate 16. At the same time, the INHIBIT gate 2 is closed as the output signal of the AND gate 41 connected the output terminal 13 of the control circuit 9 becomes logically "1" at the time of T B when the output signal of the flip-flop 42 is "1."
Thus, the new figure is set into a digit position of the second register the same as the entry mark in the first register.
The right shifting operation of the entry mark is described below.
When the instruction pulse is generated at the output terminal 12 of the control circuit 9, the contents of the second digit position of the first register is fed into the 4-bit shift register 31 through the AND gate 29 and the OR gate 30 as the AND gate 44 connected to the output terminal 12 of the control circuit 9 becomes logically "1" at the time of T-1 and T A and the output signal of the AND gate 44 closes the INHIBIT gate 32 through the OR gate 28. The contents of the circulating register including the 4-shift register 31 and the full adder 33 is transferred to the 192-bit circulating register through the AND gate 38 and the OR gate 6 at the next "store and transfer" operation same as the entry mark setting operation. Thus, the entry mark is right shifted by one digit position.
After right-shifting of the entry mark by the entry mark setting operation exactly similar to that of the previous example, the first digit holds "0011;" the second digit, "0001;" the third digit "0000;" the fourth digit, "1111;" the fifth digit, "1110;" the sixth digit, "1101" and so on.
The following description explains by way of example the operation of entering the number 12.345.
When the key corresponding to the figure "1" is depressed, the actions shown in FIG. 4 are successively executed in the order (a), (b), (c), (f), and (e). In the action step (b), the instruction pulse generated at the output terminal 11 of the control circuit 9 sets the entry mark into the fifth digit position of the first register.
In step (f), the contents of the second register are shifted to the left by one digit position; that is, to the position of next higher significance, but nothing significant occurs because the second register has previously been cleared.
In step (e), the digit "1" is set into the fifth digit position of the second register by control of the AND gate 41. This condition of the second register, that is, the input register, is represented in FIG. 5(A).
When the key corresponding to the figure "2" is depressed, actions shown in FIG. 4 are successively executed in the order (a), (c), (f) and (e).
In step (f), the number in the second register is shifted to the left by one digit position, and in step (e) the digit "2" is set into the fifth digit position; that is, the units digit position of the second register. The condition of the second register is now represented by FIG. 5(B).
When the key corresponding to the figure "3" is depressed after the depression of the decimal point key, the actions shown in FIG. 4 are successively executed in the order (a), (c), (d) and (e).
In step (d), the entry mark in the first register is shifted to the right by one digit position; that is, to the position of next lower significance. Therefore, in step (e) the digit "3" is put into the fourth digit position; that is, the one-tenth digit position of the second register. The condition of the second register is now represented by FIG. 5(c).
Similarly, when the keys corresponding to the figures "4" and "5" are successively depressed, the digits "4" and "5" are put into the input register at the proper position. The consequent conditions of the second register are then represented, respectively, by FIGS. 5 (D) and (E).
FIG. 6 is a block diagram of a display system displaying the contents of the input register which is used as an output register of the electronic desk calculator shown in FIG. 1. For display of the contents of the input register, fourteen glow discharge type numerical indicator tubes such as NIXIE tubes are used since the contents of the least significant digit of the input register, that is, decimal point position, are displayed by the conventional method and the contents of the most significant digit of the input register are not displayed.
In FIG. 6, the numerical indicator tubes and the peripheral circuits corresponding to the digit position from the third digit to the 13th digit of the input register are not shown to simplify the explanation.
Referring to FIG. 6, the one end of the zero suppress switch 60 is connected to the anode power supply V A and the other end of the zero suppress switch 60 is connected to the one ends of all of the anode selection switches 54, 55 and 56.
The other end of the anode selection switches 54, 55 and 56 is connected to the anode of the indicator tubes 51, 52 and 53, respectively. The indicator tube 51 is used for display of the contents of the second digit of the input register. The indicator tubes 52 and 53 are for the 14th and the 15th digits of the input register. Therefore, by opening the zero suppress switch 60, the anode supply voltage is not supplied to any of the anodes of the indicator tubes 51, 52 and 53 and none of the indicator tubes are lighted.
The cathode terminal corresponding to the figures from "0" to "9" of each indicator tube 51, 52 and 53 is connected to the corresponding output terminal corresponding to the figures from "0" to "9" of the decoder-driver 61 which connects the respective output terminals corresponding to the figures from "0" to "9" to the ground depending upon the contents of the 4-bit shift register 62 which is used as buffer register means. The input signal to the 4-bit shift register 62 is fed from the output terminal of the 188-bit shift register 1 shown in FIG. 1.
The four JK flip-flops 68, 69, 70 and 71 constitute a 4 stage binary counter which counts up from "0000" to "1111" by the clock pulse T C and which is supplied from the clock pulse generator 7 shown in FIG. 1.
The counter consisting of the JK flip-flops 68, 69, 70 and 71 is called a "C" counter. The clock pulse T-0 specifies the time when the contents of the "C" counter is "0000," that is, 0. The clock pulse T-1 . . . T-15 specifies the time when the contents of "C" counter is "0001" . . . "1111," that is, 1 . . . 15.
Another four JK flip-flops 64, 65, 66 and 67 constitute a 4 stage binary reverse counter which counts down from "1111" to "0000" by the output signal of the AND gate 72 and which is called an "S" counter and is used as anode selection counter means. The "S" counter is used for selective switching of the anode selection switches 54, 55 and 56.
The output signal of the OR gate 73 becomes logically "1" when the output signal of the AND gate 77 or the AND gate 78 become "1;" that is, when the states of both JK flip-flops 64 and 68 are the same. The OR gate 74 is used to detect whether the states of both JK flip-flops 65 and 69 are the same by the output signal of the AND gate 79 or the AND gate 80. Each of the OR gates 75 and 76 is used to detect whether the states of the JK flip-flops 66 and 70 are the same by the output signal of the AND gate 81 or the AND GATE 82 and whether the states of the JK flip-flops 67 and 71 are the same by the output signal of the AND gate 83 or the AND gate 84. Therefore, the output signal of the AND gate 72 becomes "1" at the time of T B when the contents of both the "S" counter and the "C" counter become the same. When the output signal of the AND gate 72 changes state from "1" to "0," in detail, at the trailing edge of the clock pulse T B , the "S" counter is counted down by 1.
The following description is of the case when the switching circuit 60 is closed.
In the initial condition, the content of the "S" counter is assumed to be 14; that is, "1110." When the content of the "C" counter becomes "14," that is, at the time of T-14, the output signal of the AND gate 72 becomes "1" at the time of T B and the four clock pulse synchronized by CL appear at the output terminal of the AND gate 63.
The above four clock pulses shift the output signal from the 188-bit shift register 1 to the 4-bit shift register 62. That is, the contents of the 15th digit position of the second register are transferred to the 4-bit shift register 62. The 4-bit shift register holds the contents of the 15th digit position of the second register and cause the decoder-drive to drive selectively. At the same time, the "S" counter is counted down to "13" at the trailing edge of T B . Then, the AND gate 59 becomes "1" as the contents of "S" counter are "13" and the indicator tube 53 displays the contents of the 15th digit position of the second register as the anode selection switch 56 is closed as the decoder-driver 61 is controlled by the contents of the 4-bit shift register 62 to move to the position corresponding to the number in the shift register 62. At the next time T-13, the contents of the 14th digit position of the second register are transferred to the 4-bit shift register 62 and the "S" counter is counted down to "12." At the same time, the indicator tube 52 displays the contents of the 14th digit position of the second register as the anode selection switch 55 is closed by the output signal of the AND gate 58.
In this manner, the fourteen indicator tubes display the contents of the second register in the direction from the 15th digit position to the 2nd digit position.
The flip-flop circuit 89 is a clock pulse driven JK flip-flop by CL and controls the zero suppress switch 60. When the output signal of the flip-flop 89 is "1, " the zero suppress switch 60 is closed. When the output signal of the flip-flop 89 is "0," the zero suppress switch 60 is opened and the display on the indicator tubes is suppressed. The flip-flop 89 is reset by the output signal of the AND gate 86 through OR gate 87. The AND gate 86 becomes "1" when the content of the "S" counter becomes "14," that is, one step before the time of displaying the contents of the 15th digit position of the second register and the output signal of the AND gate 86 resets the flip-flop 86 through terminal K. Therefore, the zero suppress switch 60 is opened just before the display of the contents of the 15th digit position of the second register.
When both the "S" counter and "C" counter become "14," the information to be displayed enters the 4-bit shift register 62 and the "S" counter counts down to "13."
If any of the contents of N1, N2, N4 and N8, which constitute the 4-bit shift register 62, is not "0," the flip-flop 89 is set through the OR gate 88 and the indicator tube is lighted as the zero suppress switch 60 is closed.
If all of the contents of N1, N2, N4 and N8 are "0," the flip-flop remains in the reset state and the zero suppress switch 60 is opened.
As explained above, the display of the leading non-significant zeroes are suppressed until the appearance of a significant figure.
During a data entry operation, the first register which is the auxiliary register, holds the entry mark and other signals as explained before. To suppress the display of the trailing non-significant zeroes below the decimal point position, the display of the contents of all the digit positions below the digit position corresponding to one digit below the entry mark in the first register which is represented as "0000" in the first register must be suppressed.
When the output signal of the AND gate 72 becomes "1" and all the output signals of A1, A2, A4 and A8 which constitute the 4-bit shift register 4 shown in FIG. 1 are "0, " the flip-flop 89 is reset by the output signal of the AND gate 85 through the OR gate 87 and the zero suppress switch 60 is closed.
The clock pulse T 1 is added to the input terminal of the AND gate 85 to specify the time when the 4-bit shift register 4 holds the contents of the first register. Thus, the trailing non-significant zeroes are not displayed.
FIGS. 7 (A) - (E) show the display conditions corresponding to each step of the number entry operation of the number 12.345.
As mentioned above, a digital data processor having a simple construction in accordance with the invention facilities the number entry by using an entry mark setting and shifting operation while the decimal point is fixed. It is not necessary to shift the contents of the input register in advance of the elementary arithmetic operation. Therefore, overflow of the contents of the input register can be avoided.
The electronic desk calculator according to the invention can suppress easily the display of the non-significant zeroes below the decimal point position by use of the entry mark setting and shifting operation.
The electronic desk calculator according to the invention can be easily handled and is free from misoperation.
A conventional electronic desk calculator into which numbers are set by the use of a 10-key figure keyboard does not fix the decimal point in the position specified by means of decimal point setting means such as a decimal point selection switch when it has numbers set thereinto. When numbers are set into such an electronic desk calculator, numbers are set into the input register in the position of the least significant digit after the contents of the input register has been left-shifted in accordance with the keyboard handling.
The position of the decimal point is tracked by a decimal point counter which is cleared to zero prior to the number entry and which counts whenever a digit is sent from the keyboard after the decimal point key is depressed. In such a manner, the decimal point counter indicates the position of the decimal point and does not necessarily agree with the decimal point position specified by means of a decimal point setting means such as a decimal point selection switch. In advance of the start of arithmetic operations, such as addition, subtraction, multiplication, or division initiated by the corresponding instructions from the function keys, the numbers in the input register have to be normalized to make the decimal point position in the input register consistent with the decimal point position specified by the decimal point setting means by shifting the contents of the input register and tracking the decimal point on the input register by the decimal point counter. Only then can the arithmetic operation be executed. During the normalization of the contents of the input register, overflow of the contents of the input register might occur by left-shifting the contents of the input register. On the other hand, when the numbers are set into the input register, overflow of the contents of the input register does not occur. Therefore, when numbers are set into such an electronic desk calculator, it is inconvenient to handle the electronic desk calculator. Besides, such a calculator has to have both a decimal point counter and a controlling circuit and therefore becomes complicated and expensive.
Another conventional electronic desk calculator into which numbers are set by the use of a 10-key figure keyboard suppresses the display of the leading nonsignificant zeroes of the contents of the display register which holds the input number or the result of the arithmetic operation. On the other hand, such an electronic desk calculator does not suppress the display of the trailing nonsignificant zeroes below the decimal point position. Therefore, it is inconvenient to handle the electronic desk calculator during a number entry operation. Take an example of a case of the number entry operation of the number 12.001 into the input register having a ten digit capacity with the decimal point position specified as being at digit 5. In other words, when there are 5 digits capacity below the decimal point position, the contents of the input register are 00012.00100. The indicator displays 12.00100 suppressing the leading nonsignificant zeroes. However, it is difficult for such an electronic desk calculator to distinguish between 12.0010 and 12.001 which initially enters the calculator.
It is an object of this invention to provide a digital data processor such as an electronic desk calculator into which numbers are set by the use of a 10-key figure keyboard, while a decimal point is fixed at the position specified by means of decimal point setting for easy handling and avoidance of misoperation.
It is another object of this invention to provide a digital data processor into which numbers are set while a decimal point is being fixed at a specific position.
It is a further object of this invention to provide a digital data processor having a simple construction into which numbers are set while a decimal point is being fixed at a specific position.
It is a further object of this invention to provide a digital data processor using a register as the means for specifying the figure entry position into the input register, said register being not commonly used for the number entry operation.
It is a further object of this invention to provide a digital data processor using a novel entry mark setting system and/or a novel entry mark shifting system.
These objects are achieved by digital data processor according to the invention which comprises:(1) a circulating register which has an input register for receiving input data and an auxiliary register; (2) decimal point position memory means which stores numerical data corresponding to the specific decimal point position and which storage is carried out by the sign part of the auxiliary register; (3) left-shifting means for shifting the contents of the input register left by one digit position; (4) entry mark setting means which is coupled to the auxiliary register and which successively sets binary data into every digit position of the auxiliary register in a direction from the lowest digit to the highest digit so that an entry mark consisting entirely of 1's signals is set into the "one's" digit position of the auxiliary register, said binary data being obtained by successive subtraction of one from the contents of the decimal point position memory means at every digit; (5) right shifting means which is coupled to the auxiliary register and successively sets other binary data into the every digit position of the auxiliary register so that the entry mark in the auxiliary register is shifted right by one digit, the said other binary data being obtained by subtraction of one from the previous data of each digit position of the auxiliary register; and (6) input circuit means which is coupled to the input register and which puts the input figure into a digit position the same as that of the entry mark.
The auxiliary register is mainly used as a multiplier-quotient register in multiplication or division operations and contains no data to be processed during a number entry operation.
When the first figure of an input number is detected during number entry, the entry mark setting means sets an entry mark into the one's position of the auxiliary register. The input circuit means puts the input figure into the same digit position of the input register as that of the entry mark whenever a new figure of the input number is detected.
Before the decimal point of the input number is set in, the left-shifting means shifts the contents of the input register left by one digit position and after the decimal point of input number is set in, the right shifting means shifts the entry mark in the auxiliary register right by one digit position in advance of the entry of the input figure into the input register. Thus, the input number is put into the input register and the decimal point position is fixed.
These and other features will be readily apparent to those skilled in the art from an examination of the following specification and accompanying drawings, wherein:
FIG. 1 is a block diagram of an electronic desk calculator having three registers which are serially arranged by a time division method, each of said three registers being of 16 digit capacity in accordance with the invention;
FIG. 2 is a diagram showing the clock pulses in the electronic desk calculator shown in FIG. 1;
FIGS. 3a -3c are diagrams showing the sequence of the output pulses from the control circuit in the electronic desk calculator shown in FIG. 1;
FIG. 4 is a flow chart for explaining the operations of the electronic desk calculator shown in FIG. 1 in accordance with the invention;
FIGS. 5a-5e are diagrams showing the numbers in the input register for explanation of the operations of the electronic desk calculator shown in FIG. 1 in accordance with the invention;
FIG. 6 is a block diagram of a display system of the electronic desk calculator shown in FIG. 1 in accordance with the invention; and
FIGS. 7a-7e are diagrams showing the figures in the display tubes for explanation of the operations of the display system shown in FIG. 6 in accordance with the invention.
The following description will, for convenience, be of an electronic calculator having three registers, each of which is of 16 digit capacity and holds numbers in BCD code.
Referring to FIG. 1, which shows a specific embodiment of the invention, a circulating register consists essentially of shift registers 1 and 4, INHIBIT gates 2 and 5 and OR gates 3 and 6. A left-shifting means consists essentially of a shift register 31, AND gates 29, 39 and 40, the INHIBIT gate 2 and OR gates 17, 28 and 30. An entry mark setting means consists essentially of the shift register 31, a full adder 33, a 1-bit delay circuit 36, AND gates 27, 29, 34 and 38, INHIBIT gates 5, 32 and 37 and OR gates 6, 28, 30 and 35. A right-shifting means consists essentially of the shift register 31, the full adder 33, the 1-bit delay circuit 36, AND gates 29, 34, 38 and 44, INHIBIT gates 5, 32 and 37 and OR gates 6, 28, 30 and 35. An input circuit means consists essentially of a key board 8, a code-converter 18, AND gates 23, 24, 25, 26 and 41, the INHIBIT gate 2 and OR gates 3, 16 and 17.
The output signal of a 188-bit serial shift register 1 is fed to a 4-bit serial shift register 4 through an INHIBIT gate 2 and an OR gate 3. The output signal of the 4-bit shift register 4 is fed to the input terminal of the 188-bit shift register 1 through an INHIBIT gate 5 and an OR gate 6 so that the two shift register constitute a 192-bit circulating register. In FIG. 1, the means to clear the circulating register are not shown.
Referring to FIG. 2, CL is the master clock pulse which is supplied to the 188-bit shift register 1, the 4-bit shift register 4, and other circuits.
T 1 , T 2 , T 4 and T 8 represent the clock pulses specifying the timing of the output signals from the 188-bit shift register 1 corresponding in accordance with the code "1," the code "2," the code "4" and the code "8," respectively.
T A , T B and T C are the clock pulses specifying the timing of the output signals of the 188-bit shift register 1 corresponding in accordance with the contents of the first register, the second register and the third register, respectively. T-0, T-1, T-2. . . T-15 are the clock pulses specifying the timing of the output signals of the 188-bit shift register 1 correspondingly in accordance with the first digit, the second digit, the third digit and so on up to the 16th digit from the least significant digit. A reference character T-0 shows the time from T-1 to T-15. These clock pulses are supplied from a clock pulse generator 7 in FIG. 1.
As indicated in the above description, the 192-bit circulating register has three registers arranged in series of bits, in time division series of register and in series of digits.
The first register is an auxiliary register which is mainly used as a multiplier-quotient register in multiplication or division operations and contains no data to be processed during a number entry operation. The second register mainly holds an addend, a subtrahend, a multiplicand or a divisor during arithmetic operation and is used as an input register during number entry. The third register usually operates as an accumulator. The least significant digit of each register except the auxiliary register holds the sign of each register.
The least significant digit of the auxiliary register is used as means for memorizing a decimal point position. The decimal point position is defined by depression of a key for the entry of figures when the calculator is in "decimal point position setting mode." The "decimal point position setting mode" is set by selective depression of a mode switch.
When a key of the key-board 8 for the entry of figures is depressed, an instruction pulse whose pulse width is equal to the time necessary for the circulating register to cycle one round appears at the output terminal 10 of the control circuit 9 connected to the key-board 8 for the entry of figures. And the output signal of an AND gate 15 becomes logically "1" at the time of T-0 and TA. Only when the output signal of the AND gate 15 is logically "1" is any output signal from the output circuits 19, 20, 21 and 22 of the code-converter 18 set into the least significant digit of the first register in the circulating register through any of the AND gates 23, 24, 25 and 26, and through the OR gate 3, gates 23-26 being controlled by the output signal of the OR gate 16. At the same time, the INHIBIT gate 2 is closed by the control of the output signal of the AND gate 15 through the OR gates 16 and 17 and the signal recirculation in the circulating register is stopped.
Information from the key-board 8 for the entry of figures is converted into a binary coded decimal (BCD) signal by the code-converter 18. The output circuits 19, 20, 21 and 22 are provided with the output signal from the code-converter 18 corresponding to the code "1," the code "2," the code "4" and the code "8," respectively. Each output signal from the code-converter 18 enters the specified bit position of the least significant digit of the first register through any of the AND gates 23, 24, 25 and 26 and through the OR gate 3 when the output signals from the output circuits 19, 20, 21 and 22 of the code-converter 18 are coincident with clock pulses T 1 , T 2 , T 4 and T 8 , respectively, at the time specified by the output signal of the OR gate 16.
The following example shows the operation of decimal point position setting of "3" which means three digits capacity to the right of the decimal point. By depression of the key specifying "3" on the key-board 8 for the entry of figures, the output signals of the output circuits 19 and 20 of the code-converter 18 are set into the least significant digit of the first register through the AND gates 23 and 24 at the time of T-0 and TA. Thus, the least significant digit of the first register holds "3" in BCD form. For number entry operation, the mode of the calculator is switched to "normal" from "decimal point position setting."
When a key on the key-board 8 for the entry of figures is depressed, instruction pulses are generated at each of output terminals 11, 12, 13 and 14 of the control circuit 9 connected to the key-board 8.
Referring to FIG. 4, in the action step (a), a test is made to determine whether this depression of the key of the key-board 8 is just after the arithmetic operation. In the action step (b), the entry mark is set into the first register. The entry mark is a marker signal and is used to specify the digit position of the second register into which the number is to be entered. The new figure is set into a digit position of the second register corresponding to the entry mark position of the first register.
The operation of the action step (b) is carried out by the instruction pulse from the output terminal 11 of the control circuit 9 shown in FIG. 1. In the action step (c), a test is made to determine whether the decimal point key of the key-board 8 for the entry of figures has been depressed previously. In the action step (d), the entry mark in the first register is right-shifted by one digit position. The operation of the action step (d) is carried out by the instruction pulse from the output terminal 12 of the control circuit 9. In the action step (e), the new data corresponding to the specified key of the key-board 8 for the entry of figures is set into a digit position of the second register at a position corresponding to the entry mark digit position of the first register. The operation of the action step (e) is carried out by the instruction pulse from the output terminal 13 of the control circuit 9. In the action step (f), the contents of the second register are left-shifted by one digit position. The operation of the action step (f) is carried out by the instruction pulse from the output terminal 14 of the control circuit 9. The test operations in the action step (a) and (c) are carried out with other operations at the same time. In FIG. 1, the test circuits for the above are not shown.
FIGS. 3(A), (B) and (C) show the time relations among the instruction pulse sequences depending upon the combination of the action steps of the flow chart shown in FIG. 4. The length of the instruction pulse is equal to the time necessary for the circulating register to cycle one round. Each instruction pulse starts at T-0 and terminates at T-15.
FIG. 3(A) shows the case when the key of the key-board 8 for the entry of figures is depressed just after the arithmetic operations. FIG. 3(B) shows the case of depression of two figure entry keys in succession. FIG. 3(C) shows the case of depression of the figure entry key after depression of the decimal point key.
The following description explains the operation of the circuits for each action step in FIG. 4.
When the instruction pulse is generated at the output terminal 11 of the control circuit 9, the output signal of the 188-bit shift register 1 is put into the 4-bit shift register 31 through the AND gate 29 and the OR GATE 30 at the time of T-0 and T A as the AND gate 27 becomes logically "1" at the time of T-0 and T A and the output signal of the AND gate 27 closes the INHIBIT gate 32 and opens the AND gate 29 through the OR gate 28. That is, the contents of the least significant digit of the first register are put into the 4-bit shift register 31, but the least significant digit of the first register does not lose the data.
The output signal of the 4-bit shift register 31 is fed to the input terminal Y of the full adder 33. As there is no input signal at the input terminals X and Z of the full adder 33, the output signal from the output terminal S of the full adder 33 is therefore the same signal as the input signal to the input terminal Y of the full adder 33 and is fed to the input terminal of the 4-bit shift register 31 through the INHIBIT gate 32 and the OR gate 30. Thus, a circulating register including the 4-bit shift register 31 and the full adder 33 is formed. Then, the circulating register holds the same signal as that of the least significant digit of the first register in the main circulating register. Next, at the time of T-1 and T B , a "1111" signal is added to the contents of the circulating register including the 4-bit shift register 31 and the full adder 33 as the AND gate 34 having one input signal feed from the OR gate 35 connected with the output terminal 11 of the control circuit 9, becomes logically "1" at the time of T-0 and T B and the output signal of the AND gate 34, which is equal to "1111" at each time T B of T-0 is fed to the input terminal X of the full adder 33. But, the addition of "1111" to the contents of the circulating register is equivalent to the subtraction of "0001" from the contents of the circulating register because the carry output terminal C of the full adder 33 is connected to the input terminal Z of the full adder 33 through the 1-bit delay circuit 36 and the INHIBIT gate 37 and the input signal to the input terminal Z of the full adder 33 from carry output terminal C is inhibited at the time of T 1 by means of the INHIBIT gate 37. And the output signal from the output terminal S of the full adder 33 enters the 192-bit circulating register through the AND gate 38 and the OR gate 6 at the time of T-1 and T B while the INHIBIT gate 5 is closed. The output signal from the output terminal S of the full adder 33 is set into the first register in the 192-bit circulating register. After the above operation at the time of T-1 and T B , the circulating register including the 4-bit shift register 31 and the full adder 33 holds the result of the previous subtraction till the next subtraction operation at the time of T-2 and T B . At the time of T-2 and T B , T-3 and T B , . . . T-15 and T B , the same operations explained above are repeated.
The following example shows the case when the least significant digit of the first register holds "3," that is, "0011." After the above operations, the first digit of the first register holds "0011;" the second digit, "0010;" the third digit "0001;" the fourth digit, "0000;" the fifth digit, "1111; " the sixth digit, "1110" and so on.
The "1111" is used as the entry mark for the entry of a figure and the fifth digit holds the entry mark. The foregoing is the explanation of the entry mark setting operation into the first register. The following description is of the conventional left-shifting operation of the contents of the second register.
When the instruction pulse is generated at the output terminal 14 of the control circuit 9, the signal of each digit of the second register is fed into the 4-bit shift register 31 from the 188-bit shift register 1 through the AND gate 29 and the OR gate 30 as the AND gate 39 becomes logically "138 at the time of T-0 and T B and the INHIBIT gates 2 and 32 are closed by the output signal of the AND gate 39 through the OR gates 17 and 28, respectively. At the same time the previous contents of the circulating register including the 4-bit shift register 31 and the full adder 33 are transferred to the 192-bit circulating register at the one digit higher position in the second register than before through the AND gate 40 and the OR gate 3. The signal of each digit of the second register is held in the circulating register including the 4-bit shift register 31 and the full adder 33 till the next "store and transfer" operation. The following description is of the number entry operation into the second register that is the input register of the calculator. time,
The flip-flop circuit 42 is a JK flip-flop circuit controlled by clock pulse CL (cf. FIG. 2) and is set to "1" at the time of T C . The flip-flop 42 is reset to "0" at the time of T A by the control of the INHIBIT gate 43 whenever the output signal of the 188-bit shift register 1 corresponding to each digit position of the first register is not "1111." That is, when the first register holds the entry mark in any digit position, the output signal of the flip-flop 42 remains "1" at the succeeding time corresponding to the second register. When the instruction pulse is generated at the output terminal 13 of the control circuit 9, the information specified by the depression of the key of the key-board 8 for the entry of figures is converted into the BCD code signal by the code-converter 18 and is set into the 192-bit circulating register at the position of the specified digit position of the second register through any of the AND gates 23, 24, 25 and 26 by the control of the output signal of the OR gate 16. At the same time, the INHIBIT gate 2 is closed as the output signal of the AND gate 41 connected the output terminal 13 of the control circuit 9 becomes logically "1" at the time of T B when the output signal of the flip-flop 42 is "1."
Thus, the new figure is set into a digit position of the second register the same as the entry mark in the first register.
The right shifting operation of the entry mark is described below.
When the instruction pulse is generated at the output terminal 12 of the control circuit 9, the contents of the second digit position of the first register is fed into the 4-bit shift register 31 through the AND gate 29 and the OR gate 30 as the AND gate 44 connected to the output terminal 12 of the control circuit 9 becomes logically "1" at the time of T-1 and T A and the output signal of the AND gate 44 closes the INHIBIT gate 32 through the OR gate 28. The contents of the circulating register including the 4-shift register 31 and the full adder 33 is transferred to the 192-bit circulating register through the AND gate 38 and the OR gate 6 at the next "store and transfer" operation same as the entry mark setting operation. Thus, the entry mark is right shifted by one digit position.
After right-shifting of the entry mark by the entry mark setting operation exactly similar to that of the previous example, the first digit holds "0011;" the second digit, "0001;" the third digit "0000;" the fourth digit, "1111;" the fifth digit, "1110;" the sixth digit, "1101" and so on.
The following description explains by way of example the operation of entering the number 12.345.
When the key corresponding to the figure "1" is depressed, the actions shown in FIG. 4 are successively executed in the order (a), (b), (c), (f), and (e). In the action step (b), the instruction pulse generated at the output terminal 11 of the control circuit 9 sets the entry mark into the fifth digit position of the first register.
In step (f), the contents of the second register are shifted to the left by one digit position; that is, to the position of next higher significance, but nothing significant occurs because the second register has previously been cleared.
In step (e), the digit "1" is set into the fifth digit position of the second register by control of the AND gate 41. This condition of the second register, that is, the input register, is represented in FIG. 5(A).
When the key corresponding to the figure "2" is depressed, actions shown in FIG. 4 are successively executed in the order (a), (c), (f) and (e).
In step (f), the number in the second register is shifted to the left by one digit position, and in step (e) the digit "2" is set into the fifth digit position; that is, the units digit position of the second register. The condition of the second register is now represented by FIG. 5(B).
When the key corresponding to the figure "3" is depressed after the depression of the decimal point key, the actions shown in FIG. 4 are successively executed in the order (a), (c), (d) and (e).
In step (d), the entry mark in the first register is shifted to the right by one digit position; that is, to the position of next lower significance. Therefore, in step (e) the digit "3" is put into the fourth digit position; that is, the one-tenth digit position of the second register. The condition of the second register is now represented by FIG. 5(c).
Similarly, when the keys corresponding to the figures "4" and "5" are successively depressed, the digits "4" and "5" are put into the input register at the proper position. The consequent conditions of the second register are then represented, respectively, by FIGS. 5 (D) and (E).
FIG. 6 is a block diagram of a display system displaying the contents of the input register which is used as an output register of the electronic desk calculator shown in FIG. 1. For display of the contents of the input register, fourteen glow discharge type numerical indicator tubes such as NIXIE tubes are used since the contents of the least significant digit of the input register, that is, decimal point position, are displayed by the conventional method and the contents of the most significant digit of the input register are not displayed.
In FIG. 6, the numerical indicator tubes and the peripheral circuits corresponding to the digit position from the third digit to the 13th digit of the input register are not shown to simplify the explanation.
Referring to FIG. 6, the one end of the zero suppress switch 60 is connected to the anode power supply V A and the other end of the zero suppress switch 60 is connected to the one ends of all of the anode selection switches 54, 55 and 56.
The other end of the anode selection switches 54, 55 and 56 is connected to the anode of the indicator tubes 51, 52 and 53, respectively. The indicator tube 51 is used for display of the contents of the second digit of the input register. The indicator tubes 52 and 53 are for the 14th and the 15th digits of the input register. Therefore, by opening the zero suppress switch 60, the anode supply voltage is not supplied to any of the anodes of the indicator tubes 51, 52 and 53 and none of the indicator tubes are lighted.
The cathode terminal corresponding to the figures from "0" to "9" of each indicator tube 51, 52 and 53 is connected to the corresponding output terminal corresponding to the figures from "0" to "9" of the decoder-driver 61 which connects the respective output terminals corresponding to the figures from "0" to "9" to the ground depending upon the contents of the 4-bit shift register 62 which is used as buffer register means. The input signal to the 4-bit shift register 62 is fed from the output terminal of the 188-bit shift register 1 shown in FIG. 1.
The four JK flip-flops 68, 69, 70 and 71 constitute a 4 stage binary counter which counts up from "0000" to "1111" by the clock pulse T C and which is supplied from the clock pulse generator 7 shown in FIG. 1.
The counter consisting of the JK flip-flops 68, 69, 70 and 71 is called a "C" counter. The clock pulse T-0 specifies the time when the contents of the "C" counter is "0000," that is, 0. The clock pulse T-1 . . . T-15 specifies the time when the contents of "C" counter is "0001" . . . "1111," that is, 1 . . . 15.
Another four JK flip-flops 64, 65, 66 and 67 constitute a 4 stage binary reverse counter which counts down from "1111" to "0000" by the output signal of the AND gate 72 and which is called an "S" counter and is used as anode selection counter means. The "S" counter is used for selective switching of the anode selection switches 54, 55 and 56.
The output signal of the OR gate 73 becomes logically "1" when the output signal of the AND gate 77 or the AND gate 78 become "1;" that is, when the states of both JK flip-flops 64 and 68 are the same. The OR gate 74 is used to detect whether the states of both JK flip-flops 65 and 69 are the same by the output signal of the AND gate 79 or the AND gate 80. Each of the OR gates 75 and 76 is used to detect whether the states of the JK flip-flops 66 and 70 are the same by the output signal of the AND gate 81 or the AND GATE 82 and whether the states of the JK flip-flops 67 and 71 are the same by the output signal of the AND gate 83 or the AND gate 84. Therefore, the output signal of the AND gate 72 becomes "1" at the time of T B when the contents of both the "S" counter and the "C" counter become the same. When the output signal of the AND gate 72 changes state from "1" to "0," in detail, at the trailing edge of the clock pulse T B , the "S" counter is counted down by 1.
The following description is of the case when the switching circuit 60 is closed.
In the initial condition, the content of the "S" counter is assumed to be 14; that is, "1110." When the content of the "C" counter becomes "14," that is, at the time of T-14, the output signal of the AND gate 72 becomes "1" at the time of T B and the four clock pulse synchronized by CL appear at the output terminal of the AND gate 63.
The above four clock pulses shift the output signal from the 188-bit shift register 1 to the 4-bit shift register 62. That is, the contents of the 15th digit position of the second register are transferred to the 4-bit shift register 62. The 4-bit shift register holds the contents of the 15th digit position of the second register and cause the decoder-drive to drive selectively. At the same time, the "S" counter is counted down to "13" at the trailing edge of T B . Then, the AND gate 59 becomes "1" as the contents of "S" counter are "13" and the indicator tube 53 displays the contents of the 15th digit position of the second register as the anode selection switch 56 is closed as the decoder-driver 61 is controlled by the contents of the 4-bit shift register 62 to move to the position corresponding to the number in the shift register 62. At the next time T-13, the contents of the 14th digit position of the second register are transferred to the 4-bit shift register 62 and the "S" counter is counted down to "12." At the same time, the indicator tube 52 displays the contents of the 14th digit position of the second register as the anode selection switch 55 is closed by the output signal of the AND gate 58.
In this manner, the fourteen indicator tubes display the contents of the second register in the direction from the 15th digit position to the 2nd digit position.
The flip-flop circuit 89 is a clock pulse driven JK flip-flop by CL and controls the zero suppress switch 60. When the output signal of the flip-flop 89 is "1, " the zero suppress switch 60 is closed. When the output signal of the flip-flop 89 is "0," the zero suppress switch 60 is opened and the display on the indicator tubes is suppressed. The flip-flop 89 is reset by the output signal of the AND gate 86 through OR gate 87. The AND gate 86 becomes "1" when the content of the "S" counter becomes "14," that is, one step before the time of displaying the contents of the 15th digit position of the second register and the output signal of the AND gate 86 resets the flip-flop 86 through terminal K. Therefore, the zero suppress switch 60 is opened just before the display of the contents of the 15th digit position of the second register.
When both the "S" counter and "C" counter become "14," the information to be displayed enters the 4-bit shift register 62 and the "S" counter counts down to "13."
If any of the contents of N1, N2, N4 and N8, which constitute the 4-bit shift register 62, is not "0," the flip-flop 89 is set through the OR gate 88 and the indicator tube is lighted as the zero suppress switch 60 is closed.
If all of the contents of N1, N2, N4 and N8 are "0," the flip-flop remains in the reset state and the zero suppress switch 60 is opened.
As explained above, the display of the leading non-significant zeroes are suppressed until the appearance of a significant figure.
During a data entry operation, the first register which is the auxiliary register, holds the entry mark and other signals as explained before. To suppress the display of the trailing non-significant zeroes below the decimal point position, the display of the contents of all the digit positions below the digit position corresponding to one digit below the entry mark in the first register which is represented as "0000" in the first register must be suppressed.
When the output signal of the AND gate 72 becomes "1" and all the output signals of A1, A2, A4 and A8 which constitute the 4-bit shift register 4 shown in FIG. 1 are "0, " the flip-flop 89 is reset by the output signal of the AND gate 85 through the OR gate 87 and the zero suppress switch 60 is closed.
The clock pulse T 1 is added to the input terminal of the AND gate 85 to specify the time when the 4-bit shift register 4 holds the contents of the first register. Thus, the trailing non-significant zeroes are not displayed.
FIGS. 7 (A) - (E) show the display conditions corresponding to each step of the number entry operation of the number 12.345.
As mentioned above, a digital data processor having a simple construction in accordance with the invention facilities the number entry by using an entry mark setting and shifting operation while the decimal point is fixed. It is not necessary to shift the contents of the input register in advance of the elementary arithmetic operation. Therefore, overflow of the contents of the input register can be avoided.
The electronic desk calculator according to the invention can suppress easily the display of the non-significant zeroes below the decimal point position by use of the entry mark setting and shifting operation.
The electronic desk calculator according to the invention can be easily handled and is free from misoperation.