05/070222

04/18/1972

09/08/1970

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Data Printer Corporation (Cambridge, MA)

101/93.290

B41J9/14; B41J9/00; B41J9/10; B41J1/34

101/93C 340/172.5

3240920	Data transmission verifier	March 1966	Barbagallo et al.
3430210	ARRANGEMENT FOR THE CONTROL OF THE RECORDING OF ALPHANUMERICAL CHARACTERS	February 1969	Foure et al.
3430211	SYSTEM FOR STORING CODED CHARACTER REPRESENTATIONS	February 1969	Foure et al.
3555518		January 1971	Nelson

Penn, William B.

Having thus described my invention, what I claim is

1. In combination with a printer having a character signal generator for producing first character signals each indicating the character following the next character to arrive in printing position, memory means for storing second character signals representing a line of characters to be printed, and comparator means for comparing each first character signal with all of said second character signals and producing a binary signal for each comparison having a first or a second truth value according as the first and second signals agree or do not agree, respectively, sequencing means controlled by said character signal generator for sequentially producing a first and a second control signal, first register means for storing a sequence of binary signals, second register means for storing a sequence of binary signals, means responsive to said first control signal for transferring the contents of said first register means to said second register means, means responsive to said second control signal and controlled by said comparator means for storing the binary signals produced by said comparator means in said first register means, and printing means responsive to said second control signal and controlled by said second register means for printing characters in locations directed by the contents of said second register means.

2. The apparatus of claim 1, in which said character signal generator comprises a character pulse generator for producing a pulse each time a different character approaches printing position, and a counter advanced by said pulses for producing signals each representing the character following the one next coming into printing position.

3. The apparatus of claim 1, in which said printing means comprises a pulse generator responsive to said second control signal to produce a timing pulse of predetermined amplitude and duration, an image forming means for each column in the line to be printed and responsive to applied energy to form an image, and gate means controlled by said timing pulse and said second register for supplying energy to those image forming means selected by the contents of said second register in amounts determined by the amplitude and duration of said timing pulse.

4. The apparatus of claim 3, in which said image forming means each comprises an actuating solenoid having a winding connected in series with a source of energy and a current control switch, said switch being closed by said gate means when selected by the contents of said second register for the duration of said timing pulse and supplying current to said winding in an amount determined by the amplitude of said timing pulse.

5. In a high speed printer comprising signal generating means for producing a sequence of first character signals each identifying a different character approaching printing position, and storage means for storing an ordered sequence of second character signals, one for each column in a line to be printed, first register means for storing an ordered sequence of binary signals, one for each column in the line to be printed, second register means for storing an ordered sequence of binary signals, one for each column in the line to be printed, sequencing means controlled by said signal generating means for sequentially producing a first control signal and a second control signal when each first character signal is produced, means responsive to said first control signal for transferring the contents of said first register means to said second register means, comparator means responsive to said second control signal and controlled by said storage means and said signal generating means for comparing each of said first character signals with all of said second character signals and storing a sequence of signals in said first register means each having a first or a second truth value according as the first character signal is the same as or different from the second character signal for each comparison, and printing means responsive to said second control signal and controlled by said second register means for printing characters in the columns determined by the contents of said second register means.

6. The apparatus of claim 5, further comprising means responsive to said control signal for producing a third control signal intermediate said first and second control signals, and means responsive to said third control signal for clearing said first register means.

7. In an m column high speed printer having m selectively actuatable print control means, one for each column, each print control means being responsive to an applied signal for effecting printing in a different column, gate means for each print control means, each gate means being responsive to two applied signals to apply a signal to the corresponding print control means, a first one-bit register associated with each gate means, a second one-bit register associated with each gate means, sequencing means responsive to an applied signal for sequentially producing first and second control signals, means responsive to said first control signal for transferring the contents of each first register to the associated second register, selecting means responsive to said control signal for storing a sequence of signals in said first registers, means responsive to said second control signal for applying a first signal to said gate means, and means connecting each second register to the associated gate means to apply or not apply a signal to the gate means in dependence on the contents of the register.

8. The apparatus of claim 7, in which said selecting means comprises an available character signal generating means for producing signals indicating the character following the character that can next be printed, storage means for storing a sequence of requested character signals representing a line to be printed, comparator means controlled by said character signal generating means and said storage means and responsive to said second control signal for comparing each available character signal with all of said requested character signals and storing a binary signal having a first or a second truth value according as said compared signals agree in the first register corresponding to the column in which the requested character is to be printed, and further comprising means controlled by said selecting means for applying a signal to said sequencing means each time an available character signal is produced.

9. In a high speed printer having a character pulse generator for producing character pulses each signifying the approach of a different character to printing position, code signal generating means controlled by said character pulse generator for producing a sequence of code signals, one for each of a series of characters to be printed, and one for each character pulse, recirculating memory means having a plurality of sequential storage locations for storing a group of signals each representing a character in a line to be printed and responsive to applied shift pulses to shift the locations of the stored group of signals once for each applied shift pulse in a sequential loop, comparator means controlled by said code signal generating means and said memory means for producing a true compare signal when the signal stored in a predetermined one of said storage locations agrees with the signal produced by said code signal generating means, sequencing means controlled by said character pulse generator for sequentially producing first, second, and third control signals, a group of first register means, one for each storage location in said memory means, means responsive to said second control signal for clearing said first register means, means responsive to said third signal for producing a train of shift pulses, one for each storage location in said memory means, means for applying said shift pulses to said memory means, means controlled by said comparator means and responsive to said shift pulses for sequentially storing in said first register means signals each having a first or a second truth value according as said true compare signal is or is not produced, respectively, a group of second register means, one for each first register means, means responsive to said first control signal for transferring the contents of said first register means to said second register means, and printing means controlled by said second register means and said third signal for printing characters in columns dependent on the contents of said second register means.

10. The apparatus of claim 9, in which said printing means comprise a group of hammer driving solenoid windings, one for each storage location in said memory means, an electrical source, a group of electronic switches, one for each winding, each of said switches having load terminals connected in series with said source and with a different one of said windings, each of said switches having a control terminal, a group of control circuits, one for each switch, each control circuit comprising an output terminal connected to a different one of said control terminals and two input terminals, each of said control circuits being responsive to signals of a predetermined truth value applied to both of said input terminals to produce a signal on said output terminal effective to close the switch to which it is connected, each of said second register means being operatively connected to a different one of said first input terminals to close the associated switch when said and only when the stored signal indicates the associated winding is to be energized and a second signal of said predetermined truth value is applied to the second input terminal of the control circuit, and pulse generating means connected to all of said second input terminals and responsive to said third control signal to apply said second signal to said second input terminals for a predetermined time.

My invention relates to high speed printers, and particularly to a novel print cycle control system. The

High speed printers of the line at a time type have been highly developed and widely accepted. Such printers generally operate on a cycle divided into a paper moving interval followed by a printing interval. Previous to a printing operation, data is normally registered representing the characters to be printed in the several columns on the record sheet in the next line to be printed. During the printing cycle, this stored data is processed and, for each column to be printed, compared with the position of the type carrier relative to the print station so that the image forming device for each column can be actuated at the proper time to print the selected character on the line in the column selected. The print cycle thus involves the operations of identifying the proper character to be printed in each column, timing the initiation of the impact device for each column so that the proper character is printed in the correct registry, and metering to each image forming device the correct amount of energy so that a uniform line of print of good quality is produced. The objects of my invention are to facilitate the data processing and timing operations occurring during the print cycle of a high speed printer.

Briefly, the above and other objects of my invention are attained by means of data processing apparatus, under the control of conventional character and index pulse generators, connected between a conventional printer buffer and the image forming devices of the printer to carry out the several functions required of the printer following each character pulse. The apparatus includes two registers, each capable of containing a signal for each column indicating whether or not the image forming device for that column is to be actuated.

Following each character pulse, the contents of the first register are first transferred to the second register. A search of the memory is then begun, during which the first register is loaded with print signals in column positions corresponding to the columns in which images are to be printed following the next character pulse.

During the memory scan, the contents of the second register control the image forming circuits of the printer to select which columns are to receive image forming energy. The necessary energy is provided by a series of current control switches, one for each column, with which constant current is supplied to those image forming devices to be activated for a predetermined time under the control of a standardized image control pulse, generated once for each character pulse. The amplitude as well as the duration of the image forming pulse is controlled. The current control switches respond to both amplitude and the duration of the image control pulse to deliver measured amounts of energy to the image forming devices. The result is a simple and effective system for accurately producing images with a minimum of complex timing circuits.

The manner in which the apparatus of my invention is constructed, and its mode of operation, will best be understood in the light of the following detailed description, together with the accompanying drawings, of a proposed embodiment thereof.

In the drawings,

FIG. 1 is a schematic block and wiring diagram of a print control system in accordance with my invention;

FIG. 2 is a composite timing chart illustrating pulses formed during the operation of the apparatus of FIG. 1; and

FIG. 3 is a schematic wiring diagram of typical circuits useful in the print control system of FIG. 1.

Referring now to FIG. 1, I have shown my invention in a particular and exemplary embodiment in which it comprises the print control system for a high-speed impact drum printer. Application of the invention in its broader aspects to printers of other forms will be apparent to those skilled in the art as the description proceeds. Those aspects of the printer which may be of conventional construction, and will be understood by those versed in the art, will be but briefly alluded to.

In FIG. 1, the printer is shown to comprise a movable type carrier in a form of a print drum 1 on which rows of characters are engraved in a conventional manner. Conventional means, not shown, are provided to rotate the drum 1 at constant speed. In a typical configuration, there would be 64 different characters available for printing in each of 132 columns. The like characters, such as the A's, are arranged in straight rows parallel to the axis of the drum so that all like characters come into printing position with respect to a bank of print hammers H1 through H132 at the same time.

Each of the print hammers, such as the hammers H1 and H132 shown, is arranged to be actuated by an actuating solenoid having a winding, such as the winding L1 for the hammer H1 and the winding L132 for the hammer H132. The showing of the hammers and their actuating windings is intended as a functional schematic diagram. In practice, any conventional hammer and actuating assembly can be employed, although the actuators and print hammers are preferably of the kind shown and described in copending U.S. application Letters Patent Ser. No. 822,985, filed on May 8, 1969 by Joseph Knokel and Frank H. Schaller for Print Hammer Actuator for High Speed Printers and assigned to the assignee of this application.

Each of the windings is provided with an independent actuating circuit extending from a power supply terminal at a potential + B1, through the winding such as L1, and through an electronic switch such as S1 to ground. The corresponding switch circuit for the winding L132 extends through a switch S132 to ground. The switches such as S1 and S132 may be conventional electronic switches having load terminals such as b and c for the switch S1 and a control terminal such as a. A particular and preferred embodiment of these switches will be described below in connection with FIG. 3.

Each of the switches such as S1 and S132 is arranged to be closed when a logic 1 signal appears on an output terminal of an associated AND gate such as a gate CG1 for the switch S1 and a gate CG132 for the switch S132. While AND gates such as CG1 and electronic switches such as S1 of any conventional design may be employed within the broader aspects of my invention, in its preferred embodiment, the gates and switches correspond to those to be described in more detail below in connection with FIG. 3.

Each of the AND gates such as CG1 and CG132 has two input terminals, one of which is connected to the output terminal of a conventional one shot multivibrator OS. When triggered, the multivibrator OS produces a pulse FP that enables all the gates CG1 through CG132.

The second input terminal of each of the gates such as CG1 is connected to the logic 1 output terminal of a register, here shown as a conventional flip-flop F1. Each of the other gates such as CG132 similarly has an input terminal connected to the logic 1 terminal of a flip-flop such as F132. When the flip-flops such as F1 are set to supply a logic 1 signal to the gates such as CG1, and the pulse FP is produced, the corresponding switch such as S1 will be closed to pass current through the winding such as L1 for the duration of the pulse FP and cause the hammer such as H1 to strike toward the print drum, engaging conventional intermediate paper and ribbon, not shown, to produce an image.

During the printing cycle, each time a different character comes into printing position, the 132 registers F1 through F132 are each set or not set according as the character is to be printed or not printed, respectively, in the corresponding column. The apparatus for so loading the registers F1 through F132 will next be described.

Basic timing in the print cycle is provided by a conventional character pulse generator generally designated 2 and a conventional index pulse generator generally designated 3. While these generators may take that variety of forms known to those skilled in the art, as here shown the character pulse generator 2 comprises a toothed ferromagnetic disc 4 having a tooth such as 5 for each different character that can be printed. The teeth cooperate with a magnetic circuit including a stationary pickoff coil 6 to produce a pulse in the coil 6 each time a character approaches printing position. Similarly, the index pulse generator may comprise a single tooth 7 of ferromagnetic material fixed to the shaft 8 on which the drum 1 is carried to produce a pulse in a coil 9 once for each revolution of the print drum.

The pulses produced by the coil 6 are applied to a conventional pulse shaping circuit PS1 to produce a character pulse CP for each pulse induced in the coil 6. Similarly, the pulses induced in the coil 9 are applied to a conventional pulse shaping circuit PS2 to produce an index pulse IP for each revolution of the print drum 1.

The character pulses CP are applied to the input terminal of a six stage counter 10. The counter 10 may be a conventional electronic binary counter producing a digital output signal on six output leads such as 11 that has a different one of 64 values for each of the 64 different characters that can be printed. The index pulse IP is applied to reset the counter once each revolution, so that its count always accurately represents the character next coming into position after the character then coming into position has passed through the printing position and been printed or not in the selected columns.

The character pulses CP are also applied to one input terminal of a two input terminal AND gate 12. The gate 12 receives a second input signal, labeled PRINT, from a flip-flop PF1, to be described. When the PRINT signal is present at logic 1, and a character pulse CP is present, the gate 12 produces a gated character pulse labeled GCP. This pulse is applied to a conventional delayed pulse generator DPG1, of any conventional design. The delayed pulse generator DPG1 produces a transfer pulse labeled XFR following the pulse GCP in the manner shown in FIG. 2. The pulse XFR is applied to a second delayed pulse generator DPG2 to produce a clear pulse, labeled CLR in FIG. 1, and following the transfer pulse XFR in the manner shown in FIG. 2.

The clear pulse CLR is applied to a conventional 132 bit shift register 13, to be described, to reset the shift register so that each of its 132 bits are at logic 0. The pulse CLR is also applied to a delayed pulse generator DPG3, which produces a START pulse following the pulse CLR as illustrated in FIG. 2.

The START pulse is applied to the set input terminal of a conventional flip-flop PF2 to set the flip-flop and thereby produce a logic 1 signal, labeled CLOCK ENABLE, at its logic 1 output terminal. The trailing edge of the start pulse triggers the one shot multivibrator OS to produce the pulse FP, as illustrated in FIG. 2.

The apparatus includes a conventional recirculating line memory 14 of any conventional construction. It essentially comprises a conventional 132 stage, seven bit per stage shift register and connected for data rotation. The memory 14 may be of conventional MOS construction, or may be a core plane or the like, and includes 132 word storage locations of seven bits each. Suitable gating, reading and writing circuits are provided for entering external digital data on seven input leads, including six data leads 15, of which the first and last are shown, and a lead 16 on which there is a logic 1 flag bit for each six bit character signal entered on the leads 15.

The signals on the leads 15 and 16 are entered into a first seven bit location in the memory in response to an EXTERNAL LOAD pulse supplied to a lead 17. The next character represented by signals on the leads 15 and 16 is loaded into the first memory location by the subsequent EXTERNAL LOAD pulse, which also effects transfer of the first character into the second location. That action proceeds until 132 characters have been entered into the memory with the first character entered in the 132nd location in position to be read out on six output data leads 18, of which the first and last are shown, and an output flag lead 19. A set of leads 20 interconnects the leads 18 and the leads 15, and a lead 21 interconnects the leads 16 and 19.

After the memory 14 is loaded, a SHIFT pulse, at times provided by a clock oscillator 22 in a manner to be described, causes the contents of each seven bit location in the memory 14 to be transferred into the next location. The contents of the first character entered into the memory in location 132, and appearing on the leads 18, are transferred over to the leads 20 to be entered into the first location of the memory.

As each set of data signals on the leads 18 is read out of the memory 14, it is supplied to a conventional six bit comparator 23, in which the data on the leads 18 is compared with the data on the six output leads 18 11 of the six stage counter 10. When the character represented by the six bit code on the leads 18 agrees with the character represented by the six bit code on the leads 11, a "true compare" bit TC is produced.

When a true-compare pulse TC is produced, it is applied as a FLAG RESET signal to erase the flag bit associated with the character signal that produced it. Thus, as a character is read out of the 132 location in the memory into the comparator, and at the same time over the leads 20 to be loaded into the first character location, if a flag reset and true-compare pulse is produced, the flag bit will be erased.

When a flag bit is produced on lead 19 as the corresponding character is read into the comparator and back into the first location of the memory, it is also applied to one input terminal of a conventional OR gate 24. The output terminal of the gate 24 is connected to the reset input terminal of a conventional flip-flop PF1. A flag bit on lead 19 accordingly resets the flip-flop PF1 and causes it to produce the PRINT signal at logic 1 at its logic 0 output terminal. The flip-flop PF1 is arranged to be set by the transfer pulse XFR.

The OR gate 24 has a second input terminal connected through means schematically shown as a switch SP to a suitable source of potential +B2. The switch SP is momentarily closed at the end of a cycle of paper movement to reset the flip-flop PF1. The closing of the switch SP represents the conventional "start print" signal produced in a conventional manner as well understood by those skilled in the art.

When enabled by the CLOCK ENABLE signal produced by the flip-flop PF2 in its set state, the clock oscillator 22 produces a series of 132 shift pulses that are applied to the memory 14, and to the shift register 13. The shift pulses from the oscillator 22 are also applied to the input terminal of a conventional 132 state counter 31. After 132 such pulses are applied to the counter, it produces an output signal that resets the flip-flop PF2.

The shift register 13 comprises 132 stages of storage, which may be flip-flops or the like, connected as a shift register. A first stage is connected to the output of the comparator 23 to receive the pulses TC. The first stage has an output lead labeled BIT 1 on which a signal representing the contents of the first stage appears. Subsequent stages in the shift register also have corresponding output terminals. For example, the last stage 132 has an output lead on which a signal labeled BIT 132, representing its contents, appears.

When 132 clock pulses are applied by the clock oscillator 22 to the shift register 13, at each shift pulse that causes a character to be supplied from the memory to the comparator 23 that produces a pulse TC, a logic 1 is entered into the shift register. If a pulse TC is not produced, a logic 0 is loaded into the register. The contents of that stage are transferred to the next stage with the succeeding shift pulse, until 132 storage locations in the shift register have been loaded with logic 1's for each pulse TC representing that the character is to be printed in the corresponding column. Thus, at the end of each of the 132 shift pulses, the shift register 13 contains a train of signals, one for each of the 132 columns of the printer, and each indicating by a logic 1 state that the character represented by the current state of the six stage counter 10 is to be printed, or by a logic 0 state that it is not to be printed, in the corresponding column.

Each of the 132 leads labeled BIT 1 through BIT 132 is connected to gates for controlling a corresponding one of the flip-flops F1 through F132. For example, the signal labeled BIT 1 is applied to one input terminal of a two input AND gate 25. The same signal is applied through an inverter 26 to one input terminal of a two input AND gate 27. The output terminal of the gate 25 is connected to the set input terminal of the flip-flop F1, and the output terminal of the gate 27 is connected to the reset input terminal of the flip-flop F1.

Similarly, the signal labeled BIT 132 is supplied to one input terminal of an AND gate 28, and through an inverter 29, to one input terminal of an AND gate 30. The output terminal of the gate 28 is connected to the set input terminal of the flip-flop F132, and the output terminal of the gate 30 is connected to the reset input terminal of the flip-flop 132.

The second input terminals of all of the gates such as 25, 27, 28, and 30 are connected to the output terminal of a delayed pulse generator DPG1 to receive the transfer signal XFR. Thus, when the signal XFR is produced, the contents of the shift register 13 are copied into the flip-flops F1 through F132.

The one shot multivibrator OS preferably includes an astable circuit for producing a pulse of a preterminal level and duration at the trailing edge of the start pulse. It also preferably includes as the output stage an operational amplifier to produce a pulse FP of preterminal level and duration that will not be appreciably regulated by the number of the gates CG1 through CG132 that supply current to it, as will be described.

Referring next to FIG. 3, the preferred construction of the gates such as CG1 and the switches such as S1 will next be described. Particular reference will be made to the gate CG1 and the switch S1, but it will be understood the other gates and switches such as CG132 and S132 may be identical.

The input terminal a of the gate G1 may be considered a voltage tolerant input terminal. As will appear, that is because the gate output signal is not particularly sensitive to the voltage levels appearing at the logic 1 output terminal of the flip-flop F1. The advantage of that voltage tolerance is that integrated circuit flip-flops that do not produce precise levels may be employed.

It will be assumed for purposes of illustration that the flip-flop F1 produces a logic 0 level of about 0 volts, and a logic 1 level that may be from +3 to +5 volts. Within that range, the precise levels produced by the flip-flop are not critical.

The gate CG1 comprises a resistor R1 having one terminal connected to the input terminal a of the gate, and a second terminal connected to the output terminal c of the gate and to the anode of a diode D1. The cathode of the diode D1 is connected to the input terminal b of the gate to receive the pulse FP. The gate output level is determined by the level of the pulse FP.

In the discussion that follows, references will be made to forward drops through diodes and transistor junctions. For simplicity of exposition, it will be assumed that all such voltage drops are 0.5 volts. As will be apparent to those skilled in the art, the exact drops will depend on the transistor or diode types. Again for convenience, it will be assumed that the printer is arranged to operate at 600 lines per minute, so that there are about 1.56 milliseconds between character pulses CP. Under those conditions, the duration of the pulse FP may be 1.3 milliseconds, and its level may be +1.75 volts. When the pulse FP is absent, the output terminal of the one-shot multivibrator OS will be assumed to be at ground potential.

With the values assumed, it will be apparent that the input terminal a of the gate CG1 will be at either zero potential, or at a value between 3 and 5 volts, the latter depending upon the exact logic 1 output level produced by the flip-flop F1. Input terminal b will be either at zero volts or at + 1.75 volts. If the associated flip-flop such as F1 is in its reset state, with its logic 1 output terminal at ground potential, then the output terminal c of the gate such as CG1 will be at ground potential approximately, regardless of the voltage at the input terminal b of the gate. When a flip-flop such as F1 is set, then the output terminal c of the associated gate such as CG1 will be at plus 0.5 volts with respect to ground, if the input terminal b is at ground potential, or at 30 2.25 volts with respect to ground, if terminal b is at +1.75 volts. Variations of potential on the input terminal a of the gate G1 will not affect the potential at the output terminal c so long as the logic 1 voltage applied at terminal a is above the voltage at terminal b by at least the forward drop through the diode D1. Thus, the variations in logic voltage levels produced by typical integrated circuits can readily be accommodated.

The output terminal c of the gate CG1 is connected to the control input terminal a of the associated current control switch S1. The current control switch S1 is shown in detail, and corresponds to the current control switch for column 1. Each of the other switches, such as the switch schematically shown at S132 for column 132 in FIG. 1, may be of the same construction as the switch S1.

The input terminal a of the current control switch S1 is connected to the base of a conventional NPN transistor Q1. The collector of the transistor Q1 is returned to a suitable source of positive potential B3+ through a resistor R2. The emitter of the transistor Q1 is connected to ground through a diode D2 and a resistor R5 in series.

The collector of the transistor Q1 is connected to the base of a PNP transistor Q2. The emitter of the transistor Q2 is returned to the positive terminal at the potential B3+ through a resistor R3. The collector of the transistor Q2 is returned to ground through two resistors R4 and R5 in series.

The collector of the transistor Q2 is connected to the base of an NPN power transistor Q3. The emitter of the transistor Q3 is connected to ground through the resistor R5. The collector of the transistor Q3 is connected to the output terminal b of the switch S1, and is also connected to the cathode of a zener diode D3. The anode of the diode D3 is connected to the collector of the transistor Q2 and the base of the transistor Q3.

The hammers of the printer are arranged to be actuated by an actuating solenoid for each hammer, each having a winding such as the winding L1. The solenoid windings such as L1 may be wound in a conventional manner on a core, and arranged to attract an associated armature when energized. The armature may drive the hammer, either directly or through an intermediate actuating arm.

Each hammer actuating solenoid winding such as L1 has one terminal connected to a suitable source of regulated potential B1+, which may be, for example a 40 volt supply. The source B1+ should provide a constant potential within not more than plus or minus 5 percent, regardless of the number of solenoids that are to be actuated at once. That requirement implies a reasonably good power supply, but not necessarily one that would meet the much higher standards of conventional printer power supply circuits.

The second terminal of each hammer solenoid winding such as L1 is connected to the output terminal b of a corresponding current control switch, such as S1. When the power transistor such as Q3 in the switch S1 is biased against conduction, no current will flow through the corresponding coil such as L1. When the transistor Q3 is biased into conduction, current will flow from the positive terminal B1+ through the winding L1, through the collector-to-emitter path of the transistor Q3, and through the resistor R5 to ground. As will appear, the impedance in the collector-emitter path of the transistor Q3 is so controlled that the current through the winding L1 is a constant value depending on the level of the voltage applied to the input terminal a of the switch S1.

The reistor R5 preferably has a small resistance, such as one-half ohm, and should be a 1 percent precision resistor. Its function is to control the current through the winding L1 by means of the voltage across the resistor, which determines the bias on the transistor Q1 when a fixed potential is applied to the base. As will appear, the current through the winding L1 during energization is very much greater than the small current components that flow through the resistor R4 and the diode D2, so that those components are negligible to the regulation achieved.

The circuits shown in FIG. 3 are more fully shown and described in copending U.S. application for Letters Patent Ser. No. 70,002, now U.S. Pat. No. 3,628,100, filed at the same time as this application by John F. Zettler for Hammer Driving Circuits for High Speed Printers and assigned to the assignee of this application.

Typical component values employed in the circuits of FIG. 3 are as follows:

Resistors Diodes Transistors R1 3.3K ohms D1 1N283 Q1 2N3859A R2 10K ohms D2 1N283 Q2 2N2907 R3 150 ohms D3 68 volts, Q3 2N5036 1 watt 1N4761 R4 470 ohms R5 0.5 ohms B1=B3=+140 volts DC L1=5.5 ohms DC

operation of the circuits shown in FIG. 3, which are typical for each column, will next be described. Assume first that the flip-flop F1 is not set. The input terminal a of the gate G1 will accordingly remain at ground. When the pulse FP is produced, raising the potential at terminal b of the gate G1, the output terminal c of the gate G1 will remain at ground potential. Thus, the transistor Q1 will not be biased into conduction. Accordingly, the transistor Q2 will be cut off by the positive potential applied through the resistor R2 to its base. With the transistor Q2 cut off, no current will flow through the resistor R4, and the transistor Q3 will remain unbiased and cut off.

Next, assume that the flip-flop F1 is set following a character pulse CP. When the pulse FP is produced, the potential of the output terminal c of the gate G1 will go to 2.25 volts. That will bias the transistor Q1 into conduction, causing the current to flow from the positive terminal B3+ through the resistor R2, from the collector to the emitter of the transistor Q1, through the diode D2, and through the resistor R5 to ground. The reduced potential at the collector of the transistor Q1 will bias the transistor Q2 into conduction, allowing current to flow from the supply terminal at B3+ through the resistor R3, from the emitter to the collector of the transistor Q2, and through the resistors R4 and R5 to ground. The voltage drop across the resistor R4 will now bias the transistor Q3 into conduction, allowing energizing current to flow from the source terminal +B2 through the solenoid winding L1, from the collector to the emitter of the transistor Q3, and through the resistor R5 to ground. All of these events will of course take place quite rapidly.

The current through the winding L1 will be held to 2.5 amperes by controlling the impedance between the collector and emitter of the transistor Q3. The voltage across the resistor R5 will be established by the transistor Q1 at 1.25 volts. Should this voltage tend to rise, the base-emitter bias on the transistor Q1 will be reduced, raising the potential on the collector of the transistor Q1, and thereby reducing the biasing voltage on the base-emitter junction of the transistor Q2. That will reduce the potential across the resistor R4, thereby increasing the impedance between the collector and the emitter of the transistor Q3.

Should the voltage across the resistor R5 tend to fall, forward bias on the transistor Q1 will be increased, reducing the potential at the collector of the transistor Q1 and increasing the bias on the transistor Q2. That will allow a larger current to flow through the resistor R4, and reduce the impedance presented by the collector-to-emitter path of the transistor Q3, thus supplying more current through the winding L1 and the resistor L5. Thus, precise current control action, determined by the level of the voltage established at the input terminal c of the gate G1, is effective in the presence of minor variations of the power supply voltage B1+ which occur by reason of the different numbers of solenoids such as L1 which may be energized at any given time.

Operation of the apparatus of my invention will next be described with reference to FIGS. 1 and 2. Referring to FIG. 1, assume that the flip-flops F1 through F132 are reset, that the flip-flop PF1's set, and the flip-flop PF2 is reset. The print drum 1 is assumed to be rotated at a constant speed of 600 r.p.m. Character pulses CP are accordingly being produced at intervals of 1.56 milliseconds, and index pulses IP are produced once each 100 milliseconds. Assume that the memory 14 has been loaded with 132 six-bit characters on the leads 15, by application of EXTERNAL LOAD pulses to shift them into the memory, each signal on the leads 15 being accompanied by a logic 1 FLAG bit applied on the lead 16. Assuming the storage location assignments shown, the character signal for column 1 would be loaded into the memory first, and the character signal for column 132 would be that last loaded into the memory over the leads 15 and 16.

Next, assume that a start print signal is given by momentarily closing the switch SP to reset the flip-flop PF1 through the OR gate 24. The PRINT signal will now be produced, enabling the gate 12 to respond to the next character pulse CP to produce a gated character pulse GCP. Assume that the shift register 13 has each of its 132 storage locations set to 0.

The first gated character pulse GCP produced by the gate 12 will cause the delayed pulse generator DPG1 to produce the transfer pulse XFR, as shown in FIG. 2. The pulse XFR will transfer the contents of the shift register 13 into the flip-flops F1 through F132. The flip-flops F1 through F132 will remain reset, as the shift register 13 is cleared at this time. The pulse XFR will also set the flip-flop PF1, removing the signal PRINT and disabling the gate 12.

The pulse XFR also actuates the delayed pulse generator DPG2 2 to produce the signal CLR as illustrated in FIG. 2. This pulse serves to clear the shift register 13, but as it is already cleared no change will take place.

The pulse CLR applied to the delayed pulse generator DPG3 will thereafter produce the START signal. That signal will set the flip-flop PF2 and trigger the one shot multivibrator OS.

The multivibrator OS will produce a pulse FP that is applied to each of the gates CG1 through CG132. However, as all the flip-flops F1 through F132 are now reset, no hammers will be actuated.

With the flip-flop PF2 set, producing the signal CLOCK ENABLE, the clock oscillator 22 will begin to produce SHIFT pulses, and at the same time to advance the 132 state counter 31. The SHIFT pulses will cause the contents of the memory 14 to be supplied one at a time to the comparator 23, and restored to the memory over the leads 20 and 21.

In the comparator 23, the characters supplied from the memory are compared with the signal on leads 11 from the counter 10. During the 132 shift pulses in which the contents of the memory are supplied to the comparator, the counter 10 remains at the state set by the last character pulse CP that produced the pulse GCP.

As each character of the memory 14 is supplied to the comparator 23, a pulse TC is produced or not produced according as the corresponding character is the same as or different from the character in the counter 10, respectively. Thus, if the character code supplied by the counter 10 represents the character A, and the memory had a line of characters all of which are A's, 132 TC pulses would be strobed into the shift register 13. On the other hand, if none of the characters were A's, 132 logic 0's would be supplied to the shift register 13. At the end of the 132 pulses, the shift register 13 is loaded with logic 1's in each location in which the character in the counter 10 is to be printed, and logic 0's in each location that is not to be printed. In the response to the last of the 132 shift pulses, the 132 state counter will reset the flip-flop PF2 and disable the oscillator 22.

As the first and each following shift pulse is applied to the memory 14, and a character is read out of the memory 14 to the comparator, the corresponding FLAG bit on the lead 19 is applied to the gate 24 and resets the flip-flop PF1. Each TC pulse that is produced causes a FLAG RESET signal to be applied to the memory to erase the corresponding flag-bit. However, the result following the first pulse GCP in the print cycle will be that the first SHIFT pulse will cause the first FLAG bit in the memory to reset the flip-flop PF1 and restore the print signal. Subsequent FLAG bits will produce no change because the flip-flop PF1 is already reset.

The next character pulse CP that is produced will advance the counter 10 and enable the gate 12 to produce another pulse GCP. When a subsequent transfer pulse XFR is produced by the delayed pulse generator DPG1, the contents of the shift register 13 will be transferred into the flip-flops F1 through F132. These flip-flops will thus be set or not set depending on whether or not the character formerly represented by the counter 10 and now coming into printing position is to be printed in the corresponding column. The pulses CLR and START will be produced, as described above in connection with the first memory scan cycle, clearing the shift register 13 and beginning a new search of the memory for the character now represented by the counter 10. At the trailing edge of the START pulse, the multivibrator OS will be triggered to produce the pulse FP, causing each of the hammers to be actuated for the columns in which a character is to be printed, as determined by the setting of its corresponding flip-flop F1 through F132. During the pulse FP, the memory search is completed by advancing each character in the memory to the comparator and then restoring it to the memory as described above.

During some memory scan cycle, which may be the first cycle, the 64th cycle, or any intermediate cycle, the last character in the memory will be found to agree with the character in the counter 10. The last such true comparison will cause the flip-flop PF1 to be reset, if it has not been previously reset, and produce the PRINT signal. That will enable another gated character pulse GCP to be produced.

The subsequent produced transfer pulse XFR will transfer the contents of the shift register 13 to the flip-flops F1 through F132 as before. Thus, the characters last directed to be printed will be printed during the subsequently produced pulse FP.

However, the pulse XFR having set the flip-flop PF1, with no flag bits remaining in the memory, the flip-flop PF1 will still be set when the next character pulse CP is produced. That will end the print cycle.

The printer will then enter the cycle in which paper is moved and another line of characters is loaded into the memory. No further operation of the apparatus of my invention will take place until the next start print signal is produced by momentarily closing the switch SP.

While I have described my invention with the respect to the details of a preferred embodiment thereof, many changes and variations will occur to those skilled in the art upon reading my description, and such can obviously be made without departing from the scope of my invention.