Downing, Randall W. (Wheaton, IL)
Nowak, John S. (Wheaton, IL)
Taylor, Frank F. (West Chicago, IL)
Ulrich, Werner (Glen Ellyn, IL)

04/685636

03/21/1972

11/24/1967

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Bell Telephone Laboratories, Incorporated (New York, NY)

714/6

714/12, 714/48, 713/502, 714/E11.063

G06F11/16; H04Q3/545; G06F15/16

340/172.5 235/157

Shaw, Gareth D.

CROSS REFERENCES TO RELATED APPLICATIONS

This is a division of copending application, Ser. No. 334,875, filed Dec. 31, 1963, and relates to a program controlled data processing system wherein there is a requirement for substantially continuous and uninterrupted operation.

What is claimed is

1. A program controlled data handling system comprising:

2. A program controlled data handling system in accordance with claim 1, wherein each of said transmission buses comprises a plurality of parallel transmission paths transformer-coupled to said memories and to said control arrangement.

3. A program controlled data processing system comprising:

4. A system in accordance with claim 3 wherein

5. A system in accordance with claim 3 wherein

6. A central processor of a program controlled data handling system comprising:

7. In a data processing system, a central processor system comprising an active central processor and a standby central processor,

8. In combination,

9. The combination in accordance with claim 8 wherein said means for comparing comprises

10. In combination, a central control system comprising first and second central controls,

11. In combination,

12. The combination in accordance with claim 11 wherein said means for inhibiting the transmission of trouble signals comprises a flip-flop in each of said central processors.

13. A central data processor system comprising

14. A central data processor system in accordance with claim 13 wherein said central processor system comprises means responsive to said trouble signals for momentarily interrupting the performance of said sequences of system work functions and other means for performing remedial work functions in each of said central processors, and

15. A central data processor system comprising

16. A program controlled central processor system for performing a plurality of classes of work functions comprising

17. A central processor system in accordance with claim 16 further comprising a plurality of control and supervisory circuits and wherein each of said central processors comprises

18. A central processor system in accordance with claim 16 wherein said match control circuit comprises means responsive to certain states of said register means for cyclically obtaining from said active and said standby central processor data words from selected data word sources in each of said central processors.

19. A system in accordance with claim 18 wherein said means for cyclically obtaining comprises a binary counter, and

20. A central processor system for performing a plurality of work functions comprising

21. A central processor system comprising

22. A data processing system comprising

23. A data processing system in accordance with claim 22 wherein said central processor system comprises means responsive to said remedial means and to said second signal for recording a data word representative of the location in said program store from which the invalid response was obtained.

24. In a data processing system

25. A central processor system comprising

26. In combination,

27. A central processor system comprising

28. A system in accordance with claim 27 wherein said central control further comprises first and second register means,

29. A central processor system comprising

30. A central processor system comprising

31. A central processor system in accordance with claim 30 wherein said match control circuit further comprises a phase match register and said central processor system comprises means for setting said phase match register to selected states and said means responsive to said match signal is also responsive to the state of said phase match register to gate said data words to said matching means during a phase of said machine cycle defined by the state of said phase match register.

32. A central processor system in accordance with claim 30 wherein said central processor system further comprises operational checking means for detecting faulty responses of said central processor system for generating trouble signals upon occurrence of a faulty response, remedial means responsive to said trouble signal for carrying out remedial system work functions and means responsive to said remedial means for inhibiting the incrementing of said timeout counter.

33. A central processor system comprising

34. A central processor system comprising

35. A central processor system in accordance with claim 34 wherein said match control circuit in said active central processor selectively gates information from data word sources within said active central processor to said first match register within said active central processor and to said second match register within said standby central processor and wherein said match control circuit in said standby central processor selectively gates information from said plurality of data word sources within said standby central processor to said first match register within said standby central processor and to said second match register within said active central processor.

36. In combination,

37. In combination,

38. The combination in accordance with claim 37 wherein said stop signals comprise fast stop signals and delayed stop signals and wherein said means in said standby-central control responsive to said stop signals comprises a stop sequencer,

39. The combination system in accordance with claim 38 wherein each of said central controls comprises a plurality of flip-flop registers and said sequencer in said standby-central control in response to said fast stop signal generates reset signals for resetting certain of said plurality of flip-flop registers in said standby-central control.

40. In combination:

41. The combination in accordance with claim 40 wherein said program store system comprises a plurality of program stores and said program store control write command comprises two words,

42. The combination in accordance with claim 41 wherein said means for executing said commands comprises decoding means and a data reading sequencer,

43. In combination,

44. The combination in accordance with claim 43 wherein said response transmission means comprises

45. A system for automatically controlling the times at which operation of a data handling means is initiated, comprising

46. The system set forth in claim 45 in which the control means includes a plurality of data comparing gate means for comparing the settings of the timing means and the time entry storage means.

47. The system set forth in claim 45 in which the data handling means includes address means for supplying address signals and which includes,

48. The system set forth in claim 47 including addressable reset means supplied with address signals from the data handling means and controlled by the receipt of a particular address to reset the time entry storage means.

49. A system for controlling the periods of operation of a data handling unit of the type capable of carrying out a sequence of programmed operations in response to actuation of a start means and capable of terminating its operation at the conclusion of the program, comprising

50. A data processor comprising:

51. A data processor in accordance with claim 50 wherein said change in the performance of data processing functions includes the initiation of data processing functions not being performed prior to the occurrence of said match.

52. In combination:

53. A data processing system comprising:

54. A data processing system comprising:

55. A data processing system in accordance with claim 54 wherein said system further comprises a plurality of input-output units and transmission means for interconnecting said processors and said input-output units, and

BACKGROUND OF THE INVENTION

Program controlled data processors, which include both general purpose computers and special purpose computers, are employed in many industrial applications which require accurate and continuous operation. A telephone switching system is employed herein as an illustrative example of a program controlled data processing system in which the principles of this invention are advantageously employed.

A telephone switching system is a "near real time" machine in that it must serve the demands of the lines and trunks terminating in the office without unreasonable delays. Further, a telephone switching system must be continuously operable if customer satisfaction is to be achieved and it is not possible to stop the service of a telephone office in the course of the day or the night to effect repairs or changes in the system. It is emphasized that these requirements of machine operation, that is, near real time response and continuous operation are not unique to telephone switching systems, but rather are a requirement of many other data processing systems.

The application of high speed program controlled electronic circuits to telephone switching systems is made economical through the use of a single high speed data processor to serve a large number of lines and trunks on a time division basis. Since a single data processor comprising a control unit and attendant memories serves the entire traffic of the office, a failure of that data processor is disastrous if the processing capacity cannot be rapidly recovered.

It is recognized that equipment failures may occur in the processor of a program controlled telephone switching system and that to a degree full duplication of processor elements can improve the total performance or "dependability" of such offices. The term "dependability" as employed herein is a measure of the ability of the processor to continue to perform its assigned tasks even in the presence of failures of system components.

Data handling systems have employed a number of techniques to assure accurate and continuous data processing; however, each of the prior art arrangements exhibits serious limitations. Certain arithmetic data handling systems repeat groups of work functions and compare the results of these repeated groups of functions. In the event that the results do not agree, the work functions are again repeated. If the second and third results agree, these intermediate results are accepted as valid; however, if they do not agree, processing is halted. Such an arrangement is wasteful of time and would reduce the data handling capacity below a usable limit in a large telephone switching system.

Other data handling systems employ three processors which simultaneously perform operations on the same input data. Output data from the three processors are compared and if the outputs of two or more processors agree, this data is accepted as valid and all three processors proceed to continue processing using the accepted data as the new starting point. This scheme is often termed "a majority logic arrangement. " This approach is not acceptable in a large telephone switching system since it is not only wasteful of equipment in that three complete processing systems are required but, in addition, upon occurrence of trouble in one or more units it is impossible to continue operation within the framework of this approach.

In still other data handling systems the processor is completely duplicated and each processor includes arrangements for detecting internal failures. In the event of an internal failure, operation is mechanically or electrically switched from one processor to the other. The problems of switching from regular to standby units in these systems are such that the data processing capacity of the processing system may be unreasonably interrupted during switching. Further, recovery from such switching is often very difficult.

It is an object of this invention to improve the dependability of a program controlled data processing system.

It is a further object of this invention to reduce the time required to bring about dependable system operation after a trouble in system operation has been detected.

SUMMARY OF THE INVENTION

In accordance with this invention, a program controlled data processing system comprises: functionally equivalent first and second central controls, a memory system which comprises a plurality of independent memories, and transmission circuits which comprise a plurality of independent transmission paths which are selectively connectable to the first and to the second central controls and to the plurality of independent memories. The first and second central controls, the plurality of independent memories and the plurality of independent transmission paths are arranged in selected first and second combinations thereof. Each such combination comprises a selected one of the central controls, selected ones of the independent memories and selected ones of the independent transmission paths. The processor arrangement further comprises circuits for insuring the concurrent performance of identical work functions by the first and second central controls and additional circuits for inhibiting the transmission of command signals from a selected one of the central controls to the input-output system which is served by the data processor.

It is a feature of this invention that since the transmission paths are selectively connectable to both central controls and to each of the plurality of independent memories, it is possible to provide an operable combination of central control, memory, and transmission paths even though multiple troubles may exist in the overall data processing system. Furthermore, by insuring that the first and the second central controls concurrently perform identical work functions, duplicate records are maintained by the processor and this serves to reduce the time required to initiate normal system processing functions after a trouble has occurred and particularly after it has been necessary to re-arrange the central controls, the memory, and the transmission paths into a new working combination of equipments.

In accordance with this invention, the processor system comprises circuits for transmitting trouble signals between the first and second central control and each central control comprises circuits for recording trouble signals transmitted from the other central control. Each central control comprises a number of operational checking circuits for detecting faulty operation in its combination of equipments. The operational checking circuits generate discrete trouble signals within the central control and each central control is responsive to a trouble signal occurring therein to carry out particular remedial actions discrete to that trouble signal. Furthermore, each central control is responsive to a recorded trouble signal (indicative of a trouble signal originating in the other central control) to carry out remedial actions which are identical to the remedial actions carried out in the central control in which the trouble was detected.

It is a feature of this invention that each of the two operating combinations of central control, memory and transmission paths has provisions for checking the operation of the combination, for transmitting indications of detected trouble between central controls and for simultaneously carrying out identical remedial actions within the two central controls.

In accordance with another feature of this invention, the independent memories each include operational checking circuits for monitoring the operation of the memory unit and for transmitting check signals to the central control in response to each command from the central control. Furthermore, the central controls are responsive to such check signals to perform remedial actions if the check signals indicate faulty operation of a memory unit.

In accordance with another feature of this invention, the independent memory units and the central controls each contain register circuits for defining the existing working relationship of these units and the independent transmission paths. The two operating combinations of central control, memory and transmission paths may be considered as an active combination and a standby combination, even though both combinations are carrying out identical work functions. That is, at any given time only the active combination may control the input-output system.

In accordance with still another feature of this invention, the central control of the active combination can generate control signals to control the register circuits in the independent memories and in the central controls to re-arrange these equipments into new relations with the independent transmission paths and thus to achieve new working combinations of central controls, memory and transmission paths.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a general block diagram of a telephone switching system which is employed herein as an illustrative program controlled data processor in the data processing system of FIGS. 3-6;

FIG. 2 is a more generalized block diagram of a program controlled data processor;

FIGS. 3 through 6, arranged as shown in FIG. 89 are a block diagram of a program controlled data processing system in accordance with the invention;

FIG. 7 is a general block diagram of the program store which is a portion of the data processors of FIGS. 1 through 6;

FIG. 8 is a general block diagram of a call store which is a portion of the data processors of FIGS. 1 through 6;

FIG. 9 is a block diagram of the central control of FIGS. 1, 2 and 3;

FIGS. 10 through 63, arranged as shown in FIG. 86, are a detailed diagram of the central control of FIG. 9;

FIGS. 64 through 69, arranged as shown in FIG. 87, are schematic diagrams of the major interconnecting communication paths of the data processor of FIG. 1;

FIG. 70 is a schematic diagram of the matching arrangements shown in FIGS. 3 and 4 and in FIGS. 10-63;

FIG. 71 is a diagram of the enable-verify circuitry which is employed in the input-output circuits of FIG. 1;

FIGS. 72 through 82, arranged as shown in FIG. 88, are a more detailed schematic diagram of the program store of FIG. 7;

FIG. 83 is a time diagram showing the fundamental timing pulses employed in the central control of FIG. 9 and FIGS. 10 through 63;

FIG. 84 is a time diagram which illustrates the processing of three successive program order words in the central control of FIG. 9 and FIGS. 10 through 63;

FIG. 85 shows the organization of information in the memory system of FIGS. 1, 2 and 3;

FIGS. 86 through 89 are key figures showing the arrangement of previously described figures as enumerated earlier herein.

GENERAL DESCRIPTION

The organization of a data processing system, in accordance with this invention, is shown in FIGS. 3 through 6. These figures show a Central Control System 301 which comprises a first Central Control CC1 and a functionally equivalent Central Control CC2; a Memory System 371 which comprises the independent memory units PS1 through PSN and CS1 through CSN; and the plurality of transmission paths 6400, 6401, 6402, 6406, 6501. In FIG. 3 there is shown the Routing Register 300 and the Active Unit Flip-Flop 55AU which in combination define the selective association of the Central Control (CC1 or CC2) and the independent transmission paths. Since CC2 is equivalent to CC1, there are a Routing Register 300 and an active unit flip-flop (now shown) in CC2. The active unit flip-flops of the two central control units CC1 and CC2 are always in opposite states. That is, if the Active Unit Flip-Flip 55AU in CC1 is in the "1" state, the active unit flip-flop in CC2 is in the "0" state and vice versa. The central control unit in which the Active Unit Flip-Flop 55AU is in the "1" state is defined as the active central control and the other unit is defined as the standby central control.

FIG. 5 shows the Program Store Memory Unit PS1 as comprising a Route Register 501 and FIG. 6 shows the Call Store Unit CS1 as comprising a Route Register 601. Each corresponding independent memory unit similarly contains a route register. As previously described herein, the route registers in the memory units define the selective association of the independent memory unit to the independent transmission paths which interconnect the central controls and the memory units.

As seen in FIGS. 3 through 6, the Transmission Path 6400, which is employed to transmit commands from the Central Controls CC1 and CC2 to the Memories PS1-PSN, comprises a "0" bus and a "1" bus. Similarly, the Bus 6500, which is employed to transmit responses from the Memories PS1-PSN to the two Central Controls CC1 and CC2, comprises a "0" bus and an identical "1" bus.

The circuits for insuring performance of work functions by the active and standby processors are shown in schematic form in the Central Control CC1 of FIGS. 3 and 4. The Operational Check Circuit 460 of FIG. 4 is representative of a number of operational checking circuits shown in the more detailed representation of FIGS. 10 through 63. As seen in FIG. 4, output signals of the Operational Check Circuit 460 are employed to enable the Remedial Circuits 462 of the central control in which the operational checking circuit is located and are transmitted to the other Central Control (CC2) via the Gate 463, which is representative of the number of gates which are employed in transmitting trouble signals between the two central controls. As seen in FIG. 4, there is a TBL Flip-Flop 461 for recording trouble signals transmitted from CC2 to CC1. That is, upon detection of trouble by the Operational Check Circuit 460 of CC2, the trouble signal is transmitted via the Gate 463 to the TBL Flip-Flop 461 of CC1. The "1" output terminal of the TBL Flip-Flop also provides an enabling signal to the Remedial Circuits 462. Thus, upon the occurrence of trouble in one central control, the remedial circuits in that central control are enabled by the corresponding Operational Check Circuit 460 in that central control and the Remedial Circuits 462 of the other central control are enabled by an output signal of the TBL Flip-Flop 461 in that other central control.

FIGS. 3 and 4 show the Match Circuit 360, which is employed to compare data selectively obtained from data sources within the two functionally equivalent Central Controls CC1 and CC2. There are identical Match Circuits 360 in the two central controls. The Match Circuit 360 generates a trouble signal which enables the Remedial Circuits 462 in the event that the data obtained from the two central controls does not agree. The match circuits and the obtaining of data to be compared is described more fully later herein with respect to FIG. 70 and FIGS. 10 through 63.

As discussed earlier herein the central controls, the independent memory units and the independent transmission paths of the data processing system of FIGS. 3 through 6 are selectively associated to form two working data processor combinations, namely, an active combination and a standby combination. FIG. 2 is a generalized block diagram of a program controlled data processor and the associated input-output system. The data processor comprises the Central Control 201, the Memory System 271 and the Interconnecting Transmission Paths 205, 206. The Input-Output System 270 of this generalized block diagram comprises an Input System 272 and an Output System 273. Commands are transmitted from the Central Control 201 to the Input-Output System 270 of this generalized block diagram comprises an Input System 272 and an Output System 273. Commands are transmitted from the Central Control 201 to the Input-Output System via the Paths 204 and 207 and data is returned from the Input-Output System to the Central Control via the Transmission Path 208.

The principal divisions of the telephone switching system which is employed as an illustrative embodiment for the purposes of describing this invention herein is shown in FIG. 1. The Central Processor 100 of FIG. 1 comprises the Central Control 101, the Program Store 102 and the Call Store 103. The Central Control 101 corresponds to the Central Control System 201 of FIG. 2 and to the Central Control System 301 of FIG. 3, and the Program Store 102 and the Call Store 103 correspond to the Memory System 271 of FIG. 2.

The input-output system in the case of the illustrative telephone switching system comprises the Central Pulse Distributor 143, the Master Scanner 144, the TELETYPE 145, the Program Store Card Writer 146, the AMA 147, the various elements of the Switching Network 120, the Junctor Frame 126, including the Junctor Scanner 127, the Signal Distributor 128 and the Cable Receiver 129, and the Trunk Frames 134 and 137, including the associated Trunk Scanner 135 and 139, the Trunk Signal Distributors 136 and 140, and the Cable Receivers 137 and 141. These elements of FIG. 1 correspond to the Input-Output System 270 of the generalized block diagram of FIG. 2.

Communications between major divisions of this system are by way of bus systems and by way of multiple conductor cables which provide discrete communication paths between selected divisions of the system. The buses and cables are detailed later herein.

Communication within a major division of this system, such as a Central Control 101, may be by way of bus systems; however, such internal bus systems comprise a plurality of single rail parallel paths and are not intended to be covered by the following discussion.

A bus system, as defined herein, comprises a plurality of pairs of conductors which may, in many respects, be compared to a tapped delay line. The time delay of a bus system is not necessarily an advantageous aspect of the bus system but, rather, is an inherent characteristic thereof. A bus is a transmission means for transferring information from one or more sources to a plurality of destinations. A bus is transformer coupled to both the information source or sources and to the destination loads. The information sources are connected to the bus conductors in parallel and the loads are coupled to transformers which are serially connected in the bus conductors. Dual winding load transformers are employed and the two windings of the pair of windings are connected in series with the individual conductors of a pair of conductors of a bus. The load is lightly coupled to the bus as are the taps of a delay line and the bus is terminated in its characteristic impedance also in a manner well known in the manufacture of delay lines.

A bus system is connected to a number of equipments which may be physically separated by distances which are large compared to the distances between taps of a normal delay line. Data transmitted over a bus is in pulsed form and in this particular embodiment extremely short pulses in the order of one-half microsecond are transmitted. Information on a bus system is transmitted in parallel, that is, a data word or a command is transmitted in parallel over the plurality of pairs of conductors of the bus and it is important that such parallel data elements arrive at a given load equipment at a common time. Accordingly, the pairs of conductors of a bus system are arranged to follow similar physical paths and their lengths are kept substantially identical.

There are a number of bus systems and these are described with respect to the major divisions of the system along with the general description of those divisions. Although the buses of this illustrative embodiment are shown in the drawing to be a single continuous path from a source to one or more destinations, there are, in fact, many special techniques employed to minimize propagation time from an information source to a destination point and to equalize propagation times between an information source and similar destinations. Such techniques are not discussed herein as they are not essential to an understanding of this invention; however, in a large office the routing of buses and the special techniques which are designed to achieve the above-noted desirable result are relatively important to an optimum system.

A bus system generally comprises two duplicate buses which in the drawing are labeled bus "0" and bus "1 ." In that there are a number of bus systems as will be set forth later herein, there are a number of buses labeled bus "0" and bus "1 ;" however, each bus system is identified in the drawing.

In addition to the bus systems there are a plurality of multiple conductor cables which provide discrete communication paths between selected divisions of the switching system. The conductor pairs of these cables are in many instances transformer coupled both to the information source and the destination load; however, there are also a number of cables wherein D-C connections are made to both the source and the destination load.

While a bus is a unidirectional transmission means, there are specific instances wherein a cable pair comprises a bidirectional transmission means.

The multiple conductor cables generally provide unduplicated paths between the selected divisions of the system while, as previously noted, the buses of a bus system generally provide duplicated paths between selected divisions of the system.

SWITCHING NETWORK (120)

The Switching Network 120 serves to selectively interconnect through metallic paths lines to lines via junctor circuits, lines to trunks, trunks to trunks, lines and trunks to tones, signal transmitters, signal receivers, maintenance circuits, and, in the case of lines, to provide connections to coin supervisory circuits, et cetera. Two-wire paths between the above enumerated equipments are provided through the network of this one specific illustrative embodiment.

The Switching Network 120 only provides communication paths, means for establishing such paths and means for supervising such paths. The Central Processor 100 maintains a record of the busy and idle states of all network links and a record of the makeup of every established or reserved path through the network. These records are maintained in the Call Store 103 of the Central Processor 100. The record relating to the busy-idle states of the network elements is generally referred to as the Network Memory Map. The Central Processor 100 interprets requests for connection between specific pieces of equipment and determines a free path through the network by examining the connection requirements and the above-noted busy-idle states of the possible paths.

The network is divided into two major portions, namely, line link networks which terminate lines and junctors (both wire junctors and junctor circuits) and the trunk link networks which terminate trunks and wire junctors, service circuits such as tone circuits, signal receivers, signal transmitters, et cetera. A line link network comprises four switching stages, the first two stages of which are concentrating stages, while a trunk link network comprises four stages generally without concentration. In this one specific illustrative embodiment there is a single path provided between a line and each of a plurality of line link network junctor terminals. There are four paths through a trunk link network between a trunk terminal and each of a plurality of trunk link network junctor terminals.

Certain junctor terminals of each line link network are connected directly through wire junctors (a pair of wires without other circuit elements) to certain junctor terminals of the trunk link networks; others of the line link network junctor terminals are interconnected either by way of junctor circuits (which provide talking battery and call supervision facilities) or, in very large offices, by way of junctor circuits and additional stages of switching.

Junctor terminals of a trunk link network which are not connected to junctor terminals of a line link network are directly interconnected by wire junctors or, in extremely large offices, by way of wire junctors and additional switching stages.

Control of the network and the control and supervision of the elements connected to the network are distributed through a number of control and supervisory circuits. This disbursement provides an efficient and convenient buffer between the extremely high speed Central Processor 100 and the slower network elements. The principal control and supervisory elements are:

1. The network control circuits which accept commands from the Central Processor 100 and, in response to such commands, selectively establish portions of a selected path through the network or, in response to such commands, execute particular test or maintenance functions.

2. The network scanners which comprise a ferrod scanning matrix to which system elements such as lines, trunks and junctor circuits are connected for purposes of observing the supervisory states of the connected elements; the network scanners, in response to commands from the Central Processor 100, transmit to the Central Processor 100 indications of the supervisory states of a selected group of circuit elements.

3. The network signal distributors which, in response to commands from the Central Processor 100, provide an operate or a release signal on a selected signal distributor output terminal which is termed herein a signal distributor point. A signal of a first polarity is an operate signal and a signal of the opposite polarity is a release signal. Signal distributor output signals are employed to operate or release control relays in junctor circuits, trunk circuits, and service circuits. A magnetically latched wire spring relay is used generally throughout the junctor circuits and trunk circuits for purposes of completing the transmission paths through these elements and for circuit control in general. The magnetically latched relay operates in response to an operate signal (-48v.) from a signal distributor and releases in response to a release signal (+24v.) from a signal distributor. The network signal distributors are relatively slow operating devices in that they comprise pluralities of relays. Signal distributor output signals are pulsed signals and a single signal distributor can be addressed to only one of its output points at any given instant.

Of the three above-noted network control and supervisory elements (there are pluralities of each of these) the network controllers and the signal distributors are relatively slow operating devices and to assure completion of a task, each of these devices is addressed at the maximum repetition rate of once every 25 milliseconds. This period of time is sufficient to assure completion of the work function associated with a network controller or signal distributor command. Therefore, there is no need for the Central Processor 100 to monitor these devices to assure completion of their assigned tasks before transmitting a subsequent command to the same controller. However, to assure continued trouble free operation scan points which reflect the successful completion of a preceding order are examined before sending a new command to the controller. The network scanners, however, are relatively fast operating devices and these may be addressed at a maximum rate of once every 11 microseconds.

SUBSCRIBER CIRCUITS

The subscriber sets such as 160, 161 are standard sets such as are employed with present day telephone switching systems. That is, these are sets which connect to the central office via a two-wire line, respond to normal 20 cycle ringing signals and may be arranged to transmit either dial pulses or TOUCH-TONES or may be arranged for manual origination. Subscriber stations comprising one or more subscriber sets such as 160, 161 all terminate at line terminals of a line link network. A subscriber line may have either TOUCH-TONE sets or dial pulse sets or combinations of TOUCH-TONE and dial pulse sets. Information concerning the type of call signaling apparatus associated with a subscriber's line is included in the class of service mark which is maintained normally in the Program Store 102; however, after a recent change this information is found in whole or part in the Call Store 103.

Supervision of a subscriber's line is by way of the line scanners which are located in the vicinity of a line link network. Such scanners, however, are generally employed only to detect requests for service. After a request for service has been served and a subscriber's line has been connected through the network to a trunk or to a service circuit such as a subscriber's dial pulse receiver, subscriber's TOUCH-TONE receiver, a tone source, et cetera, or to another subscriber via a junctor circuit, the scanning element associated with a subscriber's line is disconnected and subsequent supervision for answer and disconnect is transferred either to the trunk, the service circuit, or the junctor circuit. The subscriber's line scanning element is reconnected only after the subscriber's line has been released from the prior connection.

Service circuits such as subscriber call signaling receivers and subscriber information tone sources such as busy tone, ringing tone, ringing induction tone, recorded announcements, vacant level tone, et cetera, are terminated at trunk terminals of the trunk link network. Connections between a subscriber's station and a service circuit such as a dial pulse receiver or a TOUCH-TONE receiver and connections between a subscriber's set and a tone source include the four stages of a line link network and the four stages of a trunk link network.

Communication with a distant office or an operator is by way of two-way trunks, outgoing trunks, incoming trunks, operator trunks, et cetera, which are located in the Trunk Frames 134, 138 and which all terminate at trunk terminals of a trunk link network. In the case of a call between a subscriber's station and a trunk or service circuit, talking battery to the subscriber is provided through the trunk or service circuit and supervision for disconnect is accomplished by scanning the scanning elements of the connected trunk or service circuit.

CENTRAL PULSE DISTRIBUTOR (143)

The Central Pulse Distributor 143 is a high speed electronic translator which provides two classes of output signals in response to commands from the Central Processor 100. The two classes of output signals are termed unipolar signals and bipolar signals and are respectively associated with central pulse distributor output terminals designated CPD unipolar points and CPD bipolar points. Both classes of signals comprise pulses transmitted from the CPD output points to the using devices via individual transmission pairs which are transformer coupled both to the CPD output points and to the load devices.

Central pulse distributors for purposes of reliability are employed in pairs and corresponding bipolar output points of the two central pulse distributors of a pair are employed to address the same circuit element. Similarly, unipolar points are associated in pairs to accomplish related system functions.

The address coding associated with each central pulse distributor is sufficient to define 1,024 CPD points. Of these 1,024 points, 512 are assigned to unipolar points while the other 512 are assigned to 256 pairs of bipolar points.

The most common use of the unipolar signals is to momentarily enable a particular piece of equipment such as a Network Controller 122, a Network Scanner 123, et cetera. The enablement signals comprise relatively important information; therefore, in response to an enablement signal the enabled circuit, shortly after the receipt thereof, transmits a verify signal back to the Central Pulse Distributor 143 over the same pair that was used to transmit the enable signal. The verify signal is received at the Central Pulse Distributor 143 and is translated to the same form as the address portion of the command which was transmitted from the Central Control 101 to the Central Pulse Distributor 143. The translated verify signal is transmitted to the Central Control 101 where it is compared against the address which was transmitted. A match assures enablement of the correct unit of equipment. Not all unipolar output signals represent information which is as important as the enable signals; therefore, certain unipolar signals are not verified.

Both unipolar output signals and bipolar output signals comprise pulses and, as in the case of the signal distributors, only one CPD output point, either unipolar or bipolar, can be enabled at any given instant. Unipolar output signals while generally employed to provide transient gating signals to enable the receiving circuit are also used to set and reset flip-flops in particular instances. Bipolar output signals are employed to both selectively set and reset flip-flops at the receiving circuits. A bipolar signal is accompanied by a "WRMI" security signal when employed to control certain critical circuits. A signal of the first polarity serves to set a flip-flop and a signal of the other polarity serves to reset a flip-flop. The system generally has means for verifying the setting or resetting of a flip-flop in response to CPD bipolar signals; therefore, bipolar signals are not directly verified in the manner employed in the case of unipolar signals.

The Central Pulse Distributor 143 is an electronic device; therefore, its output signals are employed to control other relatively high speed circuits. For example, central pulse distributor output signals are employed to control the sending of both multifrequency signals and dial pulses from a switching center to a distant office via a trunk circuit and central pulse distributor output points are also employed to set or reset control flip-flops in a variety of system equipments. Generally these control flip-flops must be set or reset at speeds which approach a basic system instruction cycle; therefore, the slow speed signal distributor output signals are not adequate.

Commands are transmitted from the Central Control 101 to a CPD in the form of half microsecond pulses. The information required to control a CPD is transmitted in three successive waves which are each separated by 1.25 microseconds. The bus choice information which indicates that the CPD's are to accept information from either the "0" or the "1" bus of the Address Bus System 6403 [FIG. 64] is first transmitted in the first wave to all CPD's via the CPD Bus Choice Bus 6405 [FIG. 64]. The CPD Bus Choice Bus 6405 comprises two pairs labeled bus "0" and bus "1 ." The bus choice information is followed 1.25 microseconds later by address information on one of the buses "0" or "1" of the CPD Address Bus System 6403. Each bus of the CPD bus system comprises 34 parallel pairs. CPD address information is transmitted from the Central Control 101 to a CPD in the form of 1-out-of-8, 1-out-of-8, 1-out-of-16 code which accounts for 32 of the 34 pairs of each of the CPD address buses and, in addition, each bus includes a test conductor and a reset conductor.

The particular CPD of the plurality of CPD's which is to respond to a command is indicated by means of a CPD execute signal on one of the pairs of the CPD Execute Cable 6404. The pairs of the Execute Cable 6404 are discrete to individual central pulse distributors and the signal on the CPD execute pair follows the CPD address information by 1.25 microseconds.

The Central Control 101 verifies proper receipt of the address information and execution of the command by means of central pulse distributor verify signals which are transmitted from a central pulse distributor to the Central Control 101 by way of one of the CPD verify buses "0" or "1" of the Verify Bus System 6704. Only unipolar signals are verified; therefore, it is possible to transmit the verify information from a central pulse distributor to the Central Control 101 in a 1-out-of-8, 1-out-of-8, 1-out-of-8 code. The remaining eight bits of the 1-out-of-16 portion of the address are employed only in the generation of bipolar CPD output signals.

A central pulse distributor input synchronizing signal is transmitted from the central control to all CPD's at the same time that the CPD execute signal is transmitted. The CPD input synchronizing signal is transmitted over the CPD Input Sync Bus System 6702 which comprises two cable pairs which are designated the "0" and the "1" bus. The CPD input synchronizing signal is transmitted over the "0" and "1" bus on a mutually exclusive basis; therefore, there is no effort made to selectively gate the synchronizing signal from the driven bus to the central pulse distributor which has received the execute signal.

In addition to verifying the address information which was transmitted from a Central Control 101 to a central pulse distributor, central control also verifies the enablement of the appropriate central pulse distributor. This is accomplished by means of a CPD execute response signal which is transmitted from a central pulse distributor to the Central Control 101 by a discrete pair of the CPD Execute Response Cable 6502. The CPD response pair is merely an extension of the CPD execute pair. Therefore, an execute signal is transmitted from a central control, passes through a serially connected transformer in a CPD and is returned to the Central Control 101 where it is also picked off by a serially connected transformer which is terminated in the characteristic impedance of the transmission pair.

Further, the central pulse distributor performs certain internal functions which check the operation of particular circuit elements within the pulse distributor and also check the validity of the address coding. These checks serve to verify the operation of the Address Pulse Stretchers and to assure that one, and only one, of each of the elements of the address are enabled. That is, a valid address should comprise one, and only one, signal out of each of the groups A0 through A7, B0 through B7, and C0 through C15. In the event that either of these checks fails, responses to the Central Control 101 via the Central Pulse Distributor Maintenance Response Bus System 6904 are omitted thus indicating to the Central Control 101 a possible trouble within the central pulse distributor.

In addition to transmitting to the Central Control 101 a twenty-four bit verify signal which designates the enabled CPD output point, the central pulse distributor also transmits to the central control an All Seems Well signal, individual signals which indicate the validity of the A, B, and C portions of the address code, and a maintenance signal which indicates that the current employed to drive the output point transformers is within prescribed limits.

The All Seems Well signal is returned to the central control to indicate proper functioning of the Central Pulse Distributor.

A test may be performed on the operation of the CPD without concern for the content of the C address portion of the command and without enabling either a bipolar or a unipolar point. In a test command the bus choice signal, the A and B portions of the address code, and the execute signal are all transmitted to the central pulse distributor and, in addition, the test conductor with is one of the conductors of the Network Command Bus System 6406 is enabled.

For purposes of maintenance one central pulse distributor may be taken out of or returned to service by means of a control signal from another central pulse distributor. A flip-flop and its associated power relay are under control of flip-flop setting and resetting signals from the companion central pulse distributor. When the flip-flop is in its reset state, the relay is operated and power is applied to the power distribution circuit of the Central Pulse Distributor. When the flip-flop is reset by means of a signal from the companion central pulse distributor, the power relay releases and removes power from the central pulse distributor. The state of the power relay, i.e., operated or released, is transmitted to a ferrod in the master scanner.

MASTER SCANNER (144)

The Master Scanner System 144 comprises a ferrod matrix for terminating circuits to be supervised and means for selectively transmitting to Central Control 101 the supervisory states of a selected group of supervised circuits in response to a command from the Central Processor 100. The scanning element employed is the ferrod device. A ferrod comprises an apertured stick of ferromagnetic material having control, interrogate, and readout windings. The control windings are placed in series with electrical connections which indicate the supervisory state of the supervised circuit. For example, where a ferrod is employed to supervise a subscriber's line, the ferrod is placed in series with the line conductors and the subscriber's subset. When the subscriber's subset is in the on-hook state there is no current flowing in the ferrod control winding, while when the subscriber is in the off-hook state current does flow in the ferrod control winding. The interrogate and readout windings merely comprise individual conductors which thread through the two apertures of the ferrod, that is, both the interrogate conductor and the readout conductor are threaded through both apertures of the ferrod. An interrogate signal comprises a bipolar pulse which when applied to the interrogate conductor causes an output signal in the readout conductor of every ferrod which is supervising a circuit which is in the on-hook state. If the ferrod is supervising a circuit in the off-hook state, a readout pulse is not generated due to saturation of the ferrod.

The Master Scanner System 144 comprises one or more scanners each capable of supervising 512 circuits. The scanners of the Master Scanner 144 are not duplicated; however, there is a complete duplication of access circuitry within a scanner to provide system reliability. The Master Scanner 144 is generally like the Network Scanners (123, 127, 135, 139) which are distributed through the network frames; however, the Master Scanner 144 is employed to supervise certain circuit elements which reflect the operating state of the system and, therefore, the supervisory states of these elements are helpful in system maintenance and trouble diagnosis. For example, scan points of the Master Scanner 144 are employed to monitor the voltage levels of critical voltage supplies, and the states of control relays and logic packages such as flip-flops to assure proper operation thereof. In addition, the Master Scanner 144 is employed to monitor a few circuits which terminate on the Switching Network 120 and which for efficiency of grouping and more conveniently examined by way of the Master Scanner 144.

TELETYPE UNIT (145)

The Teletype Unit 145 provides means for communicating information from maintenance personnel to the switching system and for transmitting information from the switching system to maintenance personnel.

By means of the Teletype Unit 145 maintenance and operating personnel may request limited specific system actions. Included in the system actions is the ability to enter in the Call Store 103 recent change translation information. That is, in the course of daily routine business there are often requirements for changes in directory number to line equipment number translations. For example, when a line is disconnected for any reason, a new line is added, or changes are made in the service afforded a line, a recent change entry is required. Recent change information is held in a Call Store 103 until such time as the coding of a Program Store 102 is changed to reflect the recent change information.

In the course of routine operations the system may encounter abnormal or trouble operating conditions and information relating to such abnormal or trouble conditions is printed out on the teletype for the information of the maintenance personnel.

PROGRAM STORE CARD WRITER (146)

The Program Store Card Writer 146 provides means for coding the information cards of the Program Store 102. Information to be placed on the magnet cards is obtained either from a magnetic tape source or from the Central Processor 100. The card writer serves to magnetize the card magnets wherever a "0" is to be inserted in the memory and to demagnetize the card magnets wherever a "1" is to be inserted in the memory.

Message Accounting Tape Unit (147)

The automatic Message Accounting Tape Unit 147 is utilized by the system to store telephone charging information. This information is stored in a single complete entry on magnetic tape. The tapes or the information on the tapes are subsequently transmitted to a data processing accounting center where the charge information is employed in computing a subscriber's cumulative charges.

The switching system collects certain data pertaining to both message rate and toll calls and this data is assembled in a Call Store 103. After all of the information which the data processing accounting center will require to compute a subscriber's charge has been collected, the information is transferred from the Call Store 103 to the tape unit.

The tape units are employed in pairs to assure system reliability.

Central Processor

As seen in FIG. 1, the Central Processor 100 comprises a Central Control 101, the Program Store 102 and the Call Store 103. The Central Processor is also shown in FIG. 9 and in that figure there is a schematic diagram of the data processing portion of the Central Control 101. FIG. 9 is directed to an unduplicated central processor and there is no attempt therein to show the maintenance facilities and the facilities for interconnecting two central controls in accordance with this invention. A relatively detailed discussion of the operational checking facilities and the facilities for maintaining the two central controls "in step" are described herein with respect to FIGS. 10 through 63. The Program Store 102 of FIGS. 1 and 9 is shown in block diagram form in FIG. 7 and the Call Store 103 of FIGS. 1 and 9 is shown in block diagram form in FIG. 8.

CENTRAL CONTROL (101)

The Central Control 101, which is shown in simplified block diagram form in FIG. 9 and in detail in FIGS. 10 through 63, is the system data processing unit. For the purpose of discussion the Central Control 101 may be divided into three basic parts:

1. Basic data processing facilities;

2. Facilities for communicating with central control input sources and output devices; and

3. Maintenance facilities.

The Central control performs system data processing functions in accordance with program orders which are stored principally in the Program Store 102. In a few specialized instances program orders are found in the Call Store 103. The program orders are arranged within the memories in ordered sequences. The program orders fall into two general classifications, namely, decision orders and nondecision orders.

Decision orders are generally employed to institute desired actions in response to changing conditions either with regard to lines or trunks served by the switching system or changing conditions with respect to the maintenance of the system.

Decision orders dictate that a decision shall be made in accordance with certain observed conditions and the result of the decision causes central control to advance to the next order of the current sequence of order words or to transfer to an order in another sequence of order words. The decision to transfer to another sequence may be coupled with a further determination that the transfer shall be made to a particular one of a plurality of sequences. Decision orders are also termed conditional transfer orders.

Nondecision orders are employed to communicate with units external to Central Control 101 and to both move data from one location to another and to logically process the data. For example, data may be merged with other data by the logical functions of AND, OR, EXCLUSIVE-OR, product mask, et cetera, and also data may be complemented, shifted, and rotated.

Nondecision orders perform some data processing and/or communicating actions, and upon completion of such actions most nondecision orders cause the Central Control 101 to execute the next order in the sequence. A few nondecision orders are termed unconditional transfer orders and these dictate that a transfer shall be made from the current sequence of program orders to another sequence of order words without benefit of a decision.

The sequences of order words which are stored principally in the program store comprise ordered lists of both decision and nondecision orders which are intended to be executed serially in time. The processing of data within the central control is on a purely logical basis; however, ancillary to the logical operations, the Central Control 101 is arranged to perform certain minor arithmetic functions. The arithmetic functions are generally not concerned with the processing of data but, rather, are primarily employed in the process of fetching new data from the memories such as from the Program Store 102, the Call Store 103, or particular flip-flop registers within the Central Control 101.

The individual order words are designed to complement the physical characteristics of the central processor and to complement each other. Thus, through careful design of the program order word structure it is possible to maximize the data process capacity of the central processor.

The Central Control 101, in response to the order word sequences, processes data and generates and transmits signals for the control of other system units. The control signals which are called commands are selectively transmitted to the Program Store 102, the Call Store 103, the Central Pulse Distributor 143, the Master Scanner 144, the network units such as the Network Scanners 123, 127, 135, 139, Network Controllers 122, 131, Network Signal Distributors 128, 136, 140, and the miscellaneous units such as the Teletype Unit 145, the Program Store Card Writer 146, and the AMA Unit 147.

The Central Control 101 [FIG. 9] is, as its name implies, a centralized unit for controlling all of the other units of the system. A Central Control 101 principally comprises:

A. A plurality of multistage flip-flop registers;

B. A plurality of decoding circuits;

C. A plurality of private bus systems for communicating between various elements of the central control;

D. A plurality of receiving circuits for accepting input information from a plurality of sources;

E. A plurality of transmitting circuits for transmitting commands and other control signals;

F. A plurality of sequence circuits;

G. Clock sources; and

H. A plurality of gating circuits for combining timing pulses with D-C conditions derived within the system.

The Central Control 101 is a synchronous system in the sense that the functions within the Central Control 101 are under the control of a multiphase Microsecond Clock 6100 which provides timing signals for performing all of the logical functions within the system. The timing signals which are derived from the Microsecond Clock 6100 are combined with D-C signals from a number of sources in the Order Combining Gate Circuit 3901. The details of the Order Combining Gate Circuit 3901 are not shown in the drawing as the mass of this detail would merely tend to obscure the inventive concepts of this system.

Sequence of Central Control Operations

All of the system functions are accomplished by execution of the sequences of orders which are obtained from the Program Store 102 or the Call Store 103. Each order of a sequence directs Central Control 101 to perform one operational step. An operational step may include several logical operations as set forth above, a decision where specified, and the generation and transmission of commands to other system units.

The Central Control 101 at the times specified by phases of the Microsecond Clock 6100 [FIG. 61] performs the operational step actions specified by an order. Some of these operational step actions occur simultaneously within Central Control 101, while others are performed in sequence. The basic machine cycle, which in this one illustrative embodiment is 5.5 microseconds, is divided into three major phases of approximately equal duration. For purposes of controlling sequential actions within a basic phase of the machine cycle each phase is further divided into 1/2-microsecond periods which are initiated at 1/4-microsecond intervals.

The basic machine cycle for purposes of designating time is divided into 1/4-microsecond intervals, and the beginning instants of these intervals are labeled T0 through T22. The major phases are labeled phase 1, phase 2, and phase 3. These phases occur in a 5.5-microsecond machine cycle as follows:

A. Phase 1-- T0 to T8,

B. Phase 2-- T10 to T16,

C. Phase 3-- T16 to T22.

For convenience in both the following description and in the drawing, periods of time are designated bTe where b is the number assigned the instant at which a period of time begins and e the number assigned the instant at which a period of time is ended. For example, the statement 10T16 defines phase 2 which begins at time 10 and ends at time 16. The division of time is shown in FIG. 83.

As seen in FIG. 61, each central control has a 2 magacycle Clock Oscillator 6106. The Clock Oscillator 6106 of the active central control serves to drive the Microsecond Clock 6100 in both the active central control and the standby central control. The Oscillator 6106 of the active central control is connected to the input of the Microsecond Clock 6100 of the active central control via AND gate 6108 and OR gate 6110. AND gate 6108 is enabled by a signal on order cable conductor 61AU which indicates that the active unit flip-flop 55AU is in the "1" state. The output of the Oscillator 6106 is transmitted to the other central control via conductor 6111, amplifier 6112, transformer 6113, and an interconnecting transmission pair. In the other central control the oscillator output signal is received via a transformer such as 6114, an amplifier such as 6115, conductor 6116 and in the standby central control this signal is transmitted to the Microsecond Clock 6100 via a path which includes AND gate 6109 and OR gate 6110. AND gate 6109 is enabled by a signal on order cable conductor 61AU. The Microsecond Clock 6100 in the active central control generates a clock phasing pulse labeled Clock Phase-I which is transmitted from the active central control to the standby central control via conductor 6117, amplifier 6118, transformer 6119 and an interconnecting transmission pair. In the standby central control the phasing signal is received over transformer 6120, amplifier 6121 and is transmitted to the microsecond clock reset terminal via AND gate 6122. AND gate 6122 is enabled by a signal on order cable conductor 61AU. The clock phasing signal serves to keep the two microsecond clocks in correspondence.

The Microsecond Clock 6100 generates output signals as shown in FIG. 83. These output signals are transmitted to the Order Combining Gate 3901 [FIG. 39]. Further, the Microsecond Clock 6100 provides input signals to the Millisecond Clock 6101 via conductor 6105. These input signals occur once every 5.5 microseconds.

The Millisecond Clock 6101 comprises 12 binary counter stages along with counter recycling circuitry. The 12 stages are arranged as a series of recycling counters, the output of each counter providing an input to the next succeeding counter. Stages one through four provide a count of 13 and thus, with 5.5-microsecond input signals, provide an output signal once every 71.5 microseconds. Stages five through seven provide a count of 7 and thus, with an input once every 71.5 microseconds, provide an output once every 500.5 microseconds (once per half millisecond). Stage 8 provides a count of 2 and thus, with a half millisecond input interval, provides an output pulse once every millisecond. Stages 9, 10, and 11 provide a count of 5 and, with input pulses once per millisecond, provide output pulses once every 5 milliseconds. Stage 12 provides a count of 2 and thus, with input pulses once every 5 milliseconds, provides an output pulse once every 10 milliseconds.

The output conductors of the "1" side of each counter stage of the Millisecond Clock 6101 are connected to the Order Combining Gate Circuit 3901 and these conductors appear in FIG. 42 as inputs to symbolic AND gate 4200. Thus, the states of these 12 counters may be gated to the buffer register input bus system via AND gate 4200 when enabled by a signal on order cable conductor 13R-BR.

As explained later herein, the 704 microsecond output conductor of the Millisecond Clock 6101 is employed to count up to 128 machine cycles.

In order to maximize the data processing capacity of Central Control 101 three cycle overlap operation is employed. In this mode of operation central control simultaneously performs:

A. The operational step for one instruction;

B. Receives from the Program Store 102 the order for the next operational step; and

C. Sends an address to the Program Store 102 for the next succeeding order.

This mode of operation is illustrated in FIG. 84. Three cycle overlap operation is made possible by the provision of both a Buffer Order Word Register 2410, an Order Word Register 3403 and their respective decoders, the Buffer Order Word Decoder 3902 and the Order Word Decoder 3904. A Mixed Decoder 3903 resolves conflicts between the program words in the Order Word Register 3403 and the Buffer Order Word Register 2410. The Auxiliary Buffer Order Word Register 1901 absorbs differences in time of program store response.

The initial gating action signals for the order X (herein designated the indexing cycle) are derived in the Buffer Order Word Decoder 3902 in response to the appearance of order X in the Buffer Order Word Register 2410. The order X is gated to the Order Word Register 3403 (while still being retained in the Buffer Order Word Register 2410 for the indexing cycle) during phase 3 of cycle 2; upon reaching the Order Word REgister 3403 the final gating actions (herein indicated as the execution cycle) for the order X are controlled via Order Word Decoder 3904.

The indexing cycle and the execution cycle are each less than a 5.5-microsecond machine cycle in duration. In the executing of the operational steps of a sequence of orders like those shown in FIG. 84 each order remains in the Order Word Register 3403 and the Buffer Order Word Register 2410 each for one 5.5-microsecond cycle. The Buffer Order Word Decoder 3902 and the Order Word Decoder 3904 are D-C combinational circuits; the D-C output signals of the decoders are combined with selected microsecond clock pulses (among those indicated in FIG. 83) in the Order Combining Gate Circuit 3901. This Order Combining Gate Circuit 3901 thus generates the proper sequences of gating signals to carry out the indexing cycle and the execution cycle of each of the sequence of orders in turn as they appear first in the Buffer Order Word Register 2410 and then in the Order Word Register 3403.

The performance of the operational steps for certain orders requires more time than one operational step period, i.e., more than 5.5 microseconds. This requirement for additional time may be specified directly by the order; however, in other instances this requirement for additional time is imposed by indicated trouble conditions which occur during the execution of an order. Where an order specifies that the execution thereof will require more than one operational step period, the additional processing time for that order may be gained by:

1. Performing the additional data processing during and immediately following the indexing cycle of the order and before the execution cycle of the order; or

2. Performing the additional data processing during and immediately after the normal execution cycle of the order.

The performance of these additional work functions is accomplished by way of a plurality of sequence circuits within Central Control 101. These sequence circuits are hardware configurations which are activated by associated program orders or trouble indications and which serve to extend the time in the operational step beyond the normal operational step period illustrated in FIG. 84. The period of time by which the normal operational step period is extended varies depending upon the amount of additional time required and is not necessarily an integral number of machine cycles. However, the sequences which cause delays in the execution of other orders always cause delays which are an integral number of machine cycles.

The sequence circuits share control of data processing within the Central Control 101 with the decoders, i.e., the Buffer Order Word Decoder 3902 (BOWD), the Order Word Decoder 3904 (OWD), and the Mixed Decoder 3903 (MXD). In the case of orders in which the additional work functions are performed before the beginning of the execution cycle, the sequence circuit or, as more commonly referred to, the "sequencer" controls the Central Control 101 to the exclusion of decoders BOWD, OWD, and MXD. However, in the case of orders in which the additional work functions are performed during and immediately after the execution cycle of the order, the sequencer and the decoders jointly and simultaneously share control of the Central Control 101. In this latter case there are a number of limitations placed on the orders which follow an order which requires the enablement of a sequencer. Such limitations assure that the central control elements which are under the control of the sequencer are not simultaneously under control of the program order words.

Each sequence circuit contains a counter circuit, the states of which define the gating actions to be performed by the sequence circuit. The activation of a sequence circuit consists of starting its counter. The output signals of the counter stages are combined with other information signals appearing within Central Control 101 and with selected clock pulses in the Order Combining Gate Circuit 3901 to generate gating signals. These signals carry out the required sequence circuit gating actions and cause the counter circuit to advance through its sequence of internal states.

Sequence circuits which extend the period of an operational step by seizing control of a Central Control 101 to the exclusion of the decoders BOWD, OWD, and MXD are arranged to transmit the address of the next succeeding program order word concurrently with the completion of the sequencer gating actions. Thus, although the execution of the order immediately succeeding an order which enabled the sequencer of the above character is delayed, the degree of overlap shown in FIG. 84 is maintained.

Sequence circuits which do not exclude the decoders BOWD, OWD, and MXD provide additional overlap beyond that shown in FIG. 84. That is, the transmission of the address of and acceptance of the order immediately succeeding an order, which enabled a sequencer, are not delayed. The additional gating actions required by such sequence circuits are carried out not only concurrently with the indexing cycle of the immediately succeeding order, but also concurrently with at least a portion of the execution cycle of the immediately succeeding order.

A few examples will serve to illustrate the utility of the sequence circuits. A program order which is employed to read data from the Program Store 102 requires an additional two 5.5-microsecond machine cycle periods for completion. This type of order gains the additional two cycles by delaying the acceptance of the immediately succeeding order and performs the additional work operations after termination of the indexing cycle of the current order and before the execution cycle of the current order.

When errors occur in the reading of words from the Program Store 102, the Program Store Correct-Reread Sequencer 5301 is enabled to effect a correction or a rereading of the Program Store 102 at the previously addressed location. This sequence circuit is representative of the type of sequence circuit which is enabled by a trouble indication and which seizes control of the Central Control 101 to the exclusion of the decoders.

The Command Order Sequencer 4902 which serves to transmit network commands to the Switching Network 120 and to the miscellaneous network units, i.e., Master Scanner 144, AMA Tape Unit 147, and Card Writer 146, is representative of the sequence circuits which, when enabled, increase the degree of overlap beyond that shown in FIG. 84. That is, the transmission of network commands extends into the execution cycle of the order following the network command order.

In the processing of certain multicycle orders a plurality of sequence circuits may be activated so that the processing of the multicycle order may include both kinds of gating actions; first additional gating cycles may be inserted between the indexing cycle and the execution cycle of the order, and then a second sequence circuit may be activated to carry out gating actions which extend the degree of overlap to an additional cycle or cycles.

The drawing employed herein in many instances shows single lines as the connections between blocks; it is to be understood that single lines are merely symbolic and may indicate numerous connections such as a cable or a bus as previously defined herein.

In certain instances, the binary states of a circuit are provided on a pair of output conductors which are alternatively energized. Such an arrangement is called a two-rail circuit and binary devices which provide individual "0" and "1" state output signals are called two-rail logic elements herein. In other instances, only one of the two states of a binary device is employed as an output signal, and such arrangements are called single rail circuits. Throughout the drawing gates, symbols of amplifiers, et cetera, are understood to be in many cases a plurality of gates or amplifiers comprising a number of channels equal to the number of individual signals to be transmitted therethrough. For example, in FIG. 11 the AND gate 1104 when enabled, transmits the ten information bits A0-A5, S1, S2, W, and CM from the output of the Cable Receiver 1102 to the input of the symbolic plural OR gate 1109. Accordingly, Cable Receiver 1102 comprises ten transformers and ten amplifiers; AND gate 1104 comprises ten AND gates, and OR gate 1109 comprises ten OR gates. Further, in the drawing there are two types of AND gates symbolized, the first being a conventional AND gate such as AND gate 3006 shown in FIG. 30. This symbol represents a plurality of AND gates equal in number to the number of information paths included in a cable. If the cable conveys information on a single rail basis, then there is one AND gate per information bit; however, if the cable conveys information on a two-rail basis, then the number of AND gates represented by the symbol equals two times the number of information bits.

The second type of AND gate which converts information from one-rail to two-rail is symbolized in FIG. 30 wherein gate 3008 is shown as a conventional AND gate with a bar included inside the symbol. This type of AND gate is shown in schematic detail in FIG. 30A. The data on cable 30A04 is on a single rail basis, that is, the cable 30A04 comprises one conductor for each of the information bits included in the data and these conductors are energized when a "1" is transmitted and are deenergized or held near ground when a "0" is transmitted. The single rail data on cable 30A04 is inverted on a bit-by-bit basis by the symbolic inverter 30A03, the output conductors of which comprise the input cable to conventional AND gate 30A02. The input signals to the AND gate 30A02 are the complement of the input signals to the AND gate 30A01. The AND gates 30A01 and 30A02 may be enabled by a signal on conductor 30A05 and the output terminals of these gates represent the "1" and "0" rails which are employed to set and reset registers. The symbol for this type of converting AND gate is shown in FIG. 30A and is labeled 30A06.

Program Store (102) [FIGS. 7 and 72 through 82]

The Program Store of the Central Processor comprises a plurality of independent memory units. FIG. 7 is a block diagram of one such independent memory unit.

The Program Store of FIG. 7 is passive in the absence of commands from the Central Control.

In the illustrative embodiment, the Program Store is a permanent magnet-magnetic wire memory (Twistor) which affords nondestructive readout of the information stored therein. The Program Store, being semipermanent in nature, is employed to store certain system data which is changed only at relatively long intervals and the system programs. Information is written into the Program Store by means of the Program Store Card Writer 146 (FIG. 1) under commands from the Central Control 101.

Commands for controlling the Program Store are transmitted from the Central Control to the Program Store via the Bus System 6400, which comprises a "0" bus and an identical "1" bus. As seen in FIG. 7, information can be selectively gated from the "0" bus or the "1" bus to the Control 701 via the Input Path Selection Gates 702 and 703, respectively. The Gates 702 and 703 are selectively enabled in accordance with the contents of the Route Register 501. The Control 701 responds to commands from the Central Control to: (a) enable the Timing Circuit 7800, 7801 to initiate a memory timing cycle, (b) generate control signals for the Access Circuit 7401, 7402, and (c) generate signals for the Operational Check Circuit 7728. Output signals of the Timing Circuit 7800, 7801 serve to advance the Control 701 through a fixed sequence and to provide gating signals for the Access Circuits 7401, 7402 and for the Readout Circuit 7703 through 7706. The Memory 704 of the Program Store of FIG. 7 comprises a plurality of memory (Twistor) modules not to exceed 16 in number. Each memory module comprises 8,192 forty-four bit words. The memory words are associated in pairs at 4096 discrete word pair addresses. The readout circuits 7703 through 7706 have provisions for selecting a chosen 44-bit word of the pair of words which are obtained by addressing one of these discrete word pair addresses. The Operational Check Circuit 7728 monitors the internal operation of the Program Store of FIG. 7 and generates a check signal (termed an all seems well ASW signal), which is returned to the Central Control along with the information which is read from the memory module. Output signals of the Timing Circuit 7800, 7801, along with signals generated within the Control 701, provide gating signals for selectively transmitting information read from the Memory 704 to one of the two identical buses of the Program Store Response Bus System 6500. That is, the Output Path Selection Gates 705 and 706 are selectively enabled to gate the information read from the Memory 704 to the "0" bus and to the "1" bus, respectively.

As seen in FIG. 7, the Route Register 501 is selectively controlled by signals received over the Cables 6700, 6701. The Cables 6700 and 6701 are output cables of the Central Pulse Distributor 143. The Central Pulse Distributor 143 selectively generates output signals on conductors of these cables in accordance with commands received from the Central Control 101.

The Central Control 101 manipulates the information in the Route Register 501 to achieve a desired association of an independent Program Store memory unit and the buses of the Command Bus System 6400 and of the Response Bus System 6500.

In summary, an independent Program Store memory unit, such as is shown in FIG. 7, accepts command signals from the Central Control over a selected one of the buses "0" or "1" of the Program Store Command Bus System 6400 and transmits responses to the Central Control via a selected one of the buses "0" or "1" of the Response Bus System 6500. The Program Store of FIG. 7, through the Operational Check Circuit 7728, monitors the internal operation of that program store memory unit and generates check signals for transmission to the Central Control along with information read from the Memory 704. The internal operation of a program store unit is in accordance with timing signals generated by the Timing Circuit 7800, 7801 and information is transmitted to the Central Control at times determined by such internally generated timing signals. The timing circuit is arranged to initiate a timing sequence when a command is received from the Central Control.

As seen in FIG. 5, the Memory System 371 comprises a plurality of independent Program Stores PS1 through PSN and a plurality of independent Call Stores CS1 through CSN. The organization of the long term data and program information into one type of memory unit and the rapidly changing data into other types of memory units is not essential to the present invention, but rather is a characteristic of the illustrative data processing system which is described herein. That is, the Memory System 371 could comprise a plurality of independent read and write memories in which all of the system information was stored.

The number of Program Stores PS1 through PSN is determined principally by the size of the switching system, i.e., the number of lines and trunks served by the system and the variety of services rendered the lines and trunks. However, at least two program stores are always used to achieve system dependability through the teachings of this invention.

The information capacity of a program store is divided into a left half and a right half [see FIG. 85]. Where the number of program stores employed exceeds two, the information in the right half of the first store is duplicated in the left half of the second store; the information in the right half of the second store is duplicated in the left half of the succeeding store; and the information in the right half of the last store is duplicated in the left half of the first store. This arrangement permits full duplication of information with either an even or an odd number of stores.

FIGS. 64 through 69 show the major paths of communication between the major divisions of this system. FIGS. 64, 65 and 66 are devoted to a showing of the various address and control buses and the response buses of the various units; FIGS. 67 and 68 are directed to the distribution of Central Pulse Distributor 143 output signals and the timing of such signals under the control of Central Control 101 by way of CPD input sync signals; and FIG. 69 is devoted to a showing of the principal maintenance and diagnostic communication paths.

As seen in FIGS. 64 and 65, the Central Control System 101 comprising CC1 and CC2 is connected to the Program Store System 102 comprising PS1 through PSN via the Program Store Address Bus System 6400. The Address Bus System 6400 comprises two buses designated "0" and "1" and each bus comprises 25 conductor pairs. Both CC1 and CC2 may selectively transmit to the Program Store System 102 via either bus "0" or bus "1" of the Program Store Address Bus System 6400. The Program Store Address Bus System 6400 is coupled by way of serially connected transformers to receiving circuitry in each of the program stores PS1 through PSN OF THE Program Store System 102.

As seen in FIGS. 64 and 65 the Program Store Response Bus System 6500 comprises two buses termed "0" and "1" and each bus comprises 46 conductor pairs. The buses are driven in parallel by cable drivers in each of the plurality of program stores and these buses are coupled by way of serially connected transformers to receiving circuitry in both of the central controls CC1 and CC2. The significance of the information transmitted from the central controls to the Program Stores System 102 via the Program Store Address Bus System 6400 and the significance of the information transmitted from the Program Store System 102 to the central controls by way of the Program Store Response Bus System 6500 is set forth later herein.

A program store may be operated in the following modes:

1. Normal Mode-- In this mode of operation Central Control 101 defines an address location in a particular block of store information and requests that the information found at this address be transmitted to Central Control 101. A block of store information is defined as a duplicated segment of information. In a small office, i.e., one wherein only two stores comprise the Program Store System 102, there will be but two blocks of store information, namely, the first block which is found in the right half of the first store and the left half of the second store, and the second block of information which is found in the right half of the first store and the left half of the second store. As the size of the system is increased and the number of stores comprising the Program Store System 102 is increased, additional blocks of information are added. Each block of duplicated information is assigned a code name in a four-bit code and each name comprises two "1's" and two "0's." Accordingly, two program stores which have duplicate information stored therein will respond to a single code name.

2. H Maintenance Mode-- In this mode of operation Central Control 101 defines an address in a particular block of store information and only the store wherein this information is stored in the H, i.e., left side, will respond.

3. G Maintenance Mode-- In this mode of operation Central Control 101 defines an address in a particular block of store information and only the store wherein this information is stored in the G, i.e., right side, will respond.

4. Read Control Mode-- This is a maintenance mode of operation and in this mode status information in binary form relating to a number of test points, approximately 176 in number, is transmitted from a program store to Central Control 101 via the Program Store Response Bus System 6500. The 176 test points are divided into four basic groups called rows, each row comprising 44 test points.

5. Write Control Mode-- This mode permits Central Control 101, for purposes of trouble diagnosis, to selectively write binary information into various elements of the Program Store System 102 such as the address registers, the routing registers, et cetera. A combination of write control mode orders and read control mode orders permits Central Control 101 to pinpoint trouble in the control circuitry of a program store by performing sequences of logical acts on the store control elements. It is not possible to write into all test points which may be read under the read control mode as there are a large number of test points which merely reflect the state of a circuit within the store and this state cannot be externally altered by a write control mode order.

The Program Stores 102 are passive in the absence of commands from Central Control 101, that is, the Program Stores 102 are dependent upon commands from the Central Control 101.

In the most common mode of central processor operation the stores which contain duplicate information are addressed over separate input buses, that is, the first store which has a block of information in its left half is addressed over, for example, the "0" bus, while the other store which has the duplicate block of information stored in its right half is addressed over the "1" bus. Similarly, the first store transmits its responses over the "0" response bus, while the other store transmits its responses over the "1" response bus. This is but one of a number of possible bus and store configurations and the exact store-bus configuration is determined by the Central Processor 100.

There are seven bistable flip-flops in each store which are provided to control the inputs from the buses and the outputs to the buses. Certain of these flip-flops are set or reset by output signals from the Central Pulse Distributor 143, while others are set or reset by operating the store in the write control mode. A table of these flip-flops, the source of information for setting or resetting the flip-flop and the significance of the flip-flop being set or reset is set forth below. ------------------------------------------------------------ --------------- Routing Flip-flop Setting Source and Significance

Flip-flop Set and reset by Significance ____________________________________________________________ ______________ R0 CPD Set -Receive from bus "0." Send maintenance and control readout on bus "0." Reset -Receive from bus "1." Send maintenance and control readout on bus "1." HS0 Write Control Set -Send normal readouts from H on bus "0." HS1 Write Control Set -Send normal readouts from H on bus "1." GS0 Write Control Set -Send normal readout from G on bus "0." GS1 Write Control Set -Send normal readout from G on bus "1." TBL0 CPD Set -Inhibit operation with bus "0" (both receive and send). TBL1 CPD Set -Inhibit operation with bus "1" (both receive and send). ____________________________________________________________ ______________

These flip-flops are manipulated by the Central Control 101 to obtain desired store-bus configurations not only during times when all stores and all bus systems are operating properly, but also during times when trouble is encountered and either the facilities of a bus or a particular store are not available.

The set and reset signals for the central pulse distributor controlled flip-flops RO, TBL0, and TBL1 are received over the Bipolar Cable 6700. There are bipolar signals other than those set forth above which are applied to the Program Store 102 and the functions of these will be described later herein.

The bipolar signals are brought into the Program Store 102 via individual cable pairs of the Bipolar Cable 6700 and they each terminate in a transformer such as 7501. The transformer 7501 is connected to provide an input signal to a first amplifier such as 7502 for a bipolar signal of a first polarity, i.e., a set signal, and to provide an input signal to another amplifier such as 7503 in response to a bipolar input signal of the opposite polarity for a reset signal. A security signal termed herein a WRMI gating pulse accompanies each bipolar signal. WRMI signals are transmitted from the Central Pulse Distributor 143 to the various locations throughout the system via the WRMI Bus System 6701 which comprises a first cable pair which is labeled bus "0" and a second cable pair which is labeled bus "1."

In the in-step mode of operation of Central Control 101, which is the normal mode in the absence of trouble, the Central Control System 101 will transmit identical address and control information over the two Program Store Address Buses of the Bus System 6400. This identical information on the two buses of 6400 may come from the active central control, or one address and control bus of the Bus System 6400 may be addressed by the active central control while the other address and control bus of the Bus System 6400 may be addressed by the standby central control.

The connection of the address buses to a program store is shown in FIG. 72. In accordance with the symbology used throughout the drawing, the transformer 7200 and the amplifier 7202 are representative of a plurality of transformers and amplifiers, respectively, the number of transformers and amplifiers represented being equal in number to the number of address and control bits of information which are found in the "0" bus of the Address and Control Bus System 6400. The "0" bus, like the "1" bus as shown in FIG. 64, comprises 25 bits as follows:

A. 16 address bits A0-A15;

B. Four code bits K0-K3;

C. Four mode bits CM, HM, GM, CRW; and

D. A single synchronizing bit.

As previously noted, each Twistor module comprises 4,096 discrete information addresses and at each address there is located a pair of 44 bit words. The 4,096 address locations of a Twistor module are arranged in a square array and a word location is thus defined by coincidence of input signals on 1-out-of-64 X axis drive windings and 1-out-of-64 Y axis drive windings. The 16 modules are also arranged in a 4 × 4 square array. Accordingly, an information location within the store may be defined by the coincident enablement of 1-out-of-256 X axis drive windings and 1-out-of-256 Y axis drive windings. Both the X and the Y access circuitry therefore requires an eight bit binary address to define the selected 1-out-of-256 drive windings. A word pair address within the store is thus defined by 16 binary bits. In addition, one binary bit is required to select one word from the pair of words at the selected address location. Accordingly, an address word comprising seventeen binary bits is required to define the store location from which a word is to be read. The seventeen bit word address is derived from the sixteen address bits AO-A15 and the information code bits KO-K3. The address bits AO-A11 and A13-A15 along with an additional bit which is derived from a decoding of the four code bits KO-K3 defines the word pair address and the address bit A12 defines the word of the pair of words.

Pulses on the four leads HM, GM, CM, and CRW specify the mode of operation of the store as follows:

HM GM CM CRW Mode 0 0 0 0 Normal 0 1 1 0 Maintenance H 1 0 1 0 Maintenance G 1 1 0 0 Read Control 1 1 0 1 Write Control

The sync pulse is employed as a gating signal and reduces the time during which the program stores are vulnerable to noise signals on the buses.

In summary, information may be read from the Program Store 102 in the normal and the maintenance modes; information may be read from discrete test points within the program store control circuitry by means of a control mode read operation; information may be written into selected portions of the program store control circuitry by means of a control mode write operation; and, in addition, a large number of test points are connected to their associated scanning elements in the Master Scanner 144 either by way of the Program Store Diagnostic Cable 6901 or by way of the Program Store Diagnostic Bus 6902.

Call Store (103) [FIG. 8]

The Call Store of the Central Processor comprises a plurality of independent memory units. FIG. 8 is a block diagram of one such independent memory unit.

The Call Store of FIG. 8, like the Program Store of FIG. 7, is passive in the absence of commands from the Central Control.

In the illustrative embodiment, a word organized ferrite sheet memory is employed as the memory element of the Call Store 103. The Call Store of FIG. 8 is a destructive readout type memory and information may be read from or written into this memory in a time cycle which corresponds to the time cycle of the Central Control 101. The Call Store, being temporary in nature, is employed to store the system data which is subject to rapid change in the course of processing calls through the system.

Commands for controlling the Call Store are transmitted from the Central Control to the Call Store via the Bus System 6401, which comprises a "0" bus and an identical "1"bus. Such commands comprise an address defining a location within the Memory 8500 of FIG. 8 and an instruction portion which indicates that the command is to read information from the memory or to write information into the memory. In the case of commands to write information into the memory, the data to be placed in memory is transmitted from the Central Control to the Call Store via the Bus System 6402, which comprises a "0" bus and an identical "1" bus. As seen in FIG. 7, information can be selectively gated from the "0" bus and the "1" bus of the Bus Systems 6401 and 6402 for use in controlling the memory unit of FIG. 8. The Gates 802 through 805 are controlled in accordance with the contents of the Route Register 806 of FIG. 8. The Control 801 responds to commands from the Central Control to: (a) enable the Timing Circuit 8800 to initiate a memory timing cycle, (b) generate control signals for the Access Circuit 8501, 8502 and the Readout Circuit 8503, 8504, (c) enable the Operational Check Circuit 807, and (d) provide control signals for the Output Path Selection Gates 808. Output signals of the Timing Circuit 8800 serve to advance the Control 801 through a fixed sequence and to provide gating signals for the Access Circuit, the Readout Circuit and the Operational Check Circuit of FIG. 8. The Output Path Selection Gates 808 are selectively enabled by the Control Circuit 801 in accordance with the state of the Route Register 806 to gate data read from the Memory 8500 to the "0" or the "1" Call Store Response Bus of the Bus System 6501.

As seen in FIG. 8, the Route Register 806, like the Route Register 501 of the Program Store of FIG. 7, is controlled by signals over the Cables 6700, 6701. That is, the Route Register is controlled by output signals of the Central Pulse Distributor 143 in accordance with commands received by the Central Pulse Distributor from the Central Control 101.

The Central Control 101 manipulates the information in the Route Register 806 to achieve a desired association of the independent call store memory units and the buses of the Command Bus System 6401, the Data Bus System 6402 and the Response Bus System 6501.

In summary, an independent call store memory unit, such as is shown in FIG. 8, accepts command signals and data from the Central Control over a selected one of the buses "0" or "1" of the Call Store Command Bus System 6401 and the Call Store Data Bus System 6402 and transmits responses to the Central Control via a selected one of the buses "0" or "1" of the Response Bus System 6501. The Call Store of FIG. 8, through the Operational Check Circuit 807, monitors the internal operation of the call store memory and generates check signals for transmission to the Central Control along with the information read from the Memory 8500. The internal operation of a Call Store unit is in accordance with timing signals generated by the Timing Circuit 8500 and information is transmitted to the Central Control at times determined by such internally generated timing signals. The Timing Circuit 8500 is arranged to initiate a timing sequence when a command is received from the Central Control 101.

As previously discussed, the Call Store 103 comprises a plurality of independent Call Stores CS1 through CSN, which are shown in FIG. 6. The number of call stores is determined, like the program store is determined, by the size of the switching system and the variety of services rendered the lines and trunks of the system. At least two call stores are always used to achieve system dependability. The information capacity of a call store is divided into a left half and a right half. Where the number of call stores employed exceeds two, information is duplicated in the stores in the pattern described with respect to the storage of information in the program stores.

Information is retrieved from the Call Store System 103 by a command from the Central Control 101 designating an information block code name and an address designating the location of the desired information word within the designated information block. Similarly, information is written into the Call Store System 103 by a command from the Central Control 101 designating an information group code name, an address designating the location which is to receive the data and the coded data that is to be written into the designated information location.

With respect to the Program Store System 102, each information group therein is permanently assigned a discrete code name and since a block of information is duplicated in two stores, the two stores wherein this information is located are both arranged to respond to the same information block code name. In the case of the Program Stores 102 it is not possible to rearrange information within the stores of the Program Store System 102; however, in the case of the Call Store 103 it is possible in the event of failure of one or more stores of the system to rearrange information to assure duplication of certain important information. That is, certain of the information in the Call Stores 103 is of greater relative importance than other information; therefore, in the event of a failure of a call store within the Call Store System 103 it is desirable to rearrange the information in order to duplicate the more important information at the expense of losing duplication of the less important information. Accordingly, although each call store memory must respond to two information group code names, only one of the code names is permanently associated with a particular call store, namely, the code name of the information group stored in the left half of the memory is permanently retained. The code name associated with the information capacity of the right half of a Call Store 103 may be changed by a write control mode command from Central Control 101.

Communication Bus System 106 comprising the Address and Control buses 6401, the Data Buses 6402, and the Response buses 6501 which are private to the Central Control 101 and the Call Store 103 are employed respectively to transmit commands from the Central Control 101 to the Call Store 103; to transmit write data from the Central Control 101 to the Call Store 103; and to transmit responses from the Call Store 103 back to the Central Control 101. In addition to these three private communication paths each call store of the Call Store System 103 also receives information from the Central Control 101 via output signals of the Central Pulse Distributor 143.

An understanding of these private bus systems may be achieved through FIGS. 64 through 67. As seen in FIGS. 64 and 65 the Central Control System 101 comprising CC1 and CC2 is connected to the Call Store System 103 comprising CS1 through CSN via the Call Store Address Bus System 6401. The Call Store Address Bus System 6401 comprises two buses designated "0" and "1" and each bus comprises 26 conductor pairs. These buses may be energized from both of the central controls CC1 and CC2 and the output circuits of CC1 and CC2 are connected to the individual pairs of the Bus System 6401 in parallel. Both CC1 and CC2 may selectively transmit to the Call Store System 103 via either bus "0" or bus "1" of the Call Store Address Bus System 6401. The Call Store Address Bus System 6401 is coupled by way of serially connected transformers to receiving circuitry in each of the call stores CS1 through CSN. As seen in FIG. 64 certain of the conductor pairs of the Call Store Address Bus System 6401 are connected through serially connected transformers in both central controls CC1 and CC2. The utilization of these connections will be later described herein with respect to the transmission of certain maintenance messages from central control CC1 to central control CC2 and from central control CC2 to central control CC1.

As seen in FIGS. 64 and 65 the Call Store Write Data Bus System 6402 comprises two buses termed "0" and "1" and each bus comprises 25 conductor pairs. The buses are selectively driven in parallel by cable drivers in each of the central controls CC1 and CC2 and these buses are coupled by way of serially connected transformers to receiving circuitry in each of the call stores CS1 through CSN.

The Call Store Response Bus System 6501 comprises two buses "0" and "1" and each bus comprises 26 conductor pairs. The buses are driven in parallel by cable drivers in each of the plurality of call stores CS1 through CSN and these buses are coupled by way of serially connected transformers to receiving circuitry in both of the central controls CC1 and CC2.

The significance of the information transmitted from the Central Control 101 to the Call Store System 103 via the Call Store Address Bus System 6401, the Write Data Bus System 6402, and the Call Store Response Bus System 6501 is set forth later herein.

A call store may be operated in the following five modes:

1. Normal Read and Write Mode-- In this mode of operation Central Control 101 defines an address location in a particular block of store information and requests that the information found at this address be transmitted to Central Control 101 or that particular data be written in the defined location. Each block of duplicated information is assigned a code name in the six-bit code. Accordingly, two call stores which have duplicate information stored therein will respond to a single code name.

2. The H (left) Maintenance Read and Write Mode-- In this mode of operation Central Control 101 defines an address in a particular block of store information and only the store whose fixed name code corresponds to the transmitted code name will respond to the command. As in the normal mode, information may be read from the store or data may be written into the store.

3. The G (right) Maintenance Read and Write Mode-- In this mode of operation Central Control 101 defines an address in a particular block of information in the right or G half of a Call Store 103; however, the Call Store 103 is addressed by means of the fixed code name, i.e., the name associated with the block of information in the H or left half of the store.

In each of the above read modes of operation the addressed information location is regenerated.

4. Read Control Mode-- This is a maintenance mode of operation and in this mode status information in binary form relating to a number of test points is transmitted from a Call Store 103 to Central Control 101 via the Call Store Response Bus System 6501. The test points are arranged in groups called rows and the information comprising a row may be selectively designated in the command from Central Control 101.

5. Write Control Mode-- This mode permits Central Control 101, for purposes of rearranging data within the store and for purposes of trouble diagnosis, to selectively write information into various elements of the Call Store System 103. In the course of rearranging information in the store this mode permits Central Control 101 to selectively set or reset the flip-flops NO through N5 of the Variable Name Register and the flip-flops HS0, HS1, GS0, and GS1 of the Routing Register 601. In the course of trouble diagnosis these and other flip-flops within the call store control circuitry may be selectively set or reset in order to check their operation through a subsequent control read operation. It should be noted that it is not possible to write into all of the flip-flops of the store in this mode of operation and, further, that there are not flip-flops associated with all of the test points which may be read under the read control mode.

The Call Store System 103 is passive in the absence of commands from Central Control 101.

In the normal mode of system operation, i.e., the in-step mode, the stores which contain duplicate information are addressed over separate input buses, that is, the first store which has a block of information in its left or fixed half is addressed over, for example, the "0" bus, while the other store which has the duplicate block of information stored in its right half or variable address portion is addressed over the "1" bus. Similarly, the first store transmits its response over the "0" response bus, while the other store transmits its response over the "1" response bus. This is but one of a number of possible bus and store configurations and the exact store-bus configuration is determined by the Central Processor 100. The route register comprises seven control flip-flops in each Call Store 103. These are provided to control the inputs from the buses and the outputs to the buses. Certain of these flip-flops are set or reset by output signals from the Central Pulse Distributor 143, while others are set or reset by operating the Call Store 103 in the write control mode. A table of these flip-flops, the source of information for setting or resetting the flip-flop, and the significance of the flip-flop being set or reset is set forth below. ------------------------------------------------------------ --------------- Routing Flip-Flop Setting Source and Significance

Flip-flop Set and reset by Significance ____________________________________________________________ ______________ R0 CPD Set -Receive from bus "0." Send maintenance and control readout on bus "0." Reset-Receive from bus "1." Send maintenance and control readout on bus "1." HS0 Write Control Set -Send normal readouts from H side on bus "0." HS1 Write Control Set -Send normal readouts from H side on bus "1." GS0 Write Control Set -Send normal readout from G side on bus "0." GS1 Write Control Set -Send normal readout from G side on bus "1." TBL0 CPD Set -Inhibit operation with bus "0" (both receive and send). TBL1 CPD Set -Inhibit operation with bus "1" (both receive and send). ____________________________________________________________ ______________

These flip-flops are manipulated by the Central Control 101 to obtain desired store bus configurations not only during times when all stores and all bus systems are operating properly, but also during times when trouble is encountered and either the facilities of a bus or a particular store are not available.

The set and reset signals for the central pulse distributor controlled flip-flops RO, TBL0, and TBL1 are received over the Bipolar Cable 6700. There is one other bipolar signal which is applied to the Call Store 103 and this is employed to selectively set or reset the flip-flops of a Fault Register. The operation of the Fault Register is described later herein.

The bipolar signals are brought into the Call Store 103 via individual cable pairs of the Bipolar Cable 6700 and they each terminate in a transformer. The transformer is connected to provide an input signal to a first amplifier for a bipolar signal of a first polarity, i.e., a set signal and to provide an input signal to another amplifier in response to a bipolar input signal of the opposite polarity, i.e., a reset signal. A security signal termed herein a WRMI gating pulse accompanies each bipolar signal. WRMI signals are transmitted from the Central Pulse Distributor 143 to the various locations throughout the system via the WRMI Bus System 6701. This bus system comprises a first cable pair which is labeled bus "0" and a second cable pair which is labeled bus "1."

Separate set and reset signals are provided to the flip-flops, R0, TBL0, and TBL1.

With the above background information we may now proceed to the operation of a Call Store 103 as shown in FIG. 8 under the influence of a number of operating conditions. In the in-step mode of operation of Central Control 101, the Central Control System 101 will transmit identical address and control information over the duplicated buses of the Address Bus System 6401 and if a write order is to be executed, identical data will be transmitted from the Central Control System 101 over the two Call Store Write Data Buses 6402. This identical information on the two buses of 6401 and 6402 may come from the operating central control, or one bus of each of the Bus Systems 6401 and 6402 may be addressed by the operating central control while the other bus of each of these systems may be addressed by the standby central control.

The connection of the address buses to a Call Store 103 is shown in FIG. 8. The "0" bus, like the "1" bus as shown in FIG. 64, comprises 26 bits as follows:

a. 12 address bits A0-A11

b. six code bits K0-K5

c. three mode bits HM, GM, CM

d. synchronizing bit S1

e. two order bits R, W

f. one parity bit

g. synchronizing bit S2

As previously noted, each call store ferrite sheet memory comprises 8,192 discrete information word addresses. The 8,192 address locations of a call store memory are arranged in a minimum noise wiring pattern which is not disclosed herein. The individual word memory locations, however, may be defined for purposes of reading or changing the information at the desired location by means of a 12-bit binary address in conjunction with code bits K0-K5.

There are two identical groups each comprising 64 Y or horizontal drive lines associated with a call store memory and there are also two identical groups of X or vertical access drive lines of 64 wires each in each call store. This arrangement thus permits access to 2 × 64 × 64 or 8,192 word locations within a call store. As noted earlier herein, a 12-bit binary address comprising bits A0 through A11 is transmitted from the Central Control 101 to the Call Store 103 and, as is well known, 12 bits are necessary and sufficient to define 4,096 discrete locations. The additional bit of information required to define 8,192 locations is derived by the Code and Mode Decoder 8700. The fixed name code is always associated with the H or left half of a call store; therefore, if the Code and Mode Decoder portion of the Control 801 responds to an incoming fixed name code, and if the memory is operating in the normal mode, the command is of necessity directed to reading or writing information in a memory location which is in the left half of the store. However, if the command is to a call store which has the block of information bearing the identifying code name stored in the Variable Name Register, then the Code and Mode Decoder of the Control 801 will provide a variable address match signal. This indicates that the command is directed to reading or writing information in a memory location in the right half of the store.

The reading of information from a ferrite sheet memory is destructive and therefore it corresponds to an erase operation unless the reading is accompanied by a regenerate function. In the subject call store the reading of the memory at a bit location wherein there is stored a "0" will result in no output signal, while the reading of a bit location wherein there is stored a "1" results in an output signal.

Pulses on the five leads HM, GM, CM, R, and W specify the mode of operation of the store as follows:

HM GM CM R W Mode 0 0 0 1 Normal Read 0 0 0 0 Normal Write 0 1 1 1 H Maintenance Read 0 1 1 0 H Maintenance Write 1 0 1 1 G Maintenance Read 1 0 1 0 G Maintenance Write 1 1 0 0 Control Read 1 1 0 1 Control Read 1 1 0 1 Control Read 1 1 0 0 Control Write

A first synchronizing signal labeled "Sync 1" accompanies the address, code and mode bits and a second synchronizing signal labeled "Sync 2" accompanies the read, write and address parity information. The utilization of the read and write information is set forth in the table above.

As will be described later herein with respect to a memory write order, the data to be written at a defined word location is transmitted from Central Control 101 to the Call Store 103 via the Call Store Write Data Bus System 6402 and this information is gated to the Data Register 9016. Similarly, when the store is operated in the write control mode the information received over the Call Store Write Data Bus 6402 is gated on a two-rail basis to the various locations within the call store control circuitry which are to be selectively set or reset by the write control order.

In summary, information may be read from the Call Store 103 while operating the store in both the normal and the maintenance modes; information may be written into the memory proper of the Call Store 103 by operating the store in both the normal and maintenance modes; information may be read from discrete test points within the call store control and access circuitry by means of control mode read operations; information may be written into selected portions of the call store control circuitry by means of control mode write operations and, in addition, a large number of test points within the control and access circuitry are connected to their associated scanning elements in the Master Scanner 144 either by way of the Diagnostic Cable 6901 or the Call Store Diagnostic Bus 6903.

CENTRAL PROCESSOR DETAILS

The Central Processor 100 always comprises two central controls. In the usual mode of operation both central controls are performing the same work operations. Whenever possible the central controls obtain the same input information from different sources and over different transmission facilities. That is, in that the information in both the Program Stores 102 and the Call Stores 103 is duplicated in separate stores of the respective store systems, the first central control will receive information from a first store having the desired information and via a first bus of a bus system, while the second central control will receive information from the other store having the desired information via the other bus of the bus system. Assuming that the information obtained from the two stores, either Program Store 102 or Call Store 103, is identical and that the communication paths, i.e., buses are operating properly, the two central controls will perform the same work functions. However, at any given instant only one central control can alter the connections through the network or, in general, control the operation of the system. There are a few exceptions whereby the other central control may perform off line work functions which are different from those which are performed by the central control which is in control of the system functions.

In the normal in-step mode of operation set forth above the two central controls theoretically are operating upon identical input information; therefore, their operation should be identical. Correspondence of action of the two central controls is carefully checked by routinely comparing the flow of data through each central control. In the event that a mismatch is found between the data as it flows through the two central controls, the system is alerted.

In addition to matching the flow of data through the two central controls each central control performs a plurality of checks on the data which it processes. That is, information which is obtained from both the Program Store 102 and the Call Store 103 is protected by means of parity bits and, in the case of the Program Store 102, information is further protected by means of Hamming encoding which permits the detection of errors and the correction of single errors. In the event that either central control detects an error, either single or double, in the information received from a program store, the operation of the system is momentarily halted. In the event of a single error, the correction is made and in the case of a double error, the information is reread from the program store information source. In the case of call stores, a parity failure causes the system to momentarily halt and the information is reread from the call store.

At this point it might be well to differentiate between trouble indications which represent errors and faults. An error as defined herein is a malfunction of equipment which the system is not able to reproduce by a systematic logical procedure, while a fault is a malfunction of equipment which the system is able to reproduce repeatedly by a systematic logical procedure. When a trouble indication is first noted it is not known whether this indication represents an error or a fault; therefore, the system must undertake steps to make this determination. For example, as previously noted, if an error is detected in reading the Call Store 103 or an address error or a double error in the case of the Program Store 102, the system temporarily halts and rereads the particular store. If the trouble indication persists, a possible fault is indicated, while if the trouble indication does not persist, a mere transient error is indicated and the central controls proceed with their assigned tasks. It should be noted, however, that the central control increments a physical binary counter each time an error is noted and from time to time this counter is reset. At some time before resetting the counter, however, the output of the counter is examined to assure that the number of errors which have occurred in a fixed unit of time have not exceeded a certain maximum number. This procedure assures that the system is not overly burdened by large numbers of single nonrepeatable errors which probably indicate a system trouble. Nonrepeatable errors reduce the call processing capacity of the system in that the rereading operation requires additional time.

The realization of system maintenance objectives relies heavily on maintenance programs. Upon detection of trouble, a fault recognition program is called upon to recover the system's call processing ability. The fault recognition programs are assigned a high priority; however, their length is held to a minimum to avoid disrupting call processing. The fault recognition programs control any necessary switching or rearrangement of equipment; and request, for subsequent execution, an appropriate low priority diagnostic program which is designed to localize the fault within the faulty unit of equipment. The results of the diagnostic programs are printed out via the Teletype Unit 145 for the use of the maintenance personnel.

In addition to making routine checks on the validity of information which is received from the stores and to making routine checks upon the flow of information through the Central Processor 100, the system also performs a plurality of routine test programs. The test programs have a low execution priority and are designed to search for system faults which are likely to go undetected in normal call processing. The routine test programs can be initiated either automatically on a scheduled basis or as a function of other programs or may be manually requested by means of the Teletype Unit 145.

Central Control Responses to Program Order Words

FIG. 9, which is a simplified sketch of the Central Control 101, aids in understanding the basic operational step actions that are performed by Central Control 101 in response to various program order words. Each program order word comprises an operational field, a data-address field, and Hamming error detecting and correcting bits.

The operation field is a 14- or a 16-bit binary word which defines the order and specifies the operational step actions to be performed by the Central Control 101 in response to the order. The operation field is 14 or 16 bits long, depending on the particular order which is defined by the operation field.

There are sets of "options" that may be specified with each of the program order words. The operational step of each order consists of a specific set of gating actions to process data contained in Central Control 101 and/or communicate information between the Central Control 101 and other units in our system. When an option is specified with the program order being executed, additional data processing is included in the operational step. The specific gating actions and the data processing performed for each of the options are described elsewhere herein. Accordingly, a portion of the 14 or 16 bit operation field of a program order word specifies the program order, and the remaining portion of the field may select one or more of the options to be executed.

Certain of the options are compatible with and provide additional data processing for nearly all of the orders. An example of such an option is that of "indexing" in which none or one of seven flip-flop registers within Central Control 101 are selected for additional data processing. In the orders which permit indexing a three-bit portion of the operation field is reserved as the indexing field to indicate the choice of none or the one of seven registers to be employed.

Other options are limited to those orders for which the associated gating actions do not conflict with other portions of the operational step and are also excluded from those orders to which the options do not provide useful additions. Accordingly, portions of the operation field are reserved for those options only where applicable. That is, Central Control 101 is responsive to such options only if the program order word being executed is one to which the options are applicable. If an option is not applicable, then that portion of the operation field instead serves in the specification of other program orders or options. The assignment of the binary codes in portions of the operation field to options is therefore selectively conditioned upon the accompanying program order if the option is to have limited availability. This conditional assignment advantageously permits the inclusion of a larger variety of orders and options than could otherwise be included in the 14- to 16-bit operation field.

The data-address field of a program order word is either a twenty-three bit data word to be placed in a selected flip-flop register in Central Control 101 or a 21-bit word which may be used directly or with indexing to form a code-address for addressing memory. In all order words the sum of the bits of the operation field (16 or 14 ) plus the bits of the data-address field 21 or 23 is always 37 bits. If the order word has a sixteen bit operation field, its data-address field will be twenty-one bits long; if the operation field is 14 bits long, the data-address is a 23-bit number. The shortened D-A field is utilized to obtain more combinations in the correspondingly lengthened operation field and therefore a larger and more powerful collection of program order words.

The Central Control 101 performs the operational steps for most orders at the rate of one order per 5.5-microsecond cycle. Although such orders are designated single cycle orders, the total time involved in obtaining the order word and the central control responses thereto is in the order of three 5.5-microsecond cycles. The overlap operation previously noted herein permits Central Control 101 to achieve the stated rate of performing one such single cycle order every 5.5 microseconds.

The sequence of gating actions for a typical order, order X, and their relationship to the gating actions for the preceding order, order X-1, and a succeeding order, order X+1, are shown in FIG. 84. As shown on line 2 of FIG. 84, during phase 1 of a 5.5-microsecond cycle that is arbitrarily designated cycle 1, the code and address of program order word X appears in the Program Address Register 4801 (PAR) and is gated to the Program Store 102 via the Program Store Address Bus 6400. The code and address is interpreted by the Program Store 102 and the order word X is returned to central control over the Program Store Response Bus 6500 sometime during phase 3 of cycle 1 or phase 1 of cycle 2. The operation field portion of the program order word is gated into the Auxiliary Buffer Order Word Register 1901 (ABOWR), and the data-address field, and the Hamming bits of the order word are gated into the Buffer Order Word Register 2410 (BOWR).

The operation field is first gated into the Auxiliary Buffer Order Word Register 1901 (ABOWR) since it is possible that the program order word which is returned from the Program Store 102 reaches Central Control 101 prior to completion of the gating actions by the Buffer Order Word Decoder 3902 (BOWD) on the preceding order word, in this case order word X-1. This may be seen by reference to FIG. 84 where in the line labeled X-1, the gating directed by the Buffer Order Word Decoder 3902 (BOWD) for the order word X-1 is completed at the end of phase 3 of cycle 1; and, as shown in the line labeled X, the program order word X may reach central control in the latter portion of phase 3 of cycle 1. The Auxiliary Buffer Order Word Register 1901 (ABOWR) resolves this conflict. The same situation does not obtain with respect to either the Hamming encoding bits or the data-address word as by the end of phase 2 of cycle 1 all of the actions with respect to both the Hamming encoding bits and the data-address bits for the order X-1 have been completed.

The time at which a program order word reaches the Central Control 101 is subject to variation as a result of a number of factors. For example, since there are two central controls and a number of program stores, the physical distance between a particular central control and each of the program stores is different and this difference is reflected in both the Program Store Address Bus 6400 and in the Program Store Response Bus 6500. Further, there may be differences in the response times of the various program stores and their access circuits and these variations may be cumulative with the differences in bus lengths.

The decoded outputs of the Buffer Order Word Decoder 3902 (BOWD) are combined with selected clock pulses from the Microsecond Clock 6100 (CLK) in the Order Combining Gate Circuit 3901 (OCG) which operates selected gates within Central Control 101 in the proper time sequence during phase 2 and phase 3 of the second cycle to perform indexing, index modification, and certain other gating actions with respect to order X.

During phase 3 of the second cycle the operation field of order X (FIG. 84) is gated from the Buffer Order Word Register 2410 (BOWR) to the Order Word Register 3403 (OWR). The Order Word Decoder 3904 (OWD) decodes the operation field of the order X which is in the Order Word Register 3403 (OWR) for the performance of the remaining gating actions. D-C output signals from the Order Word Decoder 3904 (OWD) are combined with selected pulses from the Microsecond Clock 6100 (CLK) in the Order Combining Gate 3901 (OCG) to complete the gating actions of the single cycle order X during phase 1 and phase 2 of the third cycle.

During phase 2 of the third cycle order X is completing its last gating action from the Order Word Register 3403 (OWR) and the Order Word Decoder 3904 (OWD), and order X+1 is simultaneously performing the indexing step from the Buffer Order Word Register 2410 (BOWR) and the Buffer Order Word Decoder 3902 (BOWD). Since the simultaneous gating actions may conflict in the use of the flip-flop registers such as XR, YR, ZR, et cetera, the Mixed Decoder 3903 (MXD) decodes the contents of both the Buffer Order Word Register 2410 (BOWR) and the Order Word Register 3403 (OWR). The Mixed Decoder 3903 (MXD) outputs, which are D-C signals, are combined with the outputs of the Buffer Order Word Decoder 3902 (BOWD) in the Order Combining Gates 3901 (OCG) to modify gating actions so as to resolve conflicts in the two operational steps.

A conflict which is resolved by the Mixed Decoder 3903 occurs when a first order specifies a particular one of the index registers as the destination register for a memory word obtained by the execution of that order while the immediately succeeding order specifies that the contents of that same index register be employed in indexing. In the performance of indexing, the contents of the specified index register are normally gated from the output of the specified index register to the Unmasked Bus 2014 and from there to the Augend Register 2908. However, where successive orders specify the same index register as a destination register for memory reading and as a source register, there is insufficient time to complete the transfer of the information to the destination register; therefore, the Mixed Decoder 3903 in these instances transfers the desired information from the Masked Bus 2011 directly to the Augend Register 2908 at the same time that this information is being transmitted to the specified destination index register.

Mask and Complement Circuit 2000 (M&C)

The internal data processing structure is built around two multiconductor buses, the Unmasked Bus 2014 (UB) and the Masked Bus 2011 (MB), which provide a link for moving a multibit word of data from one of a specific group of flip-flop registers to another. This group consists of the Index Registers 2601 (BR), 5801 (FR), 5802 (JR), 4001 (KR), 2501 (XR), 3001 (YR), and 3002 (ZR) and the Logic Register 2508 (LR).

The Mask and Complement Circuit 2000 (M&C) connects the Unmasked Bus UB to the Masked Bus MB and provides means for logically operating upon the data as it passes from the Unmasked Bus UB to the Masked Bus MB. The logical operation to be performed, product masking (AND), union masking (OR), exclusive OR masking (EXCLUSIVE-OR), and complementing is prescribed by the operation field of the program order as decoded by either the Buffer Order Word Decoder BOWD or the Order Word Decoder OWD. Only one masking operation may be performed in a single pass of data through the circuit M&C however, the masking operation may be followed by a complementing operation in gating data through the circuit M&C. Each of the masking operations requires two operands and the contents of the Logic Register LR always comprises one of the operands.

The Mask and Complement Circuit M&C (2000) which is shown in greater detail in FIG. 20 also provides a convenient means for connecting the Data Buffer Register 2601 and the Index Adder Output Register 3401 to the Masked Bus 2011. The data word which appears at one of the input AND gates 2001-2003 of the Mask and Complement Circuit 2000 may be selectively gated directly to the Masked Bus 2011 without alteration or may be masked and/or complemented during transmission through the mask and complement circuit. The AND-OR Circuit 2005 serves to "Union" mask or "Product" mask the input data word when enabled by order cable signals on conductors 20UMASK and 20PMASK, respectively. The word appearing at the output of the AND-OR Circuit 2005 may be complemented in the Complement Circuit 2006 by enabling order cable conductor 20COMP or may be transmitted directly to the Masked Bus 2011 by enabling order cable conductor 20MPASS.

The input data word may be gated directly to the Masked Bus 2011 by enabling AND gate 2012 by an order cable signal on conductor 20PASS or may be complemented in the Complement Circuit 2007 by enabling order cable conductor 20COMP.

Exclusive OR masking may be achieved in the EXCLUSIVE-OR Circuit 2008 by enabling order cable conductor 20XMASK. It should be noted that it is not possible to complement the data word appearing at the output of the EXCLUSIVE-OR Circuit 2008.

K Register 4001 (KR); K Logic (KLOG);

Detect First-One Circuit 5415 (DF0)

The K Register KR, the K Logic KLOG, and the Detect First-One Circuit 5415 (DF0) provide a second major internal data processing facility. The K Logic KLOG comprises input and output circuitry surrounding the K Register 4001. The K Logic KLOG includes the K A Input Register 3502, the K B Input Register 3504, the K Input Logic 3505, the K Logic Homogeneity Circuit 4502; and at the output of the K Register 4001 the Rotate Shift Circuit 4500 and the K Register Homogeneity Circuit 4503. The K Logic KLOG may be directed by output signals of the Order Combining Gate OCG to perform one of four logical operations on two operands. One operand is the content of the K Register KR; the other is the information on the Masked Bus MB. The Order Word Decoder OWD and the K Register Sequence Circuit (part of SEQ) generate signals which cause the K Logic KLOG to combine the two operands in the operations of AND, OR, EXCLUSIVE-OR, or ADDITION. The word resulting from the logical combination, according to the order in the Order Word Register OWR, may either be gated to the K Register KR or to the Control Homogeneity Circuit CH and the Control Sign Circuit CS.

A word appearing on the Masked Bus MB may in some instances be gated directly to the K Register KR via the K Logic KLOG. The K Register KR may thereby be employed as a simple destination register for data like other flip-flop registers in central control such as XR, YR, ZR, et cetera.

In carrying out the ADDITION operation in the K Logic KLOG the two operands are treated as 22 bit signed numbers. The twenty-third bit of each operand is the sign bit. If this bit has the value "0" the number is positive, and the magnitude of the number by the remaining 22 bits. If the sign bit is "1" the number is negative, and the magnitude of the number is given by the one's complement of the remaining 22 bits. (The magnitude is determined by inverting each bit of the 22 bit number.) The add circuit within K Logic KLOG can correctly add any combination of positive and negative operands as long as the magnitude of the algebraic sum of the two operands is equal to or less than 2 ²² -1.

The K Logic KLOG and the K Register KR can perform other logical operations on the contents of the K Register KR. One of these operations is given the name "SHIFT." The gating action performed by SHIFT is based, in part, on the least significant six bits of the number that appears in the Index Adder IA at the time the shift is to be performed. The least significant five bits constitute a number that indicates the magnitude of the shift, and the sixth bit determines the direction of the shift. A "0" in the sixth bit is interpreted as a shift to the left, and the remaining five bits indicate the magnitude of this shift. A "1" in the sixth bit is interpreted as a shift to the right, and the one's complement of the remaining five bits indicates the magnitude of the shift to the right. Although in shifts to the right the least significant five bits contain the one's complement of the magnitude of the shift, the six bit number will be referred to hereafter as comprising a sign and a magnitude.

A shift of one to the left results in the contents of each flip-flop in the K Register KR being gated to the adjacent flip-flop to the left where the register is viewed as in FIG. 40. (The most significant bit of the K Register KR, bit 22, is on the extreme left; and the least significant bit, bit 0, is on the extreme right.) A "0" replaces the contents of the least significant bit position of the K Register KR (there is no flip-flop to the right of the "0" position flip-flop) and the most significant bit is shifted out of the register. That is, the bit 22 flip-flop has no flip-flop to its left and the information is not retained.

A shift of two to the left is equivalent to two successive shifts of one to the left, a shift of three to the left is equivalent to three successive shifts of one to the left, et cetera. A shift of 23 to the left causes all zeros to be placed in the K Register KR. A shift of one to the right results in the contents of each flip-flop in the K Register KR being gated to the adjacent flip-flop to the right. A "0" replaces the contents of the most significant bit of the K Register KR, and the original least significant bit of the K Register KR is thus not retained.

A shift of two to the right is equivalent to two successive shifts of one to the right, a shift of three to the right is equivalent to three successive shifts of one to the right, a shift of 23 to the right results in the contents of the K Register KR being made all zeros.

A logical operation similar to the shift is the operation "ROTATE." As in shifting, the six bits of the Index Adder IA are treated as a direction and magnitude for the rotation just as described for the shift.

A rotate of one to the left is identical to a shift of one to the left except for the gating of the flip-flops at each end of the K Register KR. In a rotation of one to the left the content of bit 22 is not lost as in the shift but instead replaces the content of the least significant zero bit of the K Register KR. A rotate of two to the left is identical to two rotates of one to the left in succession, a rotate of three to the left is identical to three rotates of one to the left, et cetera. A rotate of 23 to the left has the same effect on the K Register KR as no rotation. A rotation to the right bears a similar relation to a shift to the right.

In summary, the gating action of rotation is identical to that of shift except that the register is arranged in a circular fashion wherein the most significant bit is treated as being to the right of the least significant bit of the K Register KR.

A complement option may be employed with shift and rotate orders and, where specified, the significance of the sign bit is inverted, that is, where the complement option is specified a "0" in the sixth bit is interpreted as a shift to the right while a "1" in the sixth bit is interpreted as a shift to the left.

A special purpose rotate order applies rotation to only bits 6 through 21 of the K Register KR and leaves the remaining positions of the K Register KR unchanged.

Another logical gating action is the determination of the rightmost one in the contents of the K Register KR. This action is accomplished by gating the contents of the Detect First-One Circuit DF0 to the F Register FR via the Unmasked Bus UB, the Mask and Complement Circuit M&C, and the Masked Bus MB. The number gated is a five bit binary number corresponding to the first stage (reading from the right) in the K Register KR which contains a "1." If the least significant bit of the K Register KR contains a "1," zero is the number gated to the F Register FR. If the first "1" reading from the right is in the next position, one is the number gated to the F Register FR. If the only "1" appearing in the K Register KR is in the most significant position, 22 is the number gated to the F Register FR. If the K register contains no "1's," then nothing is gated to the F Register FR.

Index Adder (IA)

A third major data processing configuration within the Central Control 101 is the Index Adder IA which is used to:

1. Form a quantity designated herein as the indexed DAR word consisting of the sum of the D-A field of the program order word being executed and the contents of an index register specified in an order, or

2. To perform the task of a general purpose adder; the operands in this latter instance may be the contents of two index registers or the D-A field and the contents of an index register.

The outputs of the Index Adder IA are selectively connected to the Program Address Register PAR, the Memory Address Decoder MAD, and the Call Store Address Bus System 6401 when employed for indexing; the outputs of the adder may also be connected to the Masked Bus MB via the Mask and Complement Circuit MNC when employed as a general purpose adder. Access to the Masked Bus MB permits the word formed to be employed for a number of purposes, for example:

1. Data to be placed in the K Register KR without modification or to be combined with the contents of the K Register KR in the K Logic KLOG:

2. A number for determining the magnitude and direction of a shift or rotate;

3. Data to be placed in a specified index register;

4. Data to be transmitted over the Network Command Bus 6406 via the K Logic KLOG and the Network Translator NETW-T:

5. Data to be sent to the Central Pulse Distributor 143 via the F Register FR and the Central Pulse Distributor Translator CPD-T.

Indexing is the adding of two numbers in the Index Adder IA. The D-A field of the order as it appears in the Buffer Order Word Register BOWR is one operand used in indexing and the other operand, if required, is the contents of one of the seven Index Registers BR, FR, JR, KR, XR, YR, and ZR. For orders which include the indexing option a three bit number within the operation field specifies either (1) no indexing, of (2) indexing on one of the seven flip-flop registers according to the following table.

X34 X33 X32 Register 0 0 0 No register 0 0 1 BR 0 1 0 FR 0 1 1 JR 1 0 0 KR 1 0 1 XR 1 1 0 YR 1 1 1 ZR

if no register is specified for indexing, then only the D-A field is gated to the Index Adder IA and the output of the Index Adder IA will be the D-A field (the sum of the D-A field and zero). If an index register is specified, the contents thereof are normally gated onto the Unmasked Bus UB and from there directly into the Index Adder IA.

If the order X specifies indexing, and if the index constant is obtained by a memory reading operation of the preceding order X-1, then the Mixed Decoder MXD substitutes the Masked Bus MB for the index register. The Mixed Decoder MXD insures that the Index Adder IA always has the correct operands to perform the timely addition to complete the operational step for order X.

A number of the orders have as an option specified by a combination of bits in the operation field the loading of the D-A field into the Logic Register LR. This option permits the placing of specified new data into the Logic Register LR for use in subsequent masking operations. If the D-A field is used to load the Logic Register LR, then it is considered not available for indexing and the only operand gated to the Index Adder IA is the contents of a specified index register.

The sum appearing at the output of the Index Adder IA is referred to as the DAR address or word. If indexing is not specified in an order, the DAR address or word is the D-A field of that order. If indexing is specified and the D-A field is not gated to the Logic Register LR, the DAR address or word will be the sum of the D-A field and the contents of the specified index register. If the D-A field is used for loading the Logic Register LR, the DAR will be the contents of the specified index register.

The Index Adder IA, as well as the add circuit within the K Logic KLOG, utilizes one's complement binary arithmetic. All inputs of the index adder are treated as 22-bit numbers with the 23 bit a sign bit. A positive number is indicated by a "0" in the 23 bit and a negative number by a "1" in the 23 bit. End-around-carry is provided so that the Index Adder IA can correctly handle all four combinations of positive and negative operands as long as the algebraic sum of the two operands does not exceed 2 ²² -1.

Some orders, as previously mentioned, have a 23-bit D-A field, and others have a 21-bit D-A field. If the D-A field is only 21 bits long, then the 21 bit is treated as the sign bit; this bit is expanded to also become the 22 and 23 bits of the effective D-A field gated to the Index Adder IA. Expansion converts a 21 bit D-A field to an effective 23 bit D-A field for indexing. Expansion preserves the end-around-carry for indexing with 21-bit D-A fields.

Decision Logic 3906 (DECL)

The Central Control 101 in the execution of a decision order in a sequence of orders either continues with the current sequence of orders or transfers to a new sequence of orders. The decision is made by the Decision Logic 3906 (DECL) in accordance with the order being processed. The order specifies the information to be examined and the basis for the decision. The information may be obtained from the Control Homogeneity Flop-Flop 5020 of the Control Homogeneity Circuit CH, the Control Sign Flip-Flop 5413 of the Control Sign Circuit CS or selected outputs of the K Logic KLOG. The basis of the decision may be that the information examined is (or is not) arithmetic zero, less than zero, greater than zero, et cetera. A decision to advance does not disturb the current sequence of obtaining and executing orders. A decision to transfer to a new sequence of orders is coupled in accordance with the particular word being executed to a determination of whether the transfer is an "early transfer" or a "late transfer." Accordingly, if the decision is made to transfer, either the early transfer conductor ETR or the late transfer conductor LTR will be energized and thereby activate the Transfer Sequencer 4401. Transfer signals from these conductors lead to the gating of the transfer address to the Program Address Register PAR. This causes the next program order word to be obtained from a new sequence of order words. The transfer address may be obtained from a number of sources and the source is indicated by the order being executed. In the case of "early transfer" orders, the transfer address comprises the contents of a preselected one of the J Register JR or the Z Register ZR. In the case of "late transfer" orders the transfer address may be obtained directly, in which case the DAR code-address which is formed in the index adder is employed, or indirectly, in which case the transfer address comprises a memory reading at the location specified by the DAR code-address which is formed in the Index Adder IA. This latter case is referred to herein as indirect addressing.

The distinction between "early transfer" and "late transfer" orders is based on whether or not the decision order requires a memory reading or writing in the event of an advance. A decision order which requires a memory to be read or written into after a decision to advance is an "early transfer" order. If the decision on such an early transfer order is to advance, then the memory reading or writing operation is carried out as a normal gating action under control of the Buffer Order Word Decoder BOWD and the Order Word Decoder OWD. However, if the decision is to transfer, the decision is advantageously made "early" to inhibit the gating associated with the memory reading or writing operation.

Other transfer orders which do not require a memory reading operation but which do require extensive data processing prior to making the decision are termed "late transfer" orders. These orders cannot employ the early transfer timing sequence in that the data processing operations required thereby are not necessarily completed by the time the early transfer signal would be generated.

Two input information sources for the decision logic comprise the output signals of the control homogeneity flip-flop and the control sign flip-flop which are employed to register homogeneity and sign information which is obtained from a number of locations. For example, a 23-bit data word appearing on the Masked Bus MB may be transmitted to the Control Homogeneity Circuit CH. If the data word comprises either all "0's" or all "1's," the Control Homogeneity Flip-Flop 5020 will be set to its "2" state, otherwise the flip-flop will be reset. The Control Sign Circuit CS serves to retain the sign of the data word; the Control Sign Flip-Flop 5413 is set if the word is negative and is reset if the word is positive.

The Control Homogeneity Circuit CH and the Control Sign Circuit CS are utilized by some decision orders by gating the output of a selected index register onto the Unmasked Bus UB, through the Mask and Complement Circuit MNC, onto the Masked Bus MB, and from there into the Control Homogeneity Circuit CH and the Control Sign Circuit CS. The contents of one of the seven index registers specified in the decision order being processed are thereby summarized in the Control Homogeneity Flip-Flop 5020 and Control Sign Flip-Flop 5413. Further gating actions associated with a decision order carry out the transfer or advance according to the output of the Decision Logic DECL.

Similar homogeneity and sign circuits comprise part of the K Logic KLOG to provide facilities for a class of decision orders which transfer or advance according to combinations of the homogeneity and sign of 23-bit words contained in the K Register KR.

Communication Between the Central Control 101 and Connecting Units

A second basic function of Central Control 101 is the communication between itself and various other units such as the various memories within the Central Processor 100, the Switching Network 120, the Master Scanner 144, the Central Pulse Distributor 143, et cetera. Generally, communication is accomplished by way of the various bus systems of FIGS. 64-69 and logic circuits which are located in both Central Control 101 and the connecting units.

This communication consists of three general classes. The first class comprises the obtaining of program order words which determine the sequence of actions within Central Control 101. Program order words are primarily obtained from the Program Store 102; however, in special instances program order words for limited actions may be obtained from a Call Store 103. The second class comprises the obtaining of data (excluding program order words) from the memory units within the Central Processor 100, and the third class comprises the generation and transmission of commands to the various network units such as the Switching Network 120, the Master Scanner 144, the Central Pulse Distributor 143, et cetera.

The several memories within the Central Processor 100, namely the Program Store 102, the Call Store 103, the Auxiliary Buffer Registers 3105, 3118, 3605, 3617, 4103, 4603, 5105-5107, 5500, 5902, 6205, 3206, 3703-3708, 4206, 4211, 4717, 4725, 5201, 5209-5211, 5604, 5605, 6002, 6003, 6302 and 6307 (ABR-1...ABR-N [FIG. 9]), and certain other special locations within Central Control 101 are treated as a memory unit and distinct blocks of addresses are individually assigned to each of the memories. There are a number of memory orders which are employed to selectively obtain information from the above memories and to place this information in selected registers within Central Control 101; these are memory reading orders. There are other memory orders which are employed to selectively transmit data from designated registers within Central Control 101 to one of the above memories; these are memory writing orders. The order structure is thus simplified since access to all of the above-mentioned memory locations is by way of a single memory address format.

A memory code-address within Central Control 101 always comprises a 20-bit word consisting of:

1. A code to define a block of information; and

2. An address within the specified block. The code and the address each vary in length according to the memory unit addressed. For example, the codes for specifying information blocks in the program store are four bits long, and the corresponding address is 16 bits long; the codes for specifying information blocks in the Call Store 103 are eight bits long and are accompanied by twelve bit addresses. However, as will be seen later, the code-address which is transmitted to the Call Store 103 comprises an 18-bit portion of the word, namely a six-bit code and a twelve bit address.

Program Order Words

The communication between the Central Control 101 and the Program Store 102 to obtain program order words may be understood generally with reference to FIG. 9 and in greater detail through a consideration of the central control detail drawings FIGS. 10 through 63 and the timing diagram FIG. 84. The Program Address Register 4801 (PAR FIG. 9) and the Auxiliary Storage Register 4812 (ASR FIG. 9) are selectively employed in transmitting commands to the Program Store 102. The Program Address Register 4801 is employed in the absence of uncorrectable program store reading errors. The Auxiliary Storage Register 4812 is employed whenever a Program Store 102 must be reread. When a command is transmitted from the Program Address Register 4801 to the Program Store Address Bus System 6400 the code-address of the command is also transmitted to the Auxiliary Storage Register 4812. The Auxiliary Storage Register 4812 thus serves to temporarily hold the code-address which is employed in the performance of Hamming error checks. These checks are applied simultaneously to the order returned and the address employed in obtaining the order. Commands to the Program Store 102 to read information from the memory proper as opposed to test points within the memory access and control circuitry comprises 25 bits as follows:

A. 16 address bits A0 through A15,

B. Four code bits K0 through K3,

C. Four mode bits CM, HM, GM, CRW,

D. a single synchronizing bit SYNC. The code bits K0 through K3 define the block of information in which the selected program store word is located and the address bits A0 through A15 define the memory location within the above defined block of information. The four mode bit specify the mode of operation of the program stores as set forth below. It should be noted that the Program Store 102 is always operated in the normal mode in the course of obtaining program order words. The two maintenance modes and the read control and write control modes are reserved for obtaining from the program store information which is to be treated as data as opposed to program order words.

HM GM CM CRW Mode 0 0 0 0 Normal 0 1 1 0 Maintenance H 1 0 1 0 Maintenance G 1 1 0 0 Read Control 1 1 0 1 Write Control

The sync pulse SYNC [FIG. 33] is employed as a gating signal at the program stores and serves to reduce the time during which the program stores are vulnerable to noise signals on their command buses.

The code and address portions of the program store commands are obtained from the Program Address Register 4801 or the Auxiliary Storage Register 4812 and the four mode bits and the synchronizing bit are obtained from the Order Cable 3900. The four mode bits are required to be selectively other than "0" in all modes other than the normal mode and in these modes the mode bits are defined by the program order word being executed.

The contents of the Program Address Register 4801 (PAR) or the contents of the Auxiliary Storage Register 4812 (ASR) are selectively gated via AND gates 4805 ad 4813, respectively, to the input terminals of the OR gate 4806. AND gate 4805 is enabled by an order cable signal on conductor 48PAPS and AND gate 4813 is enabled by an order cable signal on conductor 48PAPS and AND gate 4813 is enabled by an order cable on conductor 48ASPS. Information appearing on selected output conductors of OR gate 4806 is encoded, and the encoded information is transmitted to the cable 4804. Bits 0 through 11 and 13 through 15 are passed without modification; however, bits 6 and 12 are combined in the EXCLUSIVE-OR gate 4803 to form bit 12 of the command address. The EXCLUSIVE-OR function involving bits 6 and 12 of the address provides information which is required at the program store to choose the appropriate program store tape, i.e., the A tape or the B tape. Bits 16 through 19 as received from the OR gate 4806 are translated from the four bit binary code to a 2-out-of-4 code in the Translator 4802. As previously explained, the Program Store 102 is arranged to selectively respond to 2-out-of-4 code signals.

The translated code-address is transmitted via cable 4804 to the Program Store Transmit Bus Selection Gates 3300. The remaining information signal inputs to the Program Store Transmit But Selection Gates 3300 comprise the mode bits CM, HM, GM, and CRW which are received from the Order Cable 3900 via conductor group 3317 and the synchronizing bits PS-BIT [FIG. 33] and PS-BOT [FIG. 33].

The Program Store Transmit Bus Selection Gates 3300 are divided into two groups, namely, those employed for transmitting to the "0" bus 3306 of the Program Store Address Bus System 6400 and those associated with the "1" bus 3307 of the Program Store Address Bus System 6400. The command information is selectively transmitted to the "0" bus and/or the "1" bus of the Program Store Address Bus System 6400 in accordance with the Program Store 102-Central Control 101 bus configuration which is being employed. That is, if information is being transmitted from the Central Control 101 to the Program Store 102 via the "0" bus 3306, AND gates 3302, 3308, and 3312 and amplifier 3310 are employed; however, if commands are being transmitted by the "1" bus 3307, AND gates 3303, 3309, and 3313 and amplifier 3311 are employed. The address bits A0 through A15 are selectively gated through the AND gates 3302 and 3303 by signals on order cable conductors ADRPS-BO and ADRPS-B1 [FIG. 33], respectively. Similarly, the K bits K0 through K3 and the mode bits are selectively transmitted via AND gates 3308, 3312, 3309 and 3313 by order cable signals on conductors PS-BOT and PS-BiT, respectively. Signals on PS-BOT and PS-BiT are also transmitted through their associated amplifiers 3310 and 3311 to provide the synchronizing bit of the program store command.

The output conductors of AND gates 3302, 3308, and 3312 and amplifier 3310 are transmitted via the Cable Driver 3304 to the "0" bus 3306; and the output conductors of AND gates 3303, 3309 and 3313 and amplifier 3311 are transmitted via the Cable Driver 3305 to the "1" bus 3307. The Cable Drivers 3304 and 3305 each comprise a plurality of pulse inverting amplifiers and transformers which couple the Program Store Transmit Bus Selection Gates 3300 to the "0" bus 3306 and the "1" bus 3307.

The Program Store Transmit Bus Selection Gates 3300 are selectively enabled in accordance with the setting of the central pulse distributor controlled status and routing register flip-flops AU, PBO, PBA, and PBT [FIG. 55]. The state of flip-flop AU indicates which of the two units is the active central control. The flip-flops PBO, PBA, and PBT (except for commands to read or write control or maintenance data) have the following significance: ##SPC1##

In the above table the X indicates that the standby CC is to send on neither the "0" nor the "1" bus as the active CC is engaged in transmitting to both buses.

The status and routing flip-flops AU, PBO, PBA, and PBT are selectively set and reset by pulses received from the Central Pulse Distributor 143 via selected pairs of the Bipolar Cable 6700, the transformer 1707, amplifiers 1708 and 1711, AND gates 1709 and 1712 and the CPD cable 1719.

The flip-flops PBO, PBA, and PBT in the two central controls are driven by the same CPD points, that is, when the flip-flop PBO in the first central control is set its counterpart PBO in the other central control is also set. The flip-flops AU (active unit) in the two central controls are controlled by a single central pulse distributor bipolar signal point; however, the bipolar signal which serves to set the AU flip-flop in the first central control serves to reset the AU flip-flop in the second central control. Similarly, the CPD signal which serves to reset the AU flip-flop in the first central control serves to set the AU flip-flop in the second central control.

The information required to define the code-address of a program store command is transmitted to the Program Address Register 4801 by one of three possible paths, the chosen path being determined by the sequence of events which lead to the determination of the desired address and code. The desired code-address is selectively obtained by one of the following methods:

A. In the course of executing a sequence of program order words and in the absence of a transfer decision, the code-address of the next order word in the sequence is obtained by incrementing the code-address of the preceding order word by a count of 1. This incrementing function is accomplished by means of the Add-One Register 4304 and the Add-One Logic 4305. The contents of the Program Address Register 4801 are transmitted via cable 4821, AND gate 4301, and OR gate 4303 to the Add-One Register 4304. The AND gate 4301 is enabled by an order cable signal on conductor PAAO [FIG. 43] at time 0T2. The code-address in the Add-One Register 4304 comprises the input to the Add-One Logic 4305 which when enabled by signals on conductor INCR [FIG. 43] serves to increment the input word by a count of 1. The output of the Add-One Logic 4305 is gated to the Program Address Register 4801 via AND gate 4807 and OR gate 4808 at time 3T5 by a signal on order cable conductor AOPA [FIG. 48].

From the above sequence it is seen that a very small portion of the 5.5-microsecond operational step cycle is employed in incrementing the address in the Program Address Register 4801. That is, the total time required to increment the address and to return the incremented address to the PAR 4801 is the period of time 0T5. Completion of address incrementing in this period of time frees the Add-One Register 4304 and the Add-One Logic 4305 to permit their use for other work functions during the remainder of the cycle. The Add-One Register 4304 and the Add-One Logic 4305 are arranged to operate with 23-bit words for these other work functions.

B. The second source of program store code-address words is the Index Adder Output Register 3401. The Index Adder Output Register 3401 is provided to store the DAR word as described earlier herein. The contents of the Index Adder Output Register 3401 are transmitted via cable 3402, AND gate 4307, and OR gate 4808 to the Program Address Register 4801. This transfer of information is accomplished by enabling order cable conductor IRPA [FIG. 43].

C. The third source of code-address information is the Masked Bus 2011, the contents of which are gated to the Program Address Register 4801 via cable 4313, AND gate 4308, and OR gate 4808 at time 3T5 by enabling order cable conductor MBPA [FIG. 43]. This path is employed in the case of interrupts to gate code-address words to the Program Address Register 4801 from the Interrupt Address Source 3411 and is also employed on early transfer orders to gate the contents of the J Register 5802 or the Z Register 3002 to the Program Address Register 4801.

The transmittal of commands from the Central Control 101 to the Program Store 102 and the transmittal of the program store responses to the Central Control 101 may be understood by reference to FIG. 84. In FIG. 84 the three horizontal lines represent functions which occur with respect to arbitrary orders X-1, X, and X+1, respectively. A machine cycle, as employed in the time scale of this figure, comprises a 5.5-microsecond period of time. A portion of an arbitrary cycle 1 and all of the following cycles 2 and 3 are shown. As seen in FIG. 84, the period of time between the transmission of the command to the Program Store 102 and the completion of the operational step associated with that command require greater than one 5.5-microsecond machine cycle. However, also as seen in FIG. 84, there are work functions relating to three separate orders being simultaneously performed; therefore, it is possible to complete single cycle orders at the rate of one order per 5.5-microsecond cycle.

At line X of FIG. 84 the code-address of order X is shown as being transmitted to the Program Store 102 during phase 1 of cycle 1 and the program store response thereto returned to the Central Control 101 sometime during the latter portion of cycle 1 or the early portion of cycle 2. The program store response comprises parallel 1/2-microsecond pulses which represent the 44-bit program order word, the response synchronizing signal and the All Seems Well signal.

The exact time at which the program store response arrives at the Central Control 101 depends on central control response times, the lengths of the buses connecting the Central Control 101 and the Program Store 102 and the variations in the response times of the program stores of the Program Store System 102. These variations can result in the program store response arriving at the Central Control 101 as early as T19 of the same cycle in which the program store command was transmitted or as late as T6 of the following cycle. Accordingly, the Program Store Response Bus Selection Gates 1200 are activated by order cable signals on conductors PSB0 and PSB1 [FIG. 12] in the period 19T8. This assures the acceptance of the full pulse width (approximately 0.5 microseconds) of the program store response. The Program Store Response Bus Selection Gates 1200 are selectively enabled to accept the response from the "0" bus 6500-0 or from the "1" bus 6500-1 of the Program Store Response Bus System 6500. The particular gates enabled are determined in accordance with the setting of the CPD controlled status and routing flip-flops, as enumerated in the earlier table. If the response is to be accepted over the "0" bus 6500-0, the AND gates 1204, 1206, and 1208 are enabled by a signal on order cable conductor PSB0 and if the response from the "1" bus 6500-1 is to be accepted, the AND gates 1203, 1205, and 1207 are enabled by a signal on order cable conductor PSB1.

The 44-bit response word is transmitted through OR gate 1209 and cable 1210 for insertion in the Auxiliary Buffer Order Word Register 1901 and the Buffer Order Word Register 2410. Bits 0 through 20 (the data-address field) and bits 37 through 43 (the Hamming encoding bits) are gated directly into the Buffer Order Word Register 2410 via AND gates 1907 and 1906, and OR gates 2428 and 2425, respectively. Bits 21 through 36 (the operation field) are inserted into the Auxiliary Buffer Order Word Register 1901 via AND gate 1905. The synchronizing signal is transmitted through OR gate 1211 and is employed to enable AND gates 1905, 1906, and 1907 which serve to gate the received 44-bit word to the Auxiliary Buffer Order Word Register 1901 and the Buffer Order Word Register 2410.

The All Seems Well signal, if received from the "0" bus 6500-0, serves to set flip-flop 1214 to its "1" state and if received from the "1" bus 6500-1, sets the flip-flop 1213 to its "1" state. The flip-flops 1213 and 1214 comprise two of the inputs to the Error Detection and Correction Circuit 2400. Failure to receive an All Seems Well signal along with a program store response is an indication of possible trouble within the Program Store 102 therefore the validity of the response is in question. The All Seems Well signals summarize a number of hardware checks made within the Program Store 102, and the utilization of the All Seems Well signal as a maintenance tool is discussed later herein.

The data-address field and the Hamming encoding bits are gated directly to the Buffer Order Word Register 2410 as the portions of the register which are employed to store this information are no longer required by the immediately preceding order; however, the work operations with respect to the operation field of the preceding order may not have been completed by the time the program store response has arrived at the Central Control 101. Therefore the operation field is first inserted into the Auxiliary Buffer Order Word Register 1901 and then at time 6T8 by means of signal on order cable conductor AUB0 [FIG. 19] is gated via AND gate 1900, cable 1903 and OR gates 2426, and 2427 to the Buffer Order Word Register 2410.

The information which is received both by the Auxiliary Buffer Order Word Register 1901 and the Buffer Order Word Register 2410 is on a single rail basis; therefore, both the Auxiliary Buffer Order Word Register 1901 and all of the portions 2401, 2402, 2403 of the Buffer Order Word Register 2410 are selectively reset prior to the time of the inserting of new information. A signal on order cable conductor REBB [FIG. 24] at time 19T20 serves to reset the data address portion 2403 and the Hamming portion 2401 of the Buffer Order Word Register 2410 and to reset the Auxiliary Buffer Order Word Register 1901. An order cable signal on conductor REBA [FIG. 24] at time 3T5 serves to reset the operation field 2402 of the Buffer Order Word Register 2410.

In a few special instances (principally in the course of maintenance actions) a transfer may be made to one of a number of short sequences of program orders which are located in the Call Store 103. The program sequences in the Call Store 103 may be reached through a system interrupt or through a transfer. In either event, the call store code-address corresponding to the first program order word of the sequence is gated into the Index Adder Output Register 3401 and from there to the Call Store Transmit Bus Selection Gates 1000. The detailed control of the call store bus selection gates will be described with respect to the reading and writing of data from and into the Call Store 103. The call store, in response to a program order command, returns a twenty-three bit reading to the Central Control 101 via the Call Store Response Bus System 6501. This response is gated through the Call Store Response Bus Selection Gates 1300 to the Buffer Order Word Register 2410.

The Call Store 103 returns approximately one-half of a program order word with a single reading. Therefore, two successive call store locations must be read. Conveniently, the Program Address Register 4801 and the add-one circuit comprising the Add-One Register 4304 and the Add-One Logic 4305 are employed to obtain the second code-address and subsequently the code-addresses for the following program order words to be obtained from a Call Store 103. To provide protection against an unwanted response from a Program Store 102 the call store code-addresses are not gated from the Program Address Register 4801 to the Program Store Address Bus System 6400.

The first call store word of a pair of words comprising a program order word is transmitted from OR gate 1309 via cable 1310, the right AND gate 1909, cable 1913 and the OR gates 2427 and 2428 to bits 22 through 0 of the Buffer Order Word Register 2410. The second call store word of the pair is transmitted from the OR gate 1309 via cable 1310, the left AND gate 1910, cable 1912 and the OR gates 2425 and 2426 to the bits 43 through 23 of the Buffer Order Word Register 2410. The reading of program order words from the Call Store 103 is most unusual. Two successive readings are required to obtain a single program order word. Therefore, the fetching of program order words from the Call Store 103 is under the control of the Call Store Program Sequencer 5302 which is described in greater detail later herein. It should be noted that Call Store Program order word responses are gated directly to the Buffer Order Word Register 2410 and not via the Auxiliary Buffer Order Word Register 1901. This simplification is permissible since the code-addresses for the next succeeding order are not transmitted until after the operational step for the preceding order has been completed.

Data Words

As previously described, a large body of information organized as data words as opposed to program order words is stored principally in the Call Store 103 and the Program Store 102. the more volatile information is stored principally in the Call Store 103, while the more stable information is stored in the Program Store 102. Additionally, maintenance data which is stored internally in the control and access circuits of the Program Store 102, the Call Store 103, and the standby central control is treated as data for purposes of communication.

Data words may be read from a memory location or written into a memory location by the execution of program orders termed "memory orders." Included in this term are "memory read orders" and "memory write orders." Memory orders cause the generation and transmission of commands to the various memory locations as follows:

Read Write Memory Command Command ____________________________________________________________ ______________ Call Store 103 Memory Proper X X Control and access X X Program Store 102 Memory Proper X -- Control and access X X Standby Central Control 101 -- X Auxiliary Buffer Registers X X ____________________________________________________________ ______________

the above table shows that both memory read and memory write commands apply to many of the data memories; however; memory write commands cannot be employed with respect to the memory proper of the Program Store 102 nor can memory read commands be employed with respect to the standby Central Control 101.

Call Store Memory Orders

Memory reading (writing orders which obtain (store) data from the Call Store 103 include call store reading (writing) commands as part of their operational step. The operational step of such orders is indicated by the example of order X in FIG. 84; in that example call store commands are generated and transmitted during phase 3 of the indexing cycle. If X is a memory reading order, the call store response will be transmitted from the Call Store 103 to the Data Buffer Register 2601 during phase 1 of the execution cycle; if X is a memory writing order, the word to be stored is transmitted from the Data Buffer Register 2601 to the Call Store 103 during phase 1 of the execution cycle. Call store commands are also generated for multicycle orders under control of sequence circuits, but the command and data generation and transmission have the same format and relative time sequence as described below.

A call store command comprises:

A. 12 address bits A0 through A11

B. Six code bits K0 through K5

C. Three mode bits HM, GM, CM

D. A first synchronizing bit Sync 1

E. Two order bits R and W

F. One address parity bit

G. A second synchronizing bit Sync 2.

The code bits K0 through K5 define the block of information in which the selected call store data word is located and the address bits A0 through A11 define the memory location within the above defined block of information. The code bits K0 through K5 and the address bits A0 through A11 comprise the call store code-address. The three mode bits specify the mode of operation of the Call Store 103 and the order bits specify whether the command is to read or to write. It should be noted that the Call Store 103 is always operated in the normal mode in the execution of memory read and memory write commands relating to call processing. The maintenance read and write commands and the control read and write commands are reserved for obtaining information from the Call Store 103 and writing into the Call Store 103 in the execution of special memory read and memory write orders relating to system maintenance. Pulses on the leads HM, GM, and CM specify the mode of operation of the Call Store 103 as follows:

HM GM CM Mode 0 0 0 Normal 0 1 1 H Maintenance 1 0 1 G Maintenance 1 1 0 Control

Pulses on the R and W conductors specify that the order is a call store read command or a call store write command, respectively.

The twelve address bits A0 through A11, the six code bits K0 through K5, and the address parity bit comprise a nineteen bit segment of the command in which odd parity is maintained.

The first synchronizing signal Sync 1 accompanies the address, code, and mode bits and the second synchronizing signal Sync 2 accompanies the information on the R, W, and parity conductors. The synchronizing pulse S1 and S2 are employed as gating signals at the Call Store 103 and serve to reduce the time during which the Call Store 103 is vulnerable to noise signals on its command buses.

The execution of memory orders by Central Control 101 to move data words between the Call Store 103 and the Central Control 101 is initiated by the transmission of call store commands from Central Control 101 to the Call Store 103 via the Call Store Address Bus System 6401. If the command is to write a data word into the Call Store 103, then the command is followed by the transmission of the data word via the Call Store Write Data Bus System 6402. If the command is to read a data word, then the call store read command is followed by the transmission of the data word from the Call Store 103 to Central Control 101 via the Call Store Response Bus System 6501.

In executing a call store command the code-address is always composed in the Index Adder Output Register 3401 which is connected to the Call Store Transmit Bus Selection Gates 1000 via the cable 3402. Bits 17 through 12 of the index adder output register comprise the code portion of the command and bits 11 through 0 comprise the address portion of the command. The three mode bits, the synchronizing bits, and the read-write bits are all obtained from the Order Cable 3900. The three mode bits are required to be selectively other than zero in all modes other than the normal mode and in these modes the mode bits are defined by the program order word being executed. In all mode of operation the read and write bits and the synchronizing bits are also obtained from the Order Cable 3900 according to the call store command required.

The parity signal generated as part of the call store command is generated in the Index Adder Parity Generator 2415 in response to the code-address appearing at the outputs of the Index Adder Output Register 3401 and transmitted thereto via the cable 3402.

The Call Store Transmit Bus Selection Gates 1000 are divided into two groups, namely, those employed for transmitting to the "0" bus 1004 of the Call Store Address Bus System 6401 and those associated with the "1" bus 1003 of the Call Store Address Bus System 6401. The command information is selectively transmitted to the "0" bus 1004 or the "1" bus 1003 in accordance with the Call Store 103-Central Control 101 bus configuration which is being employed. That is, whenever information is being transmitted from the Central Control 101 to the Call Store 103 via the "0" bus 1004, AND gates 1006, 1008, 1012, 1014, and 1016 and amplifiers 1010, 1018 are employed; however, when commands are transmitted via the "1" bus 1003, AND gates 1005, 1007, 1011, 1013 and 1015 and amplifiers 1009 and 1017 are employed. The address bits A0 through A11 and the code bits K0 through K5 are selectively transmitted through AND gates 1016 and 1015 enabling order cable conductors ADRCSB0 and ADRCSB1 [FIG. 10], respectively. Similarly, the mode bits HM, GM, and CM and the first of the two synchronizing pulses S1 are transmitted to the "0" and "1" buses under the control of the same order cable conductors. It should be noted that the order cable conductors ADRCSB0 and ADRCSB1 are enabled at time 17T19. Order cable conductors RWCSB0 and RWCSB1 are enabled at time 19T21 and serve to gate the READ, the WRITE, the ADDRESS PARITY and SYNC 2 pulses to their respective buses.

The Call Store Transmit Bus Selection Gates 1000 are selectively enabled in accordance with the setting of the central pulse distributor controlled status and routing register flip-flops AU, CBO, CBA, and CBT [FIG. 55]. The state of flip-flop AU indicates which of the two central controls is active. The flip-flops CBO, CBA, and CBT (except for commands to read or write maintenance data) have the following significance: ##SPC2##

In the above table the X indicates that the standby CC is to send on neither the "0" nor the "1" bus as the active CC is engaged in transmitting to both buses.

The status and routing flip-flops AU, CBO, CBA, CBT are selectively set and reset by pulses from the Central Pulse Distributor 143 which are received via selected pairs of the Bipolar Cable 6700, the transformer 1707, amplifiers 1708 and 1711, AND gates 1709 and 1712, and the CPD cable 1719.

Call Store Writing Commands

A call store writing command utilizes as data to be stored a 23-bit word in the Data Buffer Register 2601. The outputs of the Data Buffer Register 2601 are transmitted via the cable 2606 to the Call Store Write Data Bus Selection Gates 1020, and from there to the selected one, or both, of the duplicated buses of the Call Store Write Data Bus System 6402. The selection of the "0" bus or the "1" bus for the transmission of data is determined by the appearance of signals on the order leads BRCSB0 AND BRCSB1 [FIG. 10]. The selection of signals on one, or both, of BRCSB0 and BRCSB1 is determined by the setting of the CPD controlled status and routing flip-flops as enumerated in the send column of the earlier table. In the execution of the call store command to write data into the memory signals appear on one or both, of BRCSB0 or BRCSB1 during 5T7 following the transmission of the initial parts of the call store command onto the Call Store Address Bus System 6401. Accordingly, a synchronizing signal, S3, is transmitted via the amplifiers 1024 or 1023, and the 23-bit data word is transmitted via the AND gates 1028 or 1027, and a data parity signal is transmitted via the AND gates 1026 or 1025.

The D A Parity Generator (2609)

The 12 address bits A0 through A11, the six code bits K0 through K5, the 23-bit data word D0 through D22, and the data parity bit comprise a 42-bit command segment in which odd parity is maintained. The signal on the conductor D A PARITY [FIG. 26] is generated by the D A Parity Generator 2609 as required to maintain odd parity for call store writing commands. The Index Adder Parity Generator 2415 serves to examine the eighteen bit segment of the command which comprises the twelve address bits and the six code bits and provides an appropriate output signal on conductor 2418. If the parity of the code-address bits at the input of the Index Adder Parity Generator 2415 are even, a signal will appear on conductor 2418; however, if the parity of these bits is odd, there will be no signal on conductor 2418. Conductor 2418 thus serves to summarize the parity of the code-address bits and is employed as an input signal to the D A Parity Generator 2609 along with the data bits at the output of the Data Buffer Register 2601. All 24 bits of the Data Buffer Register 2601, that is, bits 0 through 23, are connected to the input of the D A Parity Generator 2609; however, the 24th bit which appears in the Data Buffer Register 2601 is always a zero as stage 23 is reset at time 21T1 by enabling cable conductor REBRP [FIG. 26]. Summarizing, in executing a call store writing command the D A Parity Generator 2609 provides the data parity signal on conductor D A PARITY which is transmitted along with the data from the output of the Data Buffer Register 2601 via cable 2606 to the Call Store Write Data Bus Selection Gates 1020.

The D A Parity Generator 2609 is also employed in the execution of call store reading commands which either (1) obtain a data word and store that word in the Data Buffer Register 2601, or (2) obtain a transfer code-address which is placed in the Buffer Order Word Register 2410. In the case of indirect addressing bits 0 through 22 of the Buffer Order Word Register 2410 and the state of the Parity Flip-Flop 1911 are employed as the input signals to the D A Parity Generator 2609. An order cable signal on conductor CSDACK [FIG. 26] serves to substitute these conductors for the contents of the Data Buffer Register 2601. In checking a call store response for data readings the contents of the Data Buffer Register 2601 serve as the input information to the D A Parity Generator 2609.

All Seems Well Signals

In response to call store commands (both reading and writing), the Call Store 103 executes the command and, upon the successful completion of the execution responds by transmitting All Seems Well and synchronizing signals via the Call Store Response Bus System 6501 to Central Control 101. These signals are transmitted via Cable Receivers 1302 and 1301 (according to their appearance on the "0" bus 6501-0 or "1" bus 6501.varies.1, respectively) to conductors SYNC0, AWS0, and SYNC1 and ASW1 [FIG. 13]. The synchronizing and All Seems Well signals appearing at the inputs of AND gates 1308 and 1307 generate corresponding signals to set the flip-flops 1314 and 1313. Since the All Seems Well and the synchronizing signals are provided on a single rail basis, these flip-flops are previously reset in preparation by enabling order cable conductor RECER. The All Seems Well signals summarize a number of hardware checks which are made within the Call Store 103; the utilization of these signals as a maintenance tool is discussed later herein.

Call Store Reading Commands

In the execution of call store reading commands the response includes a twenty-four bit word of data, an All Seems Well signal, and a synchronizing signal appearing as 1/2-microsecond pulses on the Call Store Response Bus System 6501. The 24-bit word includes 23 bits of information to be utilized for data processing within Central Control 101 and a data parity bit. The call store response signals appear in parallel at the input terminals of the Call Store Response Bus Selection Gates 1300. The Call Store Response Bus Selection Gates 1300 are selectively enabled to accept the response from the "0" bus 6501-0 or from the "1" bus 6501-1, and the gates enabled are determined in accordance with the setting of the CPD control status and routing flip-flops as enumerated in the earlier table. If the response is to be accepted from the "0" bus 6501-0, the AND gates 1304 and 1306 are enabled by a signal on order cable conductor CSB0 and if the response from the "1" bus 6501-1 is to be accepted, the AND gates 1303 and 1305 are enabled by a signal on conductor CSB1.

Signals on order cable conductors CSB0 and CSB1 occur at time 0T11.

In FIG. 84 it is indicated that within Central Control 101 the data processing of reading from a memory other than a Program Store 102 occurs in phase 2 during the execution cycle and with the Call Store Response Bus Selection Gates 1300 enabled for the time 0T11 the call store response is returned prior to this time, that is, it is returned during phase 1 during the execution cycle. It should be noted that the Call Store Response Bus Selection Gates 1300 are enabled for a period of time which greatly exceeds the period, i.e., one-half microsecond of the call store response signals. This greater period of time permits acceptance of the full pulse width (approximately 0.5 microseconds) of the call store bus response signals without regard for variations in time of response of the Call Store 103 and variations in length of cable connecting the Call Store 103 and the Central Control 101.

The 24-bit response word is transmitted through OR gate 1309, cable 1310, and AND gate 2102. The synchronizing signal is similarly transmitted to AND gate 2102. When the call store response is to be placed in the Data Buffer Register 2601 the gating of data readings from the Call Store Response Bus System 6501 via AND gate 2102 and OR gate 2106 is controlled by enabling order cable conductor CSBR [FIG. 21].

The information which is received both by the Data Buffer Register 2601 and the special flip-flops 1313 and 1314 is on a single rail basis; therefore, the Data Buffer Register 2601 and the special flip-flops 1313 and 1314 are reset prior to the time at which the information is received. Enabling order cable conductors REBR and REBRP [FIG. 26] resets the Data Buffer Register 2601, and a signal appearing on the order cable conductor RECER resets the special flip-flops 1313 and 1314. Both of these signals occur during 0T1 prior to the receipt of information from the Call Store Response Bus System 6501.

Call Store Error Detection Circuit 2200

In Call Store performance of obtaining data from the Call Store 103 for memory reading orders the D A Parity Generator 2609 is utilized to check the parity of the data received and the address transmitted to obtain that data. The state of conductor 2418 indicates the parity of the eighteen bit code-address, and the contents of the Data Buffer Register 2601 including the 24th bit comprise the remaining inputs to the D A Parity Generator 2609. The parity of the returned data and the address which was employed in obtaining that data should be odd. In the event of failure of parity, a signal on the PF conductor 2607 is transmitted to the Call Store Error Detection Circuit 2200.

The Call Store Error Detection Circuit 2200 serves to summarize the hardware checks which are made in carrying out call store commands. The input signals to the Call Store Error Detection Circuit 2200 comprise the call store synchronizing signal conductors CSS1 and CSS0 [FIG. 13], the call store All Seems Well conductors ASWCS0 and ASWCS1 [FIG. 13], the Parity Failure conductor 2607 and order cable conductor CSCK, and READCK [FIG. 22]. The Call Store Error Detection Circuit 2200 is enabled by a signal on order cable conductor CSCK and if the parity check of a data reading is to be made order cable conductor READCK [FIG. 22] is also enabled. If one or more of the hardware checks enumerated above fails, the Call Store Error Detection Circuit 2200 enables output conductor CERI [FIG. 22]. A signal on conductor CERI sets the CSEI flip-flop 2201 which in turn activates the Call Store Reread Sequencer 5700, the operation of which will be described later herein. The AND gate 2700 is enabled by a signal on order cable conductor CSX [FIG. 27] and serves to transmit to the other central control the error indication on conductor CERI. The Call Store Error Detection Circuit 2200 is enabled for normal call store memory commands; it is not enabled for maintenance and control read and write commands.

Program Store Memory Orders

Memory reading orders may also address memory locations within the Program Store 102. In such instances the indexing step produce a code-address corresponding to a program store memory location to be read. Memory reading orders for obtaining data from a Program Store 102 utilize the same channels for addressing the store and for receiving the response employed in obtaining program order words. When data is to be read from a Program Store 102 the Data Reading Sequencer 4903 is activated. The sequencer is required since the obtaining of data from a Program Store 102 must be interleaved with the obtaining of program order words. Accordingly, this sequencer responds by storing the code-address of the next program order word temporarily in the Add-One Register 4304 and placing into the Program Address Register 4801 the data code-address by gating the outputs of the Index Adder Output Register 3401 thereto. The Data Reading Sequencer 4903 extends the processing time of a memory reading order by two 5.5-microsecond cycles. These two cycles are inserted in the operational step as set forth in FIG. 84 at the end of the indexing cycle and before the execution cycle. In the first cycle injected by the Data Reading Sequencer 4903 the order following the memory reading order is ignored and the data code-address is transmitted to the Program Address Register 4801. From there this code-address is transmitted as part of a program store command onto the Program Store Address Bus System 6400. In the second machine cycle injected by the Data Reading Sequencer 4903 the data reading is returned from the Program Store 102 via the Program Store Response Bus System 6500 to the Buffer Order Word Register 2410. From there a selected half of the 44-bit data reading is transmitted to the Data Buffer Register 2601, the selected half determined by bit 20 of the code-address formed in the indexing step of the order. When these functions are completed the Data Reading Sequencer 4903 is returned to the inactive state, and the memory reading order proceeds to its execution cycle wherein the data (now appearing in the Data Buffer Register 2601) is utilized to complete the operational step.

Auxiliary Buffer Register Memory Orders

Memory reading and writing orders may also address a selected one of the auxiliary buffer registers such as DR0 (3118), AR0 (3105) [FIG. 31], DR1 (3617) [FIG. 36], et cetera. In such instances the DAR word is a code-address corresponding to the selected one of the auxiliary buffer registers. This code-address appears in the Index Adder Output Register 3401 and is utilized to transmit data from the Data Buffer Register 2601 to a selected one of the auxiliary buffer registers for memory writing orders or to transmit data from a selected one of the auxiliary buffer registers to the Data Buffer Register 2601 for memory reading orders.

A memory reading order which addresses a selected one of the auxiliary buffer registers selects by means of a signal appearing on one of the order cable leads AR0-BR, DR0-BR [FIG. 31], AR1-BR [FIG. 36], et cetera, to transmit the contents of a selected one of the auxiliary buffer registers via the AND gates 3108, 3120, 3608, et cetera, via the Buffer Register Input Bus 3209 and the OR gate 2106 to the inputs of the Data Buffer Register 2601. This gating action occurs during 0T8 (phase 1) of the execution cycle.

Memory writing orders which place data into a selected one of the auxiliary buffer registers utilize the contents of the Index Adder Output Register 3401 to generate a signal on a selected one of the order leads BR-AR0, BR-DR0, BR-AR1, et cetera, to transmit the contents of the selected one of the registers via the Data Buffer Register 2601 and the Buffer Register Output Bus 2600 to a selected one of the AND gates 3103, 3116, 3601, et cetera, to the inputs of the selected one of the auxiliary buffer registers AR0, DR0, AR1, et cetera. In that certain of the auxiliary buffer registers 3105, 3118, 3605, and 3617, have a 24-bit capacity as opposed to the 23-bit length of data words as processed within Central Control 101, the additional bit is provided in one of the bits of the indexed code-address as it appears in the Index Adder Output Register 3401.

The address which selects the particular auxiliary buffer register for reading or writing appears in bit positions 1 through 5 of the Index Adder Output Register 3401 during the execution of the memory order. When a memory writing order specifies a 24-bit auxiliary buffer register, then bit 0 of the code-address appearing in the Index Adder Output Register 3401 serves a the 24th bit of data. Order cable conductor 23 or 23 of cable 2611 is enabled according to contents of the least significant bit of the Index Adder Output Register 3401 thereby supplying the 24th bit of data on the Buffer Register Output Bus 2600. The 24th bit of this bus is transmitted whenever a memory writing order specifies one of the Match Registers AR0, AR1, DR0 and DR1 [FIGS. 31,36].

Memory writing orders which place data into a selected one of the auxiliary buffer registers utilize the contents of the Index Adder Output Register 3401 to generate a signal on a selected one of the order leads BR-AR0, BR-DR0, BR-AR1, et cetera, to transmit the contents of bits 0 through 22 of the Data Buffer Register 2601 via the cable 2600 to a selected one of the AND gates 3103, 3116, 3601, et cetera, to the inputs of the selected one of the auxiliary buffer registers AR0 3105, DR0 3118, AR1 3605, et cetera.

Communication Via Command Orders

The third major class of communication involves the generation and transmission of "commands" to the Central Pulse Distributor 143, the Switching Network 120, the Master Scanner 144, et cetera. These commands are employed in controlling the noted units in the performance of both telephone and maintenance functions.

The Central Control 101 utilizes program orders designated herein as "command" orders to generate such commands. Certain of these orders generate commands to be transmitted only to the Central Pulse Distributor 143; these orders are designated herein as "CPD orders" and the commands associated with these orders are designated as "CPD commands." Other command orders generate information on the Network Command Bus 6406; these are designated as "network command orders" and the generation of information on the Network Command Bus 6406 is designated herein as "network commands." Network command orders are utilized to transmit information to not only the Switching Network 120 but to all units connected to the Central Control 101 via the Network Command Bus 6406 such as the Master Scanner 144, the Teletype Unit 145, et cetera. For convenience these units which are controlled by way of the Network Command Bus System 6406 are termed "Network Command Units" herein. The network command order employs the CPD command to designate a particular network command unit which is to respond to the network command.

In that the Central Pulse Distributor 143 is employed in the execution of both CPD orders and network command orders, communication with the Central Pulse Distributor 143 will be described first. The Central Pulse Distributor 143 is a high speed electronic translator which provides two classes of output signals in response to CPD commands. The first class of output signals is termed unipolar signals and the second class is termed bipolar signals. Commands are transmitted from the Central Control 101 to the Central Pulse Distributor 143 in the form of half microsecond pulses. The information required to control a Central Pulse Distributor 143 is transmitted in three successive waves which are each separated by 1.25 microseconds. The bus choice information which indicates that the central pulse distributors are to accept information from either the "0" or "1" bus of the CPD Address Bus System 6403 is transmitted in the first wave to all central pulse distributors via the CPD Bus Choice Bus 6405. This bus choice information is determined by the state of flip-flops CPDB [FIG. 59] and OL1 [FIG. 55] as described subsequently herein. The second wave consists of the CPD address transmitted on a selected "0" or "1" bus of the CPD Address Bus System 6403 to all central pulse distributors. The CPD address consists of signals which are to be translated by the Central Pulse Distributor 143 into a half microsecond output pulse appearing on a selected unipolar or bipolar output. The third wave consists of a half microsecond execute pulse transmitted on one of a plurality of cable pair in the Execute Cable 6404. Corresponding to each cable pair in the execute cable is a discrete unit of the Central Pulse Distributor 143, and the execute pulse serve to select the unit which is to carry out the translation of the CPD address signals. The central pulse distributor units which do not receive the execute pulse do not carry out this translation, and the third wave serves thereby as part of the translation of the coded data within Central Control 101 into a pulse appearing on selected discrete unipolar or bipolar output of the Central Pulse Distributor 143.

The operational step of command orders includes the information of data to specify the CPD address, the CPD execute signal, and/or the network command information. If, for example, the order X in FIG. 84 is a command order, the data is placed in the appropriate flip-flop registers within Central Control 101 during phase 2 of cycle 3, and accordingly the second and third wave information is generated only after this data is so registered. The generation of the three waves of CPD command information for the order X is correspondingly generated during 10T12, 15T17, and 20T22 of cycle 3.

The Central Pulse Distributor 143 in executing commands returns responses to the Central Control 101 as half microsecond pulses; the time of arrival of these pulses at Central Control 101 is dependent on the response time of the Central Pulse Distributor 143 and the lengths of the buses connecting the Central Control 101 and the Central Pulse Distributor 143. In the example of FIG. 84 gating signals lasting from T19 of cycle 3 until T12 of cycle 4 (a 3.75-microsecond span) are employed to gate these responses of the Central Pulse Distributor 143. It may be noted that this last gating action as well as the transmission of the second and third wave of the CPD command are generated after the order X has been replaced by the orders X+1 and X+2 in the Central Control 101; the Command Order Sequencer 4902 is therefore activated in the execution of the order X to carry out those gating actions.

If the order X is a network command order, the Command Order Sequencer 4902 is also employed to carry out the gating actions associated with the CPD command, and further the gating actions associated with the transmission of address information to the network command bus. In the execution of network command orders the network command unit returns responses to the Central Control 101 within a span of time that may extend to T5 of cycle 5. Accordingly, the Command Order Sequencer 4902 remains active to carry out all of the gating actions of the network command order which may extend to the end of phase 1 of cycle 5. It is with the aid of the Command Order Sequencer 4902 that the Central Control 101 extends the degree of overlap beyond that exhibited in FIG. 84. If the order X is a network command order, then gating actions associated with the operational step of order X will be simultaneously occurring with the execution cycle of the order X+2, at the time the order X+3 is arriving at the Buffer Order Word Register 2410, and at the time the address of the order X+4 is being transmitted on the Program Store Address Bus System 6400.

CPD Command Gating Actions

The choice of the "0" or "1" of the CPD address bus system is made according to the state of special flip-flops CPDB [FIG. 59] and OL1 [FIG. 55] within the Central Control 101. These flip-flops are set and reset under control of program sequences to indicate the routing of CPD address information as indicated in the following table:

CPDB OL1 Active CC Sends Standby CC Sends ____________________________________________________________ ______________ 0 0 0 x 0 1 X 0 1 0 1 X 1 1 X 1 ____________________________________________________________ ______________

in the above table the entry X indicates that the command is transmitted on neither bus. According to the choice of bus, signals appear on one of the order cable conductors BC0 or BC1 [FIG. 38] during 10T12 and are transmitted via the Cable Driver 3801 to the Bus Choice Bus 6405.

Signals to select a unipolar or bipolar output (the CPD address) are generated either by the CPD translator 5422 in response to the binary representation of the CPD address appearing in a portion of the First-One Register 5801 or (according to the command order) the CPD address is generated directly from outputs of portions of the K Register 4001 and the K A Input Register 3502. The CPD translator 5422 is employed in most instances; the outputs of the K Register 4001 and the K A Input Register 3502 are used in transmitting special test or control signals to the Central Pulse Distributor 143.

A signal appearing on the order cable lead CPDA [FIG. 54] causes the CPD translator 5422 to generate the CPD address on the output conductors 5425 which is transmitted to the OR gate 4004 onto a second bus 4005 and from there to the input of the CPD Transmit Bus Selection Gates 3812. The CPD address is in this instance determined by the contents of bit positions 9, 14-22 of the First-One Register 5801 which are transmitted to the CPD translator via connecting cable 5810. Here the "bus choice" is implemented by the appearance of a signal on AOB or A1B [FIG. 38] during 15T17 to transmit the CPD address via the AND gates 3814 and 3815 and the Cable Driver 3802 to the "0" bus 3804 or via the AND gates 3816 and 3817 and the Cable Driver 3803 to the "1" bus 3805.

A signal appearing on the order cable conductor 38I0 and signal appearing on the output conductors 7, 8 and 9 of the First-One Register 5801 indicates the alternative of deriving the CPD address or special signal TEST or RESET [FIG. 38] from information contained in portions of the K Register 4001 and the K A Input Register 3502. The outputs of the K Register 4001 and the K A Input Register 3502 are gated via the buses 4006 and 3519, the AND gates 4002 and 4003 (and in part via the OR gate 4004) to the bus 4005. From there the gating of the CPD address TEST and RESET signals to the CPD Address Bus System 6403 is as previously described.

The third wave of information is generated by the appearance of a signal on CPDX [FIG. 54] during 20T22; the execute signal appears on one of the conductors 5426 according to the contents of bit positions 10 through 13 of the F Register 5801. The execute signal is transmitted via the conductors 5426 and the Cable Driver 3800 to the CPD Execute Cable 6404.

In the execution of CPD commands the bipolar output signals are in some instance accompanied by a synchronizing security signal (WRMI). In such instances the CPD command utilizes the outputs of the CPD translator 5422 and the appearance of the synchronizing security signal is specified by the appearance of a "1[ in bit position 8 of the First-One Register 5801. If the synchronizing security signal is so specified, a pulse appears during 20T22 on order cable conductor CPD INPUT SYNC [FIG. 38] and is transmitted through the Cable Driver 3806 and 3807 to both the "0" 3808 and the "1" bus 3809 of the CPD Input Sync Bus System 6702.

In response to the bus choice, CPD address, and execute signals the Central Pulse Distributor 143 generates an output pulse on the selected unipolar or bipolar output point. In addition, the Central Pulse Distributor 143 generates maintenance signals that are transmitted to the Central Control 101 to permit a check on the execution of the CPD command. These signals comprise the execute response signals transmitted via the Execute Response Bus System 6502, an A11 Seems Well signal transmitted via the CPD Verify Bus System 6704, and CPD maintenance signals transmitted via the CPD Maintenance Response Bus 6904.

The execute response signals appear as half microsecond pulses on the Execute Response Bus 6502 and are transmitted through the Cable Pulse Receivers 1600. Signals appearing on the order cable conductor CPDEW [FIG. 16] during 19T12 (a Seems Well 3.75-microsecond interval from time T19 of one machine cycle to time T12 of the following machine cycle) transmit the execute response through AND gate 1601 to the CPD Execute Response Cable 1605 and the set inputs of bit positions 0 through 15 of the Command Order Maintenance Summary Register 6205. The All Seems Well signal is returned to the Central Control 101 via the "0" bus or "1" bus of the CPD Verify Bus Stem 6704 and the Cable Receivers 1502 or 1501. A signal appearing on CPDEW [FIG. 15] serves to transmit these All Seems Well signals through the AND gates 1506 and 1505 and the OR gate 1509 of the CPD Verify Bus Selection Gates 1500 to conductor 1510 of the Error Summary Cable 1218. The further appearance of the same signal on order cable conductor CPDEW [FIG. 62] transmits the All Seems Well signal from the Error Summary Cable 1218 and the bus 6200 through the AND gate 6203 to the set input of the flip-flop 62ASW CPD.

The maintenance response of a Central Pulse Distributor 143, appearing as the signals APAR, BPAR, CPAR, and M1 [FIG. 16], is returned via the CPD Maintenance Response Bus 6904 and the Cable Receiver 1603 to the Error Summary Cable 1218. From there these signals are transmitted as previously described to the set inputs of the flip-flops PCA, PCB, PCC, and MCE, respectively.

The execute response signals, the All Seems Well signals, et cetera, appear on the Error Summary Cable 1218 and the CPD Execute Response Cable 1605 as single rail half microsecond pulses sometime within the previously defined 3.75-microsecond interval 19T12. Accordingly, bits 0 through 21 of the Command Order Maintenance Summary Register 6205 are reset prior to this interval by the appearance of a signal on the order cable conductor RCPD [FIG. 62] during 17T19.

CPD Command Hardware Checks

In the execution of CPD commands the proper response of the Central Pulse Distributor 143 includes the transmitting of the All Seems Well signal to Central Control 101 and the transmission of execute response signals which match the execute signals sent in the third wave of the CPD command. Accordingly, the command order sequencer interrogates the flip-flop ASW CPD [FIG. 62] and the output of the Execute Match Circuit 5033 sometime after the 3.75 microsecond interval 19T12 in which the execute response and All Seems Well information appear. The Execute Match Circuit 5033 compares the signals appearing on the conductors 5424 (the execute signals appearing at the output of the CPD translator 5422) and the signals appearing on conductor 6210 (the execute response as registered in bits 0 through 15 of the Command Order Maintenance Summary Register 6205). If a match occurs, a signal appears on the conductor EXM [FIG. 50], and if the All Seems Well signal is returned to Central Control 101, a signal appears on ASW CPD [FIG. 62]. Failure of Signals to appear on these leads causes the Command Order Sequencer 4902 to set the flip-flop PUEI [FIG. 52] which results in ensuing maintenance program designated to determine the nature and location of the trouble.

The response of the Central Pulse Distributor 143 stored in the flip-flops MCE, PCA, PCB, and PCC [FIG. 62] are not examined by the Command Order Sequencer 4902, but serve as additional maintenance information in the event of troubles indicated by improper execute response signals or the failure of the appearance of an All Seems Well signal.

Network Command Gating Actions

The operational step of network command orders include the generation of a network command on cable 3516 and the transmission of these signals through the Network Command Transmit Bus Selection Gates 2800 to the Cable Drivers 2804 and 2805 and the bus "0" 2806 and bus "1" 2807 of the Network Command Bus System 6406. If the order X in FIG. 84 is a network command order, then signals appearing on NCTB0 or NCTB1 [FIG. 28] during 4T6 of cycle 4 (not shown in FIG. 84) transmits the command to the "0" or "1" bus, respectively, of the Network Command Bus System 6406. The selection of the duplicate bus for transmission is controlled by the state of the flip-flops 0L2 [FIG. 55] and bit position 14 of the First-One Register F14 as indicated in the following table: ------------------------------------------------------------ ---------------

550L2 F14 Active CC Send Standby CC Send ____________________________________________________________ ______________ 0 0 0 X 0 1 1 X 1 0 X 0 1 1 X 1 ____________________________________________________________ ______________

in the above table the entry X indicates that the command is transmitted on neither bus.

The network command generated on the cable 3516 is obtained from portions of the contents of either the K A Input Register 3502 or the K Register 4001 and the K A Input Register 3502 depending on the command order being executed and the contents of bit positions 7, 8, and 9 of the First-One Register 5801. That is, according to the combination of signals on 7, 7, 8, 8, 9, and 9 conductors of cable 5811 and the state of order cable conductors IO, FINH, and SR [FIG. 35], the network command is obtained from:

1. Portions of the K A Input Register 3502 via AND gates 3511, 3512 and OR gates 3514, 3515;

2. Portions of the K Register 4001 and the K A Input Register 3502 via AND gates 3513, 3511 and OR gates 3514, 3515; or

3. From portions of the K A Input Register 3502 via the Command Translator 3509 and OR gate 3515.

In the last instance, signals on cable 5811 further select the portion of the K A Input Register 3502 that are translated and the translation to be employed.

Whenever a network command is generated it is simultaneously transmitted to all network command units. The CPD command performed in the execution of a network command order serves to select which of the network command units is to execute the network command. Associated with each of the network command units are distinct unipolar outputs of the Central Pulse distributor 143. A pulse appearing on a selected one of these unipolar outputs causes the corresponding network command unit to execute the transmitted network command. In carrying out this network command certain of the network command units transmit responses to the Central Control 101. These responses may include verify signals transmitted on the CPD Verify Bus System 6704 and data transmitted on the Scanner Answer Bus System 6600. With reference to FIG. 84, if the order X is a network command order, these responses appear as half microsecond signals within a 6.25 microsecond span of time beginning with T4 of cycle 4 and ending with T7 of cycle 5. The time interval is designated herein as 4T29 to emphasize that the time interval is in excess of one machine cycle.

The enable verify signals appear on the "0" bus 6704-0 or "1" bus 6704-1 of the CPD Verify Bus System 6704 and are transmitted via the Cable Receivers 1502 and 1501, respectively, to the CPD Verify Bus Selection Gates 1500. Accordingly, signals appearing on the order cable conductors CPDB0 or CPDB1 [FIG.15] during 4T29 serve to transmit the CPD verify signals through the AND gates 1504 or 1503 and the OR gate 1507 to the cable 1508. Single rail signals appearing on the bus 1508 are thereby transmitted to the set inputs of the Y Register 3001 via the AND gate 3004 and the OR gate 3005. A signal on order cable conductor VBYR [FIG. 30] enables AND gate 3004. The CPD verify signals so placed in the Y Register 3001 must be identical in form to the CPD address appearing on the output leads 5423 of the CPD Translator 5422. The leads 5423 and the outputs of the Y register (transmitted on the cable 3013) are inputs to the Enable Verify Match Circuit 5027. In the performance of network command orders for which the CPD verify signals are to be placed in the Y Register 3001 the Command Order Sequencer 4902 interrogates the output of the Enable Verify Match Circuit 5027 upon the receipt of the CPD verify signals. This interrogation serve as a check on the proper operation of the network command; if improper operation is indicated by a mismatch, this mismatch information appearing on the lead EVM [FIG. 50] is transmitted under control of the Command Order Sequencer 4902 to set the interrupt source flip-flop PUEI [FIG. 52]. The setting of this flip-flop may lead to an ensuing interrupt program designed to determine the circuit trouble causing the detected improper operation.

The selection of the "0" bus or the "1" bus as determined by the appearance of signals on the order cable leads CPDB0 or CPDB1 [FIG. 15] are determined by the state of flip-flop CPDB [FIG. 59]. This flip-flop serves to indicate the state of connections of the CPD Verify Bus System 6704 and indicates that the "0" bus is to be used if the flip-flop is reset, otherwise the "1" bus is to be examined for CPD verify signals.

The operational step of certain of the network command orders results in the returning of data on the Scanner Answer Bus System 6600 to the Central Control 101. In such instances gating signals under the direction of the Command Order Sequencer 4902 transmit scanner answers from the "0" bus 6600-0 or "1" bus 6600-1 through the canner Answer Bus Selection Gates 1400 onto the bus 1408 through the AND gate 2100 to the inputs of the Logic Register 2508. The "0" bus 6600-0 or "1" bus 6600-1 is examined by the appearance of signals on the order cable lead SCA0 or SCA1 [FIG. 14], respectively, during 4T29. The scanner answer is transmitted through the AND gate 1404 or 1403 and the OR gate 1407 to the bus 1408. The simultaneous appearance of a signal on the order lead SCLR [FIG. 21] transmits these single rail signals through the AND gate 2100 to the set inputs of the Logic Register 2508.

The selection of the "0" bus or "1" bus is determined by the states of flip-flops AU [FIG. 55], SCBA [FIG. 59], and 59SCBB according to the following table.

55AU 59SCBA 59SCBB Bus Selected 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1

In the execution of network command orders on All Seems Well signal is returned in some instances via ASW0 or ASW1 of the Scanner Answer Bus System 6600. This signal serves to indicate the proper response to the command by the selected network command unit. In such instances a signal on order cable conductor SCA0 or SCA1 [FIG. 14] transmits the All Seems Well signal through the AND gates 1406 or 1405 and the OR gate 1409 to the Error Summary Cable 1218. The All Seems Well signal is thereby transmitted to the set input of the flip-flop ASWS [FIG. 62]. When specified by a network command order being executed, the output of the flip-flop ASWS is interrogated by the Command Order Sequencer 4902 to determine the appearance of the All Seems Well signal; if this signal is not so registered in the flip-flop, further gating actions are undertaken by the Command Order Sequencer 4902 which lead to an ensuing interrupt program to examine the system for the cause of the trouble.

The CPD verify signals, and information returned on the Scanner Answer Bus System 6600 appear as single rail half microsecond pulses which are to set selected flip-flop registers within Central Control 101. To prepare for the reception of such single rail information the corresponding flip-flop registers are previously reset. If information is to be transmitted from the Scanner Answer Bus System 6600 to the Logic Register 2508, then a signal appearing on the order lead RELR [FIG. 25]during 4T6 of cycle 4 resets that register. Similarly, signals appearing on order cable leads REYR [FIG. 30] and RASWS [FIG. 62] provide the initial resetting of the Y Register 3001 and the flip-flop ASWS [FIG. 62].

Cross Connection of Error Signals in Central Control 101

The Central Control 101 is duplicated, and at any time one of the two units is designated the "active unit" and the remaining unit is referred to as the "standby unit." The active unit serves to execute all of the call processing and most of the maintenance program sequences. That is, in most instances the control of the telephone switching system emanates from the execution of program sequences within the active central control unit; the standby central control unit may also be executing the same program sequences, but the standby central control unit does not transmit CPD commands or network commands and therefore has no direct influence in the operation of the telephone switching system.

When difficulties in the operation of the Central Processor 100 are detected by one or more of hardware or program checks remedial maintenance programs are called in which may determine that the difficulty lies within the active central control unit. If this is the case the Emergency Action Sequencer 5702 or a program sequence executed in the active central control "switches" the units. That is, the active central control unit is made to be the standby unit, and the standby central control unit is simultaneously designated the active unit. This switch is made by a CPD command which simultaneously changes the states of the CPD controlled status flip-flops AU [FIG. 55] in both central control units. The state of this flip-flop places its central control in the standby or active state. By resetting flip-flop AU an active central control is switched to the standby state.

In the absence of trouble the various duplicate units (the Central Control 101, the Program Store 102, the Call Store 103, and connecting address and response bus systems) may be assembled into two distinct or partially shared duplicates of a central processor. The active central control unit is the nucleus for an "Active Central Processor," and the standby central control serves in the "Standby Central Processor." The duplicate central processors are advantageously used in our system in two modes. The first mode is the running of the duplicate central processors in "step." That is, both active and standby central processors are executing the same program sequences (from the same or duplicate program store units), reading and writing data (from the same or duplicate call store units), but only the active central processor is controlling the Central Pulse Distributor 143 and the network command units. In the second mode of operation the active central processor is carrying on the call processing function using one set of program sequences while the standby central processor is performing diagnostic exercises utilizing different program sequences and only "unshared" units of the duplicate central processors.

In the first mode the execution of program sequences in duplicate within the Central Processor 100 is employed to detect the occurrence of circuit troubles therein by periodically matching strategic data processing nodes in both central control units. (In this embodiment two pairs of words are matched per 5.5-microsecond cycle.) The nodes matched include the Unmasked Bus 2014, the Masked Bus 2011, the Index Adder Output Register 3401, and the Data Buffer Register 2601, the Program Address Register 4801, the Buffer Order Word Register 2410, and sequencer test points.

When circuit troubles occur in one central processor unit and cause the data processing to be altered this alteration results in a mismatch of two like nodes in the duplicate central processors. The detection of the mismatch will lead to a maintenance interrupt and program sequences designed to determine the unit in trouble. It should be noted that the matching scheme works only if the duplicate program sequences are running in step. That is, if the execution of one program sequence falls behind its "twin," then mismatches of like nodes may occur as a result of different data processing steps rather than circuit troubles. The result would be the occurrence of the C level maintenance interrupt leading to the above-mentioned program sequences which is not only unnecessary but also may cause subscriber dissatisfaction by a lengthy interruption of call processing to execute exhaustive program sequences which search for a nonexistent trouble.

As previously indicated, there exist partially or wholly independent "loops" of communication between the two central control units and two or more units in the Program Store 102 and/or the Call Store 103. It is therefore possible that an error be generated in one such loop while no corresponding error occurs in the duplicate loop. For example, one central control unit may detect an error in reading program words or data while the second unit receives a valid word of program or data. In such instances one central processor unit inserts one or more 5.5-microsecond cycles to correct or reread the program or data word; to keep the two program sequences in step, for purposes of matching, the duplicate unit must also insert the same one or more 5.5-microsecond cycles. The duplicate central processors are kept in step by the "cross connecting" of error information so that correction or rereading actions are initiated in both central processors in response to hardware troubles detected in either duplicate central processor. That is, when one central control unit detects a failure of one or more hardware checks in reading or writing words in the Program Store 102 or the Call Store 103 or in executing a CPD command and/or a network command, the information is transmitted to the second central control unit. A similar transmission of information from the second central control unit to the first is included to provide the "cross connection."

This cross connection of trouble information is only relevant when the two central controls are running in step. When the central processors are executing independent programs matching is dropped. In this independent mode trouble information transmitted from one central control unit to another is irrelevant and must be ignored. This is accomplished by setting the CPD controlled status flip-flop DI [FIG. 55] which, as described below, disables the cross connection.

The hardware check of program or data words read from the Program Store 102 by the Central Control 101 is performed in the Error Detection and Correction Circuit 2400. Checks are also made therein of program words obtained from the Call Store 103. When a correctable error is detected, a signal appears on the I Correct conductor 2420; when an error requiring a rereading is detected, a signal appears on the I Reread conductor 2421.

A signal appearing on conductor 2420 sets the I Correct flip-flop 2312, and a signal on conductor 2421 sets the I Reread flip-flop 2313. The flip-flops 2312 and 2313 serve as the indication of hardware check failures within the central control unit. The setting of either of these flip-flops results in a signal being transmitted through the OR gate 2317 and the conductor 2322 to the Error Detection and Correction Circuit 2400 which in turn generates signals leading to the required actions of correcting or rereading.

Signals appearing on conductors 2420 and 2421 are transmitted through the AND gates 2302 and 2303, respectively by the appearance of a signal on order cable conductor PSX [FIG. 23] during 12T14 of the 5.5 -microsecond cycle in which the program store reading is being checked. These signals are thereby transmitted as half microsecond pulses through the Cable Drivers 2304 and 2305 and the bus 2300 to the other central control unit. The bus 2300 in each central control unit is the bus 2301 in the other central control unit; the half microsecond signals corresponding to conductors 2420 and 2421 generated in one central control unit appear on the bus 2301 of the other central control unit and are transmitted via the Cable Receivers 2310 and 2311 to the set inputs of the E Correct flip-flip 2314 and the E Reread flip-flop 2315, respectively. The setting of either the E Correct or E Reread flip-flops causes a signal to be transmitted via the OR gate 2317 and the conductor 2322 to the Error Detection and Correction Circuit 2400. Thus errors detected in reading the Program Store 102 for program words or data or the Call Store 103 for program words within one central control unit to cause the Program Store Correct-Reread Sequencer 5301 or the Call Store Program Sequencer 5302 in both units to insert the same number of machine cycles and thereby keep the program execution in step.

When the duplicate central processors are executing different program sequences the flip-flip DI [FIG. 55] must previously be set in both central control units; a signal then continually appears on the order cable lead DI [FIG. 23] and is transmitted through the OR gate 2316 to the reset inputs of the E Correct and E Reread flip-flops. This reset signal overrides any trouble signals transmitted from the other central control so that the Error Detection and Correction Circuit 2400 does not respond to any externally generated trouble signals.

A similar cross connection applies to the reading or writing of data from the Call Store 103. In this instance hardware check failures are summarized in the Call Store Error Detection Circuit 2200 and appear as a signal on the CERI output conductor 2220 which sets the CSEI flip-flop 2201 and is transmitted via the AND gate 2700 and Cable Driver 2701 to the bus 2706. The bus 2706 in each central control unit is connected to the bus 2208 of the other central control unit; the call store error signal generated as a half microsecond pulse in AND gate 2700 of one central control is thereby transmitted through Cable Receiver 2205 of the other central control unit to the CERE conductor 2212 and to the set input of the CSEE flip-flop 2202. The setting of either of the CSEI or CSEE flip-flops causes a signal to be transmitted through the OR gate 2203 to the conductor CER [FIG. 22]; signal appearing on CER leads to the activation of the Call Store Reread Sequencer 5700.

Setting the flip-flop DI [FIG. 55] causes a signal to continually appear on DI [FIG. 22] and be transmitted through the OR gate 2209 to the reset input of the CSEE flip-flop 2202; the setting of DI [FIG. 55] serves to disable the cross connection of call store error information.

A cross connection of hardware check failure information is also provided as part of the execution of CPD commands and network commands. These commands and the hardware checks are executed under control of the Command Order Sequencer 4902; upon completion of a CPD command or a network command any hardware check failures are summarized as a half microsecond pulse appearing on the order cable conductor PUEI [FIG. 27] which is connected via the bus 5205 to the set input of the Maintenance Interrupt Source Flip-Flop PUEI [FIG. 52]. This same signal is transmitted via the Cable Driver 2701 and bus 2706 to the other central control unit. This signal is transmitted to the bus 2208 of the other central control unit and within that unit through the Cable Receiver 2205 to the conductor PUEE [FIG. 22]. Unless the flip-flop DI [FIG. 55] is set the signal appearing on PUEE [FIG. 22] is transmitted through the AND gate 5218 to the set input of the Maintenance Interrupt Source Flip-Flop PUEE [FIG. 52]; setting either PUEI or PUEE leads to a level F maintenance interrupt and interrupt program sequences which investigate difficulties in CPD command or network command communications

WV

This order selectively enables output conductors of AND gates 4701-4715 according to the DAR word generated in the execution of this order. The DAR word is transmitted from the Index Adder Output Register 3401 via the Mask and Complement Circuit 2000, conductors 2017, the Insertion Mask Circuit 2109 and the OR gate 2106 to the Data Buffer Register 2601. This word is transmitted through the AND gates 4701-4715 by means of a signal on order cable conductor 47WV. The signals at the output of these gates are used to perform test functions in transmitting maintenance signals both within the central control executing the WV order to the other central control and to the network command units.

For example, signals appearing on bit positions 5 and 4 are transmitted via the conductors 47RESET and 47FCG, respectively, of the bus 4722 to the Network Command Transmit Bus Selection Gates 2800. From there these signals are transmitted simultaneously to all the network command units via the selected "0" bus 2806 or "1" bus 2807 of the Network Command Bus System 6406, to carry out test functions in certain of these units.

Signals at bit positions 6, 8-11, 13 and 14 result in half microsecond pulses being transmitted to the other central control via cable 4723, Cable Drivers 2701, and cable 2706. Cable 2706 is connected to cable 2208 in the other central control. Thus these signals are received at the Cable Receivers 2205 and transmitted to other points within the other central control via conductors 2218 and 2219 and cable 2221. Similar connections are made from the second central control to the first to provide two-way communication utilizing order WV. However, certain of these cross-connected signals may be transmitted only from the active central control to the standby central control. When order WV is executed in the standby central control the internal functions which are dictated by that order are executed, but the corresponding cross-connection signal is inhibited. The signals to which this restriction applies are those on conductors 27ISTBY5MS RS, 27ISTBY-ST, 27ISTBY-RS, 27IE STOP and 27IF STOP, which signals are transmitted via AND gate 2707 which is enabled in the active central control by a signal on order cable conductor 27AU.

Signals in bit positions appearing on one or more of the bit positions 7-9, 11, 12, 15-18 generate half microsecond pulse signals to carry out various gating actions within the central control executing the WV order. The individual gating actions are performed as follows:

47ISTBY 5MS RS

A signal appearing on this conductor in the active central control enables order cable conductor 57-5MS RS in the standby central control. This signal is transmitted via the OR gate 6104 to the reset input of the Millisecond Clock 6101 to rephase the clock.

47IACT 5MS RS

A signal appearing on the conductor 47IACT 5MS RS in the active central control enables the order cable conductor 57-5MS RS to rephase the Millisecond Clock 6101 in the active central control.

47IE STOP

47if stop

47istby st

47istby-rs

the signal appearing on a selected one of these leads causes information not only to be transmitted from the active central control to the standby control but also causes the flip-flop 4725 to be selectively set or reset.

A signal appearing on the conductor 47 i.e. STOP or 47IF STOP is transmitted from the active central control to the standby central control to stop the processing of program orders in the standby unit by activating the Stop Sequencer 4400 therein. Either signal is also transmitted through the OR gate 4724 to the set input of flip-flop 4725. Accordingly, the setting of this flip-flop serves as an indicator in the active central control that signals have been transmitted to "stop" the standby central control.

Similarly, the appearance of a signal on conductor 47ISTBY ST in the active central control causes a signal to be transmitted to "start" the standby central control. This signal also resets the flip-flop 4725 which indicates the new status of the standby central control.

Enabling conductor 47ISTBY-RS in the active central control causes a pulse to be transmitted to the OCG input cable conductor 22ESTBY-RS of the standby central control. When the standby central control has been "stopped" (that is, the Stop Sequencer 4400 in the standby unit is active) the signal on 22ESTBY-RS enables order cable conductors 24REBA, 24REBB, 34REOW, 44TS RESET, 49IS RESET, 49COS RESET, 53GBS RESET, 53PSCRS RESET, 53CSPS RESET, 57CSRS RESET, and 57KRS RESET to retain or place the Buffer Order Word Register 2410, the Order Word Register 3403, and all the sequencers except the Start Stop Sequencer 4400 and the Emergency Action Sequencer 5702 in the reset or inactive state. OL1R and OL2R

Enabling this conductor transmits a reset signal via conductor 4731 to flip-flops 550L1 and 550L2. When these flip-flops are set in the active central control the transmission of CPD and network commands to the corresponding bus systems are inhibited. When the same flip-flops are set in the standby central control that unit is permitted to transmit commands to the CPD Bus Choice Bus 6405, the CPD Address Bus System 6403, the CPD Execute Cable 6404, the CPD Input Sync Cable 6702, and the Network Command Bus System 6406.

47PKCKR

A signal on this conductor enables order cable conductors 35ADD and 35KLKR to place the contents of the K A Input Register 3502 into K Register 4001. In this instance the K Input Logic 3505 generates the sum of its two inputs, but only the contents of the K A Input Register 3502 are transmitted to the K Register 4001 since the contents of the K B Register 3504 are all zeros.

47GOPU

A signal on this conductor activates the Command Order Sequence 4902 to carry out command order gating actions as previously described.

17, 18

Signals at the output conductors of AND gates 4714 and 4715 selectively set or reset the flip-flop 4717, respectively. The one output conductor 47MOIA of this flip-flop is utilized in testing the Interrupt Sequencer 4901, and the order WV provides a means for selectively setting or resetting the flip-flop 4717.

47IINT-0

47iint-1

signals on conductors 47IINT-0 and 47IINT-1 result in the transmission of half microsecond pulses to the leads 22EINT-0 and 22EINT-1, respectively, of the other central control, and the signals appearing therein are transmitted via the conductors 2218 and 2219 to the set inputs of the maintenance interrupt source flip-flops 56CCC-0 and 56CCC-1, respectively. The setting of these flip-flops in the other central control establishes the request for a G level interrupt program therein.

Thus WV order provides a means of causing an interrupt in the other central control and thereby requests the other central control to carry out specific maintenance tasks such as the transmission of the results of diagnostic tests or to initiate program sequences to start or continue such tests.

Stop Sequencer (4400)

Signals may be transmitted from the active central control to the standby central control to selectively:

1. Stop or start the processing of program order words therein; and

2 Reset certain flip-flop registers and internal state counters of a number of sequencers within the standby central control. A signal appearing on 22EE STOP or 22EF STOP in the standby central control activates the Stop Sequencer 4400 which in turn stops the execution of program words therein; a signal on 22E START deactivates the sequencer to permit the execution of program orders to resume; and a signal on 22 IF STOP or 22E STBY RESET may be employed to reset the Buffer Order Word Register 2410, the Order Word Register 3403, and all sequencers except the Stop Sequencer 4400. Details of the gating actions resulting from the appearance of the above-mentioned signals are as follows:

22EE STOP A signal on the "Execute Stop" conductor 22EE STOP is transmitted via the OCG Cable 1812, the Order Combining Gate Circuit 3901, and the Order Cable 3900 to the order cable conductor 44HALT. This signal registers a "request" within the Stop Sequencer 4400 to inhibit the processing of orders. That is, this signal does not activate the Stop Sequencer 4400 immediately but sets a flip-flop within the sequencer which in response enables the conductor 44STOP. The signal on conductor 44STOP is transmitted via the bus 4402 to the Order Combining Gate Circuit 3901 wherein the Buffer Order Word Decoder 3902 and the Mixed Decoder 3903 are inhibited from performing gating actions for any program order word appearing in the Buffer Order Word Register 2410. Upon the completion of any order currently being processed in the Order Word Register 3403, the Stop Sequencer 4400 is activated in response to a signal on the order cable conductor 44SS GO. The Stop Sequencer 4400 responds by inhibiting the outputs of the Order Word Decoder 3904 and inhibits the activation of the remaining sequencers.

In summary, the Stop Sequencer 4400 when activated via the "Execute Stop" conductor 22EE STOP permits the completion of the operational step of the program order word appearing in the Order Word Register 3403 regardless of the number of additional machine cycles required and inhibits the gating actions for the next program order word in sequence. When the program order word appearing in the Order Word Register 3403 is a single cycle order, then the Stop Sequencer 4400 is activated within the time of a machine cycle after conductor 22EE STOP is enabled. If, however, the order is a multicycle order, the Stop Sequencer 4400 is not activated until the operational step is completed thereby insuring that the operational step of that order is not mutilated in stopping the standby central control.

22EF STOP Enabling the "Fast STOP" conductor 22EF STOP in the standby central control immediately enables conductors 44SS GO and 44HALT to activate the Stop Sequencer 4400 regardless of the states of the remaining sequencers. In addition, the signal on conductor 22EF STOP enables the reset conductors 24REBA, 24REBB, 34REOW, 44TS RESET, et cetera, which places or retains in the reset or inactive state the Buffer Order Word Register 2410, the Order Word Register 3403, and all sequencers except the Stop Sequencer 440 and the Emergency Action Sequencer 5702.

The "Fast Stop" signal serves to stop the standby central control even when one or more of the sequencers are stuck in the active state.

22E STBY START A signal on the "Start" conductor 22E STBY START is transmitted to the order cable conductor 44START to return the Stop Sequencer 4400 to the inactive state and thereby return the order processing capabilities to the decoders and sequencers within the standby central control. Restarting the Central Control 101 causes the resumption of the execution of sequences of program order words beginning with the program order word appearing in the Buffer Order Word Register 2410.

22E E STBY RS Whenever the Stop Sequencer 4400 is priorly or concurrently activated by signals on either of conductors 22EE STOP or 22EF STOP the signal appearing on the "standby reset" conductor 22E STBY RS causes the Buffer Order Word Register 2410, the Order Word Register 3403, and the remaining sequencers in the standby central control to be retained or placed in the reset or inactive state. In other words, the simultaneous appearance of signals on conductors 22EE STOP and 22E STBY RS generates gating actions identical to those performed in response to a signal on conductor 22EF STOP.

It may be noted that signals occurring on conductor 22EE STOP-MTCE AND 22EF STOP-MTCE may also serve to enable the Stop Sequencer 4400. The generation of signals on these conductors is described with respect to the Maintenance Decoder 4608.

Matching Circuits and the Maintenance Decoder (4608)

In most instances the duplicate central controls are both executing the same program sequences and both units are executing the same program orders at the same time.

Signals are generated and transmitted by a means not indicated herein from the Microsecond Clock 6100 of each central control to the clock in the other central control. These signals serve to keep the two microsecond clocks running in step so that the appearance of each of the clock pulses depicted in FIG. 84 in one central control coincides with its appearance in the other central control. By one of several program or hardware means the duplicate central controls are started with the selected same code-address placed in their respective program address registers which leads to the simultaneous entry to the same sequence of program orders. Each central control then continues in step with the other central control; the same data is read from the memory and scanners, the same data processing steps are performed and the outcome of decisions is the same in both units. Furthermore, when the cross-connection of error information as previously described herein is enabled by resetting the Disjoin Flip-Flop 55DI, any additional cycles inserted in the program execution of one central control for correction or rereading is accompanied by the insertion of these same additional cycles in the other central control.

The mode of operation just described is designated herein as the "in-step mode" and is utilized to provide a continuing hardware check of the two central controls. This check consists of repeated comparisons of common points in both central controls to permit the almost instantaneous detection of trouble conditions in either central control. The repeated comparisons are made with the matching circuits and the Maintenance Decoder 4608.

The details of the matching circuits within one Central Control 101 are described with the aid of FIGS. 10 through 63, and FIG. 70 serves to indicate the communication of information to be matched within and between each central control.

The extensive access of the matching circuits is provided within a central control via the Internal Match Buses 70INT MBO (4900) and 70INT MB1 (3400) and the communication link between central controls consisting of the Match Registers 70ARO (3105), 70DRO (3118), 7ARI (3605), and 70DR1 (3617), herein designated as the Match Register, the External Match Buses 70 EXT MBO (2210) and 70 EXT MB1 (2211), the connecting Cable Drivers 2703 and 2705, buses 2706 and 2208, and Cable Receivers 2206 and 2207.

This access permits frequent "routine matching" of many strategic points within the two central controls. It also provides the basis for a powerful diagnostic tool that may be employed with program sequences which permit one central control to examine internal points not otherwise accessible to program or to explore the internal state of the other central control in search of trouble. The control of routine matching and the selection of the "routine matching mode" or one of a plurality of "maintenance matching modes" to be described resides in the Mode Control Register (MOCR) 4603. When routine matching is specified, then additional control information is retained in the Match Cycle Control 5105 and 5106, and when certain of the maintenance matching modes are employed the Match Control Register (MACR) 4103 provides additional information.

The Maintenance Decoder 4608 receives signals from the above-mentioned registers via the connecting buses 4607, 5113 and 4107, respectively; signals on the Order Cable Leads 4600 provide microsecond clock pulses and D-C control information relating to the state of the decoders and sequencers, control information is also transmitted from the CPD controlled status flip-flops 55B-TST and 55V-BIT via the conductors 5506. In response to these inputs the Maintenance Decoder 4608 generates outputs on the OCG Cable Leads 4610 to transmit information from one register to another via the bus system depicted in FIG. 70. Other outputs of the Maintenance Decoder 4608 appearing on the Maintenance Decoder Cable 4609; (1) enable information to be placed in the match registers; (2) cause information to be transmitted from the Internal Match Buses "0" 4900 and "1" 3400 via the AND gates 2702 and 2704 to the Cable Drivers 2703 and 2705, respectively; (3) depending on the matching mode being employed set one of the maintenance interrupt source flip-flops 52MMIO, 52MMI1, 52BPI or 52TRI when mismatches or other specified conditions are detected.

The Routine Matching Mode

In the routine matching mode a frequency of two matches per 5.5 -microsecond cycle is permitted by the inclusion of two match circuits each of which is capable of performing one match per machine cycle. All information to be matched is first gated to one of the two internal match buses 70INT MBO and 70INT MB1 of each central control. The information on the internal match buses is transmitted to the internal match registers 70DRO and 70DR1, respectively and via the external match buses 70EXT MB0 and 70EXT MB1 to the external match registers 70AR0 and 70AR1, respectively of the other central control. The outputs of the AR0 and DR0 Match Registers 3105 and 3118 are transmitted via the buses 3107 and 3119 to the Match "0" Circuit 3122; this configuration of circuits and the associated communicating buses are designated herein as Match Circuit "0." A similar configuration is noted among the AR1 and DR1 Match Registers 3605 and 3617, the Match "1" Circuit 3621, and the associated communicating buses and is designated herein as Match Circuit "1."

FIG. 70 indicates the points which are examined in the routine matching mode. These are:

A. the Unmasked Bus 70UB (2014)

B. The Masked Bus 70MB (2011)

C. The Index Adder Output Register 70IAOR (3401)

D. The Data Buffer Register 70BR (2601)

E. The Program Address Register 70PAR (4801)

F. The Buffer Order Word Register 70BOWR (2410)

G. Selected sequencer and decoder outputs 70SEM1 (29SEM1).

Since only two points per machine cycle are permissible the sequence of matches in the routine matching mode is determined by the Match Cycle Control Flip-Flops 5105 and 5106 and the Maintenance Decoder 4608 according to the following requirements:

1. Match the data buffer registers and index adder output registers when a call store writing command is being executed.

2. Match the masked buses and the index adder output registers when a call store reading command is being executed or when a command order is being executed.

3. Match the buffer order word registers after the rereading or correction of a word obtained from the Program Store 102 unless requirement (1) or (2) is to be met.

4. Match the unmasked buses upon the execution of transfer orders (to sample any "return address" being transmitted to the J Register 5802) and match the program address registers for two machine cycles after the transfer to verify that both central controls executed a transfer to the same new program sequence. If requirements (1), (2) or (3) are to be met then matching as described in requirement (4) is deferred accordingly.

5. When none of the above requirements are to be met, then a routine cyclic match is performed every four machine cycles. This match is designated herein as the "4 Cycle Match."

The above listed requirements are such that: Any trouble that develops within Central Control 101 is detected at least as soon as the effect of the trouble would be communicated to other units in our system.

Signals transmitted on the order cable conductors 4600 indicate which of the above-mentioned requirements are to be met, and the Maintenance Decoder 4608 in turn sets or resets one of the Match Cycle Control Flip-Flops 5105 (51EC, 51RE, 51WR and 51PU) or causes the Match Cycle Control Binary Counter 5106 to be reset or incremented. The match cycle employed as the result and the points matched are tabulated below. In that table the time of each match is specified as one of 0T8, 10T16, 16T22 which are the three major data processing divisions in a machine cycle. The match time is specified to obtain the timely sample of information pertinent to the operation which selects the match cycle. For example, when a call store writing command is being examined for mismatches the data buffer registers are matched during 10T16. A match is thereby made of the data transmitted to the Call Store 102 after it is placed in the Data Buffer Register 2601. ##SPC3##

As indicated in the table, requirement (4) is met by resetting the Match Cycle Control Binary Counter 5106 and initiating the 4 Cycle Match. It may also be noted that in the third and fourth cycle of the 4 Cycle Match two different sets of 24points in the decoders and sequencers are examined. Matching access to a substantial number of selected points therein is not only desirable in the routine matching mode but a powerful tool for the diagnosis of troubles in those relative complex circuit configurations where no other direct "program access" is provided.

As previously noted when the duplicate central controls are running in the in-step mode the transmission of information between the central controls and the Program Store 102 and the Call Store 103 in most instances involves distinct program store and call store units and distinct interconnecting buses. When, for example, one central control receives a mutilated reading from the memory, both units will insert the required number of cycles for correction and/or rereading to keep the two central controls in step. Although the first reading obtained may be different in the two central controls the remedial action should obtain matching readings. Therefore, the indication of communication troubles of this kind in the Central Processor 100 not only initiates the required remedial action but also inhibits the routine matching mode until a rereading or rewriting step which passes the necessary hardware checks is accomplished. If the retrial fails, the routine matching is further inhibited by the resetting of the CPD controlled status flip-flop 55V-BIT which halts matching. This gating action is performed by the Program Store Correct-Reread Sequencer 5301 or the Call Store Reread Sequencer 5700 if either sequencer determines a failure in executing a repeated memory command.

Each match condition is indicated on the AM0 conductor 3123 and the AM1 conductor 3622, respectively. When the routine matching mode is employed each match is interrogated by examining these conductors. A mismatch as indicated by the enabling of AM0 conductor 3123 or AM1 conductor 3622 results in the setting of the maintenance interrupt source flip-flops 52MMI0 or 52MMI1, respectively. The setting of these flip-flops results in a C level maintenance interrupt and entry to the corresponding program sequences which determine the nature of the trouble and which if either, of the duplicate central control contains a circuit fault.

Maintenance Matching Modes

The maintenance matching modes provide program access to a plurality of flip-flop registers, buses, and test points within the decoders and sequencers not otherwise available. In the performance of certain maintenance tasks the routine matching mode is inhibited since the results of the matching operation are meaningless. For example, the active central control may be executing call process program sequences while the standby "off line" central control is simultaneously executing special test programs and therefore the states of registers, buses and test points of the two central controls are generally dissimilar. When operating in this mode, designated herein as the diagnostic mode, certain of the maintenance matching modes may be employed to:

1. Provide special monitoring of special test points in the standby central control;

2. Communicate pertinent selected data from one central control to the other.

In carrying out other maintenance tasks the two central controls are operating in the in-step mode, but the routine matching mode does not best serve the needs of these tasks; therefore, other selective maintenance matching modes permit program access to the required test points. The selection of either the routine matching mode or one of the maintenance matching modes is determined by the states of the Match Control Register 4103, the Mode Control Register 4603, and the CPD controlled status flip-flops 55V BIT and 55B TST.

Before describing the maintenance matching modes the means of obtaining the modes are briefly noted. Most of the matching modes require that the Match Control Register 4103 and the Mode Control Register 4603 in both central controls contain the same information. When the two central controls are running in step the modification of the Match Control Register 4103 and the Mode Control Register 4603 in one central control is accompanied by the simultaneous like modification in the other central control. The changing of matching modes is therefore concurrently accomplished in the two units.

When, however, the central controls are operating in the diagnostic mode the modification of the Match Control Register 4103 and/or the Mode Control Register 4603 in the active central control is not simultaneously accompanied by the corresponding modification in the standby unit. To achieve the corresponding modification in the standby unit the active central control must "stop" the standby central control and by means of control writing operations place the required information into the Match Control Register 4103 and/or the Mode Control Register 4603 of the standby central control. The standby unit may then be "restarted" to continue execution of its diagnostic program sequences.

Executing order WV in the active central control stops the standby unit by generating an Execute Stop signal or a Fast Stop signal on the conductor 27IE STOP or 27IF STOP, respectively. (Execution of the WV order with a specified D-A field serves to generate these signals.) Either signal activates the Stop Sequencer 4400 in the standby central control and thereby stops that unit. When the standby central control is stopped in this manner it is not responsive to program orders and therefore executes no program sequences; however, the Control Word Decoder 1804 and the Maintenance Decoder 4608 are responsive so that the standby central control can accept control writing data and be able to communicate internal state information to the active central control. Stopping the standby central control may then be followed by control writing commands to modify the Match Control Register 4103 and the Mode Control Register 4603. If also required, a new code-address may be placed in the Program Address Register 4801 of the standby central control to initiate the entry to a new diagnostic program sequence when the standby unit is restarted. The standby central control is restarted by generating a start signal on the conductor 27ISTART in the active central control. This signal returns the Stop Sequencer 4400 in the standby unit to the inactive state to restart the execution of sequences of program orders therein.

Whenever the matching modes are to be changed the Maintenance Decoder 4608 must first be inhibited so that the modifications to be made in the Match Control Register 4103 and the Mode Control Register 4603 do not generate spurious transient signals which, for example, could set one of the maintenance interrupt source flip-flops 52MMI1 or 52MMI0. This restriction applies when the central controls are either operating in the in-step mode or in the diagnostic mode; it also applies in most instances when the standby central control is stopped since, as noted, the maintenance decoder functions are not inhibited by stopping the Central Control 101.

The current matching mode is inhibited in both central controls by resetting the CPD controlled status flip-flop 55V BIT. The execution of a CPD command in the active central control is used to reset the flip-flop 55V BIT in both central controls to provide the simultaneous inhibition of matching. When the new mode is established by the modification of the Match Control Register 4103 and the Mode Control Register 4603 in both central controls the flip-flop 55V BIT may then be set to initiate the new matching mode.

Selection of Match Points

When the Maintenance Decoder 4608 is operating in certain of the maintenance matching modes a portion of the contents of the Match Control Register 4103 specify the match point and the time of the match. 41P ₀₀ , 41P ₀₁ and 41P ₀₂ determine the point to be matched in Match Circuit "0;" 41t ₀₀ and 41t ₀₁ determine the time of this match. A similar determination for Match Circuit "1" is made with the contents of 41P ₁₀ , 41P ₁₁ , 41P ₁₂ , 41t ₁₀ and 41t ₁₁ of the Match Control Register 4103. The selection of match points and time of match are tabulated below: ------------------------------------------------------------ --------------- MATCH CIRCUIT "0"

P ₀₂ P ₀₁ P ₀₀ Points to be Matched ____________________________________________________________ ______________ 0 0 0 No match 0 0 1 Program Address Register 4801 0 1 0 Masked Bus 2011 0 1 1 Bits 19 through 0 of Buffer Order Word Register 2410 1 0 0 Data Buffer Register 2601 1 0 1 Auxiliary Storage Register 4812 1 1 0 Group "0" Decoder Points 3423 1 1 1 Match present contents of ARO 3105 and DRO 3118 t ₀₀ t ₀₁ Time of Match ____________________________________________________________ ______________ 0 0 No match 0 1 10T16 1 0 0T8 1 1 16T22 ____________________________________________________________ ______________ ------------------------------------------------------------ --------------- MATCH CIRCUIT "1"

P ₁₂ P ₁₁ P ₁₀ Points to be Matched ____________________________________________________________ ______________ 0 0 0 No match 0 0 1 Selected Sequencer and Decoder Points 2918 0 1 0 Unmasked Bus 2014 0 1 1 Bits 43 through 20 of Buffer Order Word Register 2410 1 0 0 Index Adder Output Register 3401 1 0 1 No match 1 1 0 Group "1" Decoder Points 3426 1 1 1 Match present contents of AR1 3605 and DR1 3617 t ₁₀ t ₁₁ Time of Match ____________________________________________________________ ______________ 0 0 0 0 1 10T16 1 0 0T8 1 1 16T22 ____________________________________________________________ ______________

when Match Circuit "1" is selected to perform matches on selected sequencer and decoder points the state of the Match Cycle Control Binary Counter 5106 determines the alternate selection of the one of two groups of sequencer and decoder points as previously described in the corresponding third and fourth cycles of the 4 Cycle Routine Match employed in the routine matching mode. Whenever the flip-flop 461C in the Mode Control Register 4603 is set the Match Cycle Control 5105 and 5106 no longer respond to the state of Central Control 101 as previously described; in such instances the binary counter and flip-flops in the Match Cycle Control 5105 and 5106 can be set to a specified state to select the group of sequencer and decoder points to be matched.

In examining FIG. 70 is can be noted that certain of the information paths leading to the Match Registers 70AR0, 70DR0, 70AR1 and 70DR1 may not be specified by the state of the Match Control Register 4103. In particular the direct matching of the "0" and "1" buses of the Program Store Response Bus System 6500 (70PSB0 and 70PSB1) and the Call Store Response Bus System 6501 (70CSB0 and 70CSB1) is determined by the state of the Mode Control Register 4603. A special maintenance matching mode may be specified therein to match these buses; the responses from the duplicate units in the Program Store 102 and the Call Store 103 may thereby be matched even when the standby central control is out of service. This matching mode is also employed in determining whether circuit troubles are present in the Response Bus System 6500 and 6501, Cable Receivers 1201, 1202, 1301 and 1302, or the Response Bus Selection Gates 1200 and 1300 or whether instead the trouble is located in the Program Store 102 or the Call Store 103.

Selection of Matching Modes

The matching modes include the routine matching mode and a plurality of maintenance matching modes selected according to the contents of the Mode Control Register 4603 as follows: ##SPC4##

In the above table the X entries indicate options which may be specified in the given matching mode; the D entries are "don't care" entries which indicate that the setting of the corresponding bit position of the Mode Control Register 4603 does not affect the corresponding matching mode.

The control of matching mode options with the Mode Control Register 4603 is determined by the setting of selected flip-flops as follows:

46MS Setting this flip-flop selects the mismatch sampling mode or serves with the break point mode to select the "snapshot option."

46CB Setting this flip-flop causes the contents of the Index Adder Output Register 3401 to be matched when the break point mode is employed.

46PB Setting 46PB causes the contents of the Program Address Register 4801 to be matched when the break point mode is in operation.

46IC When 46IC is set the Match Cycle Binary Counter 5106 is incremented and the Match Cycle Control Flip-Flops 5105 set and reset as described for the routine matching mode.

46I Setting this flip-flop causes the maintenance interrupt source flip-flops 52MM10 and/or 52MM11 to be set when a match or mismatch is detected, the condition of match or mismatch being dependent on the matching mode in control.

46HM Setting 46HM causes further matching to be inhibited upon detection of the conditioned match or mismatch condition.

46E When 46E is set the detection of the conditioned match or mismatch results in the generation of the execute stop signal on the conductor 27IE STOP-MTCE to cause the standby central control to be stopped.

46F When 46F is set the detection of the conditioned match or mismatch results in the generation of the fast stop signal on the conductor 27IF STOP-MTCE to cause the standby central control to be stopped.

When the central controls are operating in the in-step mode and the routine matching mode is operative certain option bits of the Mode Control Register 4603 may be selectively set or reset according to optional gating action required. If the bit 46HM = 1, then when a mismatch is detected no further matching takes place until the Maintenance Decoder 4608 is restarted by setting the CPD controlled status flip-flop 55V BIT. If 46I is set, then a detected mismatch is followed by the setting of the maintenance interrupt source flip-flops 52MM10 and/or 52MM11; and the Interrupt Sequencer 4901 may be activated in response to the setting of these flip-flops. When 46I is reset, then the detection of mismatches does not result in the setting of the maintenance interrupt source flip-flops 52MM10 or 52MM11. Similarly, the state of 46E and 46F controls the generation of execute stop and fast stop signals, respectively.

In the routine matching mode previously described one of eight match cycles is executed according to the state of Central Control 101; this selection of matching prevails if the flip-flop 46IC is set. When 46IC is reset the Match Cycle Control 5105 and 5106 is not automatically modified to reflect the state of Central Control 101. The one of eight match cycles are still selected by the state of the Match Cycle Control 5105 and 5106; repeated "routine matching" of two points can therefore be obtained by resetting the flip-flop 46IC, writing the required information into the Match Cycle Control 5105 and 5106, and then setting the Mode Control Register 4603 to obtain the routine matching mode.

Mismatch Sampling Mode

One of the maintenance matching modes employed when the two central controls are operating in step is the mismatch sampling mode. The mismatch sample is initiated by the execution of the order EMMS. One portion of the DAR word formed in executing this order specifies the points and time of match for Match Circuit "0" and/or Match Circuit "1." Another portion is treated as a binary number which indicates the number of 5.5-microsecond cycles following the execution of the EMMS order at which the "samples" are to be taken.

The operational step of the order EMMS includes the following gating action to effect the mismatch sampling mode:

1. Set the Mode Control Register 4603 to the mismatch sampling mode state.

2. Set the Match Control Register 4103 to select the points to be matched and the time of the match.

3. Set the timeout Counter Register 41TOCR-5-- 41TOCR-0 to the binary number indicating the number of machine cycles that are to elapse before performing the match.

4. Reset the six bit Timeout Counter 4109 to the "all zeros" state.

5. Enable the Timeout Counter 4109 to be incremented once every machine cycle by setting the flip-flop 41PCTO, 41TOI, and 41ISTO.

Once the Mode Control Register 4603 is placed in the mismatch sampling mode, an incrementing pulse appears on order cable conductor 41TOC-INC once every machine cycle (with an exception subsequently noted herein), and the Maintenance Decoder 4608 examines the output conductor 41SQC of the Timeout Match Circuit 4108. A signal appears on 41SQC when the specified number of machine cycles have elapsed and the desired "samples" are obtained in that cycle by gating the selected match points to the Match Registers AR0 3105, DR0 3118, AR1 3605 and DR1 3617 of both central controls.

The mismatch sampling mode serves in the running of test program sequences for diagnosis in which the results of the test are "sampled" and thereby retained for subsequent examination in the match registers of both central controls.

In some instances the "mismatch sample" sample would be made prematurely if additional machine cycles were inserted by the Program Store Correct-Reread Sequencer 5301 or the Call Store Reread Sequence Sequencer 5700 for correction and/or rereading of program words and/or data within the sequence being sampled. An optional feature is therefore provided in the Central Control 101 wherein the Timeout Counter 4109 is not incremented in the mismatch sampling mode whenever additional machine cycles are inserted by the Program Store Correct-Reread Sequencer 5301 or the Call Store Reread Sequencer 5700. This option is obtained whenever a "1" appears in a particular bit position of the DAR word of the EMMS order; the appearance of this "1" causes the flip-flop 41EETO to be set in the execution of EMMS order. Setting 41EETO causes the incrementing signal to appear on order cable conductor 41TOC-INC only in the machine cycles in which neither Program Store Correct-Reread Sequencer 5301 nor the Call Store Reread Sequencer 5700 are active.

This mismatch sampling mode is also used to obtain samples in specified machine cycles during which the Program Store Correct-Reread Sequencer 5301 or the Call Store Reread Sequencer 5700 are active. Accordingly, the feature just described above is optional, and by placing the flip-flop 41EETO in the "0" state the above-described feature is not obtained.

Directed Match Mode

The directed match mode also may be employed when the central controls are operating in the in-step mode and generates a repeated matching of one or two selected match points as selected by the state of the Match Control Register 4103. The state of the bits 46HM, 46I, 46E and 46F of the mode control register can be placed in specified states to obtain the previously described corresponding options. The directed match mode, for example, serves to continuously examine selected test points concurrently with test program sequences to determine what step of the program sequences (and hence the specific location of a corresponding circuit trouble in one central control) at which a mismatch occurs.

Placing the Central Control 101 in the Off-Line Mode

The remaining maintenance matching modes to be described may be used in conjunction with the operation of the standby central control in the "off-line" mode wherein the standby central control executes test program sequences, and matching modes are provided to "observe" the progress of these tests. In the modes to be described the matching mode is, in most instances, operative in both central controls so that the active central control can be alerted when the matching determines the occurrence of a preselected match condition. It is possible, however, to operate the matching modes described below "independently" since information being matched in one central control need not necessarily be transmitted to the other central control.

To place the standby central control in the off-line mode when the central controls have previously been in step the active unit first "stops" the standby unit by activating the Stop Sequencer 400 in the standby central control. Then the Central Control 101 interconnection configuration of the Program Store 102, Call Store 103 and communicating buses is rearranged to provide independent active and standby control processors. The standby central control can then be "initialized" by control word writing the proper data and code-addresses into the Match Control Register 4103, the Mode Control Register 4603, the Program Address Register 4801, et cetera, as required. Once these steps are completed the standby central control can be restarted to initiate execution of its test sequences.

Preset Match

The preset match is employed to repeatedly match selected points in the standby central control with specified constants. When a match occurs, its detection results in gating actions performed under control of the Maintenance Decoder 4608 as specified by the state of the Mode Control Register 4603.

After stopping the standby central control the constants to be matched are placed in the DR0 Match Register 311S and/or the DR1 Match Register 3617 of the active central control. The same constants are placed in the AR0 Match Register 3105 and/or the AR1 Match Register 3605 of the standby control and then the required information is placed in the Mode Control Register 4603 and the Match Control Register 4103 of both central controls to specify a preset match and the selected points and times for matching.

The AC Bus Matching Mode

The AC bus matching mode is employed to match the store responses appearing on the duplicate buses of the Program Store Response Bus System 6500 and the Call Store Response Bus System 6501. This mode serves to permit matching of the store responses when the standby central control is not running and therefore not receiving responses from the Program Store 102 or the Call Store 103. In this instance only the Maintenance Decoder 4608 of the active central control need be employed. The Mode Control Register 4603 is placed in the required state to obtain AC bus matching, and bits 41P ₀₂ , 41P ₀₁ , 41P ₀₀ indicate the selection of response buses to be set. As shown in FIG. 70 the duplicate response buses are each directly transmitted to a pair of the match registers. For example, pulses appearing on the "0" bus 70CSBO of the Call Store Response Bus System 6501 may be stored in the DR0 Match Register 90DR0 for matching; a like path would be enabled from the "1" bus 70CSB1 of the Call Store Response Bus System 6501 to the AR0 Match Register 70AR0.

The state of the Match Control Register 4103 selects the buses for matching as follows:

41P ₀₂ , 41P ₀₁ , 41P ₀₀ = 011

Bits 0-19 of each program store response are examined in Match Circuit "0," and bits 20-43 of each program store responses are examined in Match Circuit "1."

41P ₀₂ , 41P ₀₁ , 41P ₀₀ 011

Each call store response is matched in Match Circuit "0," and bits 20-43 of each program store response are examined in Match Circuit "1."

Break-Point Mode

The break-point mode serves, for example, to "monitor" test programs being executed in the off-line mode in the standby central control. In this mode the Program Address Register 4801 of the standby central control may be repeatedly matched with a present constant; the matching can be performed in both central controls if required. Thus the central controls can be "alerted" by means of the break-point matching mode whenever program control advances or transfers to a program order word in which the corresponding memory code-address equal the preselected constant. Memory code-addresses formed in the Index Adder 3407 and placed in the Index Adder Output Register 3401 can also be independently or concurrently monitored in the break-point mode. As previously noted herein, the states of 46PB and 46CB serve to select the Program Address Register 4801 and/or the Index Adder Output Register 3401 to be monitored by the break-point mode. When a match is detected the Maintenance Decoder 4608 generates an order cable signal to set a maintenance interrupt source flip-flop 52BPI. Setting this flip-flop results in a G level interrupt to be executed under control of the Interrupt Sequencer 4901. This interrupt causes the Central Control 101 to enter "breakpoint-interrupt program sequences" which carry out the selected maintenance function as determined by the detected match.

In conjunction with the break-point mode flip-flop 46MS of the Mode Control Register 4603 may be set to obtain the "snapshot" option. The "snapshot" gating actions occur within one machine cycle after the detection of a break-point match of the contents of the Index Adder Output Register 3401 and/or the Program Address Register 4801. The "snapshot" consists of executing the preset match for only one machine cycle; thus the state of selected points within a central control at the time of the occurrence of the break-point match may be stored in the DR0 Match Register 3118 and/or the DR1 Match Register 3617. The "snapshot" information is also transmitted to the other central control and may be placed in the AR0 Match Register 3105 and/or the AR1 Match Register 3605, respectively, therein whenever that central control is operating with the same matching mode.

The Transfer Record Mode

The transfer record mode is provided as a tool for the "debugging" of program sequences. In this mode whenever a transfer is executed, the execution of that transfer is to be recorded in a reserved block of memory in the Call Store 103 with pertinent information such as the code-address corresponding to the location in memory of the transfer order. The execution of a transfer order in Central Control 101 results in either (1) the activation of the Transfer Sequencer 4401 or, (2) the appearance of the ENTJ order in the Order Word Register 3403. Corresponding order cable signals inform the Maintenance Decoder 4608 of the transfer; in response the contents of the Auxiliary Storage Register 4812 and the Index Adder Output Register 3401 are placed in the DR0 Match Register 3118 and the DR1 Match Register 3617 respectively. The contents of Auxiliary Storage Register 4812 as retained in this instance is the code-address of the "advance" program order immediately following the executed transfer order. The location of the executed transfer order is therefore obtained by decreasing the code-address stored in the DR0 Match Register 3118 by a count of one.

When the execution of a transfer order is detected in the Maintenance Decoder 4608 when the transfer record mode is operative an order cable signal is generated to set the interrupt source flip-flop 52TRI. Setting the 52TRI flip-flop causes a G level interrupt to be generated. Program control is transferred to the first step of "transfer record interrupt" program sequences. These program sequences "record" the pertinent information in the Call Store 103 including the code-address of the memory location of the transfer order and the code-address of the memory location of the transfer order and the code-address of the memory location of the first program order of the sequence to which the transfer is to be made. Program control is then returned to the interrupted program and the monitoring of that program by the transfer record mode continues. Subsequent examination of the record of all executed transfer orders permits the determination of the entire sequence of orders executed in the program sequences under test; any "misstep" can therefore be determined and subsequently corrected.

Reading Data from the Standby Central Control

The directed match mode or the preset match may be employed to "read" data appearing in those flip-flop registers of the standby central control to which the matching circuit has access. These modes serve in place of control reading access to the standby central control, but require that the Match Control Register 4103 and the Mode Control Register 4603 in the standby central control be placed in specific states to obtain the required reading and transmit that reading to the AR0 Match Register 3105 or the AR1 Match Circuit 3605 of the active central control. A limited alternate reading access to the standby central control is obtained by setting the CPD control status flip-flop 55B-TST in both central controls. When 55B-TST is set the contents of the Data Buffer Register 2601 in the standby central control are transmitted once every 5.5-microsecond cycle to the AR0 Match Register 3105 of the active central control; in this mode the contents of the Match Control Register 4103 and the Mode Control Register 4603 have no control of the maintenance decoder gating actions.

This "B-TST mode" serves to permit a check to be made of control writing operations directed to the standby Central Control 101. This check serves to determine that the control data at least was received and registered in the Data Buffer Register 2601 of the standby unit. It is therefore useful for the verification of control writing operations in the face of circuit troubles which preclude the normal access to the Mode Control Register 4603 and/or the Match Control Register 4103 of the standby central control.

Control of the Time-out Counter (4109)

As previously indicated, the Time-out Counter 4109, the time-out counter register 41TOCR-5...41TOCR-0, and the Time-out Match Circuit 4108 serve in the mismatch sampling mode as the machine cycle counter. These circuits are controlled by the states of the match control register flip-flops 41PCTO, 41ISTO, and 41ITOI to alternatively serve one of three functions. These are:

1. As a monitor of the activity of a selected plurality of the sequencers;

2. As the cycle counter for the mismatch sampling mode; or

3. As a "timer" for use as required in the maintenance program sequences.

In all of the above-mentioned uses a predetermined number is placed in the time-out counter register 41TOCR-5...41TOCR-0, and the Time-out Counter 4109 is repeatedly incremented according to the state of the above-mentioned flip-flops. When the binary number in the counter becomes equal to the number in the register the Time-out Match Circuit 4108 responds with a signal on its output conductor 41SQC. The occurrence of a signal on 41SQC is recorded in the flip-flop 41SHTO for possible further reference, and other gating actions may also occur according to the states of the flip-flop 41ITOI and the Mode Control Register 4603.

The first use listed above is the one employed in most instances and is obtained by setting all of the flip-flops 41ISTO, 41ITOI, and 41PCTO to the "0" state. In this state a signal is generated on 41SQC whenever one or more of a selected plurality of sequencers with Central Control 101 have been made active for an excessive number of machine cycles. This trouble condition signal is transmitted to the Order Combining Gate Circuit 3901 and results in the enabling of order cable conductor 57EA GO. The Emergency Action Sequencer 5702 responds as described subsequently herein to carry out the required remedial steps.

In the second use listed above all of the flip-flops 41ISTO, 41ITOI, and 41PCTO are set to the "1" state. Setting 41ISTO inhibits the incrementing of the counter in response to the active states of the above-mentioned plurality of sequencers; setting 41PCTO causes the Time-out Counter 4109 to be responsive to the incrementing signals generated under control of the mismatch sampling mode; and setting 41ITOI prevents the occurrence of a match signal on the conductor 41SQC from activating the Emergency Action Sequencer 5702.

In the third use the flip-flops 41ISTO and 41PCTO are set, but the mismatch sampling mode is not in force. The state of the flip-flop 41SHTO indicates whether or not a predetermined number of machine cycles have elapsed, and this flip-flop can be examined with a normal memory reading order. When the result of the match condition requires the activation of the Emergency Action Sequencer 5702, then the flip-flop 41ITOI must be placed in the "0" state; otherwise the flip-flop should be placed in the "1" state.

Maintenance

A commercial telephone switching system is measured on the basis of both subscriber satisfaction and economic considerations. The illustrative data handling system comprises many major elements or subsystems and, generally, these major elements or subsystems are time-shared by a large number of subscribers and by the maintenance functions of the system. Accordingly, a failure in any of the major elements or subsystems may result in complete system failure or severe degradation of service.

In prior art electromagnetic telephone switching systems, such as the Bell System crossbar systems, a plurality of control circuits, i.e., markers are provided in sufficient numbers to serve the traffic requirements of the switching center. Each marker is time-shared by a large number of lines and trunks. However, in such arrangements any marker may serve any line or trunk and the loss of a single marker, or of a relatively few markers of the group, results only in a reduction in system traffic handling capacity and such a loss is not fatal to system operation.

Subscriber satisfaction demands that calls be handled accurately without unreasonable delays. Further, a commercial telephone switching system must be continuously available during all hours of the night and the day.

Before describing the measures which we have taken to insure subscriber satisfaction in an economically feasible system, it is necessary to define a number of terms which will be employed in the following description:

System Dependability, as employed herein, is a measure of the system's ability to continue to accurately perform its assigned functions (both call processing and maintenance), even in the presence of component and subsystem failures.

Maintainability, as employed herein, is a measure of the ease with which component and subsystem failures can be detected, diagnosed, and repaired.

Reliability of an item, i.e., component (as opposed to a subsystem) is a measure of the probability that the item will perform a specified function for a required period of time without a failure.

System dependability requires that even though the system may experience both component and subsystem failures, the existence of these failures is not reflected in the service which is rendered to a subscriber.

Maintainability is closely related to the economics of a switching system since a system which is easily maintainable requires a minimum of operating manpower. In addition, maintainability is also directly related to system dependability. That is, if a system has a high degree of maintainability, system components and subsystems are out of service a minimum amount of time, and it is recognized that subsystem down-time must be minimized if duplication of facilities is to be effective. That is, statistically two subsystems may fail simultaneously or within an extremely short period of each other. Therefore, it is important that, once a subsystem fault has been recognized, this fault be cleared and the subsystem returned to readiness to provide effective subsystem redundancy.

We have economically achieved system dependability by a number of measures which we will now describe. Certain of these measures are similar to techniques employed in prior art systems. However, as will be seen from the following description, even where similar measures are employed, we have devised improved techniques for implementing these known measures.

The first and most obvious measure to achieve system dependability is redundancy or subsystem duplication. As in any telephone switching system, certain redundancy or equipment duplication is inherent in a subsystem. For example, a telephone switching network provides inherent redundancy both in the switching paths which serve the individual subscriber lines and in the trunks and service circuits which are always provided in groups large enough to handle the system traffic requirements. For example, each subscriber's line has access to four A links in the line switch frame of the line link network in which that subscriber's line is terminated. Accordingly, in the event of a failure of one of the crosspoints which serves to connect a subscriber's line to a particular A link, there remain three other paths available for providing connections to that subscriber. Therefore, a plurality of paths remain available to connect the subscriber to the midpoint of the network, i.e., to the junctor terminals of the line junctor switch frame.

Similarly, since it is possible to have a plurality of simultaneous connections to any given trunk group or to any given type of service circuit, both trunk circuits and service circuits are provided in groups rather than on an individual basis. The loss of a single trunk circuit or a single service circuit, therefore, will not cause system failure, but rather merely decrease the system traffic handling capacity of that one particular trunk group or service circuit group.

It should be noted that, as is the practice in other telephone switching systems, apparatus which is individual to a subscriber is not duplicated since failure of this equipment affects the service to a single subscriber. Furthermore, the apparatus which is provided on a per subscriber basis is generally extremely rugged and reliable and therefore does not pose a major problem in providing system dependability.

In this illustrative embodiment entire subsystems or portions of subsystems are duplicated to provide system dependability. The following is a summary of the various subsystems of our switching system which is an illustration of a data handling system and the duplication employed with respect to each of these subsystems.

1. Central Control 101 -- Central controls are always provided in pairs. Further, the more important input and output communication paths (buses), are duplicated and provision is made for switching between certain duplicated buses at system cycle speeds (within one basic 5.5-microsecond system cycle).

2. Program Store 102 -- Program stores are provided in accordance with the semi-permanent memory capacity requirements of the system. However, there are always at least two program stores employed in a system to provide duplicate copies of the information stored. Further, as in the case of the central control, both the input and output communication paths (the buses which connect the program stores to central control) are duplicated and provision is made for rapidly switching between both input and output buses.

3. Call Store 103 -- The number of call stores employed is based upon the temporary memory requirements of the system. However, again there are always at least two call stores employed in a system and in the absence of trouble all of the information stored is duplicated. Furthermore, both the input and the output communication paths are duplicated.

4. Network Units -- The network control and supervisory units comprise the Network Controllers 122, 131; the Network Scanners 123, 127, 135, 139; and the Network Signal Distributors 136, 140. The network controllers are provided in pairs and these pairs are each associated with a relatively small segment of the network. Further, one controller of a pair normally controls approximately one half of its associated network, while the other member of the pair normally controls the remaining portion of the network. However, in the event of failure of one member of a pair, the other member may be called upon to control the entire associated network portion. Similarly, the network signal distributors are provided in pairs and normally one member of the pair of signal distributors serves a first portion of associated circuits, while the other member serves the remaining portion of associated circuits. Again, however, in event of failure of either of the members of the pair, the remaining member may be called upon to control all of the associated circuits. This is true both in the case of the Signal Distributor 128 which serves the Junctor Frame 126 and the Signal Distributors 136 and 140 which serve the universal trunk frame and the miscellaneous trunk frame, respectively.

The Network Scanners 123, 135, and 139, are not duplicated in their entirety. The ferrod matrix which comprises a plurality of ferrods which are individual to the supervised circuit are not duplicated. However, the access circuitry which comprises core matrices for interrogating the ferrods and the control circuitry associated with the individual core matrices are completely duplicated as a failure in either a core matrix or its associated control circuitry would seriously affect system operation.

Further, in the case of all of the network elements, namely, the network controllers, the network scanners, and the network signal distributors, duplicated command communication paths are employed; and in the case of the network scanners a pair of scanner response communication paths are also provided.

5. Master Scanner 144 -- The master scanner comprises a number of independent scanners sufficient in number to serve the system capacity. However, entire scanners are not duplicated, but rather the arrangement set forth with respect to the network scanners is followed.

6. Central Pulse Distributor 143 --Central pulse distributors are provided in numbers sufficient to serve the traffic handling capacity of the system. There is 9 complete duplication of central pulse distributors. Further, all of the central pulse distributors are connected to the Central Control 101 by means of a duplicated command communication bus system.

7. Miscellaneous Units -- The Automatic Message Accounting Apparatus 147, the Program Store Card Writer 146, and the Teletype Unit 145 comprise the miscellaneous units. The Automatic Message Accounting facilities 147 are provided in duplicate and there are a plurality of teletypewriters. Certain of the teletypewriters are assigned specific tasks such as maintenance, traffic records and service while others, which are primarily employed for maintenance, may on request be used for any of the normal teletypewriter functions. However, the Program Store Card Writer 146 is not duplicated. Furthermore, all of the miscellaneous units employ the duplicated command transmission paths which serve the various network units and there is provision for rapidly switching between the input communication paths.

As seen from the above summary in the illustrative embodiment, system elements which affect a single line are not duplicated. There is inherent redundancy in certain other portions of the system, for example, in the network and the trunk circuits and service circuits. However, major elements, the failure of which would affect a large number of subscribers or would cause either a major degradation in service or a complete failure of service, are duplicated.

The manner, however, in which the duplicated facilities of our system are pressed into service advantageously differs markedly from the arrangements employed in prior art systems. That is, in prior art telephone switching systems and, similarly, in data processing systems which are somewhat analogous to our invention, subsystems which are duplicated are generally categorized as regular and standby and such subsystems are connected to and disconnected from other system subsystems by way of either manual switches or multicontact relays. These arrangements are not satisfactory in a system such as ours as the time required to switch between subsystems is inherently too long to be practical since not only is system data processing capacity or traffic handling capacity markedly decreased, but, also, there may be a substantial loss of important transient input data. For example, if dial pulse or TOUCH-TONE scanning is interrupted for periods of time sufficient to permit manual or relay switching of subsystems, calls are mutilated and this is reflected in subscriber dissatisfaction. Furthermore, mechanical contact switching of subsystems may generate random noise on the switched conductors which can introduce errors in system operation.

Accordingly, in our system a number of private communication bus systems provide the necessary input and output communication paths to the various subsystems and these communication paths are transformer coupled to both the subsystem sources and the subsystem loads. Transformer coupling serves to isolate subsystem faults from the communication paths serving that subsystem, the connecting subsystems and the duplicate of that subsystem.

Furthermore, the use of transformer coupled communication paths permits different subsystems to address a particular communication path without incurring switching time delay and permits addressed subsystems to accept commands over either one of a pair of duplicated communication paths again without incurring switching time delays.

In addition to equipment redundancy, a number of other system measures are employed in this one illustrative embodiment of our invention to enhance both system dependability and system maintainability. These measures may be divided into two major classes, each of which includes a number of subclasses. The two major classes are (1) hardware measures and (2) program measures.

Both of these classes include equipment checks which provide indications of trouble and, also, both of these classes include remedial steps which are calculated to keep a system running even in the presence of a detected trouble. The program measures also include actions which serve to not only isolate faults to a particular system or subsystem but also serve to accurately locate a fault within a subsystem. These more detailed program actions are directly reflected in the evaluation of the maintainability of our system and, as previously explained, are indirectly reflected in the dependability of our system as the rapid localization of trouble leads to rapid repair of a fault and thus makes duplicate subsystems available for service a high percentage of the time.

We have previously explained above herein the hardware checks which are performed on the various subsystems of our system and have noted that program checks are employed also to detect troubles. The hardware checks will not be discussed at this time. However, further reference to the details of these checks will be made later herein as will a more detailed reference be made to the program checks which we employ. Both of these checks, i.e., hardware checks and program checks, lead to indications which are called "detected trouble." The action paths which are followed in the presence of hardware check and program check detected troubles are quite different. However, both of these paths merge at a point in the sequence at which a transfer is made to a nondeferrable fault recognition program.

If the detected trouble is in the operation of a Call Store 103 or a Program Store 102 the path to a sequence action called "retrail" is taken and if a successful call store or program store action accompanies a retrail action, the active combination of subsystems, i.e., call stores, program stores, central controls, and buses, is considered to be acceptable (pass) and the current sequence of program actions is continued. It should be noted, however, that even though a call store or program store retrial may be successful, the fact that a retrial was necessary is recorded and a large number of retrial actions within a limited period of time will lead to maintenance actions which are calculated to find the cause of repeated call store and program store reading errors or call store writing errors. If the call store or program store retrial action does not pass, a path is taken which leads to the maintenance action of setting an interrupt source flip-flop. This action is similarly taken when the detected trouble was other than a call store or program store trouble. There are a plurality of interrupt source flip-flops and these flip-flops are individual to the various sources of trouble.

The setting of an interrupt source flip-flop enables the Interrupt Sequencer 4901 which causes the current program sequence to be interrupted and to store in a reserved area in the Call Store 103 data which is found in a number of the registers of central control. Such data is preserved to permit in certain instances a subsequent return to the interrupted program where such return is both feasible and advisable, and in other cases to provide information which may be helpful in the course of the fault recognition program.

If the interrupt source flip-flop which is set indicates that the detected trouble is in one of the elements of the Central Processor 100, namely, the Central Control 101, the Program Store 102, or the Call Store 103, the Emergency Action 40 Millisecond Timer of the Real Time Check 5703 is enabled before transfer is made to the fault recognition program. When the interrupt source flip-flop which is set indicates a detected trouble in other than the Central Processor 100, a transfer is immediately made to the fault recognition program without enabling the emergency action timer.

If the detected trouble is indicated to be in either the Central Control 101 or the Call Store 103, a transfer is made ti the fault recognition program located in the Program Store 102. However, if the detected trouble is in the Program Store 102, steps are taken to operate the Central Control 101 by means of a program which is found in the Call Store 103. That is, if a trouble is detected with respect to the operation of a Program Store 102, it does not appear reasonable to attempt to perform a fault recognition program based upon information derived from a Program Store 102; therefore, a relatively short fault recognition program is obtained from the Call Store 103. The call store program fault recognition sequence is initiated by enabling the Call Store Program Sequencer 5302.

When trouble is detected by means of program checks, a transfer is directly made to the fault recognition program which is specified by the detected trouble. It is not necessary to initiate an interrupt as was required when a hardware check detected trouble.

The fault recognition programs have the highest execution priority in our system as they are calculated to recover the system's call processing to The fault recognition programs, however, are held to a minimum length to avoid disrupting call processing and are limited to steps which isolate the faulty subsystems and the necessary control actions which serve to remove the faulty subsystems from the active combination of subsystems. The first function of a nondeferrable fault recognition program is to determine whether the detected trouble represents a system error or a system fault. If the trouble cannot be reproduced by means of the fault recognition program, the detected trouble is considered to be an error and the system returns to call processing. However, before returning to call processing, a record is made which indicates that an error did occur since this information is required to determine whether or not a high error rate is occurring. As seen above, whenever an error occurs, it is necessary to transfer to a fault recognition program and this transfer reduces the call processing capacity of the central control. Therefore, a high error rate detracts from the efficience of our Central Processor 100.

If the fault recognition program is capable of reproducing the detected trouble, a fault is indicated and the fault recognition program proceeds to isolate the fault to a specific subsystem. It should be recognized that the fault may be found in either the active or the standby subsystem and that different program actions are required to recover system call processing.

If the fault occurs in a Central Control 101, a Call Store 103, or a Program Store 102, only a limited period of time (40 milliseconds) is allowed for the fault recognition program to isolate the fault to a specific subsystem. If the fault recognition program cannot isolate the fault within the prescribed period of time to a specific subsystem and it is known that the fault lies in the Central Control 101, Call Store 103, or Program Store 102, the fault recognition program records a request to subsequently initiate a deferred fault recognition program which will isolate the fault to a specific subsystem and then the nondeferrable fault recognition program rearranges the configurations of the central processor equipments which are related to the subsystem, i.e., Central Control 101, Call Store 103, or Program Store 102, which has an indicated fault.

If the nondeferrable fault recognition program isolates the fault to a specific subsystem it must be determined whether the subsystem which has failed is in the active or standby combination of equipments and appropriate action taken thereafter. If the active unit fails, the program serves to switch the standby unit into the active combination of equipments since this change is required to recover the system's call processing ability.

After a faulty subsystem has been switched to standby or after it has been determined that a standby subsystem is faulty, the fault recognition program operates trouble indicating flip-flops within the faulty subsystem or, in the case of a Network Controller 122, 131 or Signal Distributor 128, 136, 140, sets the faulty subsystem to a quarantine mode of operation.

Further, the nondeferrable fault recognition program marks a flag in the job supervisory register associated with the deferred fault recognition program which is required to pinpoint the trouble within the faulty subsystem.

After the call processing ability of the system is recovered by means of a program rearrangement of configurations of elements of the Central Processor 100 either after registering the request for a deferred fault recognition program or after isolating the fault to a particular subsystem, the fault recognition program resets the Emergency Action 40 Millisecond Timer of 5703. This was enabled when it was determined that a trouble had been detected which involved one of the elements of the Central Processor 100. If the call processing ability of the system is not recovered prior to time-out of the timer of 5703, specific emergency actions, which are described elsewhere herein, result in a B level program interrupt and ordered rearrangements of Central Control 101, Program Store 102, and their interconnecting buses.

When the Emergency Action 40MS Timer is reset before the end of its time-out period, the fault recognition program causes a transfer to a "Restart Program." The restart program, in accordance with prescribed rules, determines whether it is both feasible and advisable to return to the interrupted program. If return to the interrupted program is not advisable, the restart program will select one of several reference points within the H level program, the J level program, or the base level executive program to reinstitute call processing. If it is determined that it is possible to return to the interrupted program, the Go Back Sequencer 5300 is enabled to, on a wired basis, reinstitute call processing.

An example of a situation wherein it is feasible to return to the interrupted program is where a standby subsystem is found to be faulty; therefore, there has been no possibility of mutilation of data or either misdirection or misinterpretation of system commands. An example of an instance wherein it is not advisable to return to an interrupted program is where an active central control was found to be faulty and therefore there may be problems in accurately returning to the interrupted program. If the change from the fault recognition program to call processing is accomplished by way of the restart program rather than by way of the Go Back Sequencer 5300, the program serves to perform similar functions to those which the Sequencer 5300 performs on a wired basis; that is, the interrupt activity flip-flop is reset and the program then determines an appropriate reference point within one of the call processing levels H, J, or L to reinstitute call processing. The program places the code-address of the reference point in the Program Address Register 4801 and transfers to the program.

The recovery of call processing at the reference point does not require any prior history such as is required when an interrupted program sequence is reentered.

Control Word Orders

Control orders are designed for the communication of special commands from the active central control to the Program Store 102, the Call Store 103 and the standby central control. Control writing orders are employed to set and reset selected status and control flip-flops in the unit addressed. Control reading orders provide a means of reading the states of these and other flip-flops and test points within the Program Store 102 and the CALL Store 103.

Control orders resemble memory orders in that their execution includes the transmission of commands and data and the reception of responses between the central control and the memory via the same command and response bus systems. Further control reading orders are Move orders which serve to read data from an addressed unit and place the reading in a flip-flop register specified in the order; control writing orders, in most instances, cause data to be moved from a specified flip-flop register to a location in memory specified in the transmitted command. These commands include the code-address format for memory reading and writing commands the code serves to select the unit within the Program Store 102 or the unit within the Call Store 103.

As noted previously herein the memory within each unit in the Program Store 102 and the Call Store 103 is divided into a G block and an H block; corresponding to each block is a discrete code. Each G(H) block of information is duplicated as the H(G) block in another store unit, and duplicate blocks are assigned the same code.

Accordingly, assigned to each store unit are two codes to which the store is responsive in receiving normal mode commands; and further for each code combination there are two store units which may respond. Control word commands are characterized by the control mode combination of mode signals; in this mode only the store unit which contains the H block corresponding to the code of the transmitted code-address is responsive. Thus for the purpose of control writing or reading the code of the H block of a store unit may be thought of as the "name" of the unit; control commands are thereby directed to only the one store unit specified in the code. Control writing commands are transmitted to the standby central control via the Call Store Address Bus System 6401 as may be noted in FIGS. 10 and 11 and FIGS. 64 through 69. A discrete code is assigned to the standby central control, and control writing commands transmitted to the Call Store Address Bus System 6401 include this code in the code-address to distinguish from a control writing command addressed to the call store.

Writing of Control Words into the Standby Central Control

As previously mentioned, certain of the control writing orders BN, FN, JN, KN, LN, XN, YN and ZN are employed to place data within control locations in the Call Store 103 and the standby central control. A control mode call store writing command is generated in such instances, and the standby central control or a specific unit in the Call Store 103 is enabled for control writing according to the code of the transmitted command.

To carry out control writing the standby central control must first be stopped, as previously described herein. Control writing is then initiated by executing one of the orders BN, FN, JN, et cetera and specifying the code assigned to the standby central control. Executing this order does not cause data appearing on the Call Store Write Data Bus System 6402 to be received by the standby central control. Instead, the standby unit receives the data from the Call Store Response Bus System 6501 in the following 5.5 microsecond cycles. The active central control provides this data by immediately following the execution of the control writing order with the execution of a memory reading order which reads a location in the Call Store 103; this location so read contains the data to be moved to the standby central control. The standby central control completes the control writing operation by accepting this reading and placing it in a flip-flop register specified in the address of the control writing command.

The response to control word commands within the standby central control may be understood with the aid of FIGS. 10 through 63, and in particular FIGS. 10, 11 and 18.

Call store commands generated within one central control unit and transmitted via one or both of the Cable Drivers 1002 and 1001 appear on the "0"10 bus 1004 and/or "1" bus 1003 of the Call Store Address Bus System 6401. The call store command is then transmitted to the Call Store 103 and to the other central control unit via the Cable Receivers 1102 and/or 1101, respectively, and the command appears at the Control Mode Bus Selection Gates 1100. The standby central control utilizes the Control Mode Bus Selection Gates 1100 in conjunction with the CPD controlled status flip-flop 55CW to accept call store commands from the "0" bus 1004 or the "1" bus 1003 by enabling AND gates 1104 and 1108 or the AND gates 1103 and 1107, respectively. If Flip-Flop 55CW is reset a signal appears on 11CW0 to select the "0" bus 1004; otherwise a signal appears on 11CW1 to select the "1" bus 1003.

A control writing command directed to the standby central control includes the following combination of signals, where a "1" indicates a signal and a "0" indicates no signal: ##SPC5##

and a control address A0 through A5.

The presence of signals on all of HM, GM, K5, K4, K3, and K2 is determined in the AND gate 1106 or the AND gate 1105; if signals are present on all of these call store command leads the OR gate 1110 is enabled to generate a signal on the KACT conductor 1113. The remaining control writing command signals are transmitted through the AND gate 1104 or AND gate 1103 and the OR gate 1109 to the bus 1112.

The standby central control unit is made responsive to control writing commands by the setting of the CPD controlled status flip-flop 55 CWC. A signal appears on 18CWC only when this flip-flop is set, and accordingly 55CWC must be set for the control writing command to be registered in the Control Word Decoder Flip-Flops 1803. Furthermore, information may be registered in these flip-flops only if a control writing command is not currently being processed in the standby central control; the availability of the Control Word Decoder Flip-Flops 1803 is indicated by a signal on the conductor 18EN. A concurrence of signals on the conductors 18CWC and 18EN enables AND gates 1802, 1800, 1801 and 1814 which serve to transmit call store commands to the Control Word Decoder Flip-Flops 1803 for storage therein.

When the call store command does not contain the previously listed combination of signals then the EN Flip-Flop 1806 remains reset. A signal appearing on the conductor 18EN enables a clock pulse 14T16 to be transmitted through the AND gate 1809 and the OR gate 1811 to reset the Control Word Decoder Flip-Flops 1803 just prior to the time of arrival of a call store command in the next 5.5-microsecond cycle. The standby central control is therefore continually examining call store commands to determine if any such command is directed thereto. When such a control writing command arrives the reception of this command in the Control Word Decoder Flip-Flops 1803 is followed by the enabling of conductors 1815, 1816 and 1817. If, further, the standby central control is stopped as indicated by a signal on the order cable conductor 18SSTOP, then the AND gate 1818 is enabled permitting the clock pulse 12T14 to set the EN Flip-Flop 1806.

Setting the EN Flip-Flop 1806 causes the standby central control to carry out its part of a control writing operation by retaining the control writing command in the Control Word Decoder Flip-Flops 1803 for a 5.5-microsecond cycle. That is, the reset input to these flip-flops does not reappear until the control writing operation is completed.

In the control writing the Control Word Decoder 1804 is enabled by signals appearing on the outputs of the EN and S2 Flip-Flops 1806 and 1808 to translate address information contained in the A5 through A1 flip-flops of the Control Word Decoder Flip-Flops 1803. The translation consists of corresponding combinations of signals on the IAR, OPOW, RESETAD, et cetera conductors 1813 of the Miscellaneous Input Cable 1812. These signals then transmit data from the Call Store Response Bus System 6501 to the Data Buffer Register 2601 bits 22 through 0 of the Buffer Order Word Register 2410, or bits 23 through 43 of the Buffer Order Word Register 2410. When the information is to be placed in another register in Central Control 101 it is then transmitted from the Data Buffer Register 2601 or the Buffer Order Word Register 2410 to the appropriate register. When, for example, the selected register is the index adder output register, then the data is first placed in the Data Buffer Register 2601. It is transmitted from there directly to the Masked Bus 2011; then it is transmitted through the Augend Register 2908 and the Index Adder 3407 to the Index Adder Output Register 3401.

The selected register is specified according to the address bits as follows:

A5-A1 Destination Register 00000 Data Buffer Register 2601 00001 ARO 3105 00010 DRO 3118 00011 AR1 3605 00100 DR1 3617 00101 Match Control Register (MACR) 4103 00110 Mode Control Register (MOCR) 4603 00111 Match Cycle Control Flip-Flops 5105 and 5106 and Maintenance Reply Flip-Flops 5107 01000 Maintenance Interrupt Sources 5209, 5210 and 5211 01001 H & J Clock Interrupt Sources 5604 and G Level Maintenance Interrupt Sources 5605 01010 Program Address Register 4801 01011 Index Adder Output Register 3401 01100 Logic Register 2508 01101 Bits 22 through 0 of the Buffer Order Word Register 2410 01110 Bits 43 through 23 of the Buffer Order word Register 2410 and the Order Word Register 3403 01111 Interrupt Inhibit Control Register 6002, 6003

It is to be noted that the moving of control word data in the standby central control utilizes in most instances existing gating paths; these gating paths determine the placement of the individual bits of control data in the selected register. For example, bits 20 through 0 of the control data are placed in bits 43 through 23 of the Buffer Order Word Register 2410 whenever A5 through A1 = 01110; and bits 0 through 15 of this data comprise the word placed in the Order Word Register 3403.

Whenever one of the registers AR0 3105, DR0 3118, AR1 3605 or DR1 3617 is selected to receive control word data then only twenty-three bits of that data are supplied with the memory reading transmitted from the Call Store Response Bus System 6501 to bits 22 through 0 of the Data Buffer Register 2601. In such instances the address bit, A0, retained in the Control Word Decoder Flip-Flops 1803 serves to determine the twenty-fourth bit. If flip-flop 18AO is set, then conductor 23 of order cable 2611 is enabled to transmit a "1" to the 24th bit of the Buffer Register Bus 2600; this signal is steered to the input of the 24th bit of AR0 3105, DR0 3118, AR1 3605 or DR1 3617. When the flip-flop 18AO is reset conductor 23 of cable 2611 is enabled to transmit "0" to the 24th bit of the Buffer Register Bus 2600.