05/006036

03/07/1972

01/26/1970

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Giddings & Lewis Machine Tool Company (Fon du Lac, WI)

713/500

G05B19/31; G06F7/50; G09G3/04; G09G3/10; G05B19/19; G05B19/406; G06F7/48; G06F3/14

340/172.5 235/151.11,157 318/20.060,562

3227364	Voting machine system	January 1966	Clark
3268866	Circuit arrangement for controlling switching matrices	August 1966	Van't Slot et al.
3274553	Time-division, multiplex, numericalcontrol system	September 1966	Oya
3365634	Numerically controlled electronic positioning system employing serial logic	January 1968	Centner et al.

Zache, Raulfe B.

Springborn, Harvey E.

A1. CROSS REFERENCES

This application is a continuation of applicant's copending application, Ser. No. 618,699 filed Feb. 27, 1967 and now abandoned.

I claim as my invention

1. A readout for numerical information represented by any one of a plurality of sets of digital signals in a system wherein the different sets of signals are repetitively applied to a time-shared multiconductor trunkline during respectively different preassigned time periods occurring within each of continuous, uninterrupted succession of recurring cycles, each cycle comprising a continuous, uninterrupted succession of identifiable time periods, said readout comprising in combination

2. A digital data system comprising

3. In combination with a system wherein different ones of a plurality of digitally coded signals are transmitted during a cyclically recurring succession of different, respective preassigned time periods over a common time-shared, multiconductor trunkline from a plurality of sources, the improvement comprising

4. In system wherein different ones of a plurality of digitally coded signals are transmitted during a cyclically recurring succession of different, respective preassigned time periods over a common time-shared, multiconductor trunkline from a plurality of sources, the improvement comprising

5. each AND gate having inputs connected to a unique combination of outputs of said timing signal generator for producing a timing signal during a preassigned one of the time periods within each cycle,

6. a connection from the output of each AND gate to a respective one of said plurality of output-gating means for applying gating signals to different ones of said gating means during respectively different preassigned time periods within each cycle,

7. In a digital-data system, the combination comprising

8. The system set forth in claim 5 further characterized in that said device includes means for temporarily storing digital signals passed from said trunk line by said passing means (g), whereby fleeting digital signals passed from said trunkline through said gate means are registered for a predetermined time period so as to prolong the duration of the image displayed.

9. In combination with a system wherein different sets of digital signals representing different items of information are repetitively and regularly applied to a time-shared multiconductor trunkline during respectively different preassigned time periods occurring within each of a continuous, uninterrupted succession of recurring time cycles, each cycle comprising a continuous, uninterrupted succession of identifiable time periods, said trunkline extending between a common processing device and a plurality of digital devices, the improvement comprising

10. In combination with a system wherein different ones of a plurality of digitally coded signals are transmitted during a cyclically recurring succession of respective preassigned time periods over a common time-shared, multiconductor trunkline from a plurality of sources, the improvement comprising

11. inputs connected to a unique combination of outputs of said timing signal generator, and

12. an output connected to apply differently timed output gating signals to a respective one of said plurality of output gating means during an individually preassigned time period within each cycle,

13. In combination with a system having a plurality of sources of different digitally coded signals representing different, changeable items of information, and wherein the digital signals from different sources are repetitively applied to a time-shared multiconductor trunkline during respectively different preassigned time periods occurring with each of a continuous, uninterrupted succession of time cycles, each cycle comprising a continuous, uninterrupted succession of identifiable time periods, the improvement comprising

14. each AND gate having inputs connected to a unique combination of outputs of said timing signal generator for producing a timing signal during a preassigned one of the time periods within each cycle,

15. a connection from the output of each AND gate to a respective one of said plurality of output-gating means for applying gating signals to different ones of said gating means during respectively different preassigned time periods within each cycle,

16. In combination with a system wherein different ones of a plurality of digitally coded signals are transmitted during a cyclically recurring succession of different, respective preassigned time periods over a common time-shared, multiconductor trunkline from a plurality of sources, the improvement comprising

17. In combination with a system wherein different ones of a plurality of digitally coded signals are transmitted during a cyclically recurring succession of respective preassigned time periods over a common time-shared, multiconductor trunkline from a plurality of sources, the improvement comprising

18. In combination with a system for processing and feeding to a utilization device continuous data derived from a plurality of digitally coded command signal sources, the improvement comprising

19. The system set forth in claim 12 further characterized in that the displaying means includes means for temporarily storing signals passed from said adder input trunk or adder output trunk through said third or fourth gating means whereby fleeting digital signals passed from said trunks through said gating means are registered for a predetermined time period so as to prolong the duration of the image displayed.

20. In combination with a system for transmitting digitally coded signals during a cyclically recurring succession of preassigned time periods from a plurality of sources of digitally coded signals over a first multiconductor trunkline to the inputs of a digital arithmetic processor and from the outputs of the processor over a second multiconductor trunkline to the inputs of devices utilizing digital signals, the improvement comprising

21. In combination with a system for transmitting digitally coded signals during a cyclically recurring succession of preassigned time periods from a plurality of sources of digitally coded signals over a first multiconductor trunkline to the inputs of a digital arithmetic processor and from the outputs of the processor over a second multiconductor trunkline to the inputs of devices utilizing digital signals, the improvement comprising

22. In combination with a system for transmitting digitally coded signals during a cyclically recurring succession of preassigned time periods from a plurality of sources of digitally coded signals over a first multiconductor trunkline to the inputs of a digital adder and from the outputs of the adder over a second multiconductor trunkline to the inputs of devices utilizing digital signals, the improvement comprising

23. inputs connected to a preassigned combination of outputs of said timing signal generator, and

24. an output connected to apply sequentially timed gating signals to respective ones of said first and second pluralities of gating means, each of said gating signals occuring during a different preassigned time period within each cycle,

25. In combination with a system wherein digitally coded signals are transmitted during a cyclically recurring succession of different preassigned time periods over a recurring succession of different preassigned time periods over a common time-shared multiconductor trunkline from different respective ones of a plurality of sources of digitally coded signals to a digital adder, the improvement comprising

26. The system set forth in claim 26 further characterized in that the displaying means includes means for temporarily storing signals passed from said trunkline through said input gating means whereby fleeting digital signals passed from said trunkline through said displaying gating means are registered for a predetermined time period so as to prolong the duration of the image displayed.

B. BACKGROUND OF THE INVENTION

The present invention relates in general to data-processing systems employing time-shared conductors and more particularly to a readout device for displaying data appearing on time-shared conductors.

Numerical controls, particularly for machine tools, have been an important application of computer technology to the manufacturing process. But bringing the computer to the factory floor has increased an already wide communication gap between the machine and its operator. Means must be provided to permit the average operator, not skilled in electronics or computer programming, to give instructions to the machine which will usually modify preprogrammed instructions stored on tapes and prepared from manufacturing drawings. Means should also be provided to give the operator some idea of what his control is doing, how it is reacting to his instructions, whether its more important components are operating properly.

C. OBJECTS OF THE INVENTION

A general object of the present invention is to provide a control readout for displaying information produced by and applied to several data sources and data-utilization devices without the use of individual electrical connections to each of the sources and devices to be monitored. More particularly, it is a general object of the invention to provide a numerical machine-tool-control system wherein data flows between several data sources and data-utilization devices and a central data processor on time-shared multiconductor trunklines and in which data originating from or destined for any selected data source or data-utilization device may be displayed by means of common display units.

It is a related object of the invention to permit the display selection to be made by an operator rapidly, simply, and without reference to the particular time period during which the desired data appears on the trunkline by means of a multiposition selection device whose positions are identified with the data source or utilization device to be monitored and not with the time period during which data sent from a source or received by a utilization device appears on the trunklines. A related object is to provide either in place of or in addition to such an operator's readout selector, a readout selector which is particularly suitable for use in servicing the numerical control system and which permits one servicing the system to select for display data appearing on the time-shared trunkline during any selected time period during which information appears on the trunkline.

Another principal object of the invention is to provide a numerical control system wherein data is fed from a plurality of data sources during successive preassigned time periods to a central calculating unit on a time-shared, multiconductor trunkline, wherein data produced by the calculating unit is fed to a plurality of utilization devices over a second time-shared multiconductor trunkline during successive preassigned time periods and wherein signals appearing during any preassigned time period at either the input or the output of the calculator or both may be displayed so as to test proper operation of the calculating unit.

D. BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages will become apparent as the following description proceeds, taken in conjunction with the accompanying drawings in which:

FIG. 1 is a general block diagram of a numerical control system embodying features of the invention;

FIG. 1a is a drawing layout to show how FIGS. 2a-d should be joined to form a single drawing;

FIG. 2, formed of FIGS. 2a-2d when joined as indicated in FIG. 1a, is a detailed block diagram of a numerical control system embodying features of the present invention;

FIG. 3 is a block and line diagram of a typical reversible counter shown in less detail in FIG. 2b and of a multiconductor trunkline for receiving signals therefrom;

FIG. 4 is an illustration of the different points of reference of the controlled machine and of the command signals which are applied to the machine control system;

FIG. 5a is a block and line diagram of an exemplary register of the type shown in FIG. 2a and of suitable logic gates for applying information thereto from the outputs of the adder;

FIG. 5b is a block and line diagram of a typical flip-flop used in the register of FIG. 5a;

FIG. 5c is a set of wave forms to illustrate the timing of signals applied to the flip-flop illustrated in FIG. 5b;

FIG. 6 is an exemplary partial program for the numerical control system illustrated in FIG. 2;

FIGS. 7a-7d show the various types of program gates which may be employed to derive gating signals from the timing signal generator of FIG. 2b;

FIG. 8a is a schematic diagram of a diode decoding matrix which may be used in place of the program gates illustrated in FIGS. 7a-7d;

FIG. 8b is a circuit diagram showing in detail a portion of the diode matrix of FIG. 8a;

FIG. 9 is a detailed block diagram of the adder shown in FIG. 2b;

FIG. 10a is a block diagram of the clock pulse source used in the timing signal generator of FIG. 2b;

FIG. 10b is a timing diagram illustrating the wave forms which are derived from the clock pulse source of FIG. 10a and of timing pulses which are applied to the adder of FIG. 9;

FIG. 10c illustrates the connection of additional gates for deriving from the clock pulse source of FIG. 10a the timing signals which are illustrated in FIG. 10b;

FIG. 11 is a block and line diagram of a typical 9's complement circuit which may be used in the adder illustrated in FIG. 9;

FIG. 12 is a block and line diagram of a carry signal producing network suitable for use in the adder of FIG. 9.

While the invention has been shown and will be described in some detail with reference to a preferred embodiment thereof, there is no intention that it thus be limited to such detail. On the contrary, it is intended to cover here all modifications, alternatives, and equivalents falling within the spirit and scope of the invention as defined by the appended claims.

E. GENERAL DESCRIPTION OF THE INVENTION

FIG. 1 illustrates the invention as applied to a numerical control system. The numerical control system 11 includes a plurality of data sources and data-utilization devices 13. Examples of typical data-utilization devices used in a numerical control system, and particularly in a numerical machine-tool-control system which will be described in detail hereinafter, are servoloops for moving elements of the machine in response to digital signals.

Data sources in such a machine usually include a source of digital command signals derived from punched or magnetic tape and representing desired distances and velocities at which the various servo loops are to drive their associated machine elements and also include digital devices for indicating the position and velocity of the machine elements so that by comparison of actual positions with desired positions, appropriate correction signals may be applied to the respective servo loops.

Other sources of data may include sources of digitally coded signals to permit the operator of the machine to modify instructions derived from the tape to compensate for peculiarities of his machine and of the tools employed. To effect these corrections, they are added to the command signals derived from the tape and the result is used as the command signal for the various servo loops. The servo loops themselves are operated by (1) comparing the digital signals indicating actual position of the machine elements which they control with the corrected digital command signals representing desired position and (2) applying a signal proportional to the difference to a servomotor forming part of the servoloop.

To perform the numerous arithmetic operations required for operation of the numerical control system, an adder 15 is provided. The term "adder" is used to denote an arithmetic unit capable of performing addition and subtraction, and where required, multiplication and division as well. In an important aspect of the invention, the outputs of the several data sources are connected to the inputs of the adder 15 over a common multiconductor trunkline 17, labeled AIT for Adder Input Trunk. In a similar of the outputs of the adder 15 are connected over a second multiconductor trunkline 19, labeled AOT for Adder Output Trunk, to the inputs of the various data utilization devices forming part of the block 13. Both of the trunklines 17 and 19 include a set of conductors, typically four, for each digit of a binary coded decimal number. Of course, other codes might be employed, and in that event a different number of conductors could be used for each digit. But, assuming the use of binary coded decimal (BCD) notation, if the trunklines are to have a 10-digit capacity, they would each include 40 conductors in 10 groups of four and an additional conductor for carrying a signal indicative of the sign of the number carried on the other forty conductors. In keeping with the invention, signals produced by the various data sources are applied to the adder input trunk 17 during successive preassigned time periods so that the adder input trunk is time-shared by all of the data sources in the block 13. Similarly, signals destined for delivery to the various data-utilization devices in block 13 are produced by the adder and appear on the adder output trunk during successive preassigned time periods on a time-sharing basis.

As will be described in greater detail, flow of data over the time-shared trunklines is on a cyclically recurring basis. Each step in the processing of data is assigned a time period and a total sequence of such time periods forms a major cycle in the operation of the numerical control system 11. During normal operation of the control system, the cycle is repeated over and over again. During each successive cycle, signals from a particular data source will appear on the adder input trunk 17 during a time period preassigned to that particular data source, and each data utilization device will receive signals over the adder output trunk during similar, individually preassigned time periods. It is worth noting that some of the data sources and data-utilization devices may be assigned several time periods on the trunklines during a major cycle, but these too will remain the same during all of the recurring major cycles of the system. To cause the signals to flow from the data sources to the adder input trunk 17 and from the adder output trunk 19 to the data utilization devices, individual gating means are interposed between each of the data sources in the block 13 and the adder input trunk 17, and individual gating means are also interposed between the adder output trunk 19 and various data utilization devices in block 13. To conserve space, these gating means are not shown separately in FIG. 1.

To successively enable the various gating means associated with the several data sources and data utilization devices, gating signals are produced at successive instants by a timing signal generator 21 in combination with a decoder or a set of program gates 23 and these gating signals are applied individually to the several gating means. In a preferred embodiment of the invention, the timing signal generator 21 produces, at a plurality of outputs, concurrent signals which digitally represent a cyclically changing series of numbers such as 0 to 999. The program gates in such a preferred embodiment are signal coincidence responsive gates, such as AND gates, which are operative to produce a signal at their outputs when signals are coincidentally applied to their inputs. The inputs of the various program gates are connected to different combinations of outputs of the timing generator so that as the timing generator counts through its cycle of digitally signaled numbers, gating signals are produced by the different program gates at successive time spaced instants. Since particular operations of the adder 15 will occur during preassigned time periods, certain of the decoder or program gate outputs are applied to the adder, as indicated by the conduit 25.

In accordance with the invention, a servicing readout is provided which is capable of displaying data generated by any of the data sources in block 13 and which is also capable of displaying data received by any of the data-utilization devices of block 13. In accordance with this aspect of the invention the servicing readout unit 27 includes a display unit 29. Through a first set of input-gating means 26, labeled AIT GATES, the display unit 29 is connected to receive signals appearing on the adder input trunk 17. Similarly, through a second set of input-gating means 28, labeled AOT GATES, the display unit 29 is connected to receive signals appearing on the adder output trunk 19.

Gating signals for the AIT- and AOT-gates 26 and 28 are provided on a plurality of timing lines 31, gating signals on respective lines being synchronized with selected ones of the gating signals produced by the decoder or program gates 23. In one preferred form, illustrated in FIG. 1, the synchronized gating signals on the timing lines 31 are produced by a set of fixed program gates 33, with each program gate having its inputs connected to a particular combination of outputs of the timing signal generator 21. Thus, with this arrangement, if it is desired to produce on one of the timing lines 31 a gating pulse which is in synchronism with one of the gating pulses produced by a program gate 23, one of the fixed program gates 33 will have its inputs connected to the same combination of outputs of the timing signal generator 21 to which the particular program gate 23 is connected.

It should be noted that while the above arrangement for producing synchronized gating pulses is effective, other arrangements can also be employed. Thus, instead of providing a separate set of program gates 33 for the servicing readout 27, synchronized pulses for the timing lines 31 could also be derived directly from the program gates 23. Furthermore, neither the numerical control system 11 nor the servicing readout unit 27 need employ individual program gates to derive gating pulses from the timing signal generator 21. Either a common decoder or individual decoders such as diode matrixes well known to those skilled in the art may be employed for this purpose.

Interposed between the timing lines 31 and the gates 26 and 28 are selective switching means for rendering the gates responsive to the gating signal produced on any chosen one of the timing lines. In the system illustrated in FIG. 1, the selective switching means is an operator's program gate selector 35. Means are also provided to associate each of the fixed program gates 33 not only with a particular time period, but also with a particular one of the trunklines 17 and 19 so that by selection of the timing line 31 associated with a given fixed program gate 33, a gating pulse may be applied at a desired time period to a desired one of the gates 26 and 28. Accordingly, the operator's program gate selector has two sets of outputs 35a and 35b. The outputs 35a are connected to the AIT-gates 26 through a gate 37, and the outputs 35b are connected to the AOT-gates 28 through a second gate 39. The operator's program gate selector 35 is operative to select not only the timing pulse appearing on any one of the timing lines 31, but is also operative always to apply the resulting timing pulse to a particular one of the gating means 37 and 39. Thus, for example, assuming that on a particular setting of the operator's program gate selector 35 the display unit 29 is to display information appearing on the adder output trunk 19 during the fourth time period of the major cycle of the system, the operator's program gate selector 35 will be so connected that it will apply the gating pulse appearing on the appropriate timing line 31 to the gate 39. Consequently, at the appropriate time period the gating pulse is applied to the AOT-gates 28 and the desired information applied to the inputs of the display unit 29.

The particular advantage of the foregoing portion of the servicing readout is that information appearing on the adder input trunk 17 or the adder output trunk 19 may be displayed on the display unit 29 without particular reference by the operator to either the trunkline on which the information appears or to the time period during which the information appears on the trunkline. This is made possible by the arrangement of the timing lines 31 and the operator's program gate selector 35 whereby a timing pulse can be applied to the appropriate one of the AIT- and AOT-gates 26 and 28 by a single selection since that is all that is required to select a particular one of the fixed program gates 33. Such an arrangement, however, is best where the number of signals to be displayed is limited. Thus, for example, it would be difficult to envision a program gate selector 35 which would be capable of selecting any one of 1,000 timing signals by means of a single selector switch since obviously the switch would have to have 1,000 positions.

Although the operator's program gate selector 35 might have a switching arrangement including several switches to handle an increased number of gating signals, the advantages of simplicity and quickness of selection would be diminished. However, where the display unit is to be operated by a serviceman rather than by a machine operator, flexibility and range of selection are paramount. In such a situation, it does not matter that the person who selects the signal to be displayed needs to know the time period during which it occurs and the trunk line on which it appears. Such an arrangement forms another important feature of the invention. According to this feature, instead of providing a plurality of individual timing lines, only a single timing line 41 is provided. This timing line is the output of a switchable program gate 43 which may be of the same construction as the previously discussed program gates 23 and 33. Unlike the previously discussed program gates, however, the switchable program gate 43 is not "hard wired." On the contrary, means in the form of the serviceman's time period selector switches 45 are provided to allow connection of the inputs of the switchable program gate 43 to any combination of outputs of the timing generator 21. By means of these switches, connected through line 35 to the outputs of the timing signal generator 21, the switchable program gate 43 can be caused to produce on the timing line 41 a gating pulse synchronously with any of the gating pulses produced by the decoder or program gates 23 of the numerical control system 11. Means are also provided for causing a gating signal to be applied to an appropriate one of the gates 26 and 28 in response to the timing signal appearing on the timing line 41. To this end, there is provided an AIT-AOT selector 27 having one output line 49 connected to the gate 37 and a second output line 51 connected to the gate 39. Depending upon whether the information to be displayed is on the adder input trunk or the adder output trunk, the AIT-AOT selector 47 is set to route the signal on the timing line 41, or a signal in response thereto, through the gate 37 or the gate 39 to the AIT-gates 26 or the AOT-gates 28 respectively. Of course, it will be recognized that other gating arrangements could also be employed. Thus, the output line 49 could be connected directly to the AIT-gates 26 and the output line 51 could be alternatively connected directly to the AOT-gates 28.

The number of servicing readout units will usually exceed one, and a second such unit 53 is therefore shown in block form in FIG. 1. The provision of more than one such unit permits a serviceman to determine quickly proper operation of a component in the numerical control system by simultaneously displaying on one of the readout units the input being fed to the component and on another readout unit the output produced by the component in response.

F. DETAILED DESCRIPTION

1. Exemplary Machine-Tool-Control System

a. The Machine Tool, and the Servo loops for Driving It

Although the invention may find utility in any system in which signals are transmitted on a common time-shared multiconductor trunkline, for sake of a concrete example, it will be explained in detail as part of a numerical control system for a machine tool. Even more particularly, the invention will be described as part of a numerical control system for performing two axis contouring with a turret lathe. FIGS. 2a-2d, assembled as one, show such a system.

A turret lathe 71 is generally shown in FIG. 2a. The turret 73 is moved horizontally along the X-axis by means of a first feed screw 75 driven by an X-axis servomotor 77. Vertical movement of the turret 73 along the Y-axis is effected through a second feed screw 79 driven by a Y-axis servomotor 81. The workpiece 83, shown as a dome-shaped structure, rests on a work table 85 mounted for rotation about the vertical axis L--L and driven through bevel gears 87 and 89 by a table drive motor 91.

Supported in a tool holder 93 on the underside of the turret 73 is a cutting tool 95 shown as inclined to the vertical. To machine the dome-shaped surface on the workpiece 83, it is rotated by the table drive motor 91 through the gears 87 and 89 with the table 85, and the turret is caused to traverse the cutting tool 95 along the X- and Y-axes at rates which are coordinated with each other and the rate of rotation of the table 85.

Motions of the turret 73 and of the tool holder 93 along the X- and Y-axes are under control of a pair of digitally controlled servo loops 76 and 78. The servo loop 76 is for controlling motion along the X-axis and includes a servomotor 77 and a digital encoder 97 having a shaft driven through appropriate gearing 99 from the X-axis lead screw 75. At a plurality of output lines 101, the X-axis digital encoder 97 produces a set of signals digitally representing in the form of a number the instantaneous position of the lead screw 75, and therefore of the tool holder 93, along the X-axis relative to a reference position. In the illustrated embodiment, each of the lines 101 represents a group of four conductors each for carrying signals representing in binary form one digit of a binary coded decimal number. An additional output line 102 carries a binary signal indicating the sign of the number.

The Y-axis servo loop 78 is similarly arranged with a Y-encoder 107 driven through gears 109 by the Y-axis lead screw 79 and producing in the form of binary coded decimal signals a number whose magnitude and sign is representative of the instantaneous position of the lead screw 79 and of the vertical position of the tool holder 93.

b. Producing the Basic Command signals

In numerical control systems for machine tools, it is common practice to store either on magnetic tape or on punched paper tape information representing the desired motions of the controlled machine element. As illustrated in FIG. 2b, a tape reader 113 is arranged to read numerical information one block at a time from a punched tape 115 and to supply its output signals to a numerical contouring director 117. Multiaxis numerical contouring directors such as that represented at 117 are well known in the art and need not be described here in detail. It will suffice to note that the director functions to produce trains of command pulses on lines 119 and 120 for X- and Y-axes of movement. Such command pulses for a given axis each represent a given increment of commanded motion (e.g., 0.0001 inch), and thus by their total number and frequency represent a desired extent of movement and a desired velocity of movement along that axis. By coordinating the number and frequency of command pulses for the X- and Y-axes, the axis component distances and velocities will result in a combined motion of a desired extent and at a desired angle in space.

The director 117 also receives sign information from the tape reader 113 and it indicates on lines 121 and 122 whether the motions directed on the X- and Y-lines 119 and 120 are to be in a positive or a negative direction (+X to the right and -X to the left, +Y up and -Y down as illustrated adjacent the turret 73).

The command pulses on lines 119 and 120 are serially spaced in time. They are converted into a digitally signaled command number which changes at a rate proportional to the command pulse frequency by means of a pair of accumulating reversible counters 123 and 125 labeled XP and YP respectively. These counters 123 and 125 may be of identical construction. Referring to the XP reversible counter 123, as better seen in FIG. 3, it has six cascaded decades, of which the units decade 123-0, the 10's decade 123-1, the 10 ⁴ decade 123-4 and the 10 ⁵ decade 123-5 are shown for storing the units, 10's, 10 ⁴ , and 10 ⁵ digits of a number respectively. The counter is also provided with a terminal 127 receiving a ± signal via line 121 which determines whether the counter counts up or counts down.

Formed of four cascaded flip-flops interconnected by appropriate gates, each decade signals its stored digit on four output lines in binary coded decimal notation. Such counting units are well known in the art and need not be described in detail. It is assumed that each decade signals the decimal digit "count" stored in it in the 8-4-2-1 code. According to this code, signals appearing on the four output lines of each decade are respectively assigned a weight of 8, 4, 2, and 1 and decimal numbers from 1 to 9 are represented by 123-0. Upon every 10the input pulse, the units decade counter 123-0 feeds one one or more lines whose total weight equals the signaled number. Of course, other binary decimal codes may be used and the 8-4-2-1 code here described is merely exemplary.

With a count up or + signal on terminal 127, each input pulse adds one to the number signaled at the output lines 131-0 of the units decade counter 123-0. Upon every 10th input pulse, the units decade counter 123-0 feeds one pulse to the tens decade counter 123-1 and upon every hundredth input pulse, the tens decade counter 123-1 steps the hundreds decade counter (not shown) by one. A similar rule of operation is followed by all of the higher decade counter stages.

To reverse the operation of the reversible counter 123, its control terminal 127 is energized with a - signal via line 121, causing the counter to diminish the number signaled at its output terminals by one for each pulse fed to its input.

The YP reversible counter 125 is similarly arranged, producing on a set of output lines 133-1 through 133-5 a digitally signaled command number which changes at a rate proportional to the Y-axis command pulse frequency on line 120 in a sense determined by the signals on the line 122.

Thus the XP and YP counters 123 and 125 are, in simplest terms, sources of digitally coded signals, multistage digital devices which produce digitally coded electrical signals at their outputs in response to signals applied at their input terminals. The contouring director 117 represents one possible means for applying the necessary signals to the inputs of the XP and YP counters.

c. The Parallel Adder, A Brief Description

Anticipating briefly the detailed description of the adder, it is the general scheme of the numerical control system periodically to apply the command signals produced by the XP and YP reversible counters to a parallel adder, to apply other signals to the adder representing corrections to be made to the command signals, to add or subtract the correction signals from the command signals, to subtract the position signals from the corrected command signals, and to apply the result to the X- and Y-servo loops. The parallel adder used for this purpose is indicated generally at 135 and is shown as having 10 decades and a stage for sign information.

An appropriate parallel adder will be described under a separate heading in detail. At this point, it is sufficient to note that each decade of the adder 135 includes four input terminals 137, four output terminals 139 and that each decade also includes means for adding or subtracting digits of numbers applied to its input terminals in the form of binary coded decimal signals. Further, a carry from each of the first nine decades to the next higher decade is provided so that collectively the adder 135 will produce at its output terminals 139 a number signaled in binary coded decimal form which is the sum of numbers similarly signaled in succession at its input terminals 137. An additional stage 141, having a single input terminal and a single output terminal is provided for receiving and producing sign information. In all, therefore, the exemplary parallel adder 135 has 41 input terminals and the same number of output terminals.

Furthermore, the adder 135 is divided into a series of adder stages 134 and a corresponding series of accumulator stages 136. Each accumulator stage 136 receives as one of its inputs the output of its associated adder stage 134, and in turn the output of each accumulator stage 136 is connected (through a set of gates not shown in FIG. 2a) to the input of its associated adder stage 134. As each successive digit is applied to the adder stage 134, that digit is added, during the following time period, to the sum accumulated in the accumulator 136. Thus, considering the entire adder 135, with each successive number signaled at the adder input terminals 137, a new subtotal is formed one time period later at the outputs of the registers 136 whose outputs comprise the adder output terminals 139.

The adder 135 will continue to accumulate numbers signaled at its input terminals 137 until a Clear Adder signal is applied to all of the accumulator stages 136. As will be described more fully later, the Clear Adder signal opens the gates which are between the outputs of the accumulator stages 136 and the inputs of the adder stages 134. Application of a Clear Adder signal thus disrupts the application of accumulated signals to the adder stages 134 so that when the next number is signaled at the adder input terminals 137, it is that number alone which will be registered in the accumulator stages 136.

The adder 135 is also capable of subtracting a number signaled on the input terminals 137 from a number previously accumulated in its accumulator stages 136. This feature is also discussed in greater detail later, but it may be observed here that operation of the adder 135 in this mode is brought about by applying a signal to its FORCE SUBTRACT terminal 138 when the number which is to be subtracted is applied at its input terminals 137.

According to an important feature of the exemplary numerical control incorporating the invention, a common input trunk 143 is provided for applying signals to the input terminals 137 of the adder 135. The adder input trunk, better seen in FIG. 3, has one conductor for each adder input terminal 137, in this instance, 41. In similar manner, a common output trunk 144 (FIG. 2a) is provided to apply signals produced by the adder 135 on its output terminals 139 to various utilization devices in the system and in particular to the X- and Y-servo loops 76 and 78.

The digitally signaled command number on the output of the XP reversible counter 123 is applied to the adder input trunk 143 by a set of read gates 145 at time periods determined by a gating signal applied to the read gates 145 on their timing input line 147. The command signals produced by the YP reversible counter are similarly applied to the adder input trunk 143 by a second set of read gates 149 under the control of a gating pulse applied to their timing line 151.

Since both the X-axis and the Y-axis command signals are carried on the same adder input trunk 143, they cannot be applied to that trunk line at the same time. Rather, the read gates 145 and 149 are enabled, i.e., opened, at different predetermined time periods so that the trunk line 143 may be "shared" by both of the counters 123 and 125. Indeed, the trunk line 143 is shared by many other components in the system, causing their signals to be applied to the trunk line during different time periods. The exact manner in which this time sharing arrangement is achieved forms an important feature of the invention and will be described subsequently.

d. Registers for Modifying the Basic Command Signals

Among the digital devices of the numerical control system, in addition to the XP and YP counters, which produce digitally coded signals applied to the adder input trunk 143 at various times are two sets of registers, each set for applying correction signals to modify the command signal produced by one of the reversible counters 123 and 125. The first set of registers includes the XTR (X-trim) register 153, the XMO (X-major offset) register 155, and the XTO (X-tool offset) register 157. A second set of registers for entering similar corrections to be used with the Y-axis servo loop includes the YTR register 159, the YMO register 161, and the YTO register 163. The nature of the corrections effected by the various registers just referred to will be best understood by reference to FIG. 4.

e. Machine Tool Characteristics; A Reason For Modifying The Basic Command Signals

"Major offset" relates to the fact that the XY coordinates of the part to be machined 83 and the X'Y' coordinates of the tool holder 93 originate at different zero points in space. Thus the position of the tool holder 93 is measured with reference to the distance of its datum point D from the zero point of the machine X'Y' coordinates. On the other hand, the points in space used to define the desired surface of the part 83 are defined with reference to their distance from the zero point of the XY coordinates. The distance along the X-axis from the part zero point x _o to the tool holder zero point x' _o is defined as x _mo for X-major offset. Correspondingly, the distance along the Y-axis from the part to the tool holder zero points, or y' ₀ -y ₀ , is defined as the Y-major offset y _mo .

The tape 115 is usually punched with information defining the desired position for the tip 96 of the tool 95 with reference to the part zero. This is indicated in FIG. 4 by the vector quantities x _c , y _c , representing the desired distance of the tool tip 96 along the X- and Y-axes with reference to x ₀ y ₀ , the machine part zero point. These instructions, if uncorrected, would cause the tool holder 93 to move from its x ₀ , y ₀ position upward and toward the right. Obviously, if the instructions were followed, the tool holder, which in its x o ', y o " position is already above and to the right of the part would be moved even farther away from it. Therefore, the X-major offset x _mo and Y-major offset y _mo of the tool holder 93 must be subtracted from x _c and y _c respectively.

Without more, the above described correction would cause the datum point D of the tool holder 93 to be positioned at the point where the tool tip 96 is located. This is so because the tool tip 96 is offset from the datum point D of the tool holder 93. This is the significance of "tool offset" and is represented in FIG. 4 by the vector quantities x _to and y _to to represent the distance of the tool tip 96 from the datum point D of the tool holder along the X- and Y-axes respectively. It may be seen then that in addition to a correction for the major offset, another correction must also be made to correct for tool offset and that the vector quantities x _to and y _to must also be subtracted from the vector quantities x _c and y _c respectively.

Assuming that the tool 95 is perfect, no further correction will be required and the tool tip 96 will be properly located. However, let it be assumed that the correct shape and location of the tool are those shown by the outline 95a. Of course, it is very unlikely that a tool would vary from normal by as much as is indicated in FIG. 4, which is exaggerated in this respect for clarity. Small variances of actual from normal locations of the tool tip 96 may be compensated by subtracting an amount from the command numbers x _c and y _c corresponding to the tool variances x _tr and y _tr along the X- and Y-axes respectively. This is the function of the registers XTR and YTR which permit such a trimming adjustment to be made by the machine operator.

Summing up, the net required movement of the tool holder 93, and in particular of its datum point D, along the X- and Y-axes are x _n and y _n as shown in FIG. 4. A brief analysis of the drawing will show that the net vector quantity x _n is obtained by subtracting the correction vectors x _mo , x _to , and x _tr from x _n , the vector quantity derived from the tape 115. Similarly, the desired motion of the datum point D along the Y-axis shown as the vector y _n , is derived by subtracting from the part-referenced, tape-derived vector quantity y _c the correction vectors y _mo , y _to , and y _tr . These relationships are concisely expressed by the equations (1) and (2) in FIG. 4.

The above explanation has been in terms of subtracting various corrections because this is more readily grasped intuitively. In practice, however, the correction quantities or "vectors" are assigned a polarity which is opposite to that assigned to them in the foregoing discussion and they are then added rather than subtracted by the adder 135.

f. The Command Signal Modifying Registers In Greater Detail

Returning briefly to the arrangement and operation of the correction registers 153-163 shown in FIG. 2b, they may be of any of several well-known types and need not be discussed in detail. To characterize them briefly and with particular reference to the XTR register 153 only, since all of the registers 153-163 may be of the same type, it is shown as having six stages, with each stage producing signals representing in binary coded decimal form one digit of a six-digit decimal number. Each of the output lines 154 originating from the six stages represent four lines necessary for signaling the numbers 0 through 9 in binary form.

The seventh stage of the XTR register 153, and of all the other registers 155-163, is for producing a signal on line 154a indicating the sign of the number represented by signals produced by the other six stages. The number of stages for the registers 153-163 are merely exemplary and will be determined by the magnitude of the correction which they are to implement. Thus, while the registers 153-163 may all be of the same type, they would in all probability not have the same number of stages.

As to the construction of the individual stages of the registers 153-163, each stage may conveniently comprise a set of four flip-flops with one output from each flip-flop being connected to one of the four lines originating from each of the stages of the register. The flip-flops in the several stages may be set to a desired one of their two stable states as by simple switches applying a control voltage to the set or reset inputs of the flip-flops. Such switches are shown in FIG. 2b as selector switches 153a, 155a, 157a, 159a, 161a, and 163a associated with respective ones of the correction registers 153-163.

To apply the signals appearing on the output lines of the registers 153-163 to the adder input trunk at desired time periods, a set of read gates is connected between the adder input trunk 143 and the output lines of each of the registers. The output of the XTR register 153, produced on its output lines 154, is applied to the adder input trunk 143 by a set of read gates 165. The gates 165 have a common control input terminal 166 and are opened by application of a gating signal to the terminal. The outputs of the registers 155-163 are applied at various time periods to the adder input trunk 143 by similarly constructed sets of read gates 167, 169, 171, 173, and 175 respectively.

g. Applying The Modified Command Signals To The Machine Tool Servo Loops

From the earlier description of the X-servo loop, it will be

When the turret 73 (FIG. 2a ) is set up for operation with a particular tool, the registers 153-163 will all be set to represent at their respective output lines the corrections required for the particular tool used. By means of the read gates 145 and 149, the XP and YP registers 123 and 125 will then be periodically interrogated so as to apply their contents representing instructions from the tape 115 to the adder input trunk 143. By a timing system which will be described in greater detail, following each application of the command signals from the XP register 123 to the adder input terminals 137, the contents of the X-axis correction registers 153, 155, and 157 are also applied, sequentially, to the adder input terminals. Thus there is presented on the adder output lines 139 at recurring intervals a signal group representing in binary coded decimal form a subtotal x _n (see FIG. 4) representing the required position of the tool holder 93.

From the earlier description of the X-servo loop, it will be recalled that the X-axis digital encoder 97 produces on its output lines an electrically signaled binary coded decimal number representing the actual position of the tool holder 93. Both the required and actual position is that of the datum point D of the holder 93. Through the set of X-axis encoder read gates 103, the output signals of the X-axis digital encoder 97 are applied to the adder input trunk 143 and through it to the adder input terminals 137. By an appropriate instruction to the adder 135, the signals x _a produced by the X-axis digital encoder 97 are subtracted from the corrected X-axis command signal (i.e., from the previous subtotal) and the difference x _e then appears on the output terminals 139 of the adder at a subsequent predetermined time period. This difference represents the error, i.e., the difference between the actual and the desired position for the tool holder 93.

A similar procedure is followed for determining on a continuous basis the positional error of the tool holder 93 along the Y-axis. The contents of the YP register 125 and of the Y-axis correction registers 159, 161, and 163 are successively applied to the adder input terminals 137 so as to produce a subtotal y _n representing the corrected Y-axis command signal. During the following time period the output y _a of the Y-axis encoder 107 is applied through the Y-axis encoder read gates 117 to the adder input trunk 143 and again by appropriate instruction to the adder 135, the number represented by the signals of the Y-axis encoder 117 is subtracted from the corrected command signal y _n so that during the following time period or cycle of the adder 135, the difference y _e , which is the positional error along the Y-axis, appears on the adder output terminals 139.

It follows from the foregoing that at frequent intervals, signals representing positional error along the X- and Y-axes will appear on the adder output trunk 144 at predetermined time periods. These signals are utilized to control the X- and Y-servo loops 76 and 78. To control the X-servo loop 76, the X-axis error signals x _e produced at the adder output terminals 139 and present on the adder output trunk 144 are applied through a set of write gates 179 to the XE register 181. The error signals y _e , representing positional error along the Y-axis, on the other hand, are applied to register YE 183 through a second set of write gates 185. By means of appropriately timed gating signals applied to timing input lines 217 and 225 of the write gates 179 and 185, the X- and Y-axis error signals x _e and y _e , appearing on the same adder output trunk 144 but at different time periods, are gated to the appropriate one of the registers 181 and 183. h. The Error Signal Registers XE and YE In Detail

As shown in FIG. 2a, the XE and YE registers 181 and 183 include seven stages for temporarily storing signals representing in binary code a number having up to seven digits. The registers also contain an eighth stage for storing a signal representing the sign of the number stored in the preceding seven stages.

With the exception of the stage for storing the sign information, all of the stages of the XE register 181 and also of the YE register 183 are identical. In order to illustrate a suitable example for the registers 181 and 183 as well as for the write gates 179 and 185, FIG. 5a shows a portion of the register 181, including the stage 181-7 for storing the sign and the stage 181-6 for storing the highest order digit of the number to be stored.

The sign stage 181-7 comprises a single, gates flip-flop 187, shown in greater detail in FIG. 5b. The gated flip-flop 187 includes a flip-flop 189, having a set input 191 and a reset input 193, a "1" output 195, and a "0" output 197. The "0 " output 197 of the flip-flops is not used in the registers 181 and 183. The "1" output 195 is capable of producing a signal at two levels, one corresponding to each of the two stable states of the flip-flop 189. A first level, corresponding to the logic level "1," is produced at the output 195 when the flip-flop 189 is set by application of a signal at its set input terminal 191. Application of a signal at the reset input terminal 193 will cause the flip-flop to assume its second stable state and the output terminal 195 to produce a signal at a second level corresponding to the logic level "0."

The function of the gated flip-flop is to store a binary signal applied at its data (D) input 199 at a selected instant. A signal representing a binary "1 " logic level at the data input 199 is to cause the flip-flop 189 to be set and a signal representing binary "0 " at the same input is to reset the flip-flop. To this end, the signal at the D input 199 is fed directly to the set input 191 through an AND-gate 201 and a unipolar differentiator 203. The function of the differentiator 203 will appear as this description proceeds.

In order to cause an appropriate triggering signal to be applied at the reset input 193 of the flip-flop 189 when the logic at the D input 199 is at logic "0" level, the signal is first inverted by the inverter 205 and then fed through and AND-gate 207 and a second unipolar differentiator 209 and applied to the reset input 193. As seen in FIG. 5c, the logic level is represented by a relatively high signal level and a binary "1" logic level by a relatively lower (i.e., less positive) signal level. The gates 201 and 207 are therefore arranged to transmit a signal when both of their inputs are at the binary "1" logic level.

To open the gates 201 and 207 at the instant when it is desired to store the information appearing on the date input line 199 in the flip-flop 189, a second input on each of the AND-gates 201 and 207 is connected to a clock (C) input terminal. With further reference to FIG. 5c, a write clock pulse 213 applied at the clock input terminal 211 of the gated flip-flop 187 causes the logic level "1 " signal, which may appear either at the output of the inverter 205 or at the D input terminal 199, to be passed through one of the gates 201 and 207. Therefore, at the end, or trailing edge, of the clock pulse 213, a positive-going voltage will appear at the output of that one of the AND-gates 201 and 207 which received a logic level "1" signal at its input. This positive-going signal is differentiated by the particular one of the differentiators 203 and 209 receiving it and that differentiator will in turn apply a triggering signal, in response to the voltage rise, to that one of the flip-flop inputs 191 and 193 to which its output is connected. The unipolar differentiators 203, 209 are per se well-known and contain an RC-differentiating circuit which converts positive and negative going input wave fronts into sharp position together with a diode which passes only the positive pulses. THus, the flip-flop 189 is triggered only when the relatively long clock pulse 213 ends.

Summing up the operation of the gated flip-flop 187, if the signal applied at its D input terminal 199 is at the binary "1" logic level, a triggering pulse will be applied at the trailing edge of the clock pulse to the set input of the flip-flop 189, causing a binary "1 " logic level signal to appear at its output 195. On the other hand, if the signal at the data input terminal 199 is at the binary "0 " logic level, then a triggering pulse will be applied to the reset input 193 in response to signals passed through the AND-gate 207, causing the flip-flop 189 to be reset and the signal appearing at its output 195 to be at the binary "0" logic level.

While the sign stage 181-7 utilizes a single gated flip-flop 187, the several digit stages 181-0 through 181-6 each utilize four such gates flip-flop, each flip-flop for storing one bit of the four bits required to represent a decimal digit in binary code. One of these stages is the stage 181-6 shown in FIG. 5a. To permit storage of signals appearing on the adder output trunk 144 in the flip-flops 187 of the register 181, each of the conductors of adder output trunk 144 is connected through one of the lines 215 and through one of the write gates 179 to the D input 199 of one of the gated flip-flops 187. Thus, in FIG. 5a, each one of the lines 215 from the adder output trunk 144 is connected to one input of an AND-gate 179 whose output is connected to the D input terminal 199 of one of the gated flip-flops 187. The other input of each of the AND-gates 179 is connected to a timing line 217. By means to be be described hereinafter, a gating pulse of appropriate polarity is applied to the timing line 217 during the time period in which the information that is to be stored in the register 181 appears on the adder output trunk 144. Further, in order to assure that the information that is applied to the register 181 is that which occurs after the adder has completed its operation for that time period, an appropriately timed clock pulse is applied on the clock line 219 which is connected to the C input terminals 211 of all of the gated flip-flops 187 within the register 181.

The outputs of the XE register 181 are applied over the output lines 196 to a data transfer trunk 221. The trunk 221 is a multiconductor trunk similar to the adder input and adder output trunks, but with fewer conductors, corresponding in number to the number of output lines 196 from the XE register 181. Thus with the exemplary XE register 181 shown in FIG. 2a, the data transfer trunk 221 would have 29 lines, 4 for each of the 7 digit stages 181-0 through 181-6 and 1 for the sign stage 181-7.

Referring only briefly to the YE register 183, since it may be identical to the XE register 181 just described, data is applied from the adder output trunk 144 to the write gates 185 periodically, once during each time cycle to be described, through input lines 223. At the desired time period, determined by a timing pulse on the timing line 225 of the write gates 185, the logic signals on the input lines 223 are applied to the inputs of the YE register 183. At the desired instant within the selected time periods, as determined by a pulse on the clock line 227 of the YE register 183, the logic signals, now on the output lines 224 of the write gates 185, are applied to the gated flip-flops of the register, immediately appear on its output lines 229, and remain there until the next clock pulse gates a new set of signals into the register.

i. Operation Of The Servo Loops

As stated earlier, the signals in the XE register 181 represent the difference between the desired and the actual position of the tool holder 93. Through the data transfer trunk 221, this error-representing signal group is applied to the inputs of a digital to analog converter 231 in the X-axis servo loop 76. Digital to analog converters are well known and will not be described here. It is sufficient to note that the digital to analog converter 231 has a plurality of inputs 233 which include several sets of four input lines, each set for receiving the four binary signals which represent one digit of a decimal number and one line for receiving the binary signal indicating the sign of the signaled number. Further, the converter 231 has an output 235 at which it produces an electrical analog of the number represented by the digital signals at its inputs. Assuming the simplest case, the electrical analog will be directly proportional to the number signaled digitally at the inputs 233 and will have a polarity corresponding to the sign of the number so signaled.

To enable the electrical analog on the output line 235 to operate the X-axis servomotor 77, it is applied to a servoamplifier 237 having an input connected to the output line 235 and an output connected to the X-axis servomotor 77. Again, assuming the simplest case, the X-axis servoamplifier 237 may be a linear one so that the signal applied to the X-axis servomotor 77 will be proportional to the electrical analog on the output line 235 and therefore to the positional error number digitally signaled on the output lines 196 of the XE register 181.

Through a set of suitable gears (not shown), the output shaft of the servomotor 77 is connected to the X-axis lead screw 75 and is operative to drive the lead screw in a direction and at a velocity corresponding to the digitally signaled error signal appearing on the XE register output lines 196.

The Y-axis servo loop 78 is similarly arranged. A data transfer trunk 239 carries the digitally signaled Y-axis error from the output lines 229 of the YE register 183 to the input lines 241 of the Y-axis digital to analog converter 243. The electrical analog produced by the converter 243 on its output line 245 is amplified by a Y-axis servoamplifier 247 whose output in turn is connected through lines 249 to the input of the Y-axis servomotor 81. Thus, in a manner similar to the operation of the X-axis servo loop, the Y-axis servomotor 81 will rotate the lead screw 79 through distances and at velocities in conformance with the sign and value of the digitally signaled error number y _e in the YE register 183.

In both the X-axis servo loop 76 and the Y-axis servo loop 78, the lead screws 75 and 79 are driven in a direction which will cause the magnitude of the error between the actual and desired positions of the tool holder to be reduced. Consequently, the servo loops 76 and 78 will continue to drive the lead screws 75 and 79 at rates and in directions which will cause the position of the tool holder 93 to follow, with a minimum of error, the position represented by the corrected position command signals produced in the adder and employed to derive the signals representing the X- and Y-axis error numbers.

It is important to realize that the X- and Y- servo loops 76 and 78, and in particular their respective registers 181 and 183, represent only two of many digital data utilization devices which would receive digital data from the adder output trunk 144 in a typical machine-tool-control system.

j. Timing Of Data Flow To And From The Adder-- Terminology

It will be recalled that data flows to the adder 135 from the registers 123 and 125 and also from the correction registers 153 to 163 through a common input trunk 143. Similarly, a common adder output trunk 144 is shared by the error registers XE 181 and YE 183 for receiving data from the adder. Many schemes could be devised for effecting a workable time sharing arrangement wherein data would flow from the various sources to the adder at different preselected time periods, and wherein different time periods would also be provided for causing data to flow through the adder output trunk 144 to the various utilization devices such as the error registers XE 181 and YE 183. The present invention would be equally applicable to all of them. The system which will be described here for sake of a specific example is a particularly simple and flexible one and may be best explained by employing terms commonly used to express periods of time, such as the year, the month, the week, and the day. In particular, in the machine tool control system under discussion, a set sequence of computations is performed during each major cycle of the system, each major cycle lasting a fiftieth of a second, or 20 milliseconds, and being called a "year" of machine time. This machine "year" of time is divided into 10 consecutive "months," each of which lasts one five-hundredths of a second or 2 milliseconds. Each "month" of machine time is further divided into 10 smaller consecutive time periods labeled "weeks," each "week+ being 0.20 milliseconds long. Finally, each "week" of machine time is divided into 10 basic consecutive time periods called "days" with a "day" lasting 20 microseconds.

A reference to FIG. 6 will help to understand this method of subdividing time. FIG. 6 shows a table, partially broken away, representing a machine "year"Timing divided into 10 columns, each column representing one of 10 "months." Each of the "month" columns is divided into 10 successive subcolumns representing a "week." Finally, each of the ten sub-columns or "weeks" is further divided into 10 blocks of time representing the 10 "days" in each "week." A brief explanation of the relatively simple timing devices which can be used to implement the timing arrangement illustrated in FIG. 6 will reveal its particular advantages.

k. Timing Of Data Flow-- The Timing Signal Generator

Signals representing the "days," "weeks," and "months" of a 20-millisecond machine "year" are generated by a timing signal generator 251 (FIG. 2b) comprising three cascaded binary coded decimal pulse counters 253, 255, and 257 driven by a clock pulse source 259. The decade counters 253-257 are of similar construction and are well known to those skilled in the art. A typical unit of this type includes four cascaded flip-flops interconnected by gating (not shown) so that the decade repeatedly counts from 0 to 9 in response to successive input pulses, being reset to 0 by every 10th input pulse, and signaling its contents on four output lines in 5-4-2-1 binary code. Additionally, the unit also produces a signal on a fifth or "carry" line each time that it is reset to 0.

The units counter 253 is stepped by output pulses from the clock pulse source 259 at a rate corresponding to the frequency with which "days," represented by the units counter are to elapse. Since each "day" in the exemplary timing system is to have a 20-microsecond duration, the frequency of pulses from the clock pulse source 259 is selected to be 50 kiloherz.

For simplicity of operation, it is desired to convert the signals produced by the binary coded decimal counter 253 (and those produced by the counter 255 and 257 as well) into pure decimal form. For this purpose, the binary coded outputs of the counter 253, appearing on its output lines 261, are applied to a binary-coded-decimal converter 263. The converter 263 has ten output terminals, or lines, labeled 0 to 9. Binary-coded-decimal to decimal converters are well known in the computer art and will not be described here in detail. It need only be noted that the converter 263 produces a pulse at one of its output terminals 0 through 9 in conformance with the binary coded number signaled at its inputs. Thus the 6-output terminal will carry a pulse when the units counter 253 signals binary 4 and 2 on its output 261. With successive pulses from the clock pulse source 259 successive ones of the output terminals 0 through 9 carry timing pulses. Each of these pulses represents a successive one of 10 successive basic time periods or "days."

To produce decimal coded pulses representing "weeks" of machine time, the carry output of the units counter 253, shown as output line 254, is applied to the input of the 10s-decade binary coded decimal counter 255. The 10 s-decade counter 255 operates in the same manner as the units counter 253, producing on its four output lines, or terminals, 267 signals which represent in binary coded decimal 5-4-2-1 code successive "weeks" of time, with the successive weeks being signaled upon each complete cycling of the units counter 253, that is, after each 10 "days" of machine time.

To covert the binary coded decimal output of the tens decade counter 255 into pure decimal signals, a second binary-coded-decimal to decimal converter 269 is provided with inputs connected to the counter output lines 267. The converter 269 is similar in construction to the units converter 263 and also has ten output lines labeled 00 to 90. As the number signaled by the 10 s-decade counter 255 in binary coded decimal 5-4-2-1 code advance from 00 through 90, a timing signal will appear on successive ones of the timing lines 00 to 90 corresponding to the signaled number. Reference to FIG. 6 shows that the output terminals 00 to 90 represent successive ones of the 10 subcolumns or "weeks" which make up each of the ten main columns or "months" of the machine "year."

To generate pulses representing the 10 "months" of the machine "year," the carry output 256 of the 10 s-counter 255 is applied to the input of the 100 s-decade binary coded decimal counter 257 having a set of output lines 270. With each successive series of hundred pulses from the clock pulse source 259, the count stored in the hundreds decade counter 257 and signaled on its output lines 270 in 5-4-2-1 code is advanced by one. The binary coded decimal output of the 100 s-decade counter 257 is converted into decimal signals by means of a third binary-coded-decimal converter 271. The 100 s-decade converter 271 is similar in construction to the first two converters 263 and 269, having a set of four inputs connected to the 100 s-decade counter output lines 270 and producing in response to the signals thereon a timing signal on one of a set of 10 output lines labeled 000 to 900. In a manner already described in connection with the first two converters 263 and 269, the hundreds decade converter 271 is operative to produce a timing pulse which is switched from one output line to the next with each change in the number signaled on the counter output lines 270 in binary coded decimal 5-4-2-1 form, i.e., with the elapse of each 10th "week" of machine time.

Summing up the operation of the timing signal generator 251, it is seen that it is operative to produce at a plurality of outputs, represented by the units-decade outputs 0 to 9, the 10 s-decade outputs 00 to 90, and the 100 s-decade outputs 000 to 900, concurrent signals, one from each decade of outputs, which together digitally represent a cyclically changing series of numbers, in the exemplary embodiment ranging from 000 to 999.

1. The Program Gates

The manner in which appropriate gating signals may be derived from the signals produced by the timing signal generator 251 will be next described. Since the signals produced by the timing generator 251 are in decimal form, appearing as they do on one of each of three decades of terminals, very simple means responsive to the coincidence signals on selected ones of the output lines of the timing signal generator 251 may be employed. One such means, the program gate, is illustrated in FIGS. 7a-d. Each of the four program gates illustrated in FIG. 7 has three input terminals, one terminal for each decade of the timing signal generator output terminals 0-9, 00-90, and 000-900. Here, and also in FIG. 2, connection to one of the output terminals of the timing signal generator 251 will be indicated by a Δ on the input terminal of the program gate involved. Where the gate is drawn so that its input terminals are arranged one above the other, the top terminal will be considered the 100 s-decade terminal, the middle terminal the 10 s-decade terminal, and the bottom terminal the units-decade terminal. Where the program gate is drawn with its input terminals arranged horizontally, they will be considered to run in a similar decreasing order from left to right.

Each of the four program gates of FIG. 7 may be of the same type, the well-known AND gate. The manner in which they are connected to the outputs of the timing signal generator 251 is what distinguishes them. The program gate of FIG. 7a has each of its input terminals connected to an output line selected from each of the three decades of output lines of the timing signal generator 251, in the particular example shown to the 100 line of the 100 s-decade, the 90 line of the 10 s-decade, and the 5 line of the units decade. In the well-known manner of operation of coincidence or AND gates, the program gate of FIG. 7a is operative to produce at its output a gating signal when and only when timing signals appear at each of its three input terminals. This occurs when the count accumulated by the cascaded counters 253, 255, and 257 is 195. Using the terminology employed to explain the basic timing concept with respect to FIG. 6, a gating signal is produced by the program gate of FIG. 7a during the 5th "day" of the 9th "week" of the 1st "month" of each machine "year."

The type of connection shown in FIG. 7a is employed when it is desired to gate signals to or from one of the adder trunklines 143 and 144 once during each major cycle or machine year. Certain operations of the control system are sufficiently important to require that data from a given data source be applied to the adder input trunk 143 or from the adder 135 to some utilization device such as the registers 181 and 183 several times in regular succession during each major cycle of machine "year" of the control system. A logical way to accomplish this is to cause the data to be transferred to or from one of the trunklines 143 and 144 either during each "month" of the machine year or in certain circumstances, during each "week" of a particular "month." At first it might be thought that this would require 10 individual program gates, one fro producing the gating signal associated with each desired month or week. With the decade-type timing signal outputs produced by the timing signal generator 251, this is not necessary. Indeed, a single program gate is sufficient to accomplish the purpose. Thus if it is desired to produce a gating signal during a particular week of each month of the machine year, a single program gate of the type shown in FIG. 7b is sufficient. Assuming, for example, that a gating signal is desired for the 4th day of the 5th week of each month, the units and decade input terminals of the program gate are respectively connected to the 4 and 50 output terminals of the timing signal generator 251. The hundreds decade input terminal of the program gate. however, is merely connected to a source of gate-enabling voltage corresponding to the voltage level of the timing pulses appearing at the outputs of the timing signal generator 251. Connection to such a voltage source is symbolically represented by an X next to the 100 s-decade input terminal of the program gate. As a result of having its hundreds decade input terminal permanently connected to a source of an enabling voltage level, the program gate of FIG. 7b produces a gating pulse regardless of the state of the 100 s-counter 257 and of the 100 s-decade converter 271, and in fact will produce a gating signal at its output whenever timing pulses appear at the 50 and at the 4 output terminals of the timing signal generator 251. Stated differently, therefore, the program gate will produce a gating signal during the 4th day of the 5th week of each of every month of the machine year.

The program gates illustrated in FIGS. 7c and 7d feature connections less frequently used than those of FIG. 7b. By means of a program gate connected as in FIG. 7c, ten signals may be produced during a given subcycle or month of a major cycle or year, and in particular such a gating signal may be produced during a given day of each week of a selected month. Thus, in the example shown, a gating signal is produced by the program gate of FIG. 7c during the 7th day of each week of the 2nd month of the machine year.

Finally, in the event that it is desired to produce a series of gating pulses during successive time periods, the connection shown in FIG. 7d might be employed. With the hundreds decade input terminal of the program gate connected to the 000 output, the 10 s-decade input terminal connected to the 90 output of the timing signal generator, and with the units decade input terminal connected to a permanently enabling voltage level, the program gate produces a gating signal during each time period in which the tens counter 255 is stepped through its ninth decade. Stated in the terminology employed in connection with FIG. 6, the gating signal would be produced during all of the days of the 9th week of the 0 month of the machine year.

m. The Decoder Matrix-- A Possible Alternative To Individual Program Gates

Although individual program gates have their advantages, as shown in the preceding section, they could all be replaced by a single, albeit rather large, decoder matrix. The diode matrix is often used for this purpose, but other types of matrices, using resistors or transistors, are also frequently employed.

FIG. 8a shows how a diode decoder matrix might be connected to the timing signal generator 251 to produce any gating signal that might possibly be derived from it by means of program gates.

The exemplary decoder shown in FIG. 8a includes three sets of 10 -column conductors, conductors of the respective sets being numbered 0 through 9, 00 through 90, and 000 through 900 respectively. These column conductors serve as the inputs to the decoder and are connected to similarly numbered ones of the outputs of the timing signal generator 251.

Forming the outputs of the decoder of FIG. 8a are 1,000 -row conductors numbered 000 through 999. Each row conductor of the decoder is operative to produce a gating signal during the time period indicated by its number. To this end, each of the row conductors is connected through three diodes to three of the 30 -column conductors and in particular to one column conductor in each of the three sets of column conductors 0 through 9, 00 through 90, and 000 through 900. This connection is schematically indicated in FIG. 8a by means of dots at the intersections of the row conductors with selected ones of the column conductors. Taking the row conductor 322 as an example, dots appear at the points where it intersects column conductors 300, 20 and 2.

FIG. 8b illustrates the manner in which the diodes represented by dots in FIG. 8a are connected and energized. As there shown, the column conductors referred to are respectively connected to the row conductor 322 through diodes 273, 274, and 275, each diode being poled for conduction of current from a column conductor to the row conductor. Through a load resistor 276 the row conductor 322 is connected to a source of negative voltage, here shown as -6 bolts. The significance of the voltage chosen is that, in the illustrated system, a logic 1 voltage level is less positive than a logic 0 voltage level (see FIG. 5c). Thus ground level may be conveniently used as logic 0 voltage level and -6 volts may be used to represent logic 1 voltage level.

From the earlier description of the timing signal generator it will be recalled that logic 1 voltage signals will appear on all three of the column conductors 300, 20, and 2 only during the 322nd time period which is generated by it. During all other time periods, one or more of the column conductors will be at a logic 0 voltage level. Observation of the circuit of FIG. 8b will shown that it is only during the single time period during which all three of the column conductors are at logic 1 (-6 volts) voltage level that the row conductor 322 will be at the logic 1 voltage level. Thus, if any one of the three column conductors 300, 20 and 2 is at zero (and logic 0 ) voltage level, its associated diode will be biased into conduction, causing current flow through the resistor 276 and a voltage which is substantially 0 volts on the column conductor 322. Only when all three of the column conductors are at the -6 -volt level will the row conductor 322 remain at that level for it is only under those conditions that there is no current flow through or voltage drop across the resistor 276.

Observation of FIG. 8b also reveals that each row conductor and the three diodes connecting it to three column conductors are in effect and AND gate performing the same function as that served by a program gate. Conversely, it is apparent that the plurality of program gates used to derive sequentially timed gating signals from the outputs of the timing signal generator 251 are in effect a single, multioutput decoder, with each output of this decoder being the output of one of the program gates. Thus, as used in the specification and claims, "decoder" or "decoding means" is meant to denote both a single decoding matrix and a plurality of individual program gates, which collectively derive sequentially timed gating signals from the outputs of the timing signal generator.

n. An Exemplary Machine Program Controlled By The Timing Signal Generator And The Program Gates

(1) Running the X-axis Servo loop

Before returning to FIG. 2 to explain the manner in which gating signals derived from the timing signal generator 251 are employed, an exemplary partial program for a machine year will be first set forth. The partial program illustrated in FIG. 6 is that required to perform the necessary additions and subtractions before translating instructions read from the punched paper tape 115 into movements of the machine tool 95. Clearly these operations represent but a small part of those performed by the control system. Nevertheless, they are sufficient to illustrate the principles involved. First, it should be observed that the operations involved in translating the punched commands into tool motion involve a series of calculations which are repetitively performed during the initial portion of each month of the machine year. Thus, any particular operation that is to be performed during the first time period or day of the first month shall also be performed during the corresponding time period of each succeeding month and the same applies to the remaining operations that are to be performed during succeeding days of the first month.

THe first operation, performed during the time period 000 (and also during time periods 100, 200, etc.) is to "read" the contents of the XP counter 123 (RXP), and to apply them to the adder input terminals 137 through the read gates 145 and through the adder input trunk 143. Accordingly, a program gate 279 (FIG. 2b ) is provided with its output connected to the timing input line 147 of the read gates 145 and with its 100s 10s and zero decade inputs connected respectively to an enabling voltage, the 00 output terminal and the 0 output terminal of the timing generator 251. Additionally, to prepare them to receive the signals from the XP register 123, the accumulator stages 136 of the adder 135 are cleared by application of a Clear Adder signal (CAR) to the Clear Adder input terminal 140 of the adder 135. The program gate 281 is provided for this purpose, having its inputs connected to the same set of signal sources to which the inputs of the program gate 279 are connected. Accordingly, the program gate 281 produces a clear adder signal during the first time period or day of each month of the machine year. The output of the programming gate 281 is applied to the Clear Adder input 140 of the adder 135 through an OR-gate 282. It might be noted that, while a separate program gate 281 has been shown for producing a Clear Adder signal, that signal could have also been derived from the output of the program gate 279.

Once the contents of the XP register 123 have been applied to the adder input terminals 137, the adder 135 is operative to store those signals in its cleared accumulator stages 136.

During the next three time periods 01, 02, and 03, the corrections stored in the XMO register 155, the XTO register 157, and the XTR register 153 are successively applied to the adder inputs 137. To open the read gates 167, 169, and 165 associated with the registers 155, 157, and 153 respectively, during the second, third, and fourth time periods, program gates 283, 285, and 287 are provided, with the outputs of respective ones of the program gates 283, 285, and 287 being connected to the timing input lines 168, 170, and 166 respectively of the corresponding read gates 167, 169, and 165. Since each of the program gates 283, 285, and 287 is to produce a gating pulse during given time periods of each month, the hundreds decade input terminal of each of these gates is connected to a source of enabling voltage as indicated by the symbol X. Similarly, since all three of the program gates 283-287 are to produce their gating pulses during only the first week of the machine year, the decade input terminal of each of the three gates is connected to the 00 output terminal of the timing signal generator 251. Finally, the units decade input terminals of the three program gates 283, 285, and 287 are respectively connected to the 1, 2, and 3 output terminals of the timing signal generator 251 thus applying gating signals to the read gate timing input lines 168, 170, and 166 during the time periods 01, 02, and 03 as required.

Briefly summing up the function of the program gates associated with the read gates 145 and 167-169, it will be seen that they collectively represent a plurality of signal-coincidence responsive means, each connected between a different combination of outputs of the timing signal generator 251 and a different one of the read gates for applying individually timed gating signals to them.

Keeping in mind that the sum (or difference) resulting from entry of a number in the adder 135 during a given time period appears in its accumulator stages 136 and hence at its output during the following time period, it will be seen that at the end of the fifth time period 04, the accumulator stages 136 of the adder 135 will contain the sum of the four numbers which were applied to the adder during the preceding four time periods 00-03 since the adder was working in the "add" mode during the first four time periods. This sum represents the corrected X-axis position command signal for the tool 95. During the fifth time period 04, the output x _a of the X-axis digital encoder 97 must be subtracted from the previously accumulated sum in order that the adder shall produce during the fifth time period the difference x _e , representing the error between actual and desired machine tool positions along the X-axis. Accordingly, the program gate 289 (FIG. 2a) is provided for timing the application of the x _a signals from the X-axis digital encoder 97 to the adder input trunk 143. The output of the program gate 289 , connected to the timing input line 104 of the X-axis encoder read gates 103. In order to produce the gating signal necessary to open the read gates 103 during the fifth time period 04, the 100s, 10s, and units decade input terminals of the program gate 289 are respectively connected to the enabling voltage source (indicated by X) the 00 -output terminal and the 4-output terminal of the timing signal generator 251.

As the signals from the X-axis digital encoder 97 are being applied to the adder input terminal 137, a signal is also applied to the Force Subtract terminal 138 of the adder 135 so as to cause the adder to work in the subtract mode of operation. The timing signal to be applied to the Force Subtract input may be derived from the same program gate 289 used to open the X-axis encoder read gates 103, or alternatively a separate program gate 291 may be provided for this purpose. In the latter event, the inputs of the program gate 291 would be connected to receive the same signals as those received by the inputs of the program gate 289. For reasons which will appear shortly, the output of the program gate 291 is applied to the Force Subtract input through an OR-gate 293.

During the sixth time period 05, the adder 135 will have completed its subtracting operation, producing at its outputs 139 the x _e or X-axis error signals representing the difference between the corrected command signal derived during the first five time periods 00- 04 and the actual position signal x _a applied to the adder during the fifth time period 04 . In keeping with the method of operation of the control system as described earlier, the X-axis error signal x _e is applied during the time period 05 through the adder output trunk 144 and through the write gate 179 to he inputs of the XE register 181. To this end, still another program gate 295 is provided having an output connected to the timing input 217 of the write gates 179. The 100s, 10s, and units decade input terminals of the program gate 295 are connected to a source of enabling voltage, the 00-output terminal and the 5-output terminal of the timing signal generator 251 respectively.

As a result of the presence of a gating voltage on their timing input line 217, the write gates 179 will apply whatever signal is present on the adder output trunk 144 during the sixth time period 05 to the D inputs of the gated flip-flops which make up the XE register (see FIG. 5a). At the appropriate instant during that time period, when the adder 135 has completed its subtracting operation, a clock signal is applied to the Write Clock input 219 of the XE register 181 and at that instant the result of the subtracting operation, i.e., the X-axis error signal x _e , is entered into the gated flip-flops of the XE register 181.

In the manner described under the heading "Applying the Modified Command Signals to the Machine Tool Servo loops" the X-axis error signals x _e stored in the XE register 181 also appear at its output lines 196 and are applied through the X-axis digital to analog converter 231 and the X-axis servoamplifier 237 to the X-axis servomotor 77 so as to move the X-axis lead screw 75 to a position conforming with the corrected position command signal.

It is worth noting that the sequence of calculations just described in connection with the first six time periods or "days" 00 through 05 is repeated during the first 6 days of each month of the machine year or every 2 milliseconds. Consequently, even if the position command signals from the punched tape 115 should change only once during each machine year, the corrected position command signal which is derived therefrom is compared with the signal representing the actual position of the tool holder 93 10 times during the machine year. This frequent checking of the actual against the desired position of the tool holder 93 results in extremely close tracking and minimum overshoot since the error signal XE always closely represents the error existing at any given instant.

(2) Running the Y-axis Servo Loop.

During the next six time periods or days of the first and subsequent month, calculations corresponding to those performed during the first six time periods are carried out to produce the Y-axis error signal y _e 10 times during each machine year. In view of the detailed explanation given with reference to the timing apparatus required to perform the operations during the first six time periods, only a brief explanation will be given of the similar apparatus required to perform the remaining six operations. Thus a set of four program gates 297, 299, 301, and 303 are provided to apply appropriately timed gating signals to the timing input lines 151, 174, 176, and 172 of the read gates 149, 173, 175, and 171 during successive ones of the time periods 06, 07, 08, and 09. Since all four of the program gates 297-303 are to produce a gating pulse during each of the 10 months, their 100-decade input terminal is in each instance connected to a source of enabling voltage indicated by the symbol X next to the terminals. Similarly, since each of the four program gates 297-303 is to produce its gating signal during the 1st week of the machine year, the 10-decade input of each of the program gates is connected to the 00 output of the timing signal generator 251.

The units decade input terminal of the program gate 297 is connected to the 6 output terminal of the timing signal generator 251 thus causing the contents of the YP counter 125 to be applied to the adder input terminals 137 during the time period 06. To clear the adder accumulator stages 136 during the same time period so as to prepare them to receive the signals read from the YP counter 125, a clear adder signal is applied to the Clear Adder input terminal 140 of the adder 135 during the time period 06 and this signal is generated by the program gate 305 whose output is connected through the OR-gate 282 to the Clear Adder input of the adder 135. The inputs of the program gate 305 are connected to the same signal sources to which the program gate 297 associated with the YP counter read gate 149 are connected. Alternatively, the signal produced by the program gate 305 may be derived directly from the output of the program gate 297.

To gate the contents of the YMO register 161 through the read gates 173, the units decade input terminal of the program gate 299 is connected to the 7 output terminal of the timing signal generator 251. Similarly, to effect transfer of signals from the YTO register 163 and from the YTR register 159 during the time periods 08 and 09 respectively, the units decade input terminals of their associated program gates 301 and 303 are connected to the 8 and 9 output terminals of the timing signal generator 251 respectively. Again, as each set of signals is applied to the adder input terminals 137 during a given time period, the sum of the number represented by those signals and of the number then stored in the accumulator stages 136 appears in the accumulator stages during the following time period.

During the 11th time period, or day 10, the accumulator stages 136 of the adder 135 will contain the corrected position command number resulting from the addition of the contents of the Y-axis correction registers 159, 161, and 163 to the number read from the YP counter 125. In order to subtract from this sum the y a output of the Y-axis encoder 107, representing the actual position of the tool holder 93 along the Y-axis a program gate 307 is provided to enable the Y encoder read gate 111 during that time period. The output of the program gate 307 is connected to the timing input line 112 of the Y-axis encoder read gates 111 and its 100s, 10s, and units decade input terminals are respectively connected to the source of enabling voltage and to the 10 and 0 output terminals of the timing signal generator 251.

During the same time period, the signals from the Y-axis encoder 107 have been entered into the adder 135, a FORCE SUBTRACT signal is applied to the FORCE SUBTRACT terminal 138 of the adder. This signal may be derived either from the output of the program gate 307 or a separate program gate 309 may be provided as shown in FIG. 2a. In the latter case, the inputs of the program gate 309 are connected to the same combination of sources to which the inputs of program gate 307 are connected and the output of the program gate 309 is connected to the FORCE SUBTRACT terminal 138 of the adder through the OR-gate 293. During the following, or 12th time period 11, the Y-axis error signal y e, representing the remainder resulting from the subtraction of the actual position signal y a from the previously accumulated corrected position command signal y n will appear on the adder output terminals 139. It is during this period therefore that the Y-axis error signal y e is applied to the Y-axis servo loop 78. To this end, the timing input 225 of the write gates 185 associated with the YE register 183 is energized by a gating pulse from a program gate 311 with 100s, 10s, and units decade inputs connected respectively to the source of enabling voltage and to the 10 and 1 outputs of the timing signal generator 251. To insure that the output of the adder 135 is not read prematurely, a clock pulse is applied to the write clock input 227 of the YE register 183 at a time when the adder is known to have completed the subtracting step.

o. Summary of the Exemplary Control System Described in a-n.

In the foregoing description of an exemplary machine-tool-control system, certain aspects of the system, particularly the means for timing flow of data to and from an adder over time-shared multiconductor trunklines have been described in considerable detail. Some of the significant features possessed by such a system may have become obscured. The following is intended to restate them briefly.

What has been described thus far in essence is a system for transmitting digitally coded signals during a cyclically recurring succession of preassigned time periods from a plurality of sources of digitally coded signals, such as the XP and YP counters 123 and 125, the correction registers 153-163, and the X- and Y-axis digital encoders 97 and 107 over a first multiconductor trunkline to the inputs of a digital adder and from the outputs of the adder over a second multiconductor trunkline to the inputs of devices such as the X- and Y-servo loops 76 and 78 which utilize digital signals.

To cause the contents of the various digital devices to be transmitted over the first trunk line during their preassigned time periods, a first plurality of gating means such as the read gates 145 and 149, 165-175, and 103 and 111 are each connected between one of the data sources and the first trunkline. Similarly, to cause the output of the adder to be transmitted to the inputs of the various digital data utilization devices over the second trunkline, a second plurality of gating means is provided, as exemplified by the write gates 179 and 185. Each of the latter gating means is connected between one of the utilization devices such as the X- and Y-servo loops 76 and 78 and the second trunkline.

The sequentially timed gating signals required to open the various ones of the first and second gating means during successive time periods are provided by a timing signal generator working into a suitable decoding means. A preferred timing signal generator is the unit 251 shown in FIG. 2b which operates to produce at a plurality of outputs concurrent signals digitally representing a cyclically changing series of numbers. Decoding means such as the various programming gates are provided to derive, from the concurrent digital signals of the timing signal generator, cyclically recurring sequentially timed signals in response to the successive combinations of signals produced at the outputs of the timing signal generator. Respective outputs of the decoding means are individually applied to the respective ones of the first and second pluralities of gating means, thereby applying to them the required sequentially timed gating signals.

p. The Single-Trunkline System

Before leaving consideration of an exemplary machine-tool-control system wherein the invention might be employed, it should be noted that the two trunklines leading to and from the adder could be replaced by a single trunkline. In such a system, the same general scheme of time sharing might be employed as that used with the system disclosed in FIGS. 2a and 2b. Thus, through a timing signal generator and associated program gates or decoder there would be produced a plurality of sequentially timed, cyclically recurring gating signals, each signal representing an individual time period during which information signals are to be applied to or taken from the adder. In addition, however, such a single trunk line system would include provision for dividing each time period into at least two portions by producing a first gating signal during the first portion of each time period and a second gating signal during the second portion of each time period. Each of the conductors of such a single trunk line would be branched to be connected to those input and output terminals of the adder which represent the same weight binary signal. Thus, a given conductor of the trunkline would be connected to the 1-bit input and output terminals of the units decade of the adder, the second conductor would be connected to the 2-bit input and output terminals of the adder, and so on. The outputs of the various read gates would be connected to the common trunkline in the same manner in which they are connected to the adder input trunk 143 in FIG. 2b, and similarly, the inputs of the write gates would also be connected to the trunkline in the same manner in which they are connected to the adder output trunk 144 in FIG. 2a.

If during a given time period signals are to be applied from a particular signal source to the adder input terminals, the gating signal produced during the first portion of that time period would be applied to the read gates associated with the particular signal source. On the other hand, if signals are to be transferred from the adder output terminals to a particular signal utilization source, such as the XE and YE registers 181 and 183 of FIG. 2a during those time periods, it would be the gating signals which are generated during the second portion of those periods which would be applied to their associated write gates 179 and 185.

It should be understood, therefore, in view of the foregoing that, while there has been described a machine-tool-control system wherein information flows to and from an adder through a pair of time-shared trunklines, this has been by way of example only, and that such a system could be readily converted along the lines suggested here into one wherein only a single multiconductor trunkline is employed. The present invention would be equally applicable to a single trunkline or to a double trunkline-control system.

2. THE READOUT

a. The AIT and AOT Gates.

In the foregoing there has been described a system having at least one multiconductor trunkline over which information flows in the form of digital signals during successive individual time periods. An important object of the present invention is to provide a readout which will permit the display of the digitally signaled data appearing on such a trunkline during any desired time period. The principal components of an exemplary form of such a readout are shown in FIGS. 2c and 2d.

With reference to FIG. 2c and also to FIG. 3, it will be recalled in connection with the description of the adder input trunkline 143 that, in the preferred embodiment, the trunkline 143 has 41 conductors numbered 143-1 through 143-41. Four conductors are used to carry the four binary signals used to represent each digit of a multidigit decimal number, with the units digit being signaled in binary 8-4-2-1 form on the lines 143-1 to 143-4 and with higher order digits being represented by higher numbered conductors up to the 10 ⁹ -digit signaled on adder input trunk conductors 143-37 to -40. Additionally, the sign of the number signaled on the conductors 143-1 to -40 is indicated on the 41st conductor 143-41. The foregoing assumes, of course, that it is desired to have the capacity to transmit a number having up to 10 digits and that the number shall be signaled through binary signals. Clearly, if a smaller capacity would suffice, lesser number of conductors would be used, and if a different code convention were employed, it is conceivable that each digit might be represented by fewer conductors than four.

The adder output trunk 144 similarly includes 41 conductors numbered 144-1 to -41, partially shown in FIG. 2c, corresponding to the adder input trunk conductors 143-1 to -41.

To permit display of signals present on either one of the trunklines 143 and 144 at any desired one of the plurality of successive individual time periods during which signals may appear on them, gating means are connected to the conductors of the trunklines 143 and 144 to permit signals to pass from the conductors through the gating means to suitable display devices. In accordance with this aspect of the invention, one set of gating means, referred to previously as the AIT-gates 26 (see FIG. 1), is connected to the conductors of the adder input trunk 143. Another set of gating means, previously labeled the AOT-gates 28, is similarly connected to the conductors of the adder output trunk 144. By applying a gating signal to the first set of gating means during a given time period, signals from the adder input trunk 143 may be applied to the display device. Similarly, by applying a gating signal during the same time period to the second set of gating means, a signal appearing during that time period on the adder output trunk 144 will be passed fro display. The gating arrangement shown in the block 321 is a preferred form of the first and second gating means.

The block of gates 321 includes 10 identical groups of gates for handling signals representing the 10 digits of a number which might be signaled either on the adder input trunk 143 or on the adder output trunk 144. Only one of these 10 stages, that which is associated with the 10 ⁹ -digit, is shown in detail. It includes a first set of four AND-gates 323, 325, 327, and 329 having an input connected to respective ones of the conductors 143-40, 143-39, 143-38, and 143-37 of the adder input trunk 143. These gates form part of the first set of gating means referred to earlier. The stage also includes a second set of four AND-gates 331, 333, 335, and 337, each having an input connected to respective ones of the conductors 144-40, 144-39, 144-38, and 144-37 of the adder output trunk 144. The latter four AND-gates thus form part of the second set of gating means referred to above.

The AND-gates 329 and 337, being respectively connected to adder trunk conductors 143-37 and 144-37, are operative to produce at their outputs, when they are opened, signals representing the 1-bit of the 10 ⁹ -digit of the number which appears on the adder input and adder output trunk, respectively. Similarly, the AND-gates 327 and 335 are connected to produce at their outputs signals corresponding to the 2-bit signal on the adder input and adder output conductors 143-38 and 144-38, the AND-gates 325 and 333 are both connected to lines carrying 4-bit signals and the AND-gates 323 and 331 are connected to conductors carrying 8-bit signals on their respective trunklines. Accordingly, to route the outputs of AND gates carrying the same weight signal to the same point, the outputs of the AND-gates 329 and 337 are connected to an OR-gate 339, those of the AND-gates 327 and 335 are connected to an OR-gate 341, a third OR-gate 343 receives the outputs of the AND-gates 325 and 333, and the outputs of the AND-gates 323 and 331 are connected to a fourth OR-gate 345.

Each of the eight AND-gates of the 10 ⁹ -decade has a second input which, when energized by an appropriate gating signal, opens the gate to pass the signal applied to its first terminal, which in each case is connected to one of the trunkline conductors. The second input terminal of each of the four AND-gates 323, 325, 327, and 329 is connected to a common line 347 labeled WRITE AIT. By applying a gating pulse to the WRITE AIT line 347, the AND-gates 323, 325, 327, and 329 are opened and cause the signals appearing on their associated adder input trunklines 143-37, 143-38, 143-39, and 143-40 to be applied to the OR-gates 339, 341, 343, and 345. In similar manner, the second input terminals of the AND-gates 331, 333, 335, and 337 are also connected to a common timing line 349 labeled WRITE AOT, so that by application of a gating pulse through the WRITE AOT line 349 signals on the adder output trunk conductors 144-37 through 144-40 may appear at the outputs of the OR-gates 339 through 345.

The remaining nine stages of the block of gates 321, for passing signals representing the decades 10 ⁰ through 10 ⁸ , are constructed and connected in a manner identical to that in which the gates of the 10 ⁹ -stage are constructed and connected. Thus, each stage includes a first set of four AND gates, each with one input connected to a conductor of the adder input trunk 143 and with another input connected to the WRITE AIT line 347. Additionally, each stage has a second set of four AND gates, each AND gate having one input individually connected to one conductor of the adder output trunk 144 and having a second input connected to the WRITE AOT line 349. Finally, each of the nine stages of the block of gates 321 has four OR gates connected to two AND gates in the same manner as shown for the 10 ⁹ -stage, the outputs of the four OR gates collectively signaling in binary form the signals which appear on the conductors connected to the particular set of four AND gates enabled through one of the write lines 347 and 349.

To handle signals representing the sign of the number signaled on the trunklines 143 and 144, the block of gates 321 includes an eleventh stage containing a pair of AND-gates 351 and 353. The AND-gate 351 is for passing signals which appear on conductor 143-41 and has one of its inputs connected to that conductor. The other AND-gate 353 is for passing signals appearing on the conductor 144-41 of the adder output trunk 144 and one of its inputs therefore is connected to that conductor. Each of the AND-gates 351 and 353 has a second input which, when signaled by a gating pulse, is operative to open the gate and pass through it the signal applied at its other terminal. The second input terminal of the AND-gate 351 is connected to the WRITE AIT line 347 and the second input terminal of the AND-gate 353 is in turn connected to the WRITE AOT line 349. Again, for the reason mentioned during the explanation of the 10 ⁹ -stage, the outputs of the AND-gates 351 and 353 are applied to an OR-gate 355 so that when a signal is gated through either one of the AND gates, that signal will also appear at the output of the OR gate.

Summarizing the function of the block of gates 321, it may be seen that collectively, the AND gates provide two sets of 41 inputs, each set of inputs being connected to all of the conductors of one of the trunklines 143 and 144 and that the OR gates provide a common set of 41 outputs. By applying a gating pulse to one or the other of the timing lines 347 and 349 at a given instant or time period, the signals appearing during that time period on all of the conductors of a selected one of the trunk lines 143 and 144 may be caused to appear at the common set of outputs. The output terminals of the block of gates 321 are conveniently numbered 321-1 to 321-41, the suffix digits of each output terminal representing the conductor in the adder input trunk 143 or the adder output trunk 144 from which signals may be gated to it.

The signals gated through to the output terminals 321-1 to -41 may be applied to any suitable display device. One such device is shown in FIG. 2d and will be described in detail shortly. Before doing so, however, there will be first described the manner in which signals appearing on a desired one of the trunklines 143 and 144 during a particular time period may be selected. What will be described are two readout control units, one for use by an operator and the other being designed principally for a service man. In the preferred embodiment shown in FIG. 2d, these control units are used together, and share several circuit components. It is to be understood, however, that, while it is particularly advantageous to provide both types of control units for use with a given readout, as illustrated in FIG. 2d, each of the control units could also be used without the other.

b. The Operator's Readout Control Unit.

The principal feature of the operator's readout control is that it permits rapid selection of data to be displayed without particular reference to the time period during which it appears on the trunkline 143 or 144. Instead, the selection may be made by an operator with reference only to the particular signal source or signal utilization device which he wishes to monitor. It will be recalled that the signals produced by the various signal sources of the exemplary numerical control system heretofore described are applied to a multiconductor trunkline such as the adder input trunk 143 through a plurality of gating means typified by the various read gates illustrated in FIGS. 2a and 2b. Similarly, it was shown that in such a system, signals destined for different utilization devices, such as the servo loops 76 and 78, are applied thereto through a second set of gating means such as the write gates 179 and 185. In carrying out that aspect of the invention whereby rapid reading of signals from or to a limited number of signal sources or signal utilization devices is to be achieved, means are provided for continually producing on a plurality of timing lines gating signals which are synchronized with selected ones of the gating signals being applied to the aforementioned pluralities of gating means, such as the read gates and write gates of FIGS. 2a and 2b. Selective switching means are connected between the block of gates 321 and the timing lines for rendering the gates 321 of the block responsive to the gating signal produced on any chosen one of the timing lines. Where more than one trunkline is to be monitored, the selective switching means also includes provision for causing the gating signal on the chosen timing line to be applied to that set of AND gates within the block of gates 321 which receives signals from the particular trunkline carrying the information which the operator wishes to view.

One convenient arrangement for producing the necessary gating signals on a plurality of timing lines is that shown in FIG. 2d wherein each of seven timing lines 357-0 through -x is in effect the output of a program gate 359 of the type already described. Of the seven program gates 359 shown in FIG. 2d, six have been connected to produce gating signals synchronized with gating signals applied to various read or write gates in FIGS. 2a and 2b. The seventh program gate 359 has been left unconnected. It represents one of many possible additional program gates for producing other gating signals which might be required.

Each of the program gates 359 is operative to produce on its output a gating pulse which, when applied to one of the WRITE lines 347 and 349, will cause signals appearing on one of the trunklines 143 and 144 during a particular time period to appear at the output lines 321-1 to -41 of the block of gates 321. To permit selection of a gating pulse appearing on a particular one of the timing lines 357, a plurality of AND-gates 361 is provided, each AND gate having a first input connected to one of the timing lines 357. To the same end, means are provided for selectively enabling any one of the AND-gates 361. One form which such a selector may take is a rotary switch 371 having a plurality of stationary contacts 373-1 through -9, each connected individually to a second input of a respective one of the AND-gates 361. The switch 371 also has a movable contact 375, connected to a source of voltage at a logic 1 level. In order to maintain the AND-gates 361 in a disabled, or closed, state unless their second input receives a logic 1 voltage level from the wiper 375 of the switch 371, the second input of each is connected to a source of logic 0 voltage level, here ground, through individually connected resistors 377.

The outputs of the AND-gates 361 are divided into two groups, 363 and 365. Through suitable means such as the OR-gate 367 the first group of outputs 363 is connected to the WRITE AIT line 347. Similarly, through a second suitable means such as the OR-gate 369, conductors of the second group 365 are connected to the WRITE AOT line 349. A gating pulse appearing on a particular timing line 357 may be caused to have the effect of passing signals from either the adder input trunk 143 or the adder output trunk 144 by connecting it to the input of the appropriate one of the OR-gates 367 and 369.

The AND-gates 361 also have a third input, all of them connected to a common conductor 379 as shown in FIG. 2d. The conductor 379 is connected to a logic 0 voltage level or ground through a resistor 381 and to a logic 1 voltage level through a double-pole double-throw switch 383.

In particular, the switch 383 has a movable bridging contact 383-1 and two pairs of stationary contacts 383-2 and 383-3. One contact of each of the stationary contact pairs 383-2 and 383-3 is connected to a source of logic 1 voltage level, the other contact of the pair 383-2 is connected to the operator's readout enable line 379.

With the bridging contact 383-1 in its first position, a logic 1 level voltage is applied to the operator's readout enable line 379. When the bridging contact 383-1 is in its second position, the logic 1 level voltage is removed from the operator's readout enable line 379, and it is pulled up to ground or logic 0 level through the resistor 381.

The AND-gates 361 are, in effect, conditionally operable, being rendered operable only when the switch 383 is thrown to connect their common line 379 to the source of logic 1 voltage level. At all other times, they are rendered inoperable because of the application of a logic 0 voltage level from ground through the resistor 381 and the line 379. This feature permits the WRITE AIT and WRITE AOT lines 347 and 349 optionally to receive gating signals from sources other than the timing lines 357, as when the readout is to be under the control of the serviceman's control unit.

Assuming that it is desired to utilize gating signals from one of the timing lines 357 selected by the operator, the readout control selector switch 383 is thrown so as to enable all of the gates 361. The operator may then select for display, by means of the operator's readout selector switch 371, from among a limited number of signal sources and signal utilization devices. The size of the selection and the particular signal sources and signal utilization devices that the operator may choose is left to the designer. Assume, for example, that with the operator's readout selector switch 371 in its first position, i.e., with movable contact 375 engaging the stationary contact 373-1, the signals in the XP register 123 are to be displayed so as to indicate to the operator the uncorrected command position for the X-axis. Since this information is gated onto the adder input trunk 143 at time period 00, the signal input terminal of the AND-gate 361-0 is connected to a timing line 357-0 carrying a gating signal which is in synchronism with the gating signal applied to the read gates 145. In the illustrated embodiment this is achieved by connecting the inputs of the program gate 359-0, used to produce the gating signal on the timing line 357-0, to the same set of signal sources to which the program gate 279, used for gating the read gates 145, is connected.

Further, since the desired information appears on the adder input trunk 143, the output of the AND-gate 361-0 is made part of the group of conductors 363 which are connected to the input of the OR-gate 367 and through it to the WRITE AIT line 347. Thus, with the operator's readout selector switch in its first position, it is the signals which are in the XP register 123 which will appear at the outputs 321-1 through -41 of the block of gates 321 ten times during each major cycle of the control system.

In a similar manner, the operator may be given the option to observe, with his readout selector switch 371 on its second, third, and fourth positions, the signals in the YP register 125, the X-axis encoder 97, or the Y-axis encoder 107 respectively. These choices are in face the ones assumed for sake of specific examples in the connections indicated for the program gates 359-6, 359-4, and 359-10. In accordance with the same logic as that followed in the case of the program gate 359-0, the inputs of the program gates 359-6, -4, and -10 are connected to the same source of signals to which the program gates 297, 289, and 307 are connected, thereby providing at their outputs gating signals which are in synchronism with the gating signals applied to the read gates 149, 103, and 111 respectively. Since the signals from each of the digital devices to be monitored when the operator's readout selector switch 371 is in its second, third, and fourth positions appear on the adder input trunk 143, the outputs from all three of the AND-gates 361-6, -4, and -10, respectively associated with the program gates 359-6, -4, and -10, are connected to the OR-gate 367 and through it to the WRITE AIT line 347.

Let it be assumed further that the operator is to have the choice of displaying the contents of the XE register 181 and the YE register 183 with his selector switch 371 on its fifth and sixth position, i.e., with the wiper 375 engaging the stationary contacts 373-5 and -6. This may be accomplished in accordance with the illustrated embodiment of the invention by producing, on the timing lines 357-5 and 357-11, respectively connected to the first inputs of a pair of AND-gates 361-5 and -11, whose second inputs are respectively connected to the switch stationary contacts 373-5 and -6 gating signals which are in synchronism with those applied to the timing lines 217 and 225 of the write gates 179 and 185 associated with the registers XE 181 and YE 183 respectively.

In terms of the program gates 359 which are employed to produce the gating signals on the timing lines 357, this is achieved by connecting the inputs of the program gate 359-5 to the same set of signal sources to which the inputs of the program gate 295 are connected and by similarly connecting the inputs of the program gate 359-11 to the signal sources matching those supplying the program gate 311. Since the signals which are applied to the XE and YE registers are both carried by the adder output trunk 144, the outputs of the AND-gates 361-5 and -11 are made part of the group of output lines 365 and are both connected through the OR-gate 369 to the WRITE AOT line 349.

From the above description of the construction and manner of operation of the operator's readout selector unit under the control of the operator's readout selector switch 371, it is clear that the number of data sources or data utilization devices whose outputs may be displayed under the control of the selector switch 371 or similar selector device is limited only by the capacity of the switch and by the number of timing lines and associated switching means such as the AND-gates 361. It is also apparent that the program gates 359 illustrated in FIG. 2d are merely one means for providing the necessary gating pulses on the timing lines 357. Indeed, they have been illustrated as separate and apart from the program gates used to provide gating signals for the read and write gates of FIGS. 2a and 2b mainly for sake of clarity. In practice, the program gates 359 may be either separate from and in addition to those used to operate the read and write gates of FIGS. 2a and 2b or they maybe one and the same, provided that the program gates have sufficient output capacity or "fan out" to handle the added load. Stated differently, a display gating signal which is synchronized with a gating signal used to enable a particular read or write gate may be produced on a given timing line 357 by directly connecting that timing line to the output of the program gate servicing the particular read or write gate. Additionally, the timing signal inputs of the various read and write gates of FIGS. 2a and 2b may receive gating signals not from individual program gates but from a large decoder such as that shown in FIG. 8 which is operative to produce the required sequentially timed gating signals on a plurality of individual output lines. In such a case the timing lines 357 may be connected either to the outputs of a second decoder independent from the first or, where desired, they may be connected to selected outputs of the first decoder so that with the operator's readout switch 371 in a particular position, an appropriately timed gating signal may be applied to its associated gate 361.

c. The Serviceman's Readout Control Unit

A second significant feature of the invention pointed to earlier is that it permits display, if desired, of information appearing on a selected trunkline during any particular time period in which information is transmitted on that line. In carrying out this aspect of the invention, there is provided a switchable program gate 385 as well as switching means connected between the inputs of the program gate and the outputs of the timing signal generator 251 for selectively connecting the program gate inputs to various selected combinations of the timing signal generator outputs, thereby producing at the output of the program gate a timing signal which is in synchronism with any selected timing signal derived from the timing signal generator 251 and applied to one of the read or write gates used to apply signals to or draw signals from the trunklines 143 and 144. In implementing this aspect of the invention, means are also provided for applying the output of the switchable program gate 385 to the inputs of the AND gates forming part of the block of gates 321. In the illustrated embodiment, wherein two sets of AND gates are provided for transferring data from a pair of multiconductor trunklines, provision is made for applying the output of the switchable program gate 385 to a selected one of the groups of AND gates so as to cause the gating signal produced by the program gate 385 to pass data from the selected one of the pair of trunklines.

Turning now to the preferred embodiment of the invention, the switchable program gate 385, illustrated as an AND gate, has three inputs 385-1, 385-2, and 385-3 corresponding in that order to the 100s, 10s, and units decade input terminals of the other program gates in the system. Timing signals for the program gate 385 are provided through a set of three rotary switches 387, 389, and 391 collectively labeled "serviceman's readout selector." Each of the three rotary selector switches has ten stationary contacts connected to the 10 output terminals of the respective decades of the timing signal generator 251. Thus, the output signals of the 100s decade of the timing signal generator 251 appear on 10 terminals of the 100s decade selector switch 387 labeled 000 through 900; the 10 stationary contacts of selector switch 389, labeled 00 through 90 receive the signals produced on the corresponding output terminals of the 10s decade of the timing signal generator 251, and the units decade timing signal generator output signals appear on the ten stationary contacts labeled 0 through 9 of the units selector switch 391.

By connecting the wipers 387-1, 389-1, and 391-1 of the 100s, units, and 10s decade selector switches 387, 389, and 391 to the 100s, 10s, and units decade input 385-1, 385-2, and 385-3 of the program gate 385, it may be made to receive three logic 1 level signals during any one of the 1000 time periods through which the timing signal generator 251 cycles.

Through a line 393, the output of the switchable program gate 385 is applied to a pair of AND-gates 395 and 397 and through them to either the WRITE AIT line 347 or the WRITE AOT line 349. If the serviceman's readout control unit were used by itself without the operator's readout control unit, the outputs of the AND-gates 395 and 397 might be connected directly to the respective ones of the WRITE AIT and WRITE AOT lines 347 and 349. In the preferred embodiment, where the control units are shown as being used together, the output of the AND-gate 395 is applied to an input of the OR-gate 367 and similarly, the output of the AND-gate 397 is applied to an input of the OR-gate 369. Thus the AND-gates 395 and 397 are operatively connected through the OR-gates 367 and 369 to respective ones of the WRITE AIT and WRITE AOT lines 347 and 349.

Each of the AND-gates 395 and 397 has a second input terminal connected through line 399, labeled "serviceman's readout enable" to the second contact of the switch contact pair 383-3, referred to in connection with the operator's readout control unit. Through a resistor 401, the serviceman's readout enable line 399 is also connected to ground, representing logic 0 level. Accordingly, so long as the bridging contact 383-1 of the readout control selector switch 383 is in its first position in which it applies a logic 1 voltage level to the operator's readout enable line 379, the AND-gates 395 and 397 are disabled by the 0 logic level voltage applied to them through the resistor 401. On the other hand, when the selector switch 383 is in its second position, with its movable bridging contact applying logic 1 level voltage to the serviceman's readout enable line 399, the AND-gates 395 and 397 are conditionally enabled, permitting the gating signal produced by the switchable program gate 385 to pass through at least one of them. It is apparent that, following the terminology applied to the several AND-gates 361 which were called "conditionally operative selective gating means," the AND-gates 395 and 397 also comprise conditionally operative gating means connected between the output of the program gate 385 and the input gating means formed of the block of gates 321 and that the switch 383 serves to cause signals to be passed through the block of gates 321 and to a display device under the control of gating signals either from the program gates 359 or from the switchable program gate 385 by selectively rendering either the AND-gates 361 operative through the operator's readout enable line 379 or by rendering the AND-gates 395 and 397 operative through the serviceman's readout enable line 399.

Means are also provided for opening one of the AND-gates 395 and 397 and for disabling the other so as to cause the gating signal from the program gate 385 to be applied to the appropriate one of the WRITE AIT and WRITE AOT lines 347 and 349. To this end, each of the AND-gates 395 and 397 has a third input terminal and means are provided for alternatively applying an enabling, or logic 1 level, voltage to the third input terminal of one or the other of the AND-gates 395 and 397. For this purpose, a trunk line selector switch 403 is provided, which may be of the same construction as the readout control selector switch 383. Thus, the switch 403 has a movable bridging contact 403-1, a first pair of stationary contacts 403-2 bridged by the movable contact 403-1 when the switch is in its first position and a second pair of stationary contacts 403-3 which are bridged by the movable contact 403-1 when the switch is in its second position.

One of each of the two pairs of stationary contacts 403-2 and 403-3 is connected to a source of logic 1 voltage level. The other contact of each of the pairs is connected to one of the AND-gates 395 and 397. Specifically, the third input terminal of AND-gate 395 is connected through line 405 to one of the contacts of the pair 403-2, and the third input of the AND-gate 397 is connected through line 407 to one of the contacts of the pair 403-3. Thus, with the movable contact 403-1 in its first position, logic 1 voltage level is applied to the third input of the AND-gate 395 and a similar voltage is applied to the third input of the AND-gate 397 when the switch 403 is in its second position.

In order to assure that only one of the AND-gates 395 and 397 is held open at any given time, the third input terminal of each of the gates is connected through a resistor to a logic 0 level or ground. This is achieved simply by individually connecting the lines 405 and 407 to ground through resistors 409 and 410.

Summarizing the operation of the serviceman's control unit, the control unit selector switch 383 is placed in its second position, providing a logic 1 voltage level over the serviceman's readout enable line 399 to the AND-gates 395 and 397. Then, depending upon whether the information to be read appears on the adder input trunk 143 or the adder output trunk 144, the trunkline selector switch 403 is placed in its first or second position, thus applying an enabling voltage to one or the other of the AND-gates 395 and 397. Assuming for sake of example that the desired information appears on the adder input trunk 143 and that the AND-gate 395 has been enabled, the next step will then be to set the serviceman's readout selector switches 387, 389, and 391 to a setting which will result in a gating pulse at the output of switchable program gate 385 at the appropriate time period. Thus, if the information to be viewed appears on the adder input trunk 143 during time period 746, for example, the wipers of the 100s, 10s, and units decade readout selector switches 387, 389, and 391 would be set to their 700, 40, and 6 positions respectively. The timing pulse would then be passed from the output of the switchable program gate 385 over the line 393, through the AND-gate 395, and through the OR-gate 367 to the WRITE AIT line 347. It is evident then, that at time period 746, the information which appears on the adder input trunk 143 will be passed through the block of gates 321, available for display by suitable display devices. A specific type of such a display device will be described next.

d. The Display Unit

Signals which have been selected for display appear at the output terminals 321-1 through -41 of the block of gates 321 for a period whose length corresponds to the basic time period (the day) of the control system. In the exemplary system described, this time period was chosen to be twenty microseconds. In keeping with the invention, means including a plurality of inputs are provided for displaying these extremely short signals for a sufficiently long time to be perceived by the human eye and according to a preferred embodiment of the invention, the input signals are displayed in decimal form, although they are digitally coded. A suitable display unit, generally indicated by the reference numeral 411, is illustrated in block form in FIG. 2c. It includes two principal subsections, a temporary storage and decoding unit 413 and a numerical indicator array 415. Both of the subunits 413 and 415 include a plurality of identical stages, one stage for each digit of the number that may be signaled on the trunklines 143 or 144. Thus, with the numerical control system illustrated herein, the subunits 413 and 415 would both have ten stages for temporarily storing and then displaying signals on the trunk line conductors 143-1 to -40 and 144-1 to -40. Both of the subunits include an 11th stage for temporarily storing and displaying the sign of the number handled by the other 10 stages and signaled on trunk conductors 143-41 and 144-41.

Turning now to the 10 ⁹ stage of the temporary storage and decoding unit 413, it includes four gated flip-flops 417, 419, 421, and 423 which may be of the same type as those illustrated in FIG. 5a and described previously for use in the XE and YE registers 181 and 183 of FIG. 2a. Respective ones of the flip-flops 417, 419, 421, and 423 are for temporarily storing the 8, 4, 2, and 1 binary weight signals from the outputs of the 10 ⁹ -stage of the gate block 321 and to this end their D (data) inputs are respectively connected to receive signals from the OR-gates 345, 343, 341, and 339 through the output lines 321-40, -39, -38, and -37 of the block of AND-gates 321.

To assure that during each time period the signals which are transferred from the trunklines 143 and 144 through the block of gates 321 to the flip-flops 417-423 occur after the adder 135 has completed its operation for that time period, a WRITE CLOCK signal is applied during each time period to the C (clock) input terminals of each of the gated flip-flops 417-423 over the line 425. The timing signal which is applied to the line 425 is the same as that which is applied to the clock lines 219 and 227 of the XE and YE registers 181 and 183. The manner of producing the WRITE CLOCK signal and its exact time relation with respect to the time when the adder 135 has completed its operation will be described immediately following the detailed description of the adder.

It is evident then, that the four signals which are taken from one of the trunklines 143 and 144 will be stored in the flip-flops 417-423 for a length of time which begins with the WRITE CLOCK signal produced during the time period in which the signals are gated through the block of gates 321 and which ends during the corresponding time period of the next major cycle, year, of the control system. This follows, since only one gating signal will be applied by the readout control units of FIG. 2d to the block of gates 321 during any given major machine cycle. Thus, since in the exemplary embodiment a major machine cycle or year is 20 milliseconds long, each set of signals taken from the trunk lines 143 and 144 will be stored in the gated flip-flops of the storage and decoding unit 413 for 20 milliseconds.

The signals which are stored in the flip-flops 417-423 appear on their 0 and 1 outputs in binary form. To convert them into pure decimal notation, a binary-coded-decimal to decimal converter 427 is employed. The code converter unit 427 may be of the same construction as the units 263-271 used in the timing signal generator 251. Such code converting units are commonly used in computer technology and may include a simple diode matrix having eight input lines and ten output lines, the latter indicated by reference numerals 429-0 through -9. Each output line is associated with respective ones of the numbers 0 through 9 signaled in binary coded decimal form at the inputs of the device which is operative to produce, in response to the input signals a single signal on that one of its output lines which corresponds to the signaled number.

The signals which appear on the output lines of the code converter 427 are amplified into large, and for display purposes preferably negative, voltages by a set of drivers indicated by the block 431. Typically there will be one driver or amplifier for each of the 10 output lines of the code converter 427, with the output of each driver appearing on one of the 10 output lines 433-0 through -9 of the block of drivers 431.

Summarizing the operation of the temporary storing and decoding unit 413, signals which are gated through and appear on the output lines of the block of gates 321 for a very short time period during each major cycle of the machine tool control unit are temporarily stored, still in digital form, in a set of gated flip-flops 417-423. Following code conversion in the converter 427 and amplification in the set of drivers 431, the decimal digit which was signaled in binary form is displayed as a single signal on one of the output lines 433-0 through -9 of the unit 413 corresponding to the decimal value of the digit. In a similar manner all nine of the remaining digits of the decimal number signaled on the selected trunk line of the control system are temporarily stored and presented in decimal form by the remaining nine stages of the unit 413.

The 11th stage of the temporary storage and code converting unit 413, which serves to process the signal representing the sign of the number processed by the first 10 stages of the unit, includes only a single gated flip-flop 435. Furthermore, the 0 and 1 outputs of the gated flip-flop 435 are directly connected to a pair of drivers 437 and 438. Since the sign of the signaled number is signaled on a single pair of lines, there is no need to convert from binary to decimal notation. The D input of the gated flip-flop 435 is simply connected to the output line 321-41 of the block of gates 321 and the C input of the flip-flop is connected to the WRITE CLOCK signal line 425. Accordingly, at the same time that the number signaled on a selected trunkline during a selected time period is signaled in decimal notation on the outputs of the first 10 stages of the unit 413, the sign of the number will be signaled at the output line 439 of the driver 437 if the sign is positive and on the output line 440 of the driver 438 if the sign is negative. In either case the sign signal will be maintained for the same length of time as the signals representing the 10 digits of the number.

It will be apparent that the numbers which are signaled at the outputs of the temporary storage and code-converting unit 413 might be utilized to actuate printout devices which are responsive to decimally coded signals, i.e., to signals which appear on a different one of 10 output lines according to the decimal value of the number that is signaled. In the preferred embodiment, however, the number which is to be monitored is displayed visually by an electronic means. Such a means, indicated generally as the block 415, is an array of numerical indicators numbered 415-0 through 415-10. Such devices are commercially available, such as the numerical indicator tube sold by the Burroughs Corporation under the NIXIE trademark. This type of numerical indicator is schematically shown in FIG. 2c. It includes ten cathodes numbered 0 through 9 and arranged in a stack, each shaped in the outline of a different one of the 10 decimal indicia 0 through 9. Each of the cathodes 0 through 9 is connected to an individual input terminal of the device and all of the cathodes are operatively associated, within a common gas-filled envelope, with a common anode 416 connected to a source of positive voltage, so that respective ones of the 10 cathodes can be made to glow and to thus display the indicium which they represent by applying a negative potential to the input terminal to which they are connected.

Referring to the numerical indicator 415-9 used to display the 10 ⁹ -digit of the number which is signaled during a desired time period on a selected one of the trunklines 143 and 144, the indicator has 10 input terminals each connected to one of the output lines 433-0 through 433-9 of the set of drivers 431 and is thus operative to display in decimal form the number which was originally signaled in binary coded decimal form on the monitored trunkline. In a similar manner, the remaining nine indicators 415-0 through -8 receive the outputs of the other nine stages of the temporary storage and code converting unit 413 and are operative to display in decimal form the other nine digits of the number signaled in binary coded decimal form on the selected trunkline.

The eleventh stage 415-10 of the array of numerical indicators 415 need only have two indicia-representing cathodes, one shaped + and the other shaped -. The + shaped cathode would be connected through its associated input terminal to the output line 439 of the + driver 437 and similarly the - shaped cathode would be connected to the output 440 of the - driver 438.

3. Detailed Description of a Parallel Digital Adder

Electronic digital adders capable of both adding and subtracting are well known to those skilled in the computer art. An arithmetic unit capable of performing addition, subtraction, multiplication, and division of digitally signaled numbers is described in Chapter 21 of Digital Computer Principles by the Burroughs Corporation, McGraw-Hill Book Company, Inc., 1962. There will be described here a digital adder capable of addition and subtraction which is particularly suitable for operation in the exemplary machine-tool-control system described herein. To simplify the description, the adder will be shown as having only two decades 451 and 452, units and 10s. It will be readily apparent, however, that it may be converted to include additional decades capable of handling numbers having more than two digits. The lowest order digit signaled over the trunklines is referred to as the units digit for ease of reference only. It will be understood that in practice the highest order digit so signaled may be in the 100s decade, and that the lowest order digit signaled and processed by the adder may be of the 10 ⁷ -order decade.

a. Timing the Addend Register

As seen in FIG. 9, both stages of the adder are essentially the same. Turning to the units decade first, signals from the adder input trunk are received by an addend register 453 having four gated flip-flops of the same type as those illustrated in FIG. 5b. Each of the flip-flops receives, at its D (data) input, signals from one of four conductors 137-1 to -4 of the adder input trunk 143 which are associated with the units digit of the number being signaled. Each of the gated flip-flops also receives, at its C (clock) input, a data store clock signal. The time of occurrence of the data store clock signal and a suitable means for producing it are producing it are shown in FIGS. 10a-10c.

The basic concept of timing the adder is to subdivide each basic 20-microsecond time period or day of the machine tool control into 10 subperiods of equal duration. In this manner, operations that are to be performed within the adder can be made to assume their proper sequence one after another during each time period of the numerical control system. To this end, the clock pulse source 259, previously described in connection with FIG. 2b as a part of the timing signal generator 251, includes a 500-kilohertz oscillator 455 and a subunits counter 457 constructed exactly like the units, 10s, and 100s counters 253, 255, and 257 of the timing signal generator 251. As the other counters of the timing signal generator, the subunits counter 457 is operative to produce one pulse on its carry output line 458 for each ten pulses which its input receives from the oscillator 455. Additionally, the counter 457 goes through ten different count states between pulses on its carry output 458. Each of its 10 stages is signaled in 5-4-2-1 binary code on its eight binary output lines labeled 0.5, 0.5, 0.4, 0.4, 0.2, 0.2, 0.1, and 0.1.

The logic levels of the binary outputs of the counter 457 are illustrated in FIG. 10b for two successive program steps N and N+1. As indicated earlier, counters operating in the 5-4-2-1 mode, such as the counter 457, are well known and usually include four cascaded flip-flops interconnected by gating in a manner which need not be set out here in detail. It is worth observing in FIG. 10b that the logic level of the 0.1 output of the counter 457 goes through a cycle which lasts through five count states and in which the logic level changes from 0 to 1 and back again with each successive count state of the counter. The same cycle is then repeated during the second five count states of the counter. The logic level on the 0.2 output also goes through a cycle lasting five count states but changing with every second count state only. The 0.4 output and the 0.5 output follow the same general rule except that in the case of the former, the switch from 0 level to 1 level does not occur until four count states have elapsed and in the case of the latter, the same does not occur until five count states have elapsed.

The fifth wave form in FIG. 10b represents the DATA STORE clock pulses of which there is one during each program step. The trailing edge of each DATA STORE clock pulse qualifies the addend registers to receive signals from the adder input trunk 143. The DATA STORE clock pulse marks the beginning of the adder step N which is associated with the program step N. (A program step is synonymous with the basic time period or day of the control system.) Since the trailing edge of the DATA STORE clock pulse is timed to occur at the start of the fifth count state 0.5, it is seen that the adder steps are staggered with respect to the program steps of the counter unit.

The DATA STORE clock pulse is conveniently derived from the outputs of the subunits counter 457 by means of an AND-gate 459 shown in FIG. 10c to the left of the DATA STORE clock pulse wave forms. Its inputs are connected to the 0.4 and the 0.5 outputs of the subunits counter 457.

b. The True/9's Complement Network

Returning now to the description of the units decade shown in FIG. 9, the four outputs of the addend register 453, representing the signal stored in its four gated flip-flops, are applied through four output lines 461 to a true/9's complement unit 463. An exemplary form of such a unit is shown in FIG. 11.

The true/9's complement network of FIG. 11 has a set of three TRUE SELECT AND-gates 467, 469, and 471 associated respectively with the 1, 4, and 8 bit inputs of the network. All three of the TRUE SELECT AND-gates 467, 469, and 471 have a first input connected to respective ones of the 1, 4, and 8 input terminals of the network through lines 473, 475, and 477 respectively. The TRUE SELECT AND gates are also provided with a second input, all of them connected to the TRUE SELECT line 479. The outputs of the TRUE SELECT AND-gates 467-471 are individually connected through an OR gate to a corresponding output of the network 463. Thus the output of the TRUE 1 SELECT gate 467 is connected to the 1 output of the network through a first OR-gate 481, the output of the TRUE 4 SELECT AND-gate 469 is connected to the 4-bit output of the network through a second OR-gate 483, and the 8 bit output of the network receives the output of the TRUE 8 SELECT gate 471 through a third OR-gate 485. The 2-bit output of the ture/9's complement network 463 is directly connected to the 2-bit input of the network through line 487.

It is seen then that application of a logic 1 voltage level to the TRUE SELECT line 479 is operative to apply to the 1-, 4-, and 8-bit outputs of the network the same signals which appear at its corresponding inputs.

Each of the OR-gates 481, 483, and 485 respectively associated with the 1-, 4-5 and 8-bit outputs of the network receives at a second input the output of a COMPLEMENT SELECT AND gate. Thus, the output of a COMPLEMENT 1 SELECT AND-gate 489 is connected to the second input of the OR-gate 481, the output of the 4-bit COMPLEMENT SELECT gate 491 is connected to the second input of the OR-gate 483, and the output of the 8-bit COMPLEMENT SELECT gate 493 is connected to the second input of the OR-gate 485.

Each of the COMPLEMENT SELECT gates 489, 491, and 493 has a first input which receives from various logic gates in the network a signal which when taken with the 2-bit signal on the line 487 and with the logic signals received by the other COMPLEMENT SELECT gates will represent the 9's complement of the number signaled at the input terminals of the network. To cause the 9's complement signals to reach the network output terminals, each of the three COMPLEMENT SELECT gates 489, 491, and 493 has a second input connected in common to a 9's COMPLEMENT SELECT line 511. Application of a logic 1 voltage level signal to the 9's COMPLEMENT SELECT line 511 rather than the TRUE SELECT line 479 causes the signals which are passed through the output OR-gates 481, 483, and 485 to be those which are applied to the first inputs of the COMPLEMENT SELECT gates 489, 491, and 493 only.

Turning now to the logic gates used to produce the 9's complement signals, the COMPLEMENT SELECT gate 489 associated with the 1-bit output receives at its first input a signal from an inverter 495 whose input is in turn connected to the 1-bit input of the true/9's complement network 463. Accordingly, the input to the COMPLEMENT SELECT gate 489 is 1. The first input of the COMPLEMENT 4 SELECT gate 491 receives a signal from an OR-gate 497 having a first input connected to the output of an AND-gate 499. The AND-gate 499 has a first input connected to the 2-bit input of the network and a second input connected to the output of an inverter 501 whose input is the 4-bit input of the network. The OR-gate 497 also has a second input connected to the output of an AND-gate 503. The AND-gate 503 has two inputs, the first of them connected to the output of an inverter 505 whose input is connected to the 2-bit input of the network and the second of them connected to the 4-bit input of the network.

From an inspection of the connections of the gates feeding the OR-gate 497, it may be seen that the signals which that OR-gate applies to the 4-bit COMPLEMENT SELECT gate 491 may be expressed as 4 ^. 2+4 ^. 2.

Finally, the first input of the 8-bit COMPLEMENT SELECT gate 493 is connected to a single AND-gate 507 having three inputs, the first of which is connected to the inverter 505 receiving a 2 signal therefrom. The second input of the AND-gate 507 is connected to the output of the inverter 501 receiving a 4 output from it. Finally, the third input of the AND-gate 507 is connected to an inverter 509 whose input is connected to the 8-bit input of the network. It is apparent from inspection of the inputs to the AND-gate 507 that its output is 2 ^. 4 ^. 8.

The ability of the network of FIG. 11 to produce the 9's complement of a binary coded number applied to its inputs may be readily confirmed by referring to the following rules which the network follows:

1. produce a 1-bit output when the input contains no 1 bit (i.e., when the input is 2, 4, 6, or 8 so that the output should be 7, 5, 3, or 1);

2. produce a 2 bit when the input number contains a 2 bit (i.e., when the input number is 2, 3, 6, or 7 so that the output number should be 7, 6, 3, or 2);

3. produce a 4 bit only if the input number contains a 4 bit but not a 2 bit (i.e., when the input number is 4 or 5) or when the input number contains a 2-bit but not a 4-bit (i.e., when the input number is a 2 or a 3). In sum, produce a 4 bit when the input number is 2, 3, 4, or 5, so that the output number should be 7, 6, 5, or 4.

4. produce an 8 bit only if the input number contains neither a 2 bit nor a 4 bit nor an 8 bit signal (i.e., when the input number is 0 or 1 so that the output number should be 8 or 9).

c. The Parallel Adder

The outputs of the true/9's complement network 463 are applied to a corresponding set of four inputs of a parallel adder 513. Suitable parallel adders are frequently used and well-known parts of computer systems and will not be described in detail here. It may be noted that the parallel adder 513 includes four cascaded stages, each stage comprising a full adder, respective stages receiving the 1-, 2-, 4-, and 8-bit signals of 4-bit numbers. Full adders are also quite well known. Reference may be made to pages 339-340 of the Burroughs Corporation book on Digital Computer Principles wherein a full adder is described. Each full adder has three inputs, two of them for receiving correspondingly weighted bits of the addend and augend numbers and the third for receiving a carry input signal. In the illustration of a parallel adder, in FIG. 9, the first inputs of the respective stages of the adder 513 are labeled A1, A2, A4, and A8 for receiving the four bits of the addend digit and similarly the second inputs of the respective full adder stages are labeled B1, B2, B4, and B8 for receiving the 4 bits of the augend digit. The carry input of each of the four full adder stages will be referred to as C _i . Although all four of the stages have such an input, only that for the first stage is shown in FIG. 9.

Each full adder stage has two outputs, one representing sum, the other representing carry. The sum outputs of the stages are labeled D1, D2, D4, and D8, and represent the results of the binary addition of the three binary signals applied to the stage. The carry outputs of the 1, 2, 4, and 8 bit full adder stages are labeled 2C ₀ , 4C ₀ , 8C ₀ , and 16C ₀ respectively. The 1 bit stage of the full adder 513 receives a signal at its C _i input from an external source, the C _i inputs of the 2-, 4-, and 8-bit adders each receive the C ₀ output of the previous bit adder stage.

The following table, adapted from page 340 of the Burroughs Corporation book Digital Computer Principles shows the signals which will appear at the various D and C ₀ outputs of the parallel adder in response to the various combinations of signals applied to its A, B, and C inputs. ------------------------------------------------------------ --------------- ------------------------------------------------------------ --------------- Full Adder Truth Table

Augend X 0 1 0 0 1 01 Addend Y 0 0 1 0 0 11 Carry C _in 0 0 0 1 1 11 Sum S 0 1 1 1 0 01 Carry C _out 0 0 0 0 1 11 ____________________________________________________________ ______________

d. The "Add-6" Subadder

The outputs of the parallel adder 513, appearing on the lines D1, D2, D4, and D8, represent the sum of the numbers signaled at its C _i input and at its A and B input groups. The parallel adder 513, having four stages, is capable of producing a number up to 15 on its D1, D2, D4, and D8 outputs. This is undesirable since the adder 513 is part of the units decade and is actually supposed to produce numbers up to 9 only and is then supposed to produce a carry signal to be applied to a corresponding parallel adder of the next higher decade. It is to this end that the "10 C ₀ " network 515 and the "add-6 subadder" 517 are provided. The gating network 515, better shown in FIG. 12, includes an OR-gate 518 whose output is that of the network 515. One input of the OR-gate 518 is connected to the 16C ₀ output of the 8 -bit stage of the parallel adder 513. The other input of the OR-gate 518 is connected to an AND-gate 519 having one input connected to the D8 output of the parallel adder 513 and another input connected to the output of an OR-gate 521. The OR-gate 521 has two inputs, respectively connected to the D4 and D2 outputs of the parallel adder 513. Consequently, the gating network 515 produces a carry output signal whenever the sum of the inputs to the units decade parallel adder 513 is 10 or greater. This carry output is applied over the line 523 to the 10-decade parallel adder 525 which receives signals representing the tens digit from the adder input trunk 143 through an addend register 527 and a true/9's complement network 529 in the same manner in which the units digits are applied to the units-decade parallel adder 513.

To compensate for the injection of 10 into the sum which will be produced by the 10s-decade of the adder 135 due to the 10C ₀ carry pulse, 6 is automatically added to the sum produced by the units decade parallel adder 513 every time that a carry signal is produced by it. Assume, for example, that the units digit of the addend is 7 and that the corresponding digit of the augend is 8. The sum signaled at the D1, D2, D4, and D8 outputs will be 15 and a carry signal will be applied to the 10s-decade parallel adder 525. Thus, there is an excess of 10 over the correct result. But if the sum in the units decade is increased by 6 from 15, the result will be 21, represented by a 16 bit, a 4 bit, and a 1 bit. If the 16 bit is discarded the result is 5, which is what it should be for the units decade. In general, it may be stated that the addition of 6 to a binary number which is greater than 9 has the same effect as subtracting 10 from it, provided that the adder in which the addition of 6 is performed does not have a fifth stage for the 16 bit which would result from such an addition.

The add-6 subadder 517 receives at its 4 addend inputs the D1, D2, D4, and D8 outputs of the units parallel adder 513. At the augend inputs of its 2 and 4 bit full adder stages, the subadder 517 receives, over line 531, the output of the 10C ₀ gating network 515 so that each time such a carry signal is produced, 6 is automatically added to the sum produced by the parallel adder 513. Since the subadder 517 does not have a fifth stage, the addition actually results in the subtraction of 10 from the previous sum in the manner explained above.

e. The Second True/9's Complement Network

The outputs of the subadder 517, labeled F1, F2, F4, and F8 are applied to the inputs of a second true/9's complement network 532 which may be exactly the same as the first true/9's complement network 463. Thus, the network 532 has a TRUE SELECT input 533 and a 9's COMPLEMENT SELECT input 534.

Under circumstances which will be explained shortly, a select signal will be applied to the TRUE SELECT input 533 so as to cause the network 532 to transmit signals applied to it by the subadder 517 unchanged. Under other circumstances, the 9's COMPLEMENT SELECT line 534 will be enabled, causing the 9's complement of the number signaled at the inputs of the network 532 to be produced at its output.

f. The Accumulator Register

The outputs of the true/9's complement network 532, labeled G1, G2, G4, and G8, are applied to respective ones of four stages of an accumulator register 535 which may be identical in construction to the addend register 453. Thus, respective ones of the G1, G2, G4, and G8 outputs of the network 532 are applied to the D (data) inputs of the respective gated flip-flops of the accumulator register 535 and each of these flip-flops will be gated at an appropriate instant by application of a DATA STORE clock pulse to their C (clock) inputs. The outputs of the four flip-flops which make up the accumulator register 535 represent the 1, 2, 4, and 8 outputs of the units decade 451 of the adder 135 and are appropriately numbered 139-1 to -8. They are connected directly to the adder output trunkline 144 (see FIG. 2b).

The outputs 139 of the accumulator register 535 also serve as the augend to which subsequently received numbers are to be added. To this end, the respective ones of the four outputs 1, 2, 4, and 8 of the accumulator register 535 are individually connected through a set of four AND-gates 541 to the B or augend inputs of the units decade parallel adder 513. Thus the 1 output of the accumulator register 535 is connected through AND-gate 541-1 to the B1 augend input of the 1-bit stage of the parallel adder 513. The 2-bit stage of the parallel adder receives at its augend input B2 and through a second AND-gate 541-2 the 2-bit output of the accumulator register 535. The 4-bit output of the register 535 is connected through a third AND-gate 541-4 to the B4 augend input of the adder 513, and finally the B8 augend input of the 8-bit stage of the parallel adder 513 receives the 8-bit output of the accumulator register 535 through a fourth AND-gate 541-8.

Each of the four AND-gates 541 has a second input jointly connected to a common terminal labeled CAR. Normally, in the absence of a CAR signal, i.e., when CAR is at logic 1 voltage level, the AND-gates 541 are open and serve to apply the outputs of the accumulator register 535 to the augend (B) inputs of the parallel adder 513. The circumstances under which a CAR signal is produced to close the gates will become apparent as this description proceeds.

g. The 10s Decade of the Adder

The foregoing description has concentrated on the elements found in the units decade of the adder 135. The tens decade of the adder includes exactly the same elements.

Thus a 100C ₀ signal is produced by gating network 542 whose inputs are connected to the outputs of the 10s decade parallel adder 525 in the same manner in which the corresponding gating network 515 of the units decade is connected to its associated parallel adder 513. The output of the 100C ₀ gating network 542 is connected to the 20-bit and 40-bit augend inputs of an add-60 subadder 543 whose 10-, 20-, 40-, and 80-bit addend inputs receive the corresponding outputs labeled D10, D20, D40, and D80 of the parallel adder 525. Thus, 60 is automatically added to the output of the parallel adder 525 whenever it exceeds 90.

The four outputs of the add-60 subadder 543, labeled F10, F20, F40, and F80 are applied to the corresponding inputs of a true/9's complement network 544 having a pair of select inputs corresponding to similar inputs 533 and 534 of the units decade true/9's complement network 537.

The output of the add-60 subadder 543 is thereafter transmitted by the true/9's complement network 544 either intact or 9's complemented to an accumulator register 545. The four outputs of the accumulator register 545, labeled 139-10, -20, -40, and -80, are directly connected to conductors of the adder output trunk 144 and are also connected through a set of four control AND-gates 546 to the corresponding augend inputs B10, B20, B40, and B80 of the 10s-decade parallel adder 525. The control gates 546 are held open by the same CAR signal which maintains the units decade control gates 541 open.

h. Adder Mode Control

Turning now to that part of the adder 135 which determines whether the adder should work in the add mode (termed "like sign addition") or the subtract mode (termed "unlike sign addition"), the determination is made on the basis of three criteria. The first criterion is whether the addend should be algebraically added to the augend or whether it should be subtracted therefrom. The second criterion is the sign of the addend and the third criterion is the sign of the augend.

Normally, the adder operates in the "add" mode. The adder mode control network comprising the block 547 includes four three-input AND gates for producing a control signal in response to selected combinations to the three criteria referred to above for causing the adder to operate in the "subtract" mode. The operation of these gates may be summed up by stating that, in response to signals fed to them, they will cause the adder 135 to operate in the subtract mode under the following two conditions: (1) if the addend and augend are of like sign, but the first is to be algebraically subtracted from the second (Although the terms subtrahend and minuend are usually employed when discussing subtraction, for sake of simplicity, the terms addend and augend will be employed for both addition and subtraction.), and (2) if the addend and augend are of unlike sign and the first is to be algebraically added to the latter.

The first criterion, whether or not the addend is to be added to the augend or whether it is to be subtracted therefrom, is signaled on the FORCE SUBTRACT line 138. If a logic 1 voltage level appears on the FORCE SUBTRACT line 138 during a given time period (or program step), it means that the addend is to be subtracted from the augend, while the absence of a signal on the line 138 signifies that an addition is required. As shown in FIG. 2b, the FORCE SUBTRACT signal may be produced on control input 138 by a suitable program gate, such as 291 and 309, during the time period in which it is desired to effect a subtraction rather than an addition of the addend and augend.

The second criterion, the sign of the addend which appears on the adder input trunk, is signaled on the adder input trunk conductor 143-41, as explained previously in connection with FIG. 3. Finally, the third criterion, the sign of the number produced by the adder during a given time period on its output lines 139, is indicated on a pair of lines 551 and 553 connected respectively to the 1 and to the 0 outputs of the accumulator sign flip-flop 555. In its first stable state the accumulator sign flip-flop 555 applies a logic 1 voltage level through its 0 output to the AOT line 553, indicating that the sign of the number stored in the accumulator resistor is not negative, i.e., that it is positive. Conversely, when the sign flip-flop 455 is in its second state, it applies a logic 1 voltage level through its logic 1 output to the AOT-line 551 signifying that the signal to be applied to the adder output trunk is negative.

The AIT signal appearing on line 143-41, the AOT signal on line 551, and the FORCE SUBTRACT signal on line 138, are applied to the three inputs of AND-gate 558 so as to produce at its output a signal when both the addend and augend are negative and the addend is to be subtracted from the augend. The AIT signal, representing a positive number on the adder input trunk and produced by inversion of the AIT signal by means of an inverter 557, is applied to the first input of the second adder mode control gate 559. The second input of the AND-gate 559 receives the AOT signal over line 553 and its third input is supplied from the FORCE SUBTRACT line 138. Therefore, the second control gate 559 produces an output when both the addend and augend are positive and the addend is to be subtracted from the augend. The third control gate 560 receives its first input from the AIT line 143-41 and its second input from the AOT line 553. The third input of AND-gate 561 is FORCE SUBTRACT and is derived through an inverter 562 from the FORCE SUBTRACT signal on line 138. Thus, the third control gate 560 produces its control signal when the addend is to be added to the augend but the two are of unlike sign, the addend being negative and the augend positive. Finally, the three inputs of the fourth control gate 561 are respectively connected to the output of the inverter 557 to receive the AIT signal, to the AOT line 551 to receive the AOT signal, and to the output of the inverter 562 to receive the FORCE SUBTRACT signal therefrom. Accordingly, a signal will be produced by the fourth control gate 561 when the addend is to be added to the augend but they are of unlike sign because the addend is positive, and the augend is negative.

The outputs of the four control gates 558, 559, 560, and 561 are applied to a common OR-gate 565 producing at its output a signal for all of the conditions which would require the adder to operate in an "unlike sign addition" or subtract mode, i.e., addend subtracted from augend, both of like sign, or addend added to augend but of unlike sign. The signal produced by the OR-gate 565 will be referred to as the "ungated unlike sign addition" signal or UL (ungated). In order to convert a UL (ungated) signal into a gated UL signal which occurs at the appropriate instant during the cycle of the adder, the ungated UL signal is applied to the D (data) input of a UL flip-flop 567 which may be of the same type as that illustrated in FIG. 5b. The C (clock) input of the flip-flop 567 is connected to receive the DATA STORE clock pulse over the clock line 569. Thus, if at the instant when the clock pulse occurs, conditions exist for unlike sign addition, the UL flip-flop 567 is set in its first stable state, producing a logic 1 voltage level (the gated UL) signal on its 1 output labeled UL. Conversely, if, when the data store clock pulse occurs, there is no output from the OR-gate 565, the UL flip-flop 567 is reset into its first stable state, producing a logic 1 level (the gated UL) signal on its 0 output labeled UL.

i. The CAR (Clear Adder Register) Flip-Flop

The first step in a typical series of adder cycles is that of clearing the accumulator registers. Referring to the units decade accumulator register 535, this is achieved by closing the AND-gates 541 which control recirculation of signals from the accumulator register 535 to the augend inputs B1-B8 of the units decade parallel adder 513. For this purpose then, the CAR terminal, connected to one of the inputs of each of the four control gates 541 is connected to the 0 output of a CAR flip-flop 571 shown to the left of the UL flip-flop 567. The CAR flip-flop 571 may also be of the type illustrated in FIG. 5b. Under normal circumstances, no signal is applied to the D input of the CAR flip-flop 571. Accordingly, when it receives a DATA STORE clock pulse over the line 569 which is connected to its C (clock) input, the flip-flop 571 produces a logic 1 voltage level on its 0 output, enabling the AND-gates 541 to which that output is connected. On the other hand, when it is desired to clear the accumulator register 535, a signal is applied to the CAR input line 140. As explained in connection with FIG. 2b, a CAR signal is produced on the CAR line 140 during those time periods in which an adding sequence is to begin and it is produced by means of a program gate such as the program gates 281 and 305 illustrated in FIG. 2b. During such time periods, therefore, on occurrence of the trailing edge of the DATA STORE clock pulse on the line 569, the CAR flip-flop 571 is set in its second stable state in which a logic 0 voltage level is produced on its 0 output which disables the control gates 541.

j. Nine's Complement Subtraction

For Use in performing Unlike sign addition, the 100C ₀ output of the tens decade gating network 542 is fed back over line 572 to the carry input C _i of the units decade parallel adder 513 through an AND-gate 573. The AND-gate 573 has a second input terminal labeled UL which is connected through line 575 to the UL output of the flip-flop 567. The signal thus applied to the carry input of the units decade parallel adder 513 when unlike sign addition is to be performed is labeled the "end around carry" (E/A) and is a commonly used expedient with 9's complement subtraction. According to this type of subtraction, each digit of the addend (properly called subtrahend) is first subtracted from 9 and it is the result which is added to the corresponding digit of the augend (properly called minuend).

The following statements apply to the 9's complement mode of subtraction. The proofs to support these statements will not be derived here, but may be found on pages 47-49 of the Burroughs Corporation book Digital Computer Principles cited previously:

1. If the true result of the unlike sign addition of the addend and the augend has the same sign as the augend (i.e., addend smaller than augend), then the results indicated by the parallel adder stages 513 and 525 and their associated subadders 517 and 543 will be 1 less than the true result, and the highest order decade of the adder, here the 10s order decade, will produce a carry signal, here 100C ₀ .

2. If the true result of the unlike sign addition of the augend and the addend would have a different sign than the augend (addend larger than augend) the result produced by the parallel adders 513 and 525 and their associated subadders 517 and 543 will be the 9's complement of the true result, and the 10s order decade will not produce a carry signal.

From the above it may be seen that connecting the output of the 100C ₀ gating network 542, representing the carry output of the highest adder stage, to the carry input of the lowest adder stage will provide the necessary addition of 1 under the proper circumstances, since the end around carry signal is only produced when the sum produced by the adder is short by 1 of the correct result.

It may also be seen that under the circumstances listed under statement (2) above, the signals appearing at the outputs of the subadders 517 and 543 must be recomplemented in order to produce the correct result. Accordingly, means are provided for detecting the existence of the conditions of statement (2) above under which recomplementing of the outputs of the subadders is necessary and when these conditions are detected, the 9's COMPLEMENT SELECT inputs of the true/9's complement networks 532 and 544 which receive the outputs of the subadders 517 and 543 are actuated. For this purpose, the 9's COMPLEMENT SELECT input 534 of the units decade true/9's complement network 532 which is also connected to the corresponding input of the true/9's complement network 544 is connected over a line 576 to the output of an AND-gate 577. The AND-gate 577 has two inputs, the first being connected to the UL output of the flip-flop 567 through line 579. The second input of the AND-gate 577 receives the signal E/A over line 581 from an inverter 583 whose input is connected to receive the end around carry signal E/A from the output of the 100C ₀ gating network 542. Thus the true/9's complement networks 532 and 544 receive a select signal at their 9's complement input over the line 576 from the AND-gate 577 only when the adder 135 operates in the unlike sign (UL) addition mode and then only if there is no carry signal from the highest order decade.

The TRUE SELECT inputs of the true/9's complement networks 532 and 544 are signaled over another line 585 connected to an OR-gate 587. The OR-gate 587 has a first input connected over to line 589 to receive the end around carry signal E/A from the 100C ₀ gating network 542 and a second input connected over line 591 to the UL output of the UL flip-flop 567. Accordingly, if there is a carry signal from the highest order adder stage, or if the adder is performing like sign addition, the true/9's complement networks 532 and 544 will transmit the signals from their associated sub-adders to their respective accumulator registers without change.

The UL signal and the E/A signal which were shown to be applied to the AND-gate 577 are also used to produce the correct sign for the number resulting from the operation of the adder. For this reason, the UL and the E/A signals are also applied to an additional AND-gate 593 whose output is connected to the C (clock) input of the flip-flop 555. At a third input the AND-gate 593 receives an Accumulator Sign Store clock signal over the line 595.

The Accumulator Sign flip-flop 555 is a complementing flip-flop which changes state on the trailing edge of each signal to its clock input terminal. The flip-flop illustrated in FIG. 5b may be converted into such a complementing flip-flop by eliminating the inverter 205 and by cross-connecting the R input of the AND-gate 207 to the 1 output of the flip-flop and by cross-connecting the S input of the AND-gate 201 to the 0 output of the flip-flop.

The flip-flop 555 is operated on the principle that if a given operation of the adder 135 has caused the sign of the number previously signaled at its outputs to change, then the flip-flop should receive the pulse so as to change its state and thereby the sign indicated at its outputs. Conversely, if the adder operation has not resulted in a change of sign at its outputs, then the flip-flop 555 should receive no signal from the AND-gate 593 so as to continue to indicate the same sign at its outputs. Since the sign of the sum signaled by the adder at the end of a given operation will change only (1) if the operation was an unlike sign addition and (2) if there is no carry signal from the highest order stage, it is seen that the output of the AND-gate 593 to the flip-flop 555 is properly limited to this set of circumstances.

With reference to FIG. 10c, the accumulator sign store clock signal is produced towards the end of each program step by means of an AND-gate 597 having a pair of inputs respectively connected to the 0.4 and to the 0.5 outputs of the subunits counter 457.

k. SUMMARY OF ADDER Operation

A brief resume of the operation of the adder with reference to FIGS. 6, 9, and 10 will help to understand the functions of its various components.

During the first program step N, signals are transmitted from the XP register 123 through its associated read gates 145 and through the adder input trunk 143 to the addend registers 453 and 527, being gated into the latter by the trailing edge of the DATA STORE clock pulse at time T1. During the same program step N, a clear adder register (CAR) signal is also applied to the adder at its input line 140. The CAR signal is clocked through the CAR flip-flop 571 by the DATA STORE clock pulse at time T1 to disable the AND gates connected between the outputs of the accumulator registers 535 and 545 and the inputs of their associated parallel adders 513 and 525. Consequently, depending upon the state of the UL flip-flop 567, the signals gated into the addend registers 453 and 527 are applied with or without 9's complementing to the addend input terminals of the parallel adders 513 and 527, with the augend inputs of the parallel adders receiving no signals from their associated accumulator registers. Accordingly, the augend added to the addend is zero, and the true or 9's complemented signals from the addend registers 453 and 527 are passed unchanged through the parallel adder and their associated subadders 517 and 543 and through the true/9's complement networks 532 and 444 to the inputs of the accumulator registers 535 and 545. Again, whether or not the signals from the subadders 517 and 543 are transmitted without change or are 9's complemented by the networks 532 and 544 will depend upon whether their TRUE or 9's COMPLEMENT SELECT inputs are signaled. It may be readily confirmed, however, from the inputs to the control gates 577 and 587, that if the signals from the addend registers were transmitted through the first pair of true/9's complement networks 463 and 529 without modification, they will be similarly transmitted by the second pair of true/9's complement networks 532 and 544. Conversely, if the signals were 9's complemented by the first pair of networks, they will be recomplemented by the second pair of networks. In either case, the number signaled at the inputs of the accumulator registers 535 and 545 is the same as that which was signaled into the addend registers 453 and 527. Because the lagging edge of the DATA STORE clock pulse will have vanished by the time the signals from the addend registers will have reached the accumulator registers 535 and 545, the signals will not be entered into the latter registers but will instead continue to be applied to the inputs of the registers until the trailing edge of the following DATA STORE clock pulse in the next program step N+1.

Just before the occurrence of the second program step N+1 the ACCUMULATOR SIGN STORE clock pulse is produced and on its trailing edge at time T2 a signal will be applied to the accumulator sign flip-flop 555 if the other inputs to the AND-gate 593 indicate that the signals which were read into the addend registers represented a number whose sign differs from the number stored in the accumulator registers during the preceding program step.

During the next program step N+1, signals are transmitted from the XMO register 155 through its read gates 167 and over the adder input trunk 143 to the addend registers 453 and 527. These signals are clocked into the addend registers on the trailing edge of the second DATA STORE clock pulse at time T3. At the same instant, the CAR flip-flop 571 is reset by the DATA STORE clock pulse and applies a CAR signal to the AND-gates 541 and 546, thereby opening them. Also at this instant, the DATA STORE clock pulse gates the signals which had been held at the accumulator register inputs from the previous program step N into the accumulator registers 535 and 545. Consequently, at time T3 the numbers which had been signaled on the adder input trunk during the first program step N are applied through the now enabled gates 541 and 546 to the augend (B) inputs of the parallel adders 513 and 525. With or without 9's complementing by the networks 463 and 529, the signals from the addend registers 453 and 527 are applied to the addend (A) inputs of the parallel adders. Again almost simultaneously, the outputs of the parallel adders 513 and 525 are applied to and appropriately modified or transmitted without change by the subadders 517 and 543 and by the true/9's complement networks 532 and 544 and then are applied to but not immediately entered in the accumulator registers 535 and 545.

The signals which are thus applied shortly after time T3 to the accumulator registers represent the algebraic sum of the numbers signaled on the adder input trunk during the first two program steps N and N+1. At the end of the second program step N+1, the accumulator sign register 555 is again pulsed through the AND-gate 593 if the sum just referred to is of a different sign than the number which had been stored in the accumulator registers during the program step N. Upon the occurrence of the trailing edge of the DATA STORE clock pulse produced during the next (third) program step N+2 (not shown in FIG. 10b but corresponding to time period 02 of FIG. 6) the sum of the numbers signaled during the previous two program steps N and N+1 will be gated into the accumulator registers 535 and 545.

Summarizing the operation of the adder, it may be seen that (1) each cycle of the adder begins halfway through a program step, (2) a number signaled during a given program step on the adder input trunk 143 is entered into the adder at the beginning of the adder step occurring during that program step, (3) the number entered into the adder during a given program step is added to the accumulated sum of the numbers which had been signaled on the adder input trunk during the previous program steps almost instantaneously, but the result does not appear in the accumulator registers of the adder and is not signaled on the adder output terminals 139 until the beginning of the following adder step, occurring during the next program step of the numerical control.

1. Producing the WRITE Clock Signal

As explained previously under the heading "The Error Signal Registers XE and YE in Detail," those registers which are to receive signals from the adder output terminals 139 during a given program step of the control system time period should not be gated to receive such information until the adder has produced the requisite sum or difference for that time period. It was also stated that this is achieved by producing an appropriately timed WRITE clock signal. The means for producing the WRITE clock signal is illustrated in FIG. 10c. For convenience of reference, AND-gate 201 of a typical gated flip-flop 187, illustrated in FIG. 5b, is shown, together with one of the WRITE gates 179 connected to one of its inputs. One of the inputs of the WRITE gate 179 is connected to one of the conductors of the adder output trunk 144 while the other input of the gate is connected to the output of a program gate such as gate 295 (see FIG. 5a). Accordingly, information appears on the D (data) input of the gate 201 during the entire program step for which the program gate 295 is enabled.

The second input of the flip-flop gate 201 is connected to a WRITE clock pulse producing AND-gate 599 whose inputs are connected to receive the 0.2 and 0.5 outputs of the subunits counter 457 of the clock pulse source 529 of FIG. 10a. Reference to the wave forms shown in FIG. 10b of the 0.2 and 0.5 outputs of the subunits counter 457 will show that a WRITE clock pulse is produced during the 0.5 and 0.6 count states of the counter.

FIG. 10b shows, to the right of the AND-gate 201, the wave form of its output if it is assumed that the program gate 295 is connected to produce an output during the program step N+1. It is seen that, since the gated flip-flop is set on the trailing edge of the signal applied to its input, the information from the adder output trunk line 144 will not be entered into the XE and YE registers 181 and 183 until the end of count state 0.8 of the subunits counter 457, well after the adder 135 has deposited the necessary data in its accumulator registers. Since the same WRITE clock signal is also applied to the readout gates 321, the instant during a selected program step or time period at which signals are taken from the adder output trunk is the same as it is for the XE and YE register.

G. CONCLUSION

What has been described as part of a numerical control system for a machine tool is a preferred embodiment of a versatile readout system which allows both simplicity of selection, best appreciated by the machine operator, and large choice of selection, most useful to a service man. For several reasons, a typical machine-tool-control system in which the readout may be incorporated has been described in great detail. First, the readout would in most instances from an integral part of the control system, in many cases utilizing outputs which are also used for timing the flow of information in the control system itself. Indeed, such a readout may be made to form an integral part of a numerical control system.

A second reason has been to illustrate the tremendous utility of such a readout when used in a machine-tool-control system. An attempt has been made to show the large number of components between which information flows in such a system. In reality, the device is even more useful than would appear from what has been described. Thus, only a two-axis machine has been shown and there have not been described in detail the components whereby the part-supporting table is rotated at controlled speeds. In fact a modern machine tool control may operate in three, four, or even five axes and the adder unit, which for sake of illustration has been shown to perform addition and subtraction only, may also be called upon to perform multiplication and division as well. All of these operations require many different time periods of operation.

Without the use of the readout system of the present invention, maintenance of a digital machine tool control would require excessive time since measurements of signals emanating from or destined for various components in the large console containing them would have to be measured at the different console locations. In sharp contrast, by use of the system disclosed herein, all of the information in the system is made to flow, seriatim, past a single set of signal outlets to which a centrally located display unit may be connected. Then, through the use of a compact cluster of switches located conveniently near the display unit, an operator or a service man can effectively reach any point in the system he desires.

Assume, for example, that, in the four bit flip-flop of the 10s decade of the XMO register 155, a clamping diode fails. In a typical machine tool control system, there are thousands of such diodes and failure of one of them is a statistically significant possibility. Failure of the diode would cause a constant X-axis error in the controlled tool's path.

This error would be a serviceman's only initial clue as to the nature of the breakdown in the system. He would not know whether the breakdown occurred in the contouring director 117, or the XP counter 123, the XP read gates 145, the adder 135, the XE error register 181 and its WRITE gates 179, or in the trunklines interconnecting them. All of these are in the chain through which X-axis information is processed. Furthermore. the service man would not know the decade or the binary bit place containing the defective component. Step by step he would have to check all of the registers, counters, gates, and the adder, and in each of them he would have to test at least several decades of components. Such a task would require many hours, resulting not only in expenditure of the service man's time but, perhaps more important, in an extended shutdown of the machine tool control while the trouble is being located. In many situations the resulting disruption of production would be intolerable.

With the present invention, given the same "sympton" the service man would simply set a known command and known corrections into the control system and would then systematically display the outputs of the suspected units one after another by means of the readout selector switches. Because of the complete display of the entire data produced by the unit under scrutiny, not only would the defective unit be rapidly isolated, but the particular decade and often the specific flip-flop or other component wherein the breakdown occurred can be quickly located.

Another particularly useful feature of the readout of the present invention is that it can be used to find defects in wiring which would otherwise be extremely difficult to locate. Thus, troubleshooting of electronic components can be accelerated to a certain extent, where they are of the removable-type, by systematically substituting for suspected units, units which are known to be good. This obviously cannot be done with the wiring of the system so that if there is, for example, a defective solder joint between a printed circuit card connector and one of the wires connecting it to its associated trunkline, such a defect would have to be traced by a continuity detector such as an ohm meter. With the present invention, such defects could be detected as quickly as those which exist in the electronic components of the system.

It is thus apparent that the present invention represents a powerful servicing tool which not only reduces the cost of locating the source of breakdown in machine-tool-control systems, but which, because of sharp reduction in the time required to locate such defects, will greatly increase the value of the machine-tool-control system to its user and the user's confidence in the system.