Title:
COMPUTER
United States Patent 3646523
Abstract:
A computer is disclosed wherein the machine language thereof is a particular formal system, i.e., the "calculus of lambda conversion." Such machine language is the language of the "well-formed" formulas of the aforementioned lambda calculus whereby the theoretical properties of the lambda calculus are implemented in the computer. Consequently, the computer is capable of computing all computable functions with time and space being the only limitations. The nerve center of the system is termed a tablet which in one implementation may essentially consist of an array of high-speed registers, each one large enough to hold a primitive term together with its designator. The nodes of a tree given by some formula corresponds to rows in the tablet and the branches extending from the nodes correspond to columns in the tablet. In one embodiment, the tablet has three columns for the branches and can have a fourth column which holds the tree addresses of the nodes. Associative techniques permit access to a row upon a match with the contents of the data or designator fields of one or more columns. The basic unit of information consists of the contents of a complete row of the tablet, such unit being termed a "message." The tablet, functioning as a central communication device, communicates with functional units, memory units, and input-output units, the latter issuing and accepting messages, or merging them with existing ones when the units obtain access to the tablet. The invention contemplates either the accessing by the units of the whole tablet, one after another in a fixed sequence, or the accessing by each unit of only a subset of the tablet, all units simultaneously accessing discrete subsets respectively. In order to render all messages available to all units, all of the messages are circulated, i.e., shifted through the whole tablet.


Inventors:
BERKLING KLAUS JUERGEN
Application Number:
04/860473
Publication Date:
02/29/1972
Filing Date:
09/24/1969
Assignee:
International Business Machines Corporation (Armonk, NY)
Primary Class:
International Classes:
G06F9/00; G06F9/44; G06F15/00; G11C15/04; (IPC1-7): G06F7/00
Field of Search:
340/172.5
View Patent Images:
Other References:

Schaffner, The Circulating Page Loose System, A New Solution for Data Processing, Research Report No. 15, Published by Smithsonian Astrophysical Observatory, Dec. 1966.
Primary Examiner:
Zache, Raulfe B.
Assistant Examiner:
Chapuran, Ronald F.
Claims:
I claim

1. A computer comprising:

2. A computer comprising:

3. A computer as defined in claim 2 wherein said data-processing means further includes:

4. A computer comprising:

5. A computer as defined in claim 4 wherein said data-processing means further includes:

6. A computer as defined in claim 5 wherein the input hereinto is a formula of a balanced parenthesis form, said formula comprising strings of symbols respectively forming logical groups which are tokens, each of said tokens comprising a descriptor for indicating the type of token, a token body and a delimiter for indicating the end of the token;

7. A computer as defined in claim 6 wherein said central communication means is an associative memory comprising an array of registers, each of said registers having a length of one word, the nodes of a tree given by a formula corresponding to rows in said central communication means, the branches emanating from the nodes corresponding to columns in the central communicating means, a tablet row for receiving a tablet entry comprising a first plus n following words to form an n-ary tree, said first word holding the node label of the tree node the entry is for, said n words holding tokens under said node.

8. A computer as defined in claim 7 wherein said input means comprises:

9. A computer as defined in claim 7 wherein said node assembler means comprises means responsive to a message therefor in said central communication means which includes a node label, a blank or back pointer, a node assembler operation code, a location in said linear memory and a token retrieved from a chosen location in said linear memory for placing messages in said central communication means in response to the combination of the code assembler operation code and the token in said message for said node assembler means, said messages placed by said node assembler means in said central communication being inserted into rows of said central communication means.

10. A computer as defined in claim 7 wherein said beta conversion means includes means for scanning said central communications means for variable nodes and means for looking up the value of a variable through back pointers.

11. A computer as defined in claim 7 wherein said "UP" means includes means to ascertain the tree position of said nodes in a program formula; and

12. A computer comprising:

13. A central communication means for a computer comprising;

14. A central communication means as defined in claim 13 and further including associative circuit means for enabling each of said conceptually vertical planar arrays of registers to function as respective associative memories.

Description:
BACKGROUND OF THE INVENTION

This invention relates to computer system organizations. More particularly, it relates to a novel computer arrangement wherein the language of a particular formal system is the machine language of the computer.

In conventional computer systems, a memory, generally of the core type, is utilized as a central communication device. In such use, input-output operations connect the memory with peripheral equipment, and one or more accumulators constitute the interface to the functional units of the system which execute instructions. Because of the dominating position of the memory, a conventional system exhibits in its operation, the nature of such memory, which can be characterized with respect to its access function as a one-dimensional array. A one-dimensional array is that data structure which can be mapped into a memory most easily while arrays with more dimensions, such as list and tree structures present increasing difficulties. The difficulties become even more numerous when it is attempted to map, i.e., compile an item of high-order language with its nesting of terms, scopes, functions, and subroutines into the linear one-dimensional instruction sequence which is, of necessity, dictated by the data structure of a core memory.

A conventional computer primarily is concerned with linear structures, a linear structure being a set of elements on which only one successor function is defined. The set of integers and the function "add one" is one example of a liner structure. The set of time intervals and the function "wait" is another one.

The only way to map a computational structure onto a conventional computer is by means of address arithmetic, the latter merely being compositions of the "add one" function and the levels of indirectness which are introduced if addresses of memory locations rather than data are loaded into memory locations.

Thus, for example, a program consists of a set of memory locations. The computer determines the location of the successor of some instruction either by incrementing the instruction counter or by taking the contents of some memory location as address, transfer instructions and interrupts. This process transforms the program structure which is disposed in the space formed by memory locations into the strictly linear structure of time. The program can now be considered as a sequence of time intervals, each labeled with an instruction, the computer executing this instruction in the corresponding time intervals.

Because of conditional transfers, there exists for written programs a class of sequences in the time domain generated by variations in the input data. It is this class of sequences with which the programmer has to be concerned. Whenever the programmer incorporates an instruction into a program, the following have to be kept in mind:

1. The state of the system just before the executing of the instruction, which is generally a product of all predecessors in a given time domain.

2. There is a class of time domain sequences to be considered.

3. The state of the system after the executing of the instruction, generally "all" of its successors (wherein "all" is, in this context, the period between power "on" and power "off").

Clearly, it is difficult for a computer user to always have a clear and complete picture of what effects result when an instruction or statement is incorporated into a program.

There are some advantages which flow from the display of a program structure in the time domain. Time flows rather freely and any inefficiencies in the program transform readily into longer run times. The space requirement for the display in the time domain is very modest, such requirement being readily satisfied by the instruction counter and the decoding register.

By contrast, the nature of time introduces many disadvantages. Access to a structure in the time domain can only occur in the relatively small interval between past and future. If something had had to be effected at a certain point in time, and the access interval had passed over that point, there is no way to go back to the latter point. An input channel not obtaining a memory cycle in time can only fail in its purpose. If some process requires a device immediately, other activities on that device have to be interrupted. If a system can handle several time domain sequences concurrently, the inserting of waiting periods is the only way to relate such sequences, i.e., to bring positions in different sequences to coincide at a certain point in time.

That the above set forth difficulties are present in connection with the operation of conventional computers is clearly brought out by the fact of the existence of programming languages with pushdown stacks existing at run time, which permit a partial display of a program structure in a linear space. The time domain along obviously cannot accommodate nontrivial program structures.

A computer whose machine language is in accordance with the lambda calculus displays program structures in a chosen space, i.e., a tree domain.

Accordingly, it is an important object of this invention to provide a computer whose machine language is the "calculus of lambda conversion."

It is another object to provide a computer in accordance with the preceding object which is capable of processing computational structures which are represented as tree structures.

SUMMARY OF THE INVENTION

Generally speaking and in accordance with the invention, there is provided a computer which comprises the following: An input device and input channel, which gathers the input entering thereinto in a character sequence and breaks it up into word-length strings; the input device processing these data, making small changes in these strings and assigning most of them to a location in a linear memory, the linear memory containing a copy of the program throughout it execution. An associative memory, termed a "tablet" is provided in which the program assumes the form of a tree, the tablet comprising an array of high-speed registers, the nodes of a tree given by some program corresponding to rows in the tablet, the branches extending from the nodes corresponding to columns in the tablet. Further included in the computer are components which are operative as functional units. These units look for messages, i.e., table entries for themselves, retrieve them, process them, and place new messages in tablet.

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a conceptual depiction of the appearance of a given program in the tablet of the computer according to the invention;

FIG. 2 shows a summary in tabular form of the operation of the node assembler of the inventive computer;

FIG. 3 depicts the essential nodes representing a beta redex;

FIG. 4 is a depiction of the general form of a "structure" in formal logic;

FIG. 5 is a diagram of a tree structure having two successor functions:

FIG. 6 is a diagram which illustrates the difference in the amount of coded information between a genuine tree-address system and a mapping of a tree structure into a linear structure by pointers;

FIG. 7 is a depiction of machine language and shows a string of symbols in accordance with a given syntax;

FIG. 8 is a tabulated depiction of the system architecture of the inventive computer;

FIGS. 9 and 10 are diagrams of a circuit which is described in forms of automata theory to transform a string of symbols according to the syntax in FIG. 7 into the arrangement of primitive terms in the tablet;

FIG. 11 is a table which shows in tabular form, the information given in FIG. 10;

FIG. 12 is a diagram which depicts the preparation of a formula for a node assembler working as a tree automation;

FIG. 13 indicates how a tree automation labels the nodes of an input tree with state symbols;

FIG. 14 shows the input tree of FIG. 12 after being processed by a tree automation according to the transition function M' in FIG. 13;

FIG. 15 is a diagram of a conceptual embodiment of an input channel according to the invention;

FIG. 16 is a block diagram of an illustrative embodiment of a computer constructed in accordance with the principles of the invention;

FIGS. 17A-17F, taken together as in FIG. 17, constitute a conceptual isometric view of the communication box, i.e., the tablet of the computer;

FIG. 18 is a diagram which illustrates the basic timing in the computer;

FIGS. 19A and 19B, provide a depiction of an associative memory plane in the tablet diagramed in FIG. 17;

FIG. 20 shows an embodiment of the associative memory read/write storage element;

FIG. 21 is a logical diagram of the associative memory vacancy bit storage element;

FIG. 22 is a fragmentary view of an associative memory element and depicts the transition which occurs in the tablet (FIG. 17) to the associative memory read/write storage element (FIG. 20);

FIGS. 23A-23F, taken together as in FIG. 23, comprise a diagram of an embodiment of the input unit;

FIGS. 24A and 24B, taken together as in FIG. 24, form a diagram of the associative memory plane for the input unit;

FIGS. 25A-25C, taken together as in FIG. 25, comprise a diagram of an embodiment of the storage unit;

FIGS. 26A-26E, taken together as in FIG. 26, constitute a diagram of an embodiment of the beta unit;

FIG. 27 shows an embodiment of a tree address register for the beta unit;

FIG. 28 is a diagram of the beta clock employed in carrying out the beta microprogram;

FIGS. 29A-29G, taken together as in FIG. 29, constitute a diagram of an embodiment of the UP unit;

FIG. 30 is an embodiment of a tree address register for the UP unit;

FIGS. 31A-31C, taken together as in FIG. 31, comprise a diagram of the UP clock;

FIGS. 32A-32H, taken together as in FIG. 32, form a diagram of an embodiment of a node assembler unit;

FIG. 33 is an embodiment of a tree address register for the node assembler unit;

FIGS. 34A and 34B, taken together as in FIG. 34, comprise a diagram of the BV (bound variable) clock;

FIGS. 35A-35G are diagrams of the clocks which control the (A microprogram;

FIGS. 36A-36E are diagrams of the clocks which control the (FA microprogram;

FIGS. 37A-37G are diagrams respectively of the clocks which control the VA microprograms;

FIGS. 38A-38G are diagrams of clocks which respectively control the CA microprograms;

FIGS. 39A-39F are diagrams of the clocks which control the δA microprograms;

FIG. 40 is a flow chart of the operations in the store unit;

FIG. 41 shows a list of node assembler output messages;

FIG. 42 is a flow chart of the ( microprogram;

FIG. 43 is a flow chart of the (F microprogram;

FIG. 44 is a flow chart for the VA microprogram;

FIG. 45 is a flow chart for the CA microprogram;

FIGS. 46A and 46B taken together as in FIG. 46, constitute a flow chart for the δ microprograms;

FIGS. 47A and 47B taken together as in FIG. 47, comprise a flow chart for the BV microprogram;

FIGS. 48A and 48B taken together as in FIG. 48, comprise a flow chart showing the operation of the beta unit;

FIGS. 49A-49D taken together as in FIG. 49, form a flow chart which shows the operation of the UP unit;

FIG. 50 is a flow chart showing the operation of the arithmetic or logical unit; and

FIGS. 51A and 51B taken together as in FIG. 51, constitute a flow chart showing the operation of the output unit.

DESCRIPTION OF A PREFERRED EMBODIMENT

In accordance with this invention, a computing system is provided whose theoretical foundation is furnished by those formal systems which have been constructed to formulate the concepts pertaining to computing. The system design according to the invention exhibits the major departure from conventional systems and concepts such as "instruction," "instruction stream," "processor," "multiprocessing," and "multiprogramming," have substantially no meaning therein although the system contains devices which, to some degree, resemble what the foregoing concepts convey.

The design of the system according to the invention is based upon the "Calculus of Lambda Conversion," a formalism which expresses a number of concepts which are connected with the operation of function application. The language of the "well-formed" formulas of the lambda calculus is the machine language of the proposed system. The theoretical properties of the lambda calculus are implemented in the system and, consequently the system is capable of computing all computable functions with time and space being the only limitation.

Prior to describing the invention, there is set forth immediately hereinbelow a brief description of the lambda calculus.

The lambda calculus is a formal system, the intended interpretation thereof residing in the concepts of function and the application of a function to its arguments. A formula of the calculus is any finite sequence of symbols from a finite, fixed alphabet and certain formulas are distinguished as well-formed formulas. A set of conversion rules is provided which permits the transformation of one formula into another.

There are actually several lambda calculi which are distinguished by their alphabets and/or the set of conversion rules they admit.

There is first described hereinbelow a so-called "pure" lambda calculus which is constructed from a very limited alphabet and two conversion rules.

In such calculus, the symbols that are permitted in a formula are:

λ, (,), variables

where the variables are character strings formed according to suitable conventions. Thus, if F, A, M, and N are considered to be intuitive (not belonging to the system) variables which denote formulas, then a well-formed formula is defined by the following conditions:

1. If a symbol x is a variable, it is a well-formed formula and the occurrence of x in this formula is free.

2. If F and A are well formed, (FA) is well formed. The properties of variables being free or bound in F or A are preserved in (FA).

3. If M is well formed and contains at least one free occurrence of x, then (➝xM) is well formed and x is bound in (λxM).

If the expression [N/x]M stands for the formula which results by substitution of N for x throughout M, this formula is well formed except in the case that x is bound in M and N is not a variable.

There is introduced the following two conversion rules on well-formed formulas:

α. M➝ [y/x ]M

a. x is not free in M;

b. y does not occur in M.

β. (λxM) N⇋[N/x]M

a. (λxM) N is well formed; the bound variables of M are distinct from

b. x; and

c. the free variables of N.

The alpha conversion set forth hereinabove formalizes, for example, the irrelevance of the symbol used to denote the summation index in a summation formula. The beta conversion is the formal correlate to the operation of applying the function (λxM) to an argument N.

In the following hereinbelow, the portion preceding the arrow of a conversion rule is termed a redex and the portion following the arrow is termed its contraction. A formula is considered to be in beta normal form if it does not contain any beta redex. A basic theorem (Church-Rosser) states that the normal form of a formula is unique up to applications of alpha conversion if it exists at all. The obtaining of the normal form of a formula by applying conversion rules reflects the intuitive concept of function evaluation.

As so far developed, arithmetic functions can be defined. Thus, if the integers are represented by the formulas

1 : λaλ b (ab)

2 : λaλ b (a(ab))

3 : λaλ b (a(a(ab)))

then integer exponentiation, nm, for example, is defined by the formula

λxλ y(yx)

in the sense that, where n, m stand for the formulas which represent the integers n and m respectively,

((λx((λy(yx))n) )m)

converts to the formula representing the integer nm. In this foregoing sense, every partial recursive function of positive integers is "lambda definable."

The calculus of lambda conversion thus constructed possesses the "completeness" property. However, in this form, it is too cumbersome to serve as a model for a practical computer design. The formalism out of which it is constructed, while facilitating arguments about the system, gives rise to lengthy and opaque computations in the system. Accordingly, if it is to provide the basis for the design of an efficient computing machine, the formalism has to be extended.

Such extensions are accomplished in several ways. In a first way, there are enlarged the set of primitive terms, i.e., those containing only variables in the pure calculus, to include primitive constants. These constants are to be considered as constant names for particular formulas. Additional conversion rules effect the evaluations of formulas constructed from such names. These additional conversion rules provide the formal equivalent of the applying of alpha and beta conversion to formulas in which the names have been replaced by what they stand for.

Thus, for example, there are introduced as primitives, notations for the integers as well as for the usual arithmetic functions on integers to integers, viz addition, subtraction, multiplication, and division. Also, with the introduction of these constants, the set of conversion rules are extended to include the following:

for all integers n, m,

(('+'n)'m) '(n+m)

(('-'n)'m) '(n-m)

(('*' n)'m) '(n*m)

(('/'n)'m) '(n/m )

where '+, '-, '*, '/, are the primitive constants which represent the arithmetic functions addition, subtraction, multiplication, and (integer) division, and 'n is the primitive constant which represents the integer n.

In the extension of the calculus of lambda conversion set forth above, the primitive constants take on a role that is similar to one taken in the pure calculus by the well-formed formulas in normal form with no free variables.

In a second variation, the system is enhanced to include definitions. The import of a "definition" is that a symbol, the "definiendum," is the abbreviation of or represents a more complex formula, the "definiens." As a first consequence, the set of primitive terms, now consisting of variables and constants, is enlarged to include definiendum symbols. These symbols are similar to constants but, while the meaning of a constant is implicit, a definiendum symbol requires an explicit explanation by a formula, i.e., the definiens. It is only required that the definiens be well formed, a well-formed formula still being considered as well formed if any well-formed portion of it is replaced by a definiendum symbol. In this sense, recursive definitions are permitted, i.e., a formula appearing as definiens may contain any definiendum symbol including its own.

At this point, the stating of a problem, which heretofore could only have been accomplished by a single formula, can now be effected by an additional list of definitions. The evaluation of the formula proceeds as before. However, only if a definiendum is to be an active or passive part of substitution procedure, which may be required while applying certain conversion rules, the definiendum symbol has to be replaced by a copy of its definiens from the list of definitions. Such type of sequencing is necessary since recursion is permitted, which signifies that a procedure which replaces all definiendum symbols first cannot be expected to terminate.

A set of functions, such that the definiendum symbol becomes the name of the function, may contain any subset of mutually recursive functions if it is so desired. This scheme of definitions facilitates the use of mutual recursiveness.

The language of the well-formed formula of the lambda calculus becomes the machine language of the system according to the invention in the following sense.

In the system, a bit string corresponds to every primitive term of a formula. The bit strings corresponds to the states of physical devices (memory cells). A physical device internally represents an empty space on paper in which to write a symbol. In the system, a particular memory cell is selected and gained access to indirectly. Depending upon the physical nature of the memory, the system interprets for this purpose a bit string (address, label, location) which is physically related to this memory cell.

Consequently, in the machine language, there are distinguished four classes of symbols, viz: (1) variable, (2) definiendum, (3) constant and (4) location. Since the knowledge of the class of a symbol includes to some degree the knowledge of the function of a symbol, one of the design features of the inventive system is the attaching to every word (bit string) in the system, a designator (another bit string) to designate the class of the symbol encoded in the word. The internal representation of a formula comprises a collection of such machine words of all four classes. To obtain such collection of machine words from a formula, there is provided an "assembly" procedure in hardware which translates language generated by the following skeleton grammar:

s ➝ (s)

s ➝ (ss)

s ➝ (sss)

s ➝ {primitive term}

The set of primitive terms is for this grammar the set of terminal symbols. It is also the set of all well-formed words with respect to a grammar which governs the construction of variable, constant, location, and definiendum symbols. This grammar is implemented in the assembling which parses the input character string in primitive terms and represents them in machine language by one machine word for each token. The arrangement of these words in the memory resembles the structure of the original formula. The machine evaluates the formula by the manipulating of the corresponding machine words rather than by the executing of a program.

As an example, a beta redex may be formed from the primitive terms λx,x,+ ,3 according to the skeleton grammar in the following manner:

((λx(x+x))3)

It has been mentioned hereinabove that known memories can be characterized with respect to their access function as one-dimensional arrays. In accordance with the invention, there is provided a memory device capable of accommodating nontrivial data structures. This memory device is hereinafter referred to as a "tablet." A set of memory units of conventional size, speed, and access operation back up the tablet.

Input enters into the system in the form of a character sequence. The character sequence is converted into a "token" sequence, the term "token" denoting an member in the set consisting of primitive terms and delimiters. This token sequence, because of its linear character, is found in the core memory.

In the following demonstrative formula, primitive terms are denoted by the letters of the alphabet. The formula is in the language defined by the skeleton grammar as follows:

((a(b,c,d) (e,f)) (g(h,m)))

A sequence of machine words in consecutive memory locations corresponds one by one to the sequence of symbols in the formula.

The balanced parentheses in the formula establishes a tree structure. There is, for example, a node branching to a, (b,c,d), and (e,f), and the semantics are that a is considered to be an operator applied to what (b,c,d), and (e,f) evaluate. Consequently, to accommodate tree structures, the table memory is accordingly constructed with its access functions. The table essentially consists of an array of high-speed registers, each one large enough to hold a primitive term together with its designator. The nodes of a tree given by some formula correspond to rows in the tablet, and the branches extending from the nodes correspond to columns in the table. According to the skeleton grammar, the table has three columns for the branches and can have one fourth column which holds the tree addresses of the nodes. Associative techniques permit access to a row upon a match with the contents of the data or designator fields of one or more columns.

The basic unit of information consists of the contents of a complete row of the tablet, such unit being conveniently termed a "message." The tablet, functioning as a central communication device, communicates with functional units, memory units, and input-output units. The latter units issue and accept messages, or merge them with existing ones, when the units obtain access to the tablet. Messages are keyed to the units such that a unit gains access only to pertinent messages. The system contemplates either the accessing by the units of the whole tablet, one after another, in a fixed sequence, or the accessing by each unit of only a subset of the tablet in the latter situation, all units simultaneously accessing discrete subsets respectively. In order to render all messages available to all units, all of the messages are circulated, i.e., shifted, through the whole tablet.

With regard to the functional units, a first of them operates in a manner which resembles that of a conventional instruction counter and accomplishes the transmission of a sequence of machine words from a memory, such as core memory, into the rows of the tablet. The other functional units corresponding to the implementations of the conversion rules of the underlying formal system and its extensions.

A tree addressing arrangement operates to manipulate the rows to the table analogous to the mapping of the relations among the contents of the cells in a linearly structured memory by address computations by integer arithmetic.

In considering the above, it is to be realized that a linear structure can be characterized as a set N of elements and one successor function s, which yields, if applied to an element of N, its successor. An example of N is the set of natural numbers which may form the addresses of cells in a linearly structured core memory, while integer address arithmetic is definable by the function s.

However, a tree structure is characterized as a set T of elements and two or more successor functions, r1, r2, ..., rk, thereby yielding several successors for each element of the set T. There exists an order among the elements of a set which is defined for every pair of elements a, b of the set such that

a follows b if repetitive applications of the successor function leads from b to a.

The foregoing definition yields a linear order for the set N and a partial order for the set T. This signifies that exactly one of the following statements concerning order relation is true for any two elements a, b ε T:

1. a follows b

2. b follows a

3. neither a follows b nor b follows a

4. a is the same element as b

For example, the nodes of a tree graph form a set T, while the number of branches extending from each node corresponds to the number of successor functions.

An arrangement is provided to construct labels (bit strings) for the rows in the tablet to reflect that they are associated with the nodes of a computational tree. Address computations are performed by functions in terms of the successor functions r1, ..., rk, rather than by integer arithmetic.

To obtain the correspondence to a tree structure, the node labels are constructed as follows: First, the branches originating from a node or from the root are numbered from left to right. Such direction is uniquely determined by the direction of writing with respect to the original formula. Next, there is obtained a label for a node by concatenating the numbers of those branches which form the path from the root of the tree to this node. However, this results in the root in the empty string . Therefore, every node label is prefixed by a decimal point. At this point, a string consisting of the decimal point alone represents the empty string. It is to be noted that these symbol strings are not to be confused with numbers. Since the tablet may most easily be envisaged as an associative, content-addressable memory, the tree labels are located in the fourth column thereof, as described hereinabove, whereby they are the main mechanism for accessing a row in the table.

Tree labels are manipulated, for example, to obtain the label of an immediate predecessor node or to determine partial order relations. Such manipulation corresponds to the address computations performed in a conventional computer such as, for example, the incrementing of the instruction counter to obtain the location of the next instruction. To this end, there are introduced a set of primitive functions which are either predicates or can be defined in terms of the basic successor functions. These functions are:

(root, x) : predicate

where x represents a tree label. The function returns the truth value "true" for x= and "false" otherwise.

(x=y) : predicate

where x and y stand for tree labels. The function returns the truth value "true," if the strings x and y consist of the same characters in the same sequence, and otherwise the "false" value.

(s, k, n) : successor function sk (p, n) : predecessor function (b, n) : branch function

where n is a tree label and k is an element of the set {1,2,3,...,i}. The function s appends the digit k to the tree label n, and the function b yields this last digit if applied to n. The functions b and p may be defined in terms of the successor function by the equation

(s, (b,n), (p,n))=n

As an example, there is composed from these primitives a function "pred," which yields, if applied to the label of some node, the label of the first predecessor for which some predicate pr about this node is true.

pred ::= (λx(cond

(if (root, x) then undefined)

else (pred2 (p,x)) ))

pred2 ::= (λy(cond

(if pry then y )

else (pred y) ))

The predicate pry denotes the contents of the other columns in the row of the tablet labeled by y.

In FIG. 1, there is shown the following example in the machine language:

((a(b,c,d) (e,f))(g(h,m)))

The pointers indicate the original tree structure which is now preserved in the tree labels in column 0. At the margin of the tablet (which is not a part thereof) there is indicated an example as to how the label of the corresponding node may be expressed in terms of predecessor and successor nodes using the functions s and p.

A node assembler effects the transmission of a formula from the (linear) core memory to the tablet. This unit resembles somewhat the known arrangements for bringing instruction word after instruction word into the decoding register. A close correspondence exists for primitive constants and variables, i.e., they cause the node assembler to issue a memory request for the next consecutive location. However, a formula consists of definiendum symbols and parentheses also. These symbols are replaced during a preprocessing scan by location symbols. As an approximate description, it may be stated that a definiendum symbol is translated into a pointer to its definiens and that a left-hand parenthesis is translated to a pointer to the symbol immediately following the matching right-hand parenthesis.

A pointer may cause the node assembler to issue more than one or no memory request at all. In this connection, let it be assumed, for example, that there is a left parenthesis at location i. Since matching parentheses enclose text which represents a subtree, the address i+1 may be interpreted as a branch to this subtree while the pointer to the symbol after the matching right-hand parenthesis points to the next element of the current node. The address i+1 may be called a branch mode address and the next element of the current mode may be called a normal mode address. The node assembler, instructed by the designator of the location symbol, issues memory requests for both addresses.

A formal description of these actions can be given in terms of messages. The contents of an input message for the node assembler consists of:

0➝n, the current node label

1➝k, the branch number

2➝m, a core memory address

3➝c(m), the contents of the cell addressed by m

in the four columns of a row in the tablet. The node assembler processes such a message according to what the designator of c(m) denotes.

If c(m) is a primitive constant, the node assembler first issues an output message:

0➝n

1 ➝ if k=1 ➝ c(m) else R

2 ➝ if k=2 ➝ c(m) else R

3 ➝ if k=3 ➝ c(m) else R

which brings c(m) in column k of the row labeled n (in column 0) and reproduces (R), the contents of the other columns in this row. Secondly, the node assembler issues a memory request, i.e., an input message for a memory unit. The latter input message has the form:

0➝n

1➝k+1

2➝m+1

3 ➝ block

This action closely resembles that of a conventional instruction counter and is the reason why the unit is called a node assembler, since a node consisting only of primitive constants is assembled in a row of the tablet.

If c(m) is a variable, the output message can have the same form as above. However, as is further explained hereinbelow, the variable is not brought into location determined by n and k. Instead, a message and new mode with the label (s,k,n) is created. The function s performs the successor function sk upon n.

0➝(s, k, n)

1➝c(m)

2 ➝ block

3 ➝ block

If c(m) is a location symbol, there has to be distinguished among several possibilities. An input message with a location symbol generally is chosen to contain two integers, m and c(m), from which new addresses such as m+c(m) can be constructed.

If c(m) is the internal representation of a right-hand parenthesis, the input message is destroyed. This signifies that no output message is generated, and the node assembler returns to its accepting state.

If c(m) is the internal representation of a left-hand parenthesis, c(m) gives the location following its matching right-hand parenthesis, either absolute or relative, as an increment. The branch mode output message corresponding to the subtree contains a new node label which is the successor node according to the branch number, an incremented core memory address, and the branch number reset to 1.

0➝(s, k, n)

1➝1

2➝m+1

3 ➝ block

The normal mode output message corresponding to the other branches originating from the current node contains the current node label, the pointer to the first location following the text which belongs to the subtree, and an incremented branch number.

0➝n

1➝k+1

2➝f(c(m), m)

3 ➝ block

If c(m) is the internal representation of a definiendum symbol, c(m) gives the location of the definiens. The output messages are in this case:

branch mode:

0➝(s, k, n)

1➝1

2➝c(m)

3 ➝ block

normal mode:

0➝n

1➝k+1

2➝m+1

3 ➝ block

This arrangement for definitions virtually incorporates the definiens in a formula for any occurrence of the definiendum symbol in this formula.

The table depicted in FIG. 2 summarizes the operation of the node assembler in tabular form. If it is assumed that any relocation of text in a linearly structured memory updates the pointers, then there can be had absolute pointers in the linear memory and a full adder is not required in the node assembler.

Thus, according to the designator field of the contents c(m) of column 3, the processing of a message can be composed from five basic operations:

1. inserting blocks,

2. inserting R's,

3. moving column to column,

4. linear successor function: plus one,

5. tree successor functions: (s, k, n),

and all fields of the output messages can be processed simultaneously.

From the foregoing, it is appreciated that the node assembler unit can be characterized as a generalized "instruction counter." The assembler transforms fully parenthesized linear text into tree structures by transmitting data from a linearly structured memory into a content-addressable memory. The assembler allocates register space for the tree nodes and generates the appropriate tree labels to enable access to the nodes.

Once a formula is in the tablet, "evaluation" of the tree structure may start. By the term "evaluation" there is meant the bringing of a formula into "normal" form. A formula is considered to be in normal form, if no conversion rule exists which could be applied. If the table is in the corresponding physical state, message exchanging no longer takes place.

The evaluation begins with the substitution of values for variables. This procedure is regulated by the beta conversion rule of the lambda calculus. The beta conversion in the invention is performed by a unit suitably termed the "beta" unit.

In the description of the beta unit, a formula of the type ((λxM)N), which calls for the beta reduction (conversion) is termed a beta redex. In FIG. 3, there are shown the essential nodes representing a simple beta redex. The term "block" in a field indicates that this field is not used. The prefix λ makes a variable a bound variable, which is internally indicated by the designator of the corresponding word. The particular arrangement of nodes has been chosen to make it compatible with the notion that (λv,M) is a function applied to an argument N, such that (f, N) where f is bound to (λv, M) somewhere else. In the formula M, i.e., among the successor nodes of node n'1, where n' denotes some node in a larger tree structure, there may be found nodes of a certain type which the node assembler generates when it encounters variables. Thus, there can be assumed the existence of the tablet row

0➝n, where n'1 precedes n

1➝v

2 ➝ block

3 ➝ block

Accordingly, there is thereby formed the input message for the beta unit, which replaces it by one or more output messages to accomplish the substitution of the argument N for the variable v. In order to obtain the information for the messages, the unit would retain a copy of the node label n for the output messages and try to find by repetitive application of the predecessor function p to n that predecessor node which contains the bound variable λv in column 1. As indicated in FIG. 3, this node appears in the form:

0➝ n' 1

1➝ λv

2 ➝ blank

3 ➝ block

To facilitate a first approximate description of the procedure, let it be assumed that the argument formula N has already been evaluated to a primitive constant. In the simple case now being considered, this primitive constant is found in column 2 of the row designated (p,n' 1)=n'. Employing the term C(x,k) to denote the contents of the column k in the tablet row designated x, the general form of the output message generated by the beta unit for the simple case being considered is as follows:

0➝(p,n)

1 ➝ if (b,n)=1, then C((p,n'),2), else R

2 ➝ if (b,n)=2, then C((p,n' 1),2), else R

3 ➝ if (b,n)=3, then C((p,n' 1),2), else R

The message inserts the value of the variable into the node determined by the input message, i.e., effects the substitution according to beta conversion.

However, in the general case, the value to be inserted may itself be a tree structure. In this situation, the substitution procedure involves the copying of nodes of a subtree while the node levels are changed appropriately. Accordingly, there has to be considered the case where no value can be obtained since the formula is of the type (...(λx,M)). Here, the formula (λx,M) is a "functional argument" which is going to be substituted for f in the formula of the form (f, A). Further complications arise if lists of bound variables and subscripted variables are provided for.

To comply with the rules of the Lambda Calculus, it is absolutely necessary to copy subtrees when they are substituted for variables. However, there arises the problem of so-called "clashing" variables, if a formula containing free variables is substituted into another formula where these free variables become bound erroneously. An effective way to cope with "clashing variables" is to avoid the substitution of any formulas containing free variables. This is accomplished as follows. If a variable, which is not marked, is encountered during the copying of a subtree, copying is discontinued until a value arrives for the encountered variable or it gets marked. In so doing, a particular sequencing is introduced but this procedure is justified by the existence of a basic theorem to the effect that the normal form of a formula, if it exists at all, no matter in what sequence the conversion rules are applied.

As has been explained hereinabove, certain standard well-formed formulas, such as, for example, arithmetic constants are represented by primitive constants. In general, there is provided for each primitive operator, a functional unit which performs the equivalent of evaluating the formulas named by the primitive constants. The input message for these units, which are suitably hereinafter termed f-units, has the general form

0➝ n

1 ➝ pr operator

2 ➝ operand

3 ➝ operand

where pr represents the designator for primitive constants. Usually, the operands will also be primitive constants but formulas as operands are permitted.

The f-unit is keyed to its pertinent input message by the pr-operator and designator of the operands. Such an input message is not complete until the operands have arrived.

The f-unit produces as a result either a formula or a primitive constant. In the latter case, the output message inserts the result into the immediate predecessor node, i.e.,

0➝(p,n)

1 ➝ if (b,n)=1, then result, else R

2 ➝ if (b,n)=2, then result, else R

3 ➝ if (b,n)=3, then result, else R

The predecessor node may now become an input message for another f-unit. It is thus seen that a maximum of simultaneous actions in the tree structure can occur while the necessary sequencing is maintained.

The arrangement described hereinabove can also operate within a binary tree structure corresponding to a tablet with three columns. In the system, arithmetic units become f-units. In general, any conventional instruction which produces a new bit string from one or more given bit strings can be implemented in this fashion.

To be able to write the assembling procedure as a formula in terms of system operators, a set of primitive operators have to be implemented. Such set may suitably be the five basic "lisp" functions, viz cons, car, cdr, eq, and atom which take strings of words in the linear memory as operands.

As has been mentioned hereinabove, beta conversion may require the substitution of a formula for a variable. With regard to the tree structures that involved, this is equivalent to the attaching of a subtree to a node determined by the variable. The general problem consists of moving the subtree ns (source), i.e., the set of nodes containing n s and all its successors to the node n t (target).

The algorithm to effect this action is stated in terms of the contents of the rows in the tablet. An approximate recursive formulation is as follows. Let is be assumed that in the tablet, there is a subtree labeled n s and a target node n t. There is then inserted into the tablet a copy of the row labeled n s wherein n s is replaced by n t. The procedure is then applied to the subtrees labeled (s, k, n s) and to the nodes (s, k, n t) for all k such that C(n s, k) = blank.

The procedure is now described in terms of input and output messages. The unit performing the copying of subtrees takes as an input message a row having the form, as follows:

0➝ n s

1 ➝ copy

2➝ n t

3 ➝ block

The information which is supplied causes the unit to destructively read from the tablet the node n s. The unit generates a copy of this row labeled n t, and writes back both rows, i.e., the original and the copy. Information has been retained about blank and nonblank columns in the row. The unit generates the following output message for every blank column k:

0➝(s, k, n s)

1 ➝ copy

2➝(s, k, n t)

3 ➝ block

Since the latter output messages are input message for the units, the following modification may be introduced, i.e., the output message with the largest k becomes internally an input message to the unit without interaction with the tablet. The remaining output messages are picked up later after the unit copied a tip node with no blanks in it. If, however, several units are available, several copy messages can be processed simultaneously to result in a gain in copying speed.

The rules of beta conversion require that certain variable nodes corresponding to "free variables" in the sense of the Lambda Calculus interrupt copying until a value has arrived. Thus, the copy unit merely returns such variable nodes to the tablet and goes into a waiting state. A similar action results if a copy unit tries to read a node which is currently not in the tablet.

Within a chosen design of the tablet, it is possible to simultaneously clear all the nodes of a subtree, i.e., the set of all nodes having labels with a common prefix. Otherwise, the copy unit can be converted by another small modification to a delete unit. Omitting the target label in the "copy" message in column 3 causes the unit to suppress the writing of both the original and the copy of the node and thereby deletes it.

The "pure" lambda calculus does not provide conditional devices. To accommodate existing programming languages in the inventive system, there can be implemented therein the elementary conditional form as disclosed in the publication titled "A Basis for a Mathematical Theory of Computation," by J. McCarthy, on pages 33-70 of "Computer Programming and Formal Systems," edited by P. Braffort and D. Hirschberg, North Holland, Amsterdam, 1962. The formal properties of conditional forms are given in this publication. The implementation would require f-units corresponding to conversion rules of the form:

(true M N) ➝ M

(false M N) ➝ N

where "true" and "false" are truth values--classified as primitive constants, and M, N are intuitive variables standing for well-formed formulas. An elementary conditional redex appears in the tablet as the root of three subtrees which develop simultaneously in the tablet. The first subtree should evaluate to a truth value. As soon as this value appears in the redex, the unnecessary subtree can be removed by associative access to the elements of the first subtree in the tablet.

It is possible to manipulate trees in connection with additional truth values such as "undefined" and "don't care."

A set of primitive functions, suitably termed "predicates," which return truth values, can be implemented to classify and relate the symbols in the system.

The inventive system permits many generalizations and extensions. Thus, considering the difference in the speeds of operation between the backup store and the tablet, more than one node assembler can be provided to utilize the tablet to its full extent and thereby permit the simultaneous processing of several programs. Depending on the structure of the programs, there can be controlled the computational speed by adding more arithmetic and functional units without changes in the structure of the system.

In reviewing the above, it can be stated that the tablet is the general communication device among the resources of the system. Input-output channels, backing store units, functional units, arithmetic units, and the program and node assembler comprise the resources of the system, while the tablet performs the interlocking, sequencing, and communication among the resources.

The system enables the use of faster and smaller compilers because the machine language itself is a relatively high-level language. This means that many facilities offered by programming languages are already implemented in hardware and do not have to be composed from primitive instructions.

In order to provide a high flexibility of associative access and to avoid masking, four-valued logic circuitry can be advantageously employed in the tablet. Thus, in addition to the binary "1" and "0" values, there could also be the additional logic values, viz "don't care" and "undefined," to obtain a match for either "1" or "0" and to avoid any match at all, respectively.

In considering the foregoing, and the advantages of a computer according to the invention, reference is made to FIGS. 4-14.

FIG. 4 shows the general form of a "structure" in formal logic. A linear structure corresponds to the natural numbers and integer arithmetic which is the theoretical base for the address system in conventional computers.

FIG. 5 illustrates the first nontrivial case of a generalized arithmetic, i.e., a tree structure with two successor functions. In this connection, if t= {0, 1} is the alphabet, the domain T=t*, i.e., the set of all binary words. These words may serve as addresses of the nodes in a binary tree as indicated in the FIG. 5. Shown therein is an intuitive correspondence of the tree structure to an arithmetic expression.

In FIG. 6, there is illustrated the difference in the amount of coded information between a genuine tree-address system and a mapping of a tree structure into a linear structure by pointers. A tree-address system permits the computation of addresses of all predecessor nodes from a given node. To provide the same information for a linear address system, pointers are required to all predecessor nodes available at a given node. An implementation with three forward and one backward pointer only yields access to immediate predecessors and, thus, requires additional time-consuming memory cycles.

In FIG. 7, there is conceptually shown the machine language of the inventive computer. The language is a string of symbols according to a given syntax. The primitive terms have the conventional interpretation. Thus, for example, λA indicates a bound variable. Bit strings (words) in the computer are classified by designators (another bit string) according to the list of primitive terms.

In FIG. 8, there is systematically shown the system architecture, i.e., the tablet and the functional units. The formula shown in FIG. 7 appears as indicated from the arrangement of parentheses in the original formula.

In FIGS. 9 and 10 there are shown a circuit set forth in forms of automata theory to transform a string of symbols according to the syntax in FIG. 7 into the arrangement of primitive terms in the tablet, when the (infinite) automaton reads a primitive term, it goes into a state of the form n.k. which is interpreted as an address in the tablet with n as node label and k as column.

In FIG. 11, the information given in FIG. 10 is repeated in tabular form.

In considering the depiction of FIG. 12, it is realized that in FIGS. 9, 10, and 11, the node assembler is described as an automaton working on an input tape. In FIG. 12, there is depicted the preparation of a formula for a node assembler working as a tree automaton. A tree automaton takes a tree as input. To obtain the input tree from a sequence of symbols, a processing scan inserts into every word corresponding a left parenthesis, a pointer to the word after the matching right parenthesis.

In FIG. 13, there is shown how a tree automaton labels the nodes of an input tree with state symbols. The transition function, M' maps a pair "state"-"input symbol" into a pair of states. Every such mapping corresponds to a split of control in terms of multiprocessing. Consequently, there results an increase in speed for this node assembler compared to the one shown in FIGS. 10, 11, and 12.

In FIG. 14, there is shown the input tree of FIG. 13 after being processed by a tree automaton according to the transition function M' in FIG. 13.

In considering the foregoing, it is realized that the computer described therein can be employed as it comes without requiring extreme modifications, attachments, and adjustments. The goals that such computer attains are:

1. Explicit, hardware-supported binding of variable (names or labels for data in presently known computers) to values.

2. Nonlinear program structure (handled directly by hardware).

3. Distributed decoding.

To understand these achievements, they have to be set in the perspective of known computer architecture. Thus given the basic mechanism to execute a linear sequence of orders one by one, the first argument arises as to which set of orders are to be implemented. For example, it is clear that arithmetic instructions form units which are almost unquestionably desirable. However, a most dangerous action in a computer is to rewrite the contents of a memory location. In this connection, almost every instruction, in this sense, changes the environment in which its successor instruction is executed. Consequently, the effect of an instruction becomes intricately dependent upon all of its predecessors. This makes machine language error prone and difficult to change because of loops and conditional transfers. High-level programming languages and assembly languages have as one of their purposes, the supporting of the programmer in explicitly controlling the environment in which some statement is evaluated or in controlling the values to which the names (tables, variables) in that statement refer.

It is important at this point to understand the difference between a functional programming language and a procedural programming language. A functional language has function definition and function composition as the basic tools with which to construct algorithms. A procedural language employs the proceeding from statement to statement as another tool to construct algorithms.

In the computer according to the invention, there is implemented in hardware, the binding mechanism as it is formalized in the Lambda Calculus.

Relative to achieving the direct handling by the computer of nonlinear program structure, it is to be borne in mind that presently known computers deal primarily with linear structures, a program with its strict sequencing of instructions constituting the most obvious example of this approach. Various attempts have been made to increase the speed of program execution by breaking into the strict sequencing, examples of such attempts being look ahead, multiple instruction counters, and multiple functional units. However, since the source of information remains a sequence of instructions, elaborate interlocking schemes are necessary to preserve the information inherent in the instruction sequence. Particularly, in the case of multiple instruction counter schemes, where instruction streams fork out into branches and reform again, it is difficult to determine which environment is valid for which branch and as to how the branch environments at a joining point of control are to be consolidated.

A linear structure may be abstractly characterized by the property that all of its component elements have only one successor. This abstract characterization, when generalized, lens itself to three structures, i.e., a binary tree structure is characterized by having two successors for each element, and an n-ary tree has, at most, n successors for each element.

The mapping of a computational structure into a tree structure presents many advantages. Thus, a tree can be easily partitioned into subtrees; there is a direction inherent in a tree since all of the elements except one have one precessor, but perhaps a number of successors; and, in a tree it is easy to substitute for leaves. Thus, to achieve the direct handling by the computer of nonlinear structures, a tree address system is suplemented which provides for the mapping of computational structures onto tree structures. The tree is developed by starting from the root and proceeding to the leaves. Results move from the leaves to the root thereby collapsing the tree. To facilitate loops and recursions, leaves are replaced by subtrees.

To effect distributed decoding, there is to be realized the great importance in presently known computers of the decoding register and the instruction counter. Usually, the only way to execute an instruction is to bring it into the decoding register. Consequently, if it becomes necessary in a conventional computer to carry out a step which is not determined by the current instruction stream, there have to be employed interrupt and trap features, i.e., in order to free the decoding facilitates for another program, the current instruction stream has to be halted, and the environment and/or the state of the computer has to be saved.

In accordance with the invention, the computer comprises several functional units which are usually in an "acceptance state," i.e., according to their particular nature, they accept messages one at a time, process them, issue messages for other units, and revert back to the acceptance state, where the units are not tied or connected to any program whatsoever. The message is self-contained and, to this end, carries an explicit code for its environment along with it. More than one program can share the same set of functional units. Control programs for administering the instruction decoding mechanism are not necessary.

As a particular design example, the basic structure of the computer, according to the invention, is chosen to be a five-byte word. The first byte of a word is used to describe the kind of data the word contains and is termed the descriptor byte. Thus, different data types are distinguished by their descriptors and not by the functions applied to them. The basic components of the computer are the following:

1. An input device and channel which gathers the input entering thereinto in a character sequence and breaks it up into word-length meaningful strings which are termed "tokens." The input device processes these data, making small changes in the tokens and assigns a location to most of them in the linear memory.

2. A linear memory which is a large conventional memory of which, each accessible part is a word long. A copy of the program is in the linear memory throughout its execution.

3. An associative memory which is the basic feature of the computer and which is termed the tablet. Only those portions of the program that are in the tablet can be executed. In the tablet, the program assumes the form of an n-ary (in this embodiment, a ternary) tree. Such form can be achieved because programs used in the computer are fully parenthesized expressions such as

(a (b c d) (e f) )

where a pair of parentheses must enclose two or three subexpressions. Such expressions inherently correspond to trees. For example, the above expression corresponds to the tree

The tablet consists of an array of high-speed registers, each one word long. The nodes of a tree given by some program correspond to rows in the tablet, and the branches extending from the nodes correspond to columns in the tablet. A tablet entry or row consists of four words (according to the illustrative embodiment). The first holds the node label of the tree node which is the entry for. The second, third, and fourth words contain the primitive tokens under the node, for those that are immediate subexpressions. For example, for node 12 above, there would be the tablet entry

Where N is the node label descriptor. If one of the points under the node is itself a branch point, no token input occurs in its place and a row must be provided for it. For example, in accordance with the tree example shown above, the row for node 1 has the form

and entries for nodes 12 and 13 must occur in the tablet. Associative techniques permit access to a row upon a match with the contents of the data or descriptor fields of one or more columns. A row is always the basic unit of information when the tablet is involved. A row need not represent a tree node i.e., the descriptor of the first word need not be N). For example, the input channel creates tablet entries that are then picked up by a storage device which places one of the words of the tablet entry in the location in linear memory indicated by one of the other words in the entry. Because of this, there is employed herein the term "message" to describe a tablet entry with the basic function of the tablet being that of the central communication device between all of the functional units.

4. The remaining components of the system are all suitably termed functional units. These units look for messages, i.e., tablet entries for themselves, retrieve them, process them, and place new messages in the tablet.

For example, an adder would retrieve a message having the form

add the 3 and 5, and place a message in the tablet indicative to another unit that it should place the answer, 8, in the kth column of the entry with node label n. The latter unit would retrieve the message, compute the label n of the predecessor of node nk, retrieve the node n entry, modify it, and then place it back in the tablet.

The language accepted as input by the inventive computer is now described. The input consists of strings of symbols broken up into logical groups and termed "tokens." Each token consists of three parts, viz (1) a descriptor which indicates the type of token, (2) the body of the token, and (3) a delimiter which indicates the end of the token. For example, in the token I2345b, I is a descriptor which indicates that the token is an integer, 12345 is the body of the token, and b a symbol which denotes a blank is the delimiter used to indicate the end of the token. The parentheses tokens (, (F, and ) serve as descriptors, bodies, and delimiters simultaneously, while other tokens require separate descriptors, bodies and delimiters. The blank is used as a delimiter for all tokens other than parentheses tokens.

There are now described the different types of descriptors, and, thus, the different types of tokens. The notations employed for a token is the type enclosed in brackets hereinbelow:

1. Integers, floating point numbers, octal numbers [i], [t], [o].

2. Truth values [tr]. The body of such tokens is T or F. The notation T(F) is used to denote the truth value token with body T(F) respectively.

3. Function Constants [P]. The function constants fall into three different categories: (1) functions from numbers to numbers, such as addition, multiplication, subtraction, sign change, quotient, remainder, raising to a power (which are denoted by +, ., -, QT, R, PR respectively); (2) functions from numbers to truth values such as "equals," "is less than," "is less than or equals," "is greater than," "is greater than or equals" (which are denoted by =, <, ≤, >, ≥, respectively); (3) functions from truth values such as "not," "and," "or," "implies," "is equivalent to," respectively denoted by the symbols , &, OR,

4. Output device names [OD]. Each output device has a different name, which forms the body of the token

5. Variable Names [v]

6. Binding Variables [λv]

7. Definition labels [Def f]

8. Defined Expression Names [δf]

9. Conditional Indicator [(F]. In addition to indicating a conditional statement, these token functions as a left parenthesis

10. Left Parenthesis [(]

11. Right Parenthesis [)]

The notation n is used to indicate any of the i,t, or o (i.e., number) tokens. Tokens of type 1 and 2 are termed basic constants and are denoted collectively by c. Tokens of the type 1-3 are termed constants and are denoted collectively by the term c. When v and λv are written in the same context, it is assumed that the tokens have the same bodies. The same is true of Def f and δf. There are used [ to denote (and (F collectively.

The "well-formed expressions"--wfe--of the language are defined as follows:

a. Any basic constant, variable, or defined expression is a wfe.

b. If e is a function constant or wfe and e2 and e3 are wfe's, then (e1 e2) and (e1 e2 e3) are wfe's.

c. If λv is a binding variable and e is a wfe, then (λv e) is a wfe.

d. If e, e1, and e2 are wfe's, then (F e e1 e2) is a wfe.

e. The only wfe's are those given by rules (a)-(d).

There is now indicated how a wfe can be looked at as a ternary tree, i.e., a tree with at most three branchings at a node. Thus considering an expression of the form

where a, b, c, d, and e are nonparentheses tokens. Such an expression corresponds to a tree

The level of a node or point on the tree can be defined as the distance from the node to the top of the tree, the distance between any two points being a unit. Hereinabove, in the depiction of the tree of this example, the levels are numerical notations to the right thereof. It is to be noted that parentheses can be numbered in a manner such (a left parenthesis is assigned one plus the number of the last unmatched left parenthesis, a right parenthesis, the number of the last unmatched left parenthesis) that that a left parenthesis numbered n opens an expression of elements at level n, and a right parenthesis numbered n indicates the end of a group of expressions of level n, all under the same node on the tree.

A program element is a string of the form Def fi ei or of the form

OD e

where Def fi is a definition label (ei is the definition of wfe designated fi) and OD is the name of an output device.

A program is a string of program elements within parentheses, such as:

(Def f1 e1 Def f2 e2 ... Def fn en OD e)

where all of the fi are distinct, i.e., the bodies of the tokens Def fi are distinct. An OD element must occur last and the wfe e has to be given by either b, c, or d above. The tree of the program is the ternary tree corresponding to wfe e.

A program is to be thought of as the following: An expression of the form ( (λν e1) e2 ) is interpreted to mean "the result which is obtained when e1 a function of v, is applied to e2." This is obtained by substituting e2 (or the result obtained by completely evaluating it) for any occurrence of v in the expression e1. An expression of the form (F e e1 e2) is interpreted to mean "e1, if the result upon evaluating e is T, e2, if the result upon evaluating e is F, and e' otherwise, where e' is the result of evaluating e." When a name for a defined expression δfi is found within an expression, it is replaced by its "definition," which is labeled by Def fi. Thus a program evaluation involves trying to obtain the value of the expression e, using the definitions δf1,...,δfn. The result is passed to the output device specified when no more evaluation can be done.

For example

(& 3= 3 4> 7 )

(( λb ( + 3b) ) 7 )

are expressions (with values F and 10 respectively). (OD(F'T 3 0)) is a program which will cause 3 to be given as output on the device OD.

PRELIMINARY PROCESSING OF THE INPUT

The input program receives a preliminary processing in the input channel before it is placed in the linear memory. The end result of this operation is that, essentially, the input tokens appear in linear memory in consecutive memory words. However, the following changes appear

1. The definition label tokens Def Fi have disappeared. In the place of each one of there, there is an entry in the tablet of the form

It is to be noted in this case that the descriptor is changed to a defined expression name descriptor. The number m is the starting location of the definition ei of fi in the linear memory. The notation u is employed to represent a so-called "unused" word. The latter type of word has a particular descriptor. The notation u is also utilized to represent the body of a word that is not used.

2. A token other than a right parenthesis that is followed by a right parenthesis is marked with a "prime" to indicate that it ends a wfe (a group of expressions at the same level). A bit switch in the descriptor of the token's word in linear memory is used for this purpose.

3. Right parentheses are eliminated.

4. A left parenthesis or conditional indicator has stored with it the location in the linear memory of the token that followed its matching right parenthesis, if there is such a token and it is not a right parenthesis. Thus, no location is stored for the first left parenthesis in

((a b ) c ),

but the location of c is stored with the second left parenthesis. This operation accomplishes the following. The expressions (a b ) and c are both expressions at the same level; together, they form a wfe when they are enclosed in parentheses. The location stored with the left parenthesis starting the first wfe of the pair indicates where the second element of the pair starts. A bit switch is turned off in the left parenthesis descriptor when it has such an address associated with it. If there is no such address, the parenthesis or conditional indicator is "primed" and ( ' or (F' is written. The OD taken does not occur in linear memory. There is however, an entry in the tablet of the form

the first word is the "empty" node label descriptor. Here, the first word is the "empty" node label which is denoted by the symbol . The number m is the address of the beginning of the program expression in linear memory.

There is now set forth a brief description of the preliminary input processing. This processing consists of three operations, viz: (1) The input channel gathers input characters and forms them into tokens; (2) The input channel then processes each token, the result being an entry in the tablet; and (3) the storage unit retrieves tablet entries of the form

and stores the token found in the fourth word of the entry in location m of the linear memory.

The input device may be provided with a keyboard with special keys for the descriptor and delimiters. The remaining keys (essentially alphabetic and numeric) are employed to form bodies of tokens. There are also suitably provided special start, reset, and dump keys, the start keys being used to clear the machine before beginning the input of a program, the reset keys being employed to wipe out a partly formed token in which an error has been made, and the dump keys being utilized to force output during the execution phase.

In FIG. 15 there are shown the essential components of the input channel. The basic functions of these components are as follows:

An input token enters into register ΣR one character at a time when the delimiter is encountered, the keyboard is locked until the token is processed. The section ΣL of register ΣR contains the address in linear memory to which the token is to go. This address is incremented after the processing of any token that takes up a location in linear memory. Tokens other than (and (F, after being processed, go to the register S together with the address in the linear memory to which they are to go, the address being in section ΣL. In register S, the tokens receive a prime if the next token is a right parenthesis. The ST descriptor, which is the message to the storage unit to store the token in linear memory, is used in register S for Def f and OD tokens for which the NOP (no operation for storage unit) descriptor is used, thereby causing the tablet entries for these tokens to be ignored by the storage unit. The Def f entries remain in the tablet as a table of definition locations and the OD entry remains in the tablet as the top node of the program tree. The tablet communication register TR is the tablet entry register where a tablet entry is formed from S or L. The pushdown stack is employed to hold (and (F tokens until the location of the nonright parenthesis following their matching right parenthesis, if any, is known. Words go to and leave from the pushdown stack only through register Z.

Section LL of register S holds the information for the last (or (F' token for which the matching right parenthesis was found. When the token following that right parenthesis is encountered, if it is not a right parenthesis, its address (ΣL) is placed into section LR of register S and the "prime" bit is turned off in the descriptor, the second word of L. When the next right parenthesis is encountered, L is used to form a tablet entry of the form

where m is the location for the left parenthesis (in linear memory) and m' is the address of the (nonright parenthesis) token occurring after its matching right parenthesis. The m' is missing when there is no nonparenthesis token following the right parenthesis matching the left parenthesis. For example, this would be true for all of the left parentheses in

(a (b c ) ).

The switch q is used to indicate when the previous entry which was matched was a right parenthesis.

The following is a more detailed description of the operation of the input channel. The term Zn in this description refers to nth byte of Z, etc.

In this operation, when the start button is pushed, S, ΣR, LL, LR, and Z are made blank and the address 0 is put into ΣL. The keyboard is then freed and input is begun to be read into ΣR. When a delimiter is encountered, the keyboard is locked and the input channel begins to process the token in ΣR. This proceeds as follows:

A. Test if ΣR is [. If not, test B. Otherwise:

1. Push Z down one in stack

2. Put ΣL and the descriptor of ΣR ', i.e., Σ15 in Z.

3. if q= q1, put ΣL in LR, reset "prime" bit off in L6 and make q equal to q0.

4. Increment ΣL by one.

5. Free keyboard.

These four steps accomplish the following. Steps (1) and (2) place the new left parenthesis-type token with its linear memory location in the pushdown stack. If the immediate previous token of the input was a right parenthesis (q= q1), the address of the current token is put in LR, which holds the information about the left parenthesis that matched this right parenthesis. The right parenthesis switch is turned off (q➝ q0). With step (4), the linear memory location counter is incremented.

B. Test if ΣR is ). If not, proceed to test C., otherwise:

1. Put L0, L in tablet communication register TR at TR1 -TR2, TR11 -TR20, respectively. Transfer contents of register TR to tablet if register TR does not contain all blanks.

2. Test whether the rest of the pushdown stack is empty but that Z is not blank. If the test does in fact find these states (end condition), proceed to step (3) outlined hereinbelow. If the end condition does not exist, the following steps are gone through.

a. Place Z in LL

b. Place contents at top of pushdown stack into Z

c. Make q equal to q1

d. Place "prime" in S5 (descriptor byte of SR)

e. Free keyboard.

These five steps under (2) immediately hereinabove achieve the following. Step (1) had caused to be placed into the tablet, the information for the left parenthesis that matched the previous right parenthesis. Now by step (a), of (2), the information about the left parenthesis matching the right parenthesis is put into LL. Step (b) causes the current contents of the top of the pushdown stack to be placed into Z. Step (c) results in the turning on of the switch q to indicate that the token just encountered was a right parenthesis. Step (d) causes the last nonparenthesis character in register S to be marked with a "prime" to indicate that it was followed by a right parenthesis.

3. For the end condition:

a. Insert So and S in section TR1 -TR2 and TR11 -TR20 of register TR. Transfer the contents of register TR to the tablet provided that these contents are not all blanks.

b. Insert N 1 into So. Place LL in SR -SR of register S. Make SA' the first byte of SR.

c. Repeat step (a).

In the above, step (a) effects the putting out of the last program token. Step (b) forms the tablet entry which initiates program execution. In this situation, N is the node label descriptor, SA' is a message to the storage unit, which is further explained hereinbelow, and the LL section contains the location of the first program token which is required to be a left parenthesis.

C. Test whether ΣR is Def fi. If it is not, proceed to test D. If this test shows that ΣR is Def fi the following steps are gone through:

1. The placing of So and S in locations TR1 -TR2 and TR11 -TR20 respectively and the transferring of the contents of register TR to the tablet providing that these contents are not all blanks.

2. The placing of Σ in location S2 -S10 of register S. Then, the making of the first byte of register S an NOP; the making of the sixth byte of register S a defined expression name descriptor; and the making of So equal to 00 ("zero zero" which stands for two half-bytes or zeros).

3. Make 9= 90.

4. The freeing of the keyboard.

In these steps as explained above, step (1) puts out the last program token. The NOP and 00 in step (2) form the tablet entry for the definition of fi. It is to be noted that ΣL is not incremented whereby the definition ei going with fi will start in the linear memory location given in the table entry.

D. The testing as to whether ΣR is OD. If the test finds that it is not, the proceeding to E. If the test finds that it is OD, the following steps are performed:

1. The placing of S0 and S in locations TR1 -TR2 and TR11 -TR20 respectively of register TR. The transferring of the contents of register TR to the tablet provided that these contents are not all blanks.

2. The placing of N in S0 and the NOP code in the first byte of register S.

3. the repeating of step (1).

4. The freeing of the keyboard.

The immediately foregoing steps put out the information for the token in register S (step 1) and then, in the top node in the tree (steps 2,3) as has been previously described.

E. If the test in D above found that ΣR is not OD, the following steps are performed.

1. The placing of S0 and S in locations TR1 -TR2 and TR11 -TR20 of register TR. The contents of register TR are transferred to the tablet provided that these contents are not all blanks.

2. The putting of Σ to S, bb to S0.

3. if q= q1, the putting of ΣL in the last four bytes of LR and the making of q= q0.

4. The incrementing of ΣL by one.

5. The freeing of the keyboard.

The immediately foregoing steps effect the handling of the remaining tokens, viz, constants, variables, and binding variables. Their function and operation are the same as like operations already hereinabove explained.

EXECUTION

After all of the program has received its initial processing and has been placed in the linear memory the execution phase begins. During this time, all of the functional units keep checking the tablet for a message indicating something for them to do. The storage unit reaches for messages having the form

where SOC is an operation code for the storage unit, m is an address in linear memory, and N is a node label. The term BP represents a "back pointer," the significance of which is explained hereinbelow.

Upon the encountering of a message, the storage unit destructively reads it from the tablet, retrieves the contents of location n of the linear memory, and inserts a message into the tablet having the form

In this message N, BP, and m are provided from the original message, the term NOC represents an operation code for the node assembler unit and is obtained by changing the first four bits of the operation code SOC.

Further, hereinbelow, there are places where a node assembler operation code is denoted by x. In such case, the storage unit operation code that differs from it only in the first four bits is denoted by x'. The term SA' represents a storage unit operation code corresponding to a "stop allocation" node assembler operation code.

In the following descriptions, for convenience of explanation, it is assumed that the first descriptor byte in a message for the node assembler or storage unit is a node label descriptor.

The node assembler's main function is to build the program tree, i.e., assemble the nodes of the tree in the tablet.

In a simple case, the result of the operation of the node assembler is a message having the following form:

where P is a function constant, and C1 and C2 are two constants appropriate to the function. For example, the case might exist where P=+, C1 =3, C2 =127.5. A message of this form is a message for the specific functional unit associated with P. This unit would retrieve the message from the tablet evaluate P for C1, C2 and insert back into the tablet, a message having the form

where R="P(C 1 C2)" is the result of evaluating P for argument C1, C2.

The latter is a message for the UP unit. If n is not 1, then n is of the form nk, where n is an integer and k is a digit. In such case, the UP unit retrieves the tablet entry which has the form

with the first word the node number n. Here, the numbers 1, 2, and 3 mark the columns of the entry. The UP unit returns a message to the tablet that is the same as the node n message except that the kth column word is replaced by R="P(C1 C2)."

If n is 1, "P(C1 C2)" is the final result of the program and the UP unit places a message in the tablet for an output unit. This message has the following form

where the R is what was the fourth word in the message in the UP unit in the example "P(C1 C2)."

In the execution phase of operation of the computer according to the invention, in addition to the node assembler and UP unit, there is also employed the beta unit, the function of the latter unit being to effect the replacement of variables by their values. For example, in the execution of the program which evaluates the polynomial 5 y 2 +30 y at 25, viz:

(( λy(+(*5(* y y )) (* 30 y) ) )25 )

the beta unit effects the substitution of 25 for y in the above expression. Then, the functional units for + and *, together with the UP unit, complete the evaluation of the expression. The interaction of the node assembler, UP unit and beta unit are discussed in further detail immediately hereinbelow.

The Node Assembler

In considering the operation of the node assembler, it is recalled that the message that the input channel places in the tablet to indicate that it has processed all of the input data has the form

where N is the node label descriptor, SA is a storage unit descriptor, m is an address in the linear memory, and the u's indicate "unused" words.

The latter message is one that causes the storage unit to pick up the contents C(m) of location m in the linear memory, this being the location of the first token of the program which is required to be a left parenthesis. It also causes the storage unit to place a message in the tablet for the node assembler which has the form

The storage unit does this as long as there are messages for it.

In the general form of a message for the node assembler, the first word of the message is the node label to which the token C(m) corresponds. Node labels in general are strings formed from the digits 1, 2, and 3 and correspond to the place of a token or expression in the program tree. The program, which itself is an expression, has the node number 1.

A node of the program tree is an entry in the tablet having the form

In this message, n is the node 1 label, and X1, X2, X3 correspond to the nodes n1, n2, and n3, respectively. If all of the Xi are constants, they occur in the node n. Otherwise, if Xi is a complex expression whereby it must be enclosed in parentheses or a variable the ith column of n usually holds a "blank" descriptor and the address of the first token of Xi in linear memory to reexecute Xi in another part of the tree and to enable retry procedures. An entry with the node label ni is created for the components of Xi. The node assembler creates such new node at the point when the beginning of its first subcomponent is being handled. Thus if the program were to be ( + ( - 3.5) 7 ), the first program node would be the entry

The node 12 would be created when the node assembler receives the following message from the storage unit

The message is a node assembler operation code that indicates that a row must be allocated. This code is created after the handling of the left parenthesis by the node assembler which indicates the beginning of a subexpression.

There are suitably two main operation codes for the node assembler which are suitably denoted R and D. The code R signifies that no node (tablet entry) exists for this token just retrieved from linear memory, whereby the node assembler must now create a row. The code D signifies that a node already exists in the tablet with a column for the token picked up, and the data of the token may be placed in that column.

When either of codes R and D are encountered with a retrieved input symbol, the node assembler (a) starts the assembling of the next expression in the same group at the same level and (b) sends up a "blank" descriptor if the expression being read is complex or a variable.

When the node assembler retrieves a token having a node assembler code, i.e., the node assembler has picked up a message such as

where n is a node label, BP is blank or a "back pointer," m is the address in linear memory where the token C(m) was found, and NOC (node assembler operation code) is D or R.

If n is a string of digits ending in i, n could be denoted by xi and x could be employed to denote n with its last digit omitted.

1. The descriptor of C(m) is (.

a. If C(m) is not primed, thereby indicating that there is a token following the right parenthesis matching this left parenthesis so that C(m) has the address of this token, m' in its last four bytes, the node assembler creates the message

and places it in the tablet. This latter message causes the node assembler to handle the next expression at the same level as n. For example, the expression ( + ( - 3 7 ) 5 ), when the second (is read as the message in question, causes the 5 to be read, the D' indicating that a tablet entry already exists for the data.

b. In addition to the message generated by step (a), the node assembler places the following message in the tablet

This message causes the token following the left parenthesis to be read and indicates that a row must be allocated for its data.

c. In addition, if the node assembler code is R, the following message creating a row is placed in the tablet

The b m+ 1 word signifies that the first component of the expression with label n is a complex and, as yet unevaluated expression that starts at address m+ 1 in the linear memory. The u's indicate blanks, i.e., zeros. This step reflects the peculiarity in associative memories of providing some initial content in a word to render it accessible.

d. In addition, if the node assembler code is D, the following message is placed in the tablet

This is a message for the UP unit which is further explained hereinbelow. The effect of this message is that the UP unit puts the b m+ 1 word in the column of the x node to indicate that the expression for that place is complex and, as yet, unevaluated.

2. The descriptor of C(m) is (F

a. As described in (1a) immediately above.

b. As described in (1b) immediately above with the difference that the storage unit operation code in the third word of the message is IFC', the "if-code."

c. As described in (1c) immediately above.

d. As described in (1d) immediately above.

3. The descriptor of C(m) is a variable descriptor

a. If C(m) is not primed indicating that the variable was not followed by a right parenthesis and thus does not end a group of expressions at the same level, the following message is placed into the tablet

This is similar to the messages of (1a) and (2a) hereinabove with the difference that the appropriate next token in the group at level x if n is xi is found at address m+ 1

b. In addition to the message of (a), the node assembler places in the tablet the following message

In this message, v is the body of C(m), i.e., the variable itself, the symbol ? is a descriptor indicating that the value of the variable must be looked up, m is the location in linear memory in which the variable was found and BP is the back pointer passed through the node assembler message.

c. The same as described in (1c) above.

d. The same as described in (1d) above.

It is to be noted that a variable, v, although a one-token expression, is treated like a complex expression and not like a constant.

4. C(m) is a constant C

a. The same as described in (3a) above.

b. If the code is R, then the following message is put in the tablet

The i in xi has to be 1 for the code R to have been used. This entry creates the node labeled x with C(m) in its first column.

c. If the code is D, the following message is placed in the tablet

This causes the UP unit to replace the ith column of the tablet entry with the node label x by the constant C.

5. c(m) is a defined expression name δf

a. The same as described in case (3a).

b. If the code is R, a row is created in the tablet with the following message:

c. A match is made in the tablet to retrieve the tablet entry of the form.

Here m' is the location where the definition of f begins a copy of the message is returned to the tablet.

d. If the code is R, the following message is placed in the tablet

This causes the definition of f to be read without sending up a blank (since message (5b) already has one) if it is complex, and without attempting to assemble the next adjacent expression of the same level.

e. If the code is D, the following message is placed in the tablet

Again, this operation causes the definition of f to be assembled without any attempts to assemble the next adjacent expression of the same level. However, blanks are set up.

6. C(m) is a binding variable λν

If the binding variable is in an operator position, which would be in an expression having the form ((λv e )e'), indicated by the fact that n ends in two 1's, the node assembler produces a node of the following form

where the second column is reserved for e', the value of v, and the third column contains the back pointer BP. It then starts reading e with the node label n 3 using a new back pointer n.

If the binding variable is not in the operator position, it creates a node having the following form

and starts to read the e in ( λv e ) for n 2 but with a new back pointer n.

The purpose of this approach is to permit the computer to use the back pointers to trace back through the appropriate binding variable nodes to find out whether a variable has a value. The ε-nodes essentially reduce a reducible expression ((λv e ) e') as soon as it is ascertained that it is reducible. In this connection, the code n can be considered as

where n is merely an information node, nodes n and n 2 carrying the information, and the body of the program tree is continued in n 3.

In the test as to whether a binding variable is in operator position, it is to be realized that the λv in the expression ((( λw (λv e)) e 1 )e 2 ) is also in operator position after the reduction for the λw is effected. Thus, the 3's present as a result of the operation of ε-nodes that may separate the two 1's indicating that the binding variable is in operating position also have to looked back through.

The information node for the variable is always one for which the second column corresponds to the value of the variable. Thus, the tree for the above expression goes through the transformations shown in the sketch hereinbelow. In this sketch, the portions below the broken lines are not in the tablet: ##SPC1##

Here, the back pointer stranded through to e will point to the εv node and the back pointer in that node will point to the εw node.

The flow diagram set forth immediately hereinbelow can be followed to understand the steps taken relative to binding variable. ##SPC2##

In the example shown in the flow chart, there are employed two functions p and b such that if n is xi, p (n)=x, and b (n)= i. In the chart, tests are indicated by question marks and an arrow is used to denote the putting of information to a temporary storage register. Movement is always downward unless there is a forcing out of sequence by the result of a test. The same notation is used for a register and its contents. For example, R➝p (n) signifies that the number p (n) is placed in register R. The term b (R)=2 is a test as to whether the result of applying the function b to the contents of register R is 2. "The node R" is the tablet entry with node label, i.e., the contents of R in the first word. A double slash at the end of a line indicates the completion of node assembler action.

There have been considered hereinabove the possible actions the node assembler can take when it retrieves a message for itself with an R or D operator code. In this connection it is recalled that if it found that an (F token had been retrieved from the linear memory, location m, it put out the following message

The code IFC is the "if-code." This and other codes are utilized in the handling of conditional statements.

In considering, in general, the effect of the operation of the node assembler, it is noted that a conditional expression has the form

(F e1 e2 e3)

where e is a predicate, e2 is to be the value of the expression if the predicate evaluates to T, and e3 is to be the value of the expression when the predicate evaluates to F. The computer starts to assemble and evaluate e1. At this time, if e1 is not a constant, it puts a message in the tablet with an SC (stop code) operation code and the location of e2. No operation is performed on e2 or e3 until e1 is evaluated. At such time, if the value is T, e2 is read with node number n and the particular code TC (true code) prevents the initiation of the reading of e3. If the value of e1 is F, e2 is read with a code FC (false code) indicating that e2 must be skipped. The node assembler performs this operation and then reads e3 with a TC code.

In explaining this operation of the node assembler, let it be assumed that it has received a message with the IFC code as follows:

The various possibilities of action depends upon the natures of C(m). These natures are as set forth below.

1. C(m) is a left parenthesis. Such left parentheses must have no "prime," i.e., C(m) also contains location m' following its matching right parenthesis.

a. The following message is sent to the tablet

This is the message that holds the location of e2 until e1 is evaluated.

b. The following message is sent to the tablet

This message starts the reading of the complex expression e1 which started with the left parenthesis on which a match was made and indicating that a row must be created for its data.

2. C(m) is (F

a. The same as described in (1a) immediately hereinabove.

b. The same as described in (1b) immediately hereinabove with the difference that the operation code of the message is IFC'.

3. C(m) is a variable v.

a. The following message is sent to the tablet:

This message holds the location of e2 until the value of e1, the variable is determined.

b. The following message is placed in the tablet:

This message causes the value of the variable to be looked up.

4. C(m) is a constant c

a. The following message is placed in the tablet

b. The following message is placed in the tablet

The UP unit causes this message to be handled as if e1 were a complex expression that had evaluated to the constant C.

5. C(m) is a defined expression name δf.

a. The same as described in (3a) immediately hereinabove.

b. The following message is retrieved from the tablet

This retrieval enables the obtaining of the location m* of the definition of f. This message is then returned to the tablet. The following message is then placed in the tablet:

This message initiates the evaluation of the expression f. It is to be noted that C(m) cannot be a binding variable in this case.

There are now considered the results which ensue when the TC, FC, or SA codes are encountered in node assembler messages.

1. The node assembler code is TC.

All of the cases of C(m) are like those when the code is D with the difference that the new message with the code D (which starts reading the next element at the same level, which would be e3 in this case) is not created. When a defined expression is encountered, the node assembler obtains its location and then again starts reading those with a TC.

2. The node assembler code is FC

If C(m) is a left parenthesis or (F, and m* is the location after the matching right parenthesis, the following message is put in the tablet:

Otherwise the following message is put into the tablet

3. The node assembler code is SA.

The following message is put into the tablet:

This message is put into the tablet at three different times, viz, when the program is to be read as node 1; when a defined expression name is retrieved with an R-code, the node assembler creates the row for n and starts to assemble the definition with the SA code; and when a defined expression name is read with an IFC code. There are considered hereinbelow the cases for C(m)

a. C(m *) is a left parenthesis. The following message is put into the tablet:

b. C(m*) is (F.

The following message is put into the tablet:

c. C(m*) is a variable v.

The following message is put into the tablet:

d. C(m*) is a constant c.

The following message is put into the tablet

e. C(m*) is a defined expression δg.

The following message is retrieved from and then returned to the tablet:

The following message is placed in the tablet

It is to be noted that in the case of codes TC, FC, and SA, if C(m) is a binding variable, there is an error.

In summarizing, the operation of the node assembler, (except in the case of binding variables), it takes various actions upon returning a message of the form:

where n is a node label; BP is a blank or a back pointer; NDC is one of the node assembler operation codes R, D, IFC, SC, TC, FC, or SA; m is a location in linear memory and tk (at times denoted by C(m)). is the token retrieved from the location m by the storage unit.

The node assembler's operation consists of placing into the tablet various messages depending upon the combination of NOC and tk. The various forms the messages may take are tabulated hereinbelow: ##SPC3##

Here, if n contains the number xi where x is a string of 1's, 2's, and 3's, and i is 1, 2, or 3, the p (n) is x, a (n) is x (i+1), and n1 is xi1.

In the above table, the parts of the message marked off into small areas by dotted lines are the descriptor parts of words. The terms b:m+ 1 signifies a word with the blank descriptor (used to indicate that this word is reserved for the result of the evaluation of a complex expression) and having the number m+ 1 as its body. The * in the table indicates that this message may be formed with various descriptors in the * position. The number m' is used when a δf is the input symbol tk. It is the address of the definition of f as found in a tablet table entry of the form:

The following tables indicate the messages generated by the mode assembler under various combinations of NOC and T (the handling of binding variables are omitted therefrom). In the tables, the rows are for messages possibly produced and the columns for the node assembler code with which the variable was retrieved. When a notation is present at the intersection of a node and a column, this signifies that when the particular input signal is retrieved with the node assembler code of the column, the message is placed in the tablet. When the message requires a descriptor for a * position, the descriptor appears in the row-column intersection; otherwise a cross appears thereat. It is to be noted that the generation of some messages depends upon the existence of a prime. This is also indicated at the intersection. In this latter connection, it is recalled that the prime on a left parenthesis (or condition symbol (F, denoted by the symbols C' and (F', signify that there is no expression of the same level following the initialing right parenthesis, and the prime on the other token indicates that the token was followed by a right parenthesis and thus completes the group of elements at its level. ##SPC4##

Once parts of the program tree are in the tablet as a result of the node assembler's operation, other functional units can start evaluating the program expression. For each function constant P, such as +, -, =, δ, AND, OR), there are functional units that scan the tablet for messages having the following form:

In this message, a and b have descriptors indicating that they are appropriate arguments for P since (b may be completely blank if P is a unary function. When a unit for P retrieves such type message, it evaluates the function at the given arguments and places in the tablet the following message:

where c is the result of the function evaluation. In this connection, the UP unit will pick up this message and move C "up" into the ith column of node x, if u is xi.

The evaluation process involves the interaction between the beta unit which is the variable evaluating unit and the UP unit. There follows now a description of the beta unit.

The Beta Unit

The beta unit scans the memory for variable nodes having the following form:

It is the function of the beta unit to look up the value of the variable V by going through back pointers. The operation is described in conjunction with the flow diagram hereinbelow. For this diagram, it is assumed that there are two four-word registers R and W. These four words are denoted by the notations R0, R1, R2, and R3 (N, B, M, and D respectively. When the operation of the beta unit is initiated, word register R composes the variable node message retrieved from the tablet.

In the flow chart, if X denotes a word, X// will denote the descriptor (first byte) of X// and //X will denote the body, i.e., the last four bytes of X. ##SPC5##

In considering the above set flow chart, after step (1) both the R- and W-registers contain the following information:

The register W holds this information throughout.

Step (2) tests whether the back pointer is blank. The notation is the "empty" or all blank node label. This can only occur for a variable that is not bound by a binding variable with the same body. This situation is taken as an error. If this is not the case, the beta unit begins to trace back through the nodes for the binding variables that could bind v. In this latter conversion, the first one found with the body v is the one that binds v.

In step (3), the "first" (the "next" etc., as these steps are repeated) ε or λ node whose binding variable may bind v is retrieved. The back pointer is the node label of that node.

In step (4), since reading of the tablet is destructive, this step effects the putting back of a copy of the node into the tablet.

In step (5), a check is made as to whether the binding variable and the variable are the same, i.e., have the same bodies. If not, the operation reverts to step (2) to continue the search up through the back pointers. If, however, the variable and binding variable are the same, the node is found for the binding variable binding the variable v.

In step (6), it is ascertained whether the node is a λ node. If this is so, the variable does not have a value and the beta unit places into the tablet the following message:

In this message, n* is the node number of the binding variable binding and v is a descriptor indicating that the word is for a variable without a current value. This completes the action of the beta unit in this situation.

If the node is not a λ node, it must be a ε node having the following form:

where R2 is the word reserved for the value of v and R3 is reserved for part of program tree and also holds the back pointer for n*. Step (9) checks whether the node is an ε node.

Step (10) checks as to whether word R2 has a blank descriptor. This is the situation when R2 is in the process of being assembled and/or evaluated. Then, R2 has the form b m*+ 1 where m* is the beginning of the value of y in the linear memory.

If the latter situation obtains, in step (11) the beta unit places the following messages in the tablet:

The first message puts the word b m*+ 1 in the column for the variable v whereby the word contains the location plus one of where its value is found in linear memory. The second message remains in the tablet indicating that node n requires the value of the variable whose ε node is n*. As will be shown further hereinbelow, the UP unit makes use of this message. The action of the beta unit ceases when the expression for the variable is unevaluated.

If the ε node is for a variable whose value expression has been assembled and evaluated but which contains a subexpression with a free (unbound) variable which does not yet have a value (this is not true if the value expression is just a variable that does not yet have a value), the descriptor of R2 will be one denoted by the term "expr" and the body of R2 will be the location plus one, m*+ 1 of where the value expression starts in linear memory. Step (14) checks for the latter case. If such case obtains 1 the beta unit places in the tablet the following messages:

The first of these messages puts in the column for the variable, the location plus one of where its value starts in linear memory. The second message starts the node assembler's reading the value expression immediately after the first left parenthesis which it must start with to evaluate an expression. The code R is employed to indicate that a row must be created with the node label n. It is to be noted that the back pointer which is used is the one found in the ε node.

When the variables value is known and is not an expression, it must be a constant. This constant, c, is in word R2. In this situation the beta unit instructs the UP unit to replace the column for the variable (in node x if n is xi). The latter action is effected by the following message:

The UP unit.

In the UP unit, there are again contained two form-word registers R(RD, R1, R2, R3) and W (N, B, M, D). It has been shown hereinabove that the other units have created of the messages of the following three types for the UP unit.

where the C in the first message is a constant. The second message is sending up the information to node X (if n is xi) that the expression corresponding to its ith column is a variable or complex expression that must be evaluated. In the third message, the v is a descriptor for a variable without a current value, n* being the location of the binding variable that caused the message generation. When operation of the UP unit begins, a message of one of the above forms is in register R.

In connection with the operation of the UP unit, there is first considered the following flow chart. ##SPC6##

In Chart A, it is seen that in step (1), the original UP unit message is stored in register W.

In step (2), the node label in register R(n or xi) is replaced by its "predecessor" node label (x). In this connection it is realized that information is being sent to the ith column of node x.

In step (3), the predecessor node is retrieved from the tablet.

In step (4), it is ascertained whether this node is the top node of the program, such node having the form

where is the all blank node label, i.e., the first byte of the word is the node label descriptor and the remaining form bytes of the word are blanks.

If register R does contain the top node, then in step (5) there is placed in the tablet the message

where D is the information being sent up. This is a message for the output unit, termed OD.

If the information is not for the top node, step (7) checks whether it is going to a "stop copy" (SC) node created by a conditional expression. The steps which are gone through when this is the case is explained hereinbelow in conjunction with Chart D.

If a "stop copy" node is involved, in step (8), it is ascertained as to whether the information is being sent up to an ε node. If it is not, the node is an ordinary part of the program tree, and the steps taken in such case are explained in conjunction with Chart C hereinbelow.

If in the above case, the node is an ε node, in step (9), it is ascertained as to whether the information is being sent up to the third column (otherwise it is being sent up to the second column). If it is being sent up to the third column, then the information pertains to the program tree, not the value of the variable that the ε node represents.

In the latter case, in step (11), the ε node is placed back into the tablet and a return is made to step (2) to send the information up to the next higher node in the program tree. In this conversion, it is mentioned that the ε-nodes are merely information holding "environment" nodes. It is noted that the tree, beginning with the node n, is not destroyed. If a constant were being sent up, this would be desired. If something else is being sent, for example, expr, b or variable information, it is desired not to destroy this information because it can be used by the output device when the program does not evaluate to a constant.

There is now considered the situation when information is being sent up into the second column of an ε node, i.e., the information being sent up pertains to the value of the variable that the node was created for. Let it be assumed that ε node matched on, i.e., now held in register R, is of the following form:

The actions which now occur are set forth in Chart B ##SPC7##

As shown in the above chart, in step (12), it is checked as to whether the information being sent up is that the value expression for the variable evaluates to a complex expression because there is within it a variable without a current value. If this is not the case, the information coming up must be a constant or "valueless variable" word, C or v n** respectively.

In this situation, in step (13), the ε node is placed back into the tablet with the value in the second column.

After the latter is effected, in steps (15-18), all of the messages placed in the tablet as a result of having the value of a variable bound by the binding variable of the ε node, which have been looked up before the value was determined, are picked up. In this connection, the following message

causes the value, just found, to be substituted for a variable, i.e., the value is sent to the column and node of a variable that had caused a search for it.

If the information coming up is that the value has been determined to be an "expression," in step (19), the ε node is placed back into the tablet with the information that its value is an expression.

In the steps (21-24 ) set forth in Chart B, there are picked up the messages left by variables whose values were looked up before the value was determined. For each such variable, the following message is created.

This message causes the node assembler to begin reading its value from linear memory, beginning such reading directly after the parenthesis with which it must begin.

After all of these variables are taken care of, in steps (25) and (26), the tree that was generated during the attempted evaluation of the variable is eliminated. The latter is, in general, the manner in which subtrees can be wiped out.

In summarizing the program evaluation concerned with variables, the node assembler starts creating the program tree, forming ε or environment nodes when it finds a binding variable in a position such that its value is known. The beta unit searches for values of variables through back pointers. When a "simple value" is known (variable or constant) the variable "requesting a value" is replaced by its value. When it is known that a value expression cannot be evaluated to a "simple value," the expression for the value is read from the linear memory in the place of the variable. In its new position, the expression may become evaluable to a simple expression. For example in the program

((λy (y 5))( λx x)).

the expression ( λx x ), which is the value of the variable y, does not evaluate to a simple expression. After this is known, the whole expression ( λx x ) is read from linear memory to replace the value y. At that point there is obtained

(( λx x )5)

which evaluates to the simple expression 5, the final value of the program.

An expression is not always read into a position such that it becomes evaluable. In this case, the "expr" information again results. This information is set up and may again go through a value (column) in an ε node. In such situation, the tree is again wiped out, the whole process repeating. However, the "expr" information could rise to the top of the program without going through a value column in an ε node, in which case the value of the program is considered to be an expression, and the output unit uses the whole program tree in the tablet to obtain what it wishes to output.

At this point in the description, there is considered Chart C, set forth immediately hereinbelow, wherein there are detailed the events which occur when information is being sent up into a node that is neither an ε node nor an SC (stop copy) node. ##SPC8##

It is to be noted that the steps on Chart C are reached from step (8) on Chart A. At this point the original UP unit message, as is set forth below, is in register W.

the information being sent up is in D. The node that is the predecessor of n-node x, if n is xi, is in register R, and information is being sent up for its ith column.

Referring now to Chart C, step (27) thereof ascertains whether it is "expression" information that is coming up.

If the latter is the case, steps (28) and (30) change the descriptor byte in the ith column to "expr" and place the predecessor node back into the tablet.

If it is not "expression" information that is coming up, as set forth in step (29), the whole column is replaced by the information coming up and the node is placed back into the tablet.

By steps (31-40), it is determined as to whether expression information should be sent further up. The latter is done if node x is now known to have evaluated to an expression. The conditions under which this is done are as follows:

1. No column is still waiting for its value, i.e., no column has a b descriptor (steps 32-34).

2. Some column has an "expr," or "valueless variable" descriptor (steps 35-40).

If the foregoing conditions are met, in step (41), "expr" is made the descriptor of D.

At the next step, i.e., step (42), a return is made to step (2), Chart A.

There remains now to be considered the action of the UP unit when information is being sent to an SC (stop copy) node. Such information must be the result of the evaluation of a predicate of a conditional expression. The events which constitute this action are detailed in Chart D as set forth hereinbelow: ##SPC9##

In considering Chart D, it is to be realized that if the predicate evaluates to an expression or valueless variable, "expr" information is sent further up (steps 43-47).

Otherwise, the predicate has evaluated to a constant. If the constant is T, steps (48), (49), and (52) place into the tablet, the following message

In the above message n is xi. The n 1, BP, m terms come from the SC message. Actually, n 1 has to be x and m is the location of e2 in the expression

(F e1 e2 e3 )

being evaluated.

If the constant is F, a message such as the one above is generated but the code is FC instead of TC (steps 50-53).

For any other constant, step (54) sends the constant further up. This causes the value of the whole conditional expression to be taken as this constant.

Output Unit

In the output unit, in accordance with the embodiment of the inventive computer being described, there are two four-word registers R(R0, R1, R2, RC and W(N, B. M, D) and a single printer. All messages retrieved from the tablet are held in register R.

The operation of the output unit is described in conjunction with the flow chart set forth hereinbelow. In this chart, the terms "retrieve" signifies both retrieval and placing a copy back. In an expression such as "retrieve code B" when, for example node B holds

there is signified the retrieving of node n*. Three functions are employed, viz; s(i, R0) which is the node label that is obtained by appending i to the node label in R0; if R0 holds the node label xi, b(R0) is i; and p(R0) is x. A one-byte counter is employed.

In the operation of the output unit, operation begins with the following message in register R:

d is the "program value" being sent up.

The flow chart for the output unit is the following: ##SPC10##

The first action of the output unit is shown at the upper right-hand side of the chart. If the program value is not an "expression," then it is a single constant. That constant is output, and the unit then stops operation. Otherwise, the unit starts reading out the program tree, starting with node 1. The ε nodes are skipped over, because they do not hold any information to be printed. During the operation, register W holds the node that is being output, register k holds the number minus one of the component of the node to be output. Whenever a component is an expression, the output unit has to go to the next lower level to obtain the node corresponding to a subexpression.

When a subexpression is completely printed out, the steps given at the bottom left-hand side of the chart ascertain whether the whole program has been output. If it has not, these steps cause the output unit to move back up a level, or a number of levels if ε nodes have to be skipped over. If the node label in N is xi, the node xi (xi1, xi2, xi3) has first been printed. If no ε nodes are involved, ks is made i (the number minus one of the next component of node x to be printed) and node x is retrieved so that the output for it way continue.

It is recalled that a valueless variable word in a node has the term v n*, where n* is the node label of the λ node containing the binding variable associated with the valueless variable. The body of this binding variable has to be looked up in order to print it out.

It is to be noted, since unary functions are permitted, R3 may sometimes be an "unused" word. In such case, the line in the chart "output R3" effects no action.

It may be desired to permit the output of the indecomposable but unevaluable nodes produced by error conditions, such node having the following form:

In such situation, each test for "expr" on the output chart could be replaced by one for "expr" or "b."

In the event that at the end of program, there remain conditional statements whose predicates still evaluate to expressions, the partially evaluated predicates and their two possible values are output by inserting test for SC nodes after the tests for ε nodes (bottom of output chart). In this situation, (F would have to be printed output instead of left parenthesis (.

Referring now to FIG. 16, the block diagram depicted therein shows the organization of the inventive system. The hub of the system is at the stage legended "communication box," referred to hereinafter as the "tablet." The tablet is, effectively, the nerve center of this system and all of the other units thereof communicate therewith. As will be further explained hereinbelow, the stage legended "input unit" is capable only of sending information to the tablet. The other units of the system as shown in FIG. 16, viz, the store units 1-N, the node assembler unit, the UP unit, the beta unit, the arithmetic-logic units 1-N, and the output unit are capable both of accepting information from the tablet and sending information back to the tablet.

Each unit communicates with the tablet through its associated memory plane, i.e., such plane is provided for each unit. The tablet, for purposes of illustration, is chosen to comprise four words in each memory plane, each word comprising 161 bits, the leftmost bit in a word being reserved for a "vacancy" bit as is further explained hereinbelow. At this point, it is sufficient to state that if the vacancy bit is set to "0," it signifies that the word is empty and if it is set to "1," it means that the word is valid. Each word comprises four fields of 40 bits each, i.e., five eight-bit bytes per word, these fields being legended as R0, R1, R2 and R3.

TABLET

A suitable embodiment of the tablet is shown in FIGS. 17A to 17F, taken together as in FIG. 17. As seen in these FIGS., there are provided four layers of flip-flops and gates. Thus, the rearmost row shown in the top layer is illustrated, for example, as comprising flip-flops 136, 137, and 138. As explained hereinabove, in the illustrative embodiment of this system, a 161-bit word is employed. Accordingly, each row of the tablet correspondingly comprises 161 flip-flops of which only the aforementioned three are depicted for purposes of convenience of illustration.

As will be explained further hereinbelow, the machine cycle is chosen to consist of two phases, suitable termed the "move" phase and the "communication" phase respectively. During the move phase, information in a row of flip-flops designated as "true" in the tablet is moved to the next row of flip-flops designated as true. Thus, in the move phase, information in the top layer of flip-flops in the row comprising flip-flops 132, 133 to 134 is moved to the row comprising flip-flops 124, 125 to 126, and the information in the leading row of the end row in the top layer, i.e., the row comprising flip-flops 114, 115 to 116 is moved into the row in the second layer comprising flip-flops 140, 141 to 142.

The move phase itself is executed in two stages. For this execution, two clock pulses, designated S1 and S2 as shown in FIG. 18, are provided. The S1 pulse is first applied to the gates of the tablet in order to gate information which is in the "true" rows of flip-flops to the rows of flip-flops designated as intermediate rows. The S2 pulse is then applied to the gates to gate the information from the "intermediate" rows to the next "true" rows. Thus, it can be appreciated that the tablet effectively constitutes a double-rank shift register with information conceptually moving from right to left (as viewed in the FIGS.) along the top layer, from left to right along the second layer, from right to left along the third layer and from left to right along the bottommost layer. From this latter layer, information is returned to the top layer.

As has been mentioned, each unit in the system has associated therewith, a vertical plane of the tablet. An example of such plane can be visualized as being defined by the vertical line 144 and the horizontal line 118. This plane comprises four layers, each layer comprising a row of 161 flip-flops. The vertical plane can conceptually be considered as an associative memory comprising four 161-bit words.

The tablet has been shown in FIG. 17 as comprising flip-flops and gates, i.e., the shift circuits which shift information therethrough. However, for simplification of exposition, a simplified version of the tablet is shown and, in actuality, each flip-flop in the tablet has additional circuits associated therewith. Thus, a typical flip-flop in the tablet such as flip-flop 141 of FIG. 17C is shown with its associated circuitry in FIG. 22.

To enable a clearer understanding of the associative plane, reference is made to FIGS. 18, 19A, 19B, 20, 21, and 22. FIG. 18 illustrates the timing relationship of the M, the S1 and the S2 clock pulses in the move phase, the clock pulses CA-1 to CA-3, and CB-1 to CB-3, in the communication phase, as is further described hereinbelow. FIGS. 19A and 19B, taken together as in FIG. 19, depict an illustrative embodiment of the associative plane which is employed for all units other that the input unit. As is shown in these FIGS., the clock pulses CA-1 to CA-3 and CB-1 to CB-3 are the pulses which control the operation. The flip-flops 146, 148, 150, and 152, FIG. 19A, are "match indicator" flip-flops and are first set to their "1" states by applying pulse to line 162, i.e., at CB-1 time, the latter pulse being the association pulse. If no match occurs in the associative memory plane when the association pulse is applied, all of the latter flip-flops are reset to their "0" states. However, for any word for which a match is found, the corresponding flip-flop 146 through 152 is left in its "1" state. Thus, when a pulse appears on line 166 at CA-3 time, the "topmost" match is found if such match exists and the desired "write" and "read" operation ensures. As is apparent from FIG. 19A, a "write" operation also conveniently referred to as a "dump to tablet" operation, is effected at CA time. To achieve a write operation, line 3606 (FIG. 19A) has to be active whereby the CA-1 pulse can be applied to line 162 to set the "match indicators" to their "1" state. The CA-2 pulse is applied to the association line (FIG. 13B) for the vacancy bit column to look for an empty space in the tablet. When such empty space is located, the CA-3 pulse (FIG. 19A) is operative to energize the topmost "write select" line and thereby cause a "write" operation. If such "write" operation is effected, then a pulse appears on the "write complete" line (FIG. 13A).

To achieve a "read" operation, line 3608, FIG. 19A, has to be active, a read operation always being effected at CB time. In this operation, the CB-1 pulse is operative to energize line 162 to set the "match indicators" to their "1" state. The CB-2 pulse is applied to selected association lines. When a match occurs, the CB-3 pulse is operative to energize the topmost "read select" line and thus cause a ♭read" operation. For the accomplishment of such read operation, a pulse appears on the "read complete" line.

FIGS. 20 and 22 show the typical flip-flop of the associative plane with its accompanying circuitry.

FIG. 21 is a circuit similar to that of FIGS. 20 and 22 and depicts the arrangement for the vacancy bit flip-flop. The latter circuitry is employed to associate on an empty space and to indicate that a word is valid. In this connection, it is to be noted that when a word is written, a vacancy bit is set to its "1" state by the pulse on the "write select" line. When a word is read out of the association plane, the vacancy flip-flop is set to its "0" state by the pulse on the "read select" line. The initial reset signal shown in FIG. 21 is employed to set all of the vacancy bits to their "0" states prior to the starting up of the system.

Effectively, therefore, the "associative plane" may be considered a four-word destructive memory. It is to be noted that only certain columns in the associative plane require the associative feature. For those columns which do not require the associative feature, those associative circuits such as shown in FIG. 20 which are unnecessary are omitted.

In FIGS. 24A and 24B, taken together as in FIG. 24, the associative memory plane for the input unit is depicted. In this plane, it is only necessary to write into the associative memory, the associative memory never being read out of. Accordingly, read select and read output lines are not employed therein and the AND circuits necessary therefor are also not employed.

TREE ADDRESS REGISTERS

In the node assembler, the beta unit and the UP unit, in the operation of the system, it is necessary to perform certain particular functions on tree addresses, these functions being performed by the "tree address" registers. A tree address denotes a node in a tree. In the illustrative embodiment of the inventive computer, there are employed ternary trees, i.e., each node has three successor nodes. A tree address register may be conveniently considered as a generalized instruction counter. Thus, while the conventional instruction counter computes the one and only successor in a linear address space, the tree address register performs the following special functions, viz:

a. compute predecessor

b. compute successor 1

c. compute successor 2

d. compute successor 3

Reference is now made to FIGS. 27, 30, and 34 wherein there are respectively shown suitable embodiments of tree address registers for the beta unit, the UP unit and the node assembler. As seen in these FIGS., each tree address register consists of 16 bit pairs and associated logic. Each bit pair can represent the decimal number 0, 1, 2, or 3.

Reference is first made to FIG. 33 wherein there is shown a tree address register of the node assembler. This register can hold up to 16 decimal digits, each digit ranging from 0 to 3. The usual state of this register is that it contains either 16 zeros or one or more successive decimal digits at the left followed by successively occurring zeros at the right.

As mentioned hereinabove, there can be three "successor" functions, viz, successor 1, successor 2 and successor 3. To perform the successor 1 function, the rightmost nonzero decimal digit in the tree address register is found and the decimal digit 1 inserted in the next place to the right. To perform the successor 2 function, the rightmost nonzero digit is found and the decimal digit 2 is inserted one place to the right. To perform the successor 3 function, the rightmost nonzero decimal digit is found and the digit 3 is inserted in the next position to the right.

In the tree address register shown in FIG. 33, the binary-coded decimal digit 1, 2, or 3 is gated to a cable 194, which contains four leads. Line 192 at this time is also activated. The information contained in the tree address register shown in FIG. 33 is always duplicated in another register, such as the register R0.

Let it be assumed that in the tree address register shown in FIG. 33, the two-bit register 3616 contains a nonzero digit and that the two-bit register 3618 contains a zero digit. In such situation, the exclusive OR-circuit 3620 is the only exclusive OR circuit in the row to have an output to enable a gate 3622 and thereby place the decimal digit which has been applied to cable 194 on a cable 3624. Cable 3624 passes through the "successor gate" to the two-bit position in register R0 which corresponds to the position of the two-bit register 3618 of the tree address register. Accordingly, with this arrangement, a decimal digit 1, 2, or 3 can be inserted to the right of the rightmost nonzero digit in the tree address register.

The "predecessor" function is operative to replace the rightmost nonzero digit in the tree address register by a zero. To perform this function, the decimal digit zero is gated to cable 194. As seen in FIG. 33, if the rightmost bit pair in the tree address register contains a number other than a decimal zero, an OR-circuit 3626 produces an output which enables a gate 3628 to thereby place the decimal digit zero which is on cable 194 onto a cable 3630, cable 3630 being the input to the rightmost bit pair of register R0. Thereby, a decimal zero is inserted into the rightmost bit pair of register R0. If the rightmost nonzero digit is contained in two-bit register 3618, an output is produced from an exclusive OR-circuit 3632 to enable a gate 3634 and thereby place the decimal zero on a cable 3636. Cable 3636 is an input to the bit pair in register R0 which corresponds to the bit pair 3618 in the tree address register. Thus, the rightmost nonzero digit is replaced by a decimal zero.

There are times when it is necessary to examine the rightmost nonzero decimal digit in the tree address register to see if is a 1, 2, or a 3. It is seen in FIG. 33 that such rightmost nonzero decimal digit appears on cable 264.

Tree Address Register for the β Unit

Reference is now made to FIG. 27 wherein there is depicted an arrangement suitable for use as the tree address register for the beta unit. In this register, the "successor" function is performed in the same manner as that previously described for the node assembler. In the beta unit, however, it is necessary to test whether or not the tree address register contains a string of decimal zeros. As seen in FIG. 27, it is obvious that if the tree address register contains at least one nonzero digit that an OR-circuit 3638 would produce an output on line 298. Thus, it can be stated that if line 298 is not active, then the tree address register for the beta unit contains a string of decimal zeros. By contrast, if line 298 is active, then the register contains at least one nonzero decimal digit.

Tree Address Register for the UP Unit

In FIG. 30, wherein there is shown the tree address register for the UP unit, it is to be noted that the "predecessor" function is performed in the same manner as that previously described in connection with the tree address register for the node assembler. The test for a string of decimal zeros is performed in the same manner as that described in connection with the tree address register for the node assembler. The test for a string of decimal zeros is performed in the same manner as that described in connection with the tree address register for the beta unit. The UP unit, in addition, has the requirement that it at times must use the nonzero digits in the tree address register as an argument when associating on its associative memory plane. To perform the latter association operation, line 1056 is rendered active in order to enable the AND-circuits 3640, 3642 and 3644. Consequently, any nonzero bit pair will enable its corresponding gate 3646, 3648 or 3650. All nonzero decimal digits will thus appear on a cable 1058. Cable 1058 extends to the columns in the associative memory plane which correspond to the right-hand four bytes of register R0. This particular association operation is explained in detail in connection with the circuit diagram for the UP unit.

OUTPUT MESSAGES

In FIG. 41, there are listed the various "output messages" which are employed in the operation of the node assembler unit, the beta unit and the UP unit. There are 14 of such messages and when a word is read from an associative memory plane in these units, it is put into a register R as indicated below.

Usually the first operation is to gate the contents of the R-register to the W-register as shown above. Then the contents of the R-register are altered as indicated in FIG. 41. Thereafter, the contents of the R-register are dumped to the tablet. As seen in FIG. 41, the "0" output message merely involves the dumping of the contents of the R-register in an unchanged form to the tablet. Such message is necessary because, if it is desired to leave the word in the associative memory, it is necessary to rewrite it in a subsequent operation since the associative memory is destructive.

The number "1" output message procedure is performed in the following manner. The first operation therein calls for the replacement of the contents of register R with the "predecessor" function of the contents of register N. If register N contains information different from that contained in register R, the four right-hand bytes of register N have to be gated both to register R and to the tree address register. If desired, the entire contents of register N can be gated to register R since the left-hand byte of register N is always the same as the left-hand byte of register R.

The "predecessor" function is obtained by finding the rightmost nonzero decimal digit in the tree address register and replacing the corresponding digit in register R0 with a decimal zero. The second operation is to replace the contents of register R1 with the contents of register B. If it is known that the contents of register R1 are the same as the contents of register B, of course, this need not be done. The left-hand byte or designator field of register R2 will be changed as dictated by the particular microprogram in operation. Such change is designated by the asterisk symbol in FIG. 41. The right-hand four bytes of register R2 are replaced by the right-hand four bytes of register D. In register R3, the left-hand byte or designator field is replaced by the symbol b (blank).

In the number "2" output message, the four right-hand bytes of register R0 are replaced by the predecessor function of the tree address register. Such replacement is effected because the tree address register contains the four right-hand bytes of register N. In register R1, the left-hand byte or designator byte is replaced by the symbol b. In addition in this register, the four right-hand bytes are replaced by the four right-hand bytes of register M incremented by one. In register R2, the left-hand or designator byte is replaced by the symbol u (unused) and in register R3, the left-hand or designator byte is also replaced by the symbol u.

In considering the next output message, i.e., number "3," the number contained in the right-hand four bytes of register R0 is replaced by the "predecessor" function of register N. The contents of register R1 are replaced by the contents of register D. In register R2, the left-hand byte is replaced by the symbol u. In register R3, the left-hand byte is replaced by the symbol u.

In the next output message, i.e., number "4," the contents of register R0 are replaced by the contents of register N. In register R1, the left-hand byte is replaced by the symbol "UP." In register R2, the left-hand byte is replaced by the symbol u. In register R3, the left-hand byte is replaced by the symbol b and the right-hand four bytes of this register are replaced by the four right-hand bytes of register M incremented by one.

In message number "5," the contents of register R0 are replaced by the contents of register N. In register R1, the left-hand byte is replaced by the symbol "UP." In register R2, the left-hand byte is replaced by the symbol u. Register R3 is left unchanged because its contents are the same as those of register D.

In effecting the next output message, i.e., number "6," the first operation in the procedure is to gate the four right-hand bytes of register N to register R0 and to the analyzer register. The rightmost nonzero digit in the analyzer register is found, incremented by one, modulo four, and gated to the corresponding position in register R0. The contents of register R1 are replaced by the contents of register B. In register R2, the left-hand byte is replaced by the symbol dictated by the particular microprogram which is then in operation and the four right-hand bytes of register R2 are replaced by the four right-hand bytes of register D. In register R3, the left-hand byte is replaced by the symbol b.

In the next output message, i.e., number "7," the first operation is to gate the four right-hand bytes of register N to register R0 and to the tree address register. The rightmost nonzero digit in the tree address register is found, incremented by one, modulo 4, and gated to the corresponding position in register R0. The contents of register R1 are replaced by the contents of register B. In register R2, the left-hand byte is replaced by the symbol dictated by the particular microprogram in operation. The right-hand four bytes of register R2 are replaced by the right-hand four bytes of register M, incremented by one. In register R3, the left-hand byte is replaced by the symbol b.

In output message number "8," the contents of register R0 are replaced by the contents of register N. The contents of register R1 are replaced by the contents of register B. In register R2, the left-hand byte is replaced by the symbol dictated by the particular microprogram then in operation. The right-hand four bytes of register R2 are replaced by the right-hand four bytes of register D. In register R3, the left-hand byte is replaced by the symbol b.

In effecting output message number "9," the contents of register R0 are replaced by the contents of register N. The contents of register R1 are replaced by the contents of register B. In register R2, the left-hand byte is replaced by the symbol dictated by the particular microprogram in operation and the right-hand four bytes are replaced by the right-hand four bytes of register M incremented by one. In register R3, the left-hand byte is replaced by the symbol b.

In output message number "10," the right-hand four bytes of register R0 are replaced by the "successor 1" function of register N. The contents of register R1 are replaced by the contents of register B. In register R2, the left-hand byte is replaced by the symbol indicated by the particular microprogram in operation. The right-hand four bytes of register R2 are replaced by the right-hand four bytes of register M incremented by one. In register R3, the left-hand byte is replaced by the symbol b.

In output message number "11," the right-hand four bytes of register R0 are replaced by the "successor 2" function of register N. The contents of register R1 are replaced by the contents of register N. In register R2, the left-hand byte is replaced by the symbol indicated by the particular microprogram in operation and the right-hand four bytes of register R2 are replaced by the right-hand four bytes of register M incremented by one. In register R3, the left-hand byte is replaced by the symbol b.

In the next output message, i.e., message number "12," the four right-hand bytes of register R0 are replaced by the "successor 3" function of register N. The contents of register R1 are replaced by the contents of register N. In register R2, the left-hand byte is replaced by the symbol indicated by the particular microprogram in operation and the right-hand four bytes of register R2 are replaced by the right-hand four bytes of register M incremented by one. In register R3, the left-hand byte is replaced by the symbol b.

In the last output message, i.e., number "13," the contents of register R0 are replaced by the contents of register N. In register R1, the left-hand byte is replaced by the symbol indicated by the particular microprogram in operation and the right-hand four bytes of register R1 are replaced by the right-hand four bytes of register D. The contents of register R2 are left unchanged. The entire contents of register R3 are replaced by the entire contents of register B.

INPUT UNIT

An embodiment suitable for use as the input unit in the inventive system is shown in FIGS. 23A to 23F, taken together as in FIG. 23. In connection with these FIGS., there is to be first noted the ΣR register shown in FIG. 23E. This register, in accordance with the embodiment selected to illustrate the invention, is chosen to have a capacity of five bytes. The first byte, i.e., byte number 1, is reserved for the "designator" character. Byte numbers 2, 3, 4, and 5 can contain either four characters or eight numerical digits. In operation, these bytes are initially set to all zeros.

The first operation is to enter from a keyboard (not shown) one to four characters, such entry starting with byte number 2. If digits are to be entered, all eight have to be entered in byte numbers 2-5, these digits including the leading zeros if they are present.

The second operation is to enter the designator character into byte number 1. In the operation of the system, some characters do not require the first operation. For example, a "(" goes directly to the designator byte of register ΣR.

At the same time that the designator character is loaded into byte number 1, a pulse appears on one of the lines 202A-202F. Thus, for example, if the designator is a "C," a "V," a "λ," or a "δ," a pulse appears on line 202A. If the designator is a "(" or an "(F," a pulse appears on line 202B. If the designator is a "(" a pulse appears on line 202C. If the designator is a "➝," a pulse appears on line 202D. If the designator is a "➝," a pulse appears on line 202E. If the designator is a ";", a pulse appears on line 202F.

The flip-flops 204A-204F and the flip-flops 210A-210F are initially in their "0" states. If a pulse appears on line 202A, it passes through an AND-circuit 206A to set flip-flop 204A to its "1" state, thereby disabling AND-circuit 206A. An AND-circuit 208A produces an output when the first M pulse appears to thereby set flip-flop 210A to its "1" state.

It is to be noted that the output of AND-circuit 208A is also operative through a diode 223 to cause a line 220 to become active. With flip-flop 210A in its "1" state, an AND-circuit 226A is enabled whereby the next S-1 pulse resets flip-flop 204A to its "0" state. It can be assumed that the latter action occurs after the pulse on line 202A has ended.

Line 220 extends to an AND-circuit 222 (FIG. 23F). If there exists material to be dumped into the S buffer, the flip-flop 318 will be in its "1" state which will permit an AND-circuit 222 to produce an output to set a flip-flop 224 to its "1" state. In the latter situation, a line 225 is active in order to enable a gate 227 whereby the contents of the S-buffer are gated to the R2 and R3 fields of the associative memory plane. A line 229 which is also active at this time is applied through an OR-circuit 231 (FIG. 23D) to a gate 233 to gate the zeros which are in a register 235 to the R0 and R1 fields of the associative memory plane. A branch circuit extends from the output of the OR-circuit 231 which is the "write" control line for the associative memory control. Accordingly, the input unit will thus associate on the associative memory plane and, when a vacant spot is found, will write the contents of the S-buffer into the vacant word in the associative memory plane. As seen in FIG. 23D, when the "write" operation is complete, a pulse appears on a line 237 which is applied to an AND-circuit 248 (FIG. 23F). The output of AND-circuit 248 is operative to reset flip-flops 318 and 224 to their "0" states. When flip-flop 318 is in its "0" state (FIG. 23F), a line 239 is active. Line 239 is applied to an AND-circuit 212 (FIG. 23A) whereby when line 239 is active, a line 241 is activated. When line 241 is active, it extends through a diode 243 to start a pulse generator 214 which delivers four pulses designated C1, C2, C3, and C4. A fifth pulse is delivered on a line 245 to reset flip-flop 210A to its "0" state.

In this operation, it is to be noted that the C1 and C2 pulses are not employed. With line 241 activated in response to the activation of line 239, an output appears from a diode 247 (FIG. 23B) which is applied to an AND-circuit 249. Consequently, the C3 pulse is effective through AND-circuit 249 to produce a pulse on a lead S33 which activates a gate 312 to thereby gate the "store OP" code to the left-hand byte of the S-buffer. The active state of line 241 also passes through a diode 251 (FIG. 23C) to an AND-circuit 253. At C3 time, AND-circuit 253 produces an output on line S36 if the "q" flip-flop is in its "1" state. The active state of line S36 enables a gate 310 (FIG. 23D) whereby the contents of the ΣL register are gated to a register LR.

The active state of line 241 also passes through a diode 255 whereby, at C4 time, the "q" flip-flop is reset to its "0" state. The active state of line 241 also causes the production of an output from a diode 257, such output being applied to an AND-circuit 259 whereby at C4 time, AND-circuit 259 produces an output on a lead S41. Such output is applied through line S41 to a gate 320 in order to gate zeros to the ΣR register. The active state of line 241 also passes through a diode 261 to an AND-circuit 263 which produces an output at C4 time on a lead S42 (FIG. 23F) which is employed to increment the ΣL register.

It is necessary that a second signal on line 202A (FIG. 23A) not be received until the events which ensue in response to the appearance of the first signal are completed. To effect the latter there may, for example, be provided an interlock (not shown) on the system keyboard which would prevent the depression of a second designator key until a pulse generator such as generator 214 had completed its production of its train of pulses. In such arrangement, the last pulse of the train could be employed to unlock the keyboard interlock. Since such interlocks are well known in the art, it is not considered to be part of the invention and further description thereof is deemed unnecessary.

Reference is now made to FIG. 23E wherein there is depicted the "push-pop" store together with its associated controls, such store being referred to as a "stack." The "push-pop" store consists of a plurality of registers successively numbered from top to bottom as 1 to N. The counter 112 and the decoder 328 are used to control the reading into and reading out of these registers. In operation, counter 112 is initially set to its "0" state. When counter 112 is in its "0" state, the output line 330 of decoder 328 is active. The "0" state of counter 112 signifies that there is nothing in the "push-pop" store and also indicates that the contents of the Z-register, if any are present therein, cannot be gated to the "push-pop" store.

Referring to FIG. 23A, a pulse is applied to line 202B when either the "(" designator or the "(F" designator is entered from the keyboard. In this situation, the flip-flop 210B is set to its "1" state. It is also to be noted in this situation that no signal is delivered to line 220, i.e., a dump of the contents of the S-buffer is not required. Pulse generator 214 will be directly started because of the effect of the circuit passing through diode 265. The output of a diode 267 is effective to enable an AND-circuit 269 whereby, when the C1 pulse occurs, a lead S11 is still active. Lead S11 is applied to an AND-circuit 332 (FIG. 23E). If the store is either not empty or not full, AND-circuit 332 produces an output which is applied to a gate 336 in order to gate the contents of the Z-register to the "push-pop" store, the register in the latter store into which the contents of the Z-register are entered being the one which is "pointed" to by decoder 328. The output of a diode 271 is effective to enable an AND-circuit 273 whereby, at C2 time, a line S22 is activated. Line S22 is applied to gates 340 and 341 (FIG. 23E). Gate 340 is operative to gate the contents of the ΣL register to the four left-hand bytes of the Z-register. Gate 341, when enabled, effects the gating of the designator byte of the ΣR register to the right-hand byte of the Z-register. The diode 275 is effective to enable an AND-circuit 277 which produces an output at C3 time on a lead S31, lead S31 being applied to gates 358 and 310. Gate 358, when enabled, is operative to gate the contents of the ΣL register to the S-buffer. Gate 310, when enabled, is effective to gate the contents of the Σregister to the S-buffer. The S31 pulse is also employed to set a flip-flop 318 (FIG. 23F) to its "1" state. The output of a diode 279 is effective to enable an AND-circuit 253 whereby, at C3 time, an output appears on a lead S36 provided that the "q" flip-flop is in its "1" state. The S36 pulse is applied to a gate 311 in order to gate the contents of the ΣL register to the L-buffer. The diode 281 is operative at C4 time to set the "q" flip-flop to its "0" state. A diode 283 is effective to enable an AND-circuit 259 whereby, at C4 time, a lead S41 is activated whereby a gate 320 is enabled to thereby gate zeros to register ΣR. A diode 285 operates to enable an AND-circuit 263 whereby, at C4 time, a pulse appears on a lead S42, lead S42 being employed to increment the ΣL register.

When the ")" designator is entered from the keyboard, a pulse appears on a lead 202C and a flip-flop 210C is set to its "1" state. It is noted that a diode 287 is provided to place a signal on a lead 219. The purpose of this latter arrangement is to cause the dumping of the contents if any which are present in the L-buffer. In this latter connection, a flip-flop 289 will be in its "1" state if there is anything present in the L-buffer at the particular time. The signal on wire 219 is applied as an input to an AND-circuit 291 (FIG. 23D) and, if flip-flop 289 is in its "1" state at the time of such application, an AND-circuit 291 produces an output to set a flip-flop 293 to its "1" state. A lead 295 is activated whereby the contents of the L-buffer are gated to the R2 and R3 fields of the associative memory plane.

With lead 295 in its active state, the signal thereon passes through an OR-circuit 231 to enable a gate 233 to gate zeros which are in a register 235 to the R0 and R1 fields of the associative memory plane. The output of OR-circuit 231 appears on the "write" line of the associative memory control. When an empty space is found in the associative memory plane, the contents of the L-buffer are written into this space and a "write complete" signal is produced on a lead 237. The latter pulse resets flip-flops 289 and 293 to their "0" states through a lead 297 and an AND-circuit 299. With the resetting of flip-flop 289 to its "0" state, a lead 301 is activated and is thereby operative to start pulse generator 214 through an AND-circuit 221 and a diode 303. The presence of diode 305 causes the enabling of an AND-circuit 307 whereby when the C1 pulse occurs, lead S12 is activated, S12 being employed to decrement counter 112 (FIG. 23E). The pulse on lead S12 is also applied to a gate 348 to gate the contents of register Z to the left portion of the L-buffer and sets flip-flop 289 to its "1" state. The S12 pulse is also applied to a gate 364 to effect the gating of the designator "store" to the left-hand byte of the L-buffer. A diode 309 is operative to enable an AND-circuit 313 whereby, when the C2 pulse occurs, a lead S21 is activated. The pulse on lead S21 is applied to a gate 352 (FIG. 23E) to gate the contents of the register in the "push-pop" store which is pointed to by decoder 228 to the Z-register.

A diode 315 effects the enabling of an AND-circuit 317 whereby when the C3 pulse occurs, a pulse appears on a lead S32, such pulse being used to set the right-hand bit of the designator byte which is in the S-buffer to its "0" state (FIG. 23F).

A diode 319 operates to enable an AND-circuit 321 if the "q" flip-flop is in its "0" state. In such situation, a pulse appears on a lead S35 at C3 time which is applied to a gate 346 (FIG. 23D) in order to gate zeros to the right-hand portion of the L-buffer.

A diode 323 is operative to enable an AND-circuit 325 if the "q" flip-flop is in its "1" state. In such situation, a pulse appears on a lead S37 at C3 time which is utilized to set the right-hand bit of the designator byte in the L-buffer to its "0" state (FIG. 23D).

A diode 327 is used to set the "q" flip-flop to its "1" state at C4 time. A diode 329 permits the production of an output on a lead S41, the operation of activated lead S41 having been explained previously hereinabove.

If the designator entered from the keyboard is a "➝," a pulse is applied to lead 202D to cause the setting to a its "1" state of a flip-flop 210D. A diode 331 causes the contents, if any, of the S-buffer to be dumped to the tablet. A diode 333 is employed to start pulse generator 214. A diode 335 is utilized to produce a pulse on lead S31. A diode 337 is operative to enable an AND-circuit 339 whereby, at C3 time, a pulse appears on a lead S34, the latter pulse being applied to a gate 360 to gate the no-op code to the left-hand byte of the S-buffer. A diode 343 causes the setting of the "q" flip-flop to its "0" state and a diode 345 permits the production of a pulse on a lead S41.

If the designator is a "➝," a lead 202E will receive a pulse whereby a flip-flop 210E is set to its "1" state. Thereafter with the diodes associated with flip-flop 210E, the operations are very similar to those previously described with other operations. Similarly, if the designator is a ";", a short pulse appears on a lead 202F whereby a flip-flop 210F is set to its "1" state. Here again, with the diodes associated with flip-flop 210F, timing pulses are produced as has been described above in other operations.

STORAGE UNIT

The storage unit is normally in its "acceptance" state. In such state, it continually associates on its associative memory plane in order to find a message that is directed to it. When it is successful in reading the word from the associative memory plane, it then tests the designator field of register R2 to ascertain whether the instruction is a "store" or a "fetch." If the instruction is a "store," it performs the store operation and then reverts to its "acceptance" state. If the instruction is a "fetch," it performs a "fetch" operation and follows the latter with a "dump to tablet" operation with the designator Ax replacing the "store" or "fetch" operator. The store unit then reverts to its acceptance state. The flow chart showing these operations is depicted in FIG. 40.

In considering the operation of the storage unit, at CB time it looks for an input message. Thus, as shown in FIG. 25B, the "acceptance state" flip-flop 374 initially would be set to its "1" state. The flip-flops 368, 370 and 372 would initially be set to their "0" states. The monostable multivibrators 376-392 (FIG. 25C) would be set to their "off" states.

With flip-flop 374 in its "1" state and flip-flop 370 in its "0" state, an AND-circuit 394 is enabled and the first M pulse which occurs is operative to set flip-flop 370 to its "1" state, whereby line 396 is activated. The activation of line 396 results in the activation of lines 398 and 400. Line 398 is the "read" input to the associative memory control unit and permits a "read" operation at the first time that an association is successful. With line 398 active, an AND-circuit 471 is enabled to permit the CB-2 pulse to associate on the vacancy bit.

As shown in FIG. 25A, it is to be noted that the storage unit associates on the common bits of the "store" and "fetch" operation codes and also on the lower order three bits of the address. At CB-2 time, outputs are produced from the AND-circuits 406 and 408 to enable gates 402 and 404 respectively. If a match occurs, the word in the associative memory plane is read into register R through a gate 410 and a cable 412. As shown in FIG. 25C, the left-hand byte of the R2 field is decoded by decoder 414 (FIG. 25B). When the "read complete" signal appears on line 416, it passes through a Delay unit 418 and is applied to a gate 420. If the operation is a "store," a pulse appears on a line 422 which turns on a monostable multivibrator 376. If the operation is a "fetch," a pulse appears on a line 424 which switches on a monostable multivibrator 382.

The "store" operation is first described immediately hereinbelow.

In the store operation, when monostable multivibrator 376 is turned on, the S-1 pulse appears on line 426 to initiate a "store" access of the linear memory and also set flip-flop 428 to its "1" state. In this connection, it is to be noted that flip-flops 428 and 430 are initially in their "0" states. When monostable multivibrator 376 turns off, monostable multivibrator 378 is turned on by the signal which passes through the OR-circuit 432. The S-2 pulse is applied to gate 434 in order to test for the state of flip-flop 428. If such test shows that flip-flop 428 is in its "1" state, a monostable multivibrator 380 will be turned on. Monostable multivibrator 380 is used for delay only and when it turns off, monostable multivibrator 378 is turned on through OR-circuit 432. This event causes the S-2 pulse to again be applied to gate 434 in order to test the condition of flip-flop 428. When the "store" access is complete, flip-flop 428 is reset to its "0" state. With flip-flop 428 in its "0" state and the S-2 pulse applied to gate 434, a pulse appears on line 436.

It is to be noted that when the "read complete" signal had appeared on line 416 that, at this time, flip-flop 374 would have been set to its "0" state. The output of Delay unit 418 will also reset flip-flop 370 to its "0" state.

Considering again the pulse on line 436, it is operative through OR-circuit 438 to set flip-flop 374 back to its "1" state. The storage unit now looks for the next message from the associative memory plane.

Relative to the "fetch" operation, as has been mentioned hereinabove that, if a pulse appears on line 424 (FIG. 25B) when gate 420 is tested by the "read complete" pulse on line 416 which extends through the Delay unit 418 to gate 420, a "fetch" operation follows.

When a monostable multivibrator 382 (FIG. 25C) is turned on, a pulse appears on a line 440 to enable a gate 442 whereby there is gated a "node assembler" operation code Ax to the left-hand byte of the R2 field. With line 440 rendered active, line 444 is correspondingly rendered active, the latter line being utilized to initiate a "fetch" access of the memory. Similarly, with line 440 active, a line 446 is also activated, line 446 being employed to set flip-flop 430 to its "1" state. When monostable multivibrator 382 is turned off, a pulse is provided through an OR-circuit 448 to turn on a monostable multivibrator 384. When monostable multivibrator 384 is turned on, the F-2 pulse appears on a line 450 to thereby enable a gate 452 to test the state of flip-flop 430. If such test shows that flip-flop 430 is in its "1" state, a pulse appears on a line 454 which is used to turn on a monostable multivibrator 386, the latter being employed for delay only and to return the clock to F-2 time through an OR-circuit 448. If flip-flop 430 is in its "0" state, a pulse appears on a line 456 which is used to turn on a monostable multivibrator 388. When flip-flop 430 is reset to its "0" state, such action signifies that the "fetch" access is complete.

Relative to the memory shown in FIG. 25C, the four right-hand bytes of R2 constitute the "memory address register" for the memory and the four right-hand bytes of R3 form form the "memory data register" for the memory.

Thus, when the "fetch" access is complete, a new word is written into the four right-hand bytes of register R3. It is next necessary to dump the contents of register R to the tablet, the latter operation being controlled by the remainder of the F-clock.

The description of the operation for returning the storage unit to its "acceptance" state now follows. Thus, when monostable multivibrator 388 is turned on, the resultant pulse on a line 458 is employed to switch a flip-flop 372 to its "1" state. With flip-flop 372 in its "1" state and flip-flop 368 in its "0" state, an AND-circuit 459 is enabled to produce the first M-pulse therefrom which sets flip-flop 368 to its "1" state, thereby disabling an AND-circuit 460. With flip-flop 368 in its "1" state, the lines 460, 462, 464, and 466 are rendered active. The AND-circuit 470 is utilized to associate on the vacancy bit of the associative memory plane and the first time that a vacant position is found, the word in register R will be gated through gate 468 to the empty location in the associative memory plane. When the "write" operation is completed, a pulse appears on line 472 to reset flip-flop 372 to its "0" state. This pulse is delayed by the Delay unit 474 and is thereafter employed to reset flip-flop 368 to its "0" state.

It is to be noted that when monostable multivibrator 388 (FIG. 24C) turns off, a monostable multivibrator 390 is turned on. Consequently, the pulse on a line 478 is applied to a gate 476 (FIG. 25B) in order to test for the state of flip-flop 372. If flip-flop 372 is in its "1" state, a pulse appears on a line 480 which is employed to turn on a monostable multivibrator 392, the latter being employed for delay only and to return the clock to F-5.

When the "dump to tablet" operation is completed, flip-flop 372 is in its "0" state and a pulse appears on line 482 which passes through OR-circuit 438 to set flip-flop 374 to its "1" state. With this arrangement, the storage unit is returned to its "acceptance" state.

NODE ASSEMBLER

There follows immediately hereinbelow a description of the BV flow chart (FIGS. 47A and 47B) taken together as in FIG. 47 which details the operations in the node assembler. FIG. 41 shows a list of node assembler output messages.

The first operation shown in this flow chart is the replacement of the contents of register W with the contents of register R. Such operation is effected by the BV- 1 pulse. It is to be noted that the BV-1 pulse also effects the gating of the four right-hand bytes of register R0 to the tree address register. Such operation is necessary since the next step is to replace the contents of register R0 with the "predecessor" function in register N. At this point, the contents of registers R0 and N are the same. It will be recalled that the "predecessor" function is performed by finding the rightmost nonzero digit in the tree address register and replacing the corresponding digit in register R0 with a decimal zero. Thus, the next step in the flow chart is to replace the contents of register N with the contents of register R0. This is effected by the BV- 3 pulse. It is seen that the BV- 3 pulse also effects the gating of the four right-hand bytes of register R0 to the tree address register. The latter operation is necessary since the next operation is to find the rightmost nonzero digit of the four right-hand bytes of register R0 and to determine whether this digit is a 1, a 2, or a 3, such operation having to be performed in the tree address register.

If it is assumed that the rightmost nonzero digit is a "3," the events as shown in the flow chart continue to the step where the contents of register R0 are replaced with the "predecessor" function of register R0. It is to be recalled that at this time the four right-hand bytes of register R0 are in the tree address register. The BV-5 pulse is operative to find this rightmost nonzero digit in the tree address register and to replace the corresponding digit in register R0 with a decimal zero. In order to perform the next operation which is to test the rightmost nonzero digit of the four right-hand bytes of register R0, the new value in register R0 has to be gated to the tree address register. The latter operation is effected by clock step BV-34. In the next clock step, i.e., step BV-35, this rightmost nonzero digit of the tree address register is tested and if it is not a decimal two, the clock branches back to clock pulse BV- 6. The BV- 6 pulse causes the node assembler unit to associate on the tablet with the contents of the R0 register and, when a match occurs, the contents of register R are replaced with the word read from the tablet.

Because the act of reading a word from the tablet destroys the word in the tablet, the next operation is to rewrite the word just read from the tablet through the operation of the BV-6 pulse back into the tablet. This latter operation is termed "dump message zero to the tablet" and is accomplished by the clock pulses BV-31, BV-32 and BV-33. It is seen that when this rereading operation is complete, the BV clock branches back to pulse BV-9.

The clock pulse BV-9 functions to test the left-hand byte of register R1 to ascertain whether it contains the symbol "ε." If it does not contain this symbol, the clock advances to BV-11 but if it does contain this symbol, it advances to BV-10. If it is assumed that the left-hand byte of register R1 did not contain this symbol ε, the output message number 13 (FIG. 41) is performed. This output message number is followed by a "dump to tablet" operation which is performed by the clock pulses BV-12, BV-13, and BV-14. The next step as shown in the BV flow chart is to perform output message number 11.

In connection with the latter (FIG. 41), it is noted that the contents of register R0 have to be replaced with a "successor 3" function in register N. To accomplish this, the four right-hand bytes of register N have to be gated to the four right-hand bytes of register R0 and also to the tree address register. It is recalled that the "successor 2" function is performed by finding the rightmost nonzero decimal digit in the tree address register and gating the decimal digit 2 to the position directly to the right of the corresponding position in register R0. When this output message number 11 is performed, it is followed by a "dump to tablet" operation which is in turn followed by a return to the "acceptance" state. The latter operations are effected by the action of clock pulses BV-17, BV-18, BV-19, and BV-20.

Referring back to clock pulse BV-4 where the rightmost nonzero digit of the four right-hand bytes of register R0 are tested, if this rightmost nonzero digit happens to be a "decimal 2," it is to be noted that there is a branch to BV-11 as has been described. It will be further noted in connection with clock pulse BV-35 that, if in this step in the cycling of the BV clock, the rightmost nonzero digit of the four right-hand bytes of register R0 happens to be a 2, there also is a branch to BV-11.

With reference to clock pulse BV-9, it is to be noted that if the left-hand byte of register R1 is the symbol ε, the BV clock advances to BV-10. At this juncture, it is seen that the four right-hand bytes of register R0 are in the tree address register. These latter bytes were in the tree address register when it was tested by the BV-35 pulse and, even though a "tablet match R0" operation followed this, the contents of the tree address register still contain the proper four right-hand bytes of register R0. The BV-10 pulse is operative to test the rightmost nonzero decimal digit of the four right-hand bytes of register R0 to ascertain whether it is a "1" or not. If it is not a "1," then the BV clock branches to BV-5 as has been described hereinabove. However, if this digit is a "1," then the BV clock advances to BV-21.

Because the four right-hand bytes of register R0 are still in the tree address register, the "predecessor" function of register R0 can be formed as has been explained. The BV clock next advances to BV-22 in order to replace the contents of register R with a "tablet match R0." For this operation, clock steps BV-22, BV-23, and BV-24 are required.

The BV clock next advances to BV-29, the latter step being employed to replace the contents of register N with the contents of register R0. The next operation is to perform output message number 13 as has been described hereinabove in connection with clock step BV-11. The output message number 13 operation is followed by a "dump to tablet" operation using clock steps BV-26, BV-27, and BV-28.

It is noted that, on clock step BV-29, the four right-hand bytes of register R0 had been gated to the tree address register. This latter operation was necessary in order to perform the next operation which is to perform output message number 12.

It is seen that output message number 12 (FIG. 41) involves forming the "successor 3" function of register N. At this time, the four right-hand bytes of register N are in the tree address register since at the same time that the contents of register R0 were gated to register N through the action of pulse BV-29, the four right-hand bytes of register R0 were also gated to the tree address register. Output message number 12 is followed by a "dump to tablet" operation and then a return to the "acceptance" state.

NODE ASSEMBLER

A diagram of the node assembler is shown in FIGS. 32A-32H taken together as in FIG. 32 and in FIG. 33 there is depicted a detail of the tree address register employed therewith.

In the first microprogram to be described in the operation of the node assembler, is the BV microprogram, BV being an abbreviation for "binding variable." The BV clock is depicted in FIGS. 34A and 34B taken together as in FIG. 34.

Normally, the node assembler unit is in the "acceptance" state with flip-flop 3,000 (FIG. 32D) set to its "1" state. The flip-flops 260, 200, 3,002, 3,004 and 3,006 are initially in their "0" state. With flip-flop 3,000 in its "1" state and flip-flop 3,002 in its "0" state, an AND-circuit 3,008 is enabled and the first M pulse is operative to set flip-flop 3,002 to its "1" state. With flip-flop 3,002 in its "1" state, a line 3,010 is rendered active, line 3,010 being applied as an input to an AND-circuit 3,012. At CB-2 time, AND-circuit 3,012 is enabled, the output thereof being applied to enable a gate 3,014 which effects the gating of Ax which is held in register 3,016 to the association circuits. Line 3,010 is applied as an input to an OR-circuit 3,018 and, when active, produces an output from OR-circuit 3,018 to enable a gate 3,020, the latter gate being employed to gate a matching word from the associative memory plane to register R. With line 3,010 active, a line 3,025 is correspondingly rendered active to produce an output from an OR-circuit 3,026, the output of the latter circuit enabling an AND-circuit 3,135 in order to permit the CB-2 pulse to associate on a vacancy bit. The latter action provides a "read" signal for the associative memory controls.

When a matching word is found in the associative memory plane, a "read complete" signal appears on line 3,028 and thereby on line 3,030 to reset flip-flop 3,000 to its "0" state (FIG. 32D). The pulse on line 3,030 is applied to an AND-circuit 3,024 (FIG. 32E) which is enabled at this time since flip-flop 3,002 is in its "1" state. An output is produced from AND-circuit 3,024 which is employed to turn on the monostable multivibrator D-1. The pulse on line 3,030 is applied through the Delay unit 3,032 to reset flip-flop 3,002 to its "0" state.

The D-1 pulse is applied to gate 3,034 to enable the latter to thereby test the designator field of register R3 through the decoder 3,036. If this designator field contains the symbol λ, a pulse appears on a line 3,038 and is employed to turn on the BV-1 monostable multivibrator. If the designator field of register R3 does not contain the symbol λ, a pulse appears on a line 3,040 which is employed to turn "on" the monostable multivibrator D-2. For purposes of explanation, let it be assumed that the designator field of register R3 does contain the symbol λ and thereby the operation of the BV clock is initiated.

The BV-1 pulse is applied to an OR-circuit 3,042 (FIG. 32E) to a gate 3,044 in order to gate the contents of register R to the contents of register W. The BV-1 pulse is also applied through an OR-circuit 3,046 to a gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register. The BV-2 pulse is applied to an OR-circuit 3,050 (FIG. 32H) to a gate 3,052 in order to gate "00" which is held in a register 3,054 to a cable 194. The BV-2 pulse is also applied through the OR-circuit 3,056 (FIG. 32F) to a gate 3,058 to gate the information cable 196 to the right-hand four bytes of register R0.

The BV-3 pulse is applied to an OR-circuit 3,046 (FIG. 32E) to a gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register. The BV-3 pulse is also applied through an OR-circuit 3,060 to a gate 3,062 to gate the contents of register R0 to register N.

The BV-4 pulse is employed to test the rightmost nonzero digit in the tree address register. This digit appears on a cable 264 (FIG. 32H) and is applied to a decoder 198. The BV-4 pulse is also applied to a gate 3,064 (FIG. 32H) in order to test the output of decoder 198. If the right-hand nonzero digit in the tree address register is a "1," a pulse appears on a line 3,066 which is employed to turn on the BV-21 monostable multivibrator. If the rightmost nonzero digit in the tree address register is a "2," a pulse appears on a line 3,068 which is employed to turn on the monostable multivibrator BV-11. If the rightmost nonzero digit in the tree address register is a "3," a pulse appears on a line 3,070 which is used to turn on the monostable multivibrator BV-5.

The BV-5 pulse is applied through an OR-circuit 3,050 (FIG. 32H) to a gate 3,052 in order to gate "00" which is in register 3,054 to cable 194. The BV-5 pulse is also applied through an OR-circuit 3,056 (FIG. 32F) to gate 3,058 in order to gate the information on cable 196 to the four right-hand bytes of register R0.

The BV-6 pulse is applied through an OR-circuit 3,072 (FIG. 32D) to set flip-flop 200 to its "1" state. This action of the BV-6 pulse initiates a "tablet match R0" operation. With flip-flop 200 in its "1" state and flip-flop 3,006 in its "0" state, an AND-circuit 3,074 is enabled and the first M pulse is operative to set flip-flop 3,006 to its "1" state. With flip-flop 3,006 in its "1" state, a line 3,076 is rendered active and is applied as an input to an AND-circuit 3,078 (FIG. 32A). With these events, AND-circuit 3,078 is enabled and, at CB-2 time, AND-circuit 3,078 produces an output which enables gate 3,080 to thereby gate the contents of register R0 to the association circuits for the associative memory plane. With line 3,076 active, a line 3,082 is active whereby an output is produced from an OR-circuit 3,018 to enable a gate 3,020 to thereby permit the gating of the word from the associative memory plane to the register R. With line 3,076 active, a line 3,084 (FIG. 32A) is also active to cause the production of an output from an OR-circuit 3,026 to the "read" input line to the associative memory controls. After a match is found in the associative memory plane, a "read complete" signal appears on line 3,028 which is employed to reset flip-flop 200 to its "0" state. The same pulse on line 3,028 is applied as an input through a Delay circuit 3,086 whereby the output from Delay circuit 3,086 resets flip-flop 3,006 to its "0" state.

The function of the BV-7 pulse is to test for the completion of the "tablet match R0" operation. Thus, the BV-7 pulse is applied to gate 3,088 (FIG. 32D) in order to test for the state of flip-flop 200. If this test finds that flip-flop 200 is in its "1" state, a pulse appears on a line 3,090 which is used to turn on a monostable multivibrator BV-8. Monostable multivibrator BV-8 is used for delay only and returns the clock to BV-7. If the test finds that flip-flop 200 is in its "0" state, a pulse appears on a line 3,092 which is used to turn on the single shot BV-31.

The BV-9 pulse is employed to test the designator byte of register R1. To this end, it is applied to a gate 3,094 (FIG. 32E). If the designator byte is equal to ε, a pulse appears on a line 3,096 which is used to turn on a monostable multivibrator BV-10. However, if the left-hand byte of register R1 is not equal to ε, a pulse then appears on a line 3,098 which is used to turn on single shot BV-11.

The BV-10 pulse is utilized to test the rightmost nonzero digit in the tree address register. To accomplish this, it is applied to a gate 3,104. If the rightmost nonzero digit in the tree address register is a "1," a pulse appears on a line 3,100 which is utilized to turn on a monostable multivibrator BV-21. If the rightmost nonzero digit in the tree address register is either a "2" or a "3," a pulse appears on a line 3,102 which is used to turn on monostable multivibrator BV-5.

The BV-11 pulse is applied to an OR-circuit 3,106 whereby the output of OR-circuit 3,106 enables the gate 3,108 to thereby gate the contents of register N to register R0 (FIG. 32B). The BV-11 pulse is also applied to a gate 3,110 to thereby effect the gating of λ which is in register 3,112 to the left-hand byte of register R1 (FIG. 32B). The BV-11 is also applied to an OR-circuit 3,114, the output of which is employed to enable a gate 3,116 to thereby gate the four right-hand bytes of register D to the four right-hand bytes of register R1 (FIG. 32F). The BV-11 pulse is applied to an OR-circuit 3,118, the output of which enables a gate 3,120 to thereby gate the contents of register B to register R3 (FIG. 32F).

The action of the BV-12 pulse is concerned with the "dump to tablet" operation. Thus, the BV-12 pulse is applied through the OR-circuit 3,122 to a line 258 to set flip-flop 260 to its "1" state thereby initiating a "dump to tablet" operation. With flip-flop 260 in its "1" state and flip-flop 3,004 in its "0" state, an AND-circuit 3,124 is enabled and the first M pulse is effective to set flip-flop 3,004 to its "1" state. With flip-flop 3,004 in its "1" state, line 3,126 is rendered active thereby enabling a gate 3,128 (FIG. 32A) to gate the contents of register R to the input lines of the associative memory plane. With line 3,126 rendered active, a line 3,130 is also rendered active to provide a "write" signal for the associative memory control (FIG. 32A). With line 3,130 rendered active, a line 3,132 is also rendered active, line 3,132 being applied as an input to an AND-circuit 3,134. At CA-2 time, AND-circuit 3,134 produces an output which permits the unit to associate on a vacant location in the associative memory plane.

When the word is written into the associative memory plane, a "write complete" signal appears on a line 3,136 to reset a flip-flop 260 to its "0" state (FIG. 32D). A pulse on line 3,136 is also applied to a Delay unit 3,138, the output of Delay unit 3,138 resetting flip-flop 3,004 to its "0" state.

The BV-13 pulse is operative to test for the completion of the "dump to tablet" operation. In this connection, the BV-13 pulse is applied to a gate 3,140 (FIG. 32D) to test for the state of flip-flop 260. If this test finds flip-flop 260 in its "1" state, a pulse appears on a line 3,142 which is employed to turn on the monostable multivibrator BV-14. Monostable multivibrator BV-14 is utilized for delay only and returns the BV clock to BV-13. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on a line 3,144 which is utilized to turn on a monostable multivibrator BV-15.

The BV-15 pulse is applied to a gate 3,146 to gate the four right-hand bytes of register N to the tree address register. It is also applied as an input to the OR-circuit 3,106, the output of OR-circuit 3,106 being applied as an enabling pulse to the gate 3,108 to gate the contents of register N to register RO (FIG. 32B).

The BV-16 pulse is applied to a gate 3,148 in order to gate "10" which is in register 3,166 to cable 194. The BV-16 pulse is applied as an input to an OR-circuit 3,150 whereby the output of OR-circuit 3,150 appears on a wire 192. The BV-16 pulse is applied as an input to the OR-circuit 3,152, the output of OR-circuit 3,152 enabling the "successor" gate 3,154 (FIG. 32E). The BV-16 pulse is applied to an OR-circuit 3,168, the consequent output of OR-circuit 3,168 enabling the gate 3,170 to thereby gate the contents or register N to register R1 (FIG. 32B). The BV-16 pulse is also applied to the OR-circuit 3,156, the output of OR-circuit 3,156 enabling a gate 3,173 to thereby gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The BV-16 pulse is applied to an OR-circuit 3,160, the output of OR-circuit 3,160 enabling a gate 3,162 to thereby gate the four right-hand bytes of register M through the incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The BV-16 pulse is also applied to an OR-circuit 3,172, the output of OR-circuit 3,172 enabling a gate 3,174 to thereby gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The BV-17 pulse is applied to an OR-circuit 3,122, the output of OR-circuit 3,122 rendering active a line 258 which sets flip-flop 260 to its "1" state (FIG. 32D). This action initiates a "dump to tablet" operation as has been previously described hereinabove.

The BV-18 pulse is employed to test for the completion of the "dump to tablet" operation. To this end, the BV-18 pulse is applied to a gate 3,178 to test for the state of flip-flop 260. If this test finds flip-flop 260 in its "1" state, a pulse appears on a line 3,180 which is used to turn on a monostable multivibrator BV-19. Monostable multivibrator BV-19 is used for delay only and returns the BV clock to BV-18. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on a line 3,182 which is used to turn on a monostable multivibrator BV-20.

The BV-20 pulse is applied to line 262 to thereby set a flip-flop 3,000 to its "1" state. This places the unit in the "acceptance" state as has been previously described hereinabove.

The BV-21 pulse is applied to an OR-circuit 3,050, the consequent output of OR-circuit 3,050 enabling a gate 3,052 to thereby gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The BV-21 pulse is also applied as an input to an OR-circuit 3,056, the consequent output of OR-circuit 3,056 enabling the "predecessor" gate 3,058 (FIG. 32F).

The BV-22 pulse is applied as an input to an OR-circuit 3,072, the consequent output of OR-circuit 3,072 setting flip-flop 200 to its "1" state. This action thereby initiates the "tablet match R0" operation which has heretofore been described.

The function of the BV-23 pulse is to test for the completion of the "tablet match R0" operation. This test involves the test for the state of flip-flop 200. Thus, the BV-23 pulse is employed to enable a gate 3,184. A pulse appears on a line 3,186 which is used to turn on a monostable multivibrator BV-24. Monostable multivibrator BV-24 is used for delay only and returns the BV clock to BV-23. If the test finds that flip-flop 200 is in its "0" state, a pulse appears on a line 3,188 and is used to turn on a monostable multivibrator BV-29.

The BV-25 pulse is applied as an input to an input to an OR-circuit 3,106, the consequent output of OR-circuit 3,106 enabling a gate 3,108 to thereby gate the contents or register N to register R0 (FIG. 32B). The BV-25 pulse is applied to a gate 3,190 in order to gate ε which is in register 3,192 to the left-hand byte or register R1. The BV-25 pulse is applied as an input to an OR-circuit 3,114, the output of OR-circuit 3,114 being applied to gate 3,116 to thereby gate the four right-hand bytes of register D to the four right-hand bytes of register R1 (FIG. 32F). The BV-25 pulse is also applied as an input to an OR-circuit 3,118, the output of OR-circuit 3,118 being applied to a gate 3,120 to gate the contents of register B to register R3 (FIG. 32F).

The BV-26 pulse is applied as an input to an OR-circuit 3,122, the output of OR-circuit 3,122 appearing on a line 258 to set flip-flop 260 to its "1" state. This action initiates a "dump to tablet" operation.

The BV-27 and BV-28 pulses are used to test for the state of flip-flop 260 (FIG. 32D). The operation of testing has already been described hereinabove.

The BV-29 pulse is applied as an input to an OR-circuit 3,060, the output of OR-circuit 3,060 being applied as an enabling pulse to a gate 3,062 to gate the contents of register R0 to register N (FIG. 32E). The BV-29 pulse is also applied to an OR-circuit 3,046, the output of OR-circuit 3,046 being applied as an enabling pulse to a gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register.

The BV-30 pulse is applied to an OR-circuit 3,150, the consequent output of OR-circuit 3,150 appearing on a line 192 (FIG. 32H). The BV-30 pulse is applied as an enabling pulse to gate 3,194 to gate "11" which is in register 3,196 to cable 194 (FIG. 32H). The BV-30 pulse is applied as an input to an OR-circuit 3,152 the consequent output of OR-circuit 3,152 being applied to the "successor" gate 3,154. The BV-30 pulse is applied as an input to an OR-circuit 3,198, the consequent output of OR-circuit 3,198 being applied as an enabling pulse to a gate 3,200 to gate "F3" which is in register 3,202 to the left-hand byte of register R2 (FIG. 32C).

The BV-30 pulse is applied as an input to an OR-circuit 3,160, the consequent output of OR-circuit 3,160 being applied as an enabling pulse to the gate 3,162 to gate the four right-hand bytes of register M through the incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32B). The BV-30 pulse is applied as an input to an OR-circuit 3,172 the consequent output of OR-circuit 3,172 being applied as an enabling pulse to gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The BV-31 pulse is applied as an input to OR-circuit 3,122 the consequent output of OR-circuit 3,122 which appears on line 258 being employed to set flip-flop 260 to its "1" state to thereby initiate a "dump to tablet" operation, as has been previously described (FIG. 32D).

Clock pulses BV-32 and BV-33 are employed to test for the flip-flop 260, as has been described hereinabove (FIG. 32D).

The BV-34 pulse is applied as an input to an OR-circuit 3,046, the output of OR-circuit 3,046 being utilized as an enabling pulse for a gate 3,045 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E).

The BV-35 pulse is applied to a gate 3,662 to test the output of decoder 198. If this output is a "2," a pulse appears on a line 3,658, such pulse being employed to turn on monostable multivibrator BV-11. If this output is either a "1" or a "3," a pulse appears on line 3,660, the latter pulse being utilized to turn on monostable multivibrator BV-6.

It is recalled in connection with the description of the BV microprogram that, if line 3,248 (FIG. 32G) is active, when the B-1 pulse is applied to gate 3,034, a pulse appears on line 3,038 to initiate the cycling of the BV clock. If line 3,248 is not active, one of lines 3,250 through 3,258 is active. Line 3,250 is active if the bit pattern in the designator byte of register R3 is either 01000000 or 01000001 (' or (. Line 3,252 is active if the bit pattern in the designator byte of register R3 is either 01000100 or 01000101 (F or (F. Line 3,254 is active if the bit pattern in the designator byte of register R3 is either 01010000 or 01010001 V' or V. Line 3,256 is active if the bit pattern in the designator byte of register R3 is either 0X10XXX0 or 0X10XXX1 C' or C, the X in the latter patterns signifying "don't care." Line 3,258 is active if the bit pattern in the designator byte of register R3 is either 01110000 or 01110001 δ' or δ. Line 3,260 may be active at the same time that line 3,254 is active. If line 3,260 is not active at the same time that line 3,254 is active, it indicates an error condition and the system operating ceases.

Line 3,260 is active if the bit pattern in the designator byte of register R3 is either 01100010 or 01100011, truth. It is to be noted (FIG. 32G) that the designator byte of register R2 is applied to a decoder 3,264. This designator byte is decoded into seven lines which are labeled A1, A2, A3, A4, A7, AC, and AD. Only one of these lines can be active at any one time. When the D-2 pulse is applied to a gate 3,262, it permits the line in the group 3,250 through 3,258 which is active to be applied to one of the gates 3,266 through 3,274. If line 3,250 is active, one of the lines in the group 3,276 through 3,288 is active. Line 3,276 is employed to turn on a monostable multivibrator (A1-1. Line 3,278 is used to turn on a monostable multivibrator (A2-1. Line 3,280 is employed to turn on a monostable multivibrator (A3-1. Line 3,282 is used to turn on a monostable multivibrator (A4-1. Line 3,284 is employed to turn on a monostable multivibrator (A7-1. Line 3,286 is used to turn on a monostable multivibrator (AC-1. Line 3,288 is used to turn on a monostable multivibrator.

If line 3,252 is active (FIG. 32G), one of the lines in the group 3,290 through 3,302 is active. Line 3,290 is used to turn on monostable multivibrator (A1-1. Line 3,292 is used to turn on a monostable multivibrator (FA3-8. Line 3,294 is used to turn on a monostable multivibrator (FA3-1. Line 3,296 is utilized to turn on a monostable multivibrator (FA4-1. Line 3,298 is used to turn on a monostable multivibrator (FA7-1. Line 3,300 is employed to turn on a monostable multivibrator (FAC-1. Line 3,302 is employed to turn on a monostable multivibrator (FAD-1. The (A clocks are shown on FIGS. 35A-35G. The (FA clocks are shown on FIGS. 36A-36E.

As seen in FIG. 32G, if line 3,254 is active, one of the lines in the group 3,304 through 3,316 is active. Line 3,304 is used to turn on a monostable multivibrator VA1-1. Line 3,306 is employed to turn on a monostable multivibrator VA2-1. Line 3,308 is utilized to turn on a monostable multivibrator VA3-1. Line 3,310 is used to turn on a monostable multivibrator VA4-1. Line 3,312 is used to turn on a monostable multivibrator VA7-1. Line 3,314 is employed to turn on a monostable multivibrator VAC-1. Line 3,316 is employed to turn on a monostable multivibrator VAD-1.

If line 3,256 is active, one of the lines in the group 3,318 through 3,332 is active. Line 3,318 is used to turn on a monostable multivibrator VA1-1. Line 3,320 is used to turn on a monostable multivibrator CA2-1. Line 3,322 is employed to turn on a monostable multivibrator CA3-1. The VA clocks are shown in FIGS. 37A-37G.

It is to be noted (FIG. 32G) that the four right-hand bytes of register R3 are applied to the decoder 3,348. Line 3,350 is active if the four right-hand bytes of register R3 are all zeros. Line 3,352 is active if the four right-hand bytes of register R3 are all "1'."

If the A4 output line of decoder 3,264 is active and if line 3,260 is also active, an output is produced on AND-circuit 3,354 which is applied to AND-circuits 3,356 and 3,358. If an output is produced from AND-circuit 3,356, such output will pass through a gate 3,272 to appear on a line 3,324, the output on line 3,324 being utilized to turn on a monostable multivibrator CA4F-1. If an output is produced from AND-circuit 3,358, such output will pass through gate 3,272 to appear on a line 3,326, the output on line 3,326 being employed to turn on a monostable multivibrator CA4T-1. The output appearing on line 3,328 is used to turn on a monostable multivibrator CA7-1. The output appearing on line 3,330 is utilized to turn on a monostable multivibrator CA2-1 and the output appearing on line 3,332 is used to turn on a monostable multivibrator CAD-1.

If line 3,258 (FIG. 32G) is active, one of the lines in the group 3,334 through 3,346 is also active. Line 3,334 is used to turn on a monostable multivibrator VA1-1.

(A-1 Microprogram

In the execution of the (A1 microprogram, the (A1-1 pulse is applied to an OR-circuit 3,042, the output of OR-circuit 3,042 enabling a gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The (A1-2 pulse is applied to an OR-circuit 3,234, the consequent output of OR-circuit output of OR-circuit 3,234 enabling a gate 3,238 to gate "F2" which is in a register 3,236 to the left-hand byte of register R2 (FIG. 32C). The (A1-2 pulse is applied to an OR-circuit 3,240, the consequent output of OR-circuit 3,240 enabling a gate 3,242 to thereby gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The (A1-2 pulse is applied to an OR-circuit 3,172, the consequent output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,196 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator (A1-2 gores off, a pulse appears on a line 3,204 (FIG. 34A) which is employed to turn on monostable multivibrator BV-17. This latter action initiates a "dump to tablet" operation which is followed by a return to the "acceptance state."

The (A2-1 pulse is applied to an OR-circuit 3,042, the consequent output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The (A2-1 pulse is also applied to an OR-circuit 3,046, the consequent output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E).

The (A2-2 pulse is applied to an OR-circuit 3,150, the consequent output of OR-circuit 3,152 appearing on line 192 (FIG. 32H). The (A2-2 pulse is applied to an OR-circuit 3,244, the consequent output of OR-circuit 3,244 enabling gate 3,246 to gate "01" which is in register 3,249 to cable 194 (FIG. 32H). The (A2-2 pulse is applied to an OR-circuit 3,152, the output of OR-circuit 3,152 being applied to "successor" gate 3,154 (FIG. 32C). The (A2-2 pulse is applied to an OR-circuit 3,198, the output of OR-circuit 3,198 enabling a gate 3,200 to gate "F3" which is in register 3,202 to the left-hand byte of register R2 (FIG. 32C). The (A2-2 pulse is applied to an OR-circuit 3,160, the output of OR-circuit 3,160 enabling a gate 3,162 in order to gate the four right-hand bytes of register M through incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The (A2-2 pulse is applied to an OR-circuit 3,172, the output of OR-circuit 3,172 enabling a gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator (A2-2 goes off, a pulse appears on a line 3,026, the latter pulse being used to turn on a monostable multivibrator BB-17. This latter action initiates a "dump to tablet" operation which is followed by a return to the "acceptance state."

The (A3-1 pulse is applied to an OR-circuit 3,042, the consequent output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The (A3-1 pulse is applied to an OR-circuit 3,046, the consequent output of OR-circuit 3,046 enabling a gate 3,048 in order to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E). The (A3-1 pulse is applied to a gate 3,360 in order to test for the state of the rightmost bit of the designator field of register R3. If this bit is in the "1" state, a pulse appears on a line 3,362 which is employed to turn on monostable multivibrator (A3-2. However, if the rightmost bit of the designator field of register R3 is a "0," a pulse appears on a line 3,364 which is used to turn on monostable multivibrator (A3-8 (FIG. 32G).

The (A3-2 pulse is applied to an OR-circuit 3,366, the consequent output of OR-circuit 3,366 enabling a gate 3,368 to gate the information on cable 264 to the mod 4 counter 3,370 (FIG. 32H).

The (A3-3 pulse is applied to an OR circuit 3,372, the consequent output of OR-circuit 3,372 incrementing mod 4 counter 3,370 (FIG. 32H).

The (A3-4 pulse is applied to OR-circuit 3,374, the output of OR-circuit 3,374 enabling gate 3,376 to gate the contents of mod 4 counter 3,370 to cable 194 (FIG. 32H). The (A3-4 pulse is applied to an OR-circuit 3,056, the consequent output of OR-circuit 3,056 enabling gate 3,058, i.e., the "predecessor gate" (FIG. 32F). The (A3-4 pulse is applied to an OR-circuit 3,156, the consequent output of OR-circuit 3,156 enabling gate 3,173 to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The (A3-4 pulse is applied to an OR-circuit 3,240, the consequent output of OR-circuit 3,240 enabling a gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The (A3-4 pulse is applied to an OR-circuit 3,172, the consequent output of OR-circuit 3,172 enabling gate 3,174 to gate "b" which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The (A3-5 pulse is applied to an OR-circuit 3,122, the consequent output of OR-circuit 3,122 appearing on line 158 to set flip-flop 260 to its "1" state (FIG. 32D). The latter action initiates a "dump to tablet" operation as has been previously described.

The (A3-6 pulse is applied to gate 3,378 in order to test for the state of flip-flop 260 (FIG. 32D). If this test shows that flip-flop 260 is in its "1" state, a pulse appears on line 3,380 which is employed to turn on monostable multivibrator (A3-7. However, if the test shows that flip-flop 260 is in its "0" state, a pulse appears on line 3,382 and is used to turn on monostable multivibrator (A3-8. Monostable multivibrator (A3-7 is used for delay only and returns the clock to (A3-6.

The (A3-8 pulse is applied to an OR-circuit 3,042, the consequent output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The (A3-8 pulse is also applied to an OR-circuit, 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E).

The (A3-9 pulse is applied to an OR-circuit 3,150, the consequent output of OR-circuit 3,150 appearing on line 192 (FIG. 32H). The (A3-9 pulse is applied to an OR-circuit 3,244, the consequent output of OR-circuit 3,244 enabling gate 3,246 to gate "01" which is in register 3,249 to cable 194 (FIG. 32H). The (A3-9 pulse is applied to an OR-circuit 3,152, the output of OR-circuit 3,152 being applied to "successor gate" 3,154 (FIG. 32C). The (A3-9 pulse is applied to an OR-circuit 3,384, the output of OR-circuit 3,384 enabling gate 3,386 to gate "F7" which is in register 3,388 to the left-hand byte of register R2 (FIG. 32C). The (A3-9 pulse is applied to an OR-circuit 3,160, the output of OR-circuit 3,160 enabling a gate 3,162 to gate the four right-hand bytes or register M through the incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The (A3-9 pulse is applied to an OR-circuit 3,172, the consequent output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The (A4-1 pulse is applied to an OR-circuit 3,042, the consequent output of OR-circuit 3,042 enabling a gate 3,044 to gate the contents of register R to register W (FIG. 32E). The (A4-1 pulse is also applied to an OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E).

The (A4-2 pulse is applied to an OR circuit 3,050, the output of OR-circuit 3,050 enabling a gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The (A4-2 pulse is applied to an OR-circuit 3,056, the output of OR-circuit 3,056 being applied to the "predecessor gate" 3,058 (FIG. 32F). The (A4-2 pulse is applied to an OR-circuit 3,390, the output of OR-circuit 3,390 enabling gate 3,392 to gate "00" which is in register 3,394 to the left-hand byte of register R2 (FIG. 32C). The (A4-2 pulse is applied to an OR-circuit 3,240, the output of OR-circuit 3,240 enabling a gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The (A4-2 pulse is applied to an OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The (A4-3 pulse is applied to an OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state. The latter action initiates a "dump to tablet" operation (FIG. 32D).

The (A4-4 pulse is applied to gate 3,396 in order to test for the state of flip-flop 260. If this test shows that flip-flop 260 is in its "1" state, a pulse appears on line 3,398 which is employed to turn on monostable multivibrator (A4-5. The latter monostable multivibrator is used for delay only and returns the clock to (A4-4. If the test shows that flip-flop 260 is in its "0" state, a pulse appears on line 3,400 which is utilized to turn on monostable multivibrator (A2-1.

The (A7-1 pulse is applied to an OR-circuit 3,042, the consequent output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W. The (A7-1 pulse is also applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register.

The (A7-2 pulse is applied to an OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The (A7-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor gate" 3,058 (FIG. 32F). The (A7-2 pulse is applied to OR-circuit 3,402, the output of OR-circuit 3,402 enabling gate 3,404 to gate the four right-hand bytes of register M through incrementor 3,406 to the four right-hand bytes of register R1 (FIG. 32F). The (A7-2 pulse is applied to OR-circuit 3,408, the output of OR-circuit 3,408 enabling the gate 3,410 to gate b which is in register 3,176 to the left-hand byte of register R1 (FIG. 32B). The (A7-2 pulse is applied to an OR-circuit 3,412, the output of OR-circuit 3,412 enabling gate 3,414 to gate u which is in register 3,416 to the left-hand byte of register R3 (FIG. 32B). The (A7-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B).

The (A7-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state thereby initiating the "dump to tablet" operation (FIG. 32D).

The (A7-4 pulse is applied to gate 3,422 to test the state of flip-flop 260 (FIG. 32D). If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,424 which is used to turn on monostable multivibrator (A7-5. The latter monostable multivibrator is employed for delay only and returns the clock to (A7-4. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,426 and is used to turn on single shot (A3-1.

The (AC-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The (AC-2 pulse is applied to an OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 to gate "UP" which is in register 3,432 to the left-hand byte of register R1 (FIG. 32B). The (AC-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The (AC-2 pulse is applied to an OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). The (AC-2 pulse is applied to OR-circuit 3,434, the output of OR-circuit 3,434 enabling gate 3,436 to gate the four right-hand bytes of register M through incrementor 3,438 to the four right-hand bytes of register R3 (FIG. 32F).

The (AC-3 pulse is applied to an OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32B). This initiates the "dump to tablet" operation.

The (AC-4 pulse is applied to gate 3,440 to test the state of flip-flop 260 (FIG. 32D). If this test shows that flip-flop 260 is in its "1" state, a pulse appears on line 3,442 which is employed to turn on monostable multivibrator (AC-5. This latter multivibrator is used for delay only and returns the clock to (AC-4. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,444 which is used to turn on monostable multivibrator (A3-8.

The (AD-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The (AD-2 pulse is applied to OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 to gate "UP" from register 3,432 to the left-hand byte of register R1 (FIG. 32B). The (AD-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The (AD-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,156 to the left-hand byte of register R3 (FIG. 32B). The (AD-2 pulse is applied to OR-circuit 3,434, the output of OR-circuit 3,434 enabling gate 3,436 to gate the four right-hand bytes of register M through incrementor 3,438 to the four right-hand bytes of register R3 (FIG 32F).

The (AD-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D). This initiates the "dump to tablet" operation.

The (AD-4 pulse is applied to gate 3,446 to test for the state of flip-flop 260. If this test finds flip-flop 260 in its "1" state, a pulse appears on line 3,448 which is used to turn on monostable multivibrator (AD-5. The latter monostable multivibrator is used for delay only and returns the clock to (AD-4. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,450 which is used to turn on monostable multivibrator (A3-1.

(F Microprograms

The (FA3-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The (FA3-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E). The (FA3-1 pulse is applied to gate 3,452 to test for the state of the rightmost bit of the designator byte of register R3 (FIG. 32G). If the test finds that this bit is a "1," a pulse appears on line 3,454 which is utilized to turn on monostable multivibrator (FA3-2. However, if the test finds that this bit is a "0," a pulse appears on line 3,456 which is used to turn on monostable multivibrator (FA3-8.

The (FA3-2 pulse is applied to OR-circuit 3,366, the output of OR-circuit 3,366 enabling gate 3,368 to gate the information on cable 264 to mod 4 counter 3,370 (FIG. 32H). The (FA3-3 pulse is also applied to OR-circuit 3,372, the output of OR-circuit 3,372 incrementing mod 4 counter 3,370 (FIG. 32H).

The (FA3-4 pulse is applied to OR-circuit 3,374, the output of OR-circuit 3,374 enabling gate 3,376 to gate the contents of mod 4 counter 3,370 to cable 194 (FIG. 32H). The (FA3-4 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor gate" 3,058 (FIG 32F). The (FA3-4 pulse is applied to OR-circuit 3,156, the output of OR-circuit 3,156 enabling gate 3,173 in order to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The (FA3-4 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The (FA3-4 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The (FA3-5 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D). This initiates the "dump to tablet" operation.

The (FA3-6 pulse is applied to gate 3,458 to test for the state of flip-flop 260 (FIG. 32D). If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,460 which is employed to turn on monostable multivibrator (FA3-7 (FIG. 32D). This latter monostable multivibrator is used for delay only and returns the clock to (FA3-6. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,462 which is used to turn on monostable multivibrator (FA3-8.

The (FA3-8 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The (FA3-8 pulse is also applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E).

The (FA3-9 pulse is applied to OR-circuit 3,150, the output of OR-circuit 3,150 appearing on line 192 (FIG. 32H). The (FA3-9 pulse is applied to OR-circuit 3,244, the output of OR-circuit 3,244 enabling gate 3,246 to gate "01" which is in register 3,249 to cable 194 (FIG. 32H). The (FA3-9 pulse is applied to OR-circuit 3,152, the output of OR-circuit 3,152 being applied to "successor gate" 3,154 (FIG. 32C). The (FA3-9 pulse is applied to gate 3,464 to gate "F4" which is in register 3,468 to the left-hand byte of register R2 (FIG. 32C). The (FA3-9 pulse is applied to OR-circuit 3,160, the output of OR-circuit 3,160 enabling gate 3,162 to gate the four right-hand bytes of register M through incrementer 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The (FA3-9 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator (FA3-9 goes off, a pulse appears on line 3,120 which is employed to turn on monostable multivibrator VV-17. The latter action initiates the "dump to tablet" operation which is followed by a return to the "acceptance state."

The (FA4-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The (FA4-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E).

The (FA4-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The (FA4-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor gate" 3,058 (FIG. 32F). The (FA4-2 pulse is applied to OR-circuit 3,090, the output of OR-circuit 3,090 enabling gate 3,392 to gate "00" which is in register 3,394 to the left-hand byte of register R2 (FIG. 32C). The (FA4-2 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The (FA4-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The (FA4-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D). The latter action initiates the "dump to tablet" operation.

The (FA4-4 pulse is applied to gate 3,470 in order to test for the state of flip-flop 260. If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,472 which is used to turn on monostable multivibrator (FA4-5. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,474 which is employed to turn on monostable multivibrator (FA3-9. Monostable multivibrator (FA4-5 is used for delay only and returns the clock to (FA4-4.

The (FA7-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W. The (FA7-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E).

The (FA7-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 in order to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The (FA7-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor" gate 3,058 (FIG. 32F). The (FA7-2 pulse is applied to OR-circuit 3,408, the output of OR-circuit 3,408 enabling gate 3,410 to gate b which is in register 3,176 to the left-hand byte of register R1 (FIG. 32B). The (FA7-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 in order to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The (FA7-2 pulse is applied to OR-circuit 3,412, the output of OR-circuit 3,412 enabling gate 3,414 to gate u which is in register 3,416 to the left-hand byte of register R3 (FIG. 32B).

The (FA7-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D). This latter action initiates a "dump to tablet" operation.

The (FA7-4 pulse is applied to gate 3,476 to test for the state of flip-flop 260. If flip-flop 260 is in its "1" state, a pulse appears on line 3,478 which is used to turn on monostable multivibrator (FA7-5. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,480 which is used to turn on monostable multivibrator (FA3-1. Monostable multivibrator (FA7-5 is used for delay only and returns the clock to (FA7-4.

The (FAC-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The (FAC-2 pulse is applied to OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 to gate "UP" which is in register 3,432 to the left-hand byte of register R1 (FIG. 32B). The (FAC-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The (FAC-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). The (FAC-2 pulse is also applied to OR-circuit 3,434, the output of OR-circuit 3,434 enabling gate 3,436 to gate the four right-hand bytes of register M through incrementor 3,438 to the four right-hand bytes of register R3 (FIG. 32F).

The (FAC-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate a "dump to tablet" operation.

The (FAC-4 pulse is applied to gate 3,482 to test for the state of flip-flop 260 (FIG. 32D). If flip-flop 260 is in its "1" state, a pulse appears on line 3,484, which is employed to turn on monostable multivibrator (FAC-5. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,486 which is employed to turn on monostable multivibrator (FA3-8. Monostable multivibrator (FAC-5 is used for delay only and returns the clock to (FAC-4.

The (FAD-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 to enable the gating of the contents of register R to register W (FIG. 32E).

The (FAD-2 pulse is applied to OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 to gate "UP" which is in register 3,432 to the left-hand byte of register R1 (FIG. 32B). The (FAD-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The (FAD-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). The (FAD-2 pulse is applied to OR-circuit 3,434, the output of OR-circuit 3,434 enabling gate 3,436 to gate the four right-hand bytes of register M through incrementor 3,438 to the four right-hand bytes of register R3 (FIG. 32F).

The (FAD-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate a "dump to tablet" operation.

The (FAD-4 pulse is applied to gate 3,488 to test for the state of flip-flop 260. If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,490 and is used to turn on monostable multivibrator (FAD-5. This monostable multivibrator is used for delay only and returns the clock to (FAD-4. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,492 and is used to turn on monostable multivibrator (FA3-1.

"V" Microprograms

The VA1-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The VA1-2 pulse is applied to OR-circuit 3,234, the output of OR-circuit 3,234 enabling gate 3,238 to gate "F2" which is in register 3,236 to the left-hand byte of register R2 (FIG. 32C). The VA1-2 pulse is applied to OR-circuit 3,160, the output of OR-circuit 3,160 enabling gate 3,162 to gate the four right-hand bytes of register M to the four right-hand bytes of register R2 (FIG. 32F). The VA1-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator VA1-2 goes off, a pulse appears on line 3,212 which is used to turn on monostable multivibrator BV-17 to thereby initiate the "dump to tablet" operation which is followed by a return to the "acceptance state."

The VA2-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The VA2-2 pulse is applied to gate 3,494 to gate "?" from register 3,496 to the left-hand byte of register R1 (FIG. 32B). The VA2-2 pulse is applied to OR-circuit 3,114, the output of OR-circuit 3,114 enabling gate 3,116 to gate the four right-hand bytes of register D to the four right-hand bytes of register R1 (FIG. 32F). The VA2-2 pulse is applied to OR-circuit 3,118, the output of OR-circuit 3,118 enabling gate 3,120 to gate the contents of register B to register R3 (FIG. 32F). It is to be noted that when monostable multivibrator VA2-2 goes off, a pulse appears on line 3,214 which is used to turn on monostable multivibrator BV-17 to thereby initiate the "dump to tablet" operation which is followed by a return to the "acceptance" state.

The VA3-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The VA3-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E). The VA3-1 pulse is applied to gate 3,498 to test for the state of the right-hand bit of the designator byte of register R3 (FIG. 32G). If this bit is a "1," a pulse appears on line 3,502 and is employed to turn on monostable multivibrator VA3-2. However, if this bit is a "0," a pulse appears on line 3,500 which is used to turn on monostable multivibrator VA2-1.

The VA3-2 pulse is applied to OR-circuit 3,366, the output of OR-circuit 3,366 enabling gate 3,368 to gate the rightmost nonzero digit in the tree address register to mod 4 counter 3,370 (FIG. 32H).

The VA3-3 pulse is applied to OR-circuit 3,372, the output of OR-circuit 3,372 incrementing mod 4 counter 3,370 (FIG. 32H).

The VA3-4 pulse is applied to OR-circuit 3,374, the output of OR-circuit 3,374 enabling gate 3,376 to gate the contents of mod 4 counter 3,370 to cable 194 (FIG. 32H). The VA3-4 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor" gate 3,058 (FIG. 32F). The VA3-4 pulse is applied to OR-circuit 3,156, the output of OR-circuit 3,156 enabling gate 3,173 to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The VA3-4 pulse is applied to OR-circuit 3,160, the output of OR-circuit 3,160 enabling gate 3,162 to gate the four right-hand bytes of register M through incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The VA3-4 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The VA3-5 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) thereby initiating a "dump to tablet" operation.

The VA3-6 pulse is applied to gate 3,504 to test for the state of flip-flop 260 (FIG. 32D). If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,506 which is employed to turn on monostable multivibrator VA3-7. Monostable multivibrator VA3-7 is used for delay only and returns the clock to VA3-6. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,508 which is used to turn on monostable multivibrator VA2-1.

The VA4-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The VA4-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register RO to the tree address register (FIG. 32E).

The VA4-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The VA4-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor" gate 3,058 (FIG. 32F). The VA4-2 pulse is applied to OR-circuit 3,390, the output of OR-circuit 3,390 enabling gate 3,392 to gate "00" which is in register 3,394 to the left-hand byte of register R2 (FIG. 32C). The VA4-2 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The VA4-2 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The VA4-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on wire 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate a "dump to tablet" operation.

The VA4-4 pulse is applied to gate 3,510 to test for the state of flip-flop 260. If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,512 which is used to turn on monostable multivibrator VA4-5. Monostable multivibrator VA4-5 is used for delay only and returns the clock to monostable multivibrator VA4-4. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,514 which is used to turn on monostable multivibrator VA2-1.

The VA7-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The VA7-1 pulse is also applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register RO to the tree address register (FIG. 32E).

The VA7-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The VA7-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to the "predecessor" gate 3,058 (FIG. 32F). The VA7-2 pulse is applied to OR-circuit 3,408, the output of OR-circuit 3,408 enabling gate 3,410 to gate b which is in register 3,176 to the left-hand byte of register R1 (FIG. 32B). The VA7-2 pulse is applied to OR-circuit 3,402, the output of OR-circuit 3,402 enabling gate 3,404 to gate the four right-hand bytes of register M through incrementor 3,406 to the four right-hand bytes of register R1 (FIG. 32F). The VA7-2 pulse is applied to OR-circuit 3,412, the output of OR-circuit 3,412 enabling gate 3,414 to gate u which is in register 3,416 to the left-hand byte of register R3 (FIG. 32B). The VA7-2 pulse is also applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B).

The VA7-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate a "dump to tablet" operation.

The VA7-4 pulse is applied to gate 3,516 to test for the state of flip-flop 260 (FIG. 32D). If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,518 which is used to turn on monostable multivibrator VA7-5. Monostable multivibrator VA7-5 is used for delay only and returns the clock to VA7-4. However, if the test shows that flip-flop 260 is in its "0" state, a pulse appears on line 3,520 which is used to turn on monostable multivibrator VA3-1.

The VAC-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The VAC-2 pulse is applied to OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 to gate "UP" which is in register 3,432 to the left-hand byte of register R1 (FIG. 32B). The VAC-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The VAC-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). The VAC-2 pulse is also applied to OR-circuit 3,434, the output of OR-circuit 3,434 enabling gate 3,436 to gate the four right-hand bytes of register M through incrementor 3,438 to the four right-hand bytes of register R3 (FIG. 32F).

The VAC-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate a "dump to tablet" operation.

The VAC-4 pulse is applied to gate 3,522 to test for the state of flip-flop 260 (FIG. 32D). If flip-flop 260 is in its "1" state, a pulse appears on line 3,524 which is used to turn on monostable multivibrator VAC-5. Monostable multivibrator VAC-5 is used for delay only and returns the clock to VAC-4. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,526 which is used to turn on monostable multivibrator VA2-1.

The VAD-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32C).

The VAD-2 pulse is applied to OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 in order to gate "UP" which is in register 3,432 to the left-hand byte of register R1 (FIG. 32B). The VAD-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The VAD-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). The VAD-2 pulse is also applied to OR-circuit 3,434, the output of OR-circuit 3,434 enabling gate 3,436 to gate the four right-hand bytes of register M through incrementor 3,438 to the four right-hand bytes of register R3 (FIG. 32F).

The VAD-3 pulse is applied to OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate a "dump to tablet" operation.

The VAD-4 pulse is applied to gate 3,528 to test for the state of flip-flop 260 (FIG. 32D). If the test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,530 which is used to turn on monostable multivibrator VAD-5. Monostable multivibrator VAD-5 is used for delay only and returns the clock to VAD-4. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,532 which is used to turn on monostable multivibrator VA3-1.

"C" Microprograms

The CA2-1 pulse is applied to OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 to gate "UP" which is in register 3,432 to the left-hand byte of register R1 (FIG. 32B). The CA2-1 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). It is to be noted that when monostable multivibrator CA2-1 goes off, a pulse appears on line 3,216 which is used to turn on monostable multivibrator BV-17 to initiate a "dump to tablet" operation which is followed by a return to the "acceptance state."

The CA3-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 in order to gate the contents of register R to register W (FIG. 32E). The CA3-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register RO to the tree address register (FIG. 32G). The CA3-1 pulse is applied to gate 3,534 to test the state of the right-hand bit of the designator byte of register R3. If this test finds the designator bit is a "1," a pulse appears on line 3,536, which is used to turn on monostable multivibrator CA3-2. However, if the test finds that the designator bit is a "0," a pulse appears on line 3,538 which is used to turn on monostable multivibrator BV-20.

The CA3-2 pulse is applied to OR-circuit 3,366, the output of OR-circuit 3,366 enabling gate 3,368 to gate the information on cable 264 to mod 4 counter 3,370 (FIG. 32H).

The CA3-3 pulse is applied to OR-circuit 3,372, the output of OR-circuit 3,372 incrementing the mod 4 counter 3,370 (FIG. 32H).

The CA3-4 pulse is applied to OR-circuit 3,374, the output of OR-circuit 3,374 enabling gate 3,376 to gate the contents of mod 4 counter 3,370 to cable 194 (FIG. 32H). The CA3-4 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor" gate 3,058 (FIG. 32F). The CA3-4 pulse is applied to OR-circuit 3,156, the output of OR-circuit 3,156 being applied to gate 3,173 to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The CA3-4 pulse is applied to OR-circuit 3,160, the output of OR-circuit 3,160 being applied to gate 3,162 to gate the four right-hand bytes of register M through incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The CA3-4 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 being applied to gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator CA3-4 goes off, a pulse appears on line 3,218 which is used to turn on monostable multivibrator BV-17. This latter action initiates a "dump to tablet" operation which is followed by a return to the "acceptance state."

The CA4T-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The CA4T-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register RO to the tree address register (FIG. 32E).

The CA4T-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The CA4T-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor" gate 3,058 (FIG. 32F). The CA4T-2 pulse is applied to OR-circuit 3,234, the output of OR-circuit 3,234 enabling gate 3,238 to gate "F2" which is in register 3,236 to the left-hand byte of register R2 (FIG. 32C). The CA4T-2 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,244 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The CA4t-2 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator CA4T-2 goes off, a pulse appears on line 3,220 which is used to turn on monostable multivibrator BV-17. The latter action initiates a "dump to tablet" operation which is followed by the return to the "acceptance state."

The CA4F-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The CA4F-1 pulse is also applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 in order to gate the four right-hand bytes of register RO to the tree address register (FIG. 32E).

The CA4F-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The CA4F-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor gate" 3,058 (FIG. 32F). The CA4F-2 pulse is applied to gate 3,540 to gate "F1" which is in register 3,542 to the left-hand byte of register R2 (FIG. 32C). The CA4F-2 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The CA4F-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator CA4F-2 goes off, a pulse appears on line 3,222 which is used to turn "on" monostable multivibrator BV-17 to initiate the "dump to tablet" operation which is followed by a return to the "acceptance state."

The CA7-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The CA7-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register RO to the tree address register (FIG. 32E).

The CA7-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" which is in register 3,054 to cable 194 (FIG. 32H). The CA7-2 pulse is applied to gate 3,544 to gate the contents of register D to register R1 (FIG. 32F). The CA7-2 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). The CA7-2 pulse is also applied to OR-circuit 3,412, the output of OR-circuit 3,412 being applied to gate 3,414 to gate u which is in register 3,416 to the left-hand byte of register R3 (FIG. 32B).

The CA7-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate the "dump to tablet" operation.

The CA7-4 pulse is applied to gate 3,546 to test for the state of flip-flop 260 (FIG. 32D). If the test finds flip-flop 260 is in the "1" state, a pulse appears on line 3,548 which is used to turn on monostable multivibrator CA7-5. Monostable multivibrator CA7-5 is used for delay only and returns the clock to CA7-4. If the test, however, finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,550 which is used to turn on monostable multivibrator CA3-1.

The CAD-1 pulse is applied to OR-circuit 3,428, the output of OR-circuit 3,428 enabling gate 3,430 to gate "UP" which is in register 3,432 to the left-hand byte of register R1 (FIG. 32B). The CAD-1 pulse is applied to OR-circuit 3,418, the output of OR-circuit 3,418 enabling gate 3,420 to gate u which is in register 3,416 to the left-hand byte of register R2 (FIG. 32B). It is to be noted that when monostable multivibrator CAD-1 goes off, a pulse appears on line 3,224 which is used to turn on monostable multivibrator BV-17. The latter action initiates a "dump to tablet" operation which is followed by a return to the "acceptance state."

"δ" Microprograms

The C δA2-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The δA2-2 pulse is applied to OR-circuit 3,198, the output of OR-circuit 3,198 enabling gate 3,200 to gate "FC" which is in register 3,202 to the left-hand byte of register R2 (FIG. 32C). The δA2-2 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The δA2-2 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator δA2-2 goes off, a pulse appears on line 3,226 which is used to turn on monostable multivibrator BV-17 to thereby initiate the "dump to tablet" operation which is followed by a return to the "acceptance state."

The δA2-3 pulse is applied to OR-circuit 3,672, the output of OR-circuit 3,672 setting flip-flop 3,670 to its "1" state. This initiates a tablet match NO-OP to the left-hand byte of registers R2, R3 to register R3. With flip-flop 3,670 in its "1" state and flip-flop 3,674 in its "0" state, an AND-circuit 3,676 is enabled and the first M-pulse is operative to set flip-flop 3,674 to its "1" state. With flip-flop 3,674 in its "1" state, a line 3,678 is rendered active and it is applied as an input to AND-circuit 3,680 (FIG. 32A). With this arrangement, AND-circuit 3,680 is enabled and, at CB-2 time, AND-circuit 3,680 produces an output which enables gates 3,682 and 3,684 to gate the contents of registers R3 and 3,686 to the association circuits for the associative memory plane. When line 3,678 is rendered active, a line 3,688 is also rendered active and is applied to OR-circuit 3,018, the output of OR-circuit 3,018 enabling gate 3,020 to permit the gating of the word from the associative memory plane to register R. Also, when line 3,678 is rendered active, a line 3,690 is rendered active and applied as an input to OR-circuit 3,026, the consequent output of OR-circuit 3,026 appearing on the "read" input line to the associative memory control. After a match is found in the associative memory plane, a "read complete" signal appears on line 3,028 which is used to set flip-flop 3,670 to its "0" state. The pulse on line 3,028 is also applied as an input to Delay circuit 3,692, the output of Delay circuit 3,692 resetting flip-flop 3,674 to its "0" state.

The δA2-4 pulse is used to test for the completion of the tablet match operation immediately described hereinabove. To this end, the δA2-4 pulse is applied to gate 3,694 to test for the state of flip-flop 3,670 (FIG. 32D). If the test finds that flip-flop 3,670 is in its "1" state, a pulse appears on line 3,696 which is used to turn on monostable multivibrator δA2-5. Monostable multivibrator δA2-5 is employed for delay only and returns the clock to δA2-4. If the test finds that flip-flop 3,670 is in its "0" state, a pulse appears on line 3,698 which is used to turn on single shot δA2-6.

The δA2-6 pulse is applied to an OR-circuit 3,718, the output of OR-circuit 3,718 enabling gate 3,720 to gate the contents of register R2 to register D.

The δA3-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The δA3-1 pulse is also applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register RO to the tree address register (FIG. 32E). The δA3-1 pulse is applied to gate 3,552 to test for the state of the right-hand bit of the designator byte of register R3. If this bit is a "1," a pulse appears on line 3,554 which is used to turn on monostable multivibrator δA3-2. However, if this bit is a "0," a pulse appears on line 3,556 and is used to turn on monostable multivibrator δA2-1.

The δA3-2 pulse is applied to OR-circuit 3,366, the output of OR-circuit 3,366 enabling gate 3,368 to gate the information on cable 264 to mod 4 counter 3,370 (FIG. 32H).

The δA3-3 pulse is applied to OR-circuit 3,372, the output of OR-circuit 3,372 incrementing mod 4 counter 3,370 (FIG. 32H).

The δA3-4 pulse is applied to OR-circuit 3,374, the output of OR-circuit 3,374 enabling gate 3,376 to gate the contents of mod 4 counter 3,370 to cable 194 (FIG. 32H). The δA3-4 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessorr" gate 3,058 (FIG. 32C). The δA3-4 pulse is applied to OR-circuit 3,156, the output of OR-circuit 3,156 being applied to gate 3,173 to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The δA3-4 pulse is applied to OR-circuit 3,160, the output of OR-circuit 3,160 enabling gate 3,162 to gate the four right-hand bytes of register M through incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The δA3-4 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The δA3-5 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 (FIG. 32D) to its "1" state to thereby initiate a "dump to tablet" operation.

The δA3-6 pulse is applied to gate 3,558 to test for the state of flip-flop 260 (FIG. 32D). If this test finds that flip-flop 260 is in its "1" state, a pulse appears on line 3,560 which is used to turn on monostable multivibrator δA3-7, monostable multivibrator δA3-7 being used for delay only and returns the clock to δA3-6. However, if the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,562 which is used to turn on monostable multivibrator δA2-1.

The δA4-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The δA4-1 pulse is also applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register RO to the tree address register (FIG. 32E).

The δA4-2 pulse is applied to OR-circuit 3,050, the output of OR-circuit 3,050 enabling gate 3,052 to gate "00" to cable 194 (FIG. 32H). The δA4-2 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to the "predecessor gate" 3,058 (FIG. 32F). The δA4-2 pulse is applied to OR-circuit 3,390, the output of OR-circuit 3,390 enabling gate 3,392 to gate "00" which is in register 3,394 to the left-hand byte of register R2 (FIG. 32C). The δA4-2 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The δA4-2 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The δA4-3 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 (FIG. 32D) to its "1" state to thereby initiate a "dump to tablet" operation.

The δA4-4 pulse is applied to gate 3,564 to test for the state of flip-flop 260 (FIG. 32D). If flip-flop 260 is in its "1" state, a pulse appears on line 3,566 which is used to turn on monostable multivibrator δA4-5. Monostable multivibrator δA4-5 is used for delay only and returns the clock to δA4-4. However, if the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,568 which is used to turn on δA2-1.

The δA7-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The δA7-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E). The δA7-1 pulse is applied to gate 3,570 to test for the state of the right-hand bit of the designator byte of register R3. If this bit is a "1," a pulse appears on line 3,572 which is used to turn on monostable multivibrator δA7-2. However, if the test finds that the designator bit is a "0," a pulse appears on line 3,574 which is used to turn on monostable multivibrator δA7-10.

The δA7-2 pulse is applied to OR-circuit 3,366, the output of OR-circuit 3,366 enabling gate 3,368 to gate the information on cable 264 to mod 4 counter 3,370 (FIG. 32H).

The δA7-3 pulse is applied to OR-circuit 3,372 to increment mod 4 counter 3,370 (FIG. 32H).

The δA7-4 pulse is applied to OR-circuit 3,374, the output of OR-circuit 3,374 enabling gate 3,376 to gate the contents of mod 4 counter 3,370 to cable 194 (FIG. 32H). The δA7-4 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to "predecessor" gate 3,058 (FIG. 32F). The δA7-4 pulse is applied to OR-circuit 3,156, the output of OR-circuit 3,156 enabling gate 3,173 to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C).

The δA7-4 pulse is applied to OR-Circuit 3,160, the output of OR-circuit 3,160 enabling gate 3,162 to gate the four right-hand bytes of register M through incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32F). The δA7-4 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The δA7-5 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 to its "1" state (FIG. 32D) to thereby initiate a "dump to tablet" operation.

The δA7-6 pulse is applied to gate 3,576 to test for the state of flip-flop 260 (FIG. 32D). If this test finds flip-flop 260 is in its "1" state, a pulse appears on line 3,578 which is used to turn on monostable multivibrator δA7-7. Monostable multivibrator δA7-7 is used for delay only and returns the clock to δA7-6. If the test, however, finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,580 which is used to turn on monostable multivibrator δA7-8.

The δA7-8 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The δA7-9 pulse is applied to OR-circuit 3,384, the output of OR-circuit 3,384 enabling gate 3,386 to gate "F7" which is in register 3,388 to the left-hand byte of register R2 (FIG. 32C). The δA7-9 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The δA7-9 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling ate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator δA7-9 goes off, a pulse appears on line 3,230 which is used to turn on single shot BV-17. The latter action initiates a "dump to tablet" operation which is followed by a return to the "acceptance state."

The δA7-10 pulse is applied to OR-circuit 3,672 to set flip-flop 3,670 to its "1" state. This initiates a tablet match NO-OP to the left-hand byte of registers R2, R3 to register R3 operation as has already been described hereinabove.

The δA7-11 pulse is applied to gate 3,700 to test for the state of flip-flop 3,670. If this test finds that flip-flop 3,670 is in its "1" state, a pulse appears on line 3,702 which is used to turn on monostable multivibrator δA7-12. However, if the test finds that flip-flop 3,670 is in its "0" state, a pulse appears on line 3,704 which is used to turn on monostable multivibrator δA7-13. Monostable multivibrator δA7-12 is used for delay only and returns the clock to δA7-11.

The δA7-13 pulse is applied to OR-circuit 3,718, the output of OR-circuit 3,718 enabling gate 3,720 to gate the contents of register R2 to register D.

The δAC-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The δAC-2 pulse is applied to gate 3,582 to gate "FC" which is in register 3,584 to the left-hand byte of register R2 (FIG. 32C). The δAC-2 pulse is applied to OR-circuit 3,240, the output of OR- circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The δAC-2 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator δAC-2 goes off, a pulse appears on line 3,228 which is used to turn on monostable multivibrator BV-17 to initiate the "dump to tablet" operation followed by a return to the "acceptance state."

The δAC-3 pulse is applied to OR-circuit 3,672 to set flip-flop 3,670 to its "1" state. This action initiates a tablet match NO-OP to the left-hand byte of registers R2, R3 to register R3 operation.

The δAC-4 pulse is applied to gate 3,706 in order to test for the state of flip-flop 3,670. If the test finds that flip-flop 3,670 is in its "1" state, a pulse appears on line 3,708 which is used to turn on monostable multivibrator δAC-5. Monostable multivibrator δAC-5 is used for delay only and returns the clock to δAC-4. If the test finds that flip-flop 3,670 is in its "0" state, a pulse appears on line 3,710 which is used to turn on monostable multivibrator δAC-6.

The δAC-6 pulse is applied to OR-circuit 3,718, the output of OR-circuit 3,718 enabling gate 3,720 to gate the contents of register R2 to register D.

The δAD-1 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E). The δAD-1 pulse is applied to OR-circuit 3,046, the output of OR-circuit 3,046 enabling gate 3,048 to gate the four right-hand bytes of register R0 to the tree address register (FIG. 32E). The δAD-1 pulse is also applied to gate 3,586 in order to test for the state of the right-hand bit of the designator byte of register R3. If the test finds that this bit is a "1," a pulse appears on line 3,588 which is used to turn on monostable multivibrator δAD-2. However, if the test finds that the designator bit is a "0," a pulse appears on line 3,590 which is used to turn on monostable multivibrator δAD-10.

The δAD-2 pulse is applied to OR-circuit 3,366, the output of OR-circuit 3,366 enabling gate 3,368 to gate the information on cable 264 to mod 4 counter 3,370 (FIG. 32H).

The δAD-3 pulse is applied to OR-circuit 3,372, the output of OR-circuit 3,372 incrementing mod 4 counter 3,370 (FIG. 32H).

The δAD-4 pulse is applied to OR-circuit 3,374, the output of OR-circuit 3,374 enabling gate 3,376 to gate the contents of mod 4 counter 3,370 to cable 194 (FIG. 32H). The δAD-4 pulse is applied to OR-circuit 3,056, the output of OR-circuit 3,056 being applied to the "predecessor gate" 3,058 (FIG. 32F). The δAD-4 pulse is applied to OR-circuit 3,156, the output of OR-circuit 3,156 enabling gate 3,173 to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The δAD-4 pulse is applied to OR-circuit 3,160, the output of OR-circuit 3,160 enabling gate 3,162 to gate the four right-hand bytes of a register M through incrementor 3,164 to the four right-hand bytes of register R2 (FIG. 32C). The δAD-4 pulse is also applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B).

The δAD-5 pulse is applied to OR-circuit 3,122, the output of OR-circuit 3,122 appearing on line 258 to set flip-flop 260 (FIG. 32D) to its "1" state to thereby initiate a "dump to tablet" operation.

The δAD-6 pulse is applied to gate 3,592 to test for the state of flip-flop 260 (FIG. 32D). If flip-flop 260 is in its "1" state, a pulse appears on line 3,594 which is used to turn on monostable multivibrator δAD-7. Monostable multivibrator δAD-7 is used for delay only and returns the clock to δAD-6. If the test finds that flip-flop 260 is in its "0" state, a pulse appears on line 3,596 which is used to turn on monostable multivibrator δAD-8.

The δAD-8 pulse is applied to OR-circuit 3,042, the output of OR-circuit 3,042 enabling gate 3,044 to gate the contents of register R to register W (FIG. 32E).

The δAD-9 pulse is applied to OR-circuit 3,156, the output of OR-circuit 3,156 enabling gate 3,173 to gate "FD" which is in register 3,158 to the left-hand byte of register R2 (FIG. 32C). The δAD-9 pulse is applied to OR-circuit 3,240, the output of OR-circuit 3,240 enabling gate 3,242 to gate the four right-hand bytes of register D to the four right-hand bytes of register R2 (FIG. 32F). The δAD-9 pulse is applied to OR-circuit 3,172, the output of OR-circuit 3,172 enabling gate 3,174 to gate b which is in register 3,176 to the left-hand byte of register R3 (FIG. 32B). It is to be noted that when monostable multivibrator δAD-9 goes off, a pulse appears on line 3,232 which is used to turn on monostable multivibrator BV-17. The latter action initiates the "dump to tablet" operation which is followed by a return to the "acceptance state."

The δAD-10 pulse is applied to OR-circuit 3,672 to set flip-flop 3,670 to its "1" state. This action initiates a tablet match NO-OP to the left-hand bytes of register R2,R3 to register R3 operation.

The δAD-11 pulse is applied to gate 3,712 to test for the state of flip-flop 3,670. If the test finds that flip-flop 3,670 is in its "1" state, a pulse appears on line 3,714 which is used to turn on monostable multivibrator δAD-12. Monostable multivibrator δAD-12 is used for delay only and returns the clock to δAD-11. However, if the test finds that flip-flop 3,670 is in its "0" state, a pulse appears on line 3,716 which is used to turn on monostable multivibrator δAD-13.

The δAD-13 pulse is applied to OR-circuit 3,718, the output of OR-circuit 3,718 enabling gate 3,720 to gate the contents of register R2 to register D.

BETA UNIT

For the description of the Beta unit, reference is made to FIGS. 26A-26E taken together as in FIG. 26. In addition, in FIG. 27 there is shown a detail of the tree address register which is used with the Beta unit and FIG. 28 is a diagram of the Beta clock. The Beta microprogram is depicted on FIGS. 48A and 48B taken together as in FIG. 48.

The Beta unit is normally in the "acceptance state." In this latter state, it looks for a message from the tablet by associating on the left-hand byte of the R1 field of the associative memory plane. In FIG. 26A, it is noted that there is a register designated by the numeral 484 which contains the designator "?v." Initially, a flip-flop 486 (FIG. 26C) is set to its "1" state and flip-flops 488, 490, 492, 494, and 496 are initially reset to their "0" states.

In the operation of the Beta unit, with flip-flop 486 (FIG. 26C) in its "1" state and flip-flop 496 in its "0" state, an AND-circuit 498 is enabled and the first M-pulse is applied to an AND-circuit 498, the output of AND-circuit 498 setting flip-flop 496 to its "1" state thereby activating a line 500. The output on line 500 is applied to OR-circuit 502, the output of OR-circuit 502 enabling a gate 504. The output on line 400 is also applied to OR-circuit 506, the output of OR-circuit 506 providing the "read" signal for the associative memory control. The output of OR-circuit 506 is also applied to an AND-circuit 555, thereby enabling it, such enabling permitting the CB-2 pulse to associate on a vacancy bit. The output on line 500 is also applied as one input to an AND-circuit 508. At CB-2 time, a CB-2 pulse is applied to AND-circuit 508, the consequent enabling of AND-circuit 508 producing an output therefrom which enables a gate 510, the enabling of gate 510 permitting the associative memory plane to associate on the designator in register 484. When a match occurs, the word in the associative memory plane is read out through a gate 504 to the R-register. Concurrently, a "read complete" pulse appears on a line 512, the latter pulse being applied to an AND-circuit 514 thereby enabling it whereby the output of AND-circuit 514 appears on a line 516 which is used to start the Beta clock. A pulse on line 512 also resets flip-flop 486 to its "0" state and is applied to a Delay unit 518, the output of Delay unit 518 resetting flip-flop 496 to its "0" state.

In the operation of the Beta clock designated as the B-clock, once the clock is started, the B-1 pulse is applied to a gate 520 to gate the contents of register R to register W (FIG. 26D). The B-1 pulse is applied to a gate 522 to gate the four right-hand bytes of register R3 to the tree address register 292 (FIG. 26E). The B clock then advances to B-2.

A function of the B-2 pulse is to test the contents of tree address register 292 to ascertain whether it contains a string of zeros. If tree address register 292 does contain such string of zeros, an error has occurred and the system will halt operation by means not shown. It is recalled that in the operation of the B-1 pulse, the four right-hand bytes of register R3 were gated to tree address register 292. The four bytes according to the embodiment chosen contain 32 bits or 16 bit pairs. An examination of FIG. 27 shows that if there is at least one nonzero bit pair in tree address register 292, then line 298 is activated whereas if all of the bit pairs in tree address register 292 are zero, line 298 is not activated. The B-2 pulse is also applied to a gate 528. If a pulse appears on line 524, the clock will continue to B-3. However, if a pulse appears on line 526, it indicates the error as above mentioned.

Let it be assumed that the clock does in fact advance to B-3. The B-3 pulse is applied to a gate 530 to gate the contents of register R3 to register R0 (FIG. 26B). The clock next advances to B-4.

The B-4 pulse is employed to set flip-flop 490 to its "1" state (FIG. 26C). With flip-flop 290 in its "1" state and flip-flop 494 in its "0" state, AND-circuit 532 is enabled whereby it produces an output when the first M-pulse appears to set flip-flop 494 to its "1" state. Line 534 is activated. It is noted that the output on line 534 is applied as an input to AND-circuit 536 and OR-circuits 506 and 502 (FIG. 26A). The consequent output of OR-circuit 506 provides a "read" signal for the associative memory control. The output of OR-circuit 502 is applied to gate 504 in order to gate the word from the associative memory plane to register R where the word is found.

An output is produced from AND-circuit 536 at CB-2 time which enables gate 528 to gate the contents of register R0 to the associative circuits, i.e., the contents of register R0 are used as an argument. When a match is found in the associative memory plane, a word is read to register R and a "read complete" signal appears on line 512. The pulse on line 512 resets flip-flop 490 to its "0" state and is applied to Delay unit 540, the output of Delay unit 540 resetting flip-flop 494 to its "0" state. This operation is suitably termed the "tablet match R0" operation. While it is proceeding, it is noted that the B-5 pulse is testing gate 542 (FIG. 26C). Thus, if flip-flop 490 is in its "1" state, a pulse appears on line 544 which is used to turn on monostable multivibrator B-6. Monostable multivibrator B-6 is used for delay only and returns the clock to B-5. If the test finds that flip-flop 490 is in its "0" state, a pulse appears on line 546 which is used to turn on monostable multivibrator B-7.

The B-7 pulse is applied to OR-circuit 548, the output of OR-circuit 548 appearing on line 302 to set flip-flop 488 to its "1" state (FIG. 26C). With this arrangement, a "dump to tablet" operation is initiated. With flip-flop 488 in its "1" state and flip-flop 492 in its "0" state, an output is produced from AND-circuit 550 when the first M-pulse appears to set flip-flop 492 to its "1" state whereby line 552 is rendered active. Line 552 is applied as an input to AND-circuit 554 (FIG. 26A), such application permitting an association to be made on an empty space in the associative memory plane when the CA-2 pulse occurs. The output on line 552 also serves as a "write" input for the associative memory control and is also applied to gate 556 (FIG. 26A), the enabling of gate 556 thereby permitting the gating of the contents of register R to the associative memory plane. When a vacant location is found in this associative memory plane, the contents of register R are entered thereinto and a "write complete" pulse appears on line 558 (FIG. 26A). The pulse on line 558 is employed to reset flip-flop 488 to its "0" state and is also applied to a Delay unit 560, the output of Delay unit 560 resetting flip-flop 492 to its "0" state.

While the "dump to tablet" operation is proceeding, the state of flip-flop 488 is being tested by the B-8 pulse which is applied to gate 561. If the test finds that flip-flop 488 is in its "1" state, a pulse appears on line 562 which is used to turn on monostable multivibrator B-9. Monostable multivibrator B-9 is used for delay only and returns the clock to B-8. If the test finds that flip-flop 488 is in its "0" state, a pulse appears on line 564 which is used to turn on the monostable multivibrator B-10.

It is noted in FIG. 26D that the compare unit 566 is connected between the four right-hand bytes of register R1 and the four right-hand bytes of register B. The B-10 pulse is applied to gate 568 thereby enabling it, such enabling effecting the testing of the output of compare unit 566. If the test finds that the output of compare unit 566 is equal, a pulse appears on a line 570 which is used to turn on monostable multivibrator B-11. If the test finds that the output of compare unit 566 is unequal, a pulse appears on a line 572 which is used to turn on monostable multivibrator B-2.

The decoder 574 (FIG. 26D) is used to decode the left-hand byte of register R1. The B-11 pulse is applied to gate 576 in order to test this left-hand byte. Thus, if the left-hand byte of register R1 is equal to λ, a pulse appears on line 578 which is used to turn on monostable multivibrator B-12. However, if the test shows that this left-hand byte of register R1 is not equal to λ, a pulse appears on line 580 which is used to turn on monostable multivibrator B-18.

The B-12 pulse is applied to gate 582 to gate v which is contained in register 584 to the left-hand byte of register D (FIG. 26D). The B-12 pulse is also applied to gate 586 to gate the four right-hand bytes of register R0 to the four right-hand bytes of register D (FIG. 26D).

The B-13 pulse is applied to OR-circuit 588, the output of OR-circuit 588 enabling gate 590 to gate the contents of register N to register RO (FIG. 26B). The B-13 pulse is applied to OR-circuit 592, the output of OR-circuit 592 enabling gate 594 to gate "UP" which is contained in register 596 to the left-hand byte of register R1 (FIG. 26B). The B-13 pulse is applied to OR-circuit 598, enabling the gate 700 to gate u which is contained in register 702 to the left-hand byte of register R2 (FIG. 26B). The B-13 pulse is also applied to OR-circuit 704, the output of OR-circuit 704 enabling gate 706 to gate the contents of register D to register R3 (FIG. 26D).

The B-14 pulse is applied to line 302 to initiate the "dump to tablet" operation (FIG. 26C).

The B-15 pulse is applied to gate 708 to test for the state of flip-flop 488 (FIG. 26C). If the test finds that flip-flop 488 is in its "1" state, a pulse appears on a line 710 which is used to turn on monostable multivibrator B-16. Monostable multivibrator B-16 is used for delay only and returns the clock to B-15. If the test finds that flip-flop 488 is in its "0" state, a pulse appears on a line 712 which is used to turn on a monostable multivibrator B-17.

The B-17 pulse is applied to a line 306 to place the beta unit in the "acceptance state."

The B-18 pulse is applied to gate 714 to test for the state of the left-hand byte of register R1 (FIG. 26D). If this left-hand byte is equal to ε, a pulse appears on a line 716 which is used to turn on monostable multivibrator B-19. If, however, this left-hand byte of register R1 is not equal to ε, a pulse appears on a line 718 which indicates an error condition.

The B-19 pulse is applied to a gate 720 to gate the contents of register R0 to register D (FIG. 26D). The B-19 pulse is applied to a gate 722 in order to gate the contents of register R2 to register M (FIG. 26D). The B-19 pulse is also applied to a gate 724 to gate the contents of register R3 to register B (FIG. 26D).

Decoder 726 is employed to decode the left-hand byte of register R2. The B-20 pulse is applied to a gate 728. If the left-hand byte of register R2 is equal to b, a pulse appears on a line 730 which is used to turn on monostable multivibrator B-21. However, if the left-hand byte of register R2 is not equal to b, a pulse appears on a line 732 which is used to turn on a monostable multivibrator B-27.

The B-21 pulse is applied to OR-circuit 588, the output of OR-circuit 588 enabling gate 590 to gate the contents of register N to register R0 (FIG. 26B). The B-21 pulse is applied to an OR-circuit 592, the output of OR-circuit 592 enabling gate 594 to gate "UP" which is in register 596 to the left-hand byte of register R1 (FIG. 26B). The B-21 pulse is applied to an OR-circuit 598, the output of OR-circuit 598 enabling gate 700 to gate u which is in register 702 to the left-hand byte of register R2 (FIG. 26B). The B-21 pulse is applied to an OR-circuit 727, the output of OR-circuit 727 enabling a gate 729 in order to gate b which is in register 731 to the left-hand byte of register R3 (FIG. 26B). The B-21 pulse is also applied to an OR-circuit 733, the output of OR-circuit 733 enabling a gate 734 to gate the four right-hand bytes of register M to the four right-hand bytes of register R3 (FIG. 26B).

The B-22 pulse is applied to an OR-circuit 548, the output of OR-circuit 548 appearing on a line 302 to initiate the "dump to tablet" operation (FIG. 26C).

The B-23 pulse is applied to the gate 736 in order to test for the state of flip-flop 488. If the test finds that flip-flop 488 is in its "1" state, a pulse appears on a line 738 which is used to turn on monostable multivibrator B-24. Monostable multivibrator B-24 is used for delay only and returns the clock to B-23. If, however, the test finds that flip-flop 488 is in its "0" state, a pulse appears on a line 740 which is used to turn on monostable multivibrator B-26.

The B-26 pulse is applied to an OR-circuit 588, the output of OR-circuit 588 enabling gate 590 to gate the contents of register N to register R0 (FIG. 26B). The B-26 pulse is applied to OR-circuit 758, the output of OR-circuit 758 enabling the gate 760 to gate the contents of register B to register R1 (FIG. 26B). The B-26 pulse is applied to gate 762 to gate "UP 2" which is contained in register 764 to the left-hand byte of register R2 (FIG. 26B). The B-26 pulse is applied to OR-circuit 766, the output of OR-circuit 766 enabling gate 768 to gate the four right-hand bytes of register M to the four right-hand bytes of register R2 (FIG. 26P). The B-26 pulse is applied to OR-circuit 704, the output of OR-circuit 704 enabling gate 706 to gate the contents of register D to register R3 (FIG. 26P).

The B-27 pulse is applied to gate 770 to test the left-hand byte of register R2 (FIG. 26D). If the test finds that this left-hand byte of register R2 is equal to "expr," a pulse appears on line 772 which is used to turn on monostable multivibrator B-28. However, if the test finds that the left-hand byte of register R2 is not equal to "expr," a pulse appears on line 774 which is used to turn on monostable multivibrator B-34.

The B-28 pulse is applied to OR-circuit 588, the output of OR-circuit 588 enabling gate 590 to gate the contents of register N to register R0 (FIG. 26B). The B-28 pulse is applied to OR-circuit 592, the output of OR-circuit 592 enabling gate 594 to gate "UP" which is contained in register 596 to the left-hand byte of register R1 (FIG. 26B). The B-28 pulse is applied to OR-circuit 598, the output of OR-circuit 598 enabling gate 700 to gate u which is in register 702 to the left-hand byte of register R2 (FIG. 26B). The B-28 pulse is applied to OR-circuit 726, the output of OR-circuit 726 enabling gate 728 to gate b which is in register 730 to the left-hand byte of register R3 (FIG. 26B). The B-28 pulse is applied to OR-circuit 732, the output of OR-circuit 732 enabling gate 734 to gate the four right-hand bytes of register M to the four right-hand bytes of register R3 (FIG. 26B).

The B-29 pulse is applied to OR-circuit 548, the output of OR-circuit 548 appearing on line 302 to initiate a "dump to tablet" operation (FIG. 26C).

The B-30 pulse is applied to gate 776 to test for the state of flip-flop 488. If the test finds that flip-flop 488 is in its "1" state, a pulse appears on line 778 which is used to turn on monostable multivibrator B-31. However, if the test finds that flip-flop 488 is in its "0" state, a pulse appears on line 780 which is used to turn on monostable multivibrator B-32. Monostable multivibrator B-31 is used for delay only and returns the clock to B-30.

The B-32 pulse is applied to gate 744 to gate the four right-hand bytes of register N to tree address register 292 (FIG. 26E).

The B-33 pulse is applied to gate 750 to gate the number "01" which is contained in the two-bit register 756 to cable 296 (FIG. 26E). The B-33 pulse is applied to OR-circuit 746, the output of OR-circuit 746 appearing on line 294 (FIG. 26E). The B-33 pulse is applied to OR-circuit 752, the output of OR-circuit 752 enabling gate 754 to gate the information on cable 308 from tree address register 292 to the four right-hand bytes of register RO (FIG. 26B). The B-33 pulse is applied to OR-circuit 758, the output of OR-circuit 758 enabling gate 760 to gate the contents of register B to register R1 (FIG. 26B). The B-33 pulse is applied to gate 777 in order to gate "F7" which is in register 779 to the left-hand byte of register R2 (FIG. 26B). The B-33 pulse is applied to OR-circuit 766, the output of OR-circuit 766 enabling gate 768 to gate the four right-hand bytes of register M to the four right-hand bytes of register R2 (FIG. 26E). The B-33 pulse is applied to OR-circuit 727, the output of OR-circuit 727 enabling gate 729 to gate b which is in register 731 to the left-hand byte of register R3 (FIG. 26D).

The B-34 pulse is applied to OR-circuit 588, the output of OR-circuit 588 enabling gate 590 to gate the contents of register N to register RO (FIG. 26B). The B-34 pulse is applied to OR-circuit 592, the output of OR-circuit 592 enabling gate 594 to gate "UP" which is in register 596 to the left-hand byte of register R1 (FIG. 26B). The B-34 pulse is applied to OR-circuit 598, the output of OR-circuit 598 enabling gate 700 to gate u which is in register 702 to the left-hand byte of register R2 (FIG. 26B). The B-34 pulse is also applied to gate 781 to gate the contents of register M to register R3 (FIG. 26B).

UP UNIT

For the description of the UP unit, reference is made to FIGS. 29A-29G, taken together as in FIG. 29. In addition, FIG. 30 shows the details of the analyzer register for the UP unit and FIGS. 31A-31C taken together as in FIG. 31 form a diagram of the UP clock. The flow chart depicting the operation of the UP unit is formed by FIGS. 49A-49D taken together as in FIG. 49.

The UP unit is normally in the "acceptance state." Flip-flop 802 is normally in its "1" state (FIG. 29C). The flip-flops 276, 284, 804, 806, and 808 are initially in their "0" states (FIG. 29C). The flip-flops 288, 290, 810, and 812 are initially in their "0" states (FIG. 29F).

With flip-flop 802 in its "1" state and flip-flop 808 in its "0" state, an AND-circuit 814 is enabled and the first M-pulse is operative to set flip-flop 808 to its "1" state whereby line 816 is rendered active (FIG. 29C). The output on line 816 is applied to OR-circuit 818 (FIG. 29A) to provide a "read" operation from the associative memory control. The output of OR-circuit 818 also enables an AND-circuit 865 to permit the CB-2 pulse to associate on the vacancy bit. The output on line 816 is also applied to an OR-circuit 820, the consequent output of OR-circuit 820 enabling gate 830 to permit the reading of a word from the associative memory plane to the R-register when a match occurs (FIG. 29A). When in the "acceptance state," the UP unit associates on the designator "UP" which is contained in a register 828 (FIG. 29A). Because line 822 is active, an AND-circuit 824 is enabled at CB-2 time to gate the designator contained in register 828 to the association circuits in the associative memory plane. When a match occurs, the word in the associative memory plane is read into register R and a "read complete" signal appears on line 832 whereby AND-circuit 834 is enabled to produce an output on line 800, the latter output starting the U-clock. The U-clock effects the microprogram for the UP unit.

The output on line 800 turns on the U-1 monostable multivibrator. The pulse on line 832 (FIG. 29A) is also operative to reset flip-flop 802 to its "0" state and is applied to a delay unit 836, the output of delay unit 836 resetting flip-flop 808 to its "0" state. The U-1 pulse is applied to gate 838 to gate the contents of register R to register W (FIG. 29D). The U-1 pulse is also applied to OR-circuit 840, the output of OR-circuit 840 enabling a gate 842 to gate the four right-hand bytes of register RO to the tree address register 268 (FIG. 29D). When monostable multivibrator U-1 goes off, the monostable multivibrator U-2 is turned on.

The U-2 pulse is applied to gate 844 to test for the condition of the line 272 (FIG. 29G). If line 272 is active, a pulse appears on line 848 which is used to turn on the monostable multivibrator U-8. However, if the test finds that line 272 is not active, a pulse appears on a line 846 which is used to turn on the monostable multivibrator U-4.

The U-4 pulse is applied to OR-circuit 851, the output of OR-circuit 851 appearing on line 274 to set flip-flop 276 to its "1" state thereby initiating a "dump to tablet" operation (FIG. 29C). With flip-flop 276 in its "1" state and flip-flop 804 in its "0" state, an AND-circuit 853 is enabled and the first M-pulse is operative to set flip-flop 804 to its "1" state. With flip-flop 804 in its "1" state, a line 854 is rendered active, such activation branching to lines 856 and 858 (FIG. 29A). Line 856 is used to effect a "write" operation for the associative memory controls. Line 858 enables gate 860 whereby the contents of register R are gated to the associative memory plane. A branch circuit extends from line 856 through line 862 and AND-circuit 864. At CA-2, time, AND-circuit 864 is effective to associate on the vacancy bit in the associative memory plane. When a match occurs, the contents of register R are read into the vacant spot in the associative memory plane and a "write complete" signal appears on line 866. The signal on line 866 is used to reset flip-flop 276 to its "0" state (FIG. 29C) and is also applied as an input to delay unit 868, the output of delay unit 868 resetting flip-flop 804 to its "0" state. When monostable multivibrator U-4 goes off, the monostable multivibrator U-5 is turned on.

The U-5 pulse is applied to gate 870 to test for the state of flip-flop 276. If the test finds that flip-flop 276 is in its "1" state, a pulse appears on a line 872 which is used to turn on the monostable multivibrator U-6 (FIG. 29C). However, if the test finds that flip-flop 276 is in its "0" state, a pulse appears on line 874 which is used to turn on the monostable multivibrator U-7. Monostable multivibrator U-6 is used for delay only and returns the clock to U-5.

The U-7 pulse is applied to OR-circuit 876, the output of OR-circuit 876 appearing on line 278 (FIG. 29C) to set flip-flop 802 to its "1" state. The operation of the unit, when it is in its "acceptance state," is as has been previously described hereinabove.

The U-8 pulse is applied to gate 878 to gate the contents of register R0 to register N (FIG. 23D). The U-8 pulse is applied to OR-circuit 840, the output of OR-circuit 840 enabling gate 842 to gate the four right-hand bytes of register R0 to tree address register 268 (FIG. 23D). When monostable multivibrator U-8 goes off, monostable multivibrator U-9 is turned on.

The U-9 pulse is applied to OR-circuit 880, the output of OR-circuit 880 appearing on line 270 which is an input to tree address register 268 (FIG. 29G). The U-9 pulse is applied to gate 882 to gate the number "00" which is contained in register 884 to cable 280 (FIG. 29B). The U-9 pulse is also applied to gate 886 in order to gate the information on cable 282 to the four right-hand bytes of register R0 (FIG. 29C). When monostable multivibrator U-9 goes off, the monostable multivibrator U-10 is turned on.

The U-10 pulse is used to set flip-flop 284 to its "1" state thereby initiating a "tablet match R0" operation (FIG. 29C). With flip-flop 284 in its "1" state and flip-flop 806 in its "0" state, an AND-circuit is enabled and the first M-pulse is operative to set flip-flop 806 to its "1" state. With flip-flop 806 in its "1" state, a line 890 is rendered active and is applied to OR-circuit 818, the output of OR-circuit 818 providing a "read" operation for the associative memory controls. The output on line 890 is also applied to an OR-circuit 820, the output of OR-circuit 820 enabling gate 830 whereby, when a match occurs in the associative memory plane, the word can be read into register R (FIG. 29A). A branch circuit extends from line 890 through a line 892 to an AND-circuit 894. Consequently, at CB-2 time, AND-circuit 894 produces an output which enables gate 896 to gate the contents of register R0 to the association circuits. When a match occurs in the associative memory plane, a "read complete" signal appears on line 832 which is used to reset flip-flop 284 to its "0" state (FIG. 29C). It is to be noted that the same signal is applied as an input to delay circuit 898, the output of delay circuit 898 resetting flip-flop 806 to its "0" state. When monostable multivibrator U-10 goes off, the monostable multivibrator U-11 goes on.

The U-11 pulse is employed to test for the completion of the "tablet match R0" operation. Thus, the U-11 pulse is applied to gate 900 to test for the state of flip-flop 284 (FIG. 29C). If the test finds that flip-flop 384 is in its "1" state, a pulse appears on a line 902, which is used to turn on the monostable multivibrator U-12. Monostable multivibrator U-12 is used for delay only and returns the clock to U-11. However, if the test finds that flip-flop 284 is in its "0" state, a pulse appears on a line 904 which is used to turn on a monostable multivibrator U-13.

It is to be noted that the decoder 906 is employed to decode the left-hand byte or designator field of register R2 (FIG. 29E).

The U-13 pulse is applied to gate 908. If the designator field of register R1 is not equal to "00," a pulse appears on a line 910 which is used to turn on the monostable multivibrator U-14. However, if the designator field of register R1 is equal to "00, " a pulse appears on line 912 and is used to turn on monostable multivibrator U-53.

The decoder 914 is employed to decoder the designator field to register R1 (FIG. 29E). The U-14 pulse is applied to a gate 916 in order to test the designator field of register R1. If this designator field is not equal to ε, a pulse appears on a line 918 which is used to turn on the monostable multivibrator U-15. However, if the designator field of register R1 is equal to ε, a pulse appears on a line 920 which is used to turn on a monostable multivibrator U-59.

The U-15 pulse which is produced when line 918 is rendered active, is applied to OR-circuit 922, the output of OR-circuit 922 enabling a gate 924 to gate the four right-hand bytes of register N to tree address register 268 (FIG. 29D). When monostable multivibrator U-15 goes off, the monostable multivibrator U-16 is turned on.

The decoder 286 decodes the rightmost nonzero digit that exists in tree address register 268 (FIG. 29G). The pulse U-16 is applied to gate 926 to test the rightmost nonzero digit in tree address register 268. If this test finds that the digit is a "2," a pulse appears on a line 928 which is used to turn on the monostable multivibrator U-18. If, however, the test finds that the digit is not a "2," a pulse appears on a line 930 which is used to turn on the monostable multivibrator U-78.

The U-18 pulse is applied to a gate 940 to test the designator field of register D. If the test finds that this field is not equal to "expra," a pulse appears on a line 942 which is used to turn on monostable multivibrator U-19. However, if the field is equal to "expr," the pulse appears on a line 944 which is used to turn on monostable multivibrator U-34.

The U-19 pulse is applied to OR-circuit 946, the output of OR-circuit 946 enabling gate 948 to gate the contents of register D to register R2 (FIG. 29B). When monostable multivibrator U-19 goes off, the monostable multivibrator U-20 goes on.

The U-20 pulse is applied to OR-circuit 850, the output of OR-circuit 850 activating line 274 which sets flip-flop 296 to its "1" state thereby initiating a "dump to tablet" operation (FIG. 29C). When monostable multivibrator U-20 goes off, the monostable multivibrator U-21 goes on.

The U-21 pulse is applied to a gate 950 to test for the state of flip-flop 276 (FIG. 29C). If the test finds flip-flop 276 is in its "1" state, a pulse appears on a line 952 which is used to turn on monostable multivibrator U-22. Monostable multivibrator U-22 is used for delay only and returns the clock to U-21. However, if the test finds that flip-flop 276 is in its "0" state, a pulse appears on line 954, which is used to turn on a monostable multivibrator U-23.

The U-23 pulse is applied to a gate 956 in order to gate the contents of register R0 to register B (FIG. 23D). When monostable multivibrator U-23 goes off, the monostable multivibrator U-24 is turned on.

The U-24 pulse is applied to gate 958 to gate the contents of register B to register R3 (FIG. 29D). When monostable multivibrator U-24 goes off, the monostable multivibrator U-25 goes on.

The U-25 pulse is applied to OR-circuit 960, the output of OR-circuit 960 setting flip-flop 288 to "1" state to thereby initiate the "tablet match R3" operation. With flip-flop 288 in its "1" state and flip-flop 812 in its "0" state, an AND-circuit 962 is enabled and the first M-pulse is operative to set flip-flop 812 to its "1" state, thereby activating a line 964. Line 964 is applied to an OR-circuit 818, the output of OR-circuit 818 consequently providing a "read" signal for the associative memory controls. Line 964 is also applied to OR-circuit 820, the consequent output of OR-circuit 820 enabling gate 830 to gate the matching word in the associative memory plane to register R (FIG. 29F). Line 964 branches to a line 966 which is applied as an input to AND-circuit 968, whereby AND-circuit 968 is enabled at CB-2 time, the output of AND-circuit 968 thereby enabling the gate 970 to gate the contents of register R3 to the associative memory circuits. When a match occurs, a "read complete" signal appears on line 832 which branches to line 972 to reset flip-flop 288 to its "0" state. Line 972 is also applied as an input to delay circuit 974, the output of delay circuit 974 being employed to reset flip-flop 812 to its "0" state (FIG. 29F). When monostable multivibrator U-25 goes off, the monostable multivibrator U-26 is turned on.

The U-26 pulse is employed to test for the completion of the "tablet match R3" operation. The U-26 pulse is applied to gate 976 to test for the state of flip-flop 288 (FIG. 29F). If the test finds that flip-flop 288 is in its "1" state, line 978 is rendered active to turn on monostable multivibrator U-27. Monostable multivibrator U-27 is used for delay only and returns the clock to U-26. However, if the test finds that flip-flop 288 is in its "0" state, the pulse appears on line 980 and is employed to turn on the monostable multivibrator U-28.

The U-28 pulse is applied to gate 982 to gate "UP" which is in register 828 to the designator field of register R1 (FIG. 29B). The U-28 pulse is applied to gate 984 to gate u which is in register 986 to the designator field of register R2 (FIG. 29B). The U-28 pulse is applied to an OR-circuit 988, the output of OR-circuit 988 enabling a gate 990 to gate the contents of register D to register R3 (FIG. 29D). The U-28 pulse is also applied to an OR-circuit 992 to start the Timer 994 (FIG. 29F). When monostable multivibrator U-28 goes off, the monostable multivibrator U-29 goes on.

The U-29 pulse is applied to an OR-circuit 850, the consequent output of OR-circuit 850 appearing on line 274 to set flip-flop 276 to its "1" state to thereby initiate a "dump to tablet" operation (FIG. 29C). When monostable multivibrator U-29 goes off, a monostable multivibrator U-30 is turned on.

The U-30 pulse tests for the completion of the "dump to tablet" operation. Thus, the U-30 pulse is applied to a gate 996 to test for the state of flip-flop 276 (FIG. 29C). If the test finds that flip-flop 276 is in its "1" state, a pulse appears on a line 998 which is used to turn on the monostable multivibrator U-31. Monostable multivibrator U-31 is used for delay only and returns the clock to U-30. However, if the test finds that flip-flop 276 is in its "0" state, a pulse appears on a line 1000 which is used to turn on the monostable multivibrator U-32.

The U-32 pulse is applied to a gate 1002 to test the Timer 994 (FIG. 29F). If there is time remaining, a pulse appears on a line 1004 which is used to turn on monostable multivibrator U-24. If there is no time remaining, a pulse will appear on line 1006 which is used to turn on the monostable multivibrator U-33.

The U-33 pulse is applied to OR-Circuit 876, the output of OR-circuit 876 activating line 278 to set flip-flop 802 to its "1" state (FIG. 29C). This places the system in the "acceptance state."

The U-34 pulse is applied to OR-circuit 1008, the output of OR-circuit 1008 enabling a gate 1010 to gate "expr" which is contained in register 1012 to the designator field of register R2 (FIG. 29B). When monostable multivibrator U-34 goes off, the monostable multivibrator U-35 is turned on.

The U-35 pulse is applied to OR-circuit 850, the output of OR-circuit 850 activating line 274 to set flip-flop to its "1" state (FIG. 29C). The latter action initiates a "dump to tablet" operation. When monostable multivibrator U-35 goes off, the monostable multivibrator U-36 is turned on.

The U-36 pulse tests for the completion of the "dump to tablet" operation. Thus, U-36 pulse is applied to gate 1014 to test for the state of flip-flop 276 (FIG. 29C). If the test finds that flip-flop 276 is in its "1" state, a pulse appears on line 1016 which is used to turn on monostable multivibrator U-37. Monostable multivibrator U-37 is used for delay only and returns the clock to U-36. However, if the test finds that flip-flop 276 is in its "0" state, a pulse appears on a line 1018 which is used to turn on the monostable multivibrator U-38.

The U-38 pulse is applied to a gate 1020 to gate the contents of register R0 to register R3, (FIG. 29B). When monostable multivibrator U-38 goes off, the monostable multivibrator U-39 is turned on.

The U-39 pulse is applied to OR-circuit 960 to set flip-flop 288 to its "1" state to thereby initiate a "tablet match R3" operation (FIG. 29F). When monostable multivibrator U-39 goes off, the monostable multivibrator U-40 is turned on.

The pulse U-40 tests for completion of the "tablet match R3" operation. Thus, the U-40 pulse is applied to gate 1022 to test for the state of flip-flop 288 (FIG. 29F). If this test finds that flip-flop 288 is in its "1" state, a pulse appears on a line 1024 which is used to turn on the monostable multivibrator U-41. Monostable multivibrator U-41 is used for delay only and returns the clock to U-40. However, if the test finds that flip-flop 288 is in its "0" state, a pulse appears on a line 1026 which is used to turn on the monostable multivibrator U-42.

The U-42 pulse is applied to a gate 1028 to gate "F7" which is in a register 1030 to the designator field of register R2 (FIG. 29B). The U-42 pulse is also applied to OR-circuit 992, the output of OR-circuit 992 starting Timer 994 (FIG. 29F). When monostable multivibrator U-42 goes off, the monostable multivibrator U-43 is turned on.

The U-43 pulse is applied to OR-circuit 850, the output of OR-circuit 850 activating wire 274 to set flip-flop 276 to its "1" state (FIG. 29C). This latter action initiates a "dump to tablet" operation. When monostable multivibrator U-43 goes off, the monostable multivibrator U-44 is turned on.

The U-44 pulse tests for the completion of the "dump to tablet" operation. Thus, the U-44 pulse is applied to a gate 1032 to test for the state of flip-flop 276 (FIG. 29C). If the test finds that flip-flop 276 is in its "1" state, the pulse appears on a line 1034 which is used to turn on the monostable multivibrator U-45. Monostable multivibrator U-45 is used for delay only and returns the clock to U-44. If, however, the test finds that flip-flop 276 is in its "0" state, a pulse appears on a line 1036 which is used to turn on monostable multivibrator U-46.

The U-46 pulse is applied to gate 1038 to test Timer 994 (FIG. 29F). If there is time remaining, a pulse appears on a line 1040 which is used to turn on a monostable multivibrator U-39. However, if there is no time remaining, a pulse appears on a line 1042 which is used to turn on the monostable multivibrator U-48.

The U-48 pulse is applied to a gate 1050 to gate the contents of register N to register R0 (FIG. 29B). The U-48 pulse is applied to OR-circuit 922, the output of OR-circuit 922 enabling gate 924 to gate the four right-hand bytes of register N to tree address register 268 (FIG. 29B). The U-48 pulse is applied to OR-circuit 992 to start Timer 994 (FIG. 29F). When monostable multivibrator U-48 goes off, the monostable multivibrator U-49 is turned on.

The U-49 pulse is used to set flip-flop 290 to its "1" state (FIG. 29F). This action initiates a "tablet match *R0" operation (FIG. 29F). With flip-flop 290 in its "1" state and flip-flop 810 in its "0" state, an AND-circuit 1052 is enabled and the first M-pulse is operative to set flip-flop 810 to its "1" state (FIG. 29F), whereby the line 1054 is rendered active. The output on line 1054 is applied to OR-circuit 818, the consequent output of OR-circuit 818 providing a "read" signal to the associative memory controls (FIG. 29A). The output on line 1054 is also applied to OR-circuit 820, the output of OR-circuit enabling gate 830 whereby, when a match occurs in the associative memory plane, the word which is selected can be gated to register R. A line 1056 which branches from line 1054 is applied as an input to tree address register 286 (FIG. 29F). It is to be noted in FIG. 30 that the signal on line 1056 is operative to gate all nonzero digits to a cable 1058.

The signals on cable 1058 are applied to a gate 1060 (FIG. 29G). The designator field of register R0 is also applied to a gate 1060 through a cable 1062. A branch circuit extends from line 1054 through a line 1064 to an AND-circuit 1066. A CB-2 time, an AND-circuit 1066 is consequently enabled and its output enables gate 1060 to gate the information on cables 1062 and 1058 to the association circuits. With this arrangement, an association is made on the designator field of register R0 and the nonzero digits which are in tree address register 268. When a match is found, a signal appears on "read complete" line 832, a line 972 branches from line 832 and is used to reset flip-flop 290 to its "0" state (FIG. 29F). The same signal is applied to delay circuit 1068, the output of delay circuit 1068 being employed to reset flip-flop 810 to its "0" state (FIG. 29F). When monostable multivibrator U-49 goes off, the monostable multivibrator U-50 is turned on.

The clock pulse U-50 is employed to test for the completion of the immediately herein above described operation. Thus, the U-50 pulse is applied to gate 1070 (FIG. 29F) to test for the state of flip-flop 290. If the test finds that flip-flop 290 is in its "1" state, a pulse appears on a line 1072 which is used to turn on the monostable multivibrator U-51, monostable multivibrator U-51 being used for delay only and returning the clock to U-50. However, if the test finds that flip-flop 290 is in its "0" state, a pulse appears on line 1074 which is employed to turn on the monostable multivibrator U-52.

The U-52 pulse is applied to a gate 1076 to test Timer 994 (FIG. 29F). If the test shows that there is time remaining, a pulse appears on a line 1078 which is used to turn on monostable multivibrator U-49. However, if the test shows that there is no time remaining, a pulse appears on a line 1080 which is used to turn on monostable multivibrator U-33.

The U-53 pulse is employed to test the designator field of register D. Thus, the U-53 pulse is applied to a gate 1082 (FIG. 29E). If the test shows that the designator field of register D is not equal to "expr," a pulse appears on a line 1084 which is used to turn on the monostable multivibrator U-54. However, if the test shows that the designator field of register D is equal to "expr," a pulse appears on a line 1086 which is used to turn on a monostable multivibrator U-67.

The U-54 pulse is used to test the designator field of register D. Thus, the U-54 pulse is applied to gate 1088 (FIG. 29E). If the test finds that the designator field of register D is not equal to V a pulse appears on a line 1090 which is used to turn on monostable multivibrator U-55. However, if the test shows that the designator field of register D is equal to v, a pulse appears on a line 1092 which is used to turn on the monostable multivibrator U-63.

The U-55 pulse is used to test the designator field of register D and also the four right-hand bytes of register D. Accordingly, the U-55 pulse is applied to gate 1094 (FIG. 29E). If the test shows that the designator byte of register D is equal to TRUTH and the four right-hand bytes of register D are all ones, a pulse appears on a line 1096 which is used to turn on the monostable multivibrator U-56. However, if the above-mentioned conditions do not obtain, a pulse appears on a line 1098 which is used to turn on the monostable multivibrator U-57.

The U-56 pulse is applied to a gate 2000 to gate "F2" which is contained in a register 2002 to the designator byte of register R2 (FIG. 29B).

The U-57 pulse is applied to a gate 2004 to test designator byte and the four right-hand bytes of register D (FIG. 29E). If the test finds that the designator field of register D is equal to TRUTH and the four right-hand bytes of register D are all zeros, a pulse appears on a line 2006 which is used to turn on the monostable multivibrator U-58. If these conditions do not obtain, the pulse appears on a line 2008 which is used to turn on monostable multivibrator U-2.

The U-58 pulse is applied to gate 2010 to gate "F1" which is contained in a register 2012 to the designator field of register R2 (FIG. 29B).

The U-59 pulse is applied to a gate 2014 to test the designator field of register D (FIG. 29E). If the test finds that this field is equal to "expr," a pulse appears on a line 2016 which is used to turn on the monostable multivibrator U-64. However, if the test finds that this field is not equal to "expr," a pulse appears on a line 2018 which is used to turn on the monostable multivibrator U-60.

The U-60 pulse is applied to a gate 2020 to test the rightmost nonzero digit in tree address register 268 (FIG. 29G). If the test finds that this digit is a "1," a pulse appears on a line 2022 which is used to turn on the monostable multivibrator U-61. However, if the test shows that this digit is a "2" a pulse appears on a line 2024 which is used to turn on the monostable multivibrator U-62. If the test finds that the digit is a "3," a pulse appears on a line 2026 which is used to turn on the monostable multivibrator U-63.

The U-61 pulse is applied to gate 2028 to gate the contents of register D to register R1 (FIG. 29B).

The U-62 pulse is applied to an OR-circuit 946, the output of OR-circuit 946 enabling gate 948 to gate the contents of register D to register R2 (FIG. 29B).

The U-63 pulse is applied to OR-circuit 988, the output of OR-circuit 988 enabling gate 990 to gate the contents of register D to register R3 (FIG. 29D).

The U-64 pulse is applied to the gate 203 to test the right-hand nonzero digit in tree address register 268 (FIG. 29G). If the test finds that this digit is a "1," a pulse appears on a line 2032 which is used to turn on the monostable multivibrator U-65. However, if the test finds that this digit is a "2," a pulse appears on a line 2034 which is used to turn on the monostable multivibrator U-66. If the test finds that the digit is a "3," a pulse appears on a line 2036 which is used to turn on the monostable multivibrator U-67.

The U-65 pulse is applied to a gate 2038 to gate "expr" which is in register 1012 to the designator field of register R1 (FIG. 29B).

The U-66 pulse is applied to OR-circuit 1008, the output of OR-circuit 1008 enabling gate 1010 to gate "expr" which is in register 1012 to the designator field of register R2 (FIG. 29B).

The U-67 pulse is applied to a gate 2040 to gate "expr" which is in register 1012 to the designator field of register R3 (FIG. 29B). When monostable multivibrator U-67 goes off, the monostable multivibrator U-68 is turned on.

The U-68 pulse is applied to OR-circuit 850 The output of OR-circuit 850 appearing on line 274 to set flip-flop 276 to its "1" state to thereby initiate a "dump to tablet" operation (FIG. 29C). When monostable multivibrator U-68 goes off, the monostable multivibrator U-69 is turned on.

The U-69 pulse is used to test for completion of the "dump to tablet" operation. Thus, the U-69 pulse is applied to gate 2042 to test for the state of flip-flop 276 (FIG. 29C). If the test finds that flip-flop 276 is in its "1" state, a pulse appears on a line 2044 which is used to turn on the monostable multivibrator U-70, monostable multivibrator U-70 being used for delay only and returning the clock to U-69. However, if the tests find that flip-flop 276 is in its "0" state, a pulse appears on a line 2046 which is used to turn on the monostable multivibrator U-71.

The U-71 pulse is applied to a gate 2048 to test the designator byte of register R1. If this test finds that the designator byte of register R1 is equal to b, a pulse appears on a line 2050 which is used to turn on the monostable multivibrator U-7. However, if the test shows that the designator byte is not equal to b, a pulse appears on line 2052 which is used to turn on monostable multivibrator U-72.

The U-72 pulse is applied to a gate 2054 to test the designator byte of register R2 (FIG. 29E). If this test ascertains that the designator byte of register R2 is equal to b, a pulse appears on a line 2056, which is used to turn on the monostable multivibrator U-7. However, if the test finds that this designator byte is not equal to b, a pulse appears on a line 2058 which is used to turn on the monostable multivibrator U-73.

The U-73 pulse is applied to a gate 2060 to test the designator byte of register R3 (FIG. 29E). If the test finds that the designator byte of register R3 is equal to b, a pulse appears on a line 2062 which is used to turn on the monostable multivibrator U-7. However, if the test finds that this designator byte is not equal to b, a pulse appears on a line 2064 which is used to turn on the monostable multivibrator U-74.

The

The U-74 pulse is applied to gate 2066 to test the designator byte of register R1 (FIG. 29E). If this test ascertains that the designator byte of register R1 is equal to "expr," a pulse appears on a line 2068 which is used to turn on the monostable multivibrator U-77. However, if the test finds that this byte is not equal to "expr," a pulse appears on a line 2070 which is used to turn on the monostable multivibrator U-75.

The U-75 pulse is applied to a gate 2072 to test the designator byte of register R2 (FIG. 29E). If this byte is equal to "expr," a pulse appears on a line 2074 which is used to turn on the monostable multivibrator U-77. However, if the test finds that this byte is not equal to "expr," a pulse appears on a line 2076, which is turned on the monostable multivibrator U-76.

The U-76 pulse is applied to a gate 2078 to test the designator byte of register R3 (FIG. 29E). If the test finds that this byte is equal to "expr," a pulse appears on a line 2080 which is used to turn on the monostable multivibrator U-77. However, if the test finds that the byte is not equal to "expr," a pulse appears on a line 2082 which is used to turn on monostable multivibrator U-7.

The U-77 pulse is applied to a gate 2084 to gate "expr" which is held in register 1012 to the designator field of register D (FIG. 29D).

The U-78 pulse is applied to OR-circuit 850, the output of OR-circuit 850 appearing on a line 274 to set flip-flop 276 to its "1" state to thereby initiate a "dump to tablet" operation (FIG. 29C). When monostable multivibrator U-78 goes off, the monostable multivibrator U-79 is turned on.

The U-79 pulse is used to test for the completion of the "dump to tablet" operation. Thus, the U-79 pulse is applied to a gate 2086 to test for the state of flip-flop 276 (FIG. 29C). If the test finds that flip-flop 276 is in its "1" state, a pulse appears on a line 2088 which is used to turn on the monostable multivibrator U-80, monostable multivibrator U-80 being used for delay only and returning the clock to U-79. However, if the test finds that flip-flop 276 is in its "0" state, a pulse appears on a line 2090 which is used to turn on monostable multivibrator U-2.

ARITHMETIC OR LOGICAL UNIT

For a description of this unit, reference is made to FIG. 50 which is the flow chart of this unit's operation. In general, the operation of the arithmetic or logical unit is similar to that of the operation of the store unit, node assembler unit, the beta unit and the UP unit. Normally, it is in its "acceptance state" and continually looks for an input message. Such looking is effected by its associating on the left-hand four bits of the designator byte of register R2. When a match is obtained on these four bits, the word in the associative memory pane is read to register R. The right-hand four bits of the designator byte of register R2 are next decoded to determine the type of arithmetic or logical operation that should be performed. If the operation is an arithmetic operation, the designator byte of register R1 indicates whether the operation is a fixed-point or a floating-point operation. When the arithmetic operation is completed, the result is placed in the four right-hand bytes of register R3. The symbol "UP" is gated to the left-hand byte of register R1. The symbol u is gated to the left-hand byte of register R2. The designator byte of register R3 is set to either "fixed point" or "floating point" according to the operation just performed. The contents of register R are then dumped to the tablet and the unit returns to its "acceptance state." The operands for the arithmetic operation are contained in the four right-hand bytes of register R1 and the four right-hand bytes of register R3. In the case of a logical operation, the left-hand byte of register R2 would be decoded to indicate "equal," "less than," and "greater than." Thus, the three questions which might be asked of the logical unit are as follows:

1. Is the number contained in the four right-hand bytes of register R1 equal to the number contained in the four right-hand bytes of register R3?

2. Is the number contained in the four right-hand bytes of register R1 less than the number contained in the four right-hand bytes of register R3?

3. Is the number contained in the four right-hand bytes of register R1 greater than the number contained in the four right-hand bytes of register R3?

The logical unit would make this determination and then do the following. The designator TRUTH would be gated to the left-hand byte of register R3. If the result of the logical operation were to be true, the right-hand four bytes of register R3 would be replaced by all "ones." If the result of the logical operation would be false, the right-hand four bytes of register R3 would be replaced with all "zeros." The symbol "UP" would be gated to the left-hand byte of register R1. The symbol u would be gated to the left-hand byte of register R2. The contents of register R would next be dumped to the tablet and the unit would return to its "acceptance" state.

OUTPUT UNIT

The output unit's operation is set forth in the flow chart depicted in FIGS. 51A and 51B taken together as in FIG. 51. Since the various steps in this operation require computer functioning similar to that already hereinabove described in connection with the operation of the other units of the computer, no detailed description thereof is deemed necessary.

Briefly, the operation of the output is initiated by a "UP" message with as a node label the symbol , of course, denoting the empty string. Since no predecessor of can be computed, "UP" is changed to "print" by the UP unit and the message is dumped to the tablet.

The print unit looks for an accepts messages with the designator "print" in register R1. The print message contains in R3 either a constant which will be printed thereby terminating the process, or an "expr" code. In the latter situation, the tree is traversed to obtain a linear representation.

For each node, the order of traversal is as follows: Retrieve code; traverse first subtree of any retrieve node; traverse second subtree of any retrieve node; and traverse third subtree of any retrieve node.

As seen in FIGS. 51A and 51B, the flow chart contains two or more loops. The ε nodes are skipped in either direction Register K keeps track of the subtree being currently traversed.

The above-described computer permits many extensions. Thus, considering the difference in speeds of operation between backup store and the tablet, more than one node assembler could be employed to enable utilization of the tablet to its fullest extent which would consequently permit the simultaneous processing of several programs. Depending upon the structure of programs, computational speed could be controlled by adding more arithmetic and functional units without changes in the structure of the computer.

The computer can be described as comprising the tablet as the general communication device among the resources of the system. Input-output channels, backup store units, functional units, arithmetic units, program and node assembler comprise the resources of the system while the tablet performs the interlocking, sequencing, and communicating among the resources.

The computer provides, among many others, the following advantages, viz: It can make optimal use of large scale integration technology; it facilitates the use of the computer by a relatively high-level machine language; and it offers a way to large scale computation which can be achieved by increasing the tablet size and by adding more resources but without posing any serious control problems.