United States Patent 3638035

A permissible blasting machine employs a capacitive discharge circuit for electrically detonating an explosion in a hazardous environment. Protective circuitry prevents capacitor discharge until full charge is reached. After detonation, redundant circuitry dissipates any charge remaining in the circuit. A failure of the dissipating circuitry disables the discharge system.

Murphy, John N. (Pittsburgh, PA)
Bowser, Merle L. (Bethel Park, PA)
Application Number:
Publication Date:
Filing Date:
Primary Class:
Other Classes:
102/219, 361/249, 361/251
International Classes:
F42D1/05; H03K3/57; H03K17/292; (IPC1-7): F42D5/00
Field of Search:
102/7.2R 317
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US Patent References:

Primary Examiner:
Pellinen A. D.
We claim

1. An apparatus for applying an electrical charge across a pair of terminals and for removing the charge within a short, definite duration comprising:

2. An apparatus as claimed in claim 1, further comprising:

3. An apparatus as claimed in claim 1, further comprising:

4. An apparatus as claimed in claim 2, further comprising:

5. An apparatus as claimed in claim 1 in which:

6. An apparatus as claimed in claim 2 in which:

7. An apparatus as claimed in claim 3 in which:

8. An apparatus as claimed in claim 4 in which:


In underground mines an electrical charge is commonly used to detonate explosives. After a detonator ignites, a short time, which is a function of the delay period of the detonator, lapses before the explosion occurs. To prevent secondary explosions of gases and fine combustible particles, it is necessary to effectively quench the electrical charge within this short lapse between ignition and explosion. U.S. Bureau of Mines Schedule 16E requires that the voltage across the terminals of an electrical blasting machine be reduced to a level precluding accidental post firing ignition within 15 milliseconds after initial detonating contact is made. A device operating within the 15 millisecond limitation is classified as a permissible blasting machine.

Because of extreme hazards incident to underground blasting, operating safety is a primary consideration in the design and use of permissible blasting machines. Close scrutiny of new designs by the Bureau of Mines safeguards operators of permissible machines in proper working order operating within design limitations. Yet, hard use under unfavorable conditions often deteriorates the machines, resulting in unsafe operation. With prior permissible blasting machines there is no assurance that the charge quenching circuitry is functioning properly, and no indication of potentially unsafe operation. To overcome this defect of the prior art, this invention was made.


Our invention is a permissible blasting machine for safely detonating explosions in hazardous atmospheres. To provide the necessary electrical current for igniting a series circuit of up to 50 detonators, each having 16-foot long iron or copper legwires, a capacitive discharge circuit is used. Shortly after ignition, a primary shunt circuit provides a path for dissipating any voltage on the firing line or across the detonators within the required 15 millisecond period. As a backup, a second shunt circuit activates shortly afterward, again within the 15 millisecond period. If sufficient current passes through the secondary shunt due to a defect in the primary shunt, the entire blasting machine is automatically disabled.

One potential hazard in operating a blasting machine is the possibility of detonating only a fraction of the total number of detonators employed. With the high number of detonators our machine is capable of detonating, this possibility becomes extremely undesirable. A common cause of failure to initiate all detonators is the discharge of the energy storage capacitors before full charge is reached. To preclude this possibility, our invention employs a lockout circuit which prevents firing of the blasting machine until the capacitors are fully charged. These and other features of our invention result in a safe and efficient machine for underground blasting.

Therefore, one object of our invention is a blasting machine with redundant shunt circuits for removing a voltage from a load within a predictable period.

Another object of our invention is a blasting machine which is automatically disabled if an operating defect occurs.

Another object of our invention is a blasting machine in which firing is prevented until sufficient charge for complete detonation is available.

These and other objects of our invention are evident in this specification and drawing.


FIG. 1 is a schematic detonation circuit of a blasting machine.

FIG. 2 is a schematic timing circuit of a blasting machine.

FIG. 3 is a schematic SCR drive circuit of a blasting machine.


The detonating circuit 10 of a permissible blasting machine is shown in FIG. 1. To energize a series of electrical detonators, represented by a resistor R1 between terminals T1 and T2, an electrical current from a battery 12 first charges two series capacitors C1 and C2 in parallel with R1. During charging, current flow through the detonators is prevented by a silicon-controlled rectifier SCR1 in series with R1. When the detonating circuit is fired, a gate signal permits SCR1 to conduct current, enabling C1 and C2 to discharge through the detonator circuit R1 with sufficient energy for detonating an explosion.

To produce the high voltage required for initiating detonators R1, battery 12, through a normally open charging switch SC is connected in series with the medium voltage inputs of a medium-to-high-voltage DC converter 14. High-voltage DC appearing at the converter output terminals is fed to capacitors C1 and C2 through a limiting resistor R2 and a buffer diode D1. Two large resistors R3 and R4, in parallel with C1 and C2 respectively, serve as bleeders and a voltage divider to improve capacitor charging performance.

In actual operation of detonating circuit 10, capacitors C1 and C2 are charged by closing charging switch SC. Discharge, or firing, is controlled by a lockout circuit incorporated in the detonator circuit. The lockout circuit prevents firing until C1 and C2 are fully charged, insuring adequate firing potential for detonators R1, and preventing hazardous misfires. Indirectly, through a timing circuit, a unijunction transistor Q1 in the lockout circuit controls the gate signal to SCR1. Four zener diodes Z1 -Z4 in series with a neon glow lamp NE1 are joined in parallel with series capacitors C1 and C2, with one diode Z4 between the glow lamp and the ground terminal of battery 14. Between the glow lamp and Z4, the emitter of unijunction transistor Q1 is connected through a normally open firing switch SF. When C1 and C2 are sufficiently charged, the neon glow lamp conducts, and voltage to trigger Q1 appears at SF. The neon glow lamp acts both as a lock-out to prevent firing with insufficient charge on the capacitors, and as a visual indicator that the circuit is ready to trigger.

Driving potential for transistor Q1 is derived from a low-voltage terminal VL between a resistor R5 and a zener diode Z5 in series with battery 12 and switch SC. The zener diode regulates the potential between VL and the battery ground to a stable level suitable for unijunction operation. Because switch SC must be closed to produce an output at VL, triggering of the unijunction is prevented unless charging potential appears across capacitors C1 and C2. This construction operates as an additional safeguard against misfiring of the detonator circuit.

To fire the detonator circuit, switch SC is first closed until lamp NE1 glows, indicating that firing potential has been reached across C1 and C2. Firing switch SF is then closed to trigger transistor Q1 and ultimately gate SCR1. With low-voltage terminal VL connected to one base lead, triggering of Q1 causes a signal to appear at the other base lead 16 and at an output terminal T3. A resistor R6 in parallel with a capacitor C3 carries this signal to ground and provides a time constant sufficient to prevent firing by spurious signals appearing at terminal T3. From terminal T3 the firing signal is fed to a timing circuit for controlling the gate signal input to SCR1 to regulate buildup and reduction of power consumption in R1.

U.S. Bureau of Mines Schedule 16E requires that the voltage across terminals T1 and T2 of the electrical blasting machine be reduced to a level precluding accidental post firing ignition within 15 milliseconds after initial detonating contact is made. Initial detonating contact occurs when, at a time t0, SCR1 receives a gating pulse from the timing circuit through a terminal T4. In response to the gate pulse, SCR1 conducts, discharging capacitors C1 and C2 through R1. Within 15 milliseconds after initiating the discharge, all voltage between terminals T1 and T2 must be removed. For this purpose a small primary shunt resistor R7, in parallel with R1, and also with C1 and C2, is used to provide a short time constant for discharging the capacitors.

Shortly after gating pulse t0 reaches SCR1, a second gating pulse t1 is transmitted from the timing circuit, through a terminal T5, to a second silicon-controlled rectifier SCR2 which completes the primary shunt circuit in series with R7. After detonators R1 have fired, the gating pulse t1 opens SCR2 to rapidly dissipate through R7 any charge remaining across C1 and C2. A diode D2 across terminals T1 and T2 provides a circuit path for dissipating any residual inductive or capacitive potential remaining across T1 and T2. Within a short time the entire charge on capacitors C1 and C2 is safely dissipated.

Safe operation of the electrical blasting machine requires that the potential across capacitors C1 and C2 be dissipated without fail shortly after initiating capacitor discharge. With R7 and SCR2 as the only shunt path available for this purpose, any defect in these elements has potentially catastrophic consequences. To preclude this result, a secondary shunt path, including a resistor R8 in series with a silicon-controlled rectifier SCR3, is provided in parallel with R1 and SCR1 to act as a backup. Shortly after gating pulse t1 reaches SCR2 to shunt current through R7, a third gating pulse t2 passes from the timing circuit, through a terminal T6, to gate SCR3. Under normal conditions, little or no current flows through this path. But if the primary shunt circuit fails to operate, the secondary circuit reduces the voltage across terminals T1 and T2 within the required 15 millisecond period. To disable the charging circuit if the primary shunt fails to operate, a fuse F1 is connected between the primary and secondary shunts. If the primary shunt fails, dissipation of the capacitor charge in R8 causes sufficient current flow to blow F1, preventing capacitor recharge until the defect is corrected. In parallel with the fuse, a neon glow lamp NE2, in series with a large resistor R9, illuminates after the fuse blows to indicate the defective condition.

A timing circuit suitable for supplying to the detonator circuit the three precisely spaced signals t0 -t2 is shown in FIG. 2. At the left side of the timing circuit the firing signal from the unijunction transistor Q1 in the lockout circuit shown in FIG. 1 is input at terminal T3. From T3 the firing signal passes simultaneously to three independent time delay generators 18-22. Timing is generated by integrated circuit (IC) logic chips which respond to the trigger signal from the unijunction. From terminal T3 the trigger signal travels through a conductor 24 to generator 18, where it is input to a logic chip IC1. Upon receiving the signal, the logic chip initiates charging of a capacitor C4 in series between IC1 and a resistor R10. The free end of R10 is joined to low-voltage terminal VL, derived from FIG. 1, to bias a second logic chip IC2, connected by a conductor 26 between C4 and R10. When the voltage across C4 overcomes the bias, the voltage input at conductor 26 is transmitted by IC2 to a conductor 28. From output conductor 28 this voltage is fed forward to an integrated circuit amplifier IC3, and back to IC1 through a conductor 30. At IC1, the signal resets the timing generator. Amplifier IC3 provides isolation and signal gain, delivering a timing pulse t0, through a capacitor C5, to an output terminal T7.

In timing generators 20 and 22 additional logic chips are employed to provide variable time delay. To obviate unnecessary repetitious description, elements with corresponding functions in the three generators are similarly numbered. From terminal T3 the trigger signal travels through a conductor 32 to generator 20, where it is input to a logic chip IC4. Upon receiving the signal, the logic chip initiates charging of a capacitor C6 in series between IC4, a fixed resistor R11 and a variable resistor R12. The free end of R12 is joined to low-voltage terminal VL to bias a logic chip IC5, with inputs connected between C6 and R11, for operation in a manner similar to IC2 in generator 18. While the delay time of generator 18 is fixed, however, variable resistor R12 enables variation of the charging time constant of C6 so that the delay between receipt of the firing signal at IC4 and transmission of a pulse from IC5 through an output conductor 34 can be precisely regulated. From conductor 34 the output pulse of IC5 is fed back through a conductor 36 to reset IC4, and forward to an intermediate isolating logic chip IC6. At the output of IC6, a capacitor C7 in series with a grounded resistor R13 receives the signal for input, through a conductor 24 between C7 and R13, to a series of elements duplicating timing generator 18. Ultimately a control pulse arrives at a timing output terminal T8 at a time t1 shortly after the initial timing pulse t0. In a similar manner a third timing pulse t2 is produced at output terminal T9 in generator 22 shortly after pulse t1.

From terminals T7 -T9 in FIG. 2 the three timing pulses are fed to an SCR drive circuit shown in FIG. 3. Because SCR1 -SCR3, shown in FIG. 1, require a higher gate current than available at the timing circuit output, an intermediate gate drive stage 40 is required for raising each timing pulse to the required level. Three similar circuits, one for each timing pulse, are employed for this purpose. Corresponding circuit elements in each gate circuit are shown with similar reference numerals.

In gate drive stage 40 a medium driving voltage is input to a conductor 42 from a terminal VM connected to switch SC, as shown in FIGS. 1 and 3. Between conductor 42 and ground are connected a cutoff resistor R14 and a capacitor C8. Under steady-state conditions the voltage VM is stored on C8. Between R14 and C8 is connected the anode of a silicon-controlled rectifier SCR4. When a timing pulse, t0 for example, appears at the associated input terminal, T7 in this case, it is fed to the gate of SCR4 by a conductor 44. The timing pulse gates the SCR, causing current to flow from C8 through the SCR cathode to the appropriate input terminal in the detonator circuit, terminal T4 in the case of timing pulse t0. As C8 discharges the voltage across R14 rises, preventing continuous current flow through the SCR. Between the cathode of SCR4 and the detonator input terminal the gating current passes through a decoupling capacitor C9, and a diode D3 which prevents feedback between the individual SCRs in the gate drive and detonator circuits. A gate holdoff resistor R15 between the cathode and gate of SCR4 provides a gate to cathode current path while preventing spontaneous gating. Gate holdoff resistors R16 between the detonator circuit SCR gates and ground perform a similar function. A resistor R17, passing from between C9 and D3 to ground, dissipates residual voltage across D3 when the detonator gating pulse ceases. In this way the detonator gating pulses to SCR1 -SCR3 are held to a short predictable duration.

As is apparent in the above description, our invention enables safe and efficient blasting in hazardous atmospheres. To exemplify the safety features of the invention, the basic operation will now be summarized. First, switch SC is closed to charge energy storage capacitors C1 and C2. Until glow lamp NE1 illuminates, the lockout circuit prevents discharge so that the hazards of firing with insufficient voltage are avoided. When the capacitors are fully charged NE1 illuminates, indicating that the detonator circuit is prepared for firing, and also making voltage available at the firing switch SF. Firing switch SF is then closed. Then, only if charge switch SC remains closed, unijunction Q1 triggers, producing a firing signal at terminal T3 and simultaneously activating timing generators 18-22. In a short time a first-timing pulse t0 is transmitted from generator terminal T7 to gate SCR1 in the detonator circuit and cause discharge of C1 and C2 through the detonators R1. Shortly afterward, a second timing pulse t1 gates SCR2 to provide a primary shunt path around R1. Then, within the 15 millisecond allowable period, a third timing pulse gates SCR3 in the secondary shunt path around R1. If, for some reason, the primary shunt fails to operate, current flow through the secondary shunt blows fuse F1, disabling the detonator circuit and illuminating glow lamp NE2 to signal the defect.

Although construction of our invention is not limited to a particular circuit, the following values of circuit elements were used effectively in the preferred embodiment: --------------------------------------------------------------------------- SEMICONDUCTORS

Q1 2N492 SCR1 -SCR3 2N5205 SCR4 -SCR6 C106B1 D1 -D3 P5052D Z1 -Z3 1N3051B Z4 1N3016B Z5 1N704 IC3 1/2MC788 IC1 2 4 5 6 1/4-MC717 --------------------------------------------------------------------------- capacitors

c1,c2 240 μf., 450 v. DC C3 1 μf., 5v. DC C4,C6 1μf., 3v. DC C5 1μf., 20v. DC C7 3,300 pf., 50v. DC

resistors (in ohms)

R1 Indefinite R2 10K, 2 watt R3,R4 100K, 1 watt R5 430, 1 watt R6, R15 -R17 1K, 1/4watt R7, R8 10, 10 watt R9 2M, 1 watt R10 5K, 1/8watt R11 499, 1/8watt R12 1K, Bourns 3067P-1-103 R13 10K, 1/4watt R14 50K, 1/4watt --------------------------------------------------------------------------- MISCELLANEOUS

NE1 DIALCO 249-7840-1431-504 NE2 DIALCO 249-7840-1433-504 F1 1/8A 3AG SB B1 2 Eveready batteries 10/BH500T Converter Advance Power Supply G. 24v., DC to 1,000v., DC 100 ma. converter. __________________________________________________________________________

While our invention is described as a specific preferred embodiment, with specific circuit parameters given in addition, equivalent designs and elements are expected. For this reason, the scope of the invention is limited only by the following claims: