Title:
INFORMATION-ANNOUNCING SYSTEM
United States Patent 3632880


Abstract:
An electronic announcing system for announcing the time at predetermined intervals, e.g., 10 seconds, wherein a digital clock is utilized with an audio storage drum in conjunction with a phase state or mode selector and control logic so that an audio readout is gated from the audio storage device every so often to announce the correct time.



Inventors:
Goldschein, Gerald (Ossining, NY)
Goldman, Alan L. (Suffern, NY)
Application Number:
04/825104
Publication Date:
01/04/1972
Filing Date:
04/23/1969
Assignee:
COGNITRONICS CORP.
Primary Class:
Other Classes:
368/63, 369/22, 968/968
International Classes:
G04G13/00; H04M3/487; (IPC1-7): G11B19/06; H04M1/64
Field of Search:
179/6TA,6CO,1
View Patent Images:
US Patent References:
3409895TIME RECORDING SYSTEM1968-11-05Hayden
3300591Audio playback unit1967-01-24Gushue et al.
3296371Voice encoder1967-01-03Fox
3249919Securities quotation apparatus1966-05-03Scantlin
3237171Timing device1966-02-22Young



Foreign References:
AU257856A
Primary Examiner:
Konick, Bernard
Assistant Examiner:
Cardillo Jr., Raymond F.
Parent Case Data:


This application is a continuation-in-part of application Ser. No. 730,730, filed May 21, 1968, now abandoned for Audio Clock.
Claims:
1. A system for announcing time comprising:

2. The system of claim 1 further including:

3. The system of claim 1 further including:

4. The system of claim 3 wherein said synchronizing means includes:

5. The system of claim 1 further indicating:

6. The system of claim 5 wherein said binary coded decimal output includes:

7. The system of claim 6 wherein said binary coded decimal output includes:

8. The system of claim 1 in combination with a telephone system including a plurality of telephone lines wherein said announcing system includes:

9. The system of claim 8 wherein said coupling means includes:

10. The system of claim 9 wherein said coupling means further includes:

11. The system of claim 1 wherein said logic means includes:

12. The system of claim 11 wherein said logic means includes:

13. The system of claim 12 wherein said gating means includes:

14. The system of claim 1 wherein said time-determining means includes:

15. The system of claim 14 wherein said output signal providing means include:

16. The system of claim 15 further including:

17. The system of claim 15 wherein each of said counter means includes a

18. The system of claim 17 wherein said logic means is operatively associated with certain of said counter means to selectively enable the

19. The system of claim 18 wherein said logic means includes:

20. The system of claim 19 wherein said logic means includes:

21. The system of claim 20 wherein said logic means further includes:

22. A system for announcing information comprising:

23. The system of claim 22 wherein said logic includes:

24. The system of claim 23 wherein said logic means includes:

25. The system of claim 24 wherein said gating means includes:

Description:
BACKGROUND OF THE INVENTION

The present invention relates to audio announcing systems and more particularly to such a system which includes a digital clock, an audio storage device, and control logic associated therewith so that the correct time is announced at predetermined time intervals, e.g., 10 seconds.

The system disclosed herein can be used in many different environments and in conjunction with many types of equipment. For example, the system could be utilized to continuously read out the correct time or it could be used in conjunction with the telephone to provide the correct time upon request by dialing a specified number. This system also has a multitude of applications for military uses as well as for civilian uses and the embodiments herein disclosed announce the time every 10 seconds on a 12-hour or on a 24-hour basis. In addition, the system could be modified to announce temperature, and could be used as an audio alarm, paging equipment, test equipment, programming equipment or to provide any predetermined message.

In the field of time-announcing devices, it has been the general practice to employ electro mechanical devices to announce the time at periodic intervals. Although such devices have served the purpose, they have not proved entirely satisfactory under all conditions of service for the reasons that they are often expensive and unwieldy in size and weight.

SUMMARY OF THE INVENTION

The general purpose of this invention, therefore, is to provide an electronic time-announcing system which embraces all the advantages of similarly employed prior art announcing systems and possesses none of the aforedescribed disadvantages.

Accordingly, it is an object of the present invention to provide an electronic time-announcing system that is both inexpensive and compact.

Another object is to provide such a time-announcing system which utilizes basic logic components so as to provide for highly reliable operation.

Other objects and features of the invention will become apparent to those of ordinary skill in the art as the disclosure is made in the following description of a preferred embodiment of the invention as illustrated in the accompanying sheets of drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a preferred embodiment of the invention;

FIG. 2 illustrates a flow diagram or phase state diagram of the system;

FIG. 3 shows, in block diagram form, a portion of the system including primarily a portion of the digital clock;

FIGS. 4a and 4b are block diagrams of a portion of the system showing primarily the minutes logic;

FIG. 5 is a block diagram of a portion of the system primarily showing the tens of minutes logic;

FIG. 6 illustrates, in block diagram form, a portion of the system showing the hour logic;

FIG. 7a is a block diagram view of a portion of the phase state selector and associated logic;

FIG. 7b is a block diagram view of the remaining portion of the phase state selector and associated logic;

FIG. 8a shows, in block diagram form, some of the audio gating amplifiers located between the audio storage device and the selection or control logic;

FIG. 8b shows, in block diagram form, the remainder of gating amplifiers and the audio output located between the audio storage device and the control logic;

FIG. 9 illustrates, in schematic form, a manual set for the digital clock, the control logic and the phase state selector;

FIG. 10 shows, partly in schematic and partly in block diagram form, circuitry for coupling this system to a telephone system;

FIG. 11 illustrates another flow diagram or phase state diagram of the system;

FIGS. 12 and 12a show, in block diagram form, a portion of the system including primarily a slightly different embodiment of a portion of the digital clock;

FIGS. 13 and 13a are block diagrams of a portion of the 24-hour clock embodiment showing primarily the minutes logic;

FIG. 14 is a block diagram of a portion of the 24-hour clock embodiment primarily showing the tens of minutes logic;

FIGS. 15 and 15a illustrate, in block diagram form, a portion of the 24-hour clock embodiment showing the hour logic;

FIG. 16 is a block diagram of a portion of the 24-hour clock embodiment primarily showing the tens of hours logic;

FIGS. 17 and 17a block diagram views of the phase state selector and associated logic of the 24-hour clock embodiment;

FIGS. 18 and 18a show, in block diagram form, the audio gating amplifiers of the 24-hour clock embodiment located between the audio storage device and the selection or control logic;

FIG. 19 illustrates, in schematic form, a manual set for the digital clock, the control logic and the phase state selector in the 24-hour clock embodiment;

FIG. 20 shows, partly in schematic and partly in block diagram form, circuitry for synchronizing either the 12-hour or 24-hour clock embodiments with an external clock or synchronizing signal; and

FIGS. 21 and 21a show, in block diagram form, a binary coded decimal output which may be associated with either the 12-hour clock or 24-hour clock embodiments.

DESCRIPTION OF A PREFERRED EMBODIMENT

General Description

In the drawings, like reference characters designate like or corresponding parts throughout the several views.

FIG. 1 illustrates a preferred embodiment using a means for storing time information such as an audio information storage drum 21 similar to that disclosed in the U.S. Pat. to Gushue et al., No. 3,300,591 wherein the drum has its periphery covered with film containing a plurality of sound or information tracks 22. Associated with each of the tracks 22 is a readout head 23 which continually senses the audio message located on each of the respective tracks 22. A means for determining the time such as a digital clock 24, and a phase state or mode selector 26 are electrically associated with control or selection logic circuit 27. A series of gates 28 are associated between the control logic circuit 27 and the readout heads 23 wherein one gate is coupled to one readout head and wherein each of the gates is coupled to a common audio output.

In explaining the general operation of the system it will be helpful to refer to FIG. 2 wherein a flow diagram or phase state diagram is shown which indicates what words and in what sequence those words are read out from the system. Each of the blocks in FIG. 2 represents one step along the way followed by the system in reading out its message. If we assume that the drum 21 is maintained in a state of constant rotation, the time message read out will begin with a period of silence indicated by the box 29 or mode 0. This will be followed by the reading out of the words "At the" as represented in box 31. Next the word "tone" will be read out as indicated in box 32 followed by the words "the time" in box 33 and by the words "will be" in box 34. From here the system will change to box 35 or mode 13 and the digital clock 24 will be interrogated as to the correct hour, following which one number in the range of 1-12 will be read out. At this point the control logic circuit 27 must decide whether the correct time includes one-word minutes or two-word minutes. If the time includes two-word minutes, e.g., 23 minutes, the system will move to box 36 or mode 12 at which point the digital clock 24 will again be interrogated and the first word, e.g., "twenty," will be read out. Again, the clock 24 will be interrogated when the system moves to box 37 or mode 14 and the second word, e.g., "three," will be read out. If while in mode or phase state 13 and upon interrogation by the control logic circuit 27 of the clock 24, it had been determined that one-word minutes, e.g., 20 minutes, would indicate the correct time, the system would have moved directly from mode 13 to mode 14, at which time the one word, e.g., "twenty," would be read out. At this point the control logic circuit 27 will again interrogate the clock 24 to determine whether or not the correct time includes seconds or does not include seconds. In the event that the correct time does not include seconds the system will move from mode 14 to mode 15 in box 38 and the word "exactly" will be read out. From here the system will move to mode 11 in box 39, which will be a silent period and then on to mode 3 in box 40, which will be an audio tone of, e.g., 750 cycles per second. Upon the completion of the audio tone the system will return from mode 3 to mode 0, at which point the process will repeat so as to read out the next correct time.

If while the system was in mode 14 in box 37 it had been determined that the correct time included seconds, the system would have moved from mode 14 to mode 6, as represented by box 41, and the word "and" would have been read out. From here the system would have moved into mode 2 in box 42 and the number of seconds, e.g., 10, 20, 30, 40, or 50, would have been read out. From mode 2 the system would have then moved into mode 10 in box 43 and the word "seconds" would have been read out. From here, the system would have moved into mode 11 and the operation of the system would follow from here back to mode 0 as previously described.

Now, referring back to FIG. 1, the drum 21 of this embodiment contains 31 tracks, 29 of which contain an audio message while the 13th track is a reference track that generates a reference pulse for each revolution of the drum 21 and the 31st track is a silent track. The reference pulse is then fed to phase state or mode selector 26, which moves the system from mode 0 through mode 5, one mode at a time, for each pulse received from the reference track of drum 21. As the mode selector 26 moves through the modes 0, 8, 9, 1 and 5, the control logic circuit 27 gates the appropriate drum track 22 and its audio message to the audio output 30. For example, when the mode selector 26 has placed the system in mode 8, the control logic circuit 27 will gate the words "At the" through gate 28 to the audio output so that the words "At the" are spoken by the system. Similarly, upon receiving the next pulse from the reference track 22 the mode selector 26, in conjunction with control logic circuit 27, will gate out the audio on track 22 which has the word "tone" thereon, so that this word will be spoken out by the system through audio output 30. The same sequence is followed with respect to the phrases "the time" in mode 1 and "will be" in mode 5.

When the pulses from the reference track of drum 21 have caused the mode selector 26 to place the system in mode 13, the control logic circuit 27 will interrogate the digital clock 24 to determine what the correct hour is. When this is determined, the control logic circuit 27 will select the track 22 upon which the correct number to indicate the hour is located. This number, in audio form, is then gated through its associated gate 28 to the audio output 30 and the number, e.g., "four," is read out if the hour is 4 o'clock. From here, the next succeeding pulses from the reference track of drum 21 drive the mode selector 26 so as to select either mode 12 or 14, which is determined by interrogation of the clock 24 by control logic circuit 27. Upon moving into one of these modes, the appropriate tracks on drum 21 are gated to the audio output 30 so as to read out the number of numbers representative of the minutes, e.g., 30 minutes.

This process of changing the condition of the mode selector or phase state counter 26 upon each revolution of the drum 21 continues, as does the interrogation by control logic circuit 27 of digital clock 24, so that the appropriate time in hours, minutes and seconds is read out at the audio output 30 and the 750 cycle per second audio tone is then sounded, at which time the condition of the mode selector 26 is changed and the system returns to mode or phase state 0 to begin another message.

Detailed Description

The system and its operation is now described in more detail. Referring to FIG. 3 there is shown a transformer 51 having, e.g., a 60 cycle per second 115-volt input. One side of the transformer secondary is grounded at 52 while the other side 53 is coupled to a diode 54, which acts as a half-wave rectifier. The rectified signal then passes through pulse shaper 56, which utilizes a Schmidt trigger to square up the rectified signal. Positive pulses then enter input terminals 57 and 59 of NAND-gate 58. For each positive pulse at the inputs a negative pulse appears at the output of gate 58 on line 61. The operation and circuitry of positive logic NAND gates is well known and is characterized by the presence of a low or negative signal at the output of the gate when all of the inputs thereto are high or positive, while the output will be high or positive for any other combination of inputs. Every gate hereinafter described is such a NAND gate.

Thus, a series of negative pulses appear on line 61 at the rate of 60 pulses per second. These pulses are then fed into a first counter formed by delay flip-flops 62, 63 and 64. Such delay-type flip-flops are also well known in the art and further discussion of their internal operation and circuitry is unnecessary here. The function of these three flip-flops is to produce an output pulse on line 66 for every six input pulses received from line 61. Thus, a series of positive pulses are produced on line 66 at the input of NAND-gate 67. At the rate of one pulse for every tenth of a second. Gate 67 inverts these positive pulses in typical NAND fashion. These negative series of pulses are then fed through line 69 into a second counter composed of flip-flops 71, 72, 73, 74 and 75. These are also delay-type flip-flops and are identical with those previously discussed. This counter then produces a series of positive pulses at line 76 at a frequency of one pulse per second. Thus, for every 10 pulses in at line 69 one pulse emerges at line 76. This signal then passes through NAND-gate 77, which acts as an inverter, and the inverted signal passes through line 78 into a third counter composed of flip-flops 79, 80, 81, 82, and 83. These flip-flops are identical with those utilized in the preceding counters and produce a signal output at line 86 having a frequency of one pulse for every 10 seconds.

This signal is then fed into a fourth counter formed by flip-flops 87, 88, and 89, which counter acts to produce a positive output pulse on line 91 for every six pulses received from line 86. Thus, a signal having a frequency of one pulse per minute is generated on line 91.

Each of the flip-flops 87, 88 and 89 has an output 92, 93 and 94, respectively which is at a high voltage when the state of the respective flip-flops is in the "one" condition. In addition, each of the flip-flops 87, 88 and 89 has an output 96, 97 and 98, respectively, which has a low voltage thereon when the respective flip-flop is in the "one" condition and which has a high voltage when the respective flip-flop is in the "zero" condition. Coupled to these outputs are NAND-gates 100, 101, 102, 103, 104 and 105. These gates represent 0, 10, 20, 30, 40, and 50 seconds, respectively, and are coupled to the outputs of flip-flops 87, 88, and 89 so that when the flip-flops are all in the "zero" state, both of the inputs to NAND-gate 100 are high and the output from NAND-gate 100 is low. Thus, a low output at 106 from NAND-gate 100 indicates that there are 0 seconds. Similarly, as each of the pulses, one every 10 seconds, appears on the input line 86 to the counters 87, 88 and 89, these counters will count from zero up through five and back to zero, or through six different states. Thus, for example, after a first pulse is received from the input line 86 the flip-flop 87 will be set in its "one" state while the other flip-flops 88 and 89 will remain in their "zero" states. As a result, the input lines 107 and 108 to NAND-gate 101 will be both be characterized by a "high" voltage since line 108 is in common with output 92 of flip-flop 87, which is high, and input 107 is in common with output 97 of flip-flop 88, which is also characterized by a high voltage, since flip-flop 88 is still in the "zero" state. So, as the input pulses from line 86, at a frequency of one pulse every 10 seconds, are fed into the counter containing flip-flops 87, 88, and 89 the NAND-gate 100 provides a low output when the count indicates zero seconds and each of the NAND-gates 101-105 has two of its inputs rendered high when the counter represents 10, 20, 30 40 and 50 seconds, respectively. The outputs of gates 101 through 105, however, will themselves remain high until the input 110, common to each of the gates 101-105, is rendered high by NAND-gate 111, which represents the existence of phase state 2 and which is shown in FIG. 7.

The one pulse per minute signal at output line 91 is also fed through NAND-gate 112, which acts as an inverter, and the inverted signal output therefrom on line 113 (4) is fed into a fifth counter as shown at 113 (3) in FIG. 4, which is composed of flip-flops 115, 116, 117, 118, and 119. In order to cross-reference connections between figures, a number in parenthesis has been used to indicate from which or to which figure a particular line is going. Here again, as in the case of the seconds counter in FIG. 3 that is composed of flip-flops 87, 88 and 89, each of the flip-flops 115-119 are placed in a condition such that their "one" outputs or their "zero" outputs are in a "high" or "low" voltage condition, depending upon the number of pulses which have been received via the input line 113. For example, when there are no minutes, each of the flip-flops 115-119 is in a condition such that its "zero" output is in a "high" voltage condition. A NAND-gate 121 has one input 122 connected through the "zero" output of flip-flop 119 and the other input 123 coupled to the "zero" output of flip-flop 115. It is only necessary to provide these two inputs to the NAND-gate 121 in order to determine that the count of the counter and of flip-flops 115-119 is zero since all other counts of the one through nine, of which the flip-flops 115-119 are capable of indicating, one or the other of inputs 122 and 123 to the NAND-gate 121 will be low. Thus, when the counter containing flip-flops 115-119 indicates that there are 0 minutes in the NAND-gate 121 output at line 124 will be low.

When a first pulse enters at input line 113 the flip-flop 115 will be placed into a condition wherein the voltage on "one" output line 126 will be high while the voltage on "zero" output line 127 will be low. All of the other flip-flops 116-119 will remain in the "zero" state. Thus, there is a count of 1 minute present within the counter, and NAND-gate 128 has an input 129 directly connected to the output 126 of flip-flop 115, and at the count of 1 minute this input is at a "high" voltage. In addition, NAND-gate 128 has a second input 131 connected to the "zero" output of flip-flop 116, which is at a "high" voltage, since the flip-flop 116 is in the "zero" state. Gate 128 also has a third input 132 coupled to the output 133 of NAND-gate 134, which is representative of 11 minutes. However, since the count is 1 minute the output of gate 134 will be high so that the input 132 to gate 128 is also high. The gate 128 also has a fourth input 136 from the output of NAND-gate 137 in FIG. 7. This NAND-gate represents the phase state 14 condition and the output therefrom is high when the system is in phase state 14, as will be later described. This phase state, as shown in FIG. 2 in box 37, represents the point at which single word minutes are to be read out. Thus, if the count is 1 minute and the phase state 14 is activated, the output from NAND-gate 128 on output line 141 will be low and will act as an input to NAND-gate 142 in FIG. 8. This low input on line 141 will cause the output of NAND-gate 142 on line 143 to be high, and this in turn, will gate the word "one" from the fifth drum track 22 through audio amplifier 144, amplifier 145, impedance matcher 146 to a speaker (not shown) at the audio output 30 that will speak out the word "one."

A similar sequence of events will occur with respect to various counts within the counter comprised of flip-flops 115-119 in FIG. 4. More specific examples, however, will be set forth later in the specification.

The output 151 from flip-flop 119 in FIG. 4 is one pulse every 10 minutes, and this signal is inverted through NAND-gate 152. The negative pulses at the output 153 of gate 152 are then fed into a sixth counter as shown in FIG. 5, which is comprised of flip-flops 154, 155 and 156. These flip-flops, as in the preceding counters discussed, will count through states 0 to 5 and are associated with various NAND gates, to be later discussed with respect to specific examples, the outputs of which indicate that a certain number of minutes in multiples of 10 exist. The output line 158 from flip-flop 156 is coupled to NAND-gate 159, which acts as an inverter, and the frequency of the pulses on line 158 is one pulse per hour. These are positive pulses which are inverted by the gate 159 so that they appear as negative pulses on the output 161 of the gate 159. This output line 161 is, in turn, coupled to the input of a seventh counter, as shown in FIG. 6, which is comprised of flip-flops 162, 163, 164, 165, 166, and 167. This counter has the capability of counting through 13 states, e.g., from 0 through 12, and has a plurality of NAND gates associated therewith, which in conjunction with the input 168 from the NAND-gate 169 in FIG. 7 representing phase state 13, provide outputs to the appropriate audio amplifiers in FIG. 8 so that the appropriate hour is read out when the system is in phase state 13.

Referring now to FIG. 7, wherein the phase state counter or mode selector 26 and its associated circuitry is shown in more detail, there is shown a means for coupling the selector to the storing drum which includes the input line 25 from the reference track of the drum 21. This line is coupled through a voltage level changer comprised of resistors 180 and 181 in conjunction with a voltage source 182. From here, pulses from the reference track pass through line 183 and into pulse shaper 184. This pulse shaper is identical with that represented at 56 in FIG. 3 and utilizes a Schmidt trigger in a manner well known in the art to square the pulses passing therethrough. The pulses are then passed through NAND-gate 186, which acts as an inverter, and a series of negative pulses emerge from the gate 186 on line 187 at a frequency equal to the frequency of rotation of the drum 21, which in this embodiment is one rotation every 625 milliseconds. These pulses are then fed into the counter or mode selector 26 which includes JK flip-flops 188, 189, 190 and 191. An example of a JK flip-flop is discussed in an article entitled "Understanding IC Logic" which appears at page 158 of Electronics magazine dated Mar. 6, 1967. Because the operation and composition of JK flip-flops is well known in the art, further detailed description is unnecessary.

Each of the flip-flops 188-191 includes a set input, a reset input, a clock input, a "one" output, and a "zero" output wherein the voltage is high on the "one" output when the flip-flop is in the "one" state and wherein the voltage is high on the "zero" output when the flip-flop is in the "zero" state. Each of the flip-flops 188-191 also has associated therewith a plurality of NAND gate logic that acts to set or reset the respective flip-flops, as will later be explained.

Description of Operation by Use of Specific Time Examples

The operation of the system will now be described in more detail by the use of various examples of time. If we assume that the system is adapted to constantly read out the time, the system will begin its readout in mode zero as represented in box 29 of FIG. 2. In this mode each of the flip-flops 188-191 in the phase state counter or mode selector 26, as represented in FIG. 7, will be in the "zero" state. Thus, each of the "zero" outputs of the flip-flops 188-191 will be in a "high" voltage state, and each of these outputs is connected to NAND-gate 201 via input lines 202, 203, 204, and 205, respectively. As a result of all these inputs being high, the output at line 207 of the NAND-gate 201 will be low. The low-voltage level is then fed into NAND-gate 208 and because each of the inputs to the gate 208 are not high, the output therefrom on line 209 is also high. This high output signal is, in turn, fed into audio amplifier 211 in FIG. 8. The other input 212 to amplifier 211 is grounded so that during the duration of the high input signal on input line 209 the amplifier 211 is triggered on but no audio signal is present on input line 212 so that no audio output signal is generated at output 213. As a result, this absence of an audio signal at 213 causes an absence of an audio signal at the output 214 of audio amplifier 145 so that no audio output passes through impedance matcher 146 and a period of silence is experienced at the audio output 30 of the system. Instead of being coupled to ground the input line 212 to audio amplifier 211 could be coupled to the readout head 23 of the drum 21 which is associated with the track 22 that contains silence thereon, as opposed to the other tracks 22 which contain words.

Each of the audio amplifiers in FIG. 8 are that associated with the amplifier 211 contain common emitter resistor 216 and common emitter capacitor 217, which is coupled across the resistor 216. In addition, although not shown, each of the audio amplifiers contains an internal collector load which is common to each of the audio amplifiers. Each of these amplifiers is also associated with a particular track 22 on the drum 21 and with a particular readout head 23 so that these amplifiers when energized act as gates to enable a particular audio message from a respective track 22 to be read out through the audio output 30. This will be seen more clearly as further examples are set forth.

Assuming now that the drum 21 after the period of silence has been read out, has made one rotation and 625 milliseconds have elapsed, the reference pulse on the reference track of the drum 21 will then place flip-flop 191 in its "one" state. Only this flip-flop will be placed in the "one" state by the occurrence of the first reference pulse from the reference track because the set input 221 has been placed in a high state prior to the occurrence of the reference pulse by NAND-gate 222. This is because the low output from gate 201 was fed into the gate 222 while the system was in phase state or mode zero and while a period of silence was being read out. The occurrence of this low signal at an input to NAND-gate 222 results in a high output from that gate on line 221.

Thus, the first pulse which occurs after one rotation of the drum 21 sets the flip-flop 191 in the "one" condition. When this occurs the signal on output 205 of the flip-flop goes low so that the output of NAND-gate 201 goes high. This high signal feeds into NAND-gate 208 and renders the output low on line 209. This low signal, in turn, then turns off the amplifier 211 in FIG. 8 so that the silent track from drum 21 is no longer read out.

At the same time the NAND-gate 226 now has each of its inputs at a high level. Its output at line 227 then becomes low and this low signal enters into NAND-gate 228 in FIG. 8, which acts as an inverter so that the output at line 229 becomes a high signal. This high signal then triggers on audio amplifier 231 so that the audio message "at the" on the first track of drum 21 is passed through the amplifier 231 and through line 213 to amplifier 145 and finally to the audio output 30 so that the phrase "At the" is spoken by the system.

The low output at line 227 from gate 226 in FIG. 7 also enters gate 230 making the output thereof on line 232 high so as to set flip-flop 188. Upon the occurrence of the reference pulse on the reference track of drum 21, the flip-flop 188 is thus placed in the "one" state so that each of the inputs to the NAND-gate 233 is high and the output therefrom on line 234 becomes low. This low output at 234 is then fed into the gate 236 in FIG. 8 rendering the output at line 237 high so that audio amplifier 238 is triggered on and the word "tone" is read out at the audio output. This low output at line 234 from gate 233 in FIG. 7 also passes into gate 239 so that the output therefrom on line 241 becomes high so as to reset flip-flop 191.

The next reference pulse then places flip-flop 191 in the "zero" state so that each of the inputs to gate 242 becomes high and the output therefrom on line 243 becomes low. This low output is then fed into the input 243 of gate 244 in FIG. 8, which acts as an inverter so that a high input emerges therefrom on line 245. This high output then triggers on amplifier 246 so that the phrase "the time" is read out of the audio output.

The low output signal on line 243 from gate 242 in FIG. 7 passes through inverting NAND-gate 247 so that a high signal appears on the output 248 thereof and flip-flop 190 is placed in a set condition. Upon occurrence of the next pulse from the reference track of drum 21, the flip-flop 190 is placed so that its output is in the "one" state and gate 251 then has each of its inputs in the high state. Thus, the output at line 252 will be low and this low signal is fed into inverting NAND-gate 253 in FIG. 8. The high output emerging therefrom on line 254 clears on amplifier 256 so that the phrase "will be" is read out of the audio output.

The low signal output at line 252 from gate 251 in FIG. 7 is also fed into gate 222, the output of which at 221 is rendered high so that flip-flop 191 is set. As a result, the next reference pulse from the reference track of drum 21 will place the flip-flop 191 in the "one" state and the gate 169 then will have each of its inputs in the high state so that its output at 168 will become low. At this point the logic system must interrogate the clock in order to determine what the correct hour reading is at that point. Thus, the output 168, which is low, passes through inverting NAND-gate 261 in FIG. 6 so that the output therefrom on line 262 is high.

Example of Operation When Time is 4:30 Exactly

If we assume that at this point the correct hour is four, each of the inputs to the four hour NAND-gate 263 from the flip-flops 162-167 will be high so that the output from the gate 263 at line 264 will be low. Each of the associated hour NAND gates will have at least one input low so that the gate 263 will be the only one having a low output. This low output is then fed into gate 266 in FIG. 8 so that the output on line 267 therefrom becomes high. This high output then triggers on amplifier 268, which is associated with the track 22 on drum 21 which has the word "four" thereon. As a result, the word "four" is read out through the audio output.

Simultaneously, the low output from gate 169 in FIG. 7 passes through inverting NAND-gate 271, the function of which is analogous to that of gate 261 in FIG. 6, and the high output from the gate 271 in FIG. 7 on line 272 feeds into one input of NAND-gate 273. If we assume that the correct time is 30 minutes past 4 the flip-flops 154-156 in FIG. 5 will be in such a condition such that each of the inputs to NAND-gate 274 from the flip-flops is high. In addition, the input 276 to gate 274 originates at the output from gate 277 in FIG. 4, and the signal on this output 276 is high when there are zero minutes and when there are even tens of minutes, i.e., 10, 20, 30, 40, or 50. Thus, since it is 30 minutes past 4 the output from gate 277 in FIG. 4 is high so that the gate 274 in FIG. 5 now has each of its three inputs high and its output on line 281 is low. This low input is then fed into NAND-gate 282 making the output on line 283 therefrom high. This high input, in turn, is passed through inverting NAND-gate 284 making the output at line 285 therefrom low, and this low signal is fed into NAND-gate 286 making its output high on line 287.

Returning now to FIG. 7, this high signal on line 287 coupled with the high signal on line 272 from gate 271 are fed into the gate 273 so that its output on line 288 becomes low. This low signal is then passed into gate 289 making its output high on line 291. This high output, in turn, sets flip-flop 189. While this is occurring, the low signal output on line 168 from gate 169 passes into gate 292 so as to render its output on line 293 high. This high output on 293 then resets flip-flop 188.

Thus, each of the flip-flops 188-191 in FIG. 7 are in such a condition that upon the occurrence of the next reference pulse from the reference track of drum 21 the outputs from the flip-flops are placed in a condition so that gate 301 has each of its inputs in a high condition. As a result of the resetting of flip-flop 188 and of the setting of flip-flop 189 the system moves now into mode or phase state 14, as represented in FIG. 2.

Because each of the inputs to gate 301 in FIG. 7 is high the output on line 302 therefrom becomes low and this low signal is then fed into gates 137 and 303, each of which act as inverters so that the outputs therefrom on lines 136 and 304, respectively, are high. The high output at line 304 of gate 303 is then fed into one input of gate 306 in FIG. 4. The second input to gate 306 comes from output 276 of gate 277, the value of which is high as previously explained. Thus, the output on line 307 from gate 306 in FIG. 4 becomes low and this, in turn, passes into gate 308 so as to render its output on line 309 high. The presence of a high signal on output line 309 indicates that the system is in either phase state 14 or in phase state 12. In this specific example the system is in phase state 14 so that the output is high. This high signal is then fed into the third input of gate 311 in FIG. 5 so that each of the inputs to the gate 311 are high, the other two originating from the flip-flops 154-156. The low output on line 312 of gate 311 is then fed into one input of gate 313 in FIG. 8, so that the output therefrom on line 314 becomes high. This high output signal then triggers on amplifier 315, which is associated with the track 22 on drum 21 which has the word "thirty" located thereon. Thus, when the amplifier 315 is triggered on the word "thirty" is read out through the audio output of the system.

If it is assumed, for the purposes of the example, that the time is 4:30 exactly and 0 seconds, then the output on line 106 from gate 100 in FIG. 3 will be low and will pass through inverting NAND-gate 326 so that the output on line 327 therefrom is high. This high signal is then fed into gate 328 in FIG. 7 along with the high signal from line 136 of gate 137, so that the output on line 329 is low. This low signal is then fed into gate 231 so that the output therefrom on line 232 becomes high and flip-flop 188 is set.

Upon the occurrence of the next reference pulse from the drum 21 the flip-flop 188 is then placed in the "one" output condition, and each of the other flip-flops 189-191 are already in that condition. As a result, each of the inputs to gate 331 is high so that the output therefrom on line 332 becomes low. This low signal is then passed through inverting NAND-gate 333 in FIG. 8 so that the output therefrom on line 334 becomes high. This high signal then triggers on amplifier 336 which is associated with the track 22 of drum 21 which has the word "exactly" thereon so that the word "exactly" is read out of the audio output of the system.

The output 332 from gate 331 in FIG. 7 also feeds into gate 341. Thus, when the output at 332 is low, the output on line 342 from gate 341 becomes high so as to reset flip-flop 190.

Upon the occurrence of the next reference pulse from the drum 21 the flip-flop 190 is placed in the "zero" condition so that each of the inputs to NAND-gate 343 is high and the output therefrom on line 344 becomes low. One portion of this output is fed into gate 208 so as to render its output on line 209 high and the amplifier 211 is then triggered on so that a period of silence is read out of the audio output 30 in the manner previously described with respect to phase state or mode zero.

The output 344 from gate 343 also leads into one input of gate 861, which acts as an inverting gate. Thus, while the system is in phase state or mode 11, the output on line 863 from gate 861 becomes high. This line 863 also acts as one input to gate 862, the output 864 which is connected to one input of gate 239. A second input to gate 862 on line 347 originates in FIG. 3 at the output of flip-flop 83. The signal on line 347 is one pulse every 10 seconds, and more specifically, is comprised of a positive going pulse for the first 5 seconds followed by a negative going pulse for the second 5 seconds. Because even the shortest time message read out by the system takes over 5 seconds to be spoken, the output from gate 343 will be low so that the input on line 863 to gate 862 will be high when the system is in phase state eleven and after a time message has been read out. Prior to the end of the message and for the last 5 seconds thereof the input to gate 862 via line 347 will be low so that the output from gate 862 upon line 864 will be high and the output on line 241 from gate 239 will be low and flip-flop 191 will not be reset. However, when the positive going edge of the pulse on line 347 occurs and while the system is in phase state eleven, both inputs to gate 862 will be high so that its output is rendered low and the output of gate 239 is rendered high. This results in the resetting of flip-flop 191 so that the system is readied to move from phase state 11 to phase state 3 upon the occurrence of the next reference pulse from the drum 21. Thus, it can be seen that depending upon the length of the time message spoken, phase state 11 will be reached at various times. However, no time will ever take longer than 10 seconds to read out. As a result, the length of the silent period in phase state 11 will vary and the system will be shifted to phase state 3 after the system is first in phase state 11 and when the positive going edge of the pulse on line 347 to line 862 coincides with the presence of a high signal on input gate 863 to the gate 862.

Upon the occurrence of the next reference pulse from the drum 21 the flip-flop 191 is placed in a "zero" output condition, and as a result, the gate 351 has each of its inputs in a high condition so that its output on line 352 is rendered low. A portion of this low output is then fed into inverting NAND-gate 353 in FIG. 8. As a result, the output on line 354 from gate 353 is rendered high and amplifier 356 is turned on so as to enable the readout of a 750 cycle tone through the audio output 30 of the system.

The low output from gate 351 on line 352 in FIG. 7 also passes into inverting NAND-gate 361 so that its output on line 362 is rendered high and the flip-flop 189 is reset. Similarly, the output 352 is fed into gate 392 and the output on line 293 is rendered high so that flip-flop 188 is also reset. At this point, each of the flip-flops 188 through 191 is in a reset condition awaiting the next cycle and the next message readout.

Thus, the system has retuned to phase state or mode 0, as represented in FIG. 2, and if it is adapted to continually read out the time, another cycle begins.

Example of Operation When Time is 4:10 and 10 Seconds

A second example of time will now be explained wherein the time is 4:10 and 10 seconds. The operation of the system is identical with the first example explained as the system moves from phase state zero through phase states 8, 9, 1 and 5 to phase state 13. Here also, because the hour 4 is being used in the second example, as it was in the first, the operation of the system in phase state 13 will also be identical. Similarly, because one word, i.e., ten, describes the number of minutes the system will also move directly from phase state 13 to phase state 14 as in the previous example.

Thus, discussion of the second example will begin with the system in phase state 14 and the gate 301 in FIG. 7 having each of its inputs in a high condition so that its output on line 302 is low. This low signal is then fed into inverting NAND-gate 303 so that the output therefrom on line 304 is high. This high output is then fed into NAND-gate 371 in FIG. 5. The flip-flops 154-156 have outputs such that the inputs to NAND-gate 372 are high while the input from line 276 is high for the reasons set forth in the first example. Thus, each of the inputs to gate 372 is high and its resulting output on line 373 is low. This low output is passed through inverting NAND-gate 374 so that the output therefrom on line 375 is high. This high output is then fed into gate 371 along with the high output from gate 303 in FIG. 7. As a result, the output on line 377 of gate 371 is low and this low output passes into gate 378 in FIG. 8. The output thereof on line 379 is thus rendered high so as to trigger on amplifier 381, which is associated with the track on drum 21 which has the word "ten" located thereon. This word "ten" is then fed out through the audio output of the system in the manner previously described.

While the system is thus in phase state or mode 14, the low signal on output line 302 in FIG. 7 is fed into NAND-gate 137, which inverts the low signal to a high signal and feeds this into gate 328. The other input 327 to the gate 328 originates from gate 326 in FIG. 3. A gate 100 in FIG. 3 is connected to the flip-flops 87-89 so that when there are zero seconds both inputs to the gate 100 are high so that its output at 106 is low and so that the output at 327 from gate 326 is high. When there are seconds, as in this example, the output at 327 will be low. As a result, the output on line 329 from gate 328 in FIG. 7 is high and the output on line 232 from gate 231 will be low so that flip-flop 188 will not be set.

The gate 401 in FIG. 7 has a first input 136 which is high when the system is in phase state or mode 14. The gate 401 also has a second input 402 which is in common with the output 106 from gate 100 in FIG. 3. When there are seconds present, as there are in this example, the output on line 402 is high so that the output of gate 401 of FIG. 7 on line 403 is low. This low output is fed into gates 239 and the output therefrom on line 241 becomes high so that flip-flop 191 is reset. Upon the occurrence of the next reference pulse from the drum reference track, the flip-flops 188-191 are placed in states such that each of the inputs to gate 404 in FIG. 7 are high. The output thereof on line 406 is thus rendered low, and this low output is fed into AND-gate 407 in FIG. 8, which acts as an inverter. The output on line 408 therefrom is thus high and this high output triggers amplifier 409 on so that the word "and" is read off the drum and is spoken from the audio output of the system.

The low signal output at line 406 from gate 404 in FIG. 7 is also fed into gate 341 so that the output thereof on line 42 becomes high and flip-flop 190 is reset.

Thus, the next pulse from the drum reference track will place flip-flop 190 in the "zero" state and gate 411 in FIG. 7 will have each of its inputs high so that its output on line 412 will become low. This low signal will be inverted by passing through gate 111 so that the output on 110 will be high. This high signal will then be present at one input of each of the gates 101-105 in FIG. 3. Because the time of this example is 4:10 and 10 seconds, each of the inputs to gate 101 in FIG. 3 will be high and the output therefrom on line 416 will be low. This low input is then fed into gate 378, FIG. 8, thus making the output therefrom on line 379 high. This high output then activates amplifier 381 so the word "ten" will be read out from the audio output.

At the same time, the low output from gate 411 on line 412 in FIG. 7 will pass into gate 222 so that the output at 221 will become high and flip-flop 191 will be set. Again, upon the occurrence of a reference pulse from the drum 21 the output of flip-flop 191 will be placed in a "one" condition and each of the inputs to gate 413 will be high so that the output of 414 will become low. This low output will then be fed through inverting NAND-gate 416 in FIG. 8 and the high output therefrom on line 417 will trigger on amplifier 418 so that the word "seconds" will be read off the appropriate track of the drum 21 and to the audio output of the system.

The low output at line 414 in FIG. 7 will also act as an input to gate 231 so that the output thereof on line 232 will be rendered high and flip-flop 188 will be set. The next pulse from the reference track of drum 21 will set flip-flop 188 and each of the inputs to gate 343 will be high. From this point back to the phase state or mode zero the operation of the system is identical with that described with respect to the first example.

Example of Operation When Time is 4:00 Exactly

In order to explain further parts of the system it will now be assumed that the time is 4 o'clock exactly. Here again, the system will act identically in moving from mode zero through modes 8, 9, 1, 5 and 13 as it did in the preceding two examples. While the system is in phase state 13 and is reading out the hour "four," the output from gate 286 in FIG. 5 on line 287 will be low as will be the input to gate 273 in FIG. 7. This will cause the output of gate 273 to be high and the output of gate 289 will be low. As a result, the flip-flop 189 will not be set. Simultaneously, the output line 168 from gate 169, which is at a low signal value, is fed into gate 292 so that the output therefrom on line 293 becomes high and flip-flop 188 is reset.

The next pulse from the reference track of drum 21 will, thus, reset flip-flop 188 so that each of the inputs to gate 421 in FIG. 7 is high and the output 422 therefrom is low. This low output passes into gate 423, which acts as an inverter, so that the output on line 424 therefrom is high. This high signal is fed into gate 426, FIG. 5, along with a high signal via line 427 which has passed through inverting gate 428 from gate 429. The output on line 431 from gate 426 is, therefore, low and this is inverted to a high signal at the output 423 of gate 433. This high signal then triggers on amplifier 434 so that the word "oh" is taken off the respective track 22 and is read out through the audio output of the system.

This low signal output on line 422 from gate 421 in FIG. 7 is fed into gate 289 so that the output therefrom on line 291 becomes high and flip-flop 189 is set. Upon the next reference pulse from the drum 21 the flip-flop 189 is placed in the "one" condition so that gate 301 has each of its inputs in a high condition and its output at line 302 becomes low. This low signal is then passed through gate 303, which acts as an inverter, so that the output therefrom on line 304 becomes high when the system is in phase state 14. This output then passes into gate 451, FIG. 4. A second input to the gate 451 comes from line 276 which is high when there are 0 minutes. A third input 427 to the clock gate 451 originates at the output of gate 428 in FIG. 5, and this line is high when there are 0 minutes. Thus, when there are 0 minutes and the system is phase state 14 the output from gate 451 on line 452 becomes low. This low output then passes through inverting gate 450, the high output of which on line 455 triggers on amplifier 453 in FIG. 8 so that the word "clock" is selected from its respective track 22 and the word "clock" is read out through the audio output of the system. From here the operation of the system is identical with that described in the first example where there were also 0 seconds.

Example of Operation When Time is 4:35 Exactly

A fourth example will now be described so that further portions of the system can be better understood, and the example described will be that when the time is exactly 35 minutes after 4. Here again, the operation of the system is exactly as has been described previously through mode or phase state 13. While the system is in phase state 13 and where there are two-word minutes, e.g., 35, both inputs to gate 289 in FIG. 7 are high so that the output therefrom is low and flip-flop 189 is not set. At the same time, the line 168 from gate 169 in FIG. 7 has a low signal thereon and this is fed into the gate 292. As a result, the output therefrom on 293 is made high and flip-flop 188 is reset.

Upon the reaction of the next pulse from the reference track of drum 21, the flip-flop 188 is placed in a "zero" state and each of the inputs to gate 421 are now high. The low output on line 422 therefrom is passed into gate 423, which acts as an inverter, and the output on line 424 therefrom becomes high. This high output is then fed into gate 501 in FIG. 4. The other input 124 to gate 501 is also high since there are minutes, and the output on line 502 from gate 501 becomes low. This low signal is then fed into gate 308 so as to render the output on 309 of that gate high. This high signal, in turn, is fed into gate 311 in FIG. 5. Because the number of minutes is 35, each of the inputs to gate 311 is now high so that the output therefrom on 312 is rendered low. This low output is then fed into gate 313 in FIG. 8, so that the output therefrom on line 314 is rendered high. This output then triggers amplifier 315 so that the word "thirty" is read out of the audio output of the system as previously set forth.

Simultaneously, the low output on line 422 from gate 421 in FIG. 7 is fed into gate 289 so that its output becomes high and flip-flop 189 is set. Upon the occurrence of the next pulse from the reference track of drum 21, the flip-flop 189 is placed in a "one" condition. Each of the inputs to gate 301 is then high so that the output therefrom on line 302 is rendered low. This low signal is fed into gate 137, which acts as an inverter, and the output therefrom on line 136 is rendered high. This high signal is then fed into gate 511 in FIG. 4 via line 136. Because the time is 35 minutes each of the other inputs to the gate 511 will also be high so that the output on line 512 therefrom will be rendered low. This low signal is then fed into gate 513 in FIG. 8 and the output 514 therefrom is thus rendered high. This high output then triggers on amplifier 516 so that the word "five" is read out through the audio output of the system as previously described. From here the operation of the system is identical with that described in previous examples where there were zero seconds.

Example of Operation When Time is 4:12 Exactly

A fifth example of time will now be described wherein the time is 4:12 exactly, in order to further describe additional portions of the system. The operation of the system will again be identical with that previously set forth through mode or phase state 13, at which point the word "four" will be read out from the audio output of the system. Referring again to FIG. 7, with the system in phase state 13 the output from gate 271 on line 272 will be high, as previously explained. This high signal is fed into gates 273 as one input thereto. The other input to the gate 273 is via line 287, which is the output line from gate 286 in FIG. 5. Since the number of minutes is not 20, 30, 40, or 50, the input to gate 286 via line 285 will be high. However, because the number of minutes is 12, the second input 531 to the gate 286 will be low so that its output on line 287 which leads into gate 273 in FIG. 7 will be high. The signal on line 531 to gate 286 in FIG. 5 will be low for the following reasons. Because there are 12 minutes in the correct time the output of gate 372 in FIG. 5 will be high, and this output acts as an input to gate 536 in FIG. 4. A second input 133 to the gate 536 is also high because the output from gate 134 is high. However, a third input to gate 536 at line 537 will be low when there are 12 minutes. This is because the output from gate 538 will be low. The input 532 to the gate 538 will be high since it is derived from the output 532 from gate 539 in FIG. 5. Because the 10-minute gate 541 in FIG. 5, when the time is 12 minutes, will have each of its inputs high its output at 542 will be low, and this low signal will pass through the inverting gate 539 so that the output at 532 is high. Returning now to the gate 538 in FIG. 4, the remaining two inputs to that gate are high from the flip-flops 116 and 117 when the time is 12 minutes. As a result, the output at line 537 will be low and this is fed into gate 536 so that its output at 543 will be high. This high signal is then passed through inverting gate 544 so that the output at 531 becomes low, and this low signal is fed into the input 531 of gate 286 in FIG. 5.

Thus, both inputs to the gate 273, if FIG. 7, are now high and its output at 288 becomes low. This, in turn, causes the output from gate 289 at line 291 to become high and flip-flop 189 is set. At the same time the low signal on output 168 from gate 169 will cause the output on line 293 from gate 292 to go high so as to reset flip-flop 188. Upon the occurrence of the next reference pulse from the drum 21, the flip-flops 188-191 will be in such a condition that each of the inputs to gate 301 in FIG. 7 will be high, thus causing the output signal at line 302 to become low. This low signal is then passed through inverting gate 303 so that the output therefrom on line 304 becomes high. This high signal is then fed into an input of gate 551 in FIG. 4. A second input 553 to gate 551 in FIG. 4 is derived from the output 537 from gate 538, which is low when there are 12 minutes. This low output is passed through inverting gate 554 so that the signal on line 553 becomes high. Thus, both inputs to the gate 551 in FIG. 4 are high so that its output on line 556 becomes low. This low signal, in turn, is fed into gate 557 in FIG. 8 so that its output on line 558 therefrom becomes high. Again, as previously set forth, this high output will trigger on amplifier 559 so as to cause the word "twelve" to be read out from the audio output of the system. From here the operation of the system will be identical with that described with respect to the examples wherein there were zero seconds.

Example of Operation When Time is 4:15 Exactly

A sixth and final example of a specific time will now be explained in order to further describe additional portions of the system not yet described. In this example the time will be 4:15 and 0 seconds. Here again, the operation of the system will be identical with respect to those examples previously set forth through mode thirteen.

Assuming that the system has just read out the word "four" and is in phase state 13, it can be seen that the output on line 287 from gate 286 in FIG. 5 will now be low. This is because the input to the gate 286 from line 285 is high and because the input on line 531 is also high. Referring to FIG. 4, it can be seen that the output from gate 544 on line 531 is high when there are 15 minutes since the output from gate 536 is low, as a result each of the inputs thereto being high. Thus, the output at line 288 from gate 273 in FIG. 7 is high and this is fed into gate 289 along with a second input which is also high, since it results from the gate 421 that represents phase state 12, and flip-flop 189 is not set by gate 289 since its output on line 291 is low.

Because flip-flop 188 has been reset via line 168 and gate 292 in FIG. 7, the next reference pulse from the drum 21 will place the flip-flops 188-191 in a condition such that each of the inputs to gate 421 is high. The output therefrom on lines 422 is thus rendered low and this low output is passed through inverting gate 423 so that the output therefrom on line 424 becomes high. This high output is then fed into gate 571, FIG. 4, which also has a second input 532 from the gate 539 in FIG. 5, and this input is also high. Each of the remaining two inputs 572 and 573 to the gate 571 are also high from the flip-flops 119 and 115, respectively. As a result, the output on line 574 from gate 571 becomes low, and this low output is passed through inverting gate 576 so that the output 577 therefrom becomes high. This high signal then triggers on amplifier 578 in FIG. 8 so that the word "fif" is read from the drum to the audio output of the system.

The low output from gate 421 in FIG. 7 is passed into gate 289 so that its output becomes high and flip-flop 189 is set. Upon the occurrence of the next reference pulse from the rotation of the drum 21, the flip-flops 188-191 are placed in such a condition that each of the inputs to the gate 301 is high and its output on line 302 becomes low. This low signal passes through inverting gate 303 so that the output therefrom on line 304 becomes high. This high output, in turn, is fed into input 304 of gate 581 in FIG. 4. The inputs to the gate 536 in FIG. 4 are each high so that its output is low and after having passed through inverting gate 544 the signal becomes high so that the signal on input 582 to gate 581 is also high. Similarly, the input 582 to gate 581 is also high since it is derived from the output 532 of gate 539 in FIG. 5 which is high for "fifteen" minutes. Thus, the output of gate 581 on line 584 is low and this passes through inverting gate 586 so that the output 587 therefrom is high. This high signal turns on amplifier 588 in FIG. 8 so that the word "teen" is read off of the drum and out through the audio output of the system. From here the operation of the system is identical with that described in previous examples where there were 0 seconds.

Because the successful operation of this system depends upon the accuracy of the digital clock it is necessary to provide a means for setting the clock to the correct time as desired. One example of such a means is represented in FIG. 9. The particular set described is a manual set and includes four multideck rotary switches 601, 602, 603 and 604. The structure and operation of the two-deck rotary switch 601 in FIG. 9 is now described, and from this the operation of the remaining switches 602, 603 and 604 becomes clear.

The switch 601 is comprised of two decks 606 and 607. Each of the decks has a respective rotary selector 608 and 609 located thereon with a common stem portion 611 fixedly attached to each of the rotary sections 608 and 609 wherein the stem extends through each of the decks 606 and 607 and at right angles thereto. The top portion of the rotary selector 608 includes a pointer 612 while the bottom portion of the rotary selector 608 includes a pointer 613 located 180° from the pointer 612. Similar pointers 614 and 616 are located on the rotary selector 609.

Each of the decks 606 and 607 includes 20 electrical contacts located around the circumference thereof on both the top and bottom. These contacts are represented by the numbers 1-20 on the inside portion of the decks 606 and 607. These contacts are, in turn, connected with respect to plugs P2-2, P2-27, P2-26, P2-1, P2-3 and P2-28, which are connected to their respective receptacles R2-2, R2-27, R2-26, R2-1, R2-3 and R2-28 that are associated with flip-flops 87-89 in FIG. 3. In addition, a common electrical line 617 is in electrical contact with each of the rotary selectors 608 and 609 and is also coupled to terminal 618 of switch 619. A second terminal 621 of the switch 619 is coupled to ground.

The operation of the two-deck rotary switch 601 in the setting of the flip-flops 87-89 in FIG. 3 to the correct time within 10 seconds will not be described.

If it is desired to set the number of seconds at e.g., 30 seconds, each of the flip-flops 87, 88 and 89 in FIG. 3 must be placed in the "one" condition so that the outputs are high on lines 92, 93, and 94. This may be accomplished by grounding each of the preset inputs 622, 623 and 624 of the respective flip-flops. In order to set the time at 30 seconds the rotary selectors 608 and 609 should be moved so that the pointers 612 and 614 are in contact with electrical contact number five. When this occurs, the points 613 and 616 on the under side of the decks 606 and 607, respectively, will be placed in contact with electrical contacts number 13. The manual pushbutton switch 619 should then be pushed into contact with terminals 618 and 621. This will then complete a circuit from ground through the switch 619 and through common electrical line 617 through the switch 601. From here the circuit is completed through the rotary selector 608, which is in electrical connection with the common line 617, and through the pointer 612 to plug P2-1. From here the ground potential is coupled through receptacle R2-1 of flip-flop 87 in FIG. 3 and through preset line 622 so that the flip-flop is placed in the "on" condition. Similarly, the common line 617 is electrically in connection with the rotary selector 608 and the ground circuit is completed therethrough to the lower pointer 613 of the deck 606 so that the ground potential is passed through contact 13 and out through plug P2-2 in FIG. 3 and preset line 623 of flip-flop 88 is thus placed at a ground potential so that flip-flop 88 is placed in the "one" condition. In like manner, the common line 617 is also in electrical contact with the rotary selector 609 and the ground circuit is completed through pointer 614 of the lower deck 607, through contact number 5 and out through plug P2-3. This ground potential then passes into receptacle R2-3 of FIG. 3 and into preset line 624 of flip-flop 89 so that the flip-flop is placed in the "one" condition.

In this manner each of the flip-flops 87-89 is placed in the "one" condition by means of its respective preset input, and the normal counting of the flip-flops 87-89 is stopped. When the desired time, e.g., 30 seconds, is reached the manual switch 619 is released which breaks the ground circuit to the preset inputs of the flip-flops and enables the flip-flops to begin their sequence of counting. Thus, a desired time can be set into the flip-flops and the flip-flops will hold this time until that moment is reached. At that point the flip-flops are permitted to begin their normal count.

For use with the system herein disclosed the flip-flops 87-89 in FIG. 3 will be set 10 seconds ahead so as to compensate for the time that readout of the message will take. Differences in the length of the message to be read out are compensated for by the length of the silent period as represented by mode or phase state 11 in FIG. 2 as previously set forth.

In a manner similar to that already described with respect to rotary switch 601, the counters 602, 603 and 604 may be set. The six-deck rotary switch 602 operates to set the flip-flops 115-119 in FIG. 4 so as to represent the correct number of minutes. The two-deck rotary switch 603 similarly operates with respect to flip-flops 154, 155 and 156 in FIG. 5 to set into these flip-flops the correct time in tens of minutes. The six-deck rotary switch 604 also operates with respect to flip-flops 162-167 in FIG. 6 so as to set these flip-flops to the correct number of hours.

In addition, the plug P2-21 located immediately adjacent to the terminal 618 in FIG. 9 is connected to receptacle R2-21 in FIG. 3, which in turn, is connected to the clear inputs of each of the flip-flops 62-64, 71-75 and 79-83. Thus, when a new time is set into the digital clock as previously described these flip-flops 62-64, 71-75, and 79-83 are placed in the "zero" condition and are ready to begin a new count. The receptacle R2-21 is also represented in FIG. 7 and acts to clear each of the phase state flip-flops 188-191.

The receptacle R2-21 is also represented in FIG. 6 and is connected through diode 731 to the clear input of flip-flop 732, which is a delay-type flip-flop similar to those previously described. A 13-hour gate 871 is coupled via its output line 872 to the preset input of flip-flop 732. The flip-flops 163, 164, and 176 are in the "one" condition while flip-flops 162, 165 and 166 are in the "zero" condition to represent the 13th hour, which also coincides with the first hour on a 12-hour clock. As a result, each of the inputs to the gate 871 is high so that the output therefrom becomes low and the output from flip-flop 732 on line 873 also goes low so as to clear flip-flops 167, 164 and 163. When this occurs each of these flip-flops goes to the "zero" condition and the flip-flop 162 is the only one remaining in the "one" condition and the state of the hour flip-flops 162-167 is then the same as when 1 hour is present. In order to prevent the flip-flops 163, 164 and 167 from remaining in the cleared condition and so they may be allowed to change their conditions as appropriate, when the counter comprised of flip-flops 162-167 is in the first hour and after 10 minutes has elapsed in the first hour, the low output from gate 372 in FIG. 5 is used and is passed through the diode 874 in FIG. 6 to the clear input of flip-flop 732 so that the output at line 873 becomes high and the flip-flops 163, 164, and 167, because of their respective diodes 876, 877 and 878, are no longer held in the cleared condition and are free to count when the time arises. The function of the diodes 881, 882 and 883 associated with flip-flops 163, 164 and 167, respectively, in FIG. 6 is to block the passage of the output on line 873 from flip-flop 732 into the manual set circuit of FIG. 9.

Although the announcing system has herein been described wherein it continuously reads out the correct time every 10 seconds, it may be desirable to interface this system with various other electronic networks by a coupling means so that the announcing system may be utilized in conjunction with the other electronic systems. One such desirable interface is with respect to the telephone system whereby it would be possible for a person to dial a given number so as to obtain the correct time. An example of such an interfacing or coupling network that will couple the announcing system with the telephone system is shown in FIG. 10.

In FIG. 10, there are shown two input lines 804 and 806 from the telephone system, and these lines are coupled to coils 807 and 808 of transformer 809. In addition, a capacitor 811 is connected between the coils 807 and 808. As in standard telephone systems, a 48 volt DC signal is present across the input lines 804 and 806. However, because the switching or relay contacts N-1 and M-1 that are coupled between coils 807 and 808 are normally open, this DC signal is not permitted to pass through the coils 807 and 808. Similarly, because of the capacitor 812 this DC signal is not permitted to pass through the variable resistance photocell lamp 813, which together with the capacitor 812 is coupled across the lines 804 and 806. When the photocell lamp 813 is off the resistance associated therewith is high so that the amplifier 814 is biased off and relay coil M is not energized.

When a ringing signal occurs across lines 804 and 806, which signal is usually a 105 to 110 volt AC signal at 20 cycles per second, the capacitor 812 allows a portion of this signal to pass through photocell lamp 813. When this occurs the resistance of the photocell lamp is reduced so that the DC voltage source is able to bias on the amplifier 814, thus allowing a current to flow from the DC voltage source 817 through a first switching or relay coil M and through triggering amplifier 814 to ground. This energizing of relay coil M then causes relay contact M-1 to close. This, in turn, enables the AC and DC signals from the telephone input to pass through second switching or relay coil N so that relay contacts N-1 and N-2 are closed. The closing of contact N-1 latches the relay coil N so that it remains energized while the closing of relay contact N-2 indicates that an incoming call has been received.

As described previously, the drum 21 in FIG. 1 is constantly rotating about its axis so that the system is constantly passing through each of the various phase states or modes represented in FIG. 2. Thus, at the beginning of each message when the system is in phase state or mode zero, the output on line 207 from gate 201 in FIG. 7 and in FIG. 10 will be low. This low signal then passes through inverting NAND-gate 821 so that the output therefrom is high when the system is in phase state zero. When the system moves on from phase state zero to phase state 8 the output from gate 821 on line 822 again becomes low. Thus, a pulse is formed on the line 822 each time the system passes through phase state zero. This pulse is inverted through inverting gate 823 so that a third switching or relay coil Q is energized each time the system passes through phase state zero. When this occurs the contact Q-1 associated therewith is closed. Thus, because relay contact N-2 has also been closed upon the reception of an incoming call, the relay coil R and the fourth relay coil S are both energized by means of DC sources 826 and 827, respectively. The energizing of coil S then results in the closing of relay contacts S-1 and S-2 so that the audio output 30 from the announcing system is coupled to the transformer 809 and the audio message is read out through the telephone circuit and telephone lines 804 and 806.

A count of two counter comprised of two delay type flip-flops (not shown) 831 has one input thereto at line 822. In addition, a second input 832 from gate 833 is also coupled to the counter 831 and is coupled to the clear inputs of the flip-flops located therein (not shown). While the relay contact R-1 is open the output from gate 833 is low so that the counter 831 is kept in the cleared state notwithstanding the presence of input pulses on line 822. However when the relay coil R is energized and the contact R-1 is closed the gate 833 has its input coupled to ground so that its output becomes high and the counter 831 is no longer in the clear state. The counter then begins to count for each input pulse received from line 822 and upon reception of the third such pulse after relay contact R-1 has been closed and the output 836 from the counter 831 becomes high. This high output is then fed through inverting NAND-gate 837 so that the output therefrom on line 838 becomes low and a fifth switching or relay coil P is energized so that normally closed relay contact P-1 is opened and the telephone line circuit is opened. As a result, the DC signal across lines 804 and 806 no longer passes through relay coil N so that relay contact N-2 is opened and relay coil S is deenergized causing relay contacts S-1 and S-2 to open so that the audio output from the announcing system is no longer transformed through the transformer 809 to the telephone circuit.

Thus, the use of the counter 831 in conjunction with the phase state gate 201 allows the person making the call to receive only two complete time messages. At the completion of the second message and when the system is returning to phase state zero to begin a third message, the third pulse created thereby on line 822 causes the output from counter 831 to energize the relay coil P. This, in turn, opens the normally closed relay contact P-1 which ultimately results in the opening of relay contact S-1 and S-2 so that the audio output from the announcing system no longer transmits its message to the caller.

In order to make this interface circuit applicable to three wire telephone systems, it is necessary only to break the line 905 in FIG. 10 and to tie that side of the lamp 813 to ground. The ringing signal then occurs between ground and line 804 while the 48 volt DC signal occurs between lines 804 and 806.

In order to prevent hearing from the audio output 30 of the system, any audible noise which might occur from the joint of the film which covers the periphery of the drum 21, the audio output of the system is suppressed momentarily immediately following the occurrence of the reference pulse from the drum 21 since the location of the joint in the film is immediately behind the point at which the reference pulse occurs as the drum rotates. This suppression of the audio output is accomplished by taking the reference pulse from the reference track and feeding it into pulse shaper 931 in FIG. 8. The output from the pulse shaper 931 is fed through suppressor 932 so that the output therefrom is such that the signal output from amplifier 145 is momentarily overcome and no audio output occurs. The reaction time of the circuit elements 931 and 932 is such that the audio output 30 will be suppressed at the moment when the joint in the film of drum 21 passes the readout heads 23. In this way no undesirable clicking sound is heard as the joint passes.

As previously stated, the announcing system may readily be adapted to announce the time based on a 24-hour basis. The following is a description of the Audio Clock so modified:

DESCRIPTION OF A PREFERRED EMBODIMENT OF THE TWENTY-FOUR HOUR CLOCK

General Description

The same basic system is utilized in both the 12-hour and the 24-hour embodiments, as illustrated in FIG. 1. Although the flow diagram or phase state diagram, as illustrated in FIG. 2, could be utilized in the operation of the 24-hour clock, a new phase state diagram illustrated in FIG. 11 represents the sequence of operation of the 24-hour clock. Similarly, the 12-hour clock could readily be adapted to function in accordance with the phase state diagram of FIG. 11 by merely making changes in the phase state selector 26 and in the selection or control logic 27 which would be obvious to one of ordinary skill in the art from the teachings herein.

In explaining the general operation of the 24-hour system it will be helpful to refer to FIG. 11 wherein a flow diagram or phase state diagram is shown which indicates what words and in what sequence those words are read out from the system. Each of the blocks in FIG. 11, as was the case in FIG. 2, represents one step along the way followed by the 24-hour system in reading out its message. If the drum 21 is maintained in a state of constant rotation, the time message read out will begin with a period of silence indicated by the box 29' or mode zero. This will be followed by the reading out of the words "at the" as represented in box 31'. Next the word "tone" will be read out as indicated in box 32' followed by the words "the time" in box 36' and by the words "will be" in box 35'. At this point the control logic circuit 27 must decide whether the correct time includes a one-word hour, e.g. 7 hours, or two-word hours, e.g. 21 hours. If the time includes two-word hours the system will move to box 34' or mode 5 at which point the digital clock 24 will again be interrogated and the first word, e.g. twenty, will be read out. Again, the clock 24 will be interrogated when the system moves to box 44' or mode seven and the second word, e.g. "one", will be read out. If while in mode or phase state 13 in box 35' and upon interrogation by the control logic circuit 27 of the clock 24, it has been determined that one-word hours, e.g. 7 hours, would indicated the correct time, the system would have moved directly from mode 13 to mode 7, at which time the one word, e.g. "seven", would have been read out.

At this point the control logic circuit 27 will again interrogate the clock 24 to determine whether or not the correct time includes minutes or does not include minutes. In the event that the correct time does not include minutes, the system will move from mode 7 to mode 15 in box 38' and the appropriate word "hour" or "hours" will be read out. The control logic circuit 27 will then further interrogate the clock 24 to determine whether or not the correct time includes seconds or does not include seconds. In the event that the correct time does not include seconds the system will move from mode 15 to mode 14 in box 37' and the word "exactly" will be read out. From here the system will move to mode six or box 41', which will be a silent period and then on to mode 4 in box 45', which will be an audio tone of, e.g. 750 cycles per second. Upon the completion of the audio tone the system will return from mode four to mode zero, at which point the process will repeat so as to read out the next correct time.

If while the system was in mode 7 in box 44', the control logic circuit 27 would have interrogated the clock 24 to determine whether or not the correct time included one-word minutes, e.g. "eight", or two-word minutes, e.g. "twenty-two." If the time includes two-word minutes, the system will move to box 33' or mode one at which point the digital clock 24 will again be interrogated and the first word, e.g. "twenty," will be read out. Again the clock 24 will be interrogated when the system moves to box 40' or mode three and the second word, e.g. two, will be read out. If while in mode or phase state 7 and upon interrogation by the control logic circuit 27 of the clock 24, it had been determined that one-word minutes, e.g. 8 minutes, would indicate the correct time, the system would have moved directly from mode 7 to mode 3, at which time the one word, e.g. "eight", would be read out. At this point the control logic circuit 27 will again interrogate the clock 24 to determine whether or not the correct time includes seconds or does not include seconds. In the event that the correct time does not include seconds the system will move from mode 3 to mode 14 in box 37' and the word "exactly" will be read out. From here the system will move to mode six in box 41', which will be a silent period and then on to mode 4 in box 45', which will be an audio tone. Upon the completion of the audio tone the system will return to mode zero, at which point the process will repeat.

If while the system was in mode 3 in box 40' it had been determined that the correct time included seconds, the system would have moved from mode 3 to mode 11 in box 39' and the word "and" would have been read out. From here the system would have moved into mode ten in box 43' and the number of seconds, e.g. 10, 20, 30, 40, or 50, would have been read out. From mode 10 the system would then have moved into mode 2 in box 42' and the word "second" would have been read out. The system would then have moved into mode 6 and the operation of the system would follow from here back to mode zero as previously described.

As in the 12-hour clock embodiment, the drum 21, in FIG. 1, contains 31 tracks, 29 of which contain an audio message while the 30th track is a reference track that generates a reference pulse for each revolution of the drum 21 and the 31st track is a silent track. The drum 21 continuously rotates at a predetermined rate and for each revolution of the drum a reference pulse is fed from the reference track via line 25 to the phase state or mode selector 26 so that the system is sequentially moved through the various phase states. For example, a first reference pulse fed to phase state or mode selector 26 moves the system from mode zero to mode 8. As the mode selector 26 moves through the various modes, the control logic circuit 27, as was the case in the 12-hour clock embodiment, gates the appropriate drum track 22 and its audio message to the audio output 30.

This process of changing the condition of the mode selector or phase state counter 26 upon each revolution of the drum 21 continues, as does the interrogation by control logic circuit 27 of digital clock 24, so that the appropriate time in hours, minutes and seconds is read out at the audio output 30 and the 750 cycle per second audio tone is then sounded, at which time the condition of the mode selector 26 is changed and the system returns to mode or phase state zero to begin another message

Detailed Description of the 24-Hour Clock Embodiment

The 24-hour clock embodiment and its operation will now be described in more detail. FIG. 12 illustrates a portion of the 24-hour clock embodiment which is analogous to that portion of the 12-hour clock embodiment illustrated in FIG. 3, and which operates in the same manner as described with respect to the portion illustrated in FIG. 3. However, diode 54' is connected between ground and the inputs to pulse shaper 56 and effectively half-wave rectifies the AC input. In addition, capacitor 55 is used as a filtering device.

As in the embodiment of FIG. 3, the one pulse per minute signal at output line 91' is fed through NAND-gate 112', which acts as an inverter and the inverted signal output therefrom on line 113 (13) is fed into a fifth counter as shown at 113' (12) in FIG. 13, which is composed of flip-flops 115', 116', 117', 118' and 119'. As in the description of the 12-hour clock embodiment, a number in parentheses has been used to indicate from which or to which Figure a particular line is going. The counters 115'-119' are analogous to the counters 115 through 119 as illustrated in FIG. 4 and operate in a similar manner. As in the operation of flip-flops 115-119 in FIG. 4, each of the flip-flops 115'-119' are placed in the condition such that the "one" outputs or the "zero" outputs are in a high- or low-voltage condition, depending upon the number of pulses which have been received via the input line 113'.

As previously explained with respect to the embodiment of FIG. 4, each of the flip-flops 115'-119' is in a condition such that its "zero" output is in a high-voltage condition. A NAND-gate 121' provides a low output on line 124' when the counter containing flip-flops 115'-119' indicates that there are 0 minutes. The operation of the counter composed of flip-flops 115'-119' and the associated circuitry is similar to the operation of the analogous counter comprised of flip-flops 115-119 and the circuitry associated therewith. Specific examples of operation of the 24-hour clock embodiment, however, will be set forth later in the specification.

The output 151' from flip-flop 119' in FIG. 13 is one pulse every 10 minutes, and this signal is inverted through NAND-gate 152'. The negative pulses of the output 153' (14) of gate 152' are then fed into a sixth counter as shown in FIG. 14, which is comprised of flip-flops 154', 155' and 156'. These flip-flops, as in the preceding counter discussed, will count through stage zero to 5 and are associated with various NAND gates and NOR gates, to be later discussed with respect to specific examples, the outputs of which indicate that a certain number of minutes in multiples of 10 exists. The output line 158' from flip-flop 156' is coupled to NAND-gate 159', which acts as an inverter, and the frequency of the pulses on line 158' is one pulse per hour. These are positive pulses which are inverted by the gate 159' so that they appear as negative pulses on the output 161' (15) of the gate 159'. The output line 161' (15) is coupled to the input of the seventh counter as shown in FIG. 15 which is comprised of flip-flops 162', 163', 164', 165', and 166'. This counter has a plurality of NAND and NOR gates associated therewith, which in conjunction with the inputs 252" (17), 1002 (17) and 1006 (17) from the NAND-gates 261', 1000 and 1004, respectively, in FIG. 17 associated with phase states 5 and 7, provide outputs to the appropriate audio amplifiers in FIG. 18 so that the appropriate hour is read out when the system is in phase state 5 or 7.

The output 1012 (16) from NAND-gate 1010 in FIG. 15 is coupled to the input of an eighth counter, as shown in FIG. 16, which is comprised of flip-flops 1014 and 1016. This counter is associated with a plurality of NAND and NOR gates which in conjunction with the phase state circuitry of FIG. 17 provide outputs to the appropriate audio amplifiers in FIG. 18.

FIG. 17 shows the phase state counter or mode selector 26 and its associated circuitry which may be utilized in the 24 -hour clock embodiment. Again, this phase state counter is analogous to that illustrated in FIG. 7 and also includes an input line 25' from the reference track of the drum 21. This line is coupled through a voltage level changer comprised of resistors 180' and 181' in conjunction with a voltage source 182'. From here, pulses from the reference track pass through line 183' to which is coupled the grounded diode 1008. The pulses then pass into pulse shaper 184' which is identical with that represented at 184 in FIG. 7. However, a filtering capacitor 185 is included, and, although not shown in the embodiment of FIG. 7 such a capacitor may be included therein also. The NAND-gate 186' acts as an inverter and a series of negative pulses emerge from the gate 186' at a frequency equal to the frequency of rotation of the drum 21, which in the 12 -hour and the 24 -hour clock embodiments is one rotation every 625 milliseconds. These pulses are then fed into the counter or mode selector 26 which includes JK flip-flops 188', 189', 190' and 191'. The operation and arrangements of JK flip-flops is well known in the art and examples of such flip-flops are discussed in an article entitled "Understanding IC Logic" which appears at page 158 of Electronics magazine dated Mar. 6, 1967 and in an article entitled "How the JK Flip-Flops" which appears at page 54 of Radio Electronics magazine dated Jan. 1969.

As previously explained with respect to the flip-flops 188-191 in FIG. 7, each of the flip-flops 188'-191' includes a set input, a reset input, a clock input, a "one" output, and a "zero" output wherein the voltage is high on the "one" output when the flip-flop is in the "one" state and wherein the voltage is high on the "zero" output when the flip-flop is in the "zero" state. Each of the flip-flops 188'-191' also has associated therewith a plurality of NAND and NOR gate logic that acts to set or reset the respective flip-flops.

Description of Operation of the 24-Hour Clock Embodiment by Use of Specific Time Examples

The operation of the 24-hour clock embodiment will now be described in more detail by the use of various examples of time. As in the 12-hour clock embodiment, the system will begin its readout in mode zero as represented in box 29' of FIG. 11. In this mode each of the flip-flops 188'-191' in the phase state counter or mode selector 26, as represented in FIG. 17, will be in the "zero" state. Thus, each of the "zero" outputs of the flip-flops 188'-191' will be in a high-voltage state, and each of these outputs is connected to NAND-gate 201' via input lines 202', 203', 204', and 205', respectively. As a result of all of these inputs being high, the output at line 207' (18) of the NAND-gate 201' will be low. This low-voltage level is then fed into NAND-gate 208' in FIG. 18, and because each of the inputs to the gate 208' are not high, the output therefrom on line 209 is also high. This high output signal is, in turn, fed into audio amplifier 211'. Because the other input 212' to amplifier 211' is grounded during the duration of the high input signal on input line 209', the amplifier 211' is triggered on but no audio signal is present on input line 212' so that no audio output signal is generated at output 213'. As a result, this absence of an audio signal at 213' causes an absence of an audio signal at the output 214' of audio amplifier 145' so that no audio output passes through impedance matcher 146' and a period of silence is experienced at the audio output 30 of the system. The audio output arrangement of FIG. 18 is similar to that illustrated in FIG. 8 and instead of being coupled to ground, the input line 212' to audio amplifier 211' could be coupled to the readout head 23 of the drum 21 which is associated with the track 22 that contains silence thereon, as opposed to the other tracks 22 which contain words.

The operation of the phase state or mode selector 26 in the 24-hour clock embodiment is similar to that of the 12-hour clock embodiment as the system passes from mode zero through modes 8 and 9 while the phrases "at the" and "tone" are read out or spoken by the system.

During the time when the word "tone" is read out at the audio output, the low output present at line 234' in FIG. 17, in addition to enabling the reading out of the word "tone," passes into gates 292' and 247' so that the outputs therefrom on lines 293' and 248', respectively, become high so as to reset flip-flop 188' and to set flip-flop 190.

The next reference pulse then places flip-flop 188' in the "zero" state and flip-flop 190' in the "one" state so that each of the inputs to gate 242' becomes high and the output therefrom on line 243' becomes low. This low output is then fed into the gate 244' in FIG. 18, which acts as an inverter so that a high output emerges therefrom on line 245. This high output then triggers on amplifier 246' so that the phrase "the time" is read out of the audio output.

The low output signal on line 243' from gage 242' in FIG. 17 passes through NAND-gate 230' so that a high signal appears on the output 232' thereof and flip-flop 188' is placed in a set condition. Upon occurrence of the next pulse from the reference track of drum 21, the flip-flop 188' is placed so that its output is in the "one" state, and gate 251' then has each of its inputs in the high state. Thus, the output at line 252' will be low and this low signal is fed into inverting NAND-gate 253' in FIG. 18. The high output emerging therefrom on line 254' turns on amplifier 256' so that the phrase "will be" is read out of the audio output.

The low signal output at line 252' from gate 251' in FIG. 17 is also red into gate 239', the output of which at 241' is rendered high so that flip-flop 191' is reset. At the same time, the low signal output at line 252' is fed into NOR-gate 1020. Thus, the next reference pulse from the reference track of drum 21 will place the flip-flop 191' in the "zero" state so that the output on line 205' will become high. At this point the logic system must interrogate the clock in order to determine what the correct hour reading is and whether there are one-word hours or two-word hours.

Example of Operation of the 24-Hour Clock Embodiment When Time is 1 A.M. Exactly

If we assume at this point that the correct hour is one, each of the inputs to the one hour NAND-gate 741' from the flip-flops 162'-166' will be high so that the output from the gate 741' at line 1022 will be low. Each of the associated hour NAND gates will have at least one input low so that the gate 741' will be the only one having a low output. This low output is then fed through inverting NAND-gate 1024 so that the output on line 1025 therefrom becomes high. This high output is then fed into NAND-gate 1026, which has a second input 1002 that originates in FIG. 17 as the output from NAND-gate 1000. Because of the condition of the flip-flops 188'-191' in FIG. 17 at this point in the reading out of the message, each of the inputs to NAND-gate 1028 is high so that the output 1030 therefrom becomes low. This low output, in turn, is fed into the gate 1000 so that the output therefrom on line 1002 becomes high. Thus, both of the inputs 1002 and 1025 to the NAND-gate 1026 in FIG. 15 are high so that the output 1032 therefrom becomes low. This low output is then fed into one of the inputs of NAND-gate 1034 in FIG. 18. The other input 1036 thereto originates as the output from NAND-gate 128' in FIG. 13. Because the system, at this point, is not in phase state 3 the output from NAND-gate 1040 in FIG. 17 on line 1038 is low so that all of the inputs to gate 128' in FIG. 13 cannot be high and the output therefrom on line 1036 must be high. This high output is fed into the NAND-gate 1034 in FIG. 18, which together with the low input on line 1032, produces a high output on line 1042. This high output then triggers on amplifier 1044, which is associated with the track 22 on drum 21 and which has the word "one" thereon. As a result, the word "one" is read out through the audio output.

Simultaneously, the low output from gate 741' on line 1022 in FIG. 15 is fed into NAND-gate 1050 in FIG. 13 so that the output therefrom on line 1052 will always be high as long as the hour is 1 and the word "hours" will never be read out when the system moves to phase state 15 as long as the hour is 1. At the same time, when the hour is 1 the output on line 1025 from gate 1024 in FIG. 15 is high and this high signal is fed into gate 1054 on input line 1025. Because there are 0 minutes in the time of 1 a.m. exactly, the input lines 124' and 1056 from gate 429' in FIG. 14 to NOR-gate 1058 in FIG. 13 are both low so that the output therefrom on line 1059 is high. This high output on line 1059, in turn, inputs to gate 1045. The NOR-gate 1058, as all NOR gates, is characterized by having a low output if any input is high and by having a high output if all the inputs are low. Thus, as the drum 21 completes another revolution and because there are 0 minutes, the system moves to phase state 15. As a result, all of the inputs to gate 331' in FIG. 17 are high so that the output therefrom on line 332' becomes low. This, in turn, is inverted by gate 1060 so that the output therefrom on line 1062 becomes high. So when phase state 15 is reached, the output of gate 1054 on lines 1064 in FIG. 13 becomes low, and this low output is inverted by gate 1066 in FIG. 18 to produce a high output on line 1068 which then triggers on amplifier 1070 associated with the track 22 on drum 21 that has the word "hour" thereon. As a result, the word "hour" is read out through the audio output.

Because the system is in phase state 15 or box 38', the output on line 332' of FIG. 17 is low while the output on line 1072 from gate 1074 is high. There are 0 seconds so that the output from line 327' in FIG. 12 is high, and this feeds gate 1076 in FIG. 17 so that both inputs to gate 1076 are high when the system is in phase state 15 and when there are 0 seconds. Thus, the output on line 1078 from gate 1076 feeds into gate 292' so that the output therefrom on 293' becomes high and flip-flop 188' becomes reset.

Upon the occurrence of the next reference pulse from the drum 21, the flip-flop 188' is placed in the "zero" condition so that each of the inputs to NAND-gate 301' is high and the output therefrom on line 302' becomes low. One portion of this output is fed into gate 1080 so as to render its output on line 1082 high and so that the amplifier 1084 is triggered on and the word "exactly" is read out of the audio output 30.

The output 302' from NAND-gate 301' in FIG. 17 also leads into one input of gate 239' so that the output therefrom on line 241' becomes high and flip-flop 191' is reset. Upon the occurrence of the next reference pulse from the drum 21, the flip-flop 191' is placed in the "zero" condition so that each of the inputs to NAND-gate 404' is high and the output therefrom on line 406' becomes low. The output from gate 208' in FIG. 18 on line 209' thus becomes high and triggers on amplifier 211' which is associated with the track 32 on drum 21 which has "silence" thereon, and as a result, silence is read out through the audio output.

The output on line 406' from gate 404' in FIG. 17 is low and passes through inverting NAND-gate 1080 so that the output on line 1082 therefrom becomes high. Depending upon the length of time in which it has taken to read out the time, a variable delay will occur until the input 86' to gate 1084 in FIG. 17 becomes high as a result of a time change of 10 seconds from the counter including flip-flops 79'-83' in FIG. 12. When the time has changed, the output in line 1086 in FIG. 17 becomes low and the output from gate 1088 on line 1090 is high so that the output from gate 1092 on line 1094 becomes high so as to reset flip-flop 189'.

Upon the occurrence of the next reference pulse from the drum 21, the flip-flop 189' is placed in the "zero" condition so that each of the inputs to gate 233' is high and the output therefrom on line 234' becomes low. One portion of this output is fed into gate 353' so as to render its output on line 354' high and the amplifier 356' is triggered on so that a 750 cycle tone is read out of the audio output.

The low output on line 234' from gate 233' in FIG. 17 also feeds into one input of gate 2000 so that the output therefrom on line 2002 becomes high and flip-flop 190' becomes reset. When the next reference pulse from the drum 21 occurs the flip-flop 190' is placed in the "zero" output condition so that each of the inputs to gate 201' is in a high condition and so that the output on line 207' becomes low. From this point, the system operates in the manner previously described to read out the next correct time which would be 1 hour and 10 seconds.

Example of Operation of the 24-Hour Clock Embodiment When the Time is 21 Hours, 35 Minutes and 30 Seconds

A second example of time will now be described wherein the time is 21 hours, 35 minutes and 30 seconds in order to further describe additional portions of the 24 hour embodiment. The operation of the system will be identical with that previously set forth through mode or phase state 13, at which point the phrase "will be" will be read out from the audio output of the system. With reference to FIG. 16, when the time is from 20 to 24 hours the input 2020 to OR-gate 2022 is high since this input originates from the output of gate 2024 in FIG. 15 which has a high output for all times except when there are 0 hours. The other input 2026 to gate 2022 in FIG. 16 is low since flip-flop 1016 is in the "one" condition when there are from 20 to 24 hours. Thus, the output from OR-gate 2022 on line 2028 is low and is fed into OR-gate 2030. The second input to NOR-gate 2030 on line 2032, which originates from NAND-gate 2034 in FIG. 15, is also low since each of the inputs to the NAND-gate 2034 in FIG. 15 is high. Thus, the output from NOR-gate 2030 in FIG. 16 on line 2036 is high so that the output from NOR-gate 1020 in FIG. 17 on line 2038 is low. This is inverted by NAND-gate 2040 so that the output on line 2042 becomes high which in turn, causes the output from gate 2044 on line 2046 to be low so that flip-flop 189' is not set and so that the system will move from phase state 13 to phase state 5 rather than from phase state 13 to phase state 7 upon the occurrence of the next reference pulse.

Therefore, when the next reference pulse does occur from the reference track of drum 21, flip-flop 191' is placed in a "zero" state so that each of the inputs to gate 251' are high which results in a low output on line 252' therefrom. This low output causes a high output from gate 2044 so that flip-flop 189' is set. At the same time, the low output on line 252" is fed through inverting NAND-gate 1004 so that the output on line 1006 therefrom becomes high. This high output, in turn, is fed into NAND-gate 2050 in FIG. 15 which also has a second input 2020 thereto which is high. Thus, the output on line 2051 becomes low and is fed into NAND-gate 2054. This low input results in a high output therefrom on line 2052. This high output is then fed into NAND-gate 2056 in FIG. 16 which together with the high input thereto on line 2058 from flip-flop 1016 results in a low output on line 2060. This, in turn, is fed into NAND-gate 2062 so that the output 2064 therefrom is high. This high output triggers on amplifier 2066 in FIG. 18 so as to cause the word "twenty" to be read out from the audio output of the system.

Because flip-flop 189' has been placed in a set condition from the output of gate 2044 in FIG. 17, the next reference pulse from the drum 21 will place the flip-flops 188'-191' in a condition such that each of the inputs to gate 1028 is high. At this point the operation of the system is similar to that with respect to the example previously given when the time was 1 o'clock exactly. However, after the word "one" has been read out from the audio output, the system must make the decision whether to go to phase state 1, 3, or 15. When the system is in phase state 7, the output from gate 1028 on line 1030 in FIG. 17 is low and passes through inverting gate 2070 so that the output therefrom on line 2072 is high as it is fed into gate 1088. At the same time, the output from gate 2074 on line 2068 in FIG. 13 is high and is fed into gate 1088 in FIG. 17. Thus, both of the inputs to gate 2080 in FIG. 17 are high so that the output therefrom on line 2082 becomes low. This, in turn, results in a high output from gate 2000 on line 2002 so that flip-flop 190' is reset. The output from gate 1092 in FIG. 17 on line 1094 is also high since the input thereto on line 1086 is low as is the input 1090 thereto. This input is low since each of the inputs to gate 1088 is high, as has been previously explained with respect to inputs to 2068 and 2072. In addition, input 2074 to gate 1088 is high and originates from NOR-gate 2075 in FIG. 14. If there are two-word minutes to be read out then each of the inputs to gate 2077 in FIG. 14 will be high so that the output therefrom on line 2079 is low. Each of the inputs to gate 2077 is high since the input 2081 to the gates 2083, 2085, 2087 and 2089 is low since there are tens of minutes the output from gate 121' in FIG. 13 is thus low so as to make the output 2081 from inverting gate 2091 low. The other input 2093 to gate 2075 in FIG. 14 is also high since it originates from gate 2095 in FIG. 13, at least one input of which is low. Thus, all of the inputs to gate 1092 in FIG. 17 are low so that the output on line 1094 therefrom is high and flip-flop 189' is reset.

Upon the occurrence of the next reference pulse, flip-flops 189' and 190' are placed in the "zero" condition so that each of the inputs to NAND-gate 3000 is high and the output therefrom on line 3002 in FIG. 17 becomes low. This low signal is then fed into inverting NAND-gate 3004 so that the output on line 3006 therefrom becomes high. This high output, in turn, is fed into gate 3008 in FIG. 13 which has a second input 124' which is also high, and as a result, the output 3010 therefrom becomes low as it inputs to gate 3012. The presence of this low input together with the low input on line 3014 results in a higher output on line 3016. Each of the inputs to gate 3018 in FIG. 14 are then high so that the output on line 3020 therefrom becomes high. This high output then triggers on amplifier 3026 so as to cause the word "thirty" to be read out from the audio output of the system.

Upon the occurrence of the next pulse from the reference track of drum 21, flip-flop 189' is placed in the "one" condition so that each of the inputs to NAND-gate 351' are high and the output on line 352' therefrom becomes low. This low output is fed into gate 222' so that the output therefrom on line 221' becomes high and flip-flop 191' is set. At the same time, the low output on line 352' is inverted by gate 1040 to provide a high output on line 1038. This high output is then fed into gate 3028 in FIG. 13 so that all of the inputs thereto are high and the output therefrom on line 3030 becomes low. This low output is then fed into gate 3032 in FIG. 18 so that the output 3034 therefrom becomes high. This high output then triggers on amplifier 3036 so that the word "five" is read out from the audio output of the system.

The low output on line 352' from gate 351' in FIG. 17 also passes into gate 1074 so that the output therefrom on line 1072 becomes high. This high output is then fed into gate 3028 together with the low output from line 402' to provide a high output on line 3030. This high output, in turn, is fed into gate 2000 so that the output therefrom on line 2002 is low and flip-flop 190' is not set.

Upon the occurrence of the next reference pulse from the drum 21, flip-flops 188'-191' are placed in a condition such that flip-flop 191' is in the "one" condition and each of the inputs to gate 343' is high so that the output therefrom on line 344' becomes low. This low output passes into gate 292' to result in a high output therefrom on line 293' so that flip-flop 188' is reset. Simultaneously, the output on line 344' is fed through gate 3040 in FIG. 18 so that the output therefrom on line 3042 becomes high. This high output then triggers on amplifier 3044 so that the word "and" is read out from the audio output.

Upon the occurrence of the next reference pulse from the drum 21, flip-flop 188' is placed in the "zero" condition and each of the inputs to gate 413' becomes high so that the output therefrom on line 414' becomes low. This low output passes into gate 239' so that the output therefrom on line 241' becomes high and flip-flop 191' is reset. At the same time, the low output on line 414' passes through gate 3046 so that the output therefrom on line 3048 becomes high. As a result, each of the inputs to gate 103' in FIG. 12 is high and the output therefrom on line 723' becomes low. This low output then passes into gate 3022 in FIG. 18 so that the output therefrom on line 3024 becomes high. This triggers on amplifier 3026 and the word "thirty" is read out from the audio output.

UPon the occurrence of the next reference pulse from the drum 21, flip-flop 191' is placed in the "zero" position so that each of the inputs to gate 411' is high and the output therefrom on line 412' becomes low. This low output passes into gate 247' so that the high output therefrom on line 248' sets flip-flop 190'. At the same time, the low output on line 412' passes into gate 3061 in FIG. 18 so that the output therefrom on line 3063 becomes high. This high output then triggers on amplifier 3065 so that the word "seconds" is read out of the audio output of the system.

Upon the occurrence of the next reference pulse, the system is placed into phase state 6 so that each of the inputs to gate 404' is high and the system then operates in a manner similar to that described in the previous example until the system is returned ultimately to phase state 0, at which time the process repeats to read out the next correct time.

Because the successful operation of the 24-hour clock embodiment and of the 12 -hour clock embodiment depends upon the accuracy of the digital clock, it is necessary to provide a means for setting the clock to the correct time as desired. One example of such a means is represented in FIG. 19, which is similar to that illustrated in FIG. 9 for the 12 -hour clock embodiment with the exception that the correct time is set into the switches of FIG. 19 to the nearest minute. The switches of FIG. 19 include four multideck rotary switches 601', 606', 603' and 604'. The switch 601' is comprised of five decks 4031-4035 wherein each deck includes 12 contacts located around the circumference thereof on both the top and bottom. These contacts are represented by the numbers 1-12 on the inside portion of the decks 4031-4035. The operation of the multideck rotary switches in FIG. 19 is similar to that with respect to FIG. 9 previously described herein so that a detailed description of the operation of the switches of FIG. 19 will be obvious to one of ordinary skill in the art after having read and understood the function of the multideck switches of FIG. 9.

With reference now to FIG. 20, there is shown a subsystem which may be associated with the 12 -hour or 24 -hour clock embodiments; however, the subsystem of FIG. 20 is shown as it may be associated with the 24 -hour clock embodiment for the sake of explanation.

This subsystem allows the audio clock to by synchronized by an external clock signal and includes an input line at 4046 to receive external sync or clock pulses. As only one example, the incoming sync or clock pulses may reach a positive-going 24 -volt level every other minute, and during the intervening minutes the pulse may reach a negative-going 24-volt level. Both the positive-going and negative-going pulses are then converted to positive-going signals at a voltage level suitable for use in the system by the combined action of the positive-negative pulse detector 4047 and the pulse shaper-level shifters 4048 and 4049. These signals are then NANDED by NAND-gate 4050 and the resulting pulses are utilized to sync the digital clock each minute via the NOR-gates 4060-4065. Flip-flop 4066 is utilized by the switches illustrated in FIG. 19. The NOR-gates 4060-4065 accept inputs each minute from the external sync or clock pulse or accept the preset signal from the flip-flop 4066 in operating to synchronize the audio clock to the external clock signal.

With reference now to FIG. 21, there is illustrated a binary coded decimal output option which may be utilized with either the 12 -hour or 24 -hour clock embodiments and wherein the plurality of NAND gates illustrated are utilized to decode the time as presented by the digital clock so as to provide a decimal output which is representative of the correct time. For example, the NAND-gates 5026-5039 in FIG. 21 are variously coupled to the counter in FIG. 12 which is composed of flip-flops 87'-89'. If, for example, the correct time includes "ten seconds" then both of the inputs 92' and 97' to NAND-gate 5026 in FIG. 21 would be high so that the output therefrom would be low. This, in turn, would result in a high output on line 5010, which output could then be fed into a visual display or other type of display device 5050 to indicate the presence of "ten seconds." Each grouping of NAND gates in FIG. 21 operates in a similar manner and is utilized in the same way to represent a binary coded decimal output of the correct time. Each of the outputs 5010-5025 may be fed into the visual display device 5050, which may be any one of a number of known binary coded decimal visual displays.

The announcing systems and associated subsystems herein disclosed provide a compact, reliable, long life and inexpensive electronic means for announcing the time every 10 seconds. Although the system has been described specifically in conjunction with a telephone system and with a binary coded decimal output, it should be understood that the announcing systems could be adapted for use with many types of electronic devices. Also, the system has been described utilizing a counter arrangement as a digital clock, but it should be understood that other timing means, such as radio station W W V, could be used. Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as described.