REGISTER CONTROL SYSTEM AND METHOD
United States Patent 3624359
A mark discriminator circuit for a plural station web apparatus wherein marks are cyclically applied in line on a web at successive stations, and a scanner produces a series of scanner pulses in each repeat interval, the circuit being operable to respond to a pair of such scanner pulses whose spacing is a measure of a registration condition of the web.
US Patent References:
Adjustment circuit for registration control device
Frommer - April 1962 - 3031118
Device for checking longitudinal registration on machines for performing repetitive operations on a continuous band
Dall'Oglio et al. - December 1962 - 3068787
Detector system for plural unit printing press
Fath et al. - June 1965 - 3191530
Adjustment circuit for registration control device
Frommer - April 1962 - 3031118
Device for checking longitudinal registration on machines for performing repetitive operations on a continuous band
Dall'Oglio et al. - December 1962 - 3068787
Detector system for plural unit printing press
Fath et al. - June 1965 - 3191530
Application Number:
04/873048
Publication Date:
11/30/1971
Filing Date:
10/31/1969
View Patent Images:
Export Citation:
Assignee:
Hurletron Incorporated (Danville, IL)
Primary Class:
Other Classes:
377/16, 340/675, 101/184, 226/28
International Classes:
B65H23/04; B65H23/22; B41F9/02
Field of Search:
226/2,27,28,45,100 340/259 101/181,183,184 235/61.11,92MP 250/219DR
Primary Examiner:
Robinson, Thomas A.
Claims:
I claim as my invention
1. A plural station web system wherein marks are cyclically applied in line on a web at successive stations, and wherein scanning of the marks for sensing the registration condition of the web at a given station produces a series of successive scanner pulses in each repeat interval, said system comprising
2. A system according to claim 1 with said scanner pulse circuit including selector switch means having respective switching positions corresponding to successive scanner pulse positions in the series, said switch means being adjustable to condition said scanner pulse circuit to respond to a selected pair of said scanner pulses pertinent to the registration condition at the given station.
3. A system according to claim 2 with said selector switch means being operable to condition said scanner pulse circuit to respond to any pulse of said series as representing a pertinent mark applied to the web in advance of the given station and select any other pulse of said series as representing the mark applied to the web at the given station.
4. A system according to claim 1 with said scanner pulse circuit comprising reset means for responding to encoder pulses produced by uniform increments of movement of the web and automatically operable to cyclically reset the scanner pulse circuit to an initial condition at intervals related to the speed of movement of the web past the station thereby to enable repeated sampling of the registration condition of the web at said station.
5. A system according to claim 1 with said scanner pulse circuit comprising scanner pulse responsive means shiftable from an initial condition to a succession of further conditions in response to successive scanner pulses of the series, and reset means for cyclically restoring said pulse responsive means to said initial condition in advance of receipt of each series of said scanner pulses.
6. A system according to claim 5 with said pulse responsive means comprising a shift register wherein successive stages are actuated in response to successive pulses until all stages have been actuated, each stage remaining in actuated condition until reset to initial condition, and said shift register after receipt of a predetermined number of pulses being nonresponsive to any further pulses received prior to resetting of the shift register to the initial condition.
7. A system according to claim 6 with said reset means comprising a counter circuit including a counter responsive to encoder pulses produced by uniform increments of movement of the web, said counter circuit being operative when the counter reaches a predetermined count value to reset the shift register to said initial condition and to reset said counter to an initial count, said counter circuit being inherently operable to place said scanner pulse circuit in proper operating condition irrespective of which scanner pulse of the series is first received by the scanner pulse circuit at initial start up of the system.
8. A mark discriminator system for a web having a series of marks at each successive repeat length therealong including one mark substantially representing a reference position on the web and a second mark whose position relative to the one mark is a function of registration condition of the web at a given station, said system comprising input means for receiving scanner pulses which are responsive to the scanning of the respective marks on the web, a scanner pulse circuit connected to said input means to receive a series of scanner pulses in each repeat interval, said circuit comprising digital logic means assuming successive conditions in response to the successive scanner pulses of the series and selectively adjustable to transmit respective output signals in response to the respective scanner pulses corresponding to said one mark and to said second mark, the output signals thereby providing a measure of the register condition of the web.
9. A system in accordance with claim 8 with said digital logic means being resettable to an initial condition and being responsive to successive scanner pulses thereafter received up to a predetermined maximum number of scanner pulses, but being nonresponsive to scanner pulses in excess of said predetermined maximum number until reset to said initial condition.
10. A system in accordance with claim 9 further comprising a counter circuit for counting encoder pulses produced by uniform increments of movement of the web and operable in response to a first of said output signals to begin a counting cycle and operable upon reaching a predetermined count which predetermined count is reached after a time interval which is greater than the time interval between said output signals, to reset said digital logic means to said initial condition, said counter circuit being inherently operable to place said digital logic means in proper operating condition irrespective of which scanner pulse of said series is first received by said scanner pulse circuit at initial startup of the system.
11. In a plural station web system wherein first, second, third and fourth marks are cyclically applied in line on a common channel of a web at respective first, second, third and fourth stations, and wherein scanning of the marks for sensing the registration condition of the web produces first, second, third and fourth scanner pulses in each of successive repeat intervals, the improvement comprising
12. In a plural station web system wherein first, second and third marks are cyclically applied in line on a common channel of a web at respective first, second and third stations, and wherein scanning of the marks at a fourth station for sensing the register condition of the web produces at least first, second and third scanner pulses in each of successive repeat intervals, the improvement comprising
13. In a plural station web system in accordance with claim 12, the improvement further comprising a digital logic circuit resettable to an initial logical switching condition and being responsive to successive scanner pulses thereafter received up to a predetermined maximum number of scanner pulses, but being nonresponsive to scanner pulses in excess of said predetermined maximum number until reset to said initial logical switching condition.
14. In a plural station web system in accordance with claim 13, the improvement further comprising a counter circuit for counting encoder pulses produced by uniform increments of movement of the web and operable in response to one of said first and second output signals to begin a counting cycle and operable upon reaching a predetermined count which predetermined count is reached after a time interval which is greater than the time interval between said first and second output signals, to reset said digital logic circuit to said initial logical switching condition, said counter circuit being inherently operable to place said digital logic circuit in proper synchronism with said series of scanner pulses irrespective of which scanner pulse of the series is first received at initial start up of the system.
15. The method of sensing web registration at a given station which comprises
1. A plural station web system wherein marks are cyclically applied in line on a web at successive stations, and wherein scanning of the marks for sensing the registration condition of the web at a given station produces a series of successive scanner pulses in each repeat interval, said system comprising
2. A system according to claim 1 with said scanner pulse circuit including selector switch means having respective switching positions corresponding to successive scanner pulse positions in the series, said switch means being adjustable to condition said scanner pulse circuit to respond to a selected pair of said scanner pulses pertinent to the registration condition at the given station.
3. A system according to claim 2 with said selector switch means being operable to condition said scanner pulse circuit to respond to any pulse of said series as representing a pertinent mark applied to the web in advance of the given station and select any other pulse of said series as representing the mark applied to the web at the given station.
4. A system according to claim 1 with said scanner pulse circuit comprising reset means for responding to encoder pulses produced by uniform increments of movement of the web and automatically operable to cyclically reset the scanner pulse circuit to an initial condition at intervals related to the speed of movement of the web past the station thereby to enable repeated sampling of the registration condition of the web at said station.
5. A system according to claim 1 with said scanner pulse circuit comprising scanner pulse responsive means shiftable from an initial condition to a succession of further conditions in response to successive scanner pulses of the series, and reset means for cyclically restoring said pulse responsive means to said initial condition in advance of receipt of each series of said scanner pulses.
6. A system according to claim 5 with said pulse responsive means comprising a shift register wherein successive stages are actuated in response to successive pulses until all stages have been actuated, each stage remaining in actuated condition until reset to initial condition, and said shift register after receipt of a predetermined number of pulses being nonresponsive to any further pulses received prior to resetting of the shift register to the initial condition.
7. A system according to claim 6 with said reset means comprising a counter circuit including a counter responsive to encoder pulses produced by uniform increments of movement of the web, said counter circuit being operative when the counter reaches a predetermined count value to reset the shift register to said initial condition and to reset said counter to an initial count, said counter circuit being inherently operable to place said scanner pulse circuit in proper operating condition irrespective of which scanner pulse of the series is first received by the scanner pulse circuit at initial start up of the system.
8. A mark discriminator system for a web having a series of marks at each successive repeat length therealong including one mark substantially representing a reference position on the web and a second mark whose position relative to the one mark is a function of registration condition of the web at a given station, said system comprising input means for receiving scanner pulses which are responsive to the scanning of the respective marks on the web, a scanner pulse circuit connected to said input means to receive a series of scanner pulses in each repeat interval, said circuit comprising digital logic means assuming successive conditions in response to the successive scanner pulses of the series and selectively adjustable to transmit respective output signals in response to the respective scanner pulses corresponding to said one mark and to said second mark, the output signals thereby providing a measure of the register condition of the web.
9. A system in accordance with claim 8 with said digital logic means being resettable to an initial condition and being responsive to successive scanner pulses thereafter received up to a predetermined maximum number of scanner pulses, but being nonresponsive to scanner pulses in excess of said predetermined maximum number until reset to said initial condition.
10. A system in accordance with claim 9 further comprising a counter circuit for counting encoder pulses produced by uniform increments of movement of the web and operable in response to a first of said output signals to begin a counting cycle and operable upon reaching a predetermined count which predetermined count is reached after a time interval which is greater than the time interval between said output signals, to reset said digital logic means to said initial condition, said counter circuit being inherently operable to place said digital logic means in proper operating condition irrespective of which scanner pulse of said series is first received by said scanner pulse circuit at initial startup of the system.
11. In a plural station web system wherein first, second, third and fourth marks are cyclically applied in line on a common channel of a web at respective first, second, third and fourth stations, and wherein scanning of the marks for sensing the registration condition of the web produces first, second, third and fourth scanner pulses in each of successive repeat intervals, the improvement comprising
12. In a plural station web system wherein first, second and third marks are cyclically applied in line on a common channel of a web at respective first, second and third stations, and wherein scanning of the marks at a fourth station for sensing the register condition of the web produces at least first, second and third scanner pulses in each of successive repeat intervals, the improvement comprising
13. In a plural station web system in accordance with claim 12, the improvement further comprising a digital logic circuit resettable to an initial logical switching condition and being responsive to successive scanner pulses thereafter received up to a predetermined maximum number of scanner pulses, but being nonresponsive to scanner pulses in excess of said predetermined maximum number until reset to said initial logical switching condition.
14. In a plural station web system in accordance with claim 13, the improvement further comprising a counter circuit for counting encoder pulses produced by uniform increments of movement of the web and operable in response to one of said first and second output signals to begin a counting cycle and operable upon reaching a predetermined count which predetermined count is reached after a time interval which is greater than the time interval between said first and second output signals, to reset said digital logic circuit to said initial logical switching condition, said counter circuit being inherently operable to place said digital logic circuit in proper synchronism with said series of scanner pulses irrespective of which scanner pulse of the series is first received at initial start up of the system.
15. The method of sensing web registration at a given station which comprises
Description:
SUMMARY OF THE INVENTION
This invention relates to a plural station web apparatus and particularly to a mark discriminator circuit for receiving a series of scanner pulses produced by scanning of respective marks on a web and for responding to a pair of such scanner pulses whose spacing provides a measure of a registration condition of the web.
It is an object of the present invention to provide a novel system and method for sensing a register condition of a web.
Another object of the invention is to provide a plural station web apparatus wherein the sensing of the register condition of the web at each station can be carried out without the need for a position detector or similar signal generator mechanically driven in step with the cyclical operation at the station.
A further object of the invention is to provide a plural station web apparatus wherein a single scanner together with a mark discriminator circuit provides a pair pulses whose spacing is a measure of a register condition of the web.
A still further object of the invention resides in the provision of a plural station web apparatus wherein setup is accomplished by the adjustment of electrical switch means to select a desired pair of marks on the web irrespective of their positions in a series of marks produced by the successive stations.
A more general object of the invention relates to the provision of a highly flexible web register sensing system and method capable of economical implementation and of convenient installation with a minimum expenditure of time and effort.
Other objects, features and advantages of the invention will be readily apparent from the following description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings, although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagrammatic indication of a plural station web apparatus in accordance with the present invention;
FIG. 2 is a circuit diagram showing a preferred mark discriminator system in accordance with the present invention; and
FIG. 3 is a wave form diagram useful in explaining the operation of the system of FIG. 2, and includes FIGS. 3A-3L.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 illustrates a multistation printing apparatus wherein a web 10 moves in the direction indicated by arrow 11 past a succession of printing stations such as indicated at A, B, C and D. Printing cylinders such as represented at 12-15 are driven from a line shaft diagrammatically indicated at 16. Also driven by the line shaft is a rotary encoder device 17 which may, for example, supply a total of 30,000 encoder pulses for each revolution of the cylinders 12-15. Since the web is driven essentially in step with the rotary motion of the cylinders 12-15, the successive encoder pulses represent successive uniform increments of movement of the web.
Considering the station D, for example, a circumferential web registration control device may act on the web at the region indicated at 20. In accordance with the present invention, each of the stations A, B, C and D may print a mark on a common channel or "gutter" on a given side of the web 10, and a suitable scanner 22 may be arranged to scan the marks on the channel and to provide a series of scanner pulses in response to the successive marks on the web at each repeat interval therealong. In a typical system of this type the marks printed by the successive stations A-D can appear in any random order. Thus referring to FIG. 3A, the first pulse of each series from scanner 22 may be produced by a mark printed at station A, the second pulse may be produced by a mark at station C, the third pulse may be produced by the mark printed at station D and the fourth pulse of the series may result from a mark printed at station B in FIG. 1. For the sake of example, it may be desired to compare the marks printed by stations C and D as a measure of the registration condition at station D. The mark printed at station C is applied in advance of the control point indicated at 20, and may be considered the controlled mark, while the mark printed by station D will serve as a reference mark representing the operation of cylinder 15 at station D.
FIG. 2 illustrates a preferred mark discriminator circuit for receiving the series of pulses such as indicated at 25-28 at input line 30 and for responding to a desired pair of such pulses such as pulses 26 and 27, for example. Since the marks are applied at the respective stations in each cycle of operation, that is in each revolution of the cylinders 12-15, the scanner 22 will provide successive series of pulses such as the pulses 25-28 followed by a further series of pulses such as indicated at 25'-28' at input line 30. For example the scanner pulses 25 and 25' would represent the successive pulses at the scanner 22 produced in response to the successive marks applied by cylinder 12, while the scanner pulses 26 and 26' would be produced by the successive marks printed by cylinder 14 at station C, and so forth.
Referring to FIGS. 1 and 2, the electrical output from scanner 22 is shown as being connected via conductor 30 with a series of conductors 31-34 in FIG. 2, while electrical conductor 35 leading from encoder 17 is shown as being connected to the input of a counter component 36 of the circuit of FIG. 2.
FIG. 2 shows a scanner pulse circuit including shift register 40, selector switches 41 and 42 and logical circuitry including gates 43-46 and D-type flip-flop 47 for supplying a first output signal at line 48 in response to the first selected scanner pulse and for supplying an output signal at line 49 in response to the second selected scanner pulse. The scanner pulse circuit further includes reset means including counter 36, gates 51 and 52 and D-type flip-flop 53.
The shift register 40 includes successive stages 55, 56 and 57 having respective Q output conductors 62-64 connected to terminals numbered 2, 3 and 4, respectively of the switches 41 and 42. In the illustrates circuit, stages 55-57 are considered to be initially in a reset or logical zero condition wherein, for example, the output lines 62-64 are at ground potential. As represented at 66 in FIG. 3 B, the trailing edge of the first pulse 25 in normal operation will serve to set stage 55 to the logical one or set condition in which condition output line 62 may be at a predetermined positive potential such as represented by the symbol +V on the drawings. Thus with stage 55 activated the J input of stage 56 is at the predetermined positive potential and the K input of stage 56 is at ground potential, conditioning the stage 56 to respond to the next input pulse 26. The change of state of the second stage 56 in response to the trailing edge of scanner pulse 26 is indicated at 67 in FIG. 3C. Similarly the third scanner pulse 27 at its trailing edge will produce the change of state indicated at 68 for output conductor 64 of the third stage 57. In the illustrated embodiment, the fourth pulse 28 will have no effect on the condition of the shift register 40 since each of the stages 55-57 is already in the activated condition.
With the selector switches 41 and 42 in positions number 2 and number 3, respectively as shown in FIG. 2, the setting of the first stage 55 of shift register 40 as represented at 66 in FIG. 3B will result in the transmission of the predetermined positive potential via switch 41 to one input of NAND gates 43 and 45. The result is a ground potential output from gate 45 and a predetermined positive potential output as indicated at 70, FIG. 3E from gate 46, conditioning the D-type flip-flop 47 to respond to the next scanner pulse 26 which is transmitted to the clock input of flip-flop 47 via conductors 30 and 34. Thus as represented at wave form 71 in FIG. 3F, the Q output of flip-flop 47 provides an output signal 71 in response to the first selected pulse of the series 25-28. Similarly, for the illustrated embodiment, with selector switch 42 in the number 3 position, the activation of the second stage 56 supplies a predetermined positive potential to output conductor 63 which is connected to the second input of gate 43, driving the output of gate 43 to ground potential, and driving the outputs of gates 44 and 45 to the predetermined positive potential. Thus the output of gate 46 shifts to ground potential, and flip-flop 47 responds to pulse 27 to provide an output signal in the form of a negative transition as indicated at 72 in FIG. 3F at output conductor 48.
The positive transition at output conductor 48 causes the D-type flip-flop 53 to assume a logical 1-condition. The transition at output conductor 74 of flip-flop 53 (the Q complement output) is represented at 75 in FIG. 3H. (The transition at the Q output of flip-flop 53 is indicated at 76 in FIG. 3G.)
Conductor 74 is connected to a control terminal of binary counter 36 such that when the potential of conductor 74 is at the ground potential level, the counter is released and begins counting encoder pulses supplied at input line 35. By way of example, conductor 80 may be connected to the output of the 11th binary stage of counter 36 so as to provide a predetermined positive potential when this stage is in a logical 1-condition while output conductor 81 may be connected with the output of the 15th binary stage of the counter so as to provide a predetermined positive potential when this stage is in a logical 1-condition. FIG. 3I represents the potential at output conductor 80, while FIG. 3J represents the output potential at conductor 81. Thus, for example, transition 82 occurs 1024 encoder pulses after the transition 75, while transition 83 occurs at a count of 16384 encoder pulses after the transition 75. At the instant that conductor 81 is exhibiting the transition 83, conductor 80 will be exhibiting a potential transition as indicated at 84 in FIG. 3I. After a further 1024 encoder pulses, output conductor 80 will shift to a predetermined positive potential as indicated at 85 in FIG. 3I. The positive potentials at conductors 80 and 81 provide a ground potential output from gate 52, causing the clearing of flip-flop 53. The return of conductor 74 to a high or positive potential as indicated at 86 serves to set the binary counter 36 to its initial count of zero and hold the counter in this state. The output of gate 52 is indicated at 87 in FIG. 3K. FIG. 3L indicates the output of gate 51 which serves to reset the shift register 40 and flip-flop 47 during the interval indicated at 88 in FIG. 3L.
The circuit of FIG. 2 further includes control pulse transmission means for coupling the output of the scanner pulse circuit to a web control and/or error display system such as represented by component 90. By way of example, the component 90 may correspond to the system disclosed in a copending application Ser. No. 722,095 filed Apr. 17, 1968, and assigned to the same assignee as the present application. For the sake of this particular example, a "one shot" circuit is indicated at 91 having its input connected to conductor 48 for transmitting a first control pulse to the system 90 which may correspond to the position detector signal (which is supplied to a conductor number 44 in the fourth figure of the copending application). Similarly a "one shot" circuit 92 is shown as having its input connected to the conductor 49 so as to supply a second control pulse to the system 90 (which may correspond to the scanner pulse supplied to conductor number 56 shown in the fourth figure of said copending application). In this event, the system 90 may control a compensator motor acting at the region 20 in FIG. 1 (and corresponding to the compensator device indicated for station D in the first figure of the copending application).
It will be apparent to those skilled in the art from a consideration of the drawings that the position of the selector switch 41 may determine the position number of either the first or second scanner pulse which is responded to by the circuit of FIG. 2, while the position number of the second selector switch 42 may determine the position number of the other scanner pulse of the series which is responded to by the circuit of FIG. 2.
If stations A-D print with yellow, red, blue and black ink, respectively, it will be understood that selector switch 41 may be set by the operator to the position of the blue mark in the series of marks on a web, while the selector switch 42 may be set to the position of the black mark of the web, irrespective of which appears first, thus greatly simplifying the setup procedure from the standpoint of the operator.
It will also be apparent to those skilled in the art from a consideration of the drawings that if when the system is initially started up, the first pulse appearing at input 30 is a different pulse than the first pulse of the series, the operation of the circuit is such that after a few cycles of operation, normal operation will automatically be achieved. Similarly if a spurious scanner pulse should be produced during normal operation, for example as a result of ink inadvertently dropping on the web or a defect in the web, the result would be only a momentary loss of synchronism, and the circuit would automatically restore proper operation after a few cycles. In order for the illustrated system to be capable of automatic start up and automatic resynchronization, there should be a clear track for approximately one half the repeat length in advance of the desired series of marks corresponding to pulses 25-28. If the required clear track in not available, resort can be had to electronic or mechanical gating techniques to maintain synchronization. It will be observed however that spurious pulses following pulse 28 and prior to the resetting of the shift register 40 as represented at 88 in FIG. 3L will have no adverse effect on the system since shift register 40 will not respond to pulses during this interval.
For the sake of a specific example, the J K flip-flop 55.57 may be type S N 7473 available from Texas Instruments Incorporated, and the type D flip-flops 47 and 53 may be type S N 7474 of the same company. It is believed evident that one skilled in the art can readily provide a binary counter meeting the requirements for the counter 36.
SUMMARY OF OPERATION
In setting up the system, the operator may adjust the selector switch 41 to a position corresponding to the position of the mark printed by station C, FIG. 1 (for example the blue mark), while the selector switch 42 may be set to a position corresponding to the position of the mark printed by the station D on the web (for example the black mark). Thus, if the sequence of marks on the web were black, red, yellow, and blue, for example, selector switch 41 would be set to position number four, while selector switch 42 would be set to position number one. Thus setup is an extremely simple matter from the standpoint of the operator.
Once stable operation of the system has been achieved, which automatically occurs regardless of the startup point, after a few cycles, the sequence of operation of the circuitry is as represented in FIG. 3 for the positions of the selector switches 41 and 42 as shown in FIG. 2. In each cycle of operation, a positive going transition 71 occurs at output line 48 at the position of the pulse selected by switch 41, and a positive going transition occurs at output line 49 (corresponding in time to transition 72 in FIG. 3F) in response to the second selected pulse as determined by the position of selector switch 42. As indicated by components 91 and 92, these transitions or output signals may be utilized to generate first and second control pulses at the input to the system 90 whose spacing is a measure of the register condition at the station D, FIG. 1. The system 90 may apply corrections at region 20, FIG. 1, should the spacing between the control pulses signify an error in the register condition at the station. By properly setting up the system, it is a very simple matter for the operator to insure that the control corrections applied at region 20 will be in the direction to reduce any registration error, should the present invention be utilized to control the register condition.
It should be emphasized that while the illustrated system is preferred and uniquely advantageous in certain applications such as rotogravure offset printing of newspapers and the like, certain simplifications of the illustrated circuit will be possible particularly for applications where the position of the mark printed by one of the stations can be conveniently predetermined, for example. It will further be evident that the invention is applicable to web apparatus having different numbers of stations than the apparatus specifically illustrated, and the application of the concepts of the invention to different numbers of marks in a common channel will be apparent to those skilled in the art from the foregoing disclosure.
It will be apparent that many other modifications and variations may be affected without departing from the scope of the novel concepts of the present invention.
This invention relates to a plural station web apparatus and particularly to a mark discriminator circuit for receiving a series of scanner pulses produced by scanning of respective marks on a web and for responding to a pair of such scanner pulses whose spacing provides a measure of a registration condition of the web.
It is an object of the present invention to provide a novel system and method for sensing a register condition of a web.
Another object of the invention is to provide a plural station web apparatus wherein the sensing of the register condition of the web at each station can be carried out without the need for a position detector or similar signal generator mechanically driven in step with the cyclical operation at the station.
A further object of the invention is to provide a plural station web apparatus wherein a single scanner together with a mark discriminator circuit provides a pair pulses whose spacing is a measure of a register condition of the web.
A still further object of the invention resides in the provision of a plural station web apparatus wherein setup is accomplished by the adjustment of electrical switch means to select a desired pair of marks on the web irrespective of their positions in a series of marks produced by the successive stations.
A more general object of the invention relates to the provision of a highly flexible web register sensing system and method capable of economical implementation and of convenient installation with a minimum expenditure of time and effort.
Other objects, features and advantages of the invention will be readily apparent from the following description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings, although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagrammatic indication of a plural station web apparatus in accordance with the present invention;
FIG. 2 is a circuit diagram showing a preferred mark discriminator system in accordance with the present invention; and
FIG. 3 is a wave form diagram useful in explaining the operation of the system of FIG. 2, and includes FIGS. 3A-3L.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 illustrates a multistation printing apparatus wherein a web 10 moves in the direction indicated by arrow 11 past a succession of printing stations such as indicated at A, B, C and D. Printing cylinders such as represented at 12-15 are driven from a line shaft diagrammatically indicated at 16. Also driven by the line shaft is a rotary encoder device 17 which may, for example, supply a total of 30,000 encoder pulses for each revolution of the cylinders 12-15. Since the web is driven essentially in step with the rotary motion of the cylinders 12-15, the successive encoder pulses represent successive uniform increments of movement of the web.
Considering the station D, for example, a circumferential web registration control device may act on the web at the region indicated at 20. In accordance with the present invention, each of the stations A, B, C and D may print a mark on a common channel or "gutter" on a given side of the web 10, and a suitable scanner 22 may be arranged to scan the marks on the channel and to provide a series of scanner pulses in response to the successive marks on the web at each repeat interval therealong. In a typical system of this type the marks printed by the successive stations A-D can appear in any random order. Thus referring to FIG. 3A, the first pulse of each series from scanner 22 may be produced by a mark printed at station A, the second pulse may be produced by a mark at station C, the third pulse may be produced by the mark printed at station D and the fourth pulse of the series may result from a mark printed at station B in FIG. 1. For the sake of example, it may be desired to compare the marks printed by stations C and D as a measure of the registration condition at station D. The mark printed at station C is applied in advance of the control point indicated at 20, and may be considered the controlled mark, while the mark printed by station D will serve as a reference mark representing the operation of cylinder 15 at station D.
FIG. 2 illustrates a preferred mark discriminator circuit for receiving the series of pulses such as indicated at 25-28 at input line 30 and for responding to a desired pair of such pulses such as pulses 26 and 27, for example. Since the marks are applied at the respective stations in each cycle of operation, that is in each revolution of the cylinders 12-15, the scanner 22 will provide successive series of pulses such as the pulses 25-28 followed by a further series of pulses such as indicated at 25'-28' at input line 30. For example the scanner pulses 25 and 25' would represent the successive pulses at the scanner 22 produced in response to the successive marks applied by cylinder 12, while the scanner pulses 26 and 26' would be produced by the successive marks printed by cylinder 14 at station C, and so forth.
Referring to FIGS. 1 and 2, the electrical output from scanner 22 is shown as being connected via conductor 30 with a series of conductors 31-34 in FIG. 2, while electrical conductor 35 leading from encoder 17 is shown as being connected to the input of a counter component 36 of the circuit of FIG. 2.
FIG. 2 shows a scanner pulse circuit including shift register 40, selector switches 41 and 42 and logical circuitry including gates 43-46 and D-type flip-flop 47 for supplying a first output signal at line 48 in response to the first selected scanner pulse and for supplying an output signal at line 49 in response to the second selected scanner pulse. The scanner pulse circuit further includes reset means including counter 36, gates 51 and 52 and D-type flip-flop 53.
The shift register 40 includes successive stages 55, 56 and 57 having respective Q output conductors 62-64 connected to terminals numbered 2, 3 and 4, respectively of the switches 41 and 42. In the illustrates circuit, stages 55-57 are considered to be initially in a reset or logical zero condition wherein, for example, the output lines 62-64 are at ground potential. As represented at 66 in FIG. 3 B, the trailing edge of the first pulse 25 in normal operation will serve to set stage 55 to the logical one or set condition in which condition output line 62 may be at a predetermined positive potential such as represented by the symbol +V on the drawings. Thus with stage 55 activated the J input of stage 56 is at the predetermined positive potential and the K input of stage 56 is at ground potential, conditioning the stage 56 to respond to the next input pulse 26. The change of state of the second stage 56 in response to the trailing edge of scanner pulse 26 is indicated at 67 in FIG. 3C. Similarly the third scanner pulse 27 at its trailing edge will produce the change of state indicated at 68 for output conductor 64 of the third stage 57. In the illustrated embodiment, the fourth pulse 28 will have no effect on the condition of the shift register 40 since each of the stages 55-57 is already in the activated condition.
With the selector switches 41 and 42 in positions number 2 and number 3, respectively as shown in FIG. 2, the setting of the first stage 55 of shift register 40 as represented at 66 in FIG. 3B will result in the transmission of the predetermined positive potential via switch 41 to one input of NAND gates 43 and 45. The result is a ground potential output from gate 45 and a predetermined positive potential output as indicated at 70, FIG. 3E from gate 46, conditioning the D-type flip-flop 47 to respond to the next scanner pulse 26 which is transmitted to the clock input of flip-flop 47 via conductors 30 and 34. Thus as represented at wave form 71 in FIG. 3F, the Q output of flip-flop 47 provides an output signal 71 in response to the first selected pulse of the series 25-28. Similarly, for the illustrated embodiment, with selector switch 42 in the number 3 position, the activation of the second stage 56 supplies a predetermined positive potential to output conductor 63 which is connected to the second input of gate 43, driving the output of gate 43 to ground potential, and driving the outputs of gates 44 and 45 to the predetermined positive potential. Thus the output of gate 46 shifts to ground potential, and flip-flop 47 responds to pulse 27 to provide an output signal in the form of a negative transition as indicated at 72 in FIG. 3F at output conductor 48.
The positive transition at output conductor 48 causes the D-type flip-flop 53 to assume a logical 1-condition. The transition at output conductor 74 of flip-flop 53 (the Q complement output) is represented at 75 in FIG. 3H. (The transition at the Q output of flip-flop 53 is indicated at 76 in FIG. 3G.)
Conductor 74 is connected to a control terminal of binary counter 36 such that when the potential of conductor 74 is at the ground potential level, the counter is released and begins counting encoder pulses supplied at input line 35. By way of example, conductor 80 may be connected to the output of the 11th binary stage of counter 36 so as to provide a predetermined positive potential when this stage is in a logical 1-condition while output conductor 81 may be connected with the output of the 15th binary stage of the counter so as to provide a predetermined positive potential when this stage is in a logical 1-condition. FIG. 3I represents the potential at output conductor 80, while FIG. 3J represents the output potential at conductor 81. Thus, for example, transition 82 occurs 1024 encoder pulses after the transition 75, while transition 83 occurs at a count of 16384 encoder pulses after the transition 75. At the instant that conductor 81 is exhibiting the transition 83, conductor 80 will be exhibiting a potential transition as indicated at 84 in FIG. 3I. After a further 1024 encoder pulses, output conductor 80 will shift to a predetermined positive potential as indicated at 85 in FIG. 3I. The positive potentials at conductors 80 and 81 provide a ground potential output from gate 52, causing the clearing of flip-flop 53. The return of conductor 74 to a high or positive potential as indicated at 86 serves to set the binary counter 36 to its initial count of zero and hold the counter in this state. The output of gate 52 is indicated at 87 in FIG. 3K. FIG. 3L indicates the output of gate 51 which serves to reset the shift register 40 and flip-flop 47 during the interval indicated at 88 in FIG. 3L.
The circuit of FIG. 2 further includes control pulse transmission means for coupling the output of the scanner pulse circuit to a web control and/or error display system such as represented by component 90. By way of example, the component 90 may correspond to the system disclosed in a copending application Ser. No. 722,095 filed Apr. 17, 1968, and assigned to the same assignee as the present application. For the sake of this particular example, a "one shot" circuit is indicated at 91 having its input connected to conductor 48 for transmitting a first control pulse to the system 90 which may correspond to the position detector signal (which is supplied to a conductor number 44 in the fourth figure of the copending application). Similarly a "one shot" circuit 92 is shown as having its input connected to the conductor 49 so as to supply a second control pulse to the system 90 (which may correspond to the scanner pulse supplied to conductor number 56 shown in the fourth figure of said copending application). In this event, the system 90 may control a compensator motor acting at the region 20 in FIG. 1 (and corresponding to the compensator device indicated for station D in the first figure of the copending application).
It will be apparent to those skilled in the art from a consideration of the drawings that the position of the selector switch 41 may determine the position number of either the first or second scanner pulse which is responded to by the circuit of FIG. 2, while the position number of the second selector switch 42 may determine the position number of the other scanner pulse of the series which is responded to by the circuit of FIG. 2.
If stations A-D print with yellow, red, blue and black ink, respectively, it will be understood that selector switch 41 may be set by the operator to the position of the blue mark in the series of marks on a web, while the selector switch 42 may be set to the position of the black mark of the web, irrespective of which appears first, thus greatly simplifying the setup procedure from the standpoint of the operator.
It will also be apparent to those skilled in the art from a consideration of the drawings that if when the system is initially started up, the first pulse appearing at input 30 is a different pulse than the first pulse of the series, the operation of the circuit is such that after a few cycles of operation, normal operation will automatically be achieved. Similarly if a spurious scanner pulse should be produced during normal operation, for example as a result of ink inadvertently dropping on the web or a defect in the web, the result would be only a momentary loss of synchronism, and the circuit would automatically restore proper operation after a few cycles. In order for the illustrated system to be capable of automatic start up and automatic resynchronization, there should be a clear track for approximately one half the repeat length in advance of the desired series of marks corresponding to pulses 25-28. If the required clear track in not available, resort can be had to electronic or mechanical gating techniques to maintain synchronization. It will be observed however that spurious pulses following pulse 28 and prior to the resetting of the shift register 40 as represented at 88 in FIG. 3L will have no adverse effect on the system since shift register 40 will not respond to pulses during this interval.
For the sake of a specific example, the J K flip-flop 55.57 may be type S N 7473 available from Texas Instruments Incorporated, and the type D flip-flops 47 and 53 may be type S N 7474 of the same company. It is believed evident that one skilled in the art can readily provide a binary counter meeting the requirements for the counter 36.
SUMMARY OF OPERATION
In setting up the system, the operator may adjust the selector switch 41 to a position corresponding to the position of the mark printed by station C, FIG. 1 (for example the blue mark), while the selector switch 42 may be set to a position corresponding to the position of the mark printed by the station D on the web (for example the black mark). Thus, if the sequence of marks on the web were black, red, yellow, and blue, for example, selector switch 41 would be set to position number four, while selector switch 42 would be set to position number one. Thus setup is an extremely simple matter from the standpoint of the operator.
Once stable operation of the system has been achieved, which automatically occurs regardless of the startup point, after a few cycles, the sequence of operation of the circuitry is as represented in FIG. 3 for the positions of the selector switches 41 and 42 as shown in FIG. 2. In each cycle of operation, a positive going transition 71 occurs at output line 48 at the position of the pulse selected by switch 41, and a positive going transition occurs at output line 49 (corresponding in time to transition 72 in FIG. 3F) in response to the second selected pulse as determined by the position of selector switch 42. As indicated by components 91 and 92, these transitions or output signals may be utilized to generate first and second control pulses at the input to the system 90 whose spacing is a measure of the register condition at the station D, FIG. 1. The system 90 may apply corrections at region 20, FIG. 1, should the spacing between the control pulses signify an error in the register condition at the station. By properly setting up the system, it is a very simple matter for the operator to insure that the control corrections applied at region 20 will be in the direction to reduce any registration error, should the present invention be utilized to control the register condition.
It should be emphasized that while the illustrated system is preferred and uniquely advantageous in certain applications such as rotogravure offset printing of newspapers and the like, certain simplifications of the illustrated circuit will be possible particularly for applications where the position of the mark printed by one of the stations can be conveniently predetermined, for example. It will further be evident that the invention is applicable to web apparatus having different numbers of stations than the apparatus specifically illustrated, and the application of the concepts of the invention to different numbers of marks in a common channel will be apparent to those skilled in the art from the foregoing disclosure.
It will be apparent that many other modifications and variations may be affected without departing from the scope of the novel concepts of the present invention.