CHARACTER GENERATOR
United States Patent 3618026
A character generator comprising a read-only-memory which accepts an input data word of six bits and from its output generates code for a set of three ASCII letters for printout on a typewriter. The three ASCII letters code in turn are converted to the same three letters of NIXIE code, these ASCII output words being rerouted into the read-only-memory and the second output being in NIXIE code for providing visual readout on segmented indicators.
US Patent References:
Race track betting data handling system
Eriksson et al. - June 1967 - 3327292
Photocomposing machines
Grube et al. - November 1967 - 3352219
Remote calculator
Clayton et al. - April 1968 - 3380031
CASH FLOW COMPUTER
Howard et al. - June 1970 - 3516068
CONTROL UNIT FOR MULTIPLE GRAPHIC AND ALPHANUMERIC DISPLAYS
Houldin et al. - November 1970 - 3539999
Race track betting data handling system
Eriksson et al. - June 1967 - 3327292
Photocomposing machines
Grube et al. - November 1967 - 3352219
Remote calculator
Clayton et al. - April 1968 - 3380031
CASH FLOW COMPUTER
Howard et al. - June 1970 - 3516068
CONTROL UNIT FOR MULTIPLE GRAPHIC AND ALPHANUMERIC DISPLAYS
Houldin et al. - November 1970 - 3539999
Application Number:
05/019980
Publication Date:
11/02/1971
Filing Date:
03/16/1970
View Patent Images:
Export Citation:
Assignee:
Honeywell Inc. (Minneapolis, MN)
Primary Class:
Other Classes:
345/536, 345/33
International Classes:
G06F3/147; G09G3/10; H04Q9/14; G09G3/04; G06F5/02; H01J17/48
Field of Search:
340/324,172.5
Primary Examiner:
Shaw, Gareth D.
Assistant Examiner:
Woods, Paul R.
Claims:
The embodiments of the invention in which an exclusive property or right is claimed are defined as follows
1. A character generator comprising:
2. The invention according to claim 1 in which said first means includes means for storing said first output data words during the interval the data is being used by said first display means and routed back into the input of said read-only-memory means.
3. The invention according to claim 1 in which said second means includes gating means for selectively connecting the input of said read-only-memory means to receive said source of data words and for selectively connecting said input to receive said output data words.
4. The invention in accordance with claim 2 in which said read-only-memory means includes a plurality of enable gates and the enabling of each such gate generating one of said first output data words and in which said means for storing said first data output words includes a storage for each of said words.
5. The invention in accordance with claim 4 in which said second means includes sequentially operated gates for routing said plurality of output words into said read-only-memory in sequence and in which said third means includes storage means for receiving each of said further output data words.
6. A character generator which accepts binary coded input data words at a read-only-memory and outputs binary coded words for actuating a teleprinter, the output binary coded words then being selectively routed again through the character generator to provide a second set of binary coded output words from the read-only-memory for controlling alphanumeric segmented indicators, the character generator comprising:
1. A character generator comprising:
2. The invention according to claim 1 in which said first means includes means for storing said first output data words during the interval the data is being used by said first display means and routed back into the input of said read-only-memory means.
3. The invention according to claim 1 in which said second means includes gating means for selectively connecting the input of said read-only-memory means to receive said source of data words and for selectively connecting said input to receive said output data words.
4. The invention in accordance with claim 2 in which said read-only-memory means includes a plurality of enable gates and the enabling of each such gate generating one of said first output data words and in which said means for storing said first data output words includes a storage for each of said words.
5. The invention in accordance with claim 4 in which said second means includes sequentially operated gates for routing said plurality of output words into said read-only-memory in sequence and in which said third means includes storage means for receiving each of said further output data words.
6. A character generator which accepts binary coded input data words at a read-only-memory and outputs binary coded words for actuating a teleprinter, the output binary coded words then being selectively routed again through the character generator to provide a second set of binary coded output words from the read-only-memory for controlling alphanumeric segmented indicators, the character generator comprising:
Description:
BACKGROUND OF THE INVENTION
This invention relates to the field of character generation in which multibit inputs are provided to an ROM-type memory for producing multibit character output for either a printer or segment indicator. An example of the use of the ROM in code conversion of this general type in the prior art is disclosed in an article entitled "ROM at the Top" by John Linford in the Electronic Engineer of May, 1969, pages 64-71.
SUMMARY OF THE INVENTION
A character generator comprising a read-only-memory which accepts binary coded input data and outputs binary coded words for actuating a teleprinter, these output words then being rerouted into the read-only-memory to provide a second set of output words for controlling alphanumeric segmented indicators. The technique used in the present invention is less costly than other possible methods of multicode conversions, which would require two read-only-memories (one for each type of conversion) or a much larger and more costly read-only-memory outputting all codes simultaneously.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the system of the character generator;
FIG. 2 shows how the Figures 3a through 3f are assembled to form a complete figure;
FIGS. 3a through 3f are a schematic representation of the block diagram shown in Figure 1;
FIGS. 4 and 5 are graphical representations of various operating pulses of the character generator plotted against time;
FIG. 6 is the significant portion of an ASCII code;
FIG. 7 is a chart of the code for a NIXIE display;
FIG. 8 is a partial chart of the 64 word, 6-bit input words which generate various three-letter printed words;
FIGS. 9 through 14 disclose the coded bits at various portions of the circuit, for a sample word;
FIG. 15 shows a functional schematic of the latches of Figure 3c; and
FIG. 16 shows a segmented display readout.
DESCRIPTION
Referring now to the block diagram of Figure 1, there is disclosed an input data word 10 which is transmitted through input gating 11 to a read-only-memory (ROM) 12. The output from the ROM is connected to output storage devices 13, 14 and 15. The output storage devices have output means 16, 17 and 18 for coupling the ASCII code characters to a typewriter or CRT, and an output means 19 to carry process information. At times typed information is sufficient and at other times a NIXIE readout is desired. For those occasions the output storages 13, 14 and 15 have further output means 20, 21, 22, 23 and 24 to the input of gating means 25, 26 and 27. The ASCII code stored in the output storages 13, 14 and 15 is selectively and sequentially fed back through the input gating 11 into the ROM 12 to generate a 13-bit code for each of the 13 segment alphanumeric indicators, here specifically, NIXIE tubes, thus gate 25 first admits five bits from the output storage 13 into the ROM 12. The gating means 26 then admits to the last two bits of storage 13 and three bits of storage 14 through the input gating 11 and into the ROM. The third gating means 27 then admits four bits from the storage 14 and one bit from the storage 15 to be applied through the input gating to the ROM.
The output from the ROM 12 in addition to being connected to the output storage means, above described, is also connected to NIXIE storage means 32, 33 and 34 which control, respectively, the NIXIE display tubes 35, 36 and 37.
The diagram of Figure 1 also includes a time and control means 40 which provides a combination of output pulses at Predetermined times to the various portions of the character generator. In general terms of operation, the timing and control means 40 first steers the input gating 11 to accept the input data word 10 into the ROM and the sequentially occurring pulses T1, T3, and T6 strobe the ROM 23 to provide the 3 coded 7-bit outputs which are entered into the output storage 13, 14 and 15, respectively. The timing and control means 40 then provides a steering to the input gating 11 to accept information from the output storage and the sequential pulses NIXIEN 1, NIXIEN 2, and NIXIEN 3, enable the gating 25, 26 and 27 to connect the intelligence stored in the output storage devices 13, 14 and 15 into the ROM 12. As each of these gates 25, 26 and 27 connects five bits into the ROM, the ROM is strobed by pulses CGDIN and CGEIN to enter seven bits and then six bits for a total of 13 bits into each NIXIE storage 32, 33 and 34.
Referring now to the schematic diagram disclosed in Figures 3a, 3b, 3c, 3d, 3e and 3f, there is disclosed in Figure 3a a source 10 of input data words of six bits which is coupled by conductors 50, 51, 52, 53, 54 and 55 to input gate means 56 of input gating 11. Gate means 56 comprises 6 NAND gates 56a, 56b, 56c, 56d, 56e and 56f, each having an input connected to the conductors 50 to 55, respectively. The second input to each of the NAND gates is an enable input and these are connected in parallel and to a conductor EN2. The input gating 11 also includes another six input gate means 57 which is of the same nature as gate means 56, and a further gate means 60. The six outputs of gate means 56 are directly connected to corresponding inputs of the six NAND gates in the gate means 60. The six outputs of gate means 57 are connected, respectively, to the other inputs of the six NAND gates in the gate 60. The six outputs of the input gating 11 are connected by conductors 61 through 66 to the inputs 1 through 6 of the ROM 12, FIG. 3b.
The ROM 12 may be of any suitable type but in one successful embodiment is of the MOS integrated circuit type identified as the TMS-4840 series by Texas Instruments, Inc. and in a specific case as the model TMS-1A-4847. The ROM is a P-channel, enhancement mode MOS monolithic integrated circuit which utilizes thick oxide technology, consisting of a 2,240 bit memory matrix, complete address decoding circuitry, and current-sinking output buffers. The memory is a DC operating device requiring two power supplies and ground as indicated. The memory is addressed by supplying a 6-bit parallel word to the ROM input terminals 1 through 6. The output word is available on seven parallel output lines 70 through 76 and a 5-bit sequence is generated on each output line by enabling the five column select lines a, b, c, d or e in time sequence.
Output storage 13 in Figure 3c is comprised of seven latches or flip-flops A1, A2, A3, A4, A5, B1 and B2. The latch is a clocked flip-flop having a data input and a clock input, a functional diagram of which is shown in Figure 15. The clock input of the seven latches are directly connected in parallel and to the conductor T1 which originates at the timer to be discussed in more detail below. When a clock pulse exists on T1, the seven latches are enabled simultaneously to accept the ROM output data on the seven conductors 70-76.
The output storage 14 includes seven more latches B3, B4, B5, C1, C2, C3 and C4. These latches are the same as latches described above in connection with storage 13, each having a data input and a clock input. The seven outputs of the ROM are connected respectively to the data inputs of the seven latches and the clock inputs are connected together in parallel and to a conductor T3 from the timer. A pulse on the conductor T3 is effective to enable the output storage 14 enabling the latches to accept the 7-bit output from the ROM.
In the output storage is, only the latch C5 of the seven latches is shown, the others not being pertinent to this invention. This latch C5 receives its data input from conductor 70 and its clock input is connected to the conductor T5 from the timer.
Each of the 15 latches A1 through A5, B1 through B5 and C1 through C5 has a Q output and Q output as shown in latch A1. The 15 latches are divided into three groups of five to provide three groups of 5-bit code from the 15 Q outputs to the typewriter ASCII interface. Thus the "A" latches provide the five bits necessary for the first letter, the "B" latches provide the five bits necessary for the second letter and the "C" latches provide the five bits necessary for the third letter to be typed by the typewriter.
When the input data word 10 is decoded by the ROM and stored into the output storage 13, 14 and 15, this intelligence must be fed through the ROM again to generate the three 13 -bit codes necessary for the NIXIE segmented display tubes. The Q outputs of the latches A1, A2, A3, A4 and A5 are connected to the five gates a, b, c, d and e of gate means 25. The enable inputs of these gates in gating means 25 are connected in parallel and to a conductor NIXIEN 1 from the timer. The five outputs of the gate means 25 are connected by conductors 80 through 84 (also indicated by conductor bundle 30) to the input gate means 57, gates a through e. The sixth gate f of gate means 57 has a constant input, here shown as ground.
The Q outputs of latches B1 through B5 are connected to the five inputs of the gating means 26. The outputs of the gates 26a through e are connected respectively to the conductors 80 through 84. The enabling inputs of these five gates are all connected together and to a conductor NIXIEN 2 from the timer. The Q outputs of the latches C1 through C5 are connected to the five inputs of the gate 27. The five outputs of the gating means 27 a through e are also connected to the conductors 80 through 84 respectively. The enabling inputs of the gates 27 a through e are all connected together and to a conductor NIXIEN 3 from the timer.
The seven outputs from the ROM 70 through 76 are also connected into the three NIXIE storage means 32, 33 and 34. When the 13 bits are properly stored in each of the NIXIE storage means, the characters can be displayed on the three NIXIE display segment indicators. The NIXIE storage 32 has been shown in more detail than the similar storages 33 and 34, and comprises 13 latches D1-D7 and E1-E6. These latches may be similar to the other latches described above. The latches each have a data input D and a clock input C, the clock inputs of latches D1 to D7 being connected together and to the conductor ST1. Likewise the clock inputs E1 to E6 are connected together and to a clock input ST2. A pulse to gates D1 to D7 on ST1 enables these gates to receive data from the ROM. Subsequently, a pulse ST2 enables gates E1 to E6 to receive data from the ROM.
Referring now to Figure 3d, the timer 40 is disclosed in more detail and a pair of signal inputs labeled start and display pulse are connected to the set and reset inputs of a flip-flop 100. A first output of the flip-flop 100 is connected to a conductor EN2 and the opposite output is connected to to conductor EN1, the EN2 conductor previously having been described as being connected to the enable inputs of input gating means 56 and the conductor EN1 having been previously described as being connected to the enable inputs of gating means 57. The start and display inputs are also connected to the inputs of an AND-gate 101, and the output of the AND-Gate is connected to the set input of a flip-flop 102. The output of the flip-flop 102 is connected to one input of an AND-gate 103, the other input of which is pulsed by a 250-kHz. clock. The output of AND-gate 103 is connected to the input of a decade counter of the binary coded decimal type such as the Motorola MC 838. The four conventional outputs of the binary coded decimal counter are connected to the input of a BCD to decimal decoder or stepper 105. total of 13 bits into 0 through 9 of which outputs 1 through 8 are inverted with respect to outputs 0 to 9. Stepper output 1 is directly connected to one input of an AND-gate 106 and also to one input of a NAND-gate 107. Output 2 of the stepper is directly connected to an input of a NAND-gate 108. Stepper output 3 is directly connected to an input of an AND-gate 109. Stepper output 4 is directly connected to an input of NAND-gate 110. Stepper output 5 is directly connected to an input of AND-gate 111 and to an input of a NAND-gate 112. Stepper output 7 is directly connected to an input of an AND-gate 113 and to an input of a NAND-gate 114. Stepper output 8 is directly connected to one input of an AND-gate 115 and also to one input of a NAND-gate 116. Stepper output 9 is connected by a conductor 120 to the reset input of flip-flop 102. Gates 107, 108, 110, 112, 114 and 116 have their second inputs all connected together to the conductor EN1 from the output of flip-flop 100. Similarly, gates 106, 109, 111, 113 and 115 have their second inputs connected together to the conductor EN2 from the other output of flip-flop 100. Thus, half of these gates are enabled by a signal on line EN2 and the other half are enabled by a signal on line EN1.
The output of gate 106 is a conductor T1 which is connected to the a input of the ROM 12 and is also connected to the clock pulse inputs of the latches in output storage 13, as has been described above. The output of AND-gate 109 is a conductor T3 which is connected to the b input of the ROM 12 and is also connected to the clock inputs of the latches in the output storage 14. The output of AND-gate 111 is a conductor T5 which is connected to the c input of the ROM is also connected to the clock input of latch C5.
The output of the NAND-gate 107 is a conductor XX1 which is connected to the input of an inverter 120 and to one input of the NAND-gate 121. The output of NAND-gate 108 is a conductor XX2 which is connected to the other input of NAND-gate 121 and to the input of an inverter 122. The NAND-gate 110 has its output directly connected by a conductor XX4 to the input of an inverter 123 and to one input of a NAND-gate 124. The NAND-gate 112 has its output connected by a conductor XX5 to the other input of NAND-gate 134 and is also connected to the input of an inverter 125. The output of NAND-gate 114 is connected by a conductor XX7 to the input of an inverter 126 and also to one input of a NAND-gate 128. The NAND-gate 116 has its output connected by a conductor XX8 to the input of an inverter 127 and also to the other input of NAND-gate 128.
A gating network 130 functionally comprises a plurality of AND gates a, b, c, d, e and f which the outputs of a, c and being connected to a conductor CGDIN and with the gates b, d and f being connected to an output conductor CGEIN, these two conductors terminating at the d and e inputs of the ROM. The AND function should be implemented by NAND gates followed by inverters. The output of inverter 120 is a conductor ST1 which is connected to one input of the gate a. The output of inverter 122 is a conductor ST2 connected to one input of the gate b. The output of NAND-gate 121 is a conductor NIXIEN 1 which is connected to the other input of gates a and b. The output of inverter 123 is a conductor ST3 which is connected to one input of the gate c and the output of the inverter 125 is a conductor ST4 which is connected to one input of the gate d. The output of NAND gate 124 is a conductor NIXIEN 2 which is connected to the second inputs of gates c and d. The output of inverter 126 is a conductor ST5 which is connected to one input of the gate e and the output of inverter 127 is a conductor ST6 which is connected to one input of the gate f. The output of NAND-gate 128 is a conductor NIXIEN 3 which is connected to the second inputs of gates e and f. The ST1 and ST2 conductors are also connected to the NIXIE storage 32; the conductors ST3 and ST4 are connected into the NIXIE storage 33; and the ST5 and ST6 conductors are connected into the NIXIE storage 34 to enable the storage at the proper time to accent data from the ROM. The NIXIEN 1 conductor is also connected to the gate means 25 as has been previously discussed; the NIXIEN 2 conductor is also connected to the gate means 25 as has been previously discussed; and the NIXIEN 3 conductor is also connected to the gate means 27.
OPERATION
The start pulse operates flip-flop 100 to cause output line EN2 to be high or "one" and line EN1 to be low or "zero," as shown in FIG. 4. EN2 is effective to enable the gates 56 so that the input data word can be applied to the ROM. The start pulse is also applied through the gate 101 to set flip-flop 102 which enables AND-gate 103 and follows decade counter 104 and stopper 105 to commence counting at a 250-kHz. rate.
With the stepper at position 1, a timing pulse T1 is generated which enables the ROM at input a and also enables the seven latches A1 through B2. The 6-bit input word into the ROM when enabled at a provides a first 7-bit output which sets the seven enabled latches.
At stepper position 2 nothing occurs. At stepper position 3 the pulse T3 is generated which enables the ROM at input b and also enables the seven latches B3 through C4. The 6-bit input word in the ROM when enabled at b provides a second 7-bit output which sets the seven enabled latches.
At stepper position 4 nothing occurs. At stepper position 5 the pulse T5 is generated which enables the ROM at input c and also enables the next seven latches, of which only C5 is shown. The 6-bit input word in the ROM which enabled at c provides a third 7-bit output which sets the third set of latches including C5. The information needed for typewriter instruction is now set into the 15 latches. At position 9 of the stepper the flip-flop resets and the counting stops.
The code set into the latches in addition to providing three 5-bit codes to the typewriter interface for the three-letter-type output is now run into the ROM six times to provide therefrom six sets of 7-bit code to be loaded into the NIXIE storage for the three letter NIXIE display. To do this the display pulse, Figure 5, initiates the count again and operates the flip-flop 100 so that EN1 is high and EN2 is low. The gates 56 are disabled disconnecting the input data word from the ROM and enabling gate means 57 so that the latch stored signals can be entered into the ROM. At stepper position 1, pulses XX1, ST1, NIXIEN 1, and CGDIN are generated. At stepper position 2 pulses XX2, NIXIEN 1, ST2, and CGEIN are generated. At stepper position 4, pulses XX4, ST3, NIXIEN 2, and CGDIN are generated. At stepper position 5 pulses XX5, ST4, NIXIEN 2, and CGEIN are generated. At stepper position 7, pulses XX7, ST5, NIXIEN 3, and CGDIN are are generated. At stepper position 8 pulses XX8, ST6, NIXIEN 3, and CGEIN are generated. The Pulses NIXIEN 1, NIXIEN 2 and NIXIEN 3 enable the gates 25, 26, and 27 in sequence so that three 5-bit words stored in the latches A1 to C5 are entered into the ROM.
Let us assume an example in which it is desired to generate the characters GPM (gallons per minute) to be printed out on the typewriter and displayed on the NIXIE display. Figure 8 shows selected portions of a 64 -word chart in which the 6-bit binary word is indicated on the left and the printed word to be displayed on typewriter at the right. The input word No. 55 is to print GPM. A 6-bit input work 110111 (which is 55 in decimal), Figure 9, is fed into the ROM when the gates 56 are enabled by EN2 and the ROM inputs a, b and c are sequentially strobed by pulses T1, T3 and T5. The T1 pulse also enables seven latches A1, A2, A3, A4, A5, B1 and B2 and these latches are loaded with the T1 output of the ROM. Subsequently, the T3 pulse again enables the ROM and seven more latches and this output is loaded into the seven latches B3, B4, B5, C1, C2, C3 and C4. Then the T5 pulse again enables the ROM and another seven latches, of which only C5 is shown, are loaded with the T5 output of the ROM. The ASCII code (American Standard Code) for upper case letters of the alphabet is shown in Figure 6. The 15 latches provide three sets of five bits output on the Q output terminals which are fed into the typewriter interface and typewriter to print the letters GPM. Thus the output of latches A1, A2, A3, A4 and A5 may be 00111, the ASCII (American Standard Code) for the letter G, the output of latches B1, B2, B3, B4 and B5 may be 10000 for the letter P and the output of latches C1, C2, C3, C4 and C5 may be 01101 for the letter M as is shown in Figure 10.
The three 5-bit codes loaded into the latches are now used as input to the ROM to generate the NIXIE characters GPM.
In this example it is desired to display as well as type the letters GPM so a display pulse is originated by equipment, not shown. The display pulse triggers the flip-flop 100 to cause EN1 to be high and EN2 low, Figure 5. The gates 56 from the input data word are now disabled and the display gates 57 are enabled. The EN1 signal also enables gates 107 and 108 to provide an XX1 pulse followed by an XX2 pulse as the stepper moves through steps 1 and 2. The sequential signals XX1 and XX2 cause gate 121 to provide a NIXIEN 1 pulse, Figure 5. The NIXIEN 1 pulse enables gates 25 a to e and the Q outputs or "not" of latches A1, A2, A3, A4 and A5 carrying code for the letter G, Figure 11, pass the gates 25a to e, conductors 80-84, display gates 57 and input gating 60 to the ROM. The XX1 pulse is also inverted by inverter 120 and generates strobe pulse ST1. Pulse ST1 and NIXIEN 1 operate AND-gate 130a to generate pulse CGDIN which is applied to ROM input d. The resulting 7-bit output of the ROM is entered into the NIXIE storage 32 latches D1 to D7 as enabled by ST1. The XX2 pulse generates ST2 through inverter 122. ST2 enables the NIXIE storage means 32 latches E1 to E6 and also together with NIXIEN 1 operates gate 130b to generate CGEIN and pulse CGEIN is applied at ROM input e. Six bits of the resulting 7-bit output of the ROM is entered into the NIXIE storage 32 latches E1-E6 thereby providing 13 bits into storage 32. FIG. 7 is a partial chart of the NIXIE code for the 13 segment NIXIE indicator. The chart includes the letters of the cited example, GPM. The NIXIE indicators are shown in more detail in Figure 16. The progression of the five bits from storage 13, through gates 25 and 11, into the ROM, the ROM output and the NIXIE storage input may be followed in Figures 11, 12, 13 and 14.
The stepper now moves to position 3 but since EN2 is low nothing happens. At stepper position 4, XX4 is generated which in turn generates both ST3 and NIXIEN 2. NIXIEN 2 is applied to gates 130c and 130d and also to the five gates 26a to e. The enabling of these five gates allows the Q or "not" outputs of latches B1, B2, B3, B4 and B5 to be coupled by conductors 80-84, gate means 57 and gate means 60 into the ROM. Pulses ST3 and NIXIEN 2 generate pulse CGDIN at 130c which is applied at ROM input d. The first seven bits for the second NIXIE character are loaded into the NIXIE storage 33. The stepper moves into position 5 generating XX5 which generates ST4 and NIXIEN 2. ST4 generates CGEIN at 130d to enable the ROM at input e thus loading a second six bits for the second NIXIE character into the NIXIE storage 33.
At position 7 of the stepper XX7 is generated which generates ST5 and NIXIEN 3. Pulse ST5 is applied to the NIXIE storage 34 and also to gate 130e. NIXIEN 3 is applied to gate 130e to generate CGDIN and enable the ROM at d. NIXIEN 3 is also applied to enable gate means 27 allowing the Q or not outputs of latches C1, C2, C3, C4 and C5 to be loaded into the ROM as described above. The 7-bit output from the ROM is loaded into the NIXIE storage 34 as the first seven bits of the third character.
At position 8 of the stepper XX8 is generated which generates ST6 and NIXIEN 3. Pulse ST6 enables the NIXIE storage 34 and together with NIXIEN 3 generates CGEIN to enable the ROM at input e. The output of the ROM goes into the NIXIE storage 34 as the sixth set and final set of code needed to generate the letters GPM in the NIXIE display. The NIXIE input information for the example GPM is shown in Figure 14, and the resulting display in Figure 16.
This invention relates to the field of character generation in which multibit inputs are provided to an ROM-type memory for producing multibit character output for either a printer or segment indicator. An example of the use of the ROM in code conversion of this general type in the prior art is disclosed in an article entitled "ROM at the Top" by John Linford in the Electronic Engineer of May, 1969, pages 64-71.
SUMMARY OF THE INVENTION
A character generator comprising a read-only-memory which accepts binary coded input data and outputs binary coded words for actuating a teleprinter, these output words then being rerouted into the read-only-memory to provide a second set of output words for controlling alphanumeric segmented indicators. The technique used in the present invention is less costly than other possible methods of multicode conversions, which would require two read-only-memories (one for each type of conversion) or a much larger and more costly read-only-memory outputting all codes simultaneously.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the system of the character generator;
FIG. 2 shows how the Figures 3a through 3f are assembled to form a complete figure;
FIGS. 3a through 3f are a schematic representation of the block diagram shown in Figure 1;
FIGS. 4 and 5 are graphical representations of various operating pulses of the character generator plotted against time;
FIG. 6 is the significant portion of an ASCII code;
FIG. 7 is a chart of the code for a NIXIE display;
FIG. 8 is a partial chart of the 64 word, 6-bit input words which generate various three-letter printed words;
FIGS. 9 through 14 disclose the coded bits at various portions of the circuit, for a sample word;
FIG. 15 shows a functional schematic of the latches of Figure 3c; and
FIG. 16 shows a segmented display readout.
DESCRIPTION
Referring now to the block diagram of Figure 1, there is disclosed an input data word 10 which is transmitted through input gating 11 to a read-only-memory (ROM) 12. The output from the ROM is connected to output storage devices 13, 14 and 15. The output storage devices have output means 16, 17 and 18 for coupling the ASCII code characters to a typewriter or CRT, and an output means 19 to carry process information. At times typed information is sufficient and at other times a NIXIE readout is desired. For those occasions the output storages 13, 14 and 15 have further output means 20, 21, 22, 23 and 24 to the input of gating means 25, 26 and 27. The ASCII code stored in the output storages 13, 14 and 15 is selectively and sequentially fed back through the input gating 11 into the ROM 12 to generate a 13-bit code for each of the 13 segment alphanumeric indicators, here specifically, NIXIE tubes, thus gate 25 first admits five bits from the output storage 13 into the ROM 12. The gating means 26 then admits to the last two bits of storage 13 and three bits of storage 14 through the input gating 11 and into the ROM. The third gating means 27 then admits four bits from the storage 14 and one bit from the storage 15 to be applied through the input gating to the ROM.
The output from the ROM 12 in addition to being connected to the output storage means, above described, is also connected to NIXIE storage means 32, 33 and 34 which control, respectively, the NIXIE display tubes 35, 36 and 37.
The diagram of Figure 1 also includes a time and control means 40 which provides a combination of output pulses at Predetermined times to the various portions of the character generator. In general terms of operation, the timing and control means 40 first steers the input gating 11 to accept the input data word 10 into the ROM and the sequentially occurring pulses T1, T3, and T6 strobe the ROM 23 to provide the 3 coded 7-bit outputs which are entered into the output storage 13, 14 and 15, respectively. The timing and control means 40 then provides a steering to the input gating 11 to accept information from the output storage and the sequential pulses NIXIEN 1, NIXIEN 2, and NIXIEN 3, enable the gating 25, 26 and 27 to connect the intelligence stored in the output storage devices 13, 14 and 15 into the ROM 12. As each of these gates 25, 26 and 27 connects five bits into the ROM, the ROM is strobed by pulses CGDIN and CGEIN to enter seven bits and then six bits for a total of 13 bits into each NIXIE storage 32, 33 and 34.
Referring now to the schematic diagram disclosed in Figures 3a, 3b, 3c, 3d, 3e and 3f, there is disclosed in Figure 3a a source 10 of input data words of six bits which is coupled by conductors 50, 51, 52, 53, 54 and 55 to input gate means 56 of input gating 11. Gate means 56 comprises 6 NAND gates 56a, 56b, 56c, 56d, 56e and 56f, each having an input connected to the conductors 50 to 55, respectively. The second input to each of the NAND gates is an enable input and these are connected in parallel and to a conductor EN2. The input gating 11 also includes another six input gate means 57 which is of the same nature as gate means 56, and a further gate means 60. The six outputs of gate means 56 are directly connected to corresponding inputs of the six NAND gates in the gate means 60. The six outputs of gate means 57 are connected, respectively, to the other inputs of the six NAND gates in the gate 60. The six outputs of the input gating 11 are connected by conductors 61 through 66 to the inputs 1 through 6 of the ROM 12, FIG. 3b.
The ROM 12 may be of any suitable type but in one successful embodiment is of the MOS integrated circuit type identified as the TMS-4840 series by Texas Instruments, Inc. and in a specific case as the model TMS-1A-4847. The ROM is a P-channel, enhancement mode MOS monolithic integrated circuit which utilizes thick oxide technology, consisting of a 2,240 bit memory matrix, complete address decoding circuitry, and current-sinking output buffers. The memory is a DC operating device requiring two power supplies and ground as indicated. The memory is addressed by supplying a 6-bit parallel word to the ROM input terminals 1 through 6. The output word is available on seven parallel output lines 70 through 76 and a 5-bit sequence is generated on each output line by enabling the five column select lines a, b, c, d or e in time sequence.
Output storage 13 in Figure 3c is comprised of seven latches or flip-flops A1, A2, A3, A4, A5, B1 and B2. The latch is a clocked flip-flop having a data input and a clock input, a functional diagram of which is shown in Figure 15. The clock input of the seven latches are directly connected in parallel and to the conductor T1 which originates at the timer to be discussed in more detail below. When a clock pulse exists on T1, the seven latches are enabled simultaneously to accept the ROM output data on the seven conductors 70-76.
The output storage 14 includes seven more latches B3, B4, B5, C1, C2, C3 and C4. These latches are the same as latches described above in connection with storage 13, each having a data input and a clock input. The seven outputs of the ROM are connected respectively to the data inputs of the seven latches and the clock inputs are connected together in parallel and to a conductor T3 from the timer. A pulse on the conductor T3 is effective to enable the output storage 14 enabling the latches to accept the 7-bit output from the ROM.
In the output storage is, only the latch C5 of the seven latches is shown, the others not being pertinent to this invention. This latch C5 receives its data input from conductor 70 and its clock input is connected to the conductor T5 from the timer.
Each of the 15 latches A1 through A5, B1 through B5 and C1 through C5 has a Q output and Q output as shown in latch A1. The 15 latches are divided into three groups of five to provide three groups of 5-bit code from the 15 Q outputs to the typewriter ASCII interface. Thus the "A" latches provide the five bits necessary for the first letter, the "B" latches provide the five bits necessary for the second letter and the "C" latches provide the five bits necessary for the third letter to be typed by the typewriter.
When the input data word 10 is decoded by the ROM and stored into the output storage 13, 14 and 15, this intelligence must be fed through the ROM again to generate the three 13 -bit codes necessary for the NIXIE segmented display tubes. The Q outputs of the latches A1, A2, A3, A4 and A5 are connected to the five gates a, b, c, d and e of gate means 25. The enable inputs of these gates in gating means 25 are connected in parallel and to a conductor NIXIEN 1 from the timer. The five outputs of the gate means 25 are connected by conductors 80 through 84 (also indicated by conductor bundle 30) to the input gate means 57, gates a through e. The sixth gate f of gate means 57 has a constant input, here shown as ground.
The Q outputs of latches B1 through B5 are connected to the five inputs of the gating means 26. The outputs of the gates 26a through e are connected respectively to the conductors 80 through 84. The enabling inputs of these five gates are all connected together and to a conductor NIXIEN 2 from the timer. The Q outputs of the latches C1 through C5 are connected to the five inputs of the gate 27. The five outputs of the gating means 27 a through e are also connected to the conductors 80 through 84 respectively. The enabling inputs of the gates 27 a through e are all connected together and to a conductor NIXIEN 3 from the timer.
The seven outputs from the ROM 70 through 76 are also connected into the three NIXIE storage means 32, 33 and 34. When the 13 bits are properly stored in each of the NIXIE storage means, the characters can be displayed on the three NIXIE display segment indicators. The NIXIE storage 32 has been shown in more detail than the similar storages 33 and 34, and comprises 13 latches D1-D7 and E1-E6. These latches may be similar to the other latches described above. The latches each have a data input D and a clock input C, the clock inputs of latches D1 to D7 being connected together and to the conductor ST1. Likewise the clock inputs E1 to E6 are connected together and to a clock input ST2. A pulse to gates D1 to D7 on ST1 enables these gates to receive data from the ROM. Subsequently, a pulse ST2 enables gates E1 to E6 to receive data from the ROM.
Referring now to Figure 3d, the timer 40 is disclosed in more detail and a pair of signal inputs labeled start and display pulse are connected to the set and reset inputs of a flip-flop 100. A first output of the flip-flop 100 is connected to a conductor EN2 and the opposite output is connected to to conductor EN1, the EN2 conductor previously having been described as being connected to the enable inputs of input gating means 56 and the conductor EN1 having been previously described as being connected to the enable inputs of gating means 57. The start and display inputs are also connected to the inputs of an AND-gate 101, and the output of the AND-Gate is connected to the set input of a flip-flop 102. The output of the flip-flop 102 is connected to one input of an AND-gate 103, the other input of which is pulsed by a 250-kHz. clock. The output of AND-gate 103 is connected to the input of a decade counter of the binary coded decimal type such as the Motorola MC 838. The four conventional outputs of the binary coded decimal counter are connected to the input of a BCD to decimal decoder or stepper 105. total of 13 bits into 0 through 9 of which outputs 1 through 8 are inverted with respect to outputs 0 to 9. Stepper output 1 is directly connected to one input of an AND-gate 106 and also to one input of a NAND-gate 107. Output 2 of the stepper is directly connected to an input of a NAND-gate 108. Stepper output 3 is directly connected to an input of an AND-gate 109. Stepper output 4 is directly connected to an input of NAND-gate 110. Stepper output 5 is directly connected to an input of AND-gate 111 and to an input of a NAND-gate 112. Stepper output 7 is directly connected to an input of an AND-gate 113 and to an input of a NAND-gate 114. Stepper output 8 is directly connected to one input of an AND-gate 115 and also to one input of a NAND-gate 116. Stepper output 9 is connected by a conductor 120 to the reset input of flip-flop 102. Gates 107, 108, 110, 112, 114 and 116 have their second inputs all connected together to the conductor EN1 from the output of flip-flop 100. Similarly, gates 106, 109, 111, 113 and 115 have their second inputs connected together to the conductor EN2 from the other output of flip-flop 100. Thus, half of these gates are enabled by a signal on line EN2 and the other half are enabled by a signal on line EN1.
The output of gate 106 is a conductor T1 which is connected to the a input of the ROM 12 and is also connected to the clock pulse inputs of the latches in output storage 13, as has been described above. The output of AND-gate 109 is a conductor T3 which is connected to the b input of the ROM 12 and is also connected to the clock inputs of the latches in the output storage 14. The output of AND-gate 111 is a conductor T5 which is connected to the c input of the ROM is also connected to the clock input of latch C5.
The output of the NAND-gate 107 is a conductor XX1 which is connected to the input of an inverter 120 and to one input of the NAND-gate 121. The output of NAND-gate 108 is a conductor XX2 which is connected to the other input of NAND-gate 121 and to the input of an inverter 122. The NAND-gate 110 has its output directly connected by a conductor XX4 to the input of an inverter 123 and to one input of a NAND-gate 124. The NAND-gate 112 has its output connected by a conductor XX5 to the other input of NAND-gate 134 and is also connected to the input of an inverter 125. The output of NAND-gate 114 is connected by a conductor XX7 to the input of an inverter 126 and also to one input of a NAND-gate 128. The NAND-gate 116 has its output connected by a conductor XX8 to the input of an inverter 127 and also to the other input of NAND-gate 128.
A gating network 130 functionally comprises a plurality of AND gates a, b, c, d, e and f which the outputs of a, c and being connected to a conductor CGDIN and with the gates b, d and f being connected to an output conductor CGEIN, these two conductors terminating at the d and e inputs of the ROM. The AND function should be implemented by NAND gates followed by inverters. The output of inverter 120 is a conductor ST1 which is connected to one input of the gate a. The output of inverter 122 is a conductor ST2 connected to one input of the gate b. The output of NAND-gate 121 is a conductor NIXIEN 1 which is connected to the other input of gates a and b. The output of inverter 123 is a conductor ST3 which is connected to one input of the gate c and the output of the inverter 125 is a conductor ST4 which is connected to one input of the gate d. The output of NAND gate 124 is a conductor NIXIEN 2 which is connected to the second inputs of gates c and d. The output of inverter 126 is a conductor ST5 which is connected to one input of the gate e and the output of inverter 127 is a conductor ST6 which is connected to one input of the gate f. The output of NAND-gate 128 is a conductor NIXIEN 3 which is connected to the second inputs of gates e and f. The ST1 and ST2 conductors are also connected to the NIXIE storage 32; the conductors ST3 and ST4 are connected into the NIXIE storage 33; and the ST5 and ST6 conductors are connected into the NIXIE storage 34 to enable the storage at the proper time to accent data from the ROM. The NIXIEN 1 conductor is also connected to the gate means 25 as has been previously discussed; the NIXIEN 2 conductor is also connected to the gate means 25 as has been previously discussed; and the NIXIEN 3 conductor is also connected to the gate means 27.
OPERATION
The start pulse operates flip-flop 100 to cause output line EN2 to be high or "one" and line EN1 to be low or "zero," as shown in FIG. 4. EN2 is effective to enable the gates 56 so that the input data word can be applied to the ROM. The start pulse is also applied through the gate 101 to set flip-flop 102 which enables AND-gate 103 and follows decade counter 104 and stopper 105 to commence counting at a 250-kHz. rate.
With the stepper at position 1, a timing pulse T1 is generated which enables the ROM at input a and also enables the seven latches A1 through B2. The 6-bit input word into the ROM when enabled at a provides a first 7-bit output which sets the seven enabled latches.
At stepper position 2 nothing occurs. At stepper position 3 the pulse T3 is generated which enables the ROM at input b and also enables the seven latches B3 through C4. The 6-bit input word in the ROM when enabled at b provides a second 7-bit output which sets the seven enabled latches.
At stepper position 4 nothing occurs. At stepper position 5 the pulse T5 is generated which enables the ROM at input c and also enables the next seven latches, of which only C5 is shown. The 6-bit input word in the ROM which enabled at c provides a third 7-bit output which sets the third set of latches including C5. The information needed for typewriter instruction is now set into the 15 latches. At position 9 of the stepper the flip-flop resets and the counting stops.
The code set into the latches in addition to providing three 5-bit codes to the typewriter interface for the three-letter-type output is now run into the ROM six times to provide therefrom six sets of 7-bit code to be loaded into the NIXIE storage for the three letter NIXIE display. To do this the display pulse, Figure 5, initiates the count again and operates the flip-flop 100 so that EN1 is high and EN2 is low. The gates 56 are disabled disconnecting the input data word from the ROM and enabling gate means 57 so that the latch stored signals can be entered into the ROM. At stepper position 1, pulses XX1, ST1, NIXIEN 1, and CGDIN are generated. At stepper position 2 pulses XX2, NIXIEN 1, ST2, and CGEIN are generated. At stepper position 4, pulses XX4, ST3, NIXIEN 2, and CGDIN are generated. At stepper position 5 pulses XX5, ST4, NIXIEN 2, and CGEIN are generated. At stepper position 7, pulses XX7, ST5, NIXIEN 3, and CGDIN are are generated. At stepper position 8 pulses XX8, ST6, NIXIEN 3, and CGEIN are generated. The Pulses NIXIEN 1, NIXIEN 2 and NIXIEN 3 enable the gates 25, 26, and 27 in sequence so that three 5-bit words stored in the latches A1 to C5 are entered into the ROM.
Let us assume an example in which it is desired to generate the characters GPM (gallons per minute) to be printed out on the typewriter and displayed on the NIXIE display. Figure 8 shows selected portions of a 64 -word chart in which the 6-bit binary word is indicated on the left and the printed word to be displayed on typewriter at the right. The input word No. 55 is to print GPM. A 6-bit input work 110111 (which is 55 in decimal), Figure 9, is fed into the ROM when the gates 56 are enabled by EN2 and the ROM inputs a, b and c are sequentially strobed by pulses T1, T3 and T5. The T1 pulse also enables seven latches A1, A2, A3, A4, A5, B1 and B2 and these latches are loaded with the T1 output of the ROM. Subsequently, the T3 pulse again enables the ROM and seven more latches and this output is loaded into the seven latches B3, B4, B5, C1, C2, C3 and C4. Then the T5 pulse again enables the ROM and another seven latches, of which only C5 is shown, are loaded with the T5 output of the ROM. The ASCII code (American Standard Code) for upper case letters of the alphabet is shown in Figure 6. The 15 latches provide three sets of five bits output on the Q output terminals which are fed into the typewriter interface and typewriter to print the letters GPM. Thus the output of latches A1, A2, A3, A4 and A5 may be 00111, the ASCII (American Standard Code) for the letter G, the output of latches B1, B2, B3, B4 and B5 may be 10000 for the letter P and the output of latches C1, C2, C3, C4 and C5 may be 01101 for the letter M as is shown in Figure 10.
The three 5-bit codes loaded into the latches are now used as input to the ROM to generate the NIXIE characters GPM.
In this example it is desired to display as well as type the letters GPM so a display pulse is originated by equipment, not shown. The display pulse triggers the flip-flop 100 to cause EN1 to be high and EN2 low, Figure 5. The gates 56 from the input data word are now disabled and the display gates 57 are enabled. The EN1 signal also enables gates 107 and 108 to provide an XX1 pulse followed by an XX2 pulse as the stepper moves through steps 1 and 2. The sequential signals XX1 and XX2 cause gate 121 to provide a NIXIEN 1 pulse, Figure 5. The NIXIEN 1 pulse enables gates 25 a to e and the Q outputs or "not" of latches A1, A2, A3, A4 and A5 carrying code for the letter G, Figure 11, pass the gates 25a to e, conductors 80-84, display gates 57 and input gating 60 to the ROM. The XX1 pulse is also inverted by inverter 120 and generates strobe pulse ST1. Pulse ST1 and NIXIEN 1 operate AND-gate 130a to generate pulse CGDIN which is applied to ROM input d. The resulting 7-bit output of the ROM is entered into the NIXIE storage 32 latches D1 to D7 as enabled by ST1. The XX2 pulse generates ST2 through inverter 122. ST2 enables the NIXIE storage means 32 latches E1 to E6 and also together with NIXIEN 1 operates gate 130b to generate CGEIN and pulse CGEIN is applied at ROM input e. Six bits of the resulting 7-bit output of the ROM is entered into the NIXIE storage 32 latches E1-E6 thereby providing 13 bits into storage 32. FIG. 7 is a partial chart of the NIXIE code for the 13 segment NIXIE indicator. The chart includes the letters of the cited example, GPM. The NIXIE indicators are shown in more detail in Figure 16. The progression of the five bits from storage 13, through gates 25 and 11, into the ROM, the ROM output and the NIXIE storage input may be followed in Figures 11, 12, 13 and 14.
The stepper now moves to position 3 but since EN2 is low nothing happens. At stepper position 4, XX4 is generated which in turn generates both ST3 and NIXIEN 2. NIXIEN 2 is applied to gates 130c and 130d and also to the five gates 26a to e. The enabling of these five gates allows the Q or "not" outputs of latches B1, B2, B3, B4 and B5 to be coupled by conductors 80-84, gate means 57 and gate means 60 into the ROM. Pulses ST3 and NIXIEN 2 generate pulse CGDIN at 130c which is applied at ROM input d. The first seven bits for the second NIXIE character are loaded into the NIXIE storage 33. The stepper moves into position 5 generating XX5 which generates ST4 and NIXIEN 2. ST4 generates CGEIN at 130d to enable the ROM at input e thus loading a second six bits for the second NIXIE character into the NIXIE storage 33.
At position 7 of the stepper XX7 is generated which generates ST5 and NIXIEN 3. Pulse ST5 is applied to the NIXIE storage 34 and also to gate 130e. NIXIEN 3 is applied to gate 130e to generate CGDIN and enable the ROM at d. NIXIEN 3 is also applied to enable gate means 27 allowing the Q or not outputs of latches C1, C2, C3, C4 and C5 to be loaded into the ROM as described above. The 7-bit output from the ROM is loaded into the NIXIE storage 34 as the first seven bits of the third character.
At position 8 of the stepper XX8 is generated which generates ST6 and NIXIEN 3. Pulse ST6 enables the NIXIE storage 34 and together with NIXIEN 3 generates CGEIN to enable the ROM at input e. The output of the ROM goes into the NIXIE storage 34 as the sixth set and final set of code needed to generate the letters GPM in the NIXIE display. The NIXIE input information for the example GPM is shown in Figure 14, and the resulting display in Figure 16.