04/772781

06/01/1971

11/01/1968

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Societe Industrielle Bull-General Electric
, (Paris, FR)

710/31

G06F13/12; G06F3/04; G06F3/00

340/172.5 235/157

Shaw, Gareth D.

I claim

1. A data processing system comprising a central unit including a data memory, an instruction memory containing more particularly data transfer control instructions, and a central control unit adapted to control the successive extraction of the instructions from the said instruction memory, a first data transfer channel, a second data transfer channel, a plurality of peripheral elements each connected to the first channel and to the second channel, the said first channel being connected to the instruction memory and to the data memory in order to transfer the data extracted from these two memories to the said peripheral elements, the said second channel being connected to the data memory in order to transfer the data from the peripheral elements to the data memory, and a plurality of functional connecting systems, each of them being associated with a peripheral element to control the operation of the said peripheral element, each functional connecting system comprising an instruction-decoding register connected to the first channel to receive a transfer control instruction extracted from the instruction memory, an order memory containing particular characters called code orders, which are intended for the central control unit in order to indicate the direction in which a data transfer is to take place between the central unit and the peripheral element associated with the said connecting system, and a local control unit connected to the order memory and to the instruction register of the said connecting system in order to control the extraction of a code order from the order memory, under the control of the instruction-decoding register and in dependence upon the direction of transfer specified by the instruction contained in the said register, the said order memory being connected to the second channel in order to transmit this code order to the central unit, the central control unit comprising a code-order register connected to the second channel to receive the said code order, control means, and decoding means, said decoding means being connected to the code-order register and to the control means in order to establish in the latter, as a result of the decoding of the said code order, the switching necessary for the control of the data transfer, in the direction defined by the instruction contained in the said instruction register.

2. A data processing system according to claim 1, wherein each peripheral element and the instruction register of the associated connecting system are connected to the first channel through an input register, having a capacity of one character, and in which the central control unit comprises in addition a permanent data register which is connected to the first channel and which permanently contains a special character representing a signal indicating the availability of the central unit, the control means of the central control unit being designed to bring about, in response to the reception in the code-order register of a code order sent by a functional connecting system, the transfer of the said special character to the input register of the said connecting system, the local control unit of the said connecting system comprising a decoder connected to the said input register and designed to generate a control signal when the latter register contains the said special character, and a switching assembly connected to the said decoder and to the associated peripheral element to initiate the operation of the said element, in response to the reception of a control signal.

3. A data processing system according to claim 2, wherein each peripheral element and the order memory of the associated connecting system are connected to the second channel through an output register which has a capacity of one character, the input register being connected to the first channel through a first gate, the said output register being connected to the second channel through a second gate, the said system comprising in addition a plurality of first conductors equal in number to the peripheral elements, each of the said conductors being connected between the switching assembly of a local control unit and the control means of the central control unit in order to transmit to the said control means a character transfer demand signal sent by the said switching assembly, and a number of second conductors equal to the number of peripheral elements, each of the said second conductors being connected between the switching assembly of a local control unit and the control means of the central control unit in order to transmit to the said switching assembly a transfer control pulse generated by the said control means in response to a character transfer demand signal sent by the said switching assembly, the said switching assembly being designed to emit a character transfer demand signal in response to the reception of a control signal sent by the decoder, and to transmit a first transfer control pulse emanating from the central control unit, either to the first gate or to the second gate, depending upon the direction of transfer specified by the instruction contained in the instruction register, in order to initiate the transfer of the first of a series of transfer characters, the said switching assembly also being designed to emit thereafter successive transfer demand signals, in response to each of which a transfer control pulse is transmitted to the said assembly and applied to one of the two gates in order to initiate the transfer of a corresponding character.

4. A data processing system according to claim 3, wherein the instruction memory, the data memory and the permanent data register of the central control unit are connected to the first channel through an output register of the central unit, having a capacity of one character, and wherein the data memory and the code-order register of the central control unit are connected to the second channel through an input register of the central unit, which has a capacity of one character, the output register of the central unit being designed to contain temporarily, either each of the successive characters which are extracted from the instruction memory or from the data memory, or the special character indicating the availability of the central unit, the input register of the central unit being intended to contain temporarily, either each of the successive characters which are successively sent by a peripheral element and are to be stored in the data memory, or a code order which, after having been extracted from the order memory of a functional connecting system, is sent to the central unit, the transfer of a character contained in the output register of the central unit to the input register associated with a peripheral element being initiated by the application of a transfer control pulse to the corresponding first gate, the transfer of a character contained in the output register associated with a peripheral element to the input register of the central unit being initiated by the application of a transfer control pulse to the second gate associated with this peripheral element.

5. A data processing system according to claim 4, wherein the permanent data register is composed of a first stage which permanently contains the special character representing a signal indicating the availability of the central unit, and of a second stage which contains a particular coded character, called the "operating" character, which is intended to establish in the switching assembly of a local control unit the switching necessary for the control of the storage of an instruction in the associated instruction register, the said second stage being connected to the output register of the central unit to transmit the said "operating" character to the said output register, under the control of the control means of the central control unit, the transfer of the said character to the input register of a chosen peripheral element for performing an operation being initiated by the application, to the first gate associated with this peripheral element, of a first transfer control pulse generated by control means of the central control unit and transmitted through the switching assembly of the local control unit associated with the said element.

6. A data processing system according to claim 5, wherein the instruction register of each of the functional connecting systems is connected to the input register associated with the said system through a third gate subject to the control of the switching assembly of the local control unit of the said system, the decoder of this control unit being also adapted to generate a recognition signal when this input register contains an "operating" character, the said switching assembly also being adapted to transmit to the control means of the central control unit, in response to the reception of a recognition signal sent by the decoder, a series of character transfer demand signals, for applying to the first gate the first transfer control pulse sent by the control means, so as to initiate the transfer of the first character of an instruction contained in the output register of the said central unit to the said input register, and in addition to apply the said first pulse with delay to the third gate in order to bring about the transfer of this first character contained in the input register into the corresponding instruction register, the transfer of the succeeding characters of this instruction being effected similarly by the application, to the first gate and then to the third gate, of the transfer control pulses generated by the control means of the central control unit.

7. A data processing system according to claim 6, wherein the instruction register of each of the functional connecting systems comprises, for the storage of an instruction, a number of stages equal to the number of characters constituting this instruction, each instruction comprising a predetermined number of characters established in relation with the nature of the associated peripheral element, including at least one character indicating an operation to be performed, each of the stages of the instruction register being intended to store the corresponding one of the characters of the said instruction.

8. A data processing system according to claim 7, wherein each local control unit comprises in addition a second decoder connected to that one of the stages of the associated instruction register which is intended to contain the operation-indicating character for performing the decoding of the said character and producing signals indicating the result of the said decoding, the switching assembly of the said local control unit being connected to the said second decoder in order to receive the signals generated by the said decoder and also being adapted to control the operation of the associated peripheral element, in response to the signals received, in order to perform the operation specified by the said operation-indicating character, this operation consisting either in an operation for reading or writing characters on an information-recording medium, or in a positioning of the said medium.

9. A data processing system according to claim 8, wherein each local control unit comprises in addition means for indicating the state of a register, which are connected on the one hand to the associated instruction register for detecting the state of occupation of the stages of this register and generating a particular signal as soon as all the characters of an instruction have been transferred into the said register, and on the other hand to a first corresponding conductor for transmitting this particular signal to the control means of the central control unit in order to establish in the said means the switching necessary for the control of the storage, in the code-order register, of a code order emanating from the order memory associated with the said local control unit, the transfer of this code order from this order memory to the associated output register being initiated simultaneously with the dispatch of the said particular signal to the control means of the central control unit.

10. A data processing system according to claim 9, wherein the code-order register is connected to the input register of the central unit through a gate subject to the control of the control means of the central control unit, the said control means being adapted to transmit a transfer control pulse to the said local control unit, in response to the reception of a particular signal emanating from a local control unit, in order to initiate the transfer of the code order contained in the output register associated with this local control unit to the input register of the central unit and to transmit a pulse to the said gate in order to produce the transfer of the said code order contained in the input register of the central unit to the code-order register.

11. A data processing system according to claim 10, wherein the central control unit comprises in addition a signal-differentiating member connected on the one hand to the first conductors to receive the signals sent by the local control units and on the other hand to the control means of the central control unit to establish in the said control means a switching which differs in accordance with whether the signal received through a first conductor is a character transfer demand signal or a particular signal sent by a local control unit at the end of the transfer of an instruction into the associated instruction register.

12. A data processing system comprising a central unit including a central control unit and memory means; a plurality of peripheral elements; said memory means storing data and peripheral control instructions, each of said peripheral control instructions being adapted to control a peripheral element to perform a respective operation; input data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said memory means to said peripheral elements; output data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said peripheral elements to said memory means; a peripheral controlling member coupled to said peripheral elements to control the operation thereof, said peripheral controlling member including an instruction register, an instruction decoder coupled to said instruction register and responsive to the instruction contents thereof to generate a peripheral control signal representative of said instruction contents, an order memory for storing a plurality of code orders, and a local control unit; each of said code orders being adapted to control said central unit to cooperate with a peripheral element in the execution of a respective peripheral operation; said central control unit controlling the retrieval of said peripheral control instructions from said memory means and the transfer of said retrieved instructions from said central unit to the instruction register of said peripheral controlling member; said local control unit responding to the entry of an instruction into said instruction register and controlled by the corresponding peripheral control signal to retrieve the corresponding code order from said order memory and to control the transfer of said retrieved code order to said central control unit; said central control unit being responsive to a code order received thereby for configuring said central unit to participate with the corresponding peripheral element in the execution of the respective peripheral operation represented by said code order received.

13. A data processing system comprising a central unit including a central control unit and memory means; a plurality of peripheral elements; said memory means storing data and peripheral control instructions, each of said peripheral control instructions being adapted to control a peripheral element to perform a respective operation; input data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said memory means to said peripheral elements; output data transfer means coupling said central unit to said peripheral elements and controllable to transfer data from said peripheral elements to said memory means; a plurality of peripheral controlling members coupled to said peripheral elements to control the operation thereof, each of said peripheral controlling members including an instruction register, an instruction decoder coupled to said instruction register and responsive to the instruction contents thereof to generate a peripheral control signal representative of said instruction contents, an order memory for storing a plurality of code orders, and a local control unit; each of said code orders being adapted to control said central unit to cooperate with a peripheral element in the execution of a respective peripheral operation; said central control unit controlling the retrieval of said peripheral control instructions from said memory means and the transfer of said retrieved instructions from said central unit to the instruction registers of the corresponding peripheral controlling members; each of said local control units responding to the entry of an instruction into the respective instruction register and controlled by the corresponding peripheral control signal to retrieve the corresponding code order from the respective order memory and to control the transfer of said retrieved code order to said central control unit; said central control unit being responsive to a code order received thereby for configuring said central unit to participate with the corresponding peripheral element in the execution of the respective peripheral operation represented by said code order received.

14. The apparatus of claim 13, wherein, when the instruction received by a peripheral control member specifies an operation to transfer data from said memory means to a peripheral element, the respective local control unit retrieves from the respective order memory a code order denoting the requirement for a data transfer from said memory means to a peripheral, and wherein said central control unit responds to said code order to activate said input data transfer means for transfer of data.

15. The apparatus of claim 13, wherein, when the instruction received by a peripheral control member specifies an operation to transfer data from a peripheral element to said memory means, the respective local control unit retrieves from the respective order memory a code order denoting the requirement for a data transfer from a peripheral element to said memory means, and wherein said central control unit responds to said code order to activate said output data transfer means for transfer of data.

The present invention relates to improvements in devices for transferring information between a central unit and peripheral elements.

Machines employed for information processing generally comprise a central unit which in turn contains a control set, a computing set and a high-speed memory which is readily accessible to the control and arithmetical circuits associated with the control unit. The central unit is connected to a number of peripheral elements such as card or punched-tape readers, magnetic tape units, printers, card punchers, etc., through input and output communications tracks which will be referred to as "channels" in the present description.

Machines are known in which the peripheral elements are connected to the central unit by means of two channels. One, called the input or collector channel, is employed to introduce data into the central unit from a peripheral element. The other, called the output or distributor channel, is employed to transfer data from the central unit in the direction of a peripheral element.

Although in these known machines the peripheral elements may be connected in accordance with a "star" arrangement, i.e. one in which each peripheral element is directly connected in the central unit by means of two separate channels and in which there are consequently as many output channels and input channels as there are peripheral elements, it has been found more advantageous, for the purpose of reducing the number of channels, to employ a single input channel and a single output channel and to connect the peripheral elements in parallel with these two channels. In this case, however, it is important to provide each peripheral element with appropriate switching circuits, sometimes called gates, which have the object of effecting the switching necessary for the transfer of the data between the central unit and the chosen peripheral element.

Machines are known in which each peripheral element is characterized by an address defined in coded form. When an address is sent by the central unit to the input channel, this address is simultaneously received by all the switching circuits associated with the peripheral elements. Decoding members cooperating with the said switching circuits then effect the decoding of this address and generate signals which indicate the result of the decoding. These signals then act on the switching circuits in such manner that only the switching circuit associated with the peripheral element determined by the said address effects the switching between the said element and the transfer channels. As soon as this switching has been effected, the transfer of the data between the central unit and the said element may take place.

On the other hand, in other machines in which the peripheral elements are connected in parallel with the transfer channels and in which the transfers of data between the central unit and the peripheral elements take place at high speed, the selection of a peripheral element involved in a transfer is effected by a decoding member which forms part of the central unit and which is provided with a number of outputs, each of these outputs being connected, respectively, to one of the switching circuits of the peripheral elements through a single control conductor, the said decoding member being designed to excite the control conductors selectively so that only the control conductor associated with the peripheral element concerned in the transfer is excited. Under these conditions, the switching circuit of this element effects the switching between the said element and the transfer channels.

However, in all these machines, as soon as the switching has taken place between a peripheral element and the central unit, the transfer of the data between the central unit and this peripheral element, in one direction or the other, is controlled by the control circuits of the central unit. Owing to the great diversity of these peripheral elements, which are distinguished from one another by their functions, their modes of data transmission and their rates of transfer, these control circuits are often very complex, and consequently the central unit is extremely costly and bulky.

Moreover, in machines thus designed, the structure of the central unit is such as to permit the connection, to this unit, of a defined number of peripheral elements of well-determined types, for example, of two card readers, of a printer and of a card puncher. Each peripheral element is connected in known manner to the central unit through a particular control system which forms part of the central unit and which is specially designed to control the operation of the said element. Consequently, a peripheral element of a particular type, such as a card reader for example, cannot be connected to the central unit through a control system which has been designed to control a peripheral element of a different type, for example of a printer. It follows that when a user desires to connect to the central unit peripheral elements differing in number or type from the peripheral elements initially provided, it is necessary first of all to ask for relatively extensive modifications to be made to the central unit in order to adapt it to the operation of the peripheral elements which it is desired to connect. Not only can these modifications be effected only by specialized personnel, but in addition they often cause the central unit to be placed out of service for a very long time and necessitate a very detailed checking of the circuits of this unit before the machine is put into operation. In addition, these modifications are more difficult to make since the central unit is very complex and the necessary space is not always available within this central unit for accommodating therein the new matching circuits.

The present invention seeks to obviate these disadvantages by providing a machine in which the central unit is simplified and does not necessitate considerable modifications for adapting it to the connection of new peripheral elements. Moreover, in the proposed machine, each peripheral element is provided with a functional connecting system which contains control circuits for effecting the particular connection of this element to the central unit.

One object of the invention concerns a data processing machine which comprises on the one hand a central unit including a central control unit, a data memory, processing devices and an instruction memory containing, in particular, data-transfer control instructions, and on the other hand a plurality of peripheral elements connected to the said central unit through transfer channels, the said machine being characterized in that each peripheral element is provided with a functional connecting system comprising an instruction register designed to store a transfer-control instruction extracted from the instruction memory and transmitted to the said register through transfer channels, an order memory containing particular data, called code orders, which specify, in accordance with the type of peripheral element, the direction in which a data transfer is to take place character-by-character between the data memory and the said peripheral element, and a local control unit designed to select, in the order memory, and under the control of the instruction contained in the instruction register, a code order corresponding to the direction of transfer determined by this instruction, and to transmit the said code order to the central control unit, the said machine being characterized in addition in that, for the transmission of the first character of the data to be transferred between the data memory and a particular peripheral element, the central control unit transmits to the local control unit of the said element, in response to the reception of a code order, a signal indicating the availability of the central unit, which triggers the direct transmission to the central control unit, by the said local control unit, of a character-transfer demand signal in response to which the central control unit directly sends to the said local control unit a pulse for the control of the transfer of the character, the transfer thus ordered being effected, through the transfer channels, in the direction determined both by the instruction contained in the instruction register of the element concerned and by the code order which has been transmitted to the central control unit.

For a better understanding of the invention and to show how it may be carried into effect, the same will now be described, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 is a general diagram of the arrangement of the machine,

FIGS. 2A to 2H represent, when assembled, a detained logical diagram of the control circuits of the central unit,

FIG. 2 shows how FIGS. 2A to 2H are assembled,

FIGS. 3A to 3H represent, when assembled, a detailed logical diagram of the circuits employed to control the operation of the magnetic tape units,

FIG. 3 shows how FIGS. 3A to 3H are assembled,

FIG. 4 is a logical diagram of a device for discriminating the signals which are sent by the peripheral elements, and

FIGS. 5 and 6 are diagrams showing the state, as a function of time, of the main points of the device of FIG. 4, in order to illustrate the operation of the said device, in response to the signals received.

Before the machine illustrated in FIGS. 2A to 2H and 3A to 3H is described in detail, there will first be described the organization of the machine which has been diagrammatically illustrated in FIG. 1, for a more ready understanding of the detailed description which will thereafter be given.

The machine illustrated in FIG. 1 comprises a central unit which will hereinafter be described, and to which there are connected, through transfer channels VCQ and VDQ, a plurality of peripheral elements, of which only four, denoted by OT-1, OT-2, OT-3 and OT-4, are shown, obviously for the sake of simplicity. The central unit comprises in particular an instruction memory 10 in which program instructions have been written. It will be assumed that these instructions belong to different categories depending upon the work which they can control and that, in the described example, they consist of processing instructions for controlling arithmetical or logical operations, of so-called "peripheral" instructions which permit of controlling either the transfer of information between the central unit and the peripheral elements in one direction or the other, or the positioning of the information-recording medium of a peripheral element, and branch instructions for orienting the performance of the program towards particular sequences. The selection and the extraction of each of the instructions contained in the memory 10 take place in known manner by means of selection control members 11 connected to the said memory. The instructions extracted are transmitted to and stored in an intermediate register 12. The selection control members 11 are set in operation by control pulses transmitted from a central control unit 13 through a conductor CL, while the selection is effected in known manner under the control of an address contained in a selection register 14 connected to the selection control members 11.

If the instruction which has been extracted from the memory 10 and which is contained in the intermediate register 12 is a processing instruction or a branch instruction, this instruction is transmitted, in a manner which will hereinafter be indicated, to an internal instruction register RITB in which it is then decoded in order to control the various circuits of the central unit for the purpose of performing the work specified by this instruction. The instruction register RITB is shown in dashed lines, because it is not utilized in the present invention. However, it will be understood that the central unit normally comprises means for controlling the work specified by the processing instructions, such as the performance of the usual arithmetical operations, for example, and means for orienting the program in accordance with the conditions specified by the branch instructions, and that the register RITB is employed to decode these instructions.

If, on the other hand, the instruction which has been extracted from the memory 10 and which is contained in the intermediate register 12 is a "peripheral" instruction, i.e. one which can control either the positioning of the information recording medium of a particular peripheral element or a transfer of data between the central unit and a particular peripheral element, this instruction is transmitted to one of the four standby registers RI-1, RI-2, RI-3, RI-4, in a manner which will hereinafter be indicated, in which it is then temporarily stored before being transferred to the peripheral element for which it is intended. It is useful to note here that each of the standby registers RI-1 to RI-4 is associated with a particular peripheral element and that consequently the peripheral instruction contained in the register RI-1 is intended for the peripheral element OT-1, that contained in the register RI-2 is intended for the peripheral element OT-2, and so on. There are therefore at least as many standby registers as there are connected peripheral elements. In practice, the number of standby registers may be greater than the number of peripheral elements actually connected, and therefore, under these conditions, as many peripheral elements as desired may be connected to the central unit provided that their number does not exceed that of the standby registers initially provided, this connection not necessitating any modifications to the circuits of the central unit.

The dispatch of an instruction contained in the intermediate register 12 to one of the registers RITB and RI-1 to RI-4 for which it is intended is controlled by a transfer control pulse emanating from the central control unit 13 and transmitted to a gate 30. This instruction is oriented either to the register RITB or to one of the standby registers by an instruction distribution member 15 subject to the control of a decoder-writer 16. For this purpose, there is associated with each one of the peripheral instructions contained in the memory 10 a coded indication called the peripheral element number, which specifies the number of the peripheral element for which this instruction is intended. For example, if this instruction is to be transmitted to the peripheral element OT-1, it is accompanied by a coded indication which stipulates that the peripheral element concerned is the element number 1, i.e. the element OT-1. Likewise, the element number 2 is the element OT-2, the element number 3 is the element OT-3, and so on. Each of the peripheral instructions contained in the memory 10 is extracted from this memory at the same time as the coded indication accompanying it, but while this instruction is transmitted to the intermediate register 12, its coded indication is transmitted to the decoder writer 16, in which it is then decoded. As a result of this decoding, the decoder-writer 16 transmits to the instruction distributor 15 a signal which effects the switching necessary for opening a channel in the direction of one of the registers RITB and RI-1 to RI-4. Thus, if the coded indication contained in the decoder-writer 16 indicates that the peripheral element concerned is the element number 2, the signal sent by this decoder-writer effects, in the distributor 15, the switching necessary for the opening of a channel in the direction of the register RI-2. If, at this instant, a transfer control pulse is sent by the central control unit to the gate 30, the instruction contained in the register 12 is transmitted to the standby register RI-2. It is useful to note that, in the case where the instruction contained in the register 12 is a processing or branch instruction and is consequently not accompanied by any coded indication, the decoder-writer 16 is at zero and the distributor 15 then opens the channel in the direction of the register RITB.

The transfer of the information between the central unit and the peripheral elements takes place through an input channel VDQ, through which the information is sent by the central unit in the direction of the peripheral elements, and through an output channel VCQ through which the information sent by the peripheral elements is transmitted to the central unit. The input channel VDQ is connected on the one hand to the register EVDQ, called the output register of the central unit, and on the other hand to a plurality of input registers of the peripheral elements, of which only four, denoted by RVDQ-1 to RVDQ-4, are shown, each peripheral element being provided with a corresponding input register. The output channel VCQ is connected on the one hand to a register RVCQ, called the input register of the central unit, and on the other hand to a plurality of output registers of the peripheral elements, of which only four, denoted by EVCQ-1 to EVCQ-4 are shown, each peripheral element being provided with a corresponding output register.

In FIG. 1, there have only been shown four peripheral elements. Consequently, only four input registers, denoted by RVDQ-1 to RVDQ-4, and four output registers, denoted by EVCQ-1 to EVCQ-4, have been shown, but it is obvious that in practice there are as many input registers and as many output registers as there peripheral elements.

Each peripheral element comprises in accordance with its type, either only reading devices (case of card or punched-tape readers, for example), or only writing or printing devices (case of card punchers or printers, for example), or again reading and writing devices (case of magnetic tape units, card or punched-tape readers-punchers, or magnetic disc units, for example). These reading and/or writing devices are now well known and it will be assumed that in FIG. 1 they form part of the blocks OT-1 to OT-4, which diagrammatically represent the peripheral elements.

In accordance with the invention, each of the peripheral elements is also provided with a particular control system, called a functional connecting system, by means of which it is possible on the one hand to control the operation of the peripheral element with which it is associated, and on the other hand to cooperate with the local control unit, in a manner which will hereinafter be described, in order to control the transfer of information between this peripheral element and the central unit, in one direction or the other. Four functional connecting systems, denoted by BLF-1 to BLF-4, have been shown in FIG. 1, each being associated with one of the four peripheral elements shown.

FIG. 1 also shows that gates S1, S2, S3, S4, subject to the control of the control unit 13 and associated with the standby registers RI-1, RI-2, RI-3, RI-4 respectively, perform the switching necessary for the transfer of an instruction contained in one of the registers RI-1 to RI-4 to the output register EVDQ. This instruction is thereafter transmitted through the input channel VDQ, under conditions which will hereinafter be described, to that one of the input registers RVDQ-1 to RVDQ-4 which is associated with the peripheral element for which it is intended.

Each of the functional connecting systems such as BLF-1 is composed essentially of an instruction register, such as RD-1, of an order memory such as MO-1, which will hereinafter be referred to, and of a local control unit such as UCL-1. The function of the instruction register is to store an instruction intended for the peripheral element with which it is associated, this instruction emanating from a corresponding standby register and being transmitted to the said instruction register through the output register EVDQ of the input channel VDQ and through the input register of this peripheral element. For example, the instruction register RD-2 of the connecting system BLF-2 is intended to store an instruction which emanates from the standby register RI-2 and which is transmitted thereto through the register EVDQ, the channel VDQ and the input register RVDQ-2. The instruction contained in the instruction register of a connecting system is decoded in known manner by decoding members which form part of the local control unit of the said system.

It is to be noted here that the instructions intended for the peripheral elements are distinguished from one another by their construction, which is designed by the programmer in accordance with the type of each peripheral element and the work to be performed. It will be assumed that these instructions may comprise a variable number of characters which, in the example described, will be between 1 and 5, but that those intended for a common peripheral element comprise a fixed number of characters. The first character of each instruction, called the "type of operation" character or T.O. character, defines the fundamental operation to be performed by the instruction. For example, the T.O. character of an instruction sent to a printer will control the printing, while that of an instruction sent to a magnetic tape unit will control the reading of a block of data recorded on the tape.

Generally speaking, the instructions which, when sent to the peripheral elements trigger an operation for the transfer of data between these elements and the central unit, as will hereinafter be indicated, are called transfer control instructions. In these instructions, the T.O. character will bring about either a printing or writing operation or a data reading operation.

In some cases, however, it will be necessary to control the positioning of the information-recording medium of a peripheral element before a transfer control instruction is transmitted thereto. For example, if it is desired to bring about the reading of a particular block of data recorded on a magnetic tape of a tape unit, but the said block is not situated under the reading circuits of this unit, it is necessary, in order to be able to read this block, first to shift the tape to such an extent that the beginning of this block is situated exactly under the reading circuits, whereafter the reading of this block can be brought about. The prior positioning will be obtained by sending to this tape unit a positioning instruction which will order the displacement of the tape and its positioning on the desired block of data. The reading of this block will then be triggered after a transfer control instruction has been transmitted to the said tape unit.

Finally, the instruction register of a functional connecting system associated with a peripheral element may contain either a positioning instruction or a transfer control instruction which brings about a transfer of data between this element and the central unit. The direction in which a transfer of data controlled by a transfer control instruction is to take place is determined by the T.O. character of this instruction. Thus, if the T.O. character of this instruction brings about a printing or writing operation, the data to be printed or written must be transferred from the central unit to the peripheral element concerned, while if this character brings about a reading operation, the data read by the reading circuits of the element concerned in the transfer must be transmitted by this element to the central unit.

In the order memory of a functional connecting system associated with a peripheral element, particular data, called code orders, have been written. Each of these code orders stored in the order memory of a functional connecting system associated with a peripheral element consists, in the described example, of a single coded character and is employed, when a transfer of data is to take place between the central unit and this element under conditions which will hereinafter be explained, to specify to the central control unit 13 the direction in which this transfer is to take place. More precisely, a code order may specify that the transfer of data will take place along the output channel, or that it will take place along the input channel. The selection of these code orders in the order memory of a functional connecting system will be effected by the local control unit of this system, in dependence upon the decoding of the T.O. character of the instruction contained in the instruction register of the said system. For example, if this T.O. character stipulates that the operation to be performed is "printing" the code order which will be selected by the local control unit will be the "input channel transfer" code order, which will thus specify that the data to be printed will be transmitted by the central unit and through the input channel to the printer which is to perform this operation.

Each of these code orders thus selected in the order memory of a functional connecting system is transmitted to the output register of the peripheral element with which it is associated, under the control of the local control unit of this system and under conditions which will hereinafter be specified. The code order contained in this output register is thereafter transferred to the register RVCQ through the output channel VCQ and from there through a gate 21 subject to the control the central control unit 13, to a decoding register RCO which forms part of this unit 13. This decoding register RCO has the object of recording and decoding a code order sent by a functional connecting system associated with a peripheral element, in such manner that, as a result of this decoding, a switching is effected in the control circuits constituting the central control unit to enable the said unit to bring about a transfer of data in the direction specified by the said code order. When this switching has been performed, the central control unit sends to the functional connecting system which has transmitted this code order to it a signal indicating the availability of the central unit. In the described example, this signal consists of a particular coded character, called the code response, which has previously been written in a permanent data register RPU which forms part of the central control unit 13. The said code response is sent by the control unit 13 to the functional connecting system concerned, through the register EVDQ, the input-channel VDQ and the input register of the peripheral element associated with this connecting system. The local control unit of this system further comprises decoding and control circuits which are specially designed to trigger a character transfer from the instant when a code response is stored in the input register of the associated peripheral element. This transfer of characters will consist either in a transfer of the characters emanating from or intended for the writing and/or reading circuits of the peripheral element concerned in the said transfer, or in a transfer to the central unit of a special character, called the "state of apparatus" character, which will hereinafter be referred to and which is generated by the said peripheral element to indicate to the central unit the state of this element when the operation specified by the instruction contained in the instruction register has been performed.

FIG. 1 further shows that each of the local control units is directly connected to the central control unit 13 through one of a series of conductors, called order conductors and denoted by OR-1 to OR-4 respectively, and through one of a series of transfer control conductors, denoted by XREP-1 to XREP- 4 respectively. These conductors effect the coordination between the central control unit and each of the local control units to enable each local control unit to cooperate with the central control unit for performing a character transfer, character-by-character, the transfer of the first character being triggered in the following manner. From the instant when a code response is stored in the input register of a peripheral element concerned in the said transfer, the local control unit of the connecting system associated with this element transmits to the central control unit 13, through its associated order conductor, a signal calling for the transfer of a character, in response to which the central control unit sends to the said local control unit, through the associated transfer control conductor, a control pulse which triggers the transfer of the said first character, either from the register EVDQ to the input register of the element concerned, or from the output register of this element to the register RVCQ. For this purpose, the circuits constituting this local control unit are subject to the control of members which effect the decoding of the T.O. character of the instruction contained in the associated instruction register, so that the said transfer takes place in the direction specified by this T.O. character.

When a transfer control instruction specifies that data read by the reading circuits of a peripheral element must be sent to the central unit, these data pass through the output register EVCQ of this element and are transmitted to the input register RVCQ of the central unit through the output channel VCQ. From the register RVCQ, these data are transmitted through a gate EM subject to the control of the control unit 13 to an input-output register RES which is intended to receive data which are to be written in a data memory 17. This register RES is also used to receive data which has been extracted from the memory 17. The memory 17 is connected to selection control members 18 which permit either the selection and extraction of data stored in the memory 17 or the selection of memory locations in which data are to be written. The data to be written are transmitted to the memory 17 from the register RES through a gate 20 subject to the control of the control unit 13. The selection control members are set in operation by control pulses transmitted from the control unit 13, by means of conductors DL and DE, while the selection is performed in known manner under the control of an address contained in a selection register 19 which is connected to the selection control members 18. It should be noted here that the connections which have been illustrated in FIG. 1 for connecting, in the manner indicated in the diagram, the memory 17, the register RES, the selection control members 18, the selection register 19 and the control unit 13, are similar to those which have been described and illustrated in FIG. 1A of U.S. Pat. application Ser. No. 3,378,819, filed Mar. 8, 1965 of Societe Industrielle Bull-General Electric. For this reason, this arrangement will not be further discussed here. Moreover, no details will be given in the present description concerning the construction of the memory 17, of the register RES, of the selection control members 18, of the selection register 19 or of the gate 20, because these constructions are similar to those which have been described and illustrated more particularly in FIGS. 2 and 3 of the aforesaid patent. It will simply be recalled that when a pulse is sent by the control unit 13 to the selection control members through the conductor DL, called the reading conductor, the character which is written in the memory 17 at the location specified by the address contained in the selection register 19 is extracted from this memory and transmitted to the register RES, while when a pulse is sent by the control unit 13 through the conductor DE, called the writing conductor, to the gate 20 and the selection control members 18, the character which is situated in the register RES is written in the memory 17 at the location specified by the address contained in the selection register 19. In the described example, it will be assumed that the capacity of the register RES is one character and that the transfer of the data sent by a peripheral element to the memory 17 is effected character-by-character. However, if the memory 17 were so arranged as to be able to write simultaneously a predetermined number of characters in a single writing operation, there would be no disadvantage in employing an input-output register RES capable of containing a number of characters equal to the said predetermined number.

In the described example, the character which is contained in the register RES after having been extracted from the memory 17 may be transmitted to the register EVDQ through a gate SM subject to the control of the control unit 13. Thus, when a transfer control instruction specifies that certain data contained in the memory 17 must be sent to the writing circuits of a peripheral element, these data are transferred character-by-character, passing successively through the register RES, the gate SM, the register EVDQ, the input channel VDQ and the input register of this element.

As indicated in the foregoing, the code order which has been sent to the decoder-register RCO by the functional connecting system associated with this peripheral element is decoded to enable the control circuits of the control unit 13 to bring about a transfer of data in the direction specified by the said code order. Likewise, the T.O. character of the instruction contained in the instruction register of this system enables the circuits of the local control unit of this system to bring about this transfer in the direction specified by this T.O. character. It is to be noted here that this transfer takes place as follows. If the said code order and the said T.O. character specify that the transfer has to take place from the memory 17 to the peripheral element concerned, the signal calling for the transfer of a character sent by the local control unit, in response to the reception of a code response, triggers the dispatch, by the central control unit 13, of a series of control pulses which enable a character stored in the memory 17, in a location specified by the address contained in the selection register 19, to be extracted from this memory and to be transferred into the register EVDQ. This character is the first of a series of characters which are to be transferred from the memory 17 to the peripheral element under consideration. Thereafter, the central control unit 13 sends a first transfer control pulse to the local control unit concerned, with in turn brings about the transfer of this first character contained in the register EVDQ to the input register of the associated peripheral element, and from there to the writing circuits of the said element. When this transfer is complete, the local control unit again sends to the central control unit a transfer demand signal, in response to which the central control unit sends a second transfer control pulse to bring about the transfer of the next character. Thus, each time the central control unit receives a transfer demand signal emanating from a local control unit, it responds by sending to this local unit a transfer control pulse which triggers the transfer of a character to the associated peripheral element.

If, on the other hand, this code order and this T.O. character specify that the transfer is to take place from the peripheral element concerned to the memory 17, the code response which is sent by the central control unit to the local control unit triggers the reading of a first character by the reading circuits of the said element and the transfer of this character into the output register of this element. Thereafter, the local control unit sends to the central control unit a character transfer demand signal, in response to which the central control unit sends on the one hand to the local control unit concerned a transfer control pulse which brings about the transfer of the character contained in the output register of the element to the register RVCQ, and on the other hand pulses which are sufficiently retarded to bring about, when the preceding transfer has been completed, the transfer of the said character from the register RVCQ to the register RES, followed by its writing in the memory 17, in a location specified by the address contained in the selection register 19. The transfer control pulse also controls the reading of a succeeding character and its transfer into the output register, of this element. Thereafter, the local control unit then again sends to the central control unit a transfer demand signal for triggering the transfer of this second character to the memory 17, in a manner similar to that just described.

Thus, the transfer of a character between the central unit and a peripheral element, or vice versa is subordinate to the dispatch of a transfer demand signal emitted by this peripheral element and transmitted to a control unit 13, through the conductor OR associated with the said element, while the transfer of this character is in fact triggered only when the control unit 13 sends a transfer control pulse to the said element, through the conductor XREP associated therewith, in response to the signal received.

The transfer of data from the memory 17 of the central unit to a peripheral element, or vice versa therefore takes place character-by-character. This transfer ceases when a predetermined number of characters has been transferred, this number being determined either by an indication of transfer length which forms part of the instruction contained in the instruction register of the connecting system associated with the said element, or in advance when it is characteristic of the type of the peripheral element under consideration. For example, if this element is a card reader, this transfer ceases when a card has been completely read, i.e. when the 24 columns of this card have been explored. If, on the other hand, this element is a tape puncher, the transfer ceases when this puncher has received a number of characters equal to that specified by the indication of transfer length.

It is further to be noted that each peripheral element, regardless of its type, must be provided with an input register such as RVDQ-1 and with an output register such as EVCQ-1, the output register serving more particularly to contain temporarily a code order which is sent by its local control unit to the central control unit, while the input register serves more particularly to contain temporarily a code response which is sent by the central control unit to the said local control unit.

In order to set in operation a peripheral element, it is necessary to transmit thereto first of all a peripheral instruction contained in the standby register which is associated therewith. The transfer of this instruction from this standby register to the instruction register of the connecting system associated with this element takes place character-by-character in the course of a so-called "instruction dispatch" phase, or phase F1, the transfer of each character being triggered, as previously indicated, by the dispatch, by the local control unit of this system, of a transfer demand signal, in response to which the central control unit sends a transfer control pulse.

If, when this transfer has been completed, the instruction contained in the instruction register of this system is a transfer instruction, the local control unit sends to the central control unit a code order specifying the direction in which the transfer is to take place, this direction being defined by the T.O. character of the instruction. This transfer is triggered by the dispatch of a code response, by the central control unit, and takes place character-by-character in the course of a so-called "quantity transfer" phase, or phase F2, the transfer of each character between the memory 17 and this peripheral element, in the previously defined direction, taking place in the manner which has hereinbefore been indicated.

Finally, after completion of the transfer of characters in the course of the phase F2, the local unit transmits to the central control unit, in the course of a so-called "qualitative information dispatch" phase, or phase F3, a "state of apparatus" character which, on the one hand, signals any incidents which may have occurred during the operation of the peripheral element, and on the other hand constitutes a warning signal to indicate to the central control unit that the conditions which enable this peripheral element to operate normally will shortly cease to exist. These conditions vary in accordance with the type of peripheral element. Thus, for example, the "state of apparatus" character emanating from a printer may notify the central control unit that the paper tape employed for the printing is about to be exhausted. Likewise, the "state of apparatus" character emanating from a card reader may notify the central control unit that its card supply magazine will shortly be empty.

The change from the phase F2 to the phase F3 is triggered by the dispatch, from the local control unit to the register RCO of the central control unit, of a particular code order initially written in the order memory and called the "qualitative transfer preparation" code order. This code transferred into the register RCO is then decoded, and as a result of the decoding a switching is performed in the circuits of the central control unit to enable this unit to bring about the transfer of the "state of apparatus" character from the peripheral element concerned to the central unit. When this switching has been performed, the central control unit sends to the connecting system which has transmitted this code order to it a code response, which is transferred from the register RPU to the input register of the associated peripheral element. In response to a character transfer demand signal which is then sent by the local control unit, the central control unit sends to this local unit a transfer control pulse which triggers the transfer of the "state of apparatus" character to the central unit, through the output channel VCQ and the register RVCQ. It will be assumed that this character is thereafter transferred into an indicating register, called the "state of apparatus" register, which has not been shown in FIG. 1, in order to avoid unnecessary overcrowding thereof. It is further to be noted that in the case where the instruction which has been transferred into the instruction register in the course of the phase F1 is a positioning instruction, and therefore does not bring about the transfer of any character between the memory 17 and the peripheral element under consideration, the phase which is then started after the phase F1 is the phase F3. This phase is started by the dispatch from the local control unit to the register RCO of a "qualitative transfer preparation" code order, in response to which the central control unit sends to this local control unit, after decoding, a code response which triggers the operation of the peripheral element until its information-recording medium is positioned in accordance with the indications specified in the positioning instruction. As soon as this positioning has been completed, a "state of apparatus" character is transmitted from this peripheral element to the "state of apparatus" register, in a manner similar to that previously described.

To sum up, when a peripheral element is ordered to perform an operation, this operation is performed either in three phases F1, F2, F3 when it consists in a transfer of data between this element and the memory 17, or in two phases F1 and F3 when it consists in a positioning concerning this element. It is further to be noted that each of the phases F1, F2 and F3 is terminated by the dispatch of a code order to the central control unit and that the code order which is transmitted at the end of the phase F1 enables the central control unit to determine which of the two phases F2 and F3 will succeed the phase F1. However, in the case where the phase which ends is the phase F3, the code order which is transmitted to the register RCO from the order memory is a particular code order called the "end of operation" code order. This "end of operation" code order is sent at the end of the phase F3 by the connecting system associated with a peripheral element to inform the central control unit that his element has completed the operation which was required of it. Under these conditions, the central control unit sends no code response to the local control unit of this system and the associated peripheral element then becomes inoperative until it is again ordered to perform an operation.

On the other hand, when a phase ends, it is necessary for an appropriate switching to take place in the circuits of the central control unit in order to enable this unit to bring about the transfer, to the register RCO of the central control unit, of a code order of the memory of the connecting system associated with the peripheral element concerned. This switching is effected by the dispatch, from the local control unit of this system to the central control unit, of a particular signal called the "end of phase" signal, which is transmitted through the order conductor of the said system. In order that this signal might not be likely to be confused with that which is sent to the control unit 13 by the local control unit to call for the transfer of a character, these two signals are distinguished by their duration in the described example. It will here be assumed that the transfer demand signal is a signal of very brief duration which, for this reason, is called a short signal, while the particular signal which is sent to the central control unit at the end of a phase consists of the application of voltage to the associated order conductor, and is for this reason called the long signal, the voltage of the said conductor being maintained until the instant when the central control unit sends a transfer control pulse to the local control unit under consideration. Of course, any other method of distinguishing these signals could be employed. Thus, for example, there could be employed two signals having different characteristic frequencies, or different characteristic amplitudes, or one signal consisting of the temporary application of an alternating voltage, and another signal consisting of the temporary application of an undirectional voltage.

In FIG. 1, there has been shown only one decoder-register RCO. However, the central control unit may comprise a plurality of such decoder-registers. Thus, in the case where the machine is designed to permit simultaneous operation of a series of peripheral elements on the basis of a time division, the central control unit comprises a number of decoder-registers RCO equal to the maximum number of peripheral elements which it is desired to connect to the central unit, each decoder-register being designed to receive and decode the code orders which are transmitted thereto by an associated peripheral element.

Owing to the fact that the construction of each functional connecting system is designed as a function of the type of peripheral element which can be connected thereby to the central unit, the central control unit can bring about, as a result of the decoding of a code order emanating from the said system, the main operations relative to a common operating phase, without having to take account of the type to which this peripheral element belongs. This procedure makes it possible to simplify considerably the construction of the central unit, since the control functions performed by the latter are then reduced to a minimum. Moreover, since each peripheral element is provided with a connecting system specially designed to permit the connection of this element to the central unit, it is possible to substitute for an assembly consisting of a peripheral element provided with its connecting system, another assembly consisting of a peripheral element of different type provided with its connecting system, without any necessity to modify the central control unit in any way. This substitution will merely necessitate the modification of the program instructions written in the memory 10.

On the other hand, in the machine the general principle of the arrangement of which has just been described, the user can, merely by making minor modifications in the program instructions, permutate between the peripheral elements initially connected, each element retaining its connecting system in the course of this permutation, without the operation of the machine thus being affected. Thus, the central unit has very great flexibility, while being of simplified construction and of reduced overall dimensions.

The form of construction of this machine will now be described with reference to FIGS. 2A to 2H, which show a detailed logical diagram of the control circuits of the central unit, and to FIGS. 3A to 3H, which show a detailed logical diagram of the circuits employed to control the operation of the magnetic tape units which are connected to this central unit. As already indicated in the foregoing, each peripheral element is connected to the central unit in the manner just described with reference to FIG. 1. Thus, each of the peripheral elements OT-1, OT-2, OT-3, etc., may consist of a card reader, a tape reader-puncher, a printer, etc., with the exception of the magnetic tape units. It is to be noted that the magnetic tape units are characterized by a high reading and writing rate and that consequently the transfer of the data read or to be written, between the central unit and a magnetic tape unit, takes place at a relatively high rate, of the order of several thousand characters per second. In the case where the machine is arranged to permit simultaneous operation of the series of peripheral elements on the basis of a time division, the time during which the transfer channels are employed to effect these simultaneous transfers is successively divided among all the elements concerned by these transfers, so that a transfer between the central unit and a peripheral element takes place intermittently in the course of reduced intervals of time, while another transfer between the central unit and another peripheral element may take place intermittently between these intervals. This procedure makes it possible for a transfer between the central unit and a relatively slow peripheral element, such as a card reader, for example, to be performed at the same time as another transfer between this central unit and a rapid peripheral element, such as a magnetic tape unit, for example. However, in the described example, it has been found that the performance of simultaneous transfers between the central unit and two magnetic tape units cannot be envisaged owing to the fact that these transfers, which are performed at a relatively high rate, would involve an excessive occupation of the transfer channels. This is why it has been considered preferable to connect these magnetic tape units to form a single assembly in which these units are disposed in a parallel arrangement, the assembly of these units thus constituted being connected to the transfer channels through a single input register RVDQ and a single output register EVCQ. In the example described, it will be assumed that the assembly of magnetic tape units which has been connected in accordance with this particular mode is schematically represented by any one of the members OT-1, OT-2, OT-3, etc. of FIG. 1. This assembly is naturally provided with a functional connecting system which will be described a little later. Each of the magnetic tape units may be selectively connected to the two registers RVDQ and EVCQ previously mentioned to enable a transfer to be performed between the chosen magnetic tape unit and the central unit.

FIGS. 2A to 2H, when assembled as indicated in FIG. 2, show the arrangement of the main devices of the central unit by means of which the information can be transferred between this central unit and the peripheral elements according to the invention. FIGS. 3A to 3H, when assembled as indicated in FIG. 3, show the arrangement of the assembly of magnetic tape units connected in accordance with the particular mode previously indicated, and also of the function connecting system associated with this assembly.

In these figures, the semicircles with a "+" sign in their interior represent logical "OR" circuits, the semicircles with a dot in their interior represent logical "AND" circuits, the semicircles without signs represent "buffer" circuits, and the triangles represent control circuits. These circuits are now well known and therefore will not be described.

In FIG. 3H, only one magnetic tape unit, denoted by DRM--1, has been shown, but it will be assumed that there are in fact a plurality thereof, and that only one at a time can be selected when it is concerned by a transfer, since this transfer necessarily takes place through the input register RVDQ, shown in FIG. 3D, or through the output register EVCQ, shown in FIG. 3A, and that these two registers are common to all these units. The selection of a magnetic tape unit concerned by a transfer is performed by a selection switch in two parts, denoted by CS-1 and CS-2, which is in turn controlled by a decoding and control member CCA, which is shown in FIG. 3C. The instruction register which forms part of the functional connecting system associated with the magnetic tape units is represented in FIG. 3C by a register RDR and has the object of receiving and writing a peripheral instruction which has been transmitted by the central unit, from a corresponding standby register, to control the operation of a magnetic tape unit. It will be assumed that the register RDR is a shift register of known type and that it comprises five stages RDR-1 to RDR-5, each stage being intended to contain a character of the instruction stored in this register. The stage RDR-1 of this register is intended to contain the T.O. character of a peripheral instruction. The stage RDR-2 is intended to contain a particular character of this instruction which indicates in coded form which magnetic tape unit is to be selected for the performance of the operation specified by the instruction. This character, called the "number of apparatus" character is decoded by the decoding and control member CCA, which in turn positions, as a result of the decoding of this character, the previously mentioned selecting switch CS-1, CS-2 to enable the magnetic tape unit designated by the "number of apparatus" character to be switched in order to be able to perform the operation specified by the instruction contained in the register RDR. The character contained in the stage RDR-3 of the register RDR is a character called the "type of complementary operation" character or T.O.C. character. This T.O.C. character represents in coded form a number which, in a manner which will hereinafter be indicated, makes it possible to position the magnetic tape of a unit designated by the "number of apparatus" character, this positioning consisting in so driving the said tape that the blocks of data recorded on this tape travel past the reading and writing heads, and then to stop it as soon as the number of blocks which have thus travelled past becomes equal to a numerical value defined by the T.O.C. character. It is to be noted here that, although the magnetic tape is generally utilized in accordance with a sequential mode, i.e. the data are either read from or recorded on the portion of tape travelling past the heads in the order in which they travel past, it may be desirable to find on this tape a particular block of recorded data. For example, it may be decided to read only the third block of data recorded on a tape. In this case, the operations take place in two stages. After the tape has been driven, if necessary, as far as its beginning, i.e. as far as the point at which the recording of the data has commenced on the said tape, the tape is driven in the course of a first stage to such an extent that the first two blocks of data recorded have travelled past, whereafter the tape is stopped. Thereafter, the tape is driven in the course of a second stage, and the block then travelling past the reading head is simultaneously read.

It is further to be noted that in the described example the positioning of the tape on a particular block of data is controlled by a positioning instruction in which the T.O. character stipulates that a positioning of the tape must be effected, and in which the T.O.C. character indicates the ordinal number of the block on which the tape is to be positioned. Thus, if the tape is to be positioned to permit the reading of the third block, the T.O.C. character stipulates that it is a question of the block "number three."

If, however, the instruction contained in the register RDR is a transfer control instruction, i.e. one which controls the reading of a particular block or the writing of a new block, the T.O.C. character which is contained in the stage RDR-2 is not used. However, it will be assumed that under these conditions the positioning of the tape has previously been effected, which means that this transfer control instruction has only been transferred into the register RDR, from a standby register when the tape positioning operation, controlled by a positioning instruction, has been completed.

The last two stages RDR-4 and RDR-5 of the register RDR are intended each to contain one character. When the instruction which is contained in the register RDR is a transfer control instruction, these two characters constitute a number, called the "transfer length" number, which expresses, in coded form, the length of this transfer, i.e. the number of characters which must be transferred, this transfer being effected either to the data memory 17, or from the latter, depending on whether they are read on the tape or whether they are to be recorded on the latter. It is to be noted that in the case where the instruction which is contained in the register RDR is a positioning instruction the characters which are contained in the stages RDR-4 and RDR-5 are not required. It will be recalled that all the instructions intended for a common peripheral element comprise the same number of characters. Consequently, as has just been seen, some of the characters of one instruction may not be used. In the case where, in particular, they concern the magnetic tape units, these instructions comprise a number of characters which has been made equal to five.

Each magnetic tape unit comprises, as shown in FIG. 3H, writing circuits CEK and reading circuits CLK which permit, respectively, of writing and reading characters on the magnetic tape of this unit, a forward driving device EAV and a reverse driving device EAR for driving the said tape either in the normal character writing direction or in the opposite direction, a detecting device DCS designed to detect, when the tape is driven, the special "end of block" characters which are each written on the tape at the end of a block of written data, and a synchronizing signal generating member designed to generate a pulse each time a character is read or written on the tape. When the tape is driven in the forward direction, i.e. in the normal character writing direction, the blocks of data travel past the reading and writing heads. Each time a block has passed these heads, the detecting device DCS detects the "end of block" character which has been written after the last character of this block. As a result of this detection, the device DCS sends a counting pulse through a line ICB to block-counting register RCB. The register RCB is essentially a register for the forward and backward counting of pulses which is designed to count the pulses which are sent to it by the device DCS, through the line ICB. Each time a forward counting pulse is sent by the device DCS the content of the register RCB advances by one. Thus, the register RCB permits of counting the number of blocks of data which travel past the heads. However, it will be assumed that when the tape is positioned at its beginning, the value written in the register RCB is equal to one. Under these conditions, when the first block has travelled past the heads, the register RCB receives a forward counting pulse and the value which it contains is brought to two. Likewise, this value is brought to three when the second block has travelled past the heads, and so on. Finally, the value contained in the register RCB represents quite simply the ordinal number of the block of data which is travelling past, or will travel past, the reading and writing heads when the tape is driven in the forward direction.

On the other hand, when the tape is driven in the reverse direction, the device DCS sends to the backward and forward counter RCB, through a line IDB, a backward counting pulse each time it detects the passage of an "end of block" character. This backward counting pulse, which has the effect of reducing by one the content of the register RCB, is not however sent by the device DCS until the whole block of data to which the detected "end of block" character is added has travelled completely past the reading and writing heads. In this way, the value contained in the register RCB represents the ordinal number of the block of data which has last travelled completely past the reading and writing heads, when the tape is driven in the reverse direction.

It will be appreciated from the explanations just given that if the tape driven in one direction or the other is stopped at the precise instant when the change of the value contained in the register RCB takes place, the fresh value contained in this register represents the ordinal number of the block of data which will be the first to travel past the reading and writing heads when the tape is again driven in the forward direction. However, if the tape is again driven in the reverse direction after having been stopped, the block of data which is the first to travel past the heads is that one whose ordinal number is lower by one unit than that contained in the register RCB at the instant of the stoppage. Consequently, in the described example, the forward reading of a particular block will take place by first positioning the tape in such manner as to stop it at the precise instant when the value contained in the register RCB becomes equal to that of the ordinal number of the block which it is desired to read, and by thereafter starting the drive of the tape in the forward direction, while the reading in the reverse direction of this block will take place by first positioning the tape in such manner as to stop it at the precise instant when the value contained in the register RCB becomes equal to that of the ordinal number of this block plus one and by thereafter starting the drive of the tape in the reverse direction. Consequently, the T.O.C. character which permits of positioning the tape in a positioning instruction will have to be chosen by the programmer in the preparation of the program with due regard to the direction in which the positioned tape will thereafter be driven.

The positioning of the tape is effected in the described example by first transferring the T.O.C. character of a positioning instruction written in the register RDR, this transfer taking place from the stage RDR-3 to a comparison register RPR through a gate 40 which will hereinafter be referred to, and thereafter comparing the ordinal number contained in the register RCB with the value represented by the said T.O.C. character, this comparison being effected by a comparator CPT which is shown in FIG. 3H. The comparator CPT comprises three outputs marked <, =and > respectively. In the case where the ordinal number contained in the register RCB is smaller than the T.O.C. character contained in the register RPR, only the output marked < is brought to a positive potential. In this case, this potential serves to close an electric contact KV shown in FIG. 3G. This contact KV is disposed in series with another electric contact KA which may be closed under conditions which will hereinafter be explained. When the two contacts KA and KV are closed, an electric direct current flows from a terminal marked + in FIG. 3G through contacts KA, KV and a buffer circuit L1 (FIG. 3H) and energizes the forward driving device EAV. Under these conditions, the tape is driven in the forward direction, so that the blocks of data then travel past the heads in the increasing order of their ordinal numbers. If, on the other hand, the ordinal number contained in the register RCB is higher than the T.O.C. character contained in the register RPR, only the output of the comparator marked > is brought to a positive potential. In this case, this potential serves to effect the closing of an electric contact KR shown in FIG. 3G and connected in series with the contact KA. When the two contacts KA and KR are closed, a direct current flows from the positive terminal through the contacts KA, KR and a buffer circuit L2 (FIG. 3H) and energizes the reverse driving device EAR. Under these conditions, the tape is driven in the reverse direction, so that the blocks of data then travel past the heads in the decreasing order of their ordinal numbers.

In FIG. 3G, there is shown a flip-flop BPA having two stable states, of known type. It will be recalled that this flip-flop, as also all those shown in FIGS. 2A to 2H and 3A to 3H, comprises a so-called "normal" input, a so-called "complementary" input, these inputs being indicated by arrows in the drawings, a "normal" output and a "complementary" output. When this flip-flop BPA receives a pulse through its "complementary" input, it changes to the state "O" and its "complementary" output is brought to a positive potential. The "complementary" output of the flip-flop BPA is connected on the one hand to an amplifying and control member A1 and on the other hand to one of two inputs of an "AND" circuit E1. The member A1 is designed to control the closing of the contact KA throughout the time when the "complementary" output of the flip-flop BPA remains at a positive potential. Under these conditions, as has been seen in the foregoing, the tape is driven in the forward direction or in the reverse direction until the ordinal number contained in the register RCB becomes equal to the T.O.C. character contained in the register RPR. As soon as this equality is produced, only the output marked "=" of the comparator CPT is brought to a positive potential. This output = is connected to the other input of the "AND" circuit E1. Since the two inputs of this circuit are then at a positive potential, its output which is connected to the gating input of a control circuit C1, is also at a positive potential. Under these conditions, the control circuit C1 becomes conductive and then permits a pulse sent by a pulse generator GI-1 and applied to the gated input of the circuit C1 to be transmitted by this circuit and passed more particularly to the normal input of the flip-flop BPA. Consequently, this flip-flop changes to the state "1" and its "complementary" output ceases to be brought to a positive potential. Therefore, the member A1 ceases to maintain the contact KA in the closed condition and hence the driving device by which the tape was driven is no longer energized. Under these conditions, the tape stops and remains positioned on the block on which it was desired to stop it.

The magnetic tape unit which is illustrated in FIG. 3H is provided in addition with a detector-coder EAP which has the object of detecting the technical incidents which may have occurred during the operation of this unit. These incidents may be of various natures and may consist, for example in breakage of the magnetic tape or in excessive heating of the electric circuits of this unit. The detector-coder EAP is employed in addition to signal states relative to the positioning or to the drive of the tape of this unit. Thus, the detector-coder EAP serves to signal, for example, that the tape is approaching its final end, or that it is positioned at its initial end. All these incidents and indications of state are detected by the detector-coder EAP, which transmits them, as they occur and in the form of a coded combination of signals, to a register RSI, in such manner that when the tape ceases to be driven, the coded combination which is contained in the register RSI represents a character indicating the momentary state of the magnetic tape unit. As has already been indicated in the foregoing description, this character is called the "state of apparatus" character.

It is to be noted that any character as referred to in the present description consists of a coded combination of eight binary digits. Under these conditions, it will be assumed more particularly that the T.O. character contained in the stage RD-1 is decoded by a decoding member DTO of known type, which is shown in FIG. 3C. The decoder DTO is provided with five outputs denoted by VID, PST, LAR, LAV, and ECR, and is designed to bring only one of these outputs to a positive potential. Thus, if the T.O. character contained in the stage RDR-1 specifies that the operation to be performed consists in a positioning of the tape, only the output PST is brought to a positive potential. If this character specifies that this operation consists in reading the tape in the reverse direction, only the output LAR is brought to a positive potential, while if this operation consists in reading the tape in the forward direction, the only output which is at positive potential is the output LAV. On the other hand, if the operation consists in recording fresh data on the tape, the only output which is brought to a positive potential as a result of the decoding of the corresponding T.O. character is the output ECR. Finally, if the stage RDR-1 contains no T.O. character, the only output which is brought to a positive potential is the output VID.

The order memory which forms part of the functional connecting system associated with the magnetic tape units is represented in FIG. 3F by a register MOR comprising seven stages denoted by MOR-1 to MOR-7, each stage permanently containing a different code order. The code orders which are written in each of the stages MOR-1 to MOR-7 are, respectively, the following code orders: "qualitative transfer preparation," "advance-1, output channel transfer," "advance+1, output channel transfer," "input channel transfer," "end of normal operation," "end of incident operation" and "call." As has already been indicated in the foregoing description, the "qualitative transfer preparation" code order is employed to trigger the phase F3. Likewise, the "advance+1, output channel transfer" and "advance -1, output channel transfer" code orders are employed to trigger the phase F2 when the T.O. character contained in the stage RDR-1 specifies that the operation to be performed consists in a reading of the tape, the first of these two code orders being transmitted to the central control unit only if this T.O. character is "forward reading," and the second being transmitted only if this T.O. character is "reverse reading." The "input channel transfer" code order is transmitted to the central control unit to initiate the phase F2 only if this T.O. character is "write." The "end of normal operation" code order is transmitted at the end of the phase F3 only when the magnetic tape unit has completed the operation required of it. However, it may happen that the operator who uses the machine is obliged to isolate this unit, either because an incident has occurred therein or, for example, because the tape has reached its end, in the data recording, and it must be replaced by another to permit the recording of further data. The isolation of this unit, however, can be undertaken only when the central control unit has previously been notified thereof in order that character transfers between the central unit and this magnetic tape unit may not take place as long as the latter remains unavailable owing to its isolation. Therefore, the operator will be able to proceed with this isolation only when the "end of incident operation" code order has been transmitted to the central control unit, this transfer being initiated, in a manner which will hereinafter be indicated, by the depression of a push button OF shown in FIG. 3E. Likewise, when the operator desires to return into the circuit the unit which has been isolated, he must depress a pushbutton ON shown in FIG. 3E, whereby the transfer of the "call" code order to the central control unit is initiated, as will hereinafter be seen.

It is also to be noted that the transfer control pulses which are sent by the central control unit through the corresponding conductor XREP to the connecting system associated with the magnetic tape units are applied, as shown in FIG. 3B, to the gated inputs of two control circuits C2 and C3, these circuits having their gating inputs connected, respectively, to the normal output and to the complementary output of a flip-flop BST. The transfer of a character from the register EVDQ of the central unit to the input register RVDQ is initiated, as will hereinafter be seen, by a pulse transmitted by the control circuit C2, the flip-flop BST being for this purpose in the state "1," while the transfer of a character from the output register EVCQ to the input register RVCQ of the central unit is initiated by a pulse which is transmitted by the control circuit C3, the flip-flop BST being for this purpose in the state "0. "

There is shown in FIG. 2C the decoder-register RCO which has the function of recording and decoding a code order which has been sent to it by the functional connecting system associated with a peripheral element. It is here to be noted that, although the central control unit may comprise a number of decoder-registers only one decoder-register has been shown in the accompanying figures, in order not to extend the description further. Likewise, for the sake of simplicity, it will be assumed that the data transfers referred to in the following description take place only between the central unit and the magnetic tape unit which is shown in FIG. 3H.

As is shown in FIG. 2C, the decoder-register RCO is provided with outputs denoted by SVD, SDP, STQ, SCP, SCM, SAP, SFI and SFN, and is so designed that, as a result of the decoding of the code order contained in this register, only one of these outputs is brought to a positive potential. It will be assumed that, in the case where this register RCO contains no code order, the only output which is brought to a positive potential is the output SVD, while in the case where the register RCO contains a code order, the only output which is brought to a positive potential is that designated in the following, namely:

Sdp, if this code order is "input channel transfer,"

Stq, if this code order is "qualitative transfer preparation,"

Scp, if this code order is "advance -1, output channel transfer,"

Scm, if this code order is "advance +1, output channel transfer,"

Sap, if this code order is "call,"

Sfi, if this code order is "end of incident operation,"

Sfn, if this code order is "end of normal operation."

FIG. 2C again shows eight control circuits denoted by C40 to C47, each of them being connected to one of the outputs SVD, SDP, STQ, SCP, SCM, SAP, SFI and SFN respectively. Each of these circuits is rendered conductive only when the output to which it is connected is at a positive potential. In addition, there is connected to the output SFN through an inverter I40 a control circuit C48. The circuits C40 to C46 are intended to transmit, when rendered conductive, the pulses which are sent to them by a signal-differentiating and pulse-generating member DSG (FIG. 2D). This member DSG has the function of differentiating the short signals from the long signals which, as has been indicated in the foregoing, are sent by the connecting system associated with the peripheral elements, a short signal serving to call for the transfer of a character, while a long signal is sent at the end of an operating phase. Since these two types of signals are transmitted, through the same order conductor OR, when they emanate from a common connecting system, it is essential to distinguish them. In FIG. 2D, seven order conductors OR-1 to OR-7 leading to the seven contact studs of a connecting bar BA are shown, which assumes that seven functional connecting systems are connected to the central unit. These systems are in addition connected to the said unit through seven transfer control conductors XREP-1 to XREP-7 connected to the seven contact studs of a connecting bar BD. When signals are sent through an order conductor, for example such as OR-1, they are transmitted to the member DSG through the corresponding one of seven conductors H1 to H7, i.e. H1 in the example under consideration. The member DSG is so designed that if the signal which is transmitted by H1 is a long signal, it sends a pulse to two control circuits C51 and C61 through a conductor SL-1, while if this signal is a short signal, it sends a pulse to the circuits C40 to C46 through a buffer circuit L40. Seven groups of two control circuits C51--C61, C52--C62, ... C57--C67 are connected to the member DSG through seven conductors SL-1 to SL-7, each group of circuits being connected to the member DSG through a corresponding conductor to receive a pulse which is sent by this member DSG in response to the reception of a long signal which has been transmitted through a corresponding order conductor.

Reference will now be made to FIG. 4, which shows in greater detail, by way of example, the construction of the member DSG. In a preferred form of construction, the member DSG comprises seven like elements D1 to D7, each of them being intended to receive the long and short signals which are transmitted by each of the conductors H1 to H7 respectively. FIG. 4 shows that the element D1 comprises a relay contact CB which, as long as the coil B which controls it is not energized, permits of charging a capacitor C from a direct-current source S. When a signal transmitted through the conductor H1 reaches the element D1, this signal is simultaneously applied to the gating input of a control circuit P2 and to the input of an inverter I whose output is connected to the gating input of a control circuit P1. In addition, this same signal is applied to the coil B which then changes over its contact CB and thus initiates the production of a pulse for the discharge of the capacitor C, this pulse being transmitted through a delay element R to the gated inputs of the control circuits P1 and P2. It will be appreciated that, under these conditions, if no signal has been sent to the conductor H1, the inverter I applies a unidirectional voltage to the gating input of the circuit P1. However, if a short signal H1C appears at the conductor H1, as may be seen with reference to FIGS. 4 and 5, the voltage H1CI applied by the inverter I to the gating input of the circuit P1 varies in the manner indicated in FIG. 5. The short signal H1C is applied to the gating input of the circuit P2 and the pulse H1R which appears at the output of the delay element R as a result of the discharge of the capacitor C is applied to the gated inputs of the circuits P1 and P2. There is thus obtained at the output of P1 a pulse analogous to H1R, while no pulse is set up at the output of P2 owning to the fact that the signal H1C which was applied to the gating input of P2 has ceased at the instant when the pulse H1R is applied to the gated input of P2. On the other hand, when the signal which is set up at H1 is a long signal H1L, the voltage H1LI which is applied by the inverter I to the gating input of P1 ceases, as shown in FIG. 6, from the instant when the signal H1L is set up. The signal H1L is applied to the gating input of the circuit P2 and to the coil B, which then changes over its contact CB and permits the temporary discharge of the capacitor C. The pulse H1R which is set up at the output of the delay element R as a result of this discharge is applied to the gated inputs of P1 and P2. Under these conditions, this pulse will be blocked by P1 as a result of the absence of the voltage H1LI, while it will be transmitted by P2 as a result of the presence of the signal H1L at the gating input of P2.

The dispatch of the transfer control pulses in the direction of a particular connecting system is effected through one of seven control circuits C71 to C77 shown in FIG. 2G, these circuits being connected respectively to the seven outputs K1 to K7 of a decoder-register RNB, called the connecting system number register. The register RNB is intended to contain a character called the "functional system number" character, or character NB, which serves to designate the connecting system which is associated with the peripheral element which it is desired to control for performing this operation. Thus, for example, if it is desired to control the peripheral element OT-2 with which the connecting system BLF-2 is associated, it will be necessary first of all to write in the register RNB a character NB which, after decoding, will specify that the connecting system to which the transfer control pulses will have to be sent is the connecting system number two, i.e. BLF-2. Under these conditions, of all the circuits C71 to C77 which are connected to the outputs K1 to K7 of the register RNB, only the circuit C72 will be rendered conductive. If then a transfer control pulse transmitted through a buffer circuit L41 (FIG. 2G) is simultaneously applied to the gated inputs of these seven circuits C71 to C77, this pulse will be transmitted only by the circuit C72 and sent to the connecting system BLF-2, through the conductor XREP-2.

FIGS. 2G and 2H also show that the outputs K1 to K7 of the register RNB are connected on the one hand to the respective gating inputs of the circuits C61 to C67 and on the other hand through inverters I41 to I47 to the respective gating inputs of the circuits C51 to C57. Under these conditions, when the connecting system which is designated by the character NB contained in the register RNB, for example BLF-2, sends a long signal through its order conductor (OR-2 in the example chosen), the member DSG sends a pulse to the pair of corresponding control circuits which are connected to this member (C52 and C62 in the present case). This pulse is then blocked by the corresponding one of the circuits C51 to C57 (i.e. C52 in the present instance) and is transmitted only by the other circuit of this pair (i.e. C62 in the example under consideration), and is then sent through a buffer circuit L42 to effect more particularly the positioning in the state "0" of a flip-flop BGX which will hereinafter be referred to. If, on the other hand, a long signal is sent by a connecting system other than that which is designated by the character NB, for example BLF-1, the member DSG, in response to this signal, sends a pulse to the corresponding pair of circuits which are connected to this member, i.e. C51 and C61 in the present instance. Under these conditions, this pulse is blocked by the corresponding one of the circuits C61 to C67 (i.e. C61 in the present instance) and is transmitted only by the other circuit of this pair i.e. C51 in the example under consideration, in order to effect the positioning in the state "1" of the corresponding one of a series of seven flip-flops BA-1 to BA-7, namely BA-1 in the present instance. These seven flip-flops BA-1 to BA-7 are intended to store the pulses which are transmitted through the conductors SL-1 to SL-7 and are sent consequently by the member DSG on reception of long signals, these long signals emanating from the functional connecting systems other than that which is designated by the character NB contained in the register RNB. More particularly, it will hereinafter be seen that when the operator depresses the button ON (FIG. 3E) in order to initiate the return into circuit of a peripheral element which has been isolated, the connecting system associated with this element sends a long signal to the member DSG. In response to the reception of this long signal, the latter then sends a pulse which is transmitted to the corresponding one of the conductors SL-1 to SL-7 and which produces the changeover of the corresponding flip-flop BA to the state "1." Owing to this arrangement, the operator can prepare the return into circuit of a peripheral element which has been isolated, without having, for this purpose, to interrupt the transfers of data which may take place between the central unit and the unisolated peripheral elements. However, this return into circuit only becomes effective when these transfers have been completed and it is initiated only by the central control unit after testing of the momentary state of the flip-flops BA-1 to BA-7, this test being effected in a manner which will now be briefly described.

When a peripheral element has completed the operation required of it, the central unit proceeds, in a manner which will hereinafter be indicated in detail, with the sequential exploration of the flip-flops BA-1 to BA-7. If the central unit detects, during this exploration, that one of these flip-flops is in the state "1," it sends to the connecting system associated with the corresponding peripheral element a transfer control pulse which initiates the transfer to the register RVCQ, and then to the register RCO, of the "call" code order which, as a result of the depression of the button ON hereinbefore referred to, has been written in the output register EVCQ of this element. In response to the reception of a short signal subsequently sent by this connecting system, the member DSG sends a pulse to the circuits C40 to C46. This pulse is transmitted only the control circuit C45 which is the only one to have been rendered conductive as a result of the decoding of the "call" code order contained in the register RCO. The pulse transmitted by the circuit C45 is applied more particularly to the gated inputs of seven control circuits C81 to C87 (FIG. 2F), of which the gating inputs are connected to the outputs K1 to K7 respectively of the register RNB. Under these conditions, this pulse is transmitted only by that one of the circuits C81 to C87 which is the only one which has been rendered conductive as a result of the decoding of the character NB contained in the register RNB, and it is then applied to the normal input of the corresponding one of a series of seven flip-flops BD-1 to BD-7, of which only three BD1, BD2 and BD7, are shown in FIG. 2E, for obvious reasons of simplicity. Consequently, that one of these seven flip-flops which receives a pulse at its normal input changes to the state "1."

If now the operator desires to proceed with the isolation of a peripheral element, he must, as seen in the foregoing, depress the push button OF of the connecting system associated with this element, and, as will hereinafter be seen, this initiates the transfer of the "end of incident operation" code order to the output register EVCQ of this element. Simultaneously, a long signal is sent to the member DSG, which in turn sends a pulse which changes over the corresponding flip-flop BA to the state "1." In the sequential exploration of the flip-flops BA-1 to BA-7, the positioning of this flip-flop in the state "1" will be detected and consequently a transfer control pulse will be sent to the connecting system associated with the corresponding peripheral element in order to bring about the transfer of the "end of incident operation" code order to the register RVCQ and then to the register RCO. In response to the reception of a short signal subsequently sent by this connecting system, the member DSG sends a pulse to the circuits C40 to C46. Under these conditions, this pulse is transmitted only by the control circuit C46, which is the only one to have been rendered conductive as a result of the decoding of the "end of incident operation" code order. The pulse transmitted by the circuit C46 is applied more particularly to the gated inputs of seven control circuits C91 to C97 (FIG. 2F), of which the gating inputs are connected to the outputs K1 to K7 respectively of the register RNB. Consequently, this pulse is transmitted only by that one of the circuits C91 to C97 which corresponds to the peripheral element which it is desired to isolate, and it is then applied to the complementary input of the corresponding flip-flop BD, which thus changes to the state "0."

Finally, each of the flip-flops BD1 to BD7 indicates whether the corresponding peripheral element is available or not. When one of these flip-flops is in the state "1," this means that the corresponding peripheral element is available. On the other hand, if it is in the state "0," this means that this element is unavailable.

It is to be indicated here that the register RCO, the member DSG, the register RNB, the flip-flop BGX, the flip-flops BA-1 to BA-7, the flip-flops BD-1 to BD-7 and the various control circuits which have been mentioned in the foregoing with reference to FIGS. 2A to 2H form part of the central control unit diagrammatically illustrated in FIG. 1. This central control unit comprises in addition a main control unit UCP which is shown in FIG. 2A, and an auxiliary control unit UCA which is shown in FIG. 2E. The main control unit UCP is intended to supply the pulses necessary for controlling the various elementary operations concerning the selection and extraction of the program instructions contained in the memory 10, the selection being effected under the control of an address contained in the selection register 14. However, it must be recalled here that there is associated with each of the peripheral instructions contained in the memory 10 a coded indication which specifies the number of the peripheral element for which this instruction is intended, i.e. again that of the functional connecting system associated with this element. This coded indication consequently represents the character NB which has just been referred to. With each of the instructions contained in the memory 10, there is associated in addition an address which indicates the location in which the character forming the subject of the processing specified by the instruction is, or will have to be written in the data memory 17. Therefore, the intermediate register 12 is shown in FIG. 2A in three parts denoted by 12A, 12B and 12C, each of these parts being intended to contain, respectively, the address, the character NB and the instruction which have been simultaneously extracted from the memory 10. The character NB contained in the part 12B is also transmitted to the writer-decoder 16 to enable it to control the member 15 whose object is to establish the path, either to the register RITB or to one of seven standby registers RI-1 to RI-7, of which only two, RI-1 and RI-2, are shown in FIG. 2A. It will be assumed that, in order to permit the sequential selection of the instructions contained in the memory 10, and of the addresses and characters NB associated therewith, the address contained in the selection register 14 may be modified in known manner by an address-modifying member 29 subject to the control of the main control unit UCP.

On the other hand, since each of the standby registers RI-1 to RI-7 can contain only one instruction at a time, as also the address and the character NB associated with this instruction, means are provided to prevent an instruction extracted from the memory 10 from being transmitted to a standby register or to the register RITB if this register already contains another instruction. These means are known, but in the present description they have been neither described nor shown since they do not form part of the invention. It is to be noted in addition that, although the machine may be arranged to permit the peripheral instructions contained in the standby registers RI-1 to RI-7 to be simultaneously transmitted to the peripheral elements for which they are intended, these transfers being effected on the basis of a time division, it has been considered preferable here not to describe such an arrangement or to illustrate it in the accompanying drawings, in order not further to extend the description. For the sake of simplicity, it will be assumed that each of the instructions contained in the registers RI-1 to RI-7 is first transferred into a connecting register RLE before being sent to the peripheral element for which it is intended. As is shown in FIG. 2A, this register RLE comprises three parts denoted by RLE-1, RLE-2 and RLE-3 respectively. The part RLE-3 is intended to contain temporarily the instruction which is to be sent to a peripheral element in order to control an operation. Thus, as has been indicated in the foregoing, this instruction comprises at most five characters and consequently the capacity of the part RLE-3 of the register RLE is five characters. The part RLE-1 of this register is intended temporarily to contain the address associated with this instruction, i.e. the address to which the first character which will be transferred in the course of the phase F2 is or at which it will have to be written in the data store 17. In order that this transfer may take place, it will therefore be necessary for this address to be transferred into the selection register 19 shown in FIG. 2B before this transfer is initiated. Finally, the part RLE-2 of the register RLE is intended temporarily to contain the character NB associated with the instruction contained in the part RLE-3, this character NB designating the connecting system to which the transfer control pulses will have to be sent in order to perform the operation specified by this instruction. In addition, the character NB contained in the part RLE-2 is applied, as shown in FIGS. 2A and 2E, through a line CNB to the auxiliary control unit UCA to enable this unit to know to which functional connecting system the instruction contained in the part RLE-3 will have to be sent. Obviously, this transfer must take place only if the peripheral element associated with this connecting system is available. Therefore, all the outputs of the flip-flops BD-1 to BD-7 7 are permanently connected as shown in FIG. 2E, to the unit UCA to inform it of the state of availability of the peripheral elements. If the peripheral element with which there is associated the connecting system which is to receive the instruction contained in the part RLE-3 is unavailable, the transfer of this instruction to the said system is delayed until this element again becomes available. Under these conditions, the instruction contained in the part RLE-3, as also the address, and the character NB associated therewith are sent back to the standby register which initially contained them, and another instruction, contained in another standby register, is transferred into the register RLE at the same time as the address and the character NB which are associated therewith. The dispatch of an instruction and of the associated address and character NB to the standby register which initially contained them takes place through one of a series of gates T1 to T7, of which only two, T1 and T2, are shown in FIG. 2A, these gates being subject to the control of the auxiliary control unit UCA.

On the other hand, if the connecting system which is to receive the instruction contained in the part RLE-3 is associated with an available peripheral element, the characters of this instruction are transferred successively to the said connecting system. For this purpose, there is combined with the part RLE-3 a step-by-step selection switch CSK which advances step-by-step under the control of pulses transmitted from the member DSG through the control circuit C40 and a conductor CIP, and which successively selects the characters contained in the part RLE-3, each of the selected characters being successively sent to the register EVDQ through a line LTK.

It is further to be noted that, in order to permit the dispatch of transfer control pulses to the connecting system associated with the peripheral element which is designated to perform the work specified by the instruction contained in the part RLE-3, the character NB contained in the part RLE-2 is previously sent into the register RNB through a gate 22 subject to the control of the unit UCA. It is also to be noted that the address emanating from the part RLE-1 and contained in the selection register 19 may be modified to permit the selection of another location in the memory 17. In the described example, it will be assumed that this modification is performed either by an address advancer PAD (FIG. 2B) which is designed to increase this address by one unit each time it receives a pulse transmitted by a buffer circuit L43 or by an address reducer MAD which is designed to decrease this address by one unit each time it receives a pulse transmitted by a delay element R40.

Without entering further into detail, it will be indicated that the permanent date register RPU which is shown in FIG. 2C comprises in fact two parts RPU-1 and RPU-2, each of which permanently contains a particular coded character. The part RPU-2 of this register contains the response-code character referred to earlier in the beginning of the description, which it will be recalled is transmitted to a connecting system in response to the reception of a code order sent by the said system, in order to indicate thereto that the central unit is available and that consequently a transfer may be initiated along the transfer channels. The part RPU-1 of the register RPU contains a special coded character, called the "operating" character, or character MAT, which is transmitted to a connecting system associated with an inoperative peripheral element in order to enable this system to cooperate with the central control unit so as to bring about the transfer of an instruction to the instruction register of this system, and thus to enable this peripheral element to perform the operation specified by this instruction.

The operation of the machine just described will now be explained with reference to FIGS. 2A to 2H and 3A to 3H, by means of a number of examples of use applied to the case of a magnetic tape unit connected in the manner previously indicated, the functional connecting system associated with this unit being assumed to be connected to the central control unit through the conductor XREP-1 and the conductor OR-1.

It will be assumed that, at the outset, i.e. at the application of voltage, the machine is in the following state:

1. In the central control unit, the flip-flops BA-1 to BA-7 (FIG. 2H) and a flip-flop BET (FIG. 2B) are in the state "0." Accordingly, seven control circuits C111 to C117 (FIG. 2H) which are connected respectively to the complementary outputs of the flip-flops BA-1 to BA-7 are conductive and seven control circuits C101 to C107 which are connected respectively to the normal outputs of these flip-flops are nonconductive. Likewise, two control circuits C49 and C50 (FIG. 2B) connected to the normal output of the flip-flop BET are nonconductive. The flip-flop BGX (FIG. 2G) is in the state "1" as also is a flip-flop BMA (FIG. 2F). A control circuit C58 connected to the complementary output of the flip-flop BGX is therefore nonconductive. Two control circuits C59 and C60 connected respectively to the normal and complementary outputs of the flip-flop BMA are rendered conductive and nonconductive respectively under the same conditions. The register RCO (FIG. 2C) contains no code order, so that the output SVD is at a positive potential. Consequently, the control circuit C40 is conductive, as also is the control circuit C48 which is connected to the output of the inverter I40.

2. In the local control unit of the connecting system associated with the magnetic tape units, the flip-flop BST is in the state "1," so that the circuit C2 is conductive. Two flip-flops BOC and BOL (FIG. 3B) are in the state "0." Consequently, a control circuit C4 which is connected to the normal output of the flip-flop BOL is nonconductive, as also is a circuit C5 connected to the normal output of the flip-flop BOC. As will hereinafter be seen, the flip-flop BOC may be changed over to the state "1" in order to bring about the dispatch of a short signal to the member DSG of the central unit, through the conductor OR-1. Likewise, the flip-flop BOL may be changed over to the state "1" to bring about the dispatch of a long signal to the said member DSG through the conductor OR-1. FIG. 3C shows a flip-flop BFF which is in the state "0" and renders nonconductive a control circuit C6 connected to its normal output. In FIG. 3D, two flip-flops BMT and BRP are in the state "0." Consequently, a control circuit C7 which is connected to the normal output of the flip-flop BMT through an AND circuit E2 is nonconductive. FIG. 3D further shows a decoder DKR provided with three outputs X1, X2, X3 which is associated with the register RVDQ and which is designed to supply a positive voltage only at its output X1 in the case where the register RVDQ contains the character MAT referred to in the foregoing. On the other hand, if this character is the code-response character, the output of the decoder DKR which is brought to a positive potential is the output X3. Finally, if the register RVDQ is empty, the output which is at a positive voltage is the output XZ. An AND circuit E21 having two inputs has one of its inputs connected to the output X2 and the other input connected to the complementary output of the flip-flop BMT. Since the flip-flop BMT is initially in the state "0," a positive voltage is set up at the output of the circuit E21. A control circuit C27 is connected by its gating input to the output X1. A control circuit C28 is connected by its gating input to the output X3. Since the outputs X1 and X3 are initially not brought to a positive potential, these control circuits C27 and C28 are not conductive. There is also connected to the output X3 by one of its two inputs an AND circuit E3, to the output of which there is connected the gating input of a control circuit C8 which is initially not conductive, since the output X3 is not at a positive potential and consequently that of the circuit E3 is not at a positive potential. In FIG. 3G, the flip-flop BPA is in the state "1," while two flip-flops BES and BTQ are in the state "0." Consequently, a control circuit C9 connected to the normal output of the flip-flop BES is not conductive, while two circuits C10 (FIG. 3G) and C26 (FIG. 3C) which are connected to the complementary output of this flip-flop are conductive. A control circuit C11 connected to the normal output of the flip-flop BTQ through an AND circuit E4 is nonconductive. The circuit E2 (FIG. 3D), one of the three inputs of which is connected to the normal output of the flip-flop BMT, is connected by one of its other two inputs to the complementary output of the flip-flop BTQ, and by its third input to the output VID of the decoder DTO. In FIG. 3H, two flip-flops BAR and BAV are in the state "0." When the flip-flop BAV is in the state "1." the positive voltage which is set up at its normal output is applied to the driving device EAV in order that the tape may be driven in the forward direction. On the other hand, when the flip-flop BAR is in the state "1," the positive voltage which is set up at its normal output is applied to the driving device EAR in order that the tape may be driven in the reverse direction. The complementary outputs of the flip-flops BAV and BAR are connected on the one hand to two inputs of an AND circuit E14 (FIG. 3D), which will hereinafter be referred to, and on the other hand to two inputs of an AND circuit E19 (FIG. 3C) having three inputs, the third input of this circuit E19 being connected to the complementary output of the flip-flop BFF. Since the flip-flops BAV, BAR and BFF are all in the state "0" at the outset, and consequently their complementary outputs are all at a positive voltage, the output of the circuit E19 is brought to a positive potential, whereby a control circuit C29 (FIG. 3B) is rendered conductive, the gating input of which is connected to the output of the circuit E19. In addition, one of the inputs of the circuit E14 is connected to the output X3 and consequently no positive voltage is set up at its output. Under these conditions, a control circuit C23 whose gating input is connected to the output of the circuit E14 is nonconductive. It is also to be noted that at the outset the instruction register RDR of the functional connecting system is empty. Consequently, the output VID of the decoder DTO is at a positive voltage. This voltage is applied on the one hand to the input of an inverter I1 which supplies no positive voltage at its output under these conditions, and on the other hand to one of two inputs of an AND circuit E5 (FIG. 3B). The other input of this circuit E5 is connected to the complementary output of the flip-flop BOL and is consequently initially at a positive potential. A positive voltage is therefore set up at the output of the circuit E5, whereby a control circuit C12 is rendered conductive. Likewise, no positive voltage is set up at the output of an AND circuit E6 (FIG. 3C), one of the two inputs of which is connected to the output of the inverter I1, and a control circuit C13 is thereby rendered nonconductive. FIG. 3C shows four AND circuits E7 to E10, one of the two inputs of which is connected respectively to the outputs PST, LAR, LAV and ECR of the decoder DTO. At the outset, no positive voltage is set up at the output of each of these circuits, whereby there are rendered nonconductive four control circuits C17 to C20 (FIG. 3F) which are connected to the outputs of the circuits E7 to E10 respectively. Likewise, no positive voltage is set up at the output of an AND circuit E11 (FIG. 3G), one of the two inputs of which is connected to the output PST, while the other is connected to the normal output of the flip-flop BRP, whereby a circuit C14 is rendered nonconductive. In FIG. 3D, two AND circuits E12 and E13 each have one of their inputs connected to the normal output of the flip-flop BRP. These two circuits E12 and E13 have their outputs connected to one of two control circuits C21 and C22 respectively. Owing to the fact that the flip-flop BRP is in the state "0," no positive voltage is set up at the output of the circuits E12 and E13, whereby the circuits C21 and C22 are rendered nonconductive. FIG. 3F shows a two-input AND circuit E15, one input of which is connected to the output of the circuit E21 (FIG. 3D), while the other input is connected to the output VID of the decoder DTO. Since these two outputs are initially at positive potential, so also is the output of the circuit E15. In FIG. 3E, two flip-flops BPD and BPC are initially in the state "0." When the operator desires to isolate all the magnetic tape units associated with the functional connecting system illustrated in FIGS. 3A to 3H, he depresses the button OF. Under these conditions, a positive voltage is applied from a terminal marked "+" in FIG. 3E to the input of a differentiating amplifier AD-1 which is designed to supply at its output a single pulse each time its input is brought to a positive potential. This pulse is applied to the normal input of the flip-flop BPD, which then changes to the state "1." Consequently, a positive voltage is set up at the normal output of this flip-flop and is applied to one of the two inputs of an AND circuit E16. The other input of this circuit E16 is connected to the output of the circuit E15. Since the output of the circuit E15 is at a positive voltage at the outset and the depression of the button OF results in the changeover of the flip-flop BPD to the state "1," a positive voltage is set up at the output of the circuit E16, whereby a control circuit C24 is rendered conductive. A pulse emitted by a pulse generator GI-2 and applied to the gated input of the circuit C24 is then transmitted by this circuit and applied on the one hand to the complementary input of the flip-flop BPD, which then returns to the state "0," and on the other hand to the normal input of the flip-flop BPC, which then changes to the state "1." The pulse transmitted by the circuit C24 is also sent more particularly to a gate 41 connected to the output of the stage MOR-6 of the order memory. Consequently, the "end of incident operation" code permanently contained in this stage is transmitted through the gate 41 to the register EVCQ, this transfer taking place, however, without return-to-zero of the stage MOR-6. On the other hand, the pulse transmitted by the circuit C24 has the effect of bringing the corresponding flip-flop BA to the state "1" (FIG. 2H), as will hereinafter be seen. In addition, owing to the changeover to the state "1" of the flip-flop BPC, a positive voltage is now set up at the normal output of this flip-flop, whereby a control circuit C25 is rendered conductive.

From this instant, the operator can initiate the return into circuit of all the magnetic tape units by depressing the button On. Depression of the button On produces the application of a positive voltage from the terminal marked "+" to the input of a differentiating amplifier AD-2, similar to the differentiating amplifier AD-1, which sends a pulse to the control circuit C25. Owing to the fact that the circuit C25 is now conductive, this pulse is transmitted by this circuit and applied more particularly on the one hand to the complementary input of the flip-flop BPC, which then returns to the state "0," and on the other hand to a gate 42 connected to the output of the stage MOR-7 of the order memory. Consequently, the "call" code order contained in this stage is transmitted through the gate 42 to the register EVCQ, this transfer taking a place without return-to-zero of the stage MOR-7. As a result of the changeover to the stage "0" of the flip-flop BPC, the circuit C25 is again rendered nonconductive. On the other hand, the pulse transmitted by the circuit C25 has the effect of bringing the corresponding flip-flop BA (FIG. 2H) to the state "1," as will hereinafter be seen. Finally, the pulse transmitted by the circuit C25 is applied to the normal input of a flip-flop BRC (FIG. 3A) which was initially in the state "0," and which then changes to the state "1" and renders conductive a control circuit C35.

When the flip-flop BPC is in the state "0," a positive voltage is set up at its complementary output, whereby a control circuit C30 (FIG. 3F) is rendered conductive. The changeover of this flip-flop to the state "1" as a result of the depression of the button OF and the appearance of a positive voltage at the output of the circuit E15 has the effect of rendering this circuit C30 nonconductive.

It is further to be noted that if the stage RDR-1 of the instruction register contains a T.O. character, or if the flip-flop BMT is at "1," or again if the register RVDQ contains a character, the output of the circuit E15 ceases to be a positive voltage. In this case, depression of the button OF again brings the flip-flop BPD to "1," but the control circuit C24 will not be rendered conductive until the state of the stage RDR-1, of the flip-flop BMT and of the register RVDQ enables a positive voltage to be set up at the output of the circuit E15. This procedure prevents the operator from starting the transfer of the "end of incident operation" code order to the register EVCQ as the magnetic tape unit has not completed the operation defined by the instruction present in the instruction register.

The machine being initially in the state just indicated, two examples of application will now be given in order that the operation of the whole arrangement may be more readily understood, the first example relating to the positioning of the tape unit which is shown in FIG. 3H, and the second example relating to the reading of data recorded on this tape. In addition, it will be assumed that the operator has not depressed the button OF.

POSITIONING OF THE TAPE

The operation of the machine is started by actuation of a pushbutton MM shown in FIG. 2E. When the operator depresses this button a positive voltage is applied from a terminal marked "+" in FIG. 2E to the input of a differentiating amplifier AD-3, similar to the differentiating amplifiers AD-1 and AD-2, which then sends a pulse in various directions through conductors which will hereinafter be referred to. This pulse which is transmitted through a conductor MM-1 (FIG. 2E) is applied to the normal input of the flip-flops BD-1 to BD-7, which then change to the state "1" or remain therein if they were already in this state. Transmitted through a conductor MM-2 (FIGS. 2E and 2F), this pulse is applied on the one hand through a buffer L44 to the normal input of the flip-flop BMA, which changes to the state "1" or remains therein if it was already in this state, and on the other hand through a buffer L45 (FIG. 2H) to the gated inputs of the circuits C101 and C111, thus making it possible for the momentary state of the flip-flops BA-1 to BA-7 to be tested. Since the circuits C111 to C117 are initially conductive and remain so as long as the operator has not depressed any of the buttons OF of the functional connecting systems, as stated in the foregoing, this pulse is successively transmitted by the circuits C111 to C117 and is applied to the gated inputs of the circuits C59 and C60. Owing to the fact that the flip-flop BMA is in the state "1," this pulse is transmitted by the circuit C59 and finally received by the control unit UCA, which is thus informed that all the flip-flops BA-1 to BA-7 are in the state "0" and that consequently all the peripheral elements are available. It will hereinafter be seen what would happen if the operator had initially depressed any one of the buttons OF of the functional connecting systems. FIGS. 2E and 2A also show that the pulse which is set up at the output of the differentiating amplifier AD-3 is in addition transmitted through a buffer L46 to the register RLE, to the selection switch CSK and to the main control unit UCP. Under the effect of this pulse, the register RLE is returned to zero and the selection switch CSK is brought into the initial position to enable it to select, when it subsequently receives a pulse transmitted through the conductor CIP, the T.O. character of an instruction registered in the part RLE-3 of the register RLE, after the return-to-zero of the latter. Finally, the pulse which is transmitted to the control unit UCP through the buffer L46 constitutes a signal which indicates to this unit UCP that the control unit UCA is ready to deal with any instruction which will be transferred from a standby register to the register RLE. Without entering into details, it will simply be recalled that the sequential extraction of the instructions contained in the memory 10 is controlled by the control unit UCP, that these instructions are successively extracted in accordance with the processing possibilities of the machine and that they are sent, as has been seen in the foregoing, to one of the registers RI-1 to RI-7 and RITB. Let it be assumed in the present case that the operation defined by the first of these instructions concerns the positioning of the magnetic tape of the tape unit illustrated in FIG. 3H, this unit being, for example, the third of the set of tape units which are connected to the central unit through the connector system BLF-1. Under these conditions, this instruction, after having been extracted from the memory 10, is sent into the standby register RI-1 as also are the address and the character NB associated therewith. In response to the reception of the pulse transmitted through the buffer L46, the control unit UCP sends to the control unit UCA, through a line CR, a coded indication specifying that the peripheral instruction which is to be carried out is that which is contained in the standby register RI-1. In response to this coded indication, the control unit UCA sends a pulse through a conductor CIS-1 on the one hand to the gate S1, whereby the transfer of the instruction contained in the register RI-1 to the register RLE is brought about, and on the other hand to the control unit UCP in order to inform it that this transfer has been performed. It will be assumed that, as a result of this transfer, the part RLE-1 has remained at zero, the part RLE-2 contains a character NB indicating that the connecting system to which the instruction will have to be sent is the system BLF-1, and the part RLE-3 contains the said instruction, this instruction comprising the following five characters:

first character: T.O. "positioning,"

second character: number of apparatus "three"

third character: T.O.C. "two" (stipulating that the tape must be positioned on the second block of data)

fourth character: no significance here

fifth character: no significance.

Since the character NB contained in the part RLE-2 is now applied to the control unit UCA through the line CNB, the unit UCA is now informed that the instruction contained in the part RLE-3 must be transferred to the connecting system BLF-1, provided however that all the tape units associated therewith are available. As indicated in the foregoing, this availability is known from the state of the flip-flop BD-1, the outputs of which are connected to the control unit UCA. Since, in the present case, the flip-flop BD-1 is in the state "1," all the magnetic tape units are therefore available. Under these conditions, the control unit UCA sends a pulse to the gate 22 (FIG. 2E), whereby the transfer of the character NB contained in the part RLE-2 to the register RNB (FIG. 2G) is triggered. Since this character NB specifies in the example under consideration that the connecting system to which the instruction contained in the part RLE-3 must be sent is the connecting system BLF-1, the output of the register RNB, which is the only one to have been brought to positive potential, is the output K1. Consequently, of the seven control circuits C71 to C77, only the circuit C71 is rendered conductive. However, it may happen that, between the instant when the last pulse transmitted by the buffer L45 has been applied to the gated inputs of the circuits C101 and C111, and the instant when the character NB is transferred into the register RNB, the operator has depressed the button OF of the connecting system BLF-1 thus rendering all the magnetic tape units unavailable. Under these conditions, the connecting system BLF-1 cannot receive the instruction which is contained in the part RLE-3. Although this case can only arise in exceptional circumstances, the probability of its existence means that it is necessary for the control unit UCA to know again the state in which the flip-flops BA-1 to BA-7 are at the instant when it is to control the transfer of the instruction contained in the part RLE-3. Therefore, as is shown in FIGS. 3E, 2F, 2G and 2H, the complementary outputs of the flip-flops BA-1 to BA-7 are directly connected to the control unit UCA. If the connecting system for which this instruction is intended is in the state to receive it, or in other words if the corresponding flip-flop BA (BA-1 in the present case) is in the state "0," the complementary output of the said flip-flop is brought to a positive voltage. The control unit UCA is so designed, that if this condition is satisfied, it sends a pulse to a conductor IDT just after having brought about the transfer of the character NB to the register RNB, this pulse producing effects which will hereinafter be discussed. On the other hand, if the output of the flip-flop BA under consideration is no longer at a positive voltage, the control unit UCA sends a pulse to a buffer L47 (FIG. 2F) through a conductor ITB just after having brought about the transfer of the character NB to the register RNB. This pulse is then successively transmitted by the buffers L47 and L45 and applied to the gated inputs of the circuits C101 and C111 to test again the state of the flip-flops BA-1 to BA-7. This case will be examined in detail in the following.

Referring now again to the case where the control unit UCA has sent a pulse along the conductor IDT, this pulse is on the one hand applied to the normal input of the flip-flop BET, which then changes to the state "1," thus rendering conductive the circuits C49 and C50, and on the other hand transmitted to a gate 23 (FIG. 2C), which triggers the transfer, to the output register EVDQ, of the "operating" or "MAT" character which is written in the part RPU-1 of the permanent data register. In addition, the pulse sent along the conductor IDT is applied to one of the inputs of a buffer L48 (FIG. 2G), which transmits it to a delay element R41. The delay of the delay element R41 is made such that when a pulse is sent by the control unit UCA along the conductor IDT, a delayed pulse appears at the output of the delay element R41 only when the transfer of the "MAT" character to the register EVDQ has been completed. This delayed pulse, which is thereafter transmitted by the buffer L41, constitutes a transfer control pulse. It is then applied to the gated inputs of the circuits C71 to C77 and transmitted only by the circuit C71 and sent to the conductor XREP-1. In addition, after having passed through the circuit C71, it is applied to the complementary input of the flip-flop BA-1, which remains at "0," since it was already in this state.

The pulse sent along the conductor XREP-1 is then applied to the gated inputs of the circuits C2 and C3 (FIG. 3B). Since, as has been stated in the foregoing, only the circuit C2 is conductive, this pulse is transmitted by the circuit C2 and applied on the one hand to the gated input of the circuit C26, which transmits it, since it is conductive, and on the other hand to the input of a delay element R1. The pulse transmitted by the circuit C26 is applied to a gate 44 (FIG. 3D), which brings about the transfer of the "MAT" character from the register EVDQ to the register RVDQ. Under these conditions, the output X1 of the decoder DKR is brought to a positive potential, thus rendering conductive the control circuit C27. The delay of the delay element R1 is such that when a pulse transmitted by the circuit C2 is applied to its input and in addition triggers the transfer of a character from the register EVDQ to the register RVDQ, a delayed pulse is set up at its output only when this transfer has been completed. This pulse is sent on the one hand through a buffer L3 (FIG. 3C) to the gated input of the circuit C6, which blocks it owing to the fact that it is not conductive, and on the other hand to the gated inputs of the circuits C9, C10 (FIG. 3G), C23, C27, C28, C7, C8 (FIG. 3D) and to the inputs of three delay elements R12, R7 (FIG. 3G) and R2 (FIG. 3D), which will hereinafter be referred to. Of all these circuits, only the circuits C10 and C27 are conductive, for reasons which have already been explained in detail. Connected to the output of the delay element R12 is the circuit C11, which is nonconductive. Connected to the output of the delay element R7 is the circuit C14, which is nonconductive. Finally, there are connected to the output of the delay element R2 the circuits C21 and C22, which are nonconductive. The pulse transmitted by the circuit C27 is simultaneously applied to the normal input of the flip-flop BMT, which changes to the state "1," and through a buffer L12 to the complementary input of the flip-flop BRP, which remains at "0." Owing to the fact that the output VID of the decoder DTO, the complementary output of the flip-flop BTQ and the normal output of the flip-flop BMT are now all at a positive voltage, the output of the circuit E2 is therefore brought to a positive potential and thus renders the circuit C7 conductive. However, the pulse which was applied to the input of this circuit C7 cannot be transmitted by this circuit owing to the fact that, when this change takes place, the said pulse has already disappeared. The pulse transmitted by the circuit C10 (FIG. 3G) is applied to the input of a delay element R3 (FIG. 3F). Finally, the delayed pulses which are set up at the outputs of the delay elements R2, R7 and R12 and which are applied to the gated inputs of the circuits C21, C22, C14 and C11 are blocked by these circuits owing to the fact that they are not conductive. Thereafter, a delayed pulse is set up at the output of the delay element R3 and is applied to the gated inputs of the circuits C17 to C20 (FIG. 3F), C12 and C13 (FIG. 3B). This pulse is blocked by the circuits C17 to C20 and C13, which are nonconductive, and is transmitted only by the circuit C12. The pulse transmitted by the circuit C12 is applied through a buffer L4 to the normal input of the flip-flop BOC, which changes to the state "1." Under these conditions, the control circuit C5 becomes conductive. A pulse emitted by a pulse generator GI-3 and applied to the gated input of the circuit C5 is then transmitted by this circuit and passed, through two buffers L5 and L6, to the order conductor OR-1, on the one hand, and applied to the complementary input of the flip-flop BOC on the other hand, this flip-flop returning to "0" and thus again rendering the circuit C5 nonconductive.

It is also to be noted that, from the instant when the register RVDQ has received the "MAT" character, the output of the circuit E21 ceases to be at a positive voltage, since the output X2 is no longer brought to a positive potential. As already explained in the foregoing, the circuit C24 (FIG. 3E) can no longer be rendered conductive from this instant, even if the operator brings about the changeover to "1" of the respective flip-flop BPD by depressing the button OF. Henceforth, even if the register RVDQ is returned to zero, the control circuit C24 can no longer be rendered conductive, since as a result of the changeover of the flip-flop BMT to the state "1," no positive voltage can be set up at the output of the circuit E21.

The pulse which has been sent to the conductor OR-1 constitutes the short signal referred to in the foregoing. In response to this signal, the member DSG (FIG. 2D) sends through the buffer L40 a pulse which, when applied to the gated inputs of the circuits C40 to C46, is transmitted only by the circuit C40. FIGS. 2A, 2B and 2C show that the pulse transmitted by the circuit C40 is sent on the one hand to the selection switch CSK, thus causing the "positioning" T.O. character of the instruction contained in the part RLE-3 to be sent to the register EVDQ, and causing this switch to advance by one step, and on the other hand to the circuit C49 which is conductive. The pulse transmitted by the circuit C49 is sent to the complementary input of the flip-flop BET through a buffer L49, and simultaneously to the main control unit UCP and to a gate 24. Under these conditions, the flip-flop BET returns to "0" and renders nonconductive the circuits C49 and C50. The pulse which is sent to the control unit UCP constitutes a signal intended to inform this control unit that the instruction which is contained in the part RLE-3 will not be sent back to the standby register from which it was transferred to the part RLE-3 and that consequently this standby register can now receive any other peripheral instruction which is intended therefor, this instruction being extracted from the memory 10 and transmitted to the said register under the control of the control unit UCP. Finally, the pulse which is applied to the gate 24 triggers the transfer of the content of the part RLE-1 to the selection register 19. Since in the present case this part RLE-1 is at zero, the selection register 19 contains no address as a result of this transfer, and therefore remains at zero. Finally, FIGS. 2C and 2G show that the pulse transmitted by the circuit C40 is in addition sent to the delay element R41 through the buffer L48. The delayed pulse which is set up at the output of this delay element is transmitted, as before, by the buffer L41 and the circuit C71 and sent to the conductor XREP-1.

Without entering further into the details, it will be indicated that this pulse is applied to the gated inputs of the circuits C2 and C3 and transmitted by the circuit C2. It is then applied on the one hand to the input of the delay element R1 and on the other hand to the gate 44 through the circuit C26, thereby bringing about the transfer of the "positioning" T.O. character from the register EVDQ to the register RVDQ. Since none of the gates of the decoder DKR is now brought to a positive potential, the circuits C27 and C28 are nonconductive. Under these conditions, the delayed pulse which is set up at the output of the delay element R1 is transmitted by the circuits C10 and C7, blocked by the circuits C6, C9, C23, C27, C28 and C8 and applied to the inputs of the delay elements R12, R7 and R2. It is transmitted by C10 and applied to the input of the delay element R3. After transmission by C7, it is applied to a gate 45 (FIG. 3D) and brings about the transfer of the "positioning" T.O. character contained in the register RVDQ to the stage RDR-5 of the instruction register. The delayed pulses which are set up at the outputs of the delay elements R12, R7 and R2 are sent to the circuits C11, C14, C21 and C22, which block them owing to the fact that they are nonconductive. Thereafter, the delayed pulse which is set up at the output of the delayed element R3 is transmitted by the circuit C12 and blocked by the circuits C17 to C20 and C13. The pulse transmitted by the circuit C12 produces the changeover of the flip-flop BOC to "1," so that, as before the generator GI-3 sends a pulse which on the one hand brings about the return of the flip-flop BOC to "0" and on the other hand is sent to the conductor OR-1, where it again constitutes a short signal.

In response to the reception of this short signal, the member DSG sends through the buffer L40 a pulse which is transmitted by the circuit C40 and blocked by the circuits C41 to C46. The pulse transmitted by the circuit C40 is sent to the selection switch CSK, thus causing the transfer, to the register EVDQ, of the second character of the instruction contained in the part RLE-3, i.e. of the number of apparatus character "three." In addition, the pulse transmitted by the circuit C40 is sent on the one hand to the circuit C49, which blocks it, and on the other hand to the delay element R41, through the buffer L48. The delayed pulse which is set up at the output of this delay element is transmitted, as before, by the buffer L41 and the circuit C71 and sent to the conductor XREP-1.

As before, this pulse is transmitted by the circuit C2 and sent on the one hand to the delay element R1 and on the other hand to the gate 44 through the circuit C26, thus producing the transfer of the number of apparatus character "three" from the register EVDQ to the register RVDQ. Thereafter, the delayed pulse which is set up at the output of R1 is transmitted by the circuits C10 and C7, blocked by the circuits C6, C9, C23, C27, C28 and C8 and applied to the inputs of R12, R7 and R2. After transmission by C10, it is applied to the input of R3, and after transmission by C7 it is applied to the gate 45, bringing about the transfer of the number of apparatus character "three" contained in the register RVDQ to the stage RDR-5 of the instruction register. At the same time, the "positioning" T.O. character is transferred, by shifting, from the stage RDR-5 to the stage RDR-4. Finally, the delayed pulses which are set up at the outputs of R12, R7 and R2 are sent to the circuits C11, C14, C21 and C22, which block them.

It will thus be seen that the characters of the instruction contained in the part RLE-3 are successively transferred into the instruction register of the connecting system BLF-1, the transfer of each character being triggered in response to the emission of a short signal by the generator GI-3. The operations for transferring the other characters of the instruction contained in the part RLE-3 are identical to those which have just been explained with reference to the transfer of the first two characters of this instruction. In order to reduce the proportions of the present description, therefore, these operations will not be described here.

There will now be described what happens from the instant when the first four characters of the instruction are contained in the stages RDR-2 to RDR-5 and when the fifth character contained in the register EVDQ is to be transferred into the register RVDQ. The pulse which is sent to the conductor XREP-1 at this instant is transmitted, as before, by the circuit C2 and is applied on the one hand to the input of the delay element R1 and on the other hand to the gate 44, through the circuit C26, thus bringing about the transfer of the fifth character from the register EVDQ to the register RVDQ. Thereafter, the delayed pulse which is set up at the output of R1 is transmitted by the circuits C10 and C7, blocked by the circuits C6, C9, C23, C27, C28 and C8 and applied to the inputs of R12, R7 and R2. After transmission by C10 it is applied to the input of R3, and after transmission by C7 it is applied to the gate 45, thus producing the transfer of the fifth character contained in the register RVDQ to the stage RDR-5. At the same time, the other characters already written in the instruction register undergo a shift to the stages RDR-1 to RDR-4, so that finally the stage RDR-1 contains the "positioning" T.O. character, thus bringing the output PST of the decoder DTO to a positive potential, the stage RDR-2 contains the T.O.C. character "three," the stage RDR-3 contains the T.O.C. character "two" and the stages RDR-4 and RDR-5 contain the fourth and fifth characters respectively. The delayed pulses which are also set up at the outputs of R12, R7 and R2 are sent to the circuits C11, C14, C21 and C22, which block them. As soon as the instruction register has received the fifth character of the instruction, the decoding and control member CCA positions the selection switch in two parts CS-1 and CS-2, so that only the magnetic tape of the third tape unit can be positioned. The complementary output of the flip-flop BRP being at a positive potential, as also is the output PST of the decoder DTO, that of the circuit E7 (FIG. 3C) is also at a positive potential, whereby the circuit C17 is rendered conductive. The output VID of this decoder no longer being at positive potential, that of the circuits E5 and E2 is also no longer at positive potential, whereby the circuits C12 and C7 are rendered nonconductive. In addition, the two inputs of the circuits E6 are now brought to a positive voltage, which renders the circuit C13 conductive. Consequently, the delayed pulse which is set up at the output of R3 is transmitted by the circuits C17 and C13 and blocked by the circuits C12 and C18 to C20. The pulse transmitted by the circuit C17 is applied through a buffer L7 on the one hand to the normal input of the flip-flop BTQ, which then changes to the state "1," and on the other hand to a gate 47, which results in the transfer, to the register EVCQ, of the "qualitative transfer preparation" code order permanently contained in the stage MOR-1 of the order memory. The pulse transmitted by the circuit C13 is applied to the input of a delay element R4, the delay of which is such that the delayed pulse which it supplies appears at its output only when the transfer of the preceding code order has been completed. The delayed pulse which is set up at the output is applied on the one hand through a buffer L8 to the complementary input of the flip-flop BST which then changes to the state "0,`" and on the other hand through a buffer L9 to the normal input of the flip-flop BOL, which thus changes to the state "1." Consequently, the circuits C4 and C3 are rendered conductive, while the circuit C2 becomes nonconductive. The positive voltage which is set up at the normal output of the flip-flop BOL is applied through the buffer L6 to the conductor OR-1 and constitutes the long signal hereinbefore referred to.

In response to the reception of this long signal, the member DSG sends a pulse through the conductor SL-1 to the control circuits C51 and C61. This pulse is blocked by the circuit C51 and transmitted by the circuit 61, which applies it through the buffer L42 to the complementary input of the flip-flop BGX, which then changes to "0," and to the input of the circuit C50 which blocks it owing to the fact that it is nonconductive. Under these conditions, the circuit C58 becomes conductive. A pulse emitted by a pulse generator GI-4 and applied to the gated input of the circuit C58 is then transmitted by this circuit and applied to the normal input of the flip-flop BGX, which returns to "1," thus again rendering the circuit C58 nonconductive. This same pulse is in addition applied on the one hand to the input of a delay element R42 which will hereinafter be referred to and on the other hand to the delay element R41, through the buffer L48. The delayed pulse which is set up at the output of the delay element R41 is transmitted by the buffer L41 and the circuit C71 and sent to the conductor XREP-1.

The pulse thus sent to the conductor XREP-1 is applied to the gated inputs of the circuits C2 and C3. Owing to the fact that the circuit C2 is now nonconductive and the circuit C3 conductive, this pulse is transmitted by the circuit C3 and applied to the gated inputs of the circuits C4 and C29, which are conductive, to the input of a delay element R5 and to a gate 51 (FIG. 3A). The application of the pulse to the gate 51 brings about the transfer of the "qualitative transfer preparation" code order contained in the register EVCQ to the register RVCQ. The pulse transmitted by the circuit C4 is applied to the complementary input of the flip-flop BOL, which then returns to "0." Consequently, the circuit C4 ceases to be conductive and the conductor OR-1 is no longer at a positive potential. The pulse transmitted by the circuit C4 is in addition applied to the gated input of the circuit C35, which is nonconductive. It is also to be noted that the flip-flop BRC performs no function at the moment and that it remains in the state "0." This flip-flop changes its state only in the course of the particular operations which concern the return into circuit of the magnetic tape units. In the following text, therefore, it will be referred to only in the description of the operations relative to this return into circuit. Since, with the exception of this particular case, the flip-flop BRC is always in the state "0" and the circuit C35 is consequently nonconductive, there will be no disadvantage in omitting to mention that the pulse transmitted by the circuit C4 is sent to the circuit C35, since the latter is nonconductive. FIG. 3B shows that the pulse which emanates from the circuit C3 and is transmitted by the circuit C29 is applied to the normal input of the flip-flop BST, which then changes to the state "1," thus again rendering C2 conductive and C3 nonconductive. Finally, the delayed pulse which is set up at the output of the delay element R5 is applied on the one hand to the register EVCQ to return this register to zero and on the other hand to the input of a delay element R6. The delayed pulse which is set up at the output of the delay element R6 is then applied through the buffer L3 to the gated input of the circuit C6, which blocks it owing to the fact that it is nonconductive.

The delay element R42 (FIG. 2G) is such that the delayed pulse which it supplies is set up at its output only when the delayed pulse which is supplied by the delay element R6 just referred to has appeared at the output of this delay element. The delayed pulse which then appears at the output of the delay element R42 is applied on the one hand through a buffer L50 to the gate 21 (FIG. 2C), whereby the transfer of the "qualitative transfer preparation" code order contained in the register RVCQ to the register RCO is triggered, and on the other hand to the input of a delay element R43 (FIG. 2C), which then supplies a delayed pulse at its output when the transfer of the said code order has been completed. It is also to be noted that as a result of this transfer only the output STQ of the register RCO is brought to a positive potential, and that consequently, of all the circuits C40 to C48, only the circuits C42 and C48 are rendered conductive. The delayed pulse which is set up at the output of R43 is applied to the gated inputs of the circuits C47 and C48 and is then transmitted only by the circuit C48. The pulse transmitted by the circuit C48 is sent on the one hand to the buffer L48, which transmits it to the delay element R41, and on the other hand through a buffer L51 (FIG. 2D) to a gate 25, which triggers the transfer, to the register EVDQ, of the code-response character permanently contained in the part RPU-2 of the register RPU. In addition, the delayed pulse which is set up at the output of the delay element R41, when this transfer has been completed, is transmitted by the buffer L41 and the circuit C71 and sent to the conductor XREP-1.

The pulse which is thus sent to the conductor XREP-1 is then transmitted by the circuit C2 and is sent on the one hand to the input of the delay element R1 and on the other hand through the circuit C26 to the gate 44, thus triggering the transfer of the code-response character contained in the register EVDQ to the register RVDQ. Consequently, the output X3 of the decoder DKR is now brought to a positive potential and the circuit C28 is thus rendered conductive. Thereafter, the delayed pulse which is set up at the output of R1 is applied to the gated inputs of the circuits C6, C9, C10, C23, C27, C28, C7, C8, and to the inputs of the delay elements R12, R7 and R2. Of all these circuits, only the circuits C10 and C28 are conductive. The pulse transmitted by the circuit C10 is applied to the input of R3. The pulse transmitted by the circuit C28 is applied to the normal input of the flip-flop BRP, which then changes to the state "1." Consequently, a positive voltage is set up at the output of the circuit E11 (FIG. 3G), whereby the circuit C14 is rendered conductive. Likewise, as a result of this changeover, the outputs of the circuits E6 and E7 (FIG. 3C) cease to be brought to a positive potential, whereby the circuits C13 and C17 are rendered nonconductive. The circuit E4 (FIG. 3G) is connected by one of its three inputs to the output of an inverter I2 whose input is connected to the output PST of the decoder DTO. Owing to the fact that this output PST is brought to a positive potential, no positive voltage is set up at the output of the inverter I2. Consequently, the output of the circuit E4 is not brought to a positive potential, and the circuit C11 is thereby rendered nonconductive. Under these conditions, the delayed pulse which is set up at the output of R12 is blocked by the circuit C11. The delayed pulse which is set up at the output of R2 is sent to the circuits C21 and C22, which block it owing to the fact that they are nonconductive. The delayed pulse which is set up at the output of R3 is sent to the circuits C12, C13 and C17 to C20, which block it owing to the fact that they are not conductive. However, the delayed pulse which is set up at the output of R7 is transmitted by the circuit C14, which has become conductive, and it is then applied on the one hand to the gate 40, thus triggering the transfer of the T.O.C. character "two" contained in the stage RDR-3 to the register RPR, and on the other hand to the input of a delay element R8 (FIG. 3G), which applies it to the complementary input of the flip-flop BPA as soon as this transfer has been completed. As explained in detail in the foregoing, the contact KA closes under these conditions and the magnetic tape of the third tape unit is driven until it is positioned on the block of data "number two." As soon as this positioning has taken place, that one of the two contacts KV and KR which enabled the tape to be driven opens and thereby stops the movement of the tape, while a positive voltage is set up at the output of the circuit E1. Under these conditions, the circuit C1 becomes conductive and transmits a pulse which is emitted by the generator GI-1. The pulse transmitted by the circuit C1 is applied to the normal input of the flip-flop BPA, which again changes to the state "1" and to the input of a delay element R9 referred to in the following. In addition, this same pulse is applied through a buffer L10 to the normal input of the flip-flop BES, which then changes to "1," and to the input of the buffer L8 which applies it to the complementary input of the flip-flop BST, which then changes to "0," and to the input of a buffer L11 (FIG. 3C), which transmits it on the one hand to the register RVDQ in order to return this register to zero, and on the other hand through the buffer L12 (FIG. 3D), to the complementary input of the flip-flop BRP, which then returns to "0." As a result of the return-to-zero of the register to RVDQ, only the output X2 of the decoder DKR is brought to a positive potential. The pulse transmitted by the circuit C1 (FIG. 3G) is in addition applied through a buffer L13 to the complementary input of the flip-flop BTQ, which then returns to "0," to a gate 52, whereby the transfer to the register EVCQ of the "state of "apparatus" character which was written in the register RSI at the instant when the tape was stopped is brought about, and finally to the input of a delay element R10, which transmits it to the register RSI in order to return the latter to zero, as soon as the latter transfer has been completed. As a result of the various changeovers which have just taken place, the circuits C9, C13, C17 and C3 become conductive, while the circuits C10, C26, C14 and C2 become nonconductive. When the various operations just described have been completed, a delayed pulse is set up at the output of the delay element R9 (FIG. 3G), which transmits it on the one hand to the register RPR in order to return the latter to zero, and on the other hand through the buffer L4 to the normal input of the flip-flop BOC, which changes to "1." As has been explained in detail in the foregoing a short signal is sent to the conductor OR-1 under these conditions.

In response to the reception of this signal, the member DSG sends a pulse to the circuits C40 to C46. This pulse is transmitted only by the circuit C42, which applies it on the one hand to the input of the delay element R41 through L48 and on the other hand to the input of a delay element R44 (FIG. 2G) which will hereinafter be referred to. The delayed pulse which is set up at the output of R41 is transmitted by L41 and C71 and sent to XREP-1.

This pulse sent to XREP-1 is transmitted by the circuit C3, which applies it to the gate 51, thereby triggering the transfer of the "state of apparatus" character from the register EVCQ to the register RVCQ. The pulse transmitted by C3 is in addition applied to the input of the delay element R5 and to the inputs of the circuits C4 and C29. Since C4 is nonconductive, it is only transmitted by the circuit C29, which applies it to the normal input of the flip-flop BST, which then changes to "1." Under these conditions, C2 becomes conductive again, while C3 becomes nonconductive again. The delayed pulse which is set up at the output of R5 is sent on the one hand to the register EVCQ to return the latter to zero and on the other hand to the delay element R6. The delayed pulse which is then set up at the output of R6 is sent to the circuit C6, which blocks it.

It is at this instant that a delayed pulse appears at the output of the delay element R44 (FIG. 2G). This pulse is then applied on the one hand to a gate 26 (FIG. 2C), thereby triggering the transfer of the "state of apparatus" character from the register RVCQ to a "state of apparatus" register REA, which is shown in FIG. 2B, and on the other hand to the input of R41 through L48. Associated with the register REA is a decoder DEA which has the object of decoding the "state of apparatus" character which is contained in the register REA. If no incident has occurred during the operation of the peripheral element, this decoder renders conductive a control circuit C88 and nonconductive a control circuit C89. If, on the other hand, an incident has occurred in the course of this operation, the decoder DEA renders conductive the circuit C89 and nonconductive the circuit C88. The delayed pulse which then appears at the output of R41 is transmitted by L41 and C71 and sent to XREP-1.

The pulse which is thus sent to XREP-1 is transmitted by the circuit C2 and applied on the one hand to the circuit C26, which blocks it because it is nonconductive, and on the other hand to the input of R1. The delayed pulse which is set up at the output of R1 is applied, as before, with or without delay, to the gated inputs of the circuits C6, C9, C10, C11, C14, C21, C22, C23, C27, C28, C7 and C8. Of all these circuits, only the circuit C9 is conductive. The pulse which is transmitted by C9 is applied to the gated input of the circuit C30 (FIG. 3F), to one of the inputs of a buffer L14 (FIG. 3C), which transmits it to the instruction register RDR in order to return the latter to zero, to one of the inputs of the buffer L8, which applies to the complementary input of the flip-flop BST, which then changes to "0," to one of the inputs of the buffer L9, which applies it to the normal input of the flip-flop BOL, which changes it to "1," under these conditions, and to one of the inputs of a buffer L15 (FIG. 3G), which applies it to the complementary inputs of the flip-flops BES and BMT, which then return to "0." Consequently, the circuit C9 again becomes nonconductive and the circuits C10 and C26 conductive. The circuit C3 becomes conductive, while the circuit C2 becomes nonconductive. The return-to-zero of the register RDR results in the appearance of a positive voltage at the output VID of the decoder DTO. Consequently, the circuits C13 and C17 become nonconductive. Likewise, the circuit C12 is nonconductive owing to the fact that the flip-flop BOL is at "1." Finally, the circuit C4 becomes conductive. It is also to be noted that if the operator has not brought about the changeover of the flip-flop BPC to "1," the complementary output of this flip-flop is at a positive potential and the circuit C30 is therefore conductive. Under these conditions, the pulse which has been transmitted by the circuit C9, as has been stated in the foregoing, is also transmitted by the circuit C30, which applies to a gate 43, thus bringing about the transfer, to the register EVCQ, of the "end of normal operation" code order permanently contained in the stage MOR-5 of the order memory. Finally, the changeover of the flip-flop BOL to "1" results in the appearance of a positive voltage, or long signal, at the conductor OR-1. However, if the operator has brought about the changeover of the flip-flop BPC to "1" by depressing the button OF, the circuit C30 will have become nonconductive and will have blocked the pulse transmitted by C9. Under the same conditions, as a result of the appearance of a positive voltage at the output of the circuits E21, E15 and E16, the circuit C24 will have become conductive and will have transmitted a pulse sent by the generator GI-2, which will then have been applied on the one hand to the gate 41, thus producing the transfer, to the register EVCQ, of the "end of incident operation" code order permanently contained in the stage MOR-6, and on the other hand through a buffer L16 and buffers L8 and L9 to the complementary input of the flip-flop BST, which will thus have changed to "0," and to the normal input of the flip-flop BOL, thus producing the appearance of a long signal at the conductor OR-1. For the sake of simplicity, it will be assumed that in the present case this has not occurred and that the code order which is now contained in the register EVCQ is "end of normal operation."

In response to the reception of the long signal which has appeared at the conductor OR-1, the member DSG sends a pulse to the circuits C51 and C61. This pulse is blocked by C51 and transmitted by C61, which applies it, as has already been seen, to the complementary input of the flip-flop BGX, which then changes to "0," and to the input of the circuit C50, which blocks it. Under these conditions, the circuit C58 becomes conductive and transmits a pulse emanating from the generator G1-4. The pulse transmitted by C58 is applied on the one hand to the normal input of the flip-flop BGX, which then returns to "1," and on the other hand to the input of the delay element R42 and through L48 to the input of the delay element R41. The delayed pulse which appears at the output of R41 is transmitted by L41 and C71 and sent to the conductor XREP-1.

The pulse which is thus sent to XREP-1 is transmitted by the circuit C3 and applied to the inputs of the circuits C4 and C29, which are conductive, to the input of the delay element R5 and to the gate 51, which results in the transfer of the "end of normal operation" code order contained in the register EVCQ to the register RVCQ. The pulse transmitted by C4 is applied to the complementary input of the flip-flop BOL, which returns to "0," thus rendering C4 nonconductive. The pulse transmitted by C29 is applied to the normal input of the flip-flop BST, which returns to "1," whereby C2 is again rendered conductive and C3 nonconductive. Finally, the delayed pulse which appears at the output of R5 is sent on the one hand to the register EVCQ in order to return it to zero, and on the other hand to the input of the delay element R6. The delayed pulse which is then set up at the output of R6 is sent through L3 to the circuit C6, which blocks it owing to the fact that it is nonconductive.

At this instant, as has been seen in the foregoing, a delayed pulse appears at the output of the delay element C42. This pulse is applied on the one hand through L50 to the gate 21, which triggers the transfer of the "end of normal operation" code order contained in the register RVCQ to the register RCO, and on the other hand to the input of the delay element R43. As a result of this transfer, only the output SFN is brought to a positive potential. Consequently, of all the circuits C40 to C48, only the circuit C47 is rendered conductive. The delayed pulse which is then set up at the output of R43 is applied to the inputs of C47 and C48 and is therefore transmitted only by the circuit C47, which in turn applies is to the gated inputs of the circuits C88 and C89. If, as explained in the foregoing, an incident has occurred in the course of the operation of the magnetic tape unit, this pulse is blocked by the circuit C88 and transmitted by the circuit C89, which then sends it to an incident-signaling device DEI (FIG. 2B) which signals to the operator that an incident has occurred. In this case, the machine stops and the operator, after having remedied this incident, will have to depress a push button MR (FIG. 2B) in order to restart the machine. Depression of the button MR results in the emission of a pulse by a differentiating amplifier AD-4, this pulse thereafter being applied to one of the two inputs of a buffer L52. If, on the other hand, no incident has occurred in the course of the operation, the pulse which emanates from C47 is transmitted by the circuit C88 and applied to the other input of L52. The pulse which emanates from C88 or from AD-4 and is transmitted by L52 is applied on the one hand to the register RNB to return the latter to zero and on the other hand through a buffer L53 (FIG. 2C) to the register RCO to return it to zero. Consequently, the circuits C40 and C48 again become conductive, while C47 becomes nonconductive. The pulse transmitted by L52 is in addition applied through a buffer L54 (FIG. 2G) and the buffer L45 to the gated inputs of the circuits C101 and C111. If all the flip-flops BA-1 to BA-7 are in the state "0," this pulse is finally transmitted by the circuit C117 and then by the circuit C59 and sent to the control unit UCA, which is thus informed that all the peripheral elements are available. Finally, the pulse which is transmitted by L52 is applied to one of the inputs of the buffer L46 to initiate the processing of another peripheral instruction by a procedure similar to that just described.

READING OF THE RECORDED DATA

The magnetic tape of the third magnetic tape unit having been positioned on the second block of recorded data, as just described, the case will now be considered in which the instruction which is to be processed is that which is contained in the standby register RI-1, and in addition, it will be assumed that this instruction controls the reading of data recorded on this tape and that it consists of the following five characters:

first character: T.O. "forward reading"

second character: number of apparatus "three"

third character: no significance here

fourth character: first character of the "transfer length" number

fifth character: second character of the "transfer length" number.

In order to fix ideas, it will be assumed here by way of example that these fourth and fifth characters are each represented respectively, by the following two combinations of eight binary digits:

fourth character: 0000 0000

fifth character: 0100 0000

the juxtaposition of these fourth and fifth characters then form the following binary combination:

00000000 01000000

that is to say, a pure binary number which, in this form, represents the decimal number 64. This number expresses the fact that the transfer length is 64, or in other words that only the first 64 characters of the block on which the tape is positioned will be read and transferred.

In order not to lengthen the description, the manner in which the transfer of this instruction to the register RDR takes place will not be indicated, this transfer being formed in the same way as that previously described. There will simply be described what happens from the instant when the first four characters of the instruction are contained in the stages RDR-2 to RDR-5 and when the fifth character contained in the register EVDQ is to be transferred into the register RVDQ. The pulse coming from the central unit and sent at this instant to the conductor XREP-1 is transmitted by the circuit C2, which is conductive under the conditions described in this respect. The pulse transmitted by the circuit C2 is applied on the one hand to the input of the delay element R1 and on the other hand to the gate 44 through the circuit C26, thus bringing about the transfer of the fifth character from the register EVDQ to the register RVDQ. The delayed pulse which is then set up at the output of R1 is transmitted by the circuits C10 and C7, blocked by the circuits C6, C9, C23, C27, C28 and C8 and applied to the inputs of the delay elements R12, R7 and R2. When transmitted by C10, it is applied to the input of the delay element R3, and when transmitted by C7 it is applied to the gate 45, thus producing the transfer of the fifth character contained in the register RVDQ to the stage RDR-5. At the same time, the four other characters already written in the register RDR are shifted to the stages RDR-1 to RDR-4, so that finally the stage RDR-1 contains the "forward reading" T.O. character, thus bringing the output LAV of the decoder DTO to a positive potential, the stage RDR-2 contains the number of apparatus character "three," the stage RDR-3 contains the third character, and the stages RDR-4 and RDR-5 contain the fourth and fifth characters, both of which form the binary combination referred to in the foregoing, expressing the fact that the length of the transfer is 64 characters.

Under these conditions, the decoding and control member CCA positions the selecting switch in two parts CS-1 and CS-2, so that only the magnetic tape of the third tape unit can be read. The delayed pulses which are set up at the outputs of the delay elements R12, R7 and R2 are blocked by the circuits C11, C14, C21 and C22. In FIG. 3D, the output of an OR circuit U2, one of the two inputs of which is connected to the output LAV of the decoder DTO, while its other input is connected to the output LAR of this same decoder, is brought to a positive potential since the output LAV is also at a positive potential. Under these conditions, a gate 53 (FIG. 3H) connected to the output of the circuit U2 becomes conductive, so as to enable the characters which will be read on the magnetic tape by the reading circuits CLK to be successively transferred, after reading, to the register EVCQ. FIG. 3D also shows two OR circuits U3 and U4, each of which has one of its inputs connected to the output LAV of the decoder DTO. Since the output LAV is brought to a positive potential, those of the circuits U3 and U4 are also brought to a positive potential. Owing to the fact that the output VID of the decoder DTO is not at a positive voltage and that the complementary output of the flip-flop BRP, which is in the state "0," is at a positive potential, the output of the circuit E6 (FIG. 3C) is brought to a positive potential, whereby the circuit C13 is rendered conductive. Since the output VID is not brought to a positive potential, no positive voltage is set up at the output of the circuit E5 and consequently the circuit C12 is not conductive. Finally, owing to the fact that the output LAV is at a positive potential, as also is the complementary output of the flip-flop BRP, a positive voltage is set up at the output of the circuit E9 (FIG. 3C), whereby the circuit C19 is tendered conductive. Consequently, the delayed pulse which, as has been seen in the foregoing, is set up at the output of the delay element R3 and which is applied to the gated inputs of the circuits C12, C13 and C17 to C20 is transmitted only by the circuits C13 and C19. The pulse transmitted by the circuit C19 is applied to a gate 49 (FIG. 3F), which results in the transfer, to the register EVCQ of the "advance +1 output channel transfer" code order which is permanently contained in the stage MOR-3 of the order memory. The pulse transmitted by the circuit C13 is applied to the input of the delay element R4, so that when the transfer of the code order just referred to has been completed, a delayed pulse is set up at the output of R4 and is applied on the one hand through the buffer L8 to the complementary input of the flip-flop BST, which then changes to "0," and on the other hand through the buffer L9 to the normal input of the flip-flop BOL, which then changes to "1." Consequently, the circuits C4 and C3 are rendered conductive, while the circuit C2 becomes nonconductive. The positive voltage which is set up at the normal output of the flip-flop BOL is applied through the buffer L6 to the conductor OR-1 and then constitutes a long signal.

In response to the reception of this signal, the member DSG sends a pulse through the conductor SL-1 to the circuits C51 and C61. This pulse is blocked by C51 and transmitted by C61, which applied it on the one hand through the buffer L42 to the complementary input of the flip-flop BGX, which then changes to "0," and on the other hand to the output of the circuit C50, which blocks it because it is nonconductive. Under these conditions, the circuit C58 becomes conductive and transmits a pulse emitted by the pulse generator GI-4. This pulse is applied to the normal input of the flip-flop BGX, which then changes to "1," thereby again rendering the circuit C58 nonconductive. This same pulse is applied to the input of the delay element R42 and, through the buffer L48, to the input of the delay element R41. The delayed pulse which is set up at the output R41 is transmitted by the buffer L41 and the circuit C71 and sent to the conductor XREP-1.

The pulse which is thus sent to the conductor XREP-1 is applied to the gated inputs of C2 and C3. Since C3 is now conductive and C2 nonconductive this pulse is transmitted by the circuit C3 and applied to the gated inputs of the circuits C4 and C29, which are conductive, to the input of the delay element R5 and to the gate 51. The pulse applied to the gate 51 produces the transfer, to the register RVCQ, of the "advance +1 output channel transfer" code order contained in the register EVCQ. The pulse transmitted by the circuit C4 is applied to the complementary input of the flip-flop BOL, which then returns to "0." Consequently, C4 ceases to be conductive and the conductor OR-1 is no longer at a positive potential. The pulse transmitted by the circuit C29 is applied to the normal input of the flip-flop BST, which then changes to "1," whereby C2 is again rendered conductive and C3 nonconductive. Finally, the delayed pulse which is set up at the output of the delay element R5 is applied on the one hand to the register EVCQ in order to return the latter to zero, and on the other hand to the input of the delay element R6. The delayed pulse which is thereafter set up at the output of R6 is applied through the buffer L3 to the input of the circuit C6, which blocks it because it is not conductive.

At this instant, a delayed pulse is set up at the output of the delay element R42 (FIG. 2G). This pulse is applied on the one hand through the buffer L50 to the gate 21, which results in triggering of the transfer, to the register RCO, of the "advance +1 output channel transfer" code order contained in the register RVCQ, and on the other hand to the input of the delay element R43, which then supplies a delayed pulse at its output when the transfer of the said code order has been completed. It is to be noted, that, as a result of this transfer, only the output SCP of the register RCO is brought to a positive potential, and that consequently, of all the circuits C40 to C48, only the circuits C43 and C48 are rendered conductive. The delayed pulse which is set up at the output of R43 and which is applied to the gated inputs of C47 and C48 is therefore transmitted only by the circuit C48. The pulse transmitted by C48 is sent on the one hand to the buffer L48 which transmits it to the delay element R41, and on the other hand through the buffer L51 to the gate 25, whereby the transfer, to the register EVDQ, of the code response character permanently contained in the part RPU-2 of the register RPU is initiated. In addition, the delayed pulse which is set up at the output of R41 when this transfer is complete is transmitted by the buffer L41 and the circuit C71 and sent to the conductor XREP-1.

The pulse which is thus sent to XREP-1 is then transmitted by the circuit C2 and sent on the one hand to the input of the delay element R1 and on the other hand through C26 to the gate 44, thus triggering the transfer of the code response character contained in the register EVDQ to the register RVDQ. As a result of this transfer, the output X3 of the decoder DKR is brought to a positive potential and the circuit C28 is rendered conductive. Owing to the fact that the output of the circuit U2 is also positive, a positive voltage is now set up at the output of the circuit E3, whereby the circuit C8 is rendered conductive. Likewise, since the complementary outputs of the flip-flops BAV and BAR are at a positive voltage, the output X3 is at a positive potential and the output of the circuit U3 is also at a positive potential, a positive voltage is set up at the output of the circuit E14, whereby the circuit C23 is rendered conductive. At this instant, there is set up at the output of the delay element R1 a delayed pulse which is applied to the gated inputs of the circuits C6, C9, C10, C23, C27, C28, C7 and C8 and to the inputs of the delay elements R12, R7 and R2. Of all these circuits, only the circuits C10, C23, C28 and C8 are conductive. The pulse transmitted by the circuit C10 is applied to the input of the delay element R3. The pulse transmitted by the circuit C23 is applied to a gate 54 (FIG. 3D), whereby the transfer of the characters contained in the stages RDR-4 and RDR-5 of the instruction register to a subtractive counting register RDK (FIG. 3H) is initiated. It will be recalled that these two characters form together a coded combination of 16 binary digits, thus constituting a binary number whose value represents the number of characters which are to be transferred. The subtractive counting register RDK is so designed that, each time it receives through its input EDK a pulse emitted by the signal-generating member GSS of a tape unit, and applied through the switch CS-1 to the gated input of a control circuit C31 which finally transmits it to the input EDK, the binary number which it contains is reduced by one unit. The subtractive counting register RDK is so designed that when one value which it contains becomes equal to zero a positive voltage is set up at its output SDK. It is to be noted here that the gating input of the circuit C31 which is connected to the output of the circuit U3 is brought to a positive potential and that under these conditions the circuit C31 is conductive. However, owing to the fact that the tape of the third tape unit is not driven, the member GSS to which the gated input of the circuit C31 is at present connected does not send any pulse. Under these conditions, the value contained in the register RDK remains unchanged. Moreover, the pulse which is transmitted by the circuit C28, as stated in the foregoing, is applied to the normal input of the flip-flop BRP, which then changes to "1." Since the normal output of the flip-flop BRP is now brought to a positive voltage, as also is that of the flip-flop BPA, and since that of the circuit U4 is also at a positive potential, a positive voltage is set up at the output of the circuit E13, whereby the circuit C22 is rendered conductive. In addition, the pulse which is transmitted by the circuit C8 is applied through L8 to the complementary input of the flip-flop BST, which then changes to "0," thus rendering C3 conductive and C2 nonconductive. It is further to be noted that, as a result of the changeover of the flip-flop BRP, the output of the circuit E6 ceases to be at a positive potential and that consequently the circuit C13 becomes nonconductive. For the same reason, the output of the circuit E9 ceases to be at a positive potential and the circuit C19 then becomes nonconductive. Under these conditions, the delayed pulse which is set up at the output of R3 and which is applied to the gated inputs of the circuits C12, C13 and C17 to C20 is not transmitted by any of these circuits. At this instant, in response to the pulse which has been applied to its input as indicated in the foregoing, the delay element R2 supplies at its output a delayed pulse which, when applied to the inputs of the circuits C21 and C22, is transmitted only by the circuit C22. The pulse transmitted by C22 is then applied to the normal input of the flip-flop BAV, which then changes to "1." Under these conditions, the positive voltage which is set up at the normal output of this flip-flop is applied through the buffer L1 to the forward driving device EAV, which then drives the magnetic tape on which the data are written. In addition, owing to the changeover of the flip-flop BAV, the output of the circuit E19 ceases to be at a positive voltage, whereby the circuit C29 is rendered nonconductive. For the same reason, the output of the circuit E14 ceases to be at a positive potential, whereby the circuit C23 is rendered nonconductive. It is further to be noted that the delayed pulses which are set up at the outputs of the delay elements R12 and R7 are applied to the gated inputs of the circuits C11 and C14, which block them because they are not conductive. FIG. 3H shows a control circuit C32 whose gating input is connected to the output of an AND circuit E20 which has one of its two inputs connected to the output of the circuit U3 and the other input connected to the output SDK of the register RDK. This circuit C32 is nonconductive because the output SDK is not brought to a positive potential.

Since the tape has been positioned at the beginning of the second block of recorded data before being driven, and since it is now driven in the forward direction, the character which is the first to be read by the reading circuits CLK is the first character of this second block. After reading, this first character is transferred to the register EVCQ through the gate 53. At the same time, a pulse is sent by the member GSS. This pulse is applied to the circuit C31, which is conductive, and to the input of a delay element R11, which will hereinafter be referred to. When transmitted by C31, this pulse is applied to the gated input of a control circuit C33 (FIG. 3H), which blocks it owing to the fact that its gating input, which is connected to the output ECR of the decoder DTO, is not brought to a positive potential. This same pulse is applied to the input EDK of the register RDK, whereby the value contained in this register is decreased by one unit and then changes to 63. Finally, this same pulse is sent to the conductor OR-1 through the buffers 15 and L6, thus constituting a short signal.

In response to the reception of this signal, the member DSG sends a pulse to the circuits C40 to C46. This pulse is transmitted only by the circuit C43, which on the one hand applies it to the input of a delay element R45 (FIG. 2C) and on the other hand sends it to the conductor XREP-1 through the buffer L41 and the circuit C71.

This pulse sent to XREP-1 is transmitted by the circuit C3 which applies it to the gate 51, thereby initiating the transfer to the register RVCQ of the first character read, which is contained in the register EVCQ. The pulse transmitted by C3 is in addition applied to the inputs of the circuits C4 and C29, which are nonconductive, and to the input of the delay element R5. The delayed pulse which is thereafter set up at the output of R5 is sent on the one hand to the register EVCQ in order to return the latter to zero, and on the other hand to the delay element R6. The delayed pulse which is then set up at the output of R6 is sent to the circuit C6, which blocks it.

As soon as the transfer of the first character read to the register RVCQ is complete, a delayed pulse is set up at the output of the delay element R45. This pulse is then applied on the one hand to the input of a delay element R47 (FIG. 2B) and on the other hand through a buffer L55 to the gate EM, which results in the transfer of the first character read which is contained in the register RVCQ to the register RES. The delayed pulse which is set up at the output of R47 when this transfer is complete is sent on the one hand through a buffer L56 to the conductor DE in order to effect the writing of the said first character read in the memory 17, and on the other hand through the buffer L43 to the address advancer PAD, which then increases by one unit the address contained in the selection register 19.

It is to be noted here that as soon as the transfer of the first character read to the register RVCQ is complete, a second character may be read on the tape by the reading circuits CLK. It will here be assumed that the reading rate of the characters on the tape is made such as to satisfy these conditions. The reading of these characters, their transfer to the central unit and their writing in the memory 17 take place by identical methods similar to that just described. In order that the description may not be lengthened, these methods will not be discussed.

Finally, when the 64 character is read by the reading circuits and sent to the register EVCQ, the pulse which is sent by the member GSS and transmitted by the circuit C31 reduces by one unit the value contained in the register RDK, this value then becoming equal to zero. Under these conditions, the positive voltage which is set up at the output SDK renders the circuit C32 conductive. Consequently, the delayed pulse which is set up at the output of R11 is transmitted by C32, which applies it on the one hand to the complementary inputs of the flip-flops BAR and BAV and on the other hand to the normal input of the flip-flop BFF. The flip-flop BAV then changes to "0," thus causing the magnetic tape to stop. On the other hand, a positive voltage is again set up at the output of E14, whereby the circuit C23 is rendered conductive. The flip-flop BFF changes to "1," thereby rendering the circuit C6 conductive and the circuit C29 nonconductive. In addition, the pulse which has been transmitted by C31 is sent to the conductor OR-1 through L5 and L6.

In response to the reception of this pulse, the member DSG sends a pulse to the circuits C40 to C46 and, as before this pulse is transmitted by the circuit C43. As has been seen, this pulse is applied on the one hand to the input of the delay element R45 and on the other hand to the conductor XREP-1.

The pulse sent to XREP-1 is transmitted by the circuit C3, which applies it to the gate 51, thereby initiating the transfer to the register RVCQ of the 64 character, or the last character read, which is contained in the register EVCQ. The pulse transmitted by C3 is in addition applied to the inputs of the circuits C4 and C29, which are nonconductive and to the input of the delay element R5. The delayed pulse which is thereafter set up at the output of this delay element is sent on the one hand to the register EVCQ to return the latter to zero and on the other hand to the delay element R6.

As soon as the transfer of the last character read to the register RVCQ is complete, a delayed pulse is set up at the output of the delay element R45. This pulse produces, by a procedure similar to that already described, the transfer of this last character read to the register RES and then its writing in the data memory 17.

The delayed pulse which is set up at the output of R6 is applied to the input of the circuit C6, which this time is conductive. The pulse transmitted by C6 is first applied through a buffer L17 to the complementary input of the flip-flop BFF, which returns to "0," thus again rendering C6 nonconductive and C29 conductive. The pulse transmitted by C6 is also applied through the buffer L7 (FIG. 3F) on the one hand to the normal input of the flip-flop BTQ, which then changes to "1," and on the other hand to the gate 47, thus triggering the transfer, to the register EVCQ of the "qualitative transfer preparation" code order contained in the stage MOR-1. The pulse transmitted by C6 is in addition applied through the buffer L11 on the one hand to the register RVDQ to return it to zero and on the other hand through the buffer L12 (FIG. 3D) to the complementary input of the flip-flop BRP, which then changes to "0." The pulse transmitted by C6 is then sent through the buffer L14 (FIG. 3C) to the instruction register RDR, which is then returned to zero. As a result of the return-to-zero of this register, the outputs of the circuits U2, U3, U4 and E9 cease to be at a positive potential. Consequently, the circuits C8, C23, C31 C32, C22 and C19 can no longer be rendered conductive. The output VID of the decoder DTO is then at a positive potential, as also is the normal output of the flip-flop BMT. However, owing to the fact that the flip-flop BTQ is now at "1," its complementary output is no longer at a positive voltage. Consequently, that of the circuit E2 is also no longer at a positive voltage and hence the circuit C7 is not conductive. Finally, the pulse which is transmitted by C6 is applied on the one hand through the buffer L8 to the complementary input of the flip-flop BST, which remains at "0," since it was already in this state, and on the other hand through the buffer L9 to the normal input of the flip-flop BOL, which then changes to "1." As a result of this changeover, the circuit C4 is rendered conductive. The positive voltage which is set up at the output of the flip-flop BOL is applied through L6 to the conductor OR-1, thus again constituting a long signal. In response to the reception of this signal, the member DSG sends a pulse to the circuits C51 and C61. This pulse is blocked by C51 and transmitted by C61, which applies it to the complementary input of the flip-flop BGX. Under these conditions, the pulse which is emitted by GI-4, as has been seen, is transmitted by C58 and applied on the one hand to the input of R42 and on the other hand to the input of R41. The delayed pulse which is thereafter set up at the output of R41 is sent to XREP-1 through L41 and C71.

The pulse which is sent to XREP-1 is transmitted by C3 and applied to the inputs of the circuits C4 and C29, which are conductive, to the input of R5 and to the gate 51. The pulse applied to the gate 51 initiates the transfer to RVCQ of the "qualitative transfer preparation" code order contained in the register EVCQ. The pulse transmitted by C4 causes the flip-flop BOL to change to "0," whereby C4 is again rendered nonconductive. Owing to the fact that the instruction register RDR has been returned to zero a positive voltage is present at the output VID of the decoder DTO, while on the other hand, owing to the fact that the flip-flop BOL is now at "0," a positive voltage is set up at the output of the circuit E5, whereby C12 is again rendered conductive. The pulse transmitted by C29 causes the flip-flop BST to change to "1," whereby C2 is rendered conductive and C3 nonconductive. The delayed pulse which is thereafter set up at the output of R5 returns EVCQ to zero and is applied to the input of R6. Finally, the delayed pulse which is set up at the output of R6 is sent to the circuit C6, which blocks it.

At this instant, a delayed pulse is set up at the output of R42. This pulse is applied on the one hand to the input of R43 and on the other hand to the gate 21, thus producing the transfer into the register RCO of the "qualitative transfer preparation" code order contained in RVCQ. Consequently, a positive voltage is set up at the output of STQ. Of all the circuits C40 to C48, only the circuits C42 and C48 are thus rendered conductive. The delayed pulse which is set up at the output of R43 is therefore transmitted by C48 and applied on the one hand to the input of R41 and on the other hand to the gate 25, thus producing the transfer into EVDQ of the code response contained in RPU-2. Finally when this transfer is complete, a delayed pulse is set up at the output of R41 and is sent to XREP-1 through L41 and C71.

The pulse sent to XREP-1 is transmitted by C2 and sent on the one hand to the input of R1 and on the other hand through C26 to the gate 44, thus initiating the transfer to the register RVDQ of the code response character contained in the register EVDQ. As a result of this transfer, the output X3 is brought to a positive potential and C28 is rendered conductive. The delayed pulse which is thereafter set up at the output of R1 is applied to the gated inputs of C6, C9, C10, C23, C27, C28, C7 and C8 and to the inputs of the delay elements R12, R7 and R2. Of all these circuits, only the circuits C10 and C28 are conductive. The pulse which is transmitted by the circuit C10 is applied to the input of R3. The pulse which is transmitted by the circuit C28 is applied to the normal input of the flip-flop BRP, which then changes to "1." Consequently, no positive voltage can be set up at the output of the circuits E6 to E10 and hence the circuits C13 and C17 to C20 are nonconductive. Since the normal output of the flip-flop BRP is now at a positive potential, as also is that of the flip-flop BTQ, and since the output of the inverter I2 is brought to a positive potential because the output PST of the decoder DTO is not at a positive potential, a positive voltage is now set up at the output of the circuit E4, whereby the control circuit C11 is rendered conductive. The delayed pulses which thereafter appear at the outputs of the delay elements R7 and R2 are blocked by the circuits C14, C21 and C22, but the delayed pulse which then appears at the output of the delay element R12 is transmitted by the circuit C11, which first transmits it through the buffer L13 to the complementary input of the flip-flop BTQ, which then returns to "0," thereby C11 nonconductive, to the input of the delay element R10 and to the gate 52, thus initiating the transfer to the register EVCQ of the "state of apparatus" character which was written in the register RSI at the end of the reading. The pulse transmitted by C11 is also transmitted through the buffer L10 on the one hand to the normal input of the flip-flop BES, which then changes to "1," and on the other hand to the inputs of the buffers L11 and L8, which transmit it to the register RVDQ in order to return the latter to zero, to the complementary input of the flip-flop BRP, which then returns to "0," and to the complementary input of the flip-flop BST, which then changes to "0." As a result of these various changeovers having just taken place, the circuits C9 and C3 are rendered conductive, while the circuits C10, C26 and C2 are rendered nonconductive. As the output VID, the normal output of the flip-flop BMT and the complementary output of the flip-flop BTQ are now all at a positive potential, a positive voltage now appears at the output of the circuit E2, whereby the circuit C7 is rendered conductive. Finally, the output of the decoder DKR which is now brought to a positive potential is the output X2, whereby the circuits C27 and C28 are rendered nonconductive. The delayed pulse which in addition appears at the output of the delay element R10 is transmitted to the register RSI to return it to zero. Finally, the delayed pulse which appears at the output of R3 is sent to the circuits C12, C13 and C17, to C20. Of all these circuits, only the circuit C12 is now conductive. Under these conditions, the pulse which is transmitted by C12 is applied to the normal input of the flip-flop BOC, which thus changes to "1." Consequently, as has already been explained, a short signal is sent to the conductor OR-1.

In response to the reception of this signal, the member DSG sends a pulse to the circuits C40 to C46, and this pulse is transmitted only by the circuit C42 because the output STQ is at a positive potential. This pulse transmitted by C42 is applied on the one hand to the input of the delay element R41 through L48 and on the other hand to the input of the delay element R44. The delayed pulse which is set up at the output of R41 is transmitted by L41 and C71 and sent to XREP-1.

This pulse sent to XREP-1 is transmitted through the circuit C3, which applies it to the gate 51, thus initiating the transfer to the register RVCQ of the "state of apparatus" character contained in the register EVCQ. The pulse transmitted by C3 is in addition applied to the input of the delay element R5 and to the inputs of the circuits C4 and C29. Since C4 is nonconductive, it is only transmitted by the circuit C29, which applies it to the normal input of the flip-flop BST, which then changes to "1." The circuit C2 then again becomes conductive and C3 nonconductive. The delayed pulse which then appears at the output of R5 is sent on the one hand to the register EVCQ to return it to zero and on the other hand to the input of R6. The delayed pulse which then appears at the output of R6 is sent to the circuit C6, which blocks it.

At this instant, a delayed pulse is set up at the output of R44 (FIG. 2G). This pulse is applied on the one hand to the gate 26 (FIG. 2C), which thus initiates the transfer of the "state of apparatus" character contained in the register RVCQ to the register REA, and on the other hand to the input of R41 through L48. In the present case, it will be assumed that no incident has occurred in the course of the reading which has been performed on the data recorded on the tape of the third tape unit. Consequently, the decoder DEA renders the circuit C88 conductive and the circuit C89 nonconductive. Thereafter, the delayed pulse which is set up at the output of R41 is transmitted by L41 and C71 and sent to XREP-1.

The pulse which is thus sent to XREP-1 is transmitted by the circuit C2 and applied on the one hand to the circuit C26, which blocks it because it is not conductive, and on the other hand to the input of R1. The delayed pulse which is thereafter set up at the output of R1 is applied to the inputs of the circuits C6, C9, C10, C23, C27, C28, C7 and C8, and to the inputs of R12, R7 and R2. Of all these circuits, only the circuits C9 and C7 are conductive. The pulse which is transmitted by C9 is applied to the input of C30, to one input of L14, which transmits it to the instruction register RDR, which remains at zero because it has already been returned to zero, to one input of L8, which applies it to the complementary input of the flip-flop BST, which then changes to "0," to one input of L9, which applies it to the normal input of the flip-flop BOL, which then changes to "1," and to one input of L15, which applies it to the complementary inputs of the flip-flops BES and BMT, which then return to "0." However, before the changeover of the flip-flop BMT occurs, the pulse which has been applied to the gated input of C7 is transmitted by this circuit and applied to the gate 45, but since the register RVDQ has previously been returned to zero, no character can be transferred from this register to the stage RDR-5, so that the instruction register RDR remains at zero. As a result of the various changeovers which have just taken place, the circuits C3, C10, C26 and C4 become conductive, while the circuits C2, C9 and C7 become nonconductive. In addition, a positive voltage is set up at the output of the circuits E21 and E15. If the flip-flop BPC is not in the state "1," the circuit C30 is conductive. Consequently, the pulse which, as has been seen in the foregoing, is applied to the input of C30 is transmitted by this circuit and applied to the gate 43, whereby the transfer of the "end of normal operation" code order contained in the stage MOR-5 to the register EVCQ is initiated. Thereafter, the delayed pulses which appear at the outputs of R12, R7 and R2 are sent to the circuits C11, C14, C21 and C22, which block them because they are not conductive. Finally, the change of the flip-flop BOL to "1" results in the appearance of a positive voltage, or long signal, at the conductor OR-1.

The operations which take place from this instant are identical to those which take place towards the end of the operation relating to the positioning of the tape and which have already been described. Without entering into details, it will simply be indicated that, in response to the reception of the long signal, the member DSG sends a pulse which initiates the changeover of the flip-flop BGX to "0." The pulse which emanates from GI-4 and is then transmitted by C58 is sent to R41 and R42. The delayed pulse which then appears at the output of R41 is sent to XREP-1.

This pulse is transmitted by C3 and produces the transfer of the "of normal operation" code order contained in the register EVCQ to the register RVCQ. This same pulse returns the flip-flop BOL to "0" and the flip-flop BST to "1," thereby rendering C2 conductive and C3 and C4 nonconductive. The delayed pulse which is set up at the output of R5 returns the register EVCQ to zero. The delayed pulse which appears at the output of R6 is blocked by C6.

The delayed pulse which appears at the output of R42 is applied to the input of R43 and to the gate 21, thus triggering the transfer of the "end of normal operation" code order contained in RVCQ to the register RCO. As a result of this transfer, the output SFN is brought to a positive potential and the circuit C47 is the only one to be rendered conductive. The delayed pulse which appears at the output of R43 is then transmitted by C47, which sends it to the circuits C88 and C89. Since C88 is conductive, this pulse is transmitted by this circuit, which sends it to the registers RNB and RCO to return them to zero, to the circuits C101 and C111 and to the buffer L46. If all the flip-flops BA-1 to BA-7 are at "0," the pulse sent to the circuits C101 and C111 is finally transmitted by C117 and then by C59, which then sends it to the control unit UCA in order to inform it that all the peripheral elements are available. Finally, the pulse which is sent to the buffer L46 serves to initiate the processing of another peripheral instruction by a procedure similar to that just described.

ISOLATION OF THE MAGNETIC TAPE UNITS

There will now be described the manner in which the isolation of a peripheral element is effected. By way of example, it will be assumed that the operator wishes to isolate all the magnetic tape units which, it will be recalled, are connected to the central unit through the functional connecting system BLF-1. This isolation is brought about by the operator depressing the pushbutton OF shown in FIG. 3E. Under these conditions, as has been seen in the foregoing, a pulse is sent by the differentiating amplifier AD-1 and applied to the normal input of the flip-flop BPD, which then changes to "1." If the pushbutton OF is depressed at an instant when the trigger BMT is at "0" and the register RVDQ and the instruction register RDR are simultaneously empty, a positive voltage is set up at the output of the circuit E16 and renders the circuit C24 conductive. Under these conditions, the circuit C24 transmits a pulse sent by the pulse generator GI-2 and applies it on the one hand to the complementary input of the flip-flop BPD, which then returns to "0" and again renders C24 nonconductive, and on the other hand to the normal input of the flip-flop BPC, which then changes to "1." thus rendering the circuit C25 conductive and the circuit C30 nonconductive. The pulse transmitted by the circuit C24 is also applied to the gate 41, whereby the transfer of the "end of incident operation" code order permanently contained in the stage MOR-6 of the order memory to the register EVCQ is initiated. The pulse transmitted by the circuit C24 is in addition applied, through L16 and L8 to the complementary input of the flip-flop BST, which then changes to "0," thereby rendering C3 conductive and C2 nonconductive, and through L16 and L9 to the normal input of the flip-flop BOL, which then changes to "1," thereby rendering C4 conductive. As a result of this last changeover, a long signal appears at the conductor OR-1. However, it may happen that, as a result of the operator depressing the button OF, the circuit C30 is rendered nonconductive until a pulse emanating from the circuit C9 has been transmitted. In this case, as has been seen, the "end of normal operation" code order is transferred into the register EVCQ but shortly afterwards the circuit C24 becomes conductive and the "end of incident operation" code order is therefore transferred in turn into the register EVCQ, while the latter has not been returned to zero. However, it will be assumed that the coding of the code orders has been so chosen that when the "end of normal operation" code order is sent into the register EVCQ which already contains the "end of normal operation" code order, the coded character which, by superimposition of the coded combinations corresponding to these two code orders, is written in the register EVCQ corresponds precisely to the "end of incident operation" code order. Finally, it is to be noted that in this case the transfer of the "end of incident operation" code order is terminated at the instant when a pulse sent by the central unit in response to a long signal is applied to the gated inputs of the circuits C2 and C3. It must in fact be pointed out that the positioning of the flip-flop BST at "0" and the positioning of the flip-flop BOL at "1" may be obtained either by transmission of a pulse by the circuit C9 or by transmission of a pulse by the circuit C24.

In response to the reception of the long signal, which appears at the conductor OR-1, as indicated in the foregoing, the member DSG sends a pulse to the circuits C51 and C61.

If the register RNB is empty or contains a character NB specifying that the functional connecting system concerned is other than the system BLF-1, the circuit C61 is nonconductive, while the circuit C51 is conductive. Under these conditions, the pulse emanating from the member DSG is transmitted by C51 and applied to the normal input of the flip-flop BA-1 which then changes to "1" and renders the circuit C101 conductive and the circuit C111 nonconductive. Thereafter, nothing happens until a pulse is applied to one of the inputs of the buffer L45. As has already been seen, this pulse may be sent by the differentiating amplifier AD-3 after depression of the button MM, or by the control unit UCA through the conductor ITB, or again by the circuit C50 through the buffer L47, or again by the differentiating amplifier AD-4 or the circuit C88, through the buffer L52. As will hereinafter be seen, this pulse may also emanate from the output of the circuit C45 or from the output of a delay element R48 which will hereinafter be referred to. This pulse, which is transmitted by the buffer L45 regardless of its origin, is applied to the gated inputs of the circuits C101 and C111. In the case under consideration, it is transmitted by the circuit C101 and sent on the one hand to the register RNB to position it in such manner that it contains a coded combination which has the effect, in the present case, of bringing the output K1 of the register RNB to a positive potential. Under these conditions, of all the circuits C71 to C77, only the circuit C71 is rendered conductive. The pulse transmitted by C101 is also sent through a buffer L57 to the complementary input of the flip-flop BMA, which then changes to "0," thereby rendering C60 conductive and C59 nonconductive. This same pulse is also sent through buffers L57 and L48 to the input of the delay element R41. Finally, this same pulse, transmitted by L57, is applied on the one hand to the input of a delay element R49, which will hereinafter be referred to, and on the other hand through the buffer L51 to the gate 25, whereby the transfer of the code-response character contained in the stage RPU-2 of the register RPU to the register EVDQ is initiated. When this transfer has been completed, a delayed pulse is set up at the output of R41 and is applied through L41 to the gated inputs of the circuits C71 to C77. Since only the circuit C71 is conductive, this pulse is transmitted by this circuit and applied to the conductor XREP-1. In addition, the pulse transmitted by C71 is applied to the complementary input of the flip-flop BA-1, which thus returns to "0," again rendering C111 conductive and C101 nonconductive.

The pulse sent to the conductor XREP-1 is then transmitted by the circuit C3, which applies it to the gate 51, thereby initiating the transfer of the "end of incident operation" code order contained in the register EVCQ to the register RVCQ. The pulse transmitted by C3 is in addition applied to the input of the delay element R5 and to the gated inputs of the circuits C4 and C29, which are conductive. The pulse transmitted by C4 is applied to the complementary input of the flip-flop BOL, which returns to "0," thereby again rendering C4 nonconductive. The pulse transmitted by C29 is applied to the normal input of the flip-flop BST, which then changes to "1," thus rendering C2 conductive and C3 nonconductive. The delayed pulse which is then set up at the output of R5 is sent on the one hand to the register EVCQ in order to return it to zero and on the other hand to the input of the delay element R6. The delayed pulse which is thereafter set up at the output of R6 is sent to the circuit C6, which blocks it.

At this instant, there is set up at the output of the delay element R49 a delayed pulse, which is applied on the one hand through the buffer L48 to the input of the delay element R41 and on the other hand through the buffer L50 to the gate 21, which initiates the transfer of the "end of incident operation" code order contained in the register RVCQ to the register RCO. Consequently, a positive voltage appears at the output SFI. Of all the circuits C40 to C48, only the circuits C46 and C48 are thus rendered conductive. When the transfer just referred to has been completed, a delayed pulse is set up at the output of the delay element R41. This pulse is then transmitted by L41 and C71 and applied to the conductor XREP-1.

The pulse thus applied to XREP-1 is now transmitted by C2 and applied on the one hand to the input of the delay element R1 and on the other hand, through C26, to the gate 44, whereby the transfer of the code-response character contained in EVDQ to the register RVDQ is initiated. Consequently, the output X3 of the decoder DKR is brought to a positive potential and C28 is rendered conductive. The delayed pulse which is thereafter set up at the output of R1 is applied to the gated inputs of the circuits C6, C9, C10, C23, C27, C28, C7 and C8, as also to the inputs of the delay elements R12, R7 and R2. Of all these circuits, only the circuits C10 and C28 are conductive. The pulse transmitted by C10 is applied to the input of the delay element R3. The pulse transmitted by C28 is applied to the normal input of the flip-flop BRP, which then changes to "1," whereby the circuits C13 and C17 to C20 are rendered nonconductive. The delayed pulses which are set up at the outputs of R12, R7 and R2 are applied to the inputs of the circuits C11, C14, C21 and C22, which block them because they are nonconductive. However, owing to the fact that the register RDR is empty and the flip-flop BOL is at "0," a positive voltage is present at the output of E5, whereby C12 is rendered conductive. Under these conditions, the delayed pulse which is set up at the output of R3 and which is sent to the circuits C12, C13 and C17 to C20 is transmitted only by the circuit C12, which applies it to the normal input of the flip-flop BOC. Consequently, as already explained, a short signal is sent to the conductor OR-1.

In response to the reception of this signal, the member DSG sends a pulse to the circuits C40 to C46. This pulse is transmitted only by the circuit C46, which applies it on the one hand to the input of the delay element R48 and on the other hand to the gated inputs of the circuits C91 to C97 (FIG. 2F). Since only the output K1 of the register RNB is at a positive potential and consequently only the circuit C91 is conductive, this pulse is transmitted by the circuit C91, which applies it to the complementary input of the flip-flop BD-1. The latter then changes to "0" and the positive voltage which is then set up at the complementary output informs the control unit UCA that all the magnetic tape units are then available. This positive voltage may also be applied to signalling means of known type, such as lamps, for example, in order to inform the operator that it is now possible for him to proceed with a manual operation concerning the magnetic tape units, such as the replacement of a type, for example. If he so wishes, the operator may even disconnect the plugs BE and BS by which the gates 44 and 51 are connected to the transfer channels, as also the conductors OR-1 and XREP-1 which lead to the bars BA and BD, without interfering with the transfers of data which may take place between the central unit and the other peripheral elements.

It is also to be noted that the delayed pulse which is set up at the output of R48 is sent to the buffer L45 to test the state of the other flip-flops BA-2 to BA-7. If one of these flip-flops is at "1," a procedure similar to that just described is initiated and repeated until the instant when all the flip-flops BA-1 to BA-7 are at "0." Under these conditions, the pulse transmitted by the buffer L45 is successively transmitted by the circuits C111 to C117. The pulse which is finally transmitted by C117 is sent to the circuits C59 and C60. Since the flip-flop BMA is now at "0," this pulse is transmitted by the circuit C60 and applied to the normal input of the flip-flop BMA, which thus returns to "1." The pulse transmitted by C60 is in addition sent to the control unit UCA and then constitutes a signal authorizing the resumption of any program which may have been interrupted owing to the unavailability of a peripheral element, this element now having become available.

It must now be pointed out that if a magnetic tape unit has completed an operation which was required of it and if, as a result of depression of the button OF, the code order which was sent to the register EVCQ is the "end of incident operation" code order instead of the "end of normal operation" code order, the procedure which then takes place is substantially the same as that which has just been described, except that the pulse which is sent by the member DSG in response to the reception of a long signal is now transmitted by C61 instead of C51, since the register RNB contains the character NB which specifies that the connecting system concerned is BLF-1. This pulse then triggers the changeover of the flip-flop BGX and consequently a pulse emitted by GI-4 is on the one hand sent to the conductor XREP-1 through L48, R41, L41 and C71, and on the other hand applied to the input of R42.

The main effect of the pulse sent to XREP-1 is to trigger the transfer of the "end of incident operation" code order contained in the register EVCQ to the register RVCQ. The delayed pulse which is then set up at the output of R42 is on the one hand applied to the input of R43 and on the other hand sent to the gate 21 to trigger the transfer of this code order to the register RCO. Consequently, the output SFI is brought to a positive potential and only the circuits C46 and C48 are conductive. The delayed pulse which is then set up at the output of R43 is transmitted by C48 which on the other hand sends it to the gate 25 to trigger the transfer of the code-response character to the register EVDQ, and on the other hand sends it to the conductor XREP-1.

The main effect of the pulse sent to XREP-1 is to trigger the transfer of the code response to the register RVDQ and the changeover of the flip-flop BRP to "1." A short signal is then sent to the conductor OR-1.

In response to the reception of this signal, the member DSG sends a pulse which is transmitted by the circuit C46. The pulse transmitted by C46 is applied on the one hand to the input of R48 and on the other hand to the inputs of C91 and C97. This pulse is then transmitted by C91 and applied to the complementary input of the flip-flop BD-1, which then changes to "0." The delayed pulse which is then set up at the output of R48 is sent to the buffer L45 to test the state of the other flip-flops BA-2 to BA-7.

RETURN INTO CIRCUIT OF THE MAGNETIC TAPE UNITS

As has just been seen, the isolation of all the magnetic tape units, initiated by the operator depressing the button OF, has resulted in the changeover of the flip-flop to the state "1." If the operator now desires to return into circuit the magnetic tape units, it is sufficient for him to depress the bottom ON. Under these conditions, a pulse a sent by the differentiating amplifier AD-2 and applied to the gated input of the circuit C25, which in this instance is conductive, since the flip-flop BPC is at "1." The pulse transmitted by the circuit C25 is applied on the one hand to the complementary input of the flip-flop BPC, which returns to "0," thereby rendering the circuit C25 nonconductive, and on the other hand to the gate 42, whereby the transfer of the "call" code order contained in the stage MOR-7 of the order memory to the register EVCQ is initiated. The pulse transmitted by C25 is also applied to the normal input of the flip-flop BRC, which then changes to "1" and renders the circuit C35 conductive. The pulse transmitted by C25 is in addition sent to the register RDR through L14 in order to return this register to zero if the latter is not already at zero. This pulse is also applied through L17 to the complementary input of the flip-flop BFF, which then changes to "0" or remains at zero if it is already in this state, and through L11 to the register RVDQ in order to return it to zero. This same pulse is applied through L11 and L12 to the complementary input of the flip-flop BRP, which then returns to "0." The pulse transmitted by C25 is in addition transmitted by the buffer L15, which applies it on the one hand to the complementary input of the flip-flop BES, which changes to "0" or remains at zero if it is already in this state, and on the other hand to the complementary input of the flip-flop BMT in order to return it to "0" if it is not already in this state. The pulse transmitted by C25 is finally transmitted by the buffer L16, which applies it on the one hand through L8 to the complementary input of the flip-flop BST, which is thus brought to "0" and renders C3 conductive and C2 nonconductive, and on the other hand through L9 to the normal input of the flip-flop BOL, which then changes to "1," thus rendering C4 conductive. Simultaneously, a long signal appears at the conductor OR-1. Under these conditions, the circuits C6, C9, C11, C14, C21, C22, C23, C27, C28, C7, C8 and C13 are not conductive, while the circuit C10 is conductive.

In response to the reception of the long signal which appears at the conductor OR-1, the member DSG sends a pulse to the circuits C51 and C61. It is to be noted here that known means (not described) are provided to prevent a pulse transmitted by the circuit C25 from being sent to the gate 42 and the buffers L16, L14, L17, L11 and L15, owing to depression of the button OF, immediately after the circuit C25 has been rendered conductive owing to depression of the button ON. By these means, which in the described example may consist, for example of a delay element of appropriate value disposed at the output of the circuit C25, the "call" code order can be sent to the register EVCQ only after the value contained in the register RNB and relating to the connecting system BLF-1 has been changed. Under these conditions, at the instant when the member DSG sends a pulse to the circuits C51 and C61, the flip-flop BD-1 is at "0," the output K1 of the register RNB is no longer at positive potential and the flip-flop BA-1 is at "0," this return to "0" having been triggered by the dispatch of a pulse transmitted by the circuit C71. Consequently, the circuit C51 is now conductive and the circuit C61 is nonconductive. The pulse then sent by the member DSG is therefore transmitted by the circuit C51, which applies it to the normal input of the flip-flop BA-1. The latter then changes to "1" and thus renders C101 conductive and C111 nonconductive. Thereafter, nothing happens until a pulse is applied to the input of the buffer L45, which pulse may emanate, as already stated with reference to the operation of isolating the magnetic tape units, from the differentiating amplifier AD-3 or from the control unit UCA, or from the circuit C50, or from the differentiating amplifier AD-4, or from the circuit C88, or from the circuit C45, or finally from the delay element R48. This pulse, regardless of its origin, initiates a procedure substantially similar to that which has been described with reference to the isolating operation, except that the first pulse received by the local control unit in response to the emission of a long signal, and transmitted by the circuits C3 and C4, is not only applied to the complementary input of the flip-flop BOL, which then returns to "0," but is in addition transmitted by the circuit C35, which is now conductive. The pulse transmitted by the circuit C35 is applied on the one hand to the complementary input of the flip-flop BRC, which then returns to "0," thus again rendering C35 nonconductive, and on the other hand to the input of a delay element R15, which will hereinafter be referred to. In addition, the code order which is now transferred from the register EVCQ, first into the register RVCQ and then into the register RCO, is now the "call" code order. Under these conditions, the output of RCO which is now brought to positive potential is the output SAP. Consequently, of all the circuits C40 to C48, only the circuits C45 and C48 are rendered conductive. However, from the instant when, in response to the reception of a short signal, the member DSG sends a pulse to the circuits C40 to C46, this pulse is transmitted only by the circuit C45. It is then sent on the one hand to the gated inputs of the circuits C81 to C87 and on the other hand to the buffers L54 and L45. It is then transmitted by C81 and applied to the normal input of the flip-flop BD-1, which this returns to the state "1," thereby informing the control unit UCA that all the magnetic tape units are again available. The pulse transmitted by L54 and L45 serves to test the state of the other flip-flops BA-2 to BA-7. It is now to be noted that the delay of the delay element R15 is such that, immediately after the last short signal has been sent to the central control unit, a delayed pulse appears at the output of this delay element R15. This delayed pulse, transmitted by the buffer L11, is on the one hand sent to the register RVDQ to return it to zero, and on the other hand applied to the complementary input of the flip-flop BRP, which then returns to "0." Under these conditions, the final state of the elements constituting the local control unit is identical to the initial state.

It is to be noted that the examples of operation which have been described in the foregoing have been given to illustrate the case concerning the positioning of the information-recording medium of a peripheral element and the forward reading of the data recorded on this medium. However, the equipment which is illustrated in FIGS. 3A to 3H may also be employed in other cases which have not been described in order not further to lengthen the description and which relate either to the backward reading of the data written on the recording medium or to the writing of fresh data on the latter.

Finally, it is to be pointed out that the functional connecting system which has been described in the foregoing has been so chosen as to have a sufficiently developed structure to cover all cases of application which can at present be envisaged. However, the functional connecting systems by which less complex peripheral elements such as, for example, card readers may be connected to the central unit are of simpler construction than that which have been described and their construction may be based on that illustrated in the accompanying drawings and may comprise only the switching circuits essential for performing the particular functions for which these elements are designed.

Although the essential features of the invention have been described in the foregoing and illustrated in the accompanying drawings, it is obvious that the person skilled in the art may make therein any modifications of form and detail which may be considered necessary, without departing from the scope of the invention.