This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2006-294392, filed on Oct. 30, 2006, the entire contents of which are incorporated herein by reference.
1. Field
The embodiment relates to a power supply circuit, a power supply control circuit, and a power supply control method.
2. Description of the Related Art
Recently, a memory card has become wide-spread as a data recording medium of portable electronic equipment (digital camera, mobile phone, etc.). The operation voltage of a memory card is determined in accordance with the operation voltage of a non-volatile memory (flash memory etc.) mounted on the memory card. For example, there exist a non-volatile memory with the operation voltage of 3.3 V and one with that of 1.8 V. Consequently, there also exist a memory card with the operation voltage of 3.3 V and one with that of 1.8 V.
In order to make the operation voltage of a memory card independent from that of an internal non-volatile memory, it is required to mount a DC-DC converter on the memory card. It is necessary for the memory card to mount, in addition to a non-volatile memory, a logic circuit for controlling the non-volatile memory. However, it is inefficient to mount two kinds of logic circuits (a logic circuit for 3.3 V and that for 1.8 V) on a memory card in accordance with the operation voltage of the non-volatile memory and when the fact that the voltage of a semiconductor device constituting a logic circuit is fixed accompanying the reduction in size thereof is considered, it is desirable to mount only the logic circuit for 1.8 V on the memory card. However, it is required to mount both the DC-DC converter for the logic circuit and that for the non-volatile memory on the memory card. By the way, techniques relating to a DC-DC converter are disclosed in Japanese Unexamined Patent Application Publication No. Hei 7-21791, Japanese Unexamined Patent Application Publication No. Hei 9-154275, Japanese Unexamined Patent Application Publication No. Hei 9-294368, etc.
It is possible to realize the independence of the operation voltage of the memory card from that of the internal non-volatile memory by mounting a DC-DC converter on the memory, however, it is very inefficient only to mount simply two or more DC-DC converters on the memory card. In addition, since the memory card is inserted/removed into/from electronic equipment in an activated state, when a voltage required inside the memory card is generated by a boost DC-DC converter, there arises a problem that the input voltage flows through to the output side when the memory card is inserted into the electronic equipment, causing an inrush current. Further, if the rising timing of the power supply voltage of the non-volatile memory and the power supply voltage of the logic circuit is not considered, there is the possibility of the risk of burn-out caused by latch-up of the semiconductor device constituting the non-volatile memory or the logic circuit.
The embodiment provides that a power supply circuit including an input pin receiving a voltage of either a first predetermined value or a second predetermined value smaller than the first predetermined value, a first output pin for which an output of a voltage of either the first or second predetermined value is required, a second output pin for which an output of a voltage of the second predetermined value is required, a DC-DC converter generating an output voltage from the voltage of the input pin in either a step-down mode or a boost mode and outputting the output voltage to at least one of the first and second output pins in accordance with a combination of the voltage value of the input pin and the voltage value required for the first output pin, a first bypass switch circuit turning on to output the voltage of the input pin to the first output pin when the voltage is not output to the first output pin from the DC-DC converter, a second bypass switch circuit turning on to output the voltage of the input pin to the second output pin when the voltage is not output to the second output pin from the DC-DC converter, a start control circuit causing the DC-DC converter to operate in the step-down mode irrespective of the combination of the voltage value of the input pin and the voltage value required for the first output pin during the period from when the DC-DC converter is started until the output voltage of the DC-DC converter becomes equal to the voltage of the input pin, and an output slope control circuit synchronizing a rising slope of the output voltage of the first bypass switch circuit with a rising slope of the output voltage of the DC-DC converter when the first bypass switch circuit turns on and synchronizes a rising slope of the output voltage of the second bypass switch circuit with a rising slope of the output voltage of the DC-DC converter when the second bypass switch circuit turns on.
The nature, principle, and utility of the embodiment will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:
FIG. 1 is an explanatory diagram showing an embodiment;
FIG. 2 is an explanatory diagram showing a configuration of a power supply circuit;
FIG. 3 is an explanatory diagram showing an operation of a decoder;
FIG. 4 is an explanatory diagram showing an operation (first mode) of the power supply circuit;
FIG. 5 is an explanatory diagram showing an operation (first mode) of a step-down PWM comparator and a boost PWM comparator;
FIG. 6 is an explanatory diagram showing rising characteristics (first mode) of a second output voltage;
FIG. 7 is an explanatory diagram showing an operation (second mode) of the power supply circuit;
FIG. 8 is an explanatory diagram showing an operation (third mode) of the power supply circuit;
FIG. 9 is an explanatory diagram showing an operation (third mode) of the step-down PWM comparator and the boost PWM comparator;
FIG. 10 is an explanatory diagram showing rising characteristics (third mode, without soft-start control) of a first output voltage;
FIG. 11 is an explanatory diagram showing an operation (third mode) of the step-down PWM comparator and the boost PWM comparator at the time of start of a DC-DC converter;
FIG. 12 is an explanatory diagram showing rising characteristics (third mode, with soft-start control) of the first output voltage;
FIG. 13 is an explanatory diagram showing an operation (fourth mode) of the power supply circuit;
FIG. 14 is an explanatory diagram showing a configuration of the decoder;
FIG. 15 is an explanatory diagram showing a configuration of an output slope control circuit; and
FIG. 16 is an explanatory diagram showing how the first and the second output voltages are activated simultaneously.
An embodiment will be described below with reference to drawings. FIG. 1 shows an embodiment. A memory card 1 to which the embodiment has been applied is configured so as to include a power supply circuit 2 , a non-volatile memory 3 , and a memory card control circuit 4 . For example, the power supply circuit 2 , the non-volatile memory 3 , and the memory card control circuit 4 are configured by separate semiconductor devices and are coupled to one another on a printed-circuit board. The power supply circuit 2 generates a first output voltage Vo 1 (3.3 V or 1.8 V) and a second output voltage Vo 2 (1.8 V) from an input voltage Vi (3.3 V or 1.8 V). The non-volatile memory 3 uses the first output voltage Vo 1 of the power supply circuit 2 as a power supply voltage. The memory card control circuit 4 uses the second output voltage Vo 2 of the power supply circuit 2 as a power supply voltage. However, in the memory card control circuit 4 , an external interface circuit 4 a (a circuit that transmits and receives an address signal and a data signal to and from the outside) uses the input voltage Vi as a power supply voltage and a memory interface circuit 4 b (a circuit that transmits and receives an address signal and a data signal to and from the non-volatile memory 3 ) uses the first output voltage Vo 1 of the power supply circuit 2 as a power supply voltage.
FIG. 2 shows the configuration of the power supply circuit 2 . The power supply circuit 2 is configured so as to include a first bypass switch circuit T 6 , a second bypass switch circuit T 7 , a first smoothing capacitor C 1 , a second smoothing capacitor C 2 , and a DC-DC converter CNV. The first bypass switch circuit T 6 is provided in order to output the input voltage Vi (the voltage of an input pin IN of the power supply circuit 2 ) as the first output voltage Vo 1 (the voltage of a first output pin OUT 1 of the power supply circuit 2 ) and configured by an n-type transistor. The input pin of the first bypass switch circuit T 6 is coupled to the input pin IN of the power supply circuit 2 . The output pin of the first bypass switch circuit T 6 is coupled to the first output pin OUT 1 of the power supply circuit 2 . A control pin of the first bypass switch circuit T 6 receives a control signal D 6 supplied from a decoder DEC of a control circuit CTL in the DC-DC converter CNV.
The second bypass switch circuit T 7 is provided in order to output the input voltage Vi as the second output voltage Vo 2 (the voltage of a second output pin OUT 2 of the power supply circuit 2 ) and is configured by a p-type transistor. The input pin of the second bypass switch circuit T 7 is coupled to the input pin IN of the power supply circuit 2 . The output pin of the second bypass switch circuit T 7 is coupled to the second output pin OUT 2 of the power supply circuit 2 . The control pin of the second bypass switch circuit T 7 receives a control signal D 7 supplied from the decoder DEC of the control circuit CTL in the DC-DC converter CNV. The first smoothing capacitor C 1 is provided in order to smooth the first output voltage Vo 1 and is coupled between the first output pin OUT 1 of the power supply circuit 2 and a ground line. The second smoothing capacitor C 2 is provided in order to smooth the second output voltage Vo 2 and is coupled between the second output pin OUT 2 of the power supply circuit 2 and a ground line.
The DC-DC converter CNV operates as either a step-down type DC-DC converter or a boost type DC-DC converter in accordance with a combination of the voltage value of the input voltage Vi and the voltage value (the voltage value of the first output voltage Vo 1 ) of the operation voltage of the non-volatile memory 3 . The DC-DC converter CNV is configured so as to include a step-down main switching transistor T 1 , a step-down synchronous commutator circuit T 2 , a choke coil L 1 , a boost main switching transistor T 3 , a boost synchronous commutator circuits T 4 and T 5 , a soft-start capacitor CS, a switch circuit SWM, and the control circuit CTL.
The step-down main switching transistor T 1 is configured by an n-type transistor. The input pin of the step-down main switching transistor T 1 is coupled to the input pin IN of the power supply circuit 2 . The output pin of the step-down main switching transistor T 1 is coupled to one pin of the choke coil L 1 . The control pin of the step-down main switching transistor T 1 receives a control signal D 1 supplied from the decoder DEC of the control circuit CTL. The step-down synchronous commutator circuit T 2 is configured by an n-type transistor. The input pin of the step-down synchronous commutator circuit T 2 is coupled to a ground line. The output pin of the step-down synchronous commutator circuit T 2 is coupled to one pin of the choke coil L 1 . The control pin of the step-down synchronous commutator circuit T 2 receives a control signal D 2 supplied from the decoder DEC of the control circuit CTL.
The boost main switching transistor T 3 is configured by an n-type transistor. The input pin of the boost main switching transistor T 3 is coupled to the other pin of the choke coil L 1 . The output pin of the boost main switching transistor T 3 is coupled to a ground line. The control pin of the boost main switching transistor T 3 receives a control signal D 3 supplied from the decoder DEC of the control circuit CTL. The boost synchronous commutator circuit T 4 is configured by an n-type transistor. The input pin of the boost synchronous commutator circuit T 4 is coupled to the other pin of the choke coil L 1 . The output pin of the boost synchronous commutator circuit T 4 is coupled to the first output pin OUT 1 of the power supply circuit 2 . The control pin of the boost synchronous commutator circuit T 4 receives a control signal D 4 supplied from the decoder DEC of the control circuit CTL. The boost synchronous commutator circuit T 5 is configured by an n-type transistor. The input pin of the boost synchronous commutator circuit T 5 is coupled to the other pin of the choke coil L 1 . The output pin of the boost synchronous commutator circuit T 5 is coupled to the second output pin OUT 2 of the power supply circuit 2 . The control pin of the boost synchronous commutator circuit T 5 receives a control signal D 5 supplied from the decoder DEC of the control circuit CTL.
One pin of the soft-start capacitor CS is coupled to, out of first and second non-inverting input pins of an error amplifier ERA 1 in the control circuit CTL, the second non-inverting input pin. The other pin of the soft-start capacitor CS is coupled to a ground line. The soft-start capacitor CS is charged gradually via a constant-current circuit (not shown) accompanying the start of the DC-DC converter CNV and is discharged gradually via a discharging resistor (not shown) accompanying the termination of the DC-DC converter CNV.
The switch circuit SWM is provided in order to generate a memory voltage request signal MEM indicative of which one is requested, 3.3 V or 1.8 V, as the operation voltage of the non-volatile memory 3 . The switch circuit SWM enters the off-state in order to set the memory voltage request signal MEM to a high level when 3.3 V is requested as the operation voltage of the non-volatile memory 3 . The switch circuit SWM enters the on-state in order to set the memory voltage request signal MEM to a low level when 1.8 V is requested as the operation voltage of the non-volatile memory 3 .
The control circuit CTL is configured so as to include resistors R 1 to R 6 , switch circuits SW 1 and SW 2 , voltage generators E 1 to E 4 , the error amplifier ERA 1 , a triangular wave oscillator OSC, a step-down PWM comparator PWM 1 , a boost PWM comparator PWM 2 , and the decoder DEC. One pin of the resistor R 1 is coupled to the first output pin OUT 1 of the power supply circuit 2 . The other pin of the resistor R 1 is coupled to one pin of the resistor R 2 . The other pin of the resistor R 2 is coupled to a ground line. One pin of the resistor R 3 is coupled to the second output pin OUT 2 of the power supply circuit 2 . The other pin of the resistor R 3 is coupled to one pin of the resistor R 4 . The other pin of the resistor R 4 is coupled to a ground line. The voltage generator E 1 generates a reference voltage Ve 1 . The voltage generator E 2 generates a reference voltage Ve 2 .
The switch circuit SW 1 couples the coupling node of the resistors R 1 and R 2 to the inverting input pin of the error amplifier ERA 1 when a control signal SWD 1 supplied from the decoder DEC indicates a high level, and couples the coupling node of the resistors R 3 and R 4 to the inverting input pin of the error amplifier ERA 1 when the control signal SWD 1 indicates a low level. The switch circuit SW 2 couples the output pin of the voltage generator E 1 to a first non-inverting input pin of the error amplifier ERA 1 when a control signal SWD 2 supplied from the decoder DEC indicates a high level, and couples the output pin of the voltage generator E 2 to the first non-inverting input pin of the error amplifier ERA 1 when the control signal SWD 2 indicates a low level.
The error amplifier ERA 1 receives a voltage supplied via the switch circuit SW 1 at the inverting input pin, receives a voltage supplied via the switch circuit SW 2 at the first non-inverting input pin, and receives a voltage generated by the soft-start capacitor CS at the second non-inverting input pin. The error amplifier ERA 1 generates an output signal DF 1 by amplifying the voltage difference between the voltage of the inverting input pin and the lower one of the voltage of the first non-inverting input pin and the voltage of the second non-inverting input pin. The triangular wave oscillator OSC generates a triangular wave signal TW having a predetermined period. The voltage generator E 3 generates an output signal DF 2 by subtracting an offset voltage Ve 3 from the voltage of the output signal DF 1 of the error amplifier ERA 1 . By the way, the offset voltage Ve 3 is set to the same voltage value as the wave-height value of the triangular wave signal TW supplied from the triangular wave oscillator OSC.
The step-down PWM comparator PWM 1 receives the output signal DF 1 of the error amplifier ERA 1 at the inverting input pin and receives the triangular wave signal TW supplied from the triangular wave oscillator OSC at the non-inverting input pin. The step-down PWM comparator PWM 1 sets an output signal Q 1 to a high level when the voltage of the output signal DF 1 of the error amplifier ERA 1 is higher than that of the triangular wave signal TW and sets an output signal /Q 1 to a low level. The step-down PWM comparator PWM 1 sets the output signal Q 1 to a low level when the voltage of the output signal DF 1 of the error amplifier ERA 1 is lower than that of the triangular wave signal TW and sets the output signal /Q 1 to a high level.
The boost PWM comparator PWM 2 receives the output signal DF 2 of the voltage generator E 3 at the inverting input pin and receives the triangular wave signal TW supplied from the triangular wave oscillator OSC at the non-inverting input pin. The boost PWM comparator PWM 2 sets an output signal Q 2 to a high level when the voltage of the output signal DF 2 of the voltage generator E 3 is higher than that of the triangular wave signal TW and sets an output signal /Q 2 to a low level. The boost PWM comparator PWM 2 sets the output signal Q 2 to a low level when the voltage of the output signal DF 2 of the voltage generator E 3 is lower than that of the triangular wave signal TW and sets the output signal /Q 2 to a high level.
One pin of the resistor R 5 is coupled to the input pin IN of the power supply circuit 2 . The other pin of the resistor R 5 is coupled to one pin of the resistor R 6 . The other pin of the resistor R 6 is coupled to a ground line. The voltage generator E 4 generates a reference voltage Ve 4 . A voltage comparator CMP is provided in order to determine whether the input voltage Vi is 3.3 V or 1.8 V. The voltage comparator CMP receives the voltage (the voltage of the input voltage Vi divided by the resistors R 5 and R 6 ) of the coupling node of the resistors R 5 and R 6 at the inverting input pin and receives the reference voltage Ve 4 supplied from the voltage generator E 4 at the non-inverting input pin. The voltage comparator CMP sets an output signal JDG to a high level when the voltage of the coupling node of the resistors R 5 and R 6 is higher than the reference voltage Ve 4 and sets the output signal JDG to a low level when the voltage of the coupling node of the resistors R 5 and R 6 is lower than the reference voltage Ve 4 . The decoder DEC generates the control signals SWD 1 , SWD 2 , and D 1 to D 7 based on the output signal JDG of the voltage comparator CMP, the memory voltage request signal MEM, the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 , and the output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 .
FIG. 3 shows the operation of the decoder DEC. When the output signal JDG of the voltage comparator CMP is set to a high level and the memory voltage request signal MEM generated by the switch circuit SWM is set to a high level (when 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ), the decoder DEC sets the control signals D 6 and D 7 to a high level as well as setting the control signals SWD 1 , SWD 2 , and D 4 to a low level. In addition, the decoder DEC outputs the output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 as the control signals D 3 and D 5 as well as outputting the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 as the control signals D 1 and D 2 .
When the output signal JDG of the voltage comparator CMP is set to a high level and the memory voltage request signal MEM generated by the switch circuit SWM is set to a low level (when 3.3 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 ), the decoder DEC sets the control signals SWD 2 and D 6 to a low level as well as setting the control signals SWD 1 and D 7 to a high level. In addition, the decoder DEC outputs the output signal Q 2 of the boost PWM comparator PWM 2 as the control signals D 3 and outputs the output signal /Q 2 of the boost PWM comparator PWM 2 as the control signals D 4 and D 5 as well as outputting the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 as the control signals D 1 and D 2 .
When the output signal JDG of the voltage comparator CMP is set to a low level and the memory voltage request signal MEM generated by the switch circuit SWM is set to a high level (when 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ), the decoder DEC sets the control signals D 5 , D 6 , and D 7 to a low level as well as setting the control signals SWD 1 and SWD 2 to a high level. In addition, the decoder DEC outputs the output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 as the control signals D 3 and D 4 as well as outputting the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 as the control signals D 1 and D 2 .
When the output signal JDG of the voltage comparator CMP is set to a low level and the memory voltage request signal MEM generated by the switch circuit SWM is set to a low level (when 1.8 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 ), the decoder DEC sets the control signals SWD 2 and D 6 to a low level as well as setting the control signals SWD 1 and D 7 to a high level. In addition, the decoder DEC outputs the output signal Q 2 of the boost PWM comparator PWM 2 as the control signal D 3 and outputs the output signal /Q 2 of the boost PWM comparator PWM 2 as the control signals D 4 and D 5 as well as outputting the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 as the control signals D 1 and D 2 .
Here, the operation of the power supply circuit 2 will be described separately by four cases: (first mode), 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ; (second mode), 3.3 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 ; (third mode), 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ; and (fourth mode), 1.8 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 .
FIG. 4 shows the operation (first mode) of the power supply circuit 2 . When 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the control signal D 4 is set to a low level and the control signal D 6 is set to a high level. Due to this, the boost synchronous commutator circuit T 4 is always in the off-state and the first bypass switch circuit T 6 is always in the on-state. Consequently, the input voltage Vi is output as the first output voltage Vo 1 . In addition, the control signal D 7 is fixed to a high level. Due to this, the second bypass switch circuit T 7 is always in the off-state.
The control signals SWD 1 and SWD 2 are set to a low level. Consequently, the switch circuit SW 1 couples the coupling node of the resistors R 3 and R 4 to the inverting input pin of the error amplifier ERA 1 and the switch circuit SW 2 couples the output pin of the voltage generator E 2 to the first non-inverting input pin of the error amplifier ERA 1 . Since the soft-start capacitor CS is charged by a constant-current circuit during the operation of the DC-DC converter CNV, the voltage of the second non-inverting input pin is higher than the voltage of the first non-inverting input pin at the error amplifier ERA 1 . Consequently, during the operation of the DC-DC converter CNV, the error amplifier ERA 1 generates the output signal DF 1 by amplifying the voltage difference between the voltage of the second output voltage Vo 2 divided by the resistors R 3 and R 4 and, the reference voltage Ve 2 .
The step-down PWM comparator PWM 1 sets the output signal /Q 1 to a low level as well as setting the output signal Q 1 to a high level when the voltage of the output signal DF 1 of the error amplifier ERA 1 is higher than the triangular wave signal TW supplied from the triangular wave oscillator OSC, and sets the output signal /Q 1 to a high level as well as setting the output signal Q 1 to a low level when the voltage of the output signal DF 1 of the error amplifier ERA 1 is lower than the triangular wave signal TW. The output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 are output as the control signals D 1 and D 2 .
The boost PWM comparator PWM 2 sets the output signal /Q 2 to a low level as well as setting the output signal Q 2 to a high level when the voltage (the voltage obtained by subtracting the offset voltage Ve 3 from the output voltage DF 1 of the error amplifier ERA 1 ) of the output signal DF 2 of the voltage generator E 3 is higher than the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC, and sets the output signal /Q 2 to a high level as well as setting the output signal Q 2 to a low level when the voltage of the output signal DF 2 of the voltage generator E 3 is lower than the voltage of the triangular wave signal TW. The output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 are output as the control signals D 3 and D 5 .
FIG. 5 shows the operation (first mode) of the step-down PWM comparator PWM 1 and the boost PWM comparator PWM 2 . When 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , since the voltage (the voltage of the output signal DF 2 of the voltage generator E 3 ) of the inverting input pin is always lower than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin at the boost PWM comparator PWM 2 , the output signal Q 2 is always set to a low level and the output signal /Q 2 is always set to a high level (a state of 0% duty). Since the output signal Q 2 of the boost PWM comparator PWM 2 is output as the control signal D 3 , the boost main switching transistor T 3 is always in the off-state. In addition, since the output signal /Q 2 of the boost PWM comparator PWM 2 is output as the control signal D 5 , the boost synchronous commutator circuit T 5 is always in the on-state.
On the other hand, at the step-down PWM comparator PWM 1 , when the voltage (the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the inverting input pin is higher than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 1 is set to a high level, and the output signal /Q 1 is set to a low level. Since the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 are output as the control signals D 1 and D 2 , when the voltage of the output signal DF 1 of the error amplifier ERA 1 is higher than the voltage of the triangular wave signal TW, the step-down main switching transistor T 1 enters the on-state, and the step-down synchronous commutator circuit T 2 enters the off-state.
At the step-down PWM comparator PWM 1 , when the voltage (the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the non-inverting input pin is lower than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 1 is set to a low level, and the output signal /Q 1 is set to a high level. Since the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 are output as the control signals D 1 and D 2 , when the voltage of the output signal DF 1 of the error amplifier ERA 1 is lower than the voltage of the triangular wave signal TW, the step-down main switching transistor T 1 enters the off-state, and the step-down synchronous commutator circuit T 2 enters the on-state.
When the step-down main switching transistor T 1 enters the on-state, the step-down synchronous commutator circuit T 2 enters the off-state and an electric current is supplied to a load from the input side via the choke coil L 1 . Since the voltage difference between the input voltage Vi and the second output voltage Vo 2 is applied across both ends of the choke coil L 1 , the current that flows through the choke coil L 1 increases as time elapses and the current supplied to the load also increases as time elapses. In addition, as the current flows through the choke coil L 1 , energy is accumulated in the choke coil L 1 . Then, when the step-down main switching transistor TI enters the off-state, the boost synchronous commutator circuit T 2 enters the on-state and the energy accumulated in the choke coil L 1 is discharged. At this time, the second output voltage Vo 2 is expressed by expression (1) using the input voltage Vi, an on-period Ton of the step-down main switching transistor T 1 , and an off-period Toff of the step-down main switching transistor T 1 .
Vo 2={ T on/( T on+ T off)}× Vi (1)
In addition, the current that flows through the choke coil L 1 flows from the input side to the output side during the on-period of the step-down main switching transistor T 1 and is supplied via the step-down synchronous commutator circuit T 2 during the off-period of the step-down main switching transistor T 1 . Consequently, an average input current Ii is expressed by expression (2) using an output current Io, the on-period Ton of the step-down main switching transistor T 1 , and the off-period Toff of the step-down main switching transistor T 1 .
Ii={T on/( T on+ T off)}× Io (2)
Consequently, when the second output voltage Vo 2 varies resulting from the variation of the input voltage Vi, it is possible to keep constant the second output voltage Vo 2 by detecting the variation of the second output voltage Vo 2 to control the ratio between on-period and off-period of the step-down main switching transistor T 1 . Similarly, when the second output voltage Vo 2 varies resulting from the variation of the load, it is also possible to keep constant the second output voltage Vo 2 by detecting the variation of the second output voltage Vo 2 to control the ratio between on-period and off-period of the step-down main switching transistor T 1 . In this manner, in the DC-DC converter CNV of PWM control system, it is possible to control the second output voltage Vo 2 by controlling the ratio between on-period and off-period of the step-down main switching transistor T 1 .
By the way, at the time of start of the DC-DC converter CNV, the second output voltage Vo 2 is 0 V, and therefore, the voltage difference between the input voltage Vi and the second output voltage Vo 2 becomes maximum and if it is assumed that the voltage of the first non-inverting input pin is lower than the voltage of the second non-inverting input pin at the error amplifier ERA 1 , the voltage of the output signal DF 1 of the error amplifier ERA 1 also becomes maximum. In this case, the pulse width (period of high level) of the output signal Q 1 of the step-down PWM comparator becomes maximum and the on-period of the step-down main switching transistor T 1 becomes maximum. In addition, a maximum current Ipeak that flows through the choke coil L 1 is expressed by expression (3) using the input voltage Vi, the second output voltage Vo 2 , an inductance L of the choke coil L 1 , and the on-period Ton of the step-down main switching transistor T 1 .
I peak={( Vi−Vo 2)/ L}×T on (3)
At the time of start of the DC-DC converter CNV, the second output voltage Vo 2 is 0 V, and therefore, the voltage to be applied to the choke coil L 1 becomes maximum and the on-period of the step-down main switching transistor T 1 becomes maximum. Thus, it is known that an excessive inrush current occurs in the choke coil L 1 and the step-down main switching transistor T 1 . This occurs because the DC-DC converter CNV attempts to raise second output voltage Vo 2 from 0 V to a rated value (1.8 V) at a burst.
However, at the time of start of the DC-DC converter CNV, the soft-start capacitor CS is charged gradually by the constant-current circuit, and thereby, the voltage (the voltage of the second non-inverting input pin of the error amplifier ERA 1 ) generated by the soft-start capacitor CS rises gradually from 0 V. Consequently, at the time of start of the DC-DC converter CNV, the error amplifier ERA 1 generates the output signal DF 1 by amplifying the voltage difference between the voltage of the second output voltage Vo 2 divided by the resistors R 3 and R 4 and the voltage generated by the soft-start capacitor CS. At the time of start of the DC-DC converter CNV, since the second output voltage Vo 2 is 0 V, the voltage of the output signal DF 1 of the error amplifier ERA 1 becomes minimum and the pulse width of the output signal Q 1 of the step-down PWM comparator PWM 1 also becomes minimum. Because of this, the on-period of the step-down main switching transistor T 1 becomes minimum and the inrush current is prevented.
In addition, the voltage generated by the soft-start capacitor CS is a voltage that defines the second output voltage Vo 2 and rises gradually with a predetermined rising slope. Because of this, the second output voltage Vo 2 also rises in proportion thereto. Consequently, the rising slope of the second output voltage Vo 2 is defined by the rising slope of the voltage generated by the soft-start capacitor CS. When the voltage generated by the soft-start capacitor CS rises and becomes higher than the reference voltage Ve 2 , the error amplifier ERA 1 generates the output voltage DF 1 by amplifying the voltage difference between the voltage of the second output voltage Vo 2 divided by the resistors R 3 and R 4 and the reference voltage Ve 2 . Consequently, after the voltage generated by the soft-start capacitor CS has reached the reference voltage Ve 2 , the second output voltage Vo 2 is defined by the reference voltage Ve 2 . By the way, at the time of termination of the DC-DC converter CNV, the soft-start capacitor CS is discharged gradually by a discharging resistor and the voltage generated by the soft-start capacitor CS drops gradually, and therefore, it is possible to reduce the second output voltage Vo 2 gradually.
FIG. 6 shows the rising characteristics (first mode) of the second output voltage Vo 2 . At time t 1 , when the DC-DC converter CNV is started, the soft-start capacitor CS is charged gradually by the constant-current circuit. Due to this, the voltage generated by the soft-start capacitor CS rises as time elapses. Accompanying this, the second output voltage Vo 2 also rises as time elapses. At time t 2 , when the voltage generated by the soft-start capacitor CS has reached the reference voltage Ve 2 , the second output voltage Vo 2 is controlled to keep constant by the reference voltage Ve 2 thereafter.
FIG. 7 shows the operation (second mode) of the power supply circuit 2 . When 3.3 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 , the control signal D 6 is set to a low level. Due to this, the first bypass switch circuit T 6 is always in the off-state. In addition, the control signal SWD 1 is set to a high level. Due to this, the switch circuit SW 1 couples the coupling node of the resistors R 1 and R 2 to the inverting input pin of the error amplifier ERA 1 . The output signal /Q 2 of the boost PWM comparator PWM 2 is not only output as the control signal D 5 but also output as the control signal D 4 . Since the operation other than this is the same as that in the first mode of the power supply circuit 2 , duplicated description will be omitted here.
FIG. 8 shows the operation (third mode) of the power supply circuit 2 . When 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the control signals D 5 and D 7 are set to a low level. Due to this, the boost synchronous commutator circuit T 5 is always in the off-state and the second bypass switch circuit T 7 is always in the on-state. Consequently, the input voltage Vi is output as the second output voltage Vo 2 . In addition, the control signal D 6 is set to a low level. Due to this, the first bypass switch circuit T 6 is always in the off-state.
The control signals SWD 1 and SWD 2 are set to a high level. Consequently, the switch circuit SW 1 couples the coupling node of the resistors R 1 and R 2 to the inverting input pin of the error amplifier ERA 1 and the switch circuit SW 2 couples the output pin of the voltage generator E 1 to the first non-inverting input pin of the error amplifier ERA 1 . Since the soft-start capacitor CS is charged by the constant-current circuit during the operation of the DC-DC converter CNV, the voltage of the second non-inverting input pin is higher than the voltage of the first non-inverting input pin at the error amplifier ERA 1 . Consequently, the error amplifier ERA 1 generates the output signal DF 1 by amplifying the voltage difference between the voltage of the first output voltage Vo 1 divided by the resistors R 1 and R 2 and the reference voltage Ve 1 .
The step-down PWM comparator PWM 1 sets the output signal /Q 1 to a low level as well as setting the output signal Q 1 to a high level when the voltage of the output signal DF 1 of the error amplifier ERA 1 is higher than the triangular wave signal TW supplied from the triangular wave oscillator OSC, and sets the output signal /Q 1 to a high level as well as setting the output signal Q 1 to a low level when the voltage of the output signal DF 1 of the error amplifier ERA 1 is lower than the voltage of the triangular wave signal TW. The output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 are output as the control signals D 1 and D 2 .
The boost PWM comparator PWM 2 sets the output signal /Q 2 to a low level as well as setting the output signal Q 2 to a high level when the voltage (the voltage obtained by subtracting the offset voltage Ve 3 from the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the output signal DF 2 of the voltage generator E 3 is higher than the triangular wave signal TW supplied from the triangular wave oscillator OSC, and sets the output signal /Q 2 to a high level as well as setting the output signal Q 2 to a low level when the voltage of the output signal DF 2 of the voltage generator E 3 is lower than the voltage of the triangular wave signal TW. The output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 are output as the control signals D 3 and D 4 .
FIG. 9 shows the operation (third mode) of the step-down PWM comparator PWM 1 and the boost PWM comparator PWM 2 . When 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , since the voltage (the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the inverting input pin is always higher than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin at the step-down PWM comparator PWM 1 , the output signal Q 1 is always set to a high level and the output signal /Q 1 is always set to a low level (a state of 100% duty). Since the output signal Q 1 of the step-down PWM comparator PWM 1 is output as the control signal D 1 , the step-down main switching transistor T 1 is always in the on-state. In addition, since the output signal /Q 1 of the step-down PWM comparator PWM 1 is output as the control signal D 2 , the step-down synchronous commutator circuit T 2 is always in the off-state.
On the other hand, at the boost PWM comparator PWM 2 , when the voltage (the voltage of the output signal DF 2 of the voltage generator E 3 ) of the inverting input pin is higher than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 2 is set to a high level and, the output signal /Q 2 is set to a low level. Since the output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 are output as the control signals D 3 and D 4 , when the voltage of the output signal DF 2 of the voltage generator E 3 is higher than the voltage of the triangular wave signal TW, the boost main switching transistor T 3 enters the on-state and the boost synchronous commutator circuit T 4 enters the off-state.
At the boost PWM comparator PWM 2 , when the voltage (the voltage of the output signal DF 2 of the voltage generator E 3 ) of the inverting input pin is lower than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 2 is set to a low level and the output signal /Q 2 is set to a high level. Since the output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 are output as the control signals D 3 and D 4 , when the voltage of the output signal DF 2 of the voltage generator E 3 is lower than the voltage of the triangular wave signal TW, the boost main switching transistor T 3 enters the off-state and the boost synchronous commutator circuit T 4 enters the on-state.
When the boost main switching transistor T 3 enters the on-state, the boost synchronous commutator circuit T 4 enters the off-state and an electric current is supplied to the choke coil L 1 from the input side. Since the input voltage Vi is applied across both ends of the choke coil L 1 , the current that flows through the choke coil L 1 increases as time elapses and the current supplied to the load also increases as time elapses. In addition, as the current flows through the choke coil L 1 , energy is accumulated in the choke coil L 1 . Then, when the boost main switching transistor T 3 enters the off-state, the boost synchronous commutator circuit T 4 enters the on-state and the energy accumulated in the choke coil L 1 is discharged.
During the on-period of the boost main switching transistor T 3 , a current IL that flows through the choke coil L 1 is expressed by expression (4) using the input voltage Vi, the inductance L of the choke coil L 1 , and the on-period Ton of the boost main switching transistor T 3 and increases as time elapses.
IL =( Vi/L )× T on (4)
In addition, during the off-period of the boost main switching transistor T 3 , the current IL that flows through the choke coil L 1 is expressed by expression (5) using the input voltage Vi, the first output voltage Vo 1 , the inductance L of the choke coil L 1 , and the off-period Toff of the boost main switching transistor T 3 and reduces as time elapses.
IL ={( Vo 1− Vi )/ L}×T off (5)
Since the current IL in the expression (4) is equal to that in the expression (5), the first output voltage Vo 1 is expressed by expression (6) using the input voltage Vi, the on-period Ton of the boost main switching transistor T 3 , and the off-period Toff of the boost main switching transistor T 3 .
Vo 1={( T on+ T off)/ T off}× Vi (6)
Consequently, when the first output voltage Vo 1 varies resulting from the variation of the input voltage Vi, it is possible to keep constant the first output voltage Vo 1 by detecting the variation of the first output voltage Vo 1 to control the ratio between on-period and off-period of the boost main switching transistor T 3 . Similarly, when the first output voltage Vo 1 varies resulting from the variation of the load, it is also possible to keep constant the first output voltage Vo 1 by detecting the variation of the first output voltage Vo 1 to control the ratio between on-period and off-period of the boost main switching transistor T 3 . In this manner, in the DC-DC converter CNV of PWM control system, it is possible to control the first output voltage Vo 1 by controlling the ratio between on-period and off-period of the boost main switching transistor T 3 .
By the way, when the DC-DC converter CNV is started, if it is assumed that the voltage of the first non-inverting input pin is lower than the voltage of the second non-inverting input pin at the error amplifier ERA 1 , the input pin IN and the first output pin OUT 1 of the power supply circuit 2 are coupled via the boost synchronous commutator circuit T 4 , and therefore, the input voltage Vi flows through as the first output voltage Vo 1 and an excessive inrush current occurs. In addition, since the input voltage Vi flows through as the first output voltage Vo 1 , the rising characteristics of the first output voltage Vo 1 will be like the rising characteristics shown in FIG. 10. Consequently, a control to raise the first output voltage Vo 1 from 0 V to the rated value (3.3 V) in a predetermined time is impossible.
However, since the voltage generated by the soft-start capacitor CS is supplied to the second non-inverting input pin of the error amplifier ERA 1 , the DC-DC converter CNV starts as a step-down type DC-DC converter, as will be described later, and makes transition to a boost type DC-DC converter when the first output voltage Vo 1 becomes equal to the input voltage Vi. Due to this, it is made possible to prevent an inrush current and control the rising slope of the first output voltage Vo 1 .
FIG. 11 shows the operation (third mode) of the step-down PWM comparator PWM 1 and the boost PWM comparator PWM 2 at the time of start of the DC-DC converter CNV. At the time of start of the DC-DC converter CNV, the soft-start capacitor CS is charged gradually by the constant-current circuit and thereby the voltage (the voltage of the second non-inverting input pin of the error amplifier ERA 1 ) generated by the soft-start capacitor CS gradually rises from 0 V. Consequently, at the time of start of the DC-DC converter CNV, the error amplifier ERA 1 generates the output signal DF 1 by amplifying the voltage difference between the voltage of the first output voltage Vo 1 divided by the resistors R 1 and R 2 and the voltage generated by the soft-start capacitor CS.
At this time, since the voltage (the voltage of the output signal DF 2 of the voltage generator E 3 ) of the inverting input pin is always lower than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin at the boost PWM comparator PWM 2 , the output signal Q 2 is always set to a low level and the output signal /Q 2 is always set to a high level (a state of 0% duty). Since the output signal Q 2 of the boost PWM comparator PWM 2 is output as the control signal D 3 , the boost main switching transistor T 3 is always in the off-state. In addition, since the output signal /Q 2 of the boost PWM comparator PWM 2 is output as the control signal D 5 , the boost synchronous commutator circuit T 5 is always in the on-state.
On the other hand, at the step-down PWM comparator PWM 1 , when the voltage (the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the inverting input pin is higher than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 1 is set to a high level and the output signal /Q 1 is set to a low level. Since the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 are output as the control signals D 1 and D 2 , when the voltage of the output signal DF 1 of the error amplifier ERA 1 is higher than the voltage of the triangular wave signal TW, the step-down main switching transistor T 1 enters the on-state and the step-down synchronous commutator circuit T 2 enters the off-state.
At the step-down PWM comparator PWM 1 , when the voltage (the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the non-inverting input pin is lower than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 1 is set to a low level and at the same time, the output signal /Q 1 is set to a high level. Since the output signals Q 1 and /Q 1 of the step-down PWM comparator PWM 1 are output as the control signals D 1 and D 2 , when the voltage of the output signal DF 1 of the error amplifier ERA 1 is lower than the voltage of the triangular wave signal TW, the step-down main switching transistor T 1 enters the off-state and the step-down synchronous commutator circuit T 2 enters the on-state.
At the time of start of the DC-DC converter CNV, the first output voltage Vo 1 is 0 V and therefore the voltage of the output signal DF 1 of the error amplifier ERA 1 becomes minimum and the pulse width of the output signal Q 1 of the step-down PWM comparator PWM 1 also becomes minimum. Because of this, the on-period of the step-down main switching transistor T 1 becomes minimum and the inrush current is prevented. In addition, the voltage generated by the soft-start capacitor CS is a voltage that defines the first output voltage Vo 1 and rises gradually with a predetermined rising slope. Because of this, the first output voltage Vo 1 also rises in proportion thereto. Consequently, the rising slope of the first output voltage Vo 1 is defined by the rising slope of the voltage generated by the soft-start capacitor CS.
When the voltage generated by the soft-start capacitor CS becomes higher than the voltage at which the first output voltage Vo 1 becomes equal to the input voltage Vi, the voltage of the output voltage DF 1 of the error amplifier ERA 1 becomes higher than the voltage of the triangular wave signal TW. Since the voltage (the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the inverting input pin is always higher than the voltage (the voltage of the triangular wave signal TW from the triangular wave oscillator OSC) supplied to the non-inverting input pin at the step-down PWM comparator PWM 1 , the output signal Q 1 is always set to a high level and the output signal /Q 1 is always set to a low level (a state of 100% duty). Since the output signal Q 1 of the step-down PWM comparator PWM 1 is output as the control signal D 1 , the step-down main switching transistor T 1 is always in the on-state. In addition, since the output signal /Q 1 of the step-down PWM comparator PWM 1 is output as the control signal D 2 , the step-down synchronous commutator circuit T 2 is always in the off-state.
On the other hand, when the voltage generated by the soft-start capacitor CS becomes higher than the voltage at which the first output voltage Vo 1 becomes equal to the input voltage Vi, the voltage (the voltage obtained by subtracting the offset voltage Ve 3 from the voltage of the output signal DF 1 of the error amplifier ERA 1 ) of the output signal DF 2 of the voltage generator E 3 comes to intersect with the voltage of the triangular wave signal TW. At the boost PWM comparator PWM 2 , when the voltage (the voltage of the output signal DF 2 of the voltage generator E 3 ) of the inverting input pin is higher than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 2 is set to a high level and the output signal /Q 2 is set to a low level. Since the output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 are output as the control signals D 3 and D 4 , when the voltage of the output signal DF 2 of the voltage generator E 3 is higher than the voltage of the triangular wave signal TW, the boost main switching transistor T 3 enters the on-state and the boost synchronous commutator circuit T 4 enters the off-state.
At the boost PWM comparator PWM 2 , when the voltage (the voltage of the output signal DF 2 of the voltage generator E 3 ) of the inverting input pin is lower than the voltage (the voltage of the triangular wave signal TW supplied from the triangular wave oscillator OSC) of the non-inverting input pin, the output signal Q 2 is set to a low level and the output signal /Q 2 is set to a high level. Since the output signals Q 2 and /Q 2 of the boost PWM comparator PWM 2 are output as the control signals D 3 and D 4 , when the voltage of the output signal DF 2 of the voltage generator E 3 is lower than the voltage of the triangular wave signal TW, the boost main switching transistor T 3 enters the off-state and the boost synchronous commutator circuit T 4 enters the on-state.
When the voltage generated by the soft-start capacitor CS rises and becomes higher than the reference voltage Ve 1 , the error amplifier ERA 1 generates the output voltage DF 1 by amplifying the voltage difference between the voltage of the first output voltage Vo 1 divided by the resistors R 1 and R 2 and the reference voltage Ve 1 . Consequently, after the voltage generated by the soft-start capacitor CS has reached the reference voltage Ve 1 , the first output voltage Vo 1 is defined by the reference voltage Ve 1 . By the way, at the time of termination of the DC-DC converter CNV, the soft-start capacitor CS is discharged gradually by a discharging resistor and the voltage generated by the soft-start capacitor CS drops gradually, and therefore, it is possible to reduce the first output voltage Vo 1 gradually.
FIG. 12 shows the rising characteristics (third mode) of the first output voltage Vo 1 . At time t 1 , when the DC-DC converter CNV is started, the soft-start capacitor CS is charged gradually by the constant-current circuit. Due to this, the voltage supplied from the soft-start capacitor CS rises as time elapses. Accompanying this, the first output voltage Vo 1 also rises as time elapses. During this time, the DC-DC converter CNV operates as the step-down type DC-DC converter.
At time t 2 , when the voltage generated by the soft-start capacitor CS becomes higher than the voltage at which the first output voltage Vo 1 becomes equal to the input voltage Vi, the DC-DC converter CNV makes transition from the step-down type DC-DC converter to the boost type DC-DC converter. The first output voltage Vo 1 continues to rise accompanying the rise in the voltage generated by the soft-start capacitor CS. At time t 3 , when the voltage generated by the soft-start capacitor CS has reached the reference voltage Ve 1 , the first output voltage Vo 1 is controlled to keep constant by the reference voltage Ve 1 thereafter.
FIG. 13 shows the operation (fourth mode) of the power supply circuit 2 . When 1.8 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 , the control signal D 7 is fixed to a high level. Due to this, the second bypass switch circuit T 7 is always in the off-state. In addition, the control signal SWD 2 is fixed to a low level. Because of this, the switch circuit SW 2 couples the output pin of the voltage generator E 2 to the first non-inverting input pin of the error amplifier ERA 1 . The output signal /Q 2 of the boost PWM comparator PWM 2 is not only output as the control signal D 4 but also output as the control signal D 5 . Since the operation other than this is the same as that in the third mode of the power supply circuit 2 , duplicated description will be omitted here.
FIG. 14 shows the configuration of the decoder DEC. The decoder DEC is configured so as to include a resistor R 7 , gate circuits G 1 to G 5 , and an output slope control circuit SC in order to embody the operation shown in FIG. 3. One pin of the resistor R 7 is coupled to the supply line of a power supply voltage Vh for a logic circuit (the voltage of the input voltage Vi raised by a charge pump circuit etc.). The other pin of the resistor R 7 is coupled to the switch circuit SWM (FIG. 2) via the signal line of the memory voltage request signal MEM. Due to this, the memory voltage request signal MEM is set to a high level when the switch circuit SWM is in the off-state and is set to a low level when the switch circuit SWM is in the on-state.
The gate circuit G 1 sets the control signal SWD 1 to a low level when the output signal JDG of the voltage comparator CMP is set to a high level and the memory voltage request signal MEM is set to a high level (when 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ). Under other conditions, the gate circuit G 1 sets the control signal SWD 1 to a high level.
The gate circuit G 2 sets the control signal SWD 2 to a high level when the output signal JDG of the voltage comparator CMP is set to a low level and the memory voltage request signal MEM is set to a high level (when 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ). Under other conditions, the gate circuit G 2 sets the control signal SWD 2 to a low level.
The gate circuit G 3 sets the control signal D 4 to a low level when the output signal of the gate circuit G 1 is set to a low level (when 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ). The gate circuit G 3 outputs the output signal /Q 2 of the boost PWM comparator PWM 2 as the control signal D 4 when the output signal of the gate circuit G 1 is set to a high level.
The gate circuit G 4 sets the output signal to a low level when the output signal JDG of the voltage comparator CMP is set to a low level and the memory voltage request signal MEM is set to a high level (when 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ). Under other conditions, the gate circuit G 4 sets the output signal to a high level.
The gate circuit G 5 sets the control signal D 5 to a low level when the output signal of the gate circuit G 4 is set to a low level (when 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ). The gate circuit G 5 outputs the output signal /Q 2 of the boost PWM comparator PWM 2 as the control signal D 5 when the output signal of the gate circuit G 4 is set to a high level.
The output slope control circuit SC sets the control signal D 6 to a high level when the output signal (control signal SWD 1 ) of the gate circuit G 1 is set to a low level (when 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory). By the way, as will be described later using FIG. 15, the output slope control circuit SC controls the voltage of the control signal D 6 so as to realize simultaneous activation of the first output voltage Vo 1 and the second output voltage Vo 2 when the output signal of the gate circuit G 1 is set to a low level. The output slope control circuit SC sets the control signal D 6 to a low level when the output signal of the gate circuit G 1 is set to a high level.
The output slope control circuit SC sets the control signal D 7 to a low level when the output signal (control signal SWD 2 ) of the gate circuit G 2 is set to a high level (when 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory). By the way, as will be described later using FIG. 15, the output slope control circuit SC controls the voltage of the control signal D 7 so as to realize simultaneous activation of the first output voltage Vo 1 and the second output voltage Vo 2 when the output signal of the gate circuit G 2 is set to a high level. The output slope control circuit SC sets the control signal D 7 to a high level when the output signal of the gate circuit G 2 is set to a low level.
FIG. 15 shows the configuration of the output slope control circuit SC. FIG. 16 shows the simultaneous activation of the first output voltage Vo 1 and the second output voltage Vo 2 . The output slope control circuit SC is configured so as to include resistors R 11 to R 15 , switch circuits SW 11 and SW 12 , error amplifiers ERA 11 and ERA 12 , and transistors T 11 to T 13 . One pin of the resistor R 11 is coupled to the first output pin OUT 1 of the power supply circuit 2 . The other pin of the resistor R 11 is coupled to one pin of the resistor R 12 . The other pin of the resistor R 12 is coupled to the ground line.
The switch circuit SW 11 couples the second output pin OUT 2 of the power supply circuit 2 to the non-inverting input pin of the error amplifier ERA 11 when the output signal (control signal SWD 1 ) of the gate circuit G 1 is set to a low level (3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ). The switch circuit SW 11 couples the ground line to the non-inverting input pin of the error amplifier ERA 11 when the output signal of the gate circuit G 1 is set to a high level.
The error amplifier ERA 11 receives the voltage (the voltage of the first output voltage Vo 1 divided by the resistors R 11 and R 12 ) of the coupling node of the resistors R 11 and R 12 at the inverting input pin and receives the voltage supplied via the switch circuit SW 11 . The error amplifier ERA 11 generates an output signal by amplifying the voltage difference between the voltage of the coupling node of the resistors R 11 and R 12 and the voltage supplied via the switch circuit SW 11 . The resistor R 13 and the transistor T 11 (n-type transistor) are coupled in series between the supply line of the power supply voltage Vh for a logic circuit and the ground line. The control pin of the transistor T 11 receives the output signal of the error amplifier ERA 11 . The transistor 12 (p-type transistor) and the resistor R 14 are coupled in series between the supply line of the power supply voltage Vh for a logic circuit and the ground line. The control pin of the transistor T 12 is coupled to the coupling node of the resistor R 13 and the transistor T 11 . The coupling node of the transistor T 12 and the resistor R 14 is coupled to the control pin of the first bypass switch circuit T 6 . In other words, the signal generated at the coupling node of the transistor T 12 and the resistor R 14 is supplied to the control pin of the first bypass switch circuit T 6 as the control signal D 6 .
The switch circuit SW 12 couples the coupling node of the resistors R 11 and R 12 to the non-inverting input pin of the error amplifier ERA 12 when the output signal (control signal SWD 2 ) of the gate circuit G 2 is set to a high level (1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 ). The switch circuit SW 12 couples the ground line to the non-inverting input pin of the error amplifier ERA 12 when the output signal of the gate circuit G 2 is set to a low level.
The error amplifier ERA 12 receives the second output voltage Vo 2 at the inverting input pin and receives the voltage supplied via the switch circuit SW 12 at the non-inverting input pin. The error amplifier ERA 12 generates an output signal by amplifying the voltage difference between the second output voltage Vo 2 and the voltage supplied via the switch circuit SW 12 . The resistor R 15 and the transistor T 13 (n-type transistor) are coupled in series between the input pin IN of the power supply circuit 2 and the ground line. The control pin of the transistor T 13 receives the output signal of the error amplifier ERA 12 . The coupling node of the resistor R 15 and the transistor T 13 are coupled to the control pin of the second bypass switch circuit T 7 . In other words, the signal generated at the coupling node of the resistor R 15 and the transistor T 13 is supplied to the control pin of the second bypass switch circuit T 7 as the control signal D 7 .
In the output slope control circuit SC having the configuration described above, when 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the second output voltage Vo 2 is supplied to the non-inverting input pin of the error amplifier ERA 11 via the switch circuit SW 11 . Because of this, the error amplifier ERA 11 generates an output signal by amplifying the voltage difference between the voltage of the first output voltage Vo 1 divided by the resistors R 11 and R 12 and the second output voltage Vo 2 .
When the second output voltage Vo 2 (the voltage of the non-inverting input pin of the error amplifier ERA 11 ) is constant, if the voltage (the voltage of the inverting input pin of the error amplifier ERA 11 ) of the first output voltage Vo 1 divided by the resistors R 11 and R 12 becomes lower than the second output voltage Vo 2 , the voltage of the output signal of the error amplifier ERA 11 rises, and therefore, the voltage of the coupling node of the resistor R 13 and the transistor T 11 drops and as a result, the voltage (the voltage of the control signal D 6 ) of the coupling node of the transistor T 12 and the resistor R 14 rises. When the voltage of the control signal D 6 rises, the first output voltage Vo 1 rises because the on-state resistance of the first bypass switch circuit T 6 becomes small.
When the first output voltage Vo 1 rises and thereby the voltage of the first output voltage Vo 1 divided by the resistors R 11 and R 12 approaches the second output voltage Vo 2 , the voltage of the output signal of the error amplifier ERA 11 drops, and therefore, the voltage of the coupling node of the resistor R 13 and the transistor T 11 rises and the voltage (the voltage of the control signal D 6 ) of the coupling node of the transistor T 12 and the resistor R 14 drops as a result. When the voltage of the control signal D 6 drops, the first output voltage Vo 1 drops because the on-state resistance of the first bypass switch circuit T 6 becomes large.
In addition, when 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the ground voltage (0 V) is supplied to the non-inverting input pin of the error amplifier ERA 12 via the switch circuit SW 12 . In the error amplifier ERA 12 , when the voltage of the non-inverting input pin is set to 0 V, the voltage of the output signal is set to 0 V irrespective of the voltage of the inverting input pin. Because of this, the control signal D 7 is set to a high level by the drive circuit constituted by the resistor R 15 and the transistor T 13 , and the second bypass switch circuit T 7 enters the off-state.
In this manner, when 3.3 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the first bypass switch circuit T 6 functions as a linear regulator such that the first output voltage Vo 1 is constant with respect to the second output voltage Vo 2 (the voltage of the non-inverting input pin of the error amplifier ERA 11 ). Consequently, when the second output voltage Vo 2 rises gradually at the time of start of the DC-DC converter CNV, the voltage of the non-inverting input pin of the error amplifier ERA 11 rises, and therefore, the first output voltage Vo 1 also rises. As a result, as shown in FIG. 16, the simultaneous activation of the first output voltage Vo 1 and the second output voltage Vo 2 is realized.
When 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the ground voltage (0 V) is supplied to the non-inverting input pin of the error amplifier ERA 11 via the switch circuit SW 11 . In the error amplifier ERA 11 , when the voltage of the non-inverting input pin is set to 0 V, the voltage of the output signal is set to 0 V irrespective of the voltage of the inverting input pin. Because of this, the control signal D 6 is set to a low level by the drive circuit constituted by the resistors R 13 and R 14 and the transistors T 11 and T 12 , and the first bypass switch circuit T 6 enters the off-state.
In addition, when 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the voltage (the voltage of the first output voltage Vo 1 divided by the resistors R 11 and R 12 ) of the coupling node of the resistors R 11 and R 12 is supplied to the non-inverting input pin of the error amplifier ERA 12 via the switch circuit SW 12 . Because of this, the error amplifier ERA 12 generates an output signal by amplifying the voltage difference between the second output voltage Vo 2 and the voltage of the first output voltage Vo 1 divided by the resistors R 11 and R 12 .
When the voltage (the voltage of the non-inverting input pin of the error amplifier ERA 12 ) of the first output voltage Vo 1 divided by the resistors R 11 and R 12 is constant, if the second output voltage Vo 2 (the voltage of the inverting input pin of the error amplifier ERA 12 ) becomes lower than the voltage of the first output voltage Vo 1 divided by the resistors R 11 and R 12 , the voltage of the output signal of the error amplifier ERA 12 rises, and therefore, the voltage (the voltage of the control signal D 7 ) of the coupling node of the resistor R 15 and the transistor T 13 drops. When the voltage of the control signal D 7 drops, the on-state resistance of the second bypass switch circuit T 7 becomes small, and therefore, the second output voltage Vo 2 rises.
When the second output voltage Vo 2 rises and thereby the second output voltage Vo 2 approaches the voltage of the first output voltage Vo 1 divided by the resistors R 11 and R 12 , the voltage of the output signal of the error amplifier ERA 12 drops, and therefore, the voltage (the voltage of the control signal D 7 ) of the coupling node of the resistor R 15 and the transistor T 13 rises. When the voltage of the control signal D 7 rises, the second output voltage Vo 2 drops because the on-state resistance of the second bypass switch circuit T 7 becomes large.
In this manner, when 1.8 V is supplied as the input voltage Vi and 3.3 V is requested as the operation voltage of the non-volatile memory 3 , the second bypass switch circuit T 7 functions as a linear regulator such that the second output voltage Vo 2 is constant with respect to the voltage (the voltage of the non-inverting input pin of the error amplifier ERA 12 ) of the first output voltage Vo 1 divided by the resistors R 11 and R 12 . Consequently, when the first output voltage Vo 1 rises gradually at the time of start of the DC-DC converter CNV, the voltage of the non-inverting input pin of the error amplifier ERA 12 rises, and therefore, the second output voltage Vo 2 also rises. As a result, as shown in FIG. 16, the simultaneous activation of the first output voltage Vo 1 and the second output voltage Vo 2 is realized.
In the embodiment as described above, it is possible to share the DC-DC converter CNV between the non-volatile memory 3 and the memory card control circuit 4 by causing the DC-DC converter CNV, the first bypass switch circuit T 6 , and the second bypass switch circuit T 7 to operate in accordance with a combination of the voltage value of the input voltage Vi and the voltage value (the voltage value of the operation voltage of the non-volatile memory 3 ) requested for the first output pin OUT 1 and therefore to reduce the number of DC-DC converters.
In addition, it is possible to prevent the inrush current without fail by causing the DC-DC converter CNV as the step-down type DC-DC converter irrespective of the combination of the voltage value of the input voltage Vi and the voltage value requested for the first output pin OUT 1 during the period from when the DC-DC converter CNV is started until when the output voltage (the first output voltage Vo 1 ) of the DC-DC converter CNV becomes equal to the input voltage Vi when the DC-DC converter CNV operates as the boost type DC-DC converter, and it is made possible to control the rising slope of the first output voltage Vo 1 from 0 V to 3.3 V. Further, it is possible to realize the simultaneous activation of the first output voltage Vo 1 and the second output voltage Vo 2 by causing the first bypass switch circuit T 6 and the second bypass switch circuit T 7 to operate in coupling with the DC-DC converter CNV. Consequently, it is possible to avoid the risk of burn-out caused by latch-up of a semiconductor device constituting the non-volatile memory 3 that uses the first output voltage Vo 1 as the power supply voltage or the memory card control circuit 4 that uses the second output voltage Vo 2 as the power supply voltage. In this manner, it is possible to realize the independence of the operation voltage of the memory card 1 from the operation voltage of the internal non-volatile memory 3 while securing the efficiency and safety.
By the way, in the embodiment described above, an example is described, in which the switch circuit SW 1 couples the coupling node of the resistors R 1 and R 2 to the inverting input pin of the error amplifier ERA 1 , taking into consideration the case where the variation of the first output voltage Vo 1 (the power supply voltage of the non-volatile memory 3 ) becomes larger than the variation of the second output voltage Vo 2 (the power supply voltage of the memory card control circuit 4 ) when 3.3 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 (second mode), however, the embodiment is not limited to this embodiment. It may also be possible for the switch circuit SW 1 to couple the coupling node of the resistors R 3 and R 4 to the inverting input pin of the error amplifier ERA 1 when 3.3 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 and if the difference between the variation of the first output voltage Vo 1 and the variation of the second output voltage Vo 2 is slight.
Similarly, in the embodiment described above, an example is described, in which the switch circuit SW 1 couples the coupling node of the resistors R 1 and R 2 to the inverting input pin of the error amplifier ERA 1 , taking into consideration the case where the variation of the first output voltage Vo 1 becomes larger than the variation of the second output voltage Vo 2 when 1.8 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 (fourth mode), however, the embodiment is not limited to this embodiment. It may also be possible for the switch circuit SW 1 to couple the coupling node of the resistors R 3 and R 4 to the inverting input pin of the error amplifier ERA 1 when 1.8 V is supplied as the input voltage Vi and 1.8 V is requested as the operation voltage of the non-volatile memory 3 and if the difference between the variation of the first output voltage Vo 1 and the variation of the second output voltage Vo 2 is slight.
An object of the aforementioned embodiment is to realize the independence of the operation voltage of a memory card from that of an internal non-volatile memory while securing the efficiency and safety.
In an aspect of the embodiment, a power supply circuit is configured so as to include an input pin, a first output pin, a second output pin, a DC-DC converter, a first bypass switch circuit, a second bypass switch circuit, a start control circuit, and an output slope control circuit. For example, the power supply circuit is constituted using a semiconductor device. The input pin receives a voltage of either a first predetermined value or a second predetermined value smaller than the first predetermined value. For the first output pin, the output of a voltage of either the first or second predetermined value is required. For the second output pin, the output of a voltage of the second predetermined value is required. For example, the power supply circuit is mounted on a memory card that has a non-volatile memory and a memory control circuit that controls the non-volatile memory. The voltage of the first output pin is used as the power supply voltage of the non-volatile memory and the voltage of the second output pin is used as the power supply voltage of the memory control circuit.
The DC-DC converter generates an output voltage from the voltage of the input pin in either a step-down mode or a boost mode and outputs the output voltage to at least one of the first and second output pins in accordance with a combination of the voltage value of the input pin and the voltage value required for the first output pin. The first bypass switch circuit turns on to output the voltage of the input pin to the first output pin when the voltage is not output to the first output pin from the DC-DC converter. The second bypass switch circuit turns on to output the voltage of the input pin to the second output pin when the voltage is not output to the second output pin from the DC-DC converter.
The start control circuit causes the DC-DC converter to operate in the step-down mode irrespective of the combination of the voltage value of the input pin and the voltage value required for the first output pin during the period from when the DC-DC converter is started until the output voltage of the DC-DC converter becomes equal to the voltage of the input pin. The output slope control circuit synchronizes the rising slope of the output voltage of the first bypass switch circuit with the rising slope of the output voltage of the DC-DC converter when the first bypass switch circuit turns on and synchronizes the rising slope of the output voltage of the second bypass switch circuit with the rising slope of the output voltage of the DC-DC converter when the second bypass switch circuit turns on.
For example, the DC-DC converter circuit generates an output voltage of the second predetermined value from the voltage of the input pin in the step-down mode and outputs the output voltage to the second output pin when the voltage value of the input pin is the first predetermined value and the voltage value required for the first output pin is the first predetermined value. The start control circuit generates an output voltage of the second predetermined value from the voltage of the input pin in the step-down mode and outputs the output voltage to the first and second output pins when the voltage value of the input pin is the first predetermined value and the voltage value required for the first output pin is the second predetermined value. The start control circuit generates an output voltage of the first predetermined value from the voltage of the input pin in the boost mode and outputs the output voltage to the first output pin when the voltage value of the input pin is the second predetermined value and the voltage value required for the first output pin is the first predetermined value. The start control circuit generates an output voltage of the second predetermined value from the voltage of the input pin in the boost mode and outputs the output voltage to the first and second output pins when the voltage value of the input pin is the second predetermined value and the voltage value required for the first output pin is the second predetermined value.
Preferably, the output slope control circuit is configured so as to include a first on-state resistance control circuit and a second on-state resistance control circuit. The first on-state resistance control circuit detects a voltage difference between the voltage that follows the voltage of the first output pin and the voltage of the second output pin and controls the on-state resistance of the first bypass switch circuit in accordance with the detection result when the first bypass switch circuit turns on. The second on-state resistance control circuit detects a voltage difference between the voltage of the second output pin and the voltage that follows the voltage of the first output pin and controls the on-state resistance of the second bypass switch circuit in accordance with the detection result when the second bypass switch circuit turns on.
In the aspect of the embodiment as described above, it is possible to share the DC-DC converter between the non-volatile memory and the memory control circuit by causing the DC-DC converter, the first and second bypass switch circuits to operate in accordance with a combination of the voltage value of the input voltage and the voltage value required for the first output pin and therefore to reduce the number of DC-DC converters. In addition, it is possible to prevent without fail the inrush current when the DC-DC converter operates in the boost mode by providing the start control circuit. Further, it is possible to realize simultaneous activation of the voltage of the first output pin and the voltage of the second output pin by causing the first and second bypass switch circuits to operate in connection with the DC-DC converter by providing the output slope control circuit. Consequently, it is possible to avoid the risk of burn-out caused by latch-up of a semiconductor device constituting the non-volatile memory or the memory control circuit. In this manner, it is possible to realize the independence of the operation voltage of the memory card from that of the internal non-volatile memory while securing the efficiency and safety.
The invention is not limited to the above embodiments and various modifications may be made without departing from the spirit and scope of the embodiments. Any improvement may be made in part or all of the components.