This application is a based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-281826 filed on Oct. 16, 2006; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to logic circuits, and particularly to logic circuits able to suppress fluctuation of electrical power consumption.
2. Description of the Related Art
Due to recent advancements in LSI technology, a great quantity and variety of semiconductor devices have come to be widely used not only for application in information systems, but also in industrial equipment, and consumer home-electronics.
Also, due to the shift to high-performance semiconductors, the electrical power consumption thereof is growing. The increase in electrical power consumption leads not only to problems of heat generation in semiconductor devices, but also to a decrease in the continuous operation time of batteries for battery-operated products, which makes lengthy continuous use of these semiconductor device-employing products impossible.
A great quantity of logic circuits for realizing various functions are contained within semiconductor devices. There are various kinds of logic circuits such as general AND circuits, exclusive OR circuits, adders, and the like.
However, since in recent years the basic unit of data processing has grown to large bit counts including 32 bit and 64 bit, there are cases in which the electrical power consumption fluctuates greatly in response to changes in simultaneously processed data. In Japanese Patent Laid-Open No. 2000-216264 for instance, there is a proposal relating to technology of low electrical power consumption in semiconductor circuits.
For this reason, there has been a problem of it being necessary to perform power circuit design in consideration of a maximum value and a minimum value that occur in electrical power consumption fluctuation that corresponds to the above mentioned changes in data.
According to an embodiment of the present invention, it is possible to provide a logic circuit that executes a prescribed arithmetic operation and comprises: a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of the input data; an interconnect network that is connected to the decoder, changes a bit pattern of the first plurality of bit data and generates a second plurality of bit data, by receiving the first plurality of bit data converted by the decoder, and substituting a bit position of received the first plurality of bit data for the purpose of the prescribed arithmetic operation; and an encoder connected to the interconnect network and converts the second plurality of bit data generated in the interconnect network into one or more binary output data.
FIG. 1 is a block diagram showing the configuration of an inverter circuit configured to execute bit inversion of a logic circuit according to a first embodiment of the present invention;
FIG. 2 is a block diagram showing an example of the configuration of the inverter circuit according to the first embodiment of the present invention;
FIG. 3 is a table showing the output of each portion of the logic circuit that is the bit inverter circuit of FIG. 2;
FIG. 4 is a block diagram showing the configuration of an exclusive OR circuit according to a second embodiment of the present invention;
FIG. 5 is a block diagram showing the configuration of an exclusive OR circuit according to a third embodiment of the present invention;
FIG. 6 is a table for explaining the relationship between the input data, and the output data of the encoder;
FIG. 7 is a table for explaining the relationship between the input data, and the output data of the encoder;
FIG. 8 is a table for explaining the relationship between the input data, and the output data of the encoder;
FIG. 9 is a table for explaining the relationship between the input data, and the output data of the encoder;
FIG. 10 is a block diagram showing the configuration of an adder according to a fourth embodiment of the present invention;
FIG. 11 is a diagram showing the relationship between the input and the output of the adder of FIG. 10;
FIG. 12 is a block diagram showing the configuration of an adder according to a fifth embodiment of the present invention;
FIG. 13 is a block diagram showing the configuration of an adder according to a sixth embodiment of the present invention;
FIG. 14 is a schematic circuit diagram showing a concrete example of the configuration of the adder circuit of FIG. 13;
FIG. 15 is a block diagram showing the configuration of an adder according to a seventh embodiment of the present invention;
FIG. 16 is a block diagram showing the configuration of an adder according to an eighth embodiment of the present invention;
FIG. 17 is a block diagram showing the configuration of a cyclic shifter according to a ninth embodiment of the present invention;
FIG. 18 is a table showing the input and result of when the binary input data has been shifted;
FIG. 19 is a block diagram showing the configuration of an AND circuit according to a tenth embodiment of the present invention;
FIG. 20 is a block diagram showing the configuration of an AND circuit according to an eleventh embodiment of the present invention;
FIG. 21 is a block diagram showing the configuration of a lower-order bit adding circuit according to a twelfth embodiment of the present invention;
FIG. 22 is a block diagram showing an example of the configuration of a higher-order bit adding circuit according to the twelfth embodiment of the present invention;
FIG. 23 is a block diagram showing the configuration of a lower-order bit eraser circuit according to a thirteenth embodiment of the present invention;
FIG. 24 is a table showing the relationship between input and output in the circuit of FIG. 23;
FIG. 25 is a schematic circuit diagram showing an example of the configuration of a higher-order bit subtracter circuit;
FIG. 26 is a block diagram showing the configuration of a bit connector circuit according to a fourteenth embodiment of the present invention;
FIG. 27 is a block diagram showing the configuration of a bit partitioning circuit according to a fifteenth embodiment of the present invention;
FIG. 28 is a block diagram showing the configuration of a bit substitution circuit according to a sixteenth embodiment of the present invention;
FIG. 29 is a table for explaining a case in which a higher-order bit changes in the circuit of FIG. 28;
FIG. 30 is a schematic circuit diagram showing a first modification of the bit substitution circuit according to the sixteenth embodiment of the present invention;
FIG. 31 is a schematic circuit diagram showing a second modification of the bit substitution circuit according to the sixteenth embodiment of the present invention;
FIG. 32 is a block diagram showing the configuration of an adder composed of a combinatorial circuit of the logic circuit according to a seventeenth embodiment of the present invention;
FIG. 33 is a top view showing an example of the layout of interconnect of the interconnect network according to the embodiments of the present invention;
FIG. 34 is a cross-sectional diagram for explaining the cross-section along line XXXIV-XXXIV of FIG. 33; and
FIG. 35 is a cross-sectional diagram for explaining the cross-section along line XXXV-XXXV of FIG. 33.
Herein below will be described embodiments of the present invention while referring to the drawings.
First, based on FIG. 1, description will be given for the entire configuration of a logic circuit according to a first embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of an inverter circuit configured to execute bit inversion of the logic circuit according to the first embodiment of the present invention.
FIG. 1 shows a basic configuration applicable to various kinds of logic circuit, and shows a logic circuit 1 including an interconnect network portion (hereinafter referred to as ‘interconnect network’) 2 , an encode portion (hereinafter referred to as ‘encoder’) 3 , and a decode portion (hereinafter referred to as ‘decoder’) 4 . The decoder 4 is a decoder configured to convert n-bit binary data into an m-bit (m>n) bit string. The interconnect network 2 is an interconnect network circuit configured to execute a prescribed operation according to substituting the decoded data. The encoder 3 is an encoder configured to convert s-bit data that has been output from the interconnect network 2 into t-bit data (s>t).
Here, though the input data is n-bit, when decoded it will become m-bit, which is larger than n-bit, and redundancy is increased. Moreover, after decoding, the decoded data is of a hamming weight unrelated to the hamming weight of the input n-bit binary data, and is processed afterward. For example, if m is 2 to the power of n, the input data is converted into such data that only one signal of the m-bit data is HIGH (hereinafter also referred to as ‘H’). If conversion is executed in this manner, after decoding, since the interconnect for the signal which will always be H is just one in quantity, the hamming weight of the decoded data will always be constant. Therefore, since the electrical power consumption of the logic circuit 1 is not dependant on the data that has been input, it is possible to realize a logic circuit that suppresses fluctuations in electrical power consumption.
The interconnect network 2 is connected to the decoder 4 , and receives through a plurality of input terminals a first plurality of bit data, which is the decoded data obtained through the conversion by the decoder 4 . For the purpose of arithmetic processing, the interconnect network 2 substitutes the bit position of the first plurality of bit data and generates a second plurality of bit data. The interconnect network performs such processing by changing the connection or signal pathway of a plurality of interconnects corresponding to each bit data of the received decode data. The second plurality of bit data is output to the encoder 3 from a plurality of output terminals of the interconnect network 2 . In other words, the interconnect network 2 performs the conversion of the bit pattern (the alignment order of the plurality of bit data) of the decode data with a constant hamming weight which was output from the decoder 4 and outputs it as output data.
Moreover, the circuit configuration shown in FIG. 1 is not solely applied to the present embodiment, but is a configuration that is applied in other logic circuits described from the second embodiment on.
Herein below, description will be given in regard to a concrete example of the present embodiment with reference to the drawings.
FIG. 2 is a block diagram showing an example of the configuration of the inverter circuit according to the present embodiment. An inverter circuit 1 A of FIG. 2 is an example of a logic circuit that realizes bit inversion.
The inverter circuit 1 A includes an input portion 101 A including three input terminals (B 2 to B 0 ) for inputting 3-bit input data, a decoder 400 A configured to convert 3-bit data into 8-bit data, an interconnect network 200 A configured to execute conversion substituting the 8-bit data (or interconnect), an encoder 300 A configured to convert 8-bit data into 3-bit data, and an output portion 102 A including three output terminals (Z 2 to Z 0 ) configured to output 3-bit data of the encoder 300 A. 3-bit binary data is input into the inverter circuit 1 A, and the inverter circuit 1 A is configured to output 3-bit binary data that has underwent bit inversion.
Here, the decoder 400 A includes eight AND circuits, and an inverter circuit is provided on the input terminals of the eight AND circuits so that for each of eight values (0 to 7) expressed as 3-bits, only one AND circuit shall put out an output. The decoder 400 A generates an output that is 8-bit decode data from a 3-bit input. The output of each AND circuit of the decoder 400 A is connected to a corresponding input terminal of the interconnect network 200 A. Each of the outputs of the interconnect network 200 A is connected to a respective input terminal of the encoder 300 A.
In FIG. 2 for example, a first AND circuit with three inverter circuits established on each of its three input terminals is provided, so that when the 3-bit input data is (0,0,0), only an output terminal D 0 of the decoder 400 A shall put out an output. Also, a second AND circuit with two inverter circuits established respectively on two of its input terminals is provided, so that when the 3-bit input data is (0,0,1), only an output terminal D 1 of the decoder 400 A shall put out an output. In the same manner, a third AND circuit with no inverter circuit established on any input terminal is provided, so that when the 3-bit input data is (1,1,1), only an output terminal D 7 of the decoder 400 A shall put out an output. In other words, only one of the interconnects (i.e., output) becomes active (or in this example, becomes ‘H’, which is the logic value ‘1’) for the output of the decoder 400 A.
The interconnect network 200 A that realizes bit inversion is configured in a manner such that the order of data or interconnects is reversed. As shown in FIG. 2, an interconnect pattern between a plurality of input terminals and a plurality of output terminals is formed so that the alignment order of the decode data, which is a plurality of bit data on a plurality of input terminals of the interconnect network 200 A, shall become reversed on the plurality of output terminals on the interconnect network 200 A. As a result, substitution of the bit position of the decode data is performed on the interconnect network 200 A.
The encoder 300 A includes three OR circuits, and the connections of the plurality of input terminals of the three OR circuits to the plurality of output terminals of the interconnect network 200 A differ from one another in such a manner that a 3-bit data is output corresponding to eight values expressed as 8-bit. The encoder 300 A is configured to generate a 3-bit output from an 8-bit input.
More specifically, as shown in FIG. 2, data from the N7 to N4 outputs of the interconnect network 200 A, from amongst 8-bit data, is input to a first OR circuit and the circuit puts out an output to an output terminal Z 2 . Data from the N7, N6, N3, N2 outputs of the interconnect network 200 A, from amongst 8-bit data, is input to a second OR circuit and the circuit puts out an output to an output terminal Z 1 . Data from the N7, N5, N3, N1 outputs of the interconnect network 200 A, from amongst 8-bit data, is input to a third OR circuit and the circuit puts out an output to an output terminal Z 0 .
Next, description will be given in regard to operation of the logic circuit shown in FIG. 2 using FIG. 3 as a reference.
FIG. 3 is a table showing the output of each portion of the logic circuit 1 that is the bit inverter circuit of FIG. 2. Description will take place using a case in which (B 2 , B 1 , B 0 )=110 are input as input data. This binary 110 is 6 when expressed as decimal. In the output of the decoder 400 A, only an output D 6 of a seventh AND circuit becomes H, while the remaining outputs are L. Therefore, the output of the decoder 400 A becomes (D 7 , D 6 , . . . , D 0 )=01000000. The interconnect network 200 A is a network in which data or the interconnect order is substituted in the manner of, N7 is substituted for D 0 , N6 is substituted for D 1 , and N5 is substituted for D 2 . When 01000000 is input, the interconnect network 200 A will output (N7, N6, . . . , N0)=00000010. This output corresponds to the decimal 1, and 001 is output by the encoder 300 A. In other words, 001, which is the bit inverse data of the input data 110 , is output.
In the above manner, it is possible to realize a bit inversion circuit using the decoder 400 A, the interconnect network 200 A, and the encoder 300 A as shown in FIG. 2. At this time, in the output of the decoder 400 A the number of signals that are H is always the same, that is, one, and even on the interconnect network 200 A the number of signals that are H will be one regardless of the kind of input. In particular, the electrical power consumption of a CMOS logic circuit is dependant upon data being processed. Therefore, the fluctuation of the electrical power consumption in the bit inversion processing is suppressed regardless of the value of the input data.
Next, description, based on FIG. 4, will be given in regard to the entire configuration of a logic circuit according to a second embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of an exclusive OR circuit according to the second embodiment.
The basic configuration of the exclusive OR circuit shown in FIG. 4 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1.
An exclusive OR circuit 1 B of FIG. 4 is an example of a circuit that takes the exclusive disjunction of two two-digit binary numbers.
The exclusive OR circuit 1 B includes an input portion 101 B, a decoder 400 B, an interconnect network 200 B, an encoder 300 B, and an output portion 102 B. The input portion 101 B includes two input portions that each include a pair of input terminals (A 1 , A 0 ) and (B 1 , B 0 ) respectively, for 2-bit input data. The decoder 400 B is configured to convert the 2-bit data of one pair of input terminals, (B 1 , B 0 ), into 4-bit data. The interconnect network 200 B is configured to receive an input of 4-bit decode data from the decoder 400 B and yet another 2-bit data of the other pair of input terminals (A 1 , A 0 ), and substitute the 4-bit data from (or four interconnects of) the decoder 400 B. The encoder 300 B is configured to convert input 4-bit data into 2-bit data. The output portion 102 B includes a pair of output terminals (Z 1 , Z 0 ) for outputting the 2-bit data of the encoder 300 B. Two input data A and B, which are each 2-bit binaries, are input to the exclusive OR circuit 1 B, and the exclusive OR circuit 1 B takes the exclusive disjunction of the two input data A and B, and outputs 2-bit binary output data.
The decoder 400 B here includes four AND circuits, and there is provided an inverter circuit at the input terminals of the four AND circuits so that for each of four values (0 to 3) expressed as 2-bits, only one AND circuit shall put out an output. The decoder 400 B is configured to generate a 4-bit output from a 2-bit input. Outputs “0”, “1”, “2”, “3” of AND circuit of the decoder 400 B are each connected to a corresponding input terminal of the interconnect network 200 B. Outputs “0”, “1”, “2”, “3” of the interconnect network 200 B are each connected to a respective input terminal of the encoder 300 B.
In FIG. 4, for example, a first AND circuit with two inverter circuits established on each of its two input terminals is provided so that when the 2-bit input data is (0, 0), only an output “0” of the decoder 400 B shall put out an output. Also, a second AND circuit with one inverter circuit established on one of its input terminals is provided, so that when the 2-bit input data is (0, 1), only an output “1” of the decoder 400 B shall put out an output. In the same manner, an AND circuit with no inverter circuit established on any input terminal is provided, so that when the 2-bit input data is (1, 1), only an output “3” of the decoder 400 B shall put out an output. In other words, only one of the interconnects (i.e., output) becomes active (or in this example, becomes ‘H’, which is the logic value ‘1’) for the output of the decoder 400 B.
The encoder 300 B here includes two OR circuits, and the connections of the plurality of input terminals of the two OR circuits to the plurality of output terminals of the interconnect network 200 B differ from one another in such a manner that a 2-bit data is output corresponding to four values expressed as 4-bit. The encoder 300 B is configured to generate a 2-bit output from a 4-bit input.
As shown in FIG. 4, data from the “3” and “2” outputs of the interconnect network 200 B, from amongst 4-bit data, is input to a first OR circuit. Data from the “3” and “1” outputs of the interconnect network 200 B, from amongst 4-bit data, is input to a second OR circuit inputs.
The interconnect network 200 B includes a plurality (four in this example) of selector circuits 600 - 1 - 1 , 600 - 1 - 2 , 600 - 2 - 1 , and 600 - 2 - 2 . The selector circuits 600 - 1 - 1 and 600 - 1 - 2 constitute a first stage selector. The selector circuits 600 - 2 - 1 and 600 - 2 - 2 constitute a second stage selector. Each selector includes two input data (input 1 and input 2 ), one control input, and two output data (output 1 and output 2 ). Each selector passes and outputs the input 1 and the input 2 to either of the outputs, output 1 and output 2 , in response to the control input, which is a control signal. In the case of FIG. 4, a case in which the control input is 0, the two input data proceed straightly, and as a result of this, the input 1 is output from the output 1 , and the input 2 is output from the output 2 . In a case in which the control input is 1, the two input data will cross, and as a result of this, the input 1 is output from the output 2 , and the input 2 is output from the output 1 . In other words, each of the selector circuits 600 are circuits configured to change the state at which the two signals input to the two input terminals appear on the two output terminals, in response to the control input that is input to the control input terminal.
Then, the two first stage selector circuits 600 - 1 - 1 and 600 - 1 - 2 receive four data “0”, “1”, “2”, and “3” from the first to fourth AND circuits of the decoder 400 B. The selector circuit 600 - 1 - 1 receives the “2” and “3” output from the decoder 400 B. The selector circuit 600 - 1 - 2 receives the “0” and “1” output from the decoder 400 B. An input data A 0 is input to each of the two first stage selector circuits 600 - 1 - 1 and 600 - 1 - 2 , respectively, as the control input. The input A is a different input data than an input B. The two second stage selector circuits 600 - 2 - 1 and 600 - 2 - 2 receive four data from the two selector circuits 600 - 1 - 1 and 600 - 1 - 2 . The two selector circuits 600 - 2 - 1 and 600 - 2 - 2 each receive, respectively, the output of the two first selector circuits 600 - 1 - 1 and 600 - 1 - 2 . An input data A 1 is input to each of the two selector circuits 600 - 2 - 1 and 600 - 2 - 2 , respectively, as the control input.
For example, when an output “3”, “2”, “1”, “0” of the decoder 400 B is input at a time when A 0 is 1, the two first stage selector circuits 600 - 1 - 1 and 600 - 1 - 2 put out output data in an order of “2”, “3”, “0”, “1”. The connections of interconnect between the first and second stage selector circuits are formed in a manner such that data in an order of “2”, “0”, “3”, “1” is input from the two first stage selector circuits 600 - 1 - 1 and 600 - 1 - 2 to the two second stage selector circuits 600 - 2 - 1 and 600 - 2 - 2 . In other words, the output “2”, “3”, “0”, “1” of the two first stage selector circuits 600 - 1 - 1 and 600 - 1 - 2 , become the input “2”, “0”, “3”, “1” because of the connection as shown n FIG. 4, and are input into the two second stage selector circuits 600 - 2 - 1 and 600 - 2 - 2 .
Next, at a time when A 1 is 0, this input data is output as-is, or in other words, the output “2”, “0”, “3”, “1” is put out from the two second stage selector circuits 600 - 2 - 1 and 600 - 2 - 2 . The two second stage selector circuits 600 - 2 - 1 and 600 - 2 - 2 output data in that order of “2”, “0”, “3”, “1”. The connections of interconnect between the two second stage selector circuits 600 - 2 - 1 and 600 - 2 - 2 and the encoder 300 B are formed in a manner such that output data in the order of “2”, “3”, “0”, “1” is input to the encoder 300 B.
In the above described case, the output of the interconnect network 200 B becomes “2”, “3”, “0”, “1” and is passed to the encoder 300 B. The output “2”, “3”, “0”, “1” will be “10”, “11”, “00”, “01” when expressed in decimal, and the second bit of each binary is inversed. In other words, the exclusive disjunction processing of the two inputs A and B is realized.
In the above manner, the decode data of input B is input to the plurality of selector circuits 600 of the above described interconnect network 200 B. The plurality of selector circuits 600 execute substitution of the bit position of the bit data of the decode data of the input B by inputting input data A, which is separate from input data B, into each control input terminal of the plurality of selector circuits 600 as the control input.
Therefore, by using the decoder 400 B, the interconnect network 200 B, and the encoder 300 B as shown in FIG. 4, it is possible to realize an exclusive OR circuit. At this time, in the output of the decoder 400 B the number of signals that are H is always the same, in other words one, and even on the interconnect network 200 B the number of signals that are H will be one regardless of the kind of input. Therefore, the fluctuation of the electrical power consumption in the exclusive disjunction processing is suppressed regardless of the value of the input data.
Next, description, based on FIG. 5, will be given in regard to the entire configuration of a logic circuit according to a third embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of an exclusive OR circuit according to the third embodiment of the present invention.
The basic configuration of the exclusive OR circuit shown in FIG. 5 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1.
An exclusive OR circuit 1 C shown in FIG. 5 is circuit configured to take the exclusive disjunction of two two-digit binaries, in a similar manner as the circuit of FIG. 4. In the circuit of FIG. 5, two inputs are decoded together, and this point differs from the circuit of FIG. 4.
The exclusive OR circuit 1 C includes an input portion 101 C, a decoder 400 C, an interconnect network 200 C, an encoder 300 C, and an output portion 102 C. The input portion 101 C includes two input portions 101 C 1 and 101 C 2 that include a plurality (here, a pair) of input terminals (A 1 , A 0 ) and (B 1 , B 0 ) respectively, for 2-bit input data. The decoder 400 C includes a decoder 400 C- 1 configured to convert the 2-bit data of the input terminal pair (A 1 , A 0 ) of the input portion 101 C 1 into 4-bit data, and a decoder 400 C- 2 configured to convert the 2-bit data of the input terminal pair (B 1 , B 0 ) of the input portion 101 C 2 into 4-bit data. Into the interconnect network 200 C, 4-bit decode data from the decoder 400 C-1 and 4-bit decode data from the decoder 400 C- 2 is input, and the interconnect network 200 C substitutes the two 4-bit data (or four interconnects), and outputs 4-bit data. The encoder 300 C is configured to convert input 4-bit data into 2-bit data. The output portion 102 C includes an output portion including a pair of output terminals (Z 1 , Z 0 ) for outputting the 2-bit data of the encoder 300 C. Two input data A and B, which are each 2-bit binaries, are input to the exclusive OR circuit 1 C, and the exclusive OR circuit 1 C takes the exclusive disjunction of the two input data A and B, and outputs 2-bit binary output data.
Here, the decoder 400 C- 1 and the decoder 400 C- 2 of the decoder 400 C each include four AND circuits, and there is provided an inverter circuit on each input terminal of the four AND circuits so that for each of four values (0 to 3) expressed as 2-bits, only one AND circuit shall put out an output. The two decoders 400 C- 1 and 400 C- 2 each are configured to generate a 4-bit output from a 2-bit input. Outputs “0”, “11”, “2”, “3” of each AND circuit of the decoder 400 C are each connected to a corresponding input terminal of the interconnect network 200 C. Outputs “0”, “1”, “2”, “3” of the interconnect network 200 C are each connected to a respective input terminal of the encoder 300 C.
Since operation of the two decoders decoder 400 C- 1 and decoder 400 C- 2 of FIG. 5 is analogous to the decoder 400 B explained in FIG. 4, description will be omitted.
Two 4-bit data that have each been decoded are input to the interconnect network 200 C. As shown in FIG. 5, four signal lines input with 4-bit data from the decoder 400 C- 2 and four output lines by which 4-bit data is output to the encoder 300 C are arranged in a matrix. A connection element 620 is provided at each intersection point of the matrix and is configured to set into connection or disconnection the signal lines from the decoder 400 C- 2 and the output lines to the encoder 300 C. Each connection element 620 includes two data terminals and one control input terminal configured to control connection and disconnection of the two data terminals. Connected to the control input terminal is a signal line from the decoder 400 C- 1 . That is, decoded data of the input data that was input to the input terminals (A 1 , A 0 ) of the input portion 101 C 1 is input to each control input terminal as a control input. In other words, each connection element is an element configured to change states of connection and disconnection between two terminals in response to a control input that is input to the control input terminal.
As shown in FIG. 5, when there exists a matrix of the four signal lines from the decoder 400 C- 2 and the four output lines from the interconnect network 200 C to the encoder 300 C, the four signal lines from the decoder 400 C- 1 are connected, respectively, to four control input terminals of the four connection elements 620 situated on the respective output lines. Moreover, the four signal lines from the decoder 400 C- 1 , when viewed at each output line, are each separately connected to one of the four control input terminals of the four connection elements 620 connected to each output line. Also, the four signal lines from the decoder 400 C- 1 , when viewed at each signal line, are each separately connected to one of the four control input terminals of the four connection elements 620 connected to each signal line. Thus, the signal lines of the decoder 400 C- 1 and the control input terminal of each connection element 620 are connected via interconnect in a manner such that the output of the exclusive disjunction of the two input data is output from the encoder 300 C.
Moreover, the connection element 620 is an element such as a three-state buffer or a transfer gate that possesses a function in which the two data terminals are connected or disconnected according to the control input, which is a control signal.
In the exclusive OR circuit 1 C, when the input data A to the input terminals (A 1 , A 0 ) is 0 (a binary of 00), the relationship between the input data B input to the input terminal (B 1 , B 0 ), and the output of the encoder 300 C is as is shown in FIG. 6.
FIGS. 6 to 9 are tables for the purpose of showing the relationship of the input data B and the output of the encoder.
Moreover, when the input data A to the input terminals (A 1 , A 0 ) is 1 (a binary of 01), the relationship between the input data B input to the input terminal (B 1 , B 0 ), and the output of the encoder 300 C is as is shown in FIG. 7.
Moreover, when the input data A to the input terminals (A 1 , A 0 ) is 2 (a binary of 10), the relationship between the input data B input to the input terminal (B 1 , B 0 ), and the output of the encoder 300 C is as is shown in FIG. 8.
Moreover, when the input data A to the input terminals (A 1 , A 0 ) is 3 (a binary of 11), the relationship between the input data B input to the input terminal (B 1 , B 0 ), and the output of the encoder 300 C is as is shown in FIG. 9.
In the above described manner, the decode data of the input B is input into a terminal of one end of the plurality of connection elements 620 of the above described interconnect network 200 C, and the plurality of output lines of the encoder 300 C are connected to the terminal of the other end the plurality of connection elements 620 . Moreover, by inputting decode data of input A into each control input terminal of the plurality of connection elements 620 as the control input, substitution of the bit position of the decode data of the input B on the interconnect network 200 C is executed.
Therefore, with using the decoder 400 C, the interconnect network 200 C, and the encoder 300 C, as shown in FIG. 5, it is possible to realize an exclusive OR circuit. At this time, the number of signals of the outputs of the decoder 400 C- 1 and the decoder 400 C- 2 that are H are always the same, that is, one, and even on the interconnect network 200 C the number of output signals that are H will be one regardless of the kind of input. Therefore, the fluctuation of the electrical power consumption in the exclusive OR processing is suppressed regardless of the value of the input data.
Next, description, based on FIG. 10, will be given in regard to the entire configuration of a logic circuit according to a fourth embodiment of the present invention. FIG. 10 is a block diagram showing the configuration of an adder according to the fourth embodiment. The adder of the present embodiment is a no-carry adder.
The basic configuration of the adder of FIG. 10 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1.
An adder 1 D of FIG. 10 includes an input portion 101 D, a decoder 400 D, an interconnect network 200 D, an encoder 300 D, and an output portion 102 D. The input portion 101 D includes two input portions 101 D 1 and 101 D 2 that each include a pair of input terminals (A 1 , A 0 ) and (B 1 , B 0 ) respectively, for 2-bit input data. The decoder 400 D includes a decoder 400 D- 1 configured to convert the 2-bit data of the input terminal pair (A 1 , A 0 ) of the input portion 101 D 1 into 4-bit data, and a decoder 400 D- 2 configured to convert the 2-bit data of the input terminal pair (B 1 , B 0 ) of the input portion 101 D 2 into 4-bit data. The interconnect network 200 D is configured to be input with 4-bit decode data from the decoder 400 D-1 and 4-bit decode data from the decoder 400 D- 2 , substitute the two 4-bit data (or four interconnects), and output 4-bit data. The encoder 300 D is configured to convert input 4-bit data into 2-bit data. The output portion 102 D includes an output portion including a pair of output terminals (Z 1 , Z 0 ) for outputting the 2-bit data of the encoder 300 D. Two input data A and B, which are each 2-bit binaries, are input to the adder 1 D, and the adder 1 D adds together the two input data A and B, and outputs 2-bit binary output data.
The two decoders of the decoder 400 D, the decoder 400 D- 1 and the decoder 400 D- 2 are analogous to the decoder 400 C- 1 and the decoder 400 C- 2 of FIG. 5.
Two 4-bit data which have been decoded are input to the interconnect network 200 D. As shown in FIG. 10, a plurality of signal lines (here, four is the quantity) input with 4-bit data from the decoder 400 D- 2 and a plurality of output lines (here, four is the quantity) by which 4-bit data is output to the encoder 300 D are arranged in a matrix. A connection element 620 is provided at each intersection point of the matrix and is configured to set into connection or disconnection the signal lines from the decoder 400 D- 2 and the signal lines to the encoder 300 D. The connection element 620 is the same as that of FIG. 5, as each includes two data terminals and one control input terminal configured to control connection and disconnection of the two data terminals. Connected to the control input terminal is a signal line from the decoder 400 D- 1 . That is, decoded data of the input data that was input to the input terminals (A 1 , A 0 ) of the input portion 101 D 1 is input to each control input terminal.
As shown in FIG. 10, when there exists a matrix of the four signal lines from the decoder 400 D- 2 and the four output lines from the interconnect network 200 D to the encoder 300 D, the four signal lines from the decoder 400 D- 1 are connected, respectively, to four control input terminals of the four connection elements 620 situated on each of the output lines. Moreover, the signal lines from the decoder 400 D- 1 , when viewed at each output line, are each separately connected to one of the four control input terminals of the four connection elements 620 connected to each output line. Also, the signal lines from the decoder 400 D- 1 , when viewed at each signal line from the decoder 400 D- 2 , are each connected to one of the four control input terminals of the four connection elements 620 connected to each signal line. Thus, the signal lines of the decoder 400 D- 1 and the control input terminal of each connection element 620 are connected according to interconnect in a manner such that the output of the addition result of the two input data is output from the encoder 300 D.
The adder 1 D shown in FIG. 10 is a no-carry adder of two 2-digit binaries. The adder 1 D includes two 2-digit binary inputs A and B, and both inputs are each decoded by the decoder 400 D. The decoded data is sent to the interconnect network 200 D, are subject to execution of adding, and then passed to the encoder 300 D. The no-carry adder operates in the manner shown in FIG. 11.
FIG. 11 is a diagram showing the relationship between the input and the output of the adder of FIG. 10. The interconnect network 200 D that realizes the operation shown in FIG. 11 is as shown in FIG. 10. The interconnect network 200 D is structured, in the same manner as in FIG. 5, in a manner in which the connection element 620 connects the input and the output. The connection of the control input thereof differs. In this manner, if the decoded data is of an input/output relationship that corresponds to a pair, it is possible to realize a logic circuit using a string of connection elements.
In the above described manner, the decode data of the input B is input into a terminal of one end of the plurality of connection elements 620 of the above described interconnect network 200 D, and the plurality of output lines to the encoder 300 D are connected to the terminal of the other end of the plurality of connection elements 620 . Moreover, by inputting the decode data of the input A into each of the control input terminals of the plurality of connection elements 620 as the control input, substitution of the bit position of the decode data of the input B on the interconnect network 200 D is executed.
Therefore, with using the decoder 400 D, the interconnect network 200 D, and the encoder 300 D, as shown in FIG. 10, it is possible to realize a no-carry adder. At this time, the number of signals of the outputs of the decoder 400 D- 1 and the decoder 400 D- 2 that are H are always the same, that is, one, and even on the interconnect network 200 D the number of signals that are H will be one regardless of the kind of input. Therefore, the fluctuation of the electrical power consumption in the no-carry adding is suppressed regardless of the value of the input data.
Next, description, based on FIG. 12, will be given in regard to the entire configuration of a logic circuit according to a fifth embodiment of the present invention. FIG. 12 is a block diagram showing the configuration of an adder according to the fifth embodiment. The adder of the present embodiment is an adder with a carry.
The basic configuration of the adder of FIG. 12 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1.
An adder 1 E of FIG. 12 includes an input portion 101 E, a decoder 400 E, an interconnect network 200 E, an encoder 300 E, and an output portion 102 E. The input portion 101 E includes two input portions 101 E 1 and 101 E 2 that include a pair of input terminals (A 1 , A 0 ) and (B 1 , B 0 ) respectively, each for 2-bit input data. The decoder 400 E is a decoder configured to convert the 2-bit data of the input terminal pair (B 1 , B 0 ) of the input portion 101 E 2 into 4-bit data. The interconnect network 200 E is configured to be input with 4-bit decode data from the decoder 400 E and 2-bit data from the input portion 101 E 1 , substitute the 4-bit data (or four interconnects), and output 4-bit data as well as 3-bit data. The encoder 300 E is configured to convert input 4-bit data into 2-bit data as well as output a carry signal. The output portion 102 E includes a pair of output terminals (Z 1 , Z 0 ) for outputting the 2-bit data of the encoder 300 E, and an output portion (Z 2 ) used for the carry signal. Two input data A and B, which are each 2-bit binaries, are input to the adder 1 E, and the adder 1 E adds together the two input data A and B, and outputs the resulting 2-bit binary output data and a carry signal output-data.
The decoder 400 E is analogous to the decoder 400 B of FIG. 4.
The interconnect network 200 E is an interconnect network including a plurality of selector circuits 610 . The interconnect network 200 E includes a rotate shifter 200 E 1 having a 2-stage selector. A first stage selector and a second stage selector of the rotate shifter 200 E 1 each include four selector circuits 610 . The output of the rotate shifter 200 E 1 is an output of an adding result unrelated to the presence or absence of a carry.
Each of the selector circuits 610 includes two inputs (input 1 and input 2 ), one control input, and one output. Each of the selector circuits 610 pass either of the input 1 or the input 2 to the output terminal of one end in response to the control input that is input to the control input terminal. In the case of FIG. 12, in a case in which the control input, which is a control signal, is 0, the input 1 of the upper side of each of the selector circuits 610 is output from the output terminal, and in a case in which the control input is 1, the input 2 of the lower side of each of the selector circuits 610 is output from the output terminal.
Then, four data “0”, “1”, “2”, “3” from each of the first to fourth AND circuits of the decoder 400 E are input to the input terminal of one end of the four first stage selector circuits 610 . Four data “1”, “2”, “3”, “0” from each of the second, third, fourth, and first AND circuits of the decoder 400 E are input to the input terminal of the other end of the four first stage (first to fourth) selector circuits 610 . That is, the output of an AND circuit adjacent to an AND circuit connected to each of the input terminals of one side of the four first stage selector circuits 610 is connected to the input terminal of the other side of the selector circuits 610 . An input data A 0 is input to the control input terminal of each of the four first stage selector circuits 610 as the control input.
Therefore, in a case in which the A 0 is 0, the outputs “0”, “1”, “2”, “3” of the decoder 400 E are each output to the “0”, “1”, “2”, “3” outputs of the first stage selectors, and in a case in which the A 0 is 1, the outputs “3”, “0”, “1”, “2” of the decoder 400 E are each output to the “0”, “1”, “2”, “3” outputs of the first stage selectors.
Four outputs of the four first stage (first to fourth) selector circuits 610 are each input to the input terminals of one end of the four second stage (first to fourth) selector circuits 610 . Four outputs “0”, “1”, “2”, “3” from each of the four first stage (third, fourth, first, and second) selector circuits 610 are input to the input terminals of the other end of the four second stage (first to fourth) selector circuits 610 . That is, the outputs of the selector circuit 610 adjacent to the selector circuit 610 adjacent to each selector circuit 610 connected to each of the input terminals of one end are connected to the input terminals of the other end of the four second stage selector circuits 610 . The input data A 1 is input into each of the control input terminals of the four second stage selector circuits 610 as the control input.
The interconnect network 200 E further includes four selector circuits 610 which constitute a network used to calculate a carry. An output “3” of the fourth AND circuit is input to the input terminal of one end of a first selector circuit 610 a , and an “L” is input to the input terminal of the other end thereof. The input data A 0 is input to the control input terminal of the first selector circuit 610 a as the control input.
An output “4” of the first selector circuit 610 a is connected to the input terminal of one end of a second selector circuit 610 b . An output “2” of the third selector circuit 610 of the first stage selector is connected to the input terminal of the other end of the second selector circuit 610 b . An input data A 1 is input to the control input terminal of the second selector circuit 610 b as the control input.
An output “3” of the fourth selector circuit 610 of the first selector is connected to the input terminal of one end of a third selector circuit 610 c . The “L” is input to the input terminal of the other end of the third selector circuit 610 c . The input data A 1 is input to the control input terminal of the third selector circuit 610 c as the control input.
An output “4” of the first selector circuit 610 a is connected to the input terminal of one end of a fourth selector circuit 610 d . The “L” is input to the input terminal of the other end of the fourth selector circuit 610 d . The input data A 1 is input to the control input terminal of the fourth selector circuit 610 d as the control input.
Output of an initial stage selector including four selector circuits 610 of a first stage selector and a first selector circuit 610 a of a carry calculation network is the output “0”, “1”, “2”, “3”, “4”. Output of a subsequent stage selector including four selector circuits 610 of the second stage selector and the second, third, and fourth selector circuits 610 b , 610 c , 610 d of the carry calculation network is the output “0”, “1”, “2”, “3”, “4”, “5”, “6”.
A 0 is input to the control input of the initial stage selector, and A 1 is input to the control input of the subsequent stage selector. Since the A 1 is the second digit of a binary, it is denoted by the decimal 2. Therefore this corresponds to the adding of 2 when A 1 is 1. The output in a case in which the input of the upper side of the subsequent stage selector (the output in a case in which A 1 is 0) is selected is an initial stage selector output of “0”, “1”, “2”, “3”, “4”, and the output in a case in which the input of the lower side is selected (the output in a case in which A 1 is 1) is “2”, “3”, “0”, “1”, “2”, “3”, “4”.
The encoder 300 E has a configuration analogous to the encoder 300 B shown in FIG. 4. That is, as is shown in FIG. 12, the encoder 300 E inputs the output of the four selector circuits 610 of the second stage selector into two OR circuits, and puts out the output of the two OR circuits to the output terminals (Z 1 , Z 0 ).
Also, the encoder 300 E includes an OR circuit 300 E 1 configured to be input with three outputs “4”, “5”, and “6” of the second, third and fourth selector circuits 610 b , 610 c , and 610 d of the carry calculation network, and the output of the OR circuit 300 E 1 is output to the output terminal (Z 2 ) as the carry signal.
With using this kind of configuration, in a case in which a carry has been generated, according to the output of the second stage selector, any of the three outputs “4”, “5”, and “6” of the subsequent stage selector become H while attaining the same results as in FIG. 11. It is possible to calculate a carry bit according to the exclusive disjunction of the three outputs “4”, “5”, and “6”.
In the above manner, in a case in which a carry has been generated by adding in the carry calculation network of the interconnect network 200 E, any one input of the three input terminals of the OR circuit 300 E 1 becomes H. That is, in the example of FIG. 12, in a case in which four or more adding results are generated with respect to the two data inputs each from 0 to 3, any one of the three inputs (the outputs of “ 4 ”, “5”, “6” of the second, third, fourth selector circuits 610 b , 610 c , and 610 d ) of the OR circuit 300 E 1 shall become H.
In the above manner, the input A, which is separate from the input B, is input to each of the control input terminals of the plurality of selector circuits 610 of the above described interconnect network 200 E as the control input. As a result of this, the output of the plurality of selector circuits 610 input with the decode data of the input B is changed, and substitution of the bit position of the decode data of input B is executed on the interconnect network 200 E.
Therefore, with using the decoder 400 E, the interconnect network 200 E, and the encoder 300 E as shown in FIG. 12, it is possible to realize an adder having a carry. At this time, in the output of the decoder 400 E the number of signals that are H is always the same, that is, one, and even on the interconnect network 200 E the number of signals that are H will be one regardless of the kind of input. Therefore, the fluctuation of the electrical power consumption in the adding with a carry is suppressed regardless of the value of the input data.
Next, description, based on FIG. 13, will be given in regard to the entire configuration of a logic circuit according to a sixth embodiment of the present invention. FIG. 13 is a block diagram showing the configuration of an adder according to the sixth embodiment. The adder of the present embodiment is an adder with a carry.
The basic configuration of the adder of FIG. 13 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1.
An adder 1 F of FIG. 13 includes an input portion 101 F, a decoder 400 F, an interconnect network 200 F, an encoder 300 F, and an output portion 102 F. The input portion 101 F includes two input portions 101 F 1 and 101 F 2 that include a pair of input terminals (A 1 , A 0 ) and (B 1 , B 0 ) respectively, each for inputting 2-bit input data. The decoder 400 F includes a decoder 400 F- 1 configured to convert the 2-bit data of the input terminal pair (A 1 , A 0 ) of the input portion 101 F 1 into 4-bit data, and a decoder 400 F- 2 configured to convert the 2-bit data of the input terminal pair (B 1 , B 0 ) of the input portion 101 F 2 into 4-bit data. The interconnect network 200 F is configured to be input with 4-bit decode data from the decoder 400 F-1 and 4-bit decode data from the decoder 400 F- 2 , substitute the two 4-bit data (or four interconnects), and output 4-bit data to the encoder 300 F as well as output 3-bit data to the encoder 300 F.
The encoder 300 F is configured to convert input 4-bit data into 2-bit data as well as output a carry signal. The output portion 102 F includes a pair of output terminals (Z 1 , Z 0 ) for outputting the 2-bit data of the encoder 300 F, and an output portion (Z 2 ) used for the carry signal. Two input data A and B, which are each 2-bit binaries, are input to the adder 1 F, and the adder 1 F adds together the two input data A and B, and outputs the resulting 2-bit binary output data and a carry signal output-data.
The decoder 400 F- 1 and the decoder 400 F- 2 of the decoder 400 F are analogous to the decoder 400 C- 1 and the decoder 400 C- 2 of FIG. 5.
Two 4-bit data which have each been decoded are input to the interconnect network 200 F. As shown in FIG. 13, four signal lines input with 4-bit data from the decoder 400 F- 2 and four signal lines by which 4-bit data is output to the encoder 300 F are arranged in a matrix. A connection element 620 is provided at each intersection point of the matrix and is configured to set into connection or disconnection the signal lines from the decoder 400 F- 2 and the signal lines to the encoder 300 F. The connection element 620 is the same as that of FIG. 5, as each includes two data terminals and one control input terminal configured to control connection and disconnection of the two data terminals. Connected to the control input terminal is a signal line from the decoder 400 F- 1 . That is, decoded data of the input data A that was input to the input terminals (A 1 , A 0 ) of the input portion 101 F 1 is input to each control input terminal as a control input.
As shown in FIG. 13, when there exists a matrix of the four signal lines from the decoder 400 F- 2 and the four output fines from the interconnect network 200 F to the encoder 300 F, each of the four signal lines from the decoder 400 F- 1 are connected, respectively, to four control input terminals of the four connection elements 620 situated on each of the output lines. Moreover, the four signal lines from the decoder 400 F- 1 , when viewed at each output line, are each separately connected to one of the four control input terminals of the four connection elements 620 connected to each output line. Also, the four signal lines from the decoder 400 F- 1 , when viewed at each signal line, are each separately connected to one of the four control input terminals of the four connection elements 620 connected to each signal line. Thus, the signal lines of the decoder 400 F- 1 and the control input terminal of each connection element 620 are connected via interconnect in a manner such that the output of the addition result of the two input data with the carry is output from the encoder 300 F.
The interconnect network 200 F further includes twelve connection elements 620 that constitute a carry calculation network, and three L level signal lines supplied with a “0” (that is, an “L” level) signal.
The encoder 300 F has the same configuration as the encoder 300 B of FIG. 4. Moreover, as shown in FIG. 13, the encoder 300 F includes an OR circuit 300 F 1 input with signals of three carry signal lines. Four connection elements 620 are each provided on a first carry signal line C 1 at four intersection points of three signal lines of a second, third, and fourth AND circuits of the decoder 400 F- 2 and a first L level signal line L 1 . Four connection elements 620 are each provided on a second carry signal line C 2 at four intersection points of two signal lines of the third and fourth AND circuits of the decoder 400 F- 2 and the first and second L level signal lines L 1 and L 2 . Four connection elements 620 are each provided on a third carry signal line C 3 at four intersection points of the signal lines of the fourth AND circuit of the decoder 400 F- 2 and the first, second, and third L level signal lines L 1 , L 2 , and L 3 . The three carry signal lines C 1 , C 2 , and C 3 are connected to an input terminal of the OR circuit 300 F 1 . The output of the OR circuit 300 F 1 is output to the output terminal (Z 2 ).
The adder F 1 configured in this manner is a logic circuit that realizes the same function as that of FIG. 12. In the interconnect network of FIG. 12, one input is processed with data that has not been decoded, while in the interconnect network of FIG. 13, both inputs are processed with a decoded value.
FIG. 14 is a schematic circuit drawing showing a concrete example configuration of the adder circuit shown in FIG. 13. FIG. 14 shows an example configuration of a case using an n-channel transistor NT as the connection element 620 . Also, there is connected to each of the output lines, a drain of a p-channel transistor PT used for pre-charging. Before an operation is executed, all of the p-channel transistors PT are controlled to become ON, and all outputs of the interconnect network 200 F become H. Next, all of the p-channel transistors PT are switched OFF, and data is supplied to the interconnect network 200 F from the decoder 400 F- 1 and the decoder 400 F- 2 , and each of the n-channel transistors NT are switched either ON or OFF according to each of their inputs. In each of the output lines, in a case in which each output from the decoder 400 F- 1 is L, the electrical charges that have been accumulated are pulled, and the H state is held only in a case in which the output from the decoder 400 F- 1 is H. Therefore, after the n-channel transistor NT has acted, a signal of a result identical to that of FIG. 13 is output from the interconnect network 200 F. According to configuration in this manner, it is possible to cut the number of transistors in the interconnect network 200 F, and it also becomes possible to reduce the result dependence of the electrical power consumption, as a former output state is erased according to executing pre-charging.
In the above manner, decode data of the input B is input to the terminals of one side of a plurality of the connection elements 620 of the above described interconnect network 200 F, and a plurality of output lines to the encoder 300 F are connected to the terminals of the other side of the plurality of connection elements 620 . Moreover, by inputting the decode data of the input A to the each of the control input terminals of the plurality of connection elements 620 as the control input, substitution of the bit position of the decode data of the input B is conducted on the interconnect network 200 F.
Therefore, with using the decoder 400 F, the interconnect network 200 F, and the encoder 300 F as shown in FIG. 13 and FIG. 14, it is possible to realize an adder with a carry. At this time, in the output of the decoder 400 F- 1 and the decoder 400 F- 2 , the number of signals that are H is always the same, that is, one, and even on the interconnect network 200 F the number of signals that are H will be one regardless of the kind of input. Therefore, the fluctuation of the electrical power consumption in the adding with a carry is suppressed regardless of the value of the input data.
Next, description, based on FIG. 15, will be given in regard to the entire configuration of a logic circuit according to a seventh embodiment of the present invention. FIG. 15 is a block diagram showing the configuration of an adder according to the seventh embodiment. The adder of the present embodiment is an adder with a carry input.
The basic configuration of the adder of FIG. 15 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1.
An adder 1 G of FIG. 15 includes an input portion 101 G, a decoder 400 G, an interconnect network 200 G, an encoder 300 G, and an output portion 102 G. The input portion 101 G includes two input portions 101 G 1 and 101 G 2 that include a pair of input terminals (A 1 , A 0 ) and (B 1 , B 0 ) respectively, each for inputting 2-bit input data. The decoder 400 G is a decoder configured to convert the 2-bit data of the input terminal pair (B 1 , B 0 ) of the input portion 101 G 2 into 4-bit data. The interconnect network 200 G is configured to be input with 4-bit decode data from the decoder 400 G, 2-bit data from the input portion 101 G, and a carry input data CI, substitute the two 4-bit data (or four interconnects), and output 4-bit data of the adding result to the encoder 300 G as well as output a 4-bit data, which is used for the carry, to the encoder 300 G. The encoder 300 G is configured to convert input 4-bit data into 2-bit data as well as output a carry signal. The output portion 102 G includes a pair of output terminals (Z 1 , Z 0 ) for outputting the 2-bit data of the encoder 300 G, and an output portion (Z 2 ) used for the carry signal. A carry signal input-data CI and two input data A and B, which are each 2-bit binaries, are input to the adder 1 G, and the adder 1 G adds together the two input data A and B, and outputs the resulting 2-bit binary output data and a carry signal output-data.
The decoder 400 G is analogous to the decoder 400 B of FIG. 4.
The interconnect network 200 G is an interconnect network including a plurality of selector circuits 610 . The interconnect network 200 G includes a rotate shifter 200 G 1 including a 3-stage selector. A first stage selector, a second stage selector, and a third stage selector of the rotate shifter 200 G 1 each include four selector circuits 610 . The output of the rotate shifter 200 G 1 is an output of an adding result unrelated to the presence or absence of a carry.
Each of the selector circuits 610 includes two inputs (input 1 and input 2 ), one control input, and one output. Each of the selector circuits 610 pass either of the input 1 or the input 2 to the output terminal of one end in response to the control input that is input to the control input terminal. In the same manner as in the case of FIG. 12, in a case in which the control input is 0, the input 1 of the upper side of each of the selector circuits 610 is output from the output terminal, and in a case in which the control input is 1, the input 2 of the lower side of each of the selector circuits 610 is output from the output terminal.
Then, four data “0”, “1”, “2”, “3” from each of the first to fourth AND circuits of the decoder 400 G are input to the input terminal of one end of the four selector circuits 610 of the first stage. Four data “3”, “0”, “1”, “2” from each of the fourth, first, second, and third AND circuits of the decoder 400 G are input to the input terminal of the other end of the four first stage (that is, the first to fourth) selector circuits 610 . That is, the output of an AND circuit adjacent to an AND circuit connected to each of the input terminals of one side is connected to the input terminal of the other side of the four first stage selector circuits 610 . The carry input data CI is input to the control input terminal of each of the four first stage selector circuits 610 as the control input.
Therefore, in a case in which the CI is 0, the outputs “0”, “1”, “2”, “3” of the decoder 400 G are each output to the “0”, “1”, “2”, “3” outputs of the first stage selectors, and in a case in which the CI is 1, the outputs “3”, “0”, “1”, “2” of the decoder 400 G are each output to the “0”, “1”, “2”, “3” outputs of the first stage selectors.
Four outputs of the four first stage (first to fourth) selector circuits 610 are each input to the input terminals of one end of the four second stage (first to fourth) selector circuits 610 . Four outputs from each of the four first stage (fourth, first, second, and third) selector circuits 610 are input to the input terminals of the other end of the four second stage (first to fourth) selector circuits 610 . That is, the outputs of the selector circuit 610 adjacent to the selector circuit 610 adjacent to each selector circuit 610 connected to each of the input terminals of one end are connected to the input terminals of the other end of the four second stage selector circuits 610 . The input data A 0 is input into each of the control input terminals of the four second-stage selector circuits 610 as the control input.
Four outputs of the four second stage (first to fourth) selector circuits 610 are each input to the input terminals of one end of the four third stage (first to fourth) selector circuits 610 . Four outputs from each of the four second stage (third, fourth, first, and second) selector circuits 610 are input to the input terminals of the other end of the four third stage (first to fourth) selector circuits 610 . That is, the outputs of the selector circuit 610 adjacent to the selector circuit 610 adjacent to each selector circuit 610 connected to each of the input terminals of one end are connected to the input terminals of the other end of the four third stage selector circuits 610 . The input data A 1 is input into each of the control input terminals of the four third stage selector circuits 610 as the control input.
The interconnect network 200 G further includes seven selector circuits 610 which constitute a network used to calculate a carry. An output of the fourth AND circuit is input to the input terminal of one end of a first selector circuit 610 - 1 a , and a 0(=“L”) is input to the input terminal of the other end. The input data CI is input to the control input terminal of the first selector circuit 610 - 1 a as the control input. The second to seventh selector circuits 610 - 1 b to 610 - 1 g constitute a selector that processes the carry result.
An output of the first selector circuit 610 - 1 a is connected to the input terminal of one end of a second selector circuit 610 - 1 b . An output of the fourth selector circuit of the first stage selector is connected to the input terminal of the other end of the second selector circuit 610 - 1 b . An input data A 0 is input to the control input terminal of the second selector circuit 610 - 1 b as the control input.
An output of the first selector circuit 610 - 1 a is connected to the input terminal of one end of a third selector circuit 610 - 1 c . The 0(=“L”) is input to the input terminal of the other end of the third selector circuit 610 - 1 c . The input data A 0 is input to the control input terminal of the third selector circuit 610 - 1 c as the control input.
An output of the third selector circuit of the second selector is connected to the input terminal of one end of a fourth selector circuit 610 - 1 d . The output of the second selector circuit 610 - 1 b is input to the input terminal of the other end of the fourth selector circuit 610 - 1 d . The input data A 1 is input to the control input terminal of the fourth selector circuit 610 - 1 d as the control input.
An output of the fourth selector circuit of the second selector is connected to the input terminal of one end of a fifth selector circuit 610 - 1 e . The output of the third selector circuit 610 - 1 c is input to the input terminal of the other end of the fifth selector circuit 610 - 1 e . The input data A 1 is input to the control input terminal of the fifth selector circuit 610 - 1 e as the control input.
An output of the second selector circuit 610 - 1 b is connected to the input terminal of one end of a sixth selector circuit 610 - 1 f . The 0(=“L”) is input to the input terminal of the other end of the sixth selector circuit 610 - 1 f . The input data A 1 is input to the control input terminal of the sixth selector circuit 610 - 1 f as the control input.
An output of the third selector circuit 610 - 1 c is connected to the input terminal of one end of a seventh selector circuit 610 - 1 g . The 0(=“L”) is input to the input terminal of the other end of the seventh selector circuit 610 - 1 g . The input data A 1 is input to the control input terminal of the seventh selector circuit 610 - 1 g as the control input.
Output of an initial stage selector including the four selector circuits 610 of the first stage selector and a first selector circuit 610 - 1 a of a carry calculation network is the output “0”, “1”, “2”, “3”, “4”. Output of a mid stage selector including the four selector circuits 610 of the second stage selector and the second and third selector circuits 610 - 1 b and 610 - 1 c , of the carry calculation network is the output “0”, “1”, “2”, “3”, “5”, “6”. Output of a subsequent stage selector including the four selector circuits 610 of the third stage selector and the fourth, fifth, sixth, and seventh selector circuits 610 - 1 d , 610 - 1 e , 610 - 1 f and 610 - 1 g , of the carry calculation network is the output “0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”. The selector of the initial stage is a selector stage established before the interconnect network used for adding, and is for realizing one addition.
A 1 is input to the control input of the subsequent stage selector. Since the A 1 is the second digit of a binary, it is denoted by the decimal 2. Therefore this corresponds to the adding of 2 when A 1 is 1. The output in a case in which the input of the upper side of the subsequent stage selector (the output in a case in which A 1 is 0) is selected is a mid stage selector output of “ 0 ”, “1”, “2”, “3”, “4”, L, L, and the output in a case in which the input of the lower side is selected (the output in a case in which A 1 is 1) is “2”, “3”, “0”, “2”, “3”, “4”, “5”.
The encoder 300 G has a configuration analogous to the encoder 300 B shown in FIG. 4. That is, as is shown in FIG. 15, the encoder 300 G inputs the output of the four selector circuits 610 of the third stage selector into two OR circuits, and puts out the output of those two OR circuits to the output terminals (Z 1 , Z 0 ).
Also, the encoder 300 G includes an OR circuit 300 G 1 configured to be input with the four outputs “4”, “5”, “6”, and “7” of the fourth, fifth, sixth, and seventh selector circuits 610 - 1 d , 610 - 1 e , 610 - 1 f and 610 - 1 g , of the carry calculation network, and the output of this OR circuit 300 G 1 is output to the output terminal (Z 2 ) as the carry signal.
With using this kind of configuration, in a case in which a carry has been generated, according to the output of the second stage selector, any of the four outputs “4”, “5”, “6”, and “7” of the subsequent stage selector become H while attaining the same results as in FIG. 12. It is possible to calculate a carry bit according to the exclusive disjunction of the four outputs “4”, “5”, “6”, and “7”.
In the above manner, the initial selector is provided on the interconnect network 200 G so as to further add “one” in response to an input of a carry. Moreover, in a case in which a carry has been generated by adding, any one input of the four input terminals of the OR circuit 300 G 1 becomes H. That is, in the example of FIG. 15, in a case in which four or more addition results are generated with respect to the two data inputs each from 0 to 3, any one of the three inputs (second, third, fourth selector circuits 610 b , 610 c , and 610 d ) of the OR circuit 300 E 1 shall become H.
In the above manner, the input A, which is separate from the input B, and the carry data are input to each of the control input terminals of the plurality of selector circuits 610 of the above described interconnect network 200 G as the control input. As a result of this, the output of the plurality of selector circuits 610 input with the decode data of the input B is changed, and substitution of the bit position of the decode data of input B is executed on the interconnect network 200 G.
Therefore, with using the decoder 400 G, the interconnect network 200 G, and the encoder 300 G as shown in FIG. 15, it is possible to realize an adder having a carry input. At this time, in the output of the decoder 400 G the number of signals that are H is always the same, that is, one, and even on the interconnect network 200 G the number of signals that are H will be one regardless of the kind of input. Therefore, the fluctuation of the electrical power consumption in the adding with a carry input is suppressed regardless of the value of the input data.
Next, description, based on FIG. 16, will be given in regard to the entire configuration of a logic circuit according to an eighth embodiment of the present invention. FIG. 16 is a block diagram showing the configuration of an adder according to the eighth embodiment. The adder of the present embodiment is an adder with a carry input.
The basic configuration of the adder of FIG. 16 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1.
An adder 1 H of FIG. 16 includes an input portion 101 H, a decoder 400 H, an interconnect network 200 H, an encoder 300 H, and an output portion 102 H. The input portion 101 H includes two input portions 101 H 1 and 101 H 2 that include a pair of input terminals (A 1 , A 0 ) and (B 1 , B 0 ) respectively, each for inputting 2-bit input data A and B. The decoder 400 H includes a decoder 400 H- 1 configured to convert the 2-bit data of the input terminal pair (A 1 , A 0 ) of the input portion 101 H 1 into 4-bit data, and a decoder 400 H- 2 configured to convert the 2-bit data of the input terminal pair (B 1 , B 0 ) of the input portion 101 H 2 into 4-bit data. The interconnect network 200 H is configured to be input with 4-bit decode data from the decoder 400 H- 1 , 4-bit decode data from the decoder 400 H- 2 , and a carry input data CI, substitute the two 4-bit data (or four interconnects), output 4-bit data of an addition result to the encoder 300 H, and also output 4-bit data, which is used for carrying, to the encoder 300 H.
The encoder 300 H is configured to convert input 4-bit data into 2-bit data, and also output a carry signal. The output portion 102 H includes a pair of output terminals (Z 1 , Z 0 ) for outputting the 2-bit data of the encoder 300 H, and an output terminal (Z 2 ) used for the carry signal. Two input data A and B, which are each 2-bit binaries, are input to the adder 1 H, and the adder 1 H adds together the two input data A and B, and outputs the resulting 2-bit binary output data and a carry signal output-data.
The decoder 400 H- 1 and the decoder 400 H- 2 of the decoder 400 H are analogous to the decoder 400 C- 1 and the decoder 400 C- 2 of FIG. 5.
The interconnect network 200 H includes a selector 200 H 1 that executes carry input processing, and has as input the four outputs from the decoder 400 H- 2 . The selector H 1 includes five selector circuits 610 , and the first to four outputs of the decoder 400 H- 2 are each input to the input terminal of one end of four selector circuits 610 (the first through fourth selector circuits). A “0”(=L) signal is input to the input terminal of one end of the remaining selector circuit 610 (the fifth selector circuit). The “0”(=L) signal is input to the input terminal of the other end of the first selector circuit 610 . Outputs “0”, “1”, “2”, “3” of the first to fourth AND circuits of the decoder 400 H- 2 are input to the input terminal of the other end of the second to fifth selector circuits 610 . The output of the first to fifth selector circuits 610 of the selector 200 H 1 is set to “0”, “1”, “2”, “3”, “4”. According to the above configuration, in a case in which there is a carry input, the selector 200 H 1 changes five outputs in a manner such that 1 will be added to the output.
Data of eleven signal lines including the five outputs of the selector 200 H 1 and six outputs of the “0”(=L) signal, and 4-bit data from the decoder 400 H- 1 , are input to the interconnect network 200 H. As shown in FIG. 16, these eleven signal lines, and eight signal lines through which 8-bit data is output to the encoder 300 H, are arranged in a matrix. The output of the interconnect network 200 H is “0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”.
As shown in FIG. 16, a connection element 620 is provided at each intersection point of the matrix and is configured to set into connection or disconnection the eleven signal lines and the eight output lines to the encoder 300 H. As shown in FIG. 16, the connection elements 620 are not provided at all of the intersection points. The connection elements 620 are analogous to the connection elements 620 of FIG. 5, and include two data terminals, and one control input terminal that controls the connection and disconnection of the two data terminals. There is connected to the control input terminal a signal line from the decoder 400 H- 1 . That is, decoded data of the input data A that was input to the input terminals (A 1 , A 0 ) of the input portion 101 H is input to each control input terminal. In other words, the interconnect network 200 H including the connection elements 620 executes addition of a result that has underwent carry processing in the selector 200 H 1 and a result decoded in the decoder 400 H- 1 .
As shown in FIG. 16, in a case in which the eleven signal lines are aligned in order from the first to the eleventh signal line, the first to the third signal lines are “0”(=L) signal lines. The fourth to eighth signal lines are signal lines corresponding to the output “0”, “1”, “2”, “3”, “4” of the first to fifth selector circuits 610 of the selector 200 H 1 . The ninth to eleventh signal lines are “0”(=L) signal lines.
As shown in FIG. 16, there is provided a connection element 620 at the intersection point of each of the eight outputs “0”, “1”, “2”, “3”, “4”, “5”, “6”, “7” to the encoder 300 H and the four signal lines out of the eleven signal lines.
Provided at each of the intersection points of the first output line and the first to fourth signal lines is a connection element 620 . Provided at each of the intersection points of the second output line and the second to fifth signal lines is a connection element 620 . There is provided a connection element 620 at each of other interconnections as well.
That is, there is provided at each of the intersection points of the n-th output line and the n-th to (n+3)-th signal lines is a connection element 620 . Moreover, in the case of FIG. 16, n denotes 1 to 8 .
Then, the fourth output “3” of the decoder 400 H- 1 is connected to the control input terminal of the connection element 620 provided at each intersection point of the n-th output line and the n-th signal line. The third output “2” of the decoder 400 H- 1 is connected to the control input terminal of the connection element 620 provided at each intersection point of the n-th output line and the (n+1)-th signal line. The second output “1” of the decoder 400 H- 1 is connected to the control input terminal of the connection element 620 provided at each intersection point of the n-th output line and the (n+2)-th signal line. The first output “0” of the decoder 400 H- 1 is connected to the control input terminal of the connection element 620 provided at each intersection point of the n-th output line and the (n+3)-th signal line.
The eight outputs of the interconnect network 200 H are input to the encoder 300 H.
The encoder 300 H includes a configuration identical to the configuration of the encoder 300 B of FIG. 4. Moreover, as shown in FIG. 16, the encoder 300 H includes an OR circuit 300 H 1 that is input with the signals of four carry signal lines.
Each output of a first OR circuit and a second OR circuit is connected to the two output terminals (Z 1 , Z 0 ) that output the addition result. A second, a fourth, a sixth, and an eighth output are each connected to the four inputs of the first OR circuit, respectively. A third, the fourth, a seventh, and the eighth outputs are each connected to the four inputs of the second OR circuit, respectively.
The output of the third OR circuit 300 H 1 are connected to the output terminal (Z 2 ) that outputs the carry result. A fifth, a sixth, the seventh, and the eighth outputs are each connected to the four inputs of the second OR circuit 300 H 1 , respectively.
According to configuration in the above manner, one of the five values from 0 to 4 is taken as a result of carrying being executed in the selector 200 H 1 . Also, since the output of the decoder 400 H- 1 takes one of the four values from 0 to 3, it is possible to take one of the eight values from 0 to 7 as the addition result thereof. Therefore, the output of the interconnect network 200 H becomes eight output lines, and operation occurs in which one of the eight output lines becomes “1”(=H) and the remaining output lines become “0”(=L).
For example, in a case in which the input A is 2, the input B is 3, and the carry input CI is 0, the “3” output of the outputs of the selector 200 H 1 , which is a carry processing circuit, becomes H, and the remaining outputs of the selector 200 H 1 become L. Among the plurality of the connection elements 620 , only those each of whose control inputs is connected to the output “2” of the decoder 400 H- 1 assume a conductive state. Therefore, only the output “5” of the interconnect network 200 H becomes H, while the remaining outputs become L. According to the kind of operation described herein above, only data that has been subject to addition operation is output from the interconnect network 200 H and input to the encoder 300 H. The encoder 300 H encodes the input data, and in the case of this example, outputs a binary 101. According to the kind of operation described herein above, it is possible to realize addition processing.
Moreover, although in the circuits of FIGS. 12 to 15 there were included an addition result output line and a carry output line, the adder of the present embodiment is configured in a manner in which the addition result output line and the carry output line are not respective exclusive-use output lines.
The adder 1 H configured in this manner is a logic circuit that realizes the same function as in FIG. 13 while including a carry input. Also, in the present embodiment as well, the fluctuation of the electrical power consumption is suppressed regardless of carry adding since only one of the plurality of output lines of the interconnect network become H.
In the above manner, the decode data of input B and the carry data are input to the plurality of the selector circuits of the above described interconnect network 200 H, and a carrying data is generated. The carrying data is input to the terminal of one end of the plurality of connection elements 620 , and a plurality of output lines to the encoder 300 H are connected to the terminals of the other end of the plurality of connection elements 620 . Moreover, according to inputting decode data of the input data A into each of the control input terminals of the plurality of connection elements 620 as the control input, substitution of the bit position of the decode data of the input B is executed in the interconnect network 200 H.
Therefore, with using the decoder 400 H, the interconnect network 200 H, and the encoder 300 H as shown in FIG. 16, it is possible to realize an adder with a carry input. At this time, the number of signals of the outputs of the decoder 400 H- 1 and the decoder 400 H- 2 that are H are always the same, that is, one, and even on the interconnect network 200 H the number of signals that are H will be one regardless of the kind of input. Therefore, the fluctuation of the electrical power consumption in the adding with a carry input is suppressed regardless of the value of the input data.
Next, description, based on FIG. 17, will be given in regard to the entire configuration of a logic circuit according to a ninth embodiment of the present invention. FIG. 17 is a block diagram showing the configuration of a cyclic shifter according to the ninth embodiment.
The basic configuration of the cyclic shifter of FIG. 17 includes a decoder, an interconnect network, and an encoder, as is similar to the basic configuration shown in FIG. 1. A cyclic shifter 1 I of FIG. 17 includes an input portion 101 , a decoder 400 I, an interconnect network 200 I, an encoder 300 I, and an output portion 102 I. The cyclic shifter 1 I is an example of a circuit that right shifts 4-bit binary input data from any of 0 to 3-bit.
The input portion 101 I includes an input portion 101 I 1 including four input terminals (Bit 0 , Bit 1 , Bit 2 , Bit 3 ) for inputting 4-bit input data, and an input portion 101 I 2 including two input terminals (Sft 0 , Sft 1 ). The decoder 400 I is a decoder that converts 4-bit data of the four input terminals (Bit 0 , Bit 1 , Bit 2 , Bit 3 ) of the input portion 101 I 1 into 16-bit data, based on the input data of the input portion 101 I 2 . The interconnect network 200 I inputs the 4-bit decode data from the decoder 400 I and 2-bit shift quantity data from the input portion 101 I 2 , executes substitution of the 16-bit data (or 16 interconnects), and outputs 16-bit data. The encoder 300 I converts the input 16-bit data into 4-bit data, and outputs to the output portion 102 I. The output portion 102 I has four output terminals (Bit 0 , Bit 1 , Bit 2 , Bit 3 ) for outputting the 4-bit data of the encoder 300 I. 4-bit binary input data and 2-bit shift quantity data are input to the cyclic shifter 1 I, and the cyclic shifter 1 I outputs 16-bit binary output data shifted according to the inp