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The entire disclosure of Japanese Patent Application No. 2006-276130 filed on Oct. 10, 2006 including specification, claims, drawings and abstract is incorporated herein by reference in its entirety.
1. Field of the Invention
An aspect of the present invention relates to a DC-DC converter.
2. Description of the Related Art
As power circuits, there are provided synchronous rectification DC-DC converters that output a PWM (pulse width modulation)-controlled DC voltage by using a high-side transistor and a low-side transistor that are connected to each other in series and provided between a power supply voltage and a reference potential. To generate the PWM-controlled DC voltage, the high-side transistor and the low-side transistor are alternately turned on/off state. The on state periods of the transistors are controlled according to variations of a load and an input voltage.
As for the on/off switching timing, if there exists a period when both of the high-side transistor and the low-side transistor are turned on, a flow-through current occurs and the conversion efficiency is lowered. In view of this, the switch-on timing of each of the high-side transistor and the low-side transistor is delayed to provide a period (dead time) when both of them are turned off.
As a conventional method for delaying the switch-on timing of each of the high-side transistor and the low-side transistor, there is provided a delay circuit utilizing the CR time constant of a capacitor C and a resistor R. However, since a certain time is taken to charge or discharge the capacitor C, it is difficult to attain high-speed switching.
Additionally, since an inverter or a buffer used in the delay circuit have a variation in the threshold value, the dead time set by taking into account the variation.
On the other hand, a method is known which reliably prevents occurrence of a period when both of the high-side transistor and the low-side transistor are turned on, independently of the type or characteristic of a device (refer to JP-2004-23846-A, for example).
A DC-DC converter disclosed in JP-2004-23846-A has detecting sections that detects the on/off states of body diodes of a high-side field-effect transistor and of a low-side field-effect transistor, respectively. The on states of the high-side field-effect transistor and the low-side field-effect transistor are controlled so that an output corresponding to an input signal is output after detecting that one of the body diodes has been turned on.
However, the DC-DC converter disclosed in JP-2004-23846-A has the following problems. In a process that a field-effect transistor makes a transition from an on state to an off state, it is difficult to detect a change to the off state of the field-effect transistor until the impedance of the field-effect transistor becomes sufficiently high and the accompanying body diode makes a sufficient degree of transition to an on state. This results in a problem that the conversion efficiency lowers particularly in the case of high-frequency switching.
According to an aspect of the present invention, there is provided a DC-DC converter including: a first transistor connected to a high-potential power supply; a second transistor connected to a low-potential power supply; a first current detector that monitors a first current flowing through the first transistor and that outputs a first control signal when the first current becomes smaller than a first reference value; a second current detector that monitors a second current flowing through the second transistor and that outputs a second control signal when the second current becomes smaller than a second reference value; and a driver that turns on the second transistor based on the first control signal and that turns on the first transistor based on the second control signal.
According to another aspect of the present invention, there is provided a DC-DC converter including: an inductor; a first transistor connected to a high-potential power supply via the inductor; a second transistor connected to a low-potential power supply; a first current detector that monitors a first current flowing through the first transistor and that outputs a first control signal when the first current becomes smaller than a first reference value; a second current detector that monitors a second current flowing through the second transistor and that outputs a second control signal when the second current becomes smaller than a second reference value; and a driver that turns on the second transistor based on the first control signal and that turns on the first transistor based on the second control signal.
According to still another aspect of the present invention, there is provided a DC-DC converter including: a first transistor connected to a high-potential power supply; a second transistor connected to a low-potential power supply; a receiver that receives: a first signal capable of turn off the first transistor and turn on the second transistor; a second signal capable of turn off the second transistor and turn on the first transistor; a first path that transmits the first signal from the receiver to the second transistor via the first transistor; and a second path that transmits the second signal from the receiver to the first transistor via the second transistor; wherein: the first path includes: a first delaying element that delays an transmission of the first signal, and a first phase-advancing element that advances the transmission of the first signal; and the second path includes: a second delaying element that delays an transmission of the second signal, and a second phase-advancing element that advances the transmission of the second signal.
Embodiment may be described in detail with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram showing the configuration of a DC-DC converter according to a first embodiment;
FIG. 2 is a chart showing a delay characteristic of a transistor of the DC-DC converter according to the first embodiment;
FIG. 3 is a timing chart showing the operation of the DC-DC converter according to the first embodiment;
FIG. 4 is a chart illustrating a dead time of the DC-DC converter according to the first embodiment in comparison with that of a comparison example;
FIG. 5 shows a semiconductor integrated circuit of the DC-DC converter according to the first embodiment;
FIG. 6 is a circuit diagram showing the configuration of a DC-DC converter according to a second embodiment;
FIG. 7 is a circuit diagram showing the configuration of a DC-DC converter according to a third embodiment; and
FIG. 8A is a block diagram showing the configuration of another DC-DC converter, and
FIG. 8B is a block diagram showing the configuration of still another DC-DC converter.
Embodiments will be hereinafter described with reference to the drawings.
A DC-DC converter according to a first embodiment will be described below with reference to FIGS. 1-4. FIG. 1 is a circuit diagram of the DC-DC converter according to the first embodiment. FIG. 2 is a chart showing a delay characteristic of a transistor of the DC-DC converter. FIG. 3 is a timing chart showing the operation of the DC-DC converter. FIG. 4 is a chart illustrating a dead time of the DC-DC converter in comparison with that of a comparison example.
As shown in FIG. 1, a DC-DC converter 10 according to this embodiment includes an output section 11 having a first transistor (high-side transistor) M 1 and a second transistor (low-side transistor) M 2 which are connected to each other in series and provided between an input power source E 1 and a reference potential GND, a first current detecting section 12 which monitors a first current I 1 flowing through the first transistor M 1 and outputs a first control signal for turning on the second transistor M 2 if the first current I 1 becomes smaller than a first reference value, a second current detecting section 13 which monitors a second current I 2 flowing through the second transistor M 2 and outputs a second control signal for turning on the first transistor M 1 if the second current I 2 becomes smaller than a second reference value, and a drive section 14 which turns off the first transistor M 1 and turns on the second transistor M 2 in response to the first control signal and also turns off the second transistor M 2 and turns on the first transistor M 1 in response to the second control signal.
For example, the first transistor M 1 of the output section 11 is a p-type insulated-gate field-effect transistor (hereinafter referred to as “p-MOS transistor”), and the second transistor M 2 is an n-type insulated-gate field-effect transistor (hereinafter referred to as “n-MOS transistor”). The first transistor M 1 and the second transistor M 2 have what is called a totem-pole connection.
More specifically, the source S 1 of the first transistor M 1 is connected to an input power supply terminal VIN, the drain D 1 of the first transistor M 1 is connected to the drain D 2 of the second transistor M 2 , a connection node a of the drain D 1 of the first transistor M 1 and the drain D 2 of the second transistor M 2 is connected to an output terminal LX, and the source S 2 of the second transistor M 2 is connected to the ground potential GND.
The gate G 1 of the first transistor M 1 is connected to an output terminal 14 a of the drive section 14 . The gate G 2 of the second transistor M 2 is connected to an output terminal 14 b of the drive section 14 .
The first current detecting section 12 includes a third transistor M 3 (p-MOS transistor) whose gate G 3 (control electrode) and drain D 3 (first electrode) are connected to the gate G 1 and the drain D 1 of the first transistor M 1 , respectively, and whose source S 3 (second electrode) is connected to the source S 1 of the first transistor M 1 via a first resistor R 1 , a fourth transistor M 4 (p-MOS transistor) whose drain D 4 is connected to the reference potential GND via a first constant current source 15 and whose source S 4 is connected to the source S 3 of the third transistor M 3 via a second resistor R 2 , and a fifth transistor M 5 whose drain D 5 is connected to the reference potential GND via a second constant current source 16 , whose source S 5 is connected to the source S 1 of the first transistor M 1 via a third resistor R 3 , and whose gate G 5 is connected to its own drain D 5 and the gate G 4 of the fourth transistor M 4 .
The second current detecting section 13 includes a sixth transistor M 6 (n-MOS transistor) whose gate G 6 and drain D 6 are connected to the gate G 2 and the drain D 2 of the second transistor M 2 , respectively, and whose source S 6 is connected to the source S 2 of the second transistor M 2 via a fourth resistor R 4 , a seventh transistor M 7 (n-MOS transistor) whose drain D 7 is connected to a power source E 2 via a third constant current source 17 and whose source S 7 is connected to the source S 6 of the sixth transistor M 6 via a fifth resistor R 5 , and an eighth transistor M 8 whose drain D 8 is connected to the power source E 2 via a fourth constant current source 18 , whose source S 8 is connected to the source S 2 of the second transistor M 2 via a sixth resistor R 6 , and whose gate G 8 is connected to its own drain D 8 and the gate G 7 of the seventh transistor M 7 .
The drive section 14 includes a NOR circuit 22 which receives an input PWM signal 20 from a drive signal input terminal 19 and also receives the first control signal from the first current detecting section 12 via an inverter 21 and a NAND circuit 25 which receives the PWM signal 20 and also receives the second control signal from the second current detecting section 13 via inverters 23 and 24 .
A smoothing circuit which consists of an inductor L and a capacitor C and smoothes a PWM-controlled DC voltage which is output from the output section 11 is connected to the output terminal LX. For example, when the voltage Vin of the input power source E 1 is 3 to 5 V, the smoothing circuit supplies a load 26 with a smoothed output voltage Vout of about 1.2 to 3.3 V.
For example, the first transistor M 1 of the output section 11 and the third transistor M 3 of the first current detecting section 12 are pair transistors which have common gates G 1 and G 3 , common drains D 1 and D 3 , and sources S 1 and S 3 being different in area and which are produced in the same chip by the same process.
When a voltage is applied to the common gates G 1 and G 3 , currents flow through the first transistor M 1 and the third transistor M 3 at a ratio that is equal to the area ratio of the sources S 1 and S 3 . For example, where the area ratio of the sources S 1 and S 3 is 1000:1, a current of 1 mA flows through the third transistor M 3 when a current of 1 A flows through the first transistor M 1 .
The area of the source is adjusted, for example, by adjusting the gate width of the transistor. Plurality of the transistors having the same gate length may be used to change the effective gate width.
The same is true of the second transistor M 2 of the output section 11 and the sixth transistor M 6 of the second current detecting section 13 .
Next, the operation of the DC-DC converter 10 will be described.
First, a description will be made of an operation that when the PWM signal 20 is switched from L to H, the second transistor (low-side transistor) M 2 makes an on-to-off transition and the first transistor (high-side transistor) M 1 makes an off-to-on transition.
Since the seventh transistor M 7 and the eighth transistor M 8 are current-mirror-connected, the same current Ic 3 flows through the third constant current source 17 and the fourth constant current source 18 .
When the PWM signal 20 is switched from L to H, the output of the NOR circuit 22 is fixed at L and hence the second transistor (low-side transistor) M 2 and the sixth transistor M 6 of the second current detecting section 13 make an on-to-off transition.
Then, the voltage drop across the fourth resistor R 4 decreases and the potential difference between the gate G 7 and the source S 7 of the seventh transistor M 7 increases, whereby the drain current of the seventh transistor M 7 increases.
Since the drain current of the seventh transistor M 7 is forced to be approximately the same current as the current Ic 3 by the third constant current source 17 , the drain voltage of the seventh transistor M 7 is increased, and an H-level second control signal Sc 2 is output to the drive section 14 .
When the second control signal Sc 2 is switched from L to H, the output of the buffer inverter 23 is changed from H to H and the output of the signal adjustment inverter 24 is changed from L to H.
Since the other input of the NAND circuit 25 is H, both inputs of the NAND circuit 25 become H and the output of the NAND circuit 25 is changed from H to L. As a result, both of the first transistor (high-side transistor) M 1 and the third transistor M 3 of the first current detecting circuit 12 make an off-to-on transition.
Next, a description will be made of an operation that when the PWM signal 20 is switched from H to L, the second transistor (low-side transistor) M 2 makes an off-to-on transition and the first transistor (high-side transistor) M 1 makes an on-to-off transition.
Since the fourth transistor M 4 and the fifth transistor M 5 are current-mirror-connected, the same current Ic 1 flows through the first constant current source 15 and the second constant current source 16 .
When the PWM signal 20 is switched from H to L, the output of the NAND circuit 22 is fixed at H and hence the first transistor (high-side transistor) M 1 and the third transistor M 3 of the first current detecting section 12 make an on-to-off transition.
Then, the voltage drop across the first resistor R 1 decreases and the potential difference between the gate G 4 and the source S 4 of the fourth transistor M 4 increases, whereby the drain current of the fourth transistor M 4 increases.
Since the drain current of the fourth transistor M 4 is forced to be approximately the same current as the current Ic 1 by the first constant current source 15 , the drain voltage of the fourth transistor M 4 is increased, and an H-level first control signal Sc 1 is output to the drive section 14 .
When the first control signal Sc 1 is changed from L to H, the output of the buffer/signal adjustment inverter 23 is changed from H to L.
Since the other input of the NOR circuit 22 is L, both inputs of the NOR circuit 22 become L and the output of the NOR circuit 22 is changed from L to H. As a result, both of the second transistor (low-side transistor) M 2 and the sixth transistor M 6 of the second current detecting circuit 13 make an off-to-on transition.
The output signal VLX has a voltage that is the voltage Vin of the input power source E 1 minus an on-voltage Vds 1 of the first transistor M 1 , that is, Vin−Vds 1 , during a period when the first transistor M 1 is on and the second transistor M 2 is off. And the output signal VLX has a voltage that is equal to an on-voltage Vds 2 of the second transistor M 2 during a period when the first transistor M 1 is off and the second transistor M 2 is on.
During a dead time when both of the first and second transistors M 1 and M 2 are off, the energy stored in the inductor L is released to cause a flow of a regenerative current through the body diode of the second transistor M 2 . Therefore, the output signal VLX has a voltage that is equal to a forward voltage −Vf of the body diode.
As shown in FIG. 2, even when a control signal for turning off the first transistor M 1 is input to it at time t 0 , the gate voltage Vg 1 of the first transistor M 1 does not vary quickly but increases depending on the time constant of the gate capacitance etc.
When the gate-source voltage Vgs 1 of the first transistor M 1 becomes close to its threshold voltage Vth 1 at time t 1 , the current I 1 flowing through the first transistor M 1 starts to decrease. After the gate-source voltage Vgs 1 becomes equal to the threshold voltage Vth 1 at time t 2 , the current I 1 decreases steeply.
As a result, from time t 0 to time t 1 , the impedance RM 1 of the first transistor M 1 becomes an on-state impedance Ron that is 1 to 100 mΩ and increases steeply to an off-state impedance Roff that is about several megaohms after time t 1 . Therefore, a turn-off delay δ=t 2 −t 0 occurs from the application of the control signal to the turning-off of the first transistor M 1 .
Next, the operation of the DC-DC converter 10 will be described in detail with reference to a timing chart.
As shown in FIG. 3, when the PWM signal 20 is switched from L to H at time t 0 , the second transistor (low-side transistor) M 2 makes an on-to-off transition. Therefore, the second current I 2 decreases according to the turn-off delay characteristic of the second transistor M 2 .
Then, at time t 1 when the second current I 2 becomes equal to a second reference value Iref 2 which is smaller than or equal to, for example, 1/100 of a peak second current I 2 p of the second transistor M 2 , the second control signal Sc 2 is changed from H to L.
Then, at time t 2 , the second current I 2 of the transistor M 2 becomes zero.
During that course, when the second control signal Sc 2 is changed from H to L, the gate voltage Vg 1 of the first transistor (high-side transistor) M 1 starts to decrease from the power supply voltage Vin. The first transistor M 1 is turned on and the first current I 1 starts flow through it at time t 3 when the gate voltage Vg 1 of the first transistor M 1 has decreased by its threshold voltage Vth 1 .
From time t 2 to time t 3 , no flow-through current flows through the first and second transistors M 1 and M 2 because both of the first current I 1 of the first transistor M 1 and the second current I 2 of the second transistor M 2 are zero and a dead time td 1 =t 3 −t 2 occurs.
Then, at time t 4 when the PWM signal 20 is switched from H to L, the first transistor (high-side transistor) M 1 makes an on-to-off transition and hence the first current I 1 decreases according to the turn-off delay characteristic of the first transistor M 1 .
Then, at time t 5 when the first current I 1 becomes equal to a first reference value Iref 1 which is smaller than or equal to, for example, 1/100 of a peak first current I 1 p of the first transistor M 1 , the first control signal Sc 1 is changed from L to H.
In response to this trigger signal, the gate-source voltage Vgs 2 of the second transistor (low-side transistor) M 2 starts to increase from the reference potential GND. At time t 7 when the gate-source voltage Vgs 2 of the second transistor M 2 has increased by its threshold voltage Vth 2 , the second transistor M 2 is turned on and the second current I 2 starts to flow through the second transistor M 2 .
During that course, at time t 6 , the first current I 1 of the transistor M 1 becomes zero.
From time t 5 to time t 6 , no flow-through current flows through the first and second transistors M 1 and M 2 because both of the first current I 1 of the first transistor M 1 and the second current I 2 of the second transistor M 2 are zero and a dead time td 2 =t 7 −t 6 occurs.
FIG. 4 shows a relationship between the dead time and the conversion efficiency of a DC-DC converter. In FIG. 4, symbol a denotes a dead time range of this embodiment and symbol b denotes a dead time range of a comparison example in which a dead time is produced by a delay circuit which utilizes a CR time constant.
As shown in FIG. 4, in the case where the dead time is positive, the body diode of each of the first and second transistors M 1 and M 2 is turned on during an off-period to cause a loss. Therefore, the DC-DC conversion efficiency decreases gently as the dead time becomes longer.
On the other hand, in the case where the dead time is negative, a flow-through current flows through the first and second transistors M 1 and M 2 and hence the DC-DC conversion efficiency decreases steeply.
The dead time range b of the comparison example is wide (td>0) because of variations of the turn-on/off delay characteristics of the high-side and low-side transistors and other reasons. On the other hand, the dead time range a of this embodiment is a narrow range around td=0.
The dead time td 1 depends on the turn-on delay characteristic of the first transistor M 1 , the delay characteristic of the second current detecting section 13 , the gate delay characteristic of the drive section 14 , and the phase-advancing effect obtained by setting the second reference value Iref 2 so as to be larger than 0.
Likewise, the dead time td 2 depends on the turn-on delay characteristic of the second transistor M 2 , the delay characteristic of the first current detecting section 12 , the gate delay characteristic of the drive section 14 , and the phase-advancing effect obtained by setting the first reference value Iref 1 so as to be larger than 0.
As a result, by increasing the first reference value Iref 1 , the phase-advancing effect is increased, and the dead time td 2 can be shortened. On the other hand, if the first reference value Iref 1 is decreased, the phase-advancing effect is decreased, and the dead time td 2 is made longer.
If the first reference value Iref 1 is set at zero, the phase-advancing effect of the first reference value Iref 1 disappears, as a result of which a dead time occurs which depends on the turn-on delay characteristic of the second transistor M 2 , the delay characteristic of the first current detecting section 12 , and the gate delay characteristic of the drive section 14 .
If the first reference value Iref 1 is set too large, the phase-advancing effect of the first reference value Iref 1 becomes greater than the total effect of the turn-on delay characteristic of the second transistor M 2 , the delay characteristic of the first current detecting section 12 , and the gate delay characteristic of the drive section 14 and the dead time td 2 becomes negative. Therefore, a flow-through current occurs.
In consideration of the above-mentioned matter, the first reference value Iref 1 is set to smaller than or equal to, for example, 1/100 of the peak first current Ip 1 of the first transistor M 1 . Alternatively, the first reference value Iref 1 may be set in a range of 1/500 to 1/1000 of the peak first current Ip 1 .
Likewise, the dead time td 1 can be shortened by increasing the second reference value Iref 2 . On the other hand, the dead time td 1 is made longer if the second reference value Iref 2 is decreased.
If the second reference value Iref 2 is set at zero, the phase-advancing effect of the second reference value Iref 2 disappears, as a result of which a dead time occurs which depends on the turn-on delay characteristic of the first transistor M 1 , the delay characteristic of the second current detecting section 13 , and the gate delay characteristic of the drive section 14 .
If the second reference value Iref 2 is set too large, the phase-advancing effect of the second reference value Iref 2 becomes greater than the total effect of the turn-on delay characteristic of the first transistor M 1 , the delay characteristic of the second current detecting section 13 , and the gate delay characteristic of the drive section 14 and the dead time td 1 becomes negative. Therefore, a flow-through current occurs.
In consideration of the above-mentioned matter, the second reference value Iref 2 is set to smaller than or equal to, for example, 1/100 of the peak second current Ip 2 of the second transistor M 2 . Alternatively, the second reference value Iref 2 may be set in a range of 1/500 to 1/1000 of the peak second current Ip 2 .
Furthermore, it is possible to make the dead time td 2 equal to zero by balancing the total effect of the turn-on delay characteristic of the second transistor M 2 , the delay characteristic of the first current detecting section 12 , and the gate delay characteristic of the drive section 14 with the phase-advancing effect of the first reference value Iref 1 .
Likewise, it is possible to make the dead time td 1 equal to zero by balancing the total effect of the turn-on delay characteristic of the first transistor M 1 , the delay characteristic of the second current detecting section 13 , and the gate delay characteristic of the drive section 14 with the phase-advancing effect of the second reference value Iref 2 .
Next, a description will be made of a semiconductor integrated circuit of the DC-DC converter 10 .
As shown in FIG. 5, a semiconductor integrated circuit 40 of the DC-DC converter 10 is configured in such a manner that an output section 11 having a series connection of a first transistor M 1 and a second transistor M 2 , a first current detecting section 12 which monitors a first current I 1 flowing through the first transistor M 1 and outputs a first control signal for turning on the second transistor M 2 if the first current I 1 becomes smaller than a first reference value Iref 1 , a second current detecting section 13 which monitors a second current I 2 flowing through the second transistor M 2 and outputs a second control signal for turning on the first transistor M 1 if the second current I 2 becomes smaller than a second reference value Iref 2 , and a drive section 14 which turns off the first transistor M 1 and turns on the second transistor M 2 in response to the first control signal and also turns off the second transistor M 2 and turns on the first transistor M 1 in response to the second control signal are integrated monolithically on a single chip 41 .
For example, the first transistor M 1 and the second transistor M 2 of the output section 11 are a p-MOS transistor and an n-MOS transistor, respectively, and thus constitute a CMOS circuit. It is preferable that they be formed in a region that is shielded by a guard ring so that switching noise does not affect nearby circuits.
Bonding pads 42 a - 42 d which are necessary for receiving an external PWM signal 20 and outputs a PWM-controlled output voltage to the outside are formed on the semiconductor chip 41 .
As described above, in the DC-DC converter 10 according to this embodiment, the first and second currents I 1 and I 2 flowing through the first and second transistors M 1 and M 2 , respectively, are monitored. An operation of turning on the second transistor M 2 is started immediately before the first current I 1 flowing through the first transistor (high-side transistor) M 1 becomes zero. And an operation of turning on the first transistor M 1 is started immediately before the second current I 2 flowing through the second transistor M 2 becomes zero.
As a result, the dead times td 1 and td 2 can reliably be confined in a narrow range around td=0 even if the turn-on/off delay characteristics of the first and second transistors M 1 and M 2 vary.
Therefore, noise can be reduced and the DC-DC conversion efficiency can be kept high even if the frequency of the PWM signal 20 becomes high. The DC-DC converter 10 can thus be given sufficiently high conversion efficiency.
Although the above description is directed to the case that the first and second reference values Iref 1 and Iref 2 are identical, they may be different from each other.
This provides an advantage that the dead times td 1 and td 2 equalized by adjusting the first and second reference values Iref 1 and Iref 2 in the case where the first and second transistors M 1 and M 2 have different turn-off delay characteristics.
Although the above description is directed to the case that the first and second transistors M 1 and M 2 are MOS transistors, they may be bipolar transistors or insulated-gate bipolar transistors (IGBTs).
Where bipolar transistors or IGBTs are used which are not accompanied by body diodes unlike in the case of MOS transistors, it is necessary to add external diodes for bypassing regenerative currents.
Although the above description is directed to the case that the third to eighth transistors of the first and second current detecting sections 12 and 13 are MOS transistors, they may be bipolar transistors.
Although the semiconductor integrated circuit 40 was described above as being such that the first and second transistors M 1 and M 2 of the output section 11 are integrated monolithically on the single chip 41 , the output section 11 may be composed of external, discrete MOS transistors.
Although the turn-on/off delay characteristics of discrete MOS transistors have larger variations than those of integrated MOS transistors, this embodiment is advantageous in not being affected by such variations.
FIG. 6 is a circuit diagram showing the configuration of a DC-DC converter according to a second embodiment. Components having the same ones in the first embodiment will be given the same reference symbols as the latter and will not be described. That is, only different features will be described.
This embodiment is different from the first embodiment in that the first and second currents flowing through the first and second transistors are detected by using resistors.
More specifically, as shown in FIG. 6, a DC-DC converter 50 according to this embodiment includes a first current detecting section 52 which includes a differential amplifier 54 whose positive and negative input terminals are connected to the two respective ends of a resistor R 7 (first current detecting element) for detecting a first current I 1 flowing through the first transistor M 1 , a first reference value generation circuit 55 which outputs a first reference voltage Vref 1 according to a first reference value, and a comparator 56 which compares an output of the differential amplifier 54 with the first reference voltage Vref 1 and outputs a comparison result to the inverter 21 the drive section 14 . The current detecting resistor R 7 is connected between the high-potential power supply side and the first transistor M 1 .
Likewise, the DC-DC converter 50 includes a second current detecting section 53 which includes a differential amplifier 57 whose positive and negative input terminals are connected to the two respective ends of a resistor R 8 (second current detecting element) for detecting a second current I 2 flowing through the second transistor M 2 , a second reference value generation circuit 58 which outputs a second reference voltage Vref 2 according to a second reference value, and a comparator 59 which compares an output of the differential amplifier 57 with the second reference voltage Vref 2 and outputs a comparison result to the inverter 23 of the drive section 14 . The current detecting resistor R 8 is connected between the low-potential power supply side and the second transistor M 2 .
Let Ga 1 represent the gain of the differential amplifier 54 ; then, the output voltage of the differential amplifier 54 is given by I 1 ×R 7 ×Ga 1 . Therefore, by setting the first reference voltage Vref 1 equal to 0.01×Ip 1 ×R 7 ×Ga 1 , the comparator 56 can detect an instant when the first current I 1 flowing through the first transistor M 1 becomes smaller than the first reference value Iref 1 .
Likewise, let Ga 2 represent the gain of the differential amplifier 57 ; then, the output voltage of the differential amplifier 57 is given by I 2 ×R 8 ×Ga 2 . Therefore, by setting the second reference voltage Vref 2 equal to 0.01×Ip 2 ×R 8 ×Ga 2 , the comparator 59 can detect an instant when the second current I 2 flowing through the second transistor M 2 becomes smaller than the second reference value Iref 2 .
As described above, in the DC-DC converter 50 according to this embodiment, the first and second currents I 1 and I 2 are converted by the resistors R 7 and R 8 into voltages, which are compared with the first and second reference voltages Vref 1 and Vre 2 corresponding to the first and second reference values, respectively. As such, the DC-DC converter 50 is advantageous in that the circuits of the first and second current detecting sections 52 and 53 are simplified.
For example, the DC-DC converter 50 is suitably used within a relatively low current range in which detected current values does not be influenced by parasitic inductances of the resistors R 7 and R 8 .
Although the above description is directed to the case that the first and second current detecting elements are resistors, they are not restricted to any elements as long as they can detect target currents.
FIG. 7 is a circuit diagram showing the configuration of a DC-DC converter according to a third embodiment. Components having the same ones in the first embodiment will be given the same reference symbols as the latter and will not be described. That is, only different features will be described.
This embodiment is different from the first embodiment in that the DC-DC converter is of a boost type rather than the step-down type.
More specifically, as shown in FIG. 7, in a DC-DC converter 60 according to this embodiment, the first transistor M 1 is connected between the high-potential power supply side and the output terminal LX via an inductor L and the second transistor M 2 is connected between the high-potential power supply side and the reference potential GND via the inductor L.
As described above, constructed by using the first and second current detecting sections 12 and 13 , the boost type DC-DC converter 60 is advantageous in that the dead times have only small variations and an output voltage that is higher than an input voltage can be obtained stably.
The above description is directed to the case that the DC-DC converter 60 is of the boost type rather than the step-down type. Alternatively, an inversion type DC-DC converter 70 may be constructed as shown in FIG. 8A. As a further alternative, a boost/step-down type DC-DC converter 80 may be constructed as shown in FIG. 8B.
In the voltage boosting type DC-DC converter 80 , two sets of the first current detecting section 12 , the second current detecting section 13 , and the drive section 14 are connected to a boosting section and a step-down section, respectively.
According to an aspect of the present invention, there is provided a DC-DC converter having sufficiently high conversion efficiency.