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Title:
CURRENT GENERATING APPARATUS AND FEEDBACK-CONTROLLED SYSTEM UTILIZING THE CURRENT GENERATING APPARATUS
Document Type and Number:
Kind Code:
A1
Abstract:
The present invention discloses a current generating apparatus for generating an output current. The current generating apparatus includes: a first current mirror; a first bias current generator for providing a first bias current, and the first bias current generator includes: a first current source for providing the first current; and a capacitive device for conducting a reference current; a second current mirror for generating a second mirror current; a second bias current generator for generating a second current; a third current source for providing a third current, wherein the second mirror current is equal to the third current; a feedback circuit; and a fourth current source for providing a fourth current, wherein the output current is outputted at an output node of the first current mirror.
Inventors:
Lee, Chien-lung (Hsinchu City, TW)
Huang, Yi-wen (Tainan County, TW)
Huang, Yi-wen (Tainan County, TW)
Plaque It!
Sponsored by: Flash of Genius |
Application Number:
11/567228
Publication Date:
03/20/2008
Filing Date:
12/06/2006
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Referenced by:
Export Citation:
Primary Class:
International Classes:
G05F1/00
Attorney, Agent or Firm:
NORTH AMERICA INTELLECTUAL PROPERTY CORPORATION (P.O. BOX 506, MERRIFIELD, VA, 22116, US)
Claims:
What is claimed is:
1. A current generating apparatus, for generating an output current, comprising: a first current mirror, for generating a first mirror current according to a first bias current and a current mirror ratio; a first bias current generator, coupled to the first current mirror, for providing the first bias current according to a first current and a reference current, the first bias current generator comprising: a first current source, biased by a first bias voltage for providing the first current; and a capacitive device, coupled to the first current source in parallel, for conducting the reference current; a second current mirror, for generating a second mirror current according to a second bias current and the current mirror ratio; a second bias current generator, coupled to the second current mirror, the second bias current generator having a second current source biased by the first bias voltage for generating a second current serving as the second bias current; a third current source, coupled to an output node of the second current mirror, the third current source being biased by a second bias voltage for providing a third current, wherein the second mirror current is equal to the third current; a feedback circuit, coupled to the output node of the second current mirror and the third current source, for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level; and a fourth current source, coupled to an output node of the first current mirror, the fourth current source being biased by the second bias voltage for providing a fourth current, wherein the output current is outputted at the output node of the first current mirror.
2. The current generating apparatus of claim 1, wherein the first current source comprises a first transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to a first reference voltage level; the second current source comprises a second transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to the first reference voltage level, and the first bias current generator further comprises: a third transistor, having a first node coupled to the first current mirror, a second node coupled to the first node of the first transistor, and a control node; and a first error amplifier, having a first input node coupled to a second reference voltage level, a second input node coupled to the second node of the third transistor, and an output node coupled to the control node of the third transistor; and the second bias current generator further comprises: a fourth transistor, having a first node coupled to the second current mirror, a second node coupled to the first node of the second transistor, and a control node; and a second error amplifier, having a first input node coupled to the second reference voltage level, a second input node coupled to the second node of the fourth transistor, and an output node coupled to the control node of the fourth transistor.
3. The current generating apparatus of claim 1, wherein the third current source comprises a fifth transistor having a control node for receiving the second bias voltage, a first node coupled to the output node of the second current mirror, and a second node coupled to the first reference voltage level; the fourth current source comprises a sixth transistor having a control node coupled to the control node of the fifth transistor, a first node coupled to the output node of the first current mirror, and a second node coupled to the first reference voltage level, and the feedback circuit comprises: a third error amplifier, having a first input node coupled to the first node of the fifth transistor, a second input node coupled to the target voltage level, and an output node coupled to the control node of the fifth transistor.
4. A feedback-controlled system, comprising: a plurality of operational stages cascaded in a closed loop; and a current generating apparatus, for generating an output current to an output of a first operational stage in the operational stages, the current generating apparatus comprising: a first current mirror, for generating a first mirror current according to a first bias current and a current mirror ratio; a first bias current generator, coupled to the first current mirror, for receiving an output of a second operational stage in the operational stages and providing the first bias current according to a first current and a reference current, the first bias current generator comprising: a first current source, for providing the first current according to a first bias voltage and the output of the second operational stage; and a capacitive device, coupled to the first current source in parallel, for conducting the reference current; a second current mirror, for generating a second mirror current according to a second bias current and the current mirror ratio; a second bias current generator, coupled to the second current mirror, the second bias current generator having a second current source for generating a second current serving as the second bias current according to the first bias voltage and the output of the second operational stage; a third current source, coupled to an output node of the second current mirror, the third current source being biased by a second bias voltage for providing a third current, wherein the second mirror current is equal to the third mirror current; a feedback circuit, coupled to the output node of the second current mirror and the third current source, for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level; and a fourth current source, coupled to an output node of the first current mirror, the fourth current source being biased by the second bias voltage for providing a fourth current, wherein the output current is outputted from the output node of the first current mirror.
5. The feedback-controlled system of claim 4, wherein the first current source comprises a first transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to a first reference voltage level; the second current source comprises a second transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to the first reference voltage level, and the first bias current generator further comprises: a third transistor, having a first node coupled to the first current mirror, a second node coupled to the first node of the first transistor, and a control node; and a first error amplifier, having a first input node coupled to a second reference voltage level, a second input node coupled to the second node of the third transistor, and an output node coupled to the control node of the third transistor; and the second bias current generator further comprises: a fourth transistor, having a first node coupled to the second current mirror, a second node coupled to the first node of the second transistor, and a control node; and a second error amplifier, having a first input node coupled to the second reference voltage level, a second input node coupled to the second node of the fourth transistor, and an output node coupled to the control node of the fourth transistor.
6. The feedback-controlled system of claim 4, wherein the third current source comprises a fifth transistor having a control node for receiving the second bias voltage, a first node coupled to the output node of the second current mirror, and a second node coupled to the first reference voltage level; the fourth current source comprises a sixth transistor having a control node coupled to the control node of the fifth transistor, a first node coupled to the output node of the first current mirror, and a second node coupled to the first reference voltage level, and the feedback circuit comprises: a third error amplifier, having a first input node coupled to the first node of the fifth transistor, a second node coupled to the target voltage level, and an output node coupled to the control node of the fifth transistor.
7. The feedback-controlled system of claim 4, wherein the current generating apparatus further comprises: a loading sensing circuit, coupled to the first current mirror and the second current mirror, for sensing loading variation of the feedback-controlled system to adjust the current mirror ratio of the first current mirror and the second current mirror.
8. The feedback-controlled system of claim 7, wherein the loading sensing circuit decreases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the feedback-controlled system increases, and the loading sensing circuit increases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the feedback-controlled system decreases.
9. The feedback-controlled system of claim 4, being a voltage regulator, wherein the second operational stage comprises a pass transistor, the first operational stage is a voltage divider for providing a feedback voltage level according to an output voltage level passed by the pass transistor; and the operational stages also include a third operational stage comprising a fourth error amplifier having a first input node coupled to the voltage divider for receiving the feedback voltage level, a second input node coupled to the target voltage level, and an output node coupled to a control node of the pass transistor.
10. The feedback-controlled system of claim 9, wherein the first current source comprises a first transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to a first reference voltage level; the second current source comprises a second transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to the first reference voltage level, and the first bias current generator further comprises: a third transistor, having a first node coupled to the first current mirror, a second node coupled to the first node of the first transistor, and a control node; and a first error amplifier, having a first input node coupled to a second reference voltage level, a second input node coupled to the second node of the third transistor, and an output node coupled to the control node of the third transistor; and the second bias current generator further comprises: a fourth transistor, having a first node coupled to the second current mirror, a second node coupled to the first node of the second transistor, and a control node; and a second error amplifier, having a first input node coupled to the second reference voltage level, a second input node coupled to the second node of the fourth transistor, and an output node coupled to the control node of the fourth transistor.
11. The feedback-controlled system of claim 9, wherein the third current source comprises a fifth transistor having a control node for receiving the second bias voltage, a first node coupled to the output node of the second current mirror, and a second node coupled to the first reference voltage level; the fourth current source comprises a sixth transistor having a control node coupled to the control node of the fifth transistor, a first node coupled to the output node of the first current mirror, and a second node coupled to the first reference voltage level, and the feedback circuit comprises: a third error amplifier, having a first input node coupled to the first node of the fifth transistor, a second node coupled to the target voltage level, and an output node coupled to the control node of the fifth transistor.
12. The feedback-controlled system of claim 9, wherein the current generating apparatus further comprises: a loading sensing circuit, coupled to the first current mirror and the second current mirror, for sensing loading variation of the voltage regulator to adjust the current mirror ratio of the first current mirror and the second current mirror.
13. The feedback-controlled system of claim 12, wherein the loading sensing circuit decreases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the voltage regulator increases, and the loading sensing circuit increases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the voltage regulator decreases.
1. A current generating apparatus, for generating an output current, comprising: a first current mirror, for generating a first mirror current according to a first bias current and a current mirror ratio; a first bias current generator, coupled to the first current mirror, for providing the first bias current according to a first current and a reference current, the first bias current generator comprising: a first current source, biased by a first bias voltage for providing the first current; and a capacitive device, coupled to the first current source in parallel, for conducting the reference current; a second current mirror, for generating a second mirror current according to a second bias current and the current mirror ratio; a second bias current generator, coupled to the second current mirror, the second bias current generator having a second current source biased by the first bias voltage for generating a second current serving as the second bias current; a third current source, coupled to an output node of the second current mirror, the third current source being biased by a second bias voltage for providing a third current, wherein the second mirror current is equal to the third current; a feedback circuit, coupled to the output node of the second current mirror and the third current source, for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level; and a fourth current source, coupled to an output node of the first current mirror, the fourth current source being biased by the second bias voltage for providing a fourth current, wherein the output current is outputted at the output node of the first current mirror.
2. The current generating apparatus of claim 1, wherein the first current source comprises a first transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to a first reference voltage level; the second current source comprises a second transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to the first reference voltage level, and the first bias current generator further comprises: a third transistor, having a first node coupled to the first current mirror, a second node coupled to the first node of the first transistor, and a control node; and a first error amplifier, having a first input node coupled to a second reference voltage level, a second input node coupled to the second node of the third transistor, and an output node coupled to the control node of the third transistor; and the second bias current generator further comprises: a fourth transistor, having a first node coupled to the second current mirror, a second node coupled to the first node of the second transistor, and a control node; and a second error amplifier, having a first input node coupled to the second reference voltage level, a second input node coupled to the second node of the fourth transistor, and an output node coupled to the control node of the fourth transistor.
3. The current generating apparatus of claim 1, wherein the third current source comprises a fifth transistor having a control node for receiving the second bias voltage, a first node coupled to the output node of the second current mirror, and a second node coupled to the first reference voltage level; the fourth current source comprises a sixth transistor having a control node coupled to the control node of the fifth transistor, a first node coupled to the output node of the first current mirror, and a second node coupled to the first reference voltage level, and the feedback circuit comprises: a third error amplifier, having a first input node coupled to the first node of the fifth transistor, a second input node coupled to the target voltage level, and an output node coupled to the control node of the fifth transistor.
4. A feedback-controlled system, comprising: a plurality of operational stages cascaded in a closed loop; and a current generating apparatus, for generating an output current to an output of a first operational stage in the operational stages, the current generating apparatus comprising: a first current mirror, for generating a first mirror current according to a first bias current and a current mirror ratio; a first bias current generator, coupled to the first current mirror, for receiving an output of a second operational stage in the operational stages and providing the first bias current according to a first current and a reference current, the first bias current generator comprising: a first current source, for providing the first current according to a first bias voltage and the output of the second operational stage; and a capacitive device, coupled to the first current source in parallel, for conducting the reference current; a second current mirror, for generating a second mirror current according to a second bias current and the current mirror ratio; a second bias current generator, coupled to the second current mirror, the second bias current generator having a second current source for generating a second current serving as the second bias current according to the first bias voltage and the output of the second operational stage; a third current source, coupled to an output node of the second current mirror, the third current source being biased by a second bias voltage for providing a third current, wherein the second mirror current is equal to the third mirror current; a feedback circuit, coupled to the output node of the second current mirror and the third current source, for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level; and a fourth current source, coupled to an output node of the first current mirror, the fourth current source being biased by the second bias voltage for providing a fourth current, wherein the output current is outputted from the output node of the first current mirror.
5. The feedback-controlled system of claim 4, wherein the first current source comprises a first transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to a first reference voltage level; the second current source comprises a second transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to the first reference voltage level, and the first bias current generator further comprises: a third transistor, having a first node coupled to the first current mirror, a second node coupled to the first node of the first transistor, and a control node; and a first error amplifier, having a first input node coupled to a second reference voltage level, a second input node coupled to the second node of the third transistor, and an output node coupled to the control node of the third transistor; and the second bias current generator further comprises: a fourth transistor, having a first node coupled to the second current mirror, a second node coupled to the first node of the second transistor, and a control node; and a second error amplifier, having a first input node coupled to the second reference voltage level, a second input node coupled to the second node of the fourth transistor, and an output node coupled to the control node of the fourth transistor.
6. The feedback-controlled system of claim 4, wherein the third current source comprises a fifth transistor having a control node for receiving the second bias voltage, a first node coupled to the output node of the second current mirror, and a second node coupled to the first reference voltage level; the fourth current source comprises a sixth transistor having a control node coupled to the control node of the fifth transistor, a first node coupled to the output node of the first current mirror, and a second node coupled to the first reference voltage level, and the feedback circuit comprises: a third error amplifier, having a first input node coupled to the first node of the fifth transistor, a second node coupled to the target voltage level, and an output node coupled to the control node of the fifth transistor.
7. The feedback-controlled system of claim 4, wherein the current generating apparatus further comprises: a loading sensing circuit, coupled to the first current mirror and the second current mirror, for sensing loading variation of the feedback-controlled system to adjust the current mirror ratio of the first current mirror and the second current mirror.
8. The feedback-controlled system of claim 7, wherein the loading sensing circuit decreases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the feedback-controlled system increases, and the loading sensing circuit increases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the feedback-controlled system decreases.
9. The feedback-controlled system of claim 4, being a voltage regulator, wherein the second operational stage comprises a pass transistor, the first operational stage is a voltage divider for providing a feedback voltage level according to an output voltage level passed by the pass transistor; and the operational stages also include a third operational stage comprising a fourth error amplifier having a first input node coupled to the voltage divider for receiving the feedback voltage level, a second input node coupled to the target voltage level, and an output node coupled to a control node of the pass transistor.
10. The feedback-controlled system of claim 9, wherein the first current source comprises a first transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to a first reference voltage level; the second current source comprises a second transistor having a control node coupled to the first bias voltage, a first node, and a second node coupled to the first reference voltage level, and the first bias current generator further comprises: a third transistor, having a first node coupled to the first current mirror, a second node coupled to the first node of the first transistor, and a control node; and a first error amplifier, having a first input node coupled to a second reference voltage level, a second input node coupled to the second node of the third transistor, and an output node coupled to the control node of the third transistor; and the second bias current generator further comprises: a fourth transistor, having a first node coupled to the second current mirror, a second node coupled to the first node of the second transistor, and a control node; and a second error amplifier, having a first input node coupled to the second reference voltage level, a second input node coupled to the second node of the fourth transistor, and an output node coupled to the control node of the fourth transistor.
11. The feedback-controlled system of claim 9, wherein the third current source comprises a fifth transistor having a control node for receiving the second bias voltage, a first node coupled to the output node of the second current mirror, and a second node coupled to the first reference voltage level; the fourth current source comprises a sixth transistor having a control node coupled to the control node of the fifth transistor, a first node coupled to the output node of the first current mirror, and a second node coupled to the first reference voltage level, and the feedback circuit comprises: a third error amplifier, having a first input node coupled to the first node of the fifth transistor, a second node coupled to the target voltage level, and an output node coupled to the control node of the fifth transistor.
12. The feedback-controlled system of claim 9, wherein the current generating apparatus further comprises: a loading sensing circuit, coupled to the first current mirror and the second current mirror, for sensing loading variation of the voltage regulator to adjust the current mirror ratio of the first current mirror and the second current mirror.
13. The feedback-controlled system of claim 12, wherein the loading sensing circuit decreases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the voltage regulator increases, and the loading sensing circuit increases the current mirror ratio of the first current mirror and the second current mirror when detecting that the loading of the voltage regulator decreases.
Description:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/826,076, which was filed on Sep. 18, 2006 and is included herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to providing frequency compensation, and more particularly, to a feedback-controlled system (e.g., an LDO voltage regulator) using a current generating apparatus capable of minimizing the DC offset of an output current used for frequency compensation.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a first conventional LDO (low dropout) voltage regulator 10 . The LDO voltage regulator 10 comprises a pass transistor MP, a feedback voltage divider 11 , and an error amplifier 12 . The connections between the pass transistor MP, the feedback voltage divider 11 , and the error amplifier 12 are shown in FIG. 1. The input terminal N in of the LDO voltage regulator 10 is coupled to a supply voltage VDD. The output terminal N out of the LDO voltage regulator 10 is coupled to a loading stage, which is equivalent to a resistor R L connected with a capacitor C L in parallel. Please note that the terminal N g has a parasitic resistor R PAR and a parasitic capacitor C PAR , where the capacitor C L has an equivalent series resistance of R ESR connected to the capacitor C L . Accordingly, it is well-known that there are two low-frequency poles that need to be taken into account when determining the closed-loop transfer function of the frequency response of the LDO voltage regulator 10 . In order to guarantee the phase margin of the LDO voltage regulator 10 will be greater than 45 degrees, a zero is introduced to compensate the phase contribution of the two low-frequency poles. Normally, the series combination of the capacitor C L and the equivalent series resistance R ESR generates a zero ω ESR that provides the LDO voltage regulator 10 with proper phase margin. However, in some conditions, the equivalent series resistance R ESR fails to provide proper phase margin for the LDO voltage regulator 10 . Please refer to FIG. 2. FIG. 2 is a frequency response diagram of the LDO voltage regulator 10 with various load currents I L at fixed ω ESR . For brevity, three Bode plots 21 , 22 , and 23 are shown in FIG. 2, which correspond, respectively, to light load current, proper load current, and heavy load current of the LDO voltage regulator 10 . Furthermore, there are three poles and one zero for each of the Bode plots 21 , 22 , and 23 , in which the first pole ω p1 is mainly concentrated at the output terminal N out , the second pole ω p2 is mainly concentrated at the terminal N g of the transistor MP, and the zero is ω ESR . When the load current I L varies from the heavy load status to the light load status, the first pole ω p1 decreases roughly and the second pole ω p2 decreases as well, as shown in the Bode plots 21 , 22 , and 23 of FIG. 2. Furthermore, three of the Bode plots 21 , 22 , and 23 have poor phase margin in this case. There are at least three drawbacks by utilizing the zero ω ESR to compensate the pole of the LDO voltage regulator 10 . Firstly, the high-frequency bypass capacitor C gdpass placed in parallel with the capacitor C L provides another pole with the zero ω ESR of the capacitor C L , in which the new pole will further decrease the phase margin of the LDO voltage regulator 10 . Secondly, the equivalent series resistance of R ESR of the capacitor C L is not properly specified in many cases and varies with temperature. As a result, the zero ω ESR cannot be predicted easily. Thirdly, owing to some advantages of ceramic capacitors, such as low R ESR , less expense, and compact printed circuit boards, using the ceramic capacitor is becoming more popular. However, it is hard to generate a proper zero ω ESR with the low R ESR .
Besides utilizing the zero ω ESR to compensate the pole of the LDO voltage regulator 10 , there are various other frequency compensation means taught in the prior art. Please refer to FIG. 3. FIG. 3 is a diagram illustrating a second conventional LDO voltage regulator 30 having a prior art frequency compensation implemented therein. The LDO voltage regulator 30 shown in FIG. 3 is equivalent to applying the prior art frequency compensation to the LDO voltage regulator 10 . The frequency compensation method of FIG. 3 is to provide a feedback path for the output voltage V out through an additional capacitor CF, and the connection is shown in FIG. 3. The capacitor CF provides a high-frequency bypass path for the loop gain of the LDO voltage regulator 10 . Then a pole-zero pair (ω p , ω z ) is generated, which is represented by the following equation (1) and equation (2),
ω z =1/( R F1 *CF ), (1)
ω p =(1+( R F1 /R F2 ))/( R F1 *CF ) (2)
According to this prior art circuit configuration, due to the fact that the resistance magnitudes of feedback resistors R F1 and R F2 have the same order, the pole ω p and the zero ω z are not far from each other as shown in FIG. 4. FIG. 4 is a diagram illustrating the frequency response of capacitive feedback frequency compensation of FIG. 3. The curve 41 represents the transferring characteristic of the frequency compensation of FIG. 3, and the curve 42 represents the phase variation of the frequency compensation of FIG. 3. Accordingly, the zero ω z contributes less phase margin for the frequency compensation of FIG. 3.
According to the reference of Chaitanya K. Chaya, and Jose Silva-Martinez, “A Frequency Compensation Scheme for LDO Voltage Regulators”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I. REGULAR PAPERS, VOL. 51, NO. 6, JUN. 2004, an improved prior art frequency compensation developed from the frequency compensation of FIG. 3 is proposed. Please refer to FIG. 5. FIG. 5 is a diagram illustrating a third conventional LDO voltage regulator 50 having another prior art frequency compensation implemented therein. The LDO voltage regulator 50 shown in FIG. 5 is equivalent to applying the improved prior art frequency compensation to the LDO voltage regulator 10 . The frequency compensation of FIG. 5 is implemented using a frequency-dependent voltage-controlled current source (VCCS) 52 connected at the feedback terminal N FB of the LDO voltage regulator 50 . The frequency-dependent VCCS 52 is capable of eliminating the pole ω p of FIG. 3 and generate a new zero ω z0 . The new zero ω z0 is determined by the following equation:
ω z0 =1/( N*R F1 *CF ). (3)
Therefore, the location of the new zero ω z0 can be easily adjusted by modifying the current mirror ratio N set to the current mirrors 54 a , 54 b or modifying the capacitance of the ground capacitor C 1 of the FIG. 6. FIG. 6 is a diagram illustrating the frequency-dependent voltage-controlled current source 52 shown in FIG. 5. However, the mismatch of the current mirror 54 a and the current mirror 54 b , both having the same current mirror ratio N, induces a DC current ΔI B flowing into the feedback resistors R F1 , R F2 , and equivalently forms a mismatch resistor R mismatch parallel with the feedback resistors R F1 , R F2 as shown in FIG. 6. Hence, the output voltage V out varies due to the mismatch resistor R mismatch from the imbalanced current mirrors 54 a , 54 b . Furthermore, the mismatch of current mirrors 54 a , 54 b contributes considerable yield loss for chip mass production. In addition, the mismatch current ΔI B is in proportion to the current mirror ratio N of current mirrors 54 a , 54 b . Furthermore, as the output voltage V out changes, the mismatch current ΔI B changes accordingly. In order to decrease the effect of the mismatch current ΔI B , the current mirror ratio N of the current mirrors 54 a , 54 b should preferably be lower, and the capacitance of the grounded capacitor C 1 should preferably be larger. However, the larger the capacitance, the higher the production cost and chip area becomes.
SUMMARY OF THE INVENTION
Therefore, one of the objectives of the present invention is to provide a feedback-controlled system (e.g. an LDO voltage regulator) using a current generating apparatus capable of minimizing the DC offset of an output current used for frequency compensation.
According to an embodiment of the present invention, a current generating apparatus is disclosed for generating an output current. The current generating apparatus comprises: a first current mirror, a first bias current generator, a second current mirror, a second bias current generator, a third current source, a feedback circuit, and a fourth current source. The first current mirror generates a first mirror current according to a first bias current and a current mirror ratio. The first bias current generator is coupled to the first current mirror for providing the first bias current according to a first current and a reference current, and the first bias current generator comprises: a first current source biased by a first bias voltage for providing the first current; and a capacitive device coupled to the first current source in parallel for conducting the reference current. The second current mirror generates a second mirror current according to a second bias current and the current mirror ratio. The second bias current generator is coupled to the second current mirror, and the second bias current generator has a second current source biased by the first bias voltage for generating a second current serving as the second bias current. The third current source is coupled to an output node of the second current mirror, and is biased by a second bias voltage to provide a third current, wherein the second mirror current is equal to the third current. The feedback circuit is coupled to the output node of the second current mirror and the third current source for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level. The fourth current source is coupled to an output node of the first current mirror, and is biased by the second bias voltage to provide a fourth current, wherein the output current is outputted at the output node of the first current mirror.
According to an embodiment of the present invention, a feedback-controlled system is disclosed. The feedback-controlled system comprises: a plurality of operational stages cascaded in a closed loop; and a current generating apparatus. The current generating apparatus generates an output current to an output of a first operational stage in the operational stages. The current generating apparatus comprises: a first current mirror, a first bias current generator, a second current mirror, a second bias current generator, a third current source, a feedback circuit, and a fourth current source. The first current mirror generates a first mirror current according to a first bias current and a current mirror ratio. The first bias current generator is coupled to the first current mirror for receiving an output of a second operational stage in the operational stages and providing the first bias current according to a first current and a reference current. The first bias current generator comprises: a first current source for providing the first current according to a first bias voltage and the output of the second operational stage; and a capacitive device coupled to the first current source in parallel for conducting the reference current. The second current mirror generates a second mirror current according to a second bias current and the current mirror ratio. The second bias current generator is coupled to the second current mirror, and the second bias current generator has a second current source for generating a second current serving as the second bias current according to the first bias voltage and the output of the second operational stage. The third current source is coupled to an output node of the second current mirror, and is biased by a second bias voltage to provide a third current, wherein the second mirror current is equal to the third mirror current. The feedback circuit is coupled to the output node of the second current mirror and the third current source for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level. The fourth current source is coupled to an output node of the first current mirror, and is biased by the second bias voltage to provide a fourth current, wherein the output current is outputted from the output node of the first current mirror.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a prior art LDO voltage regulator.
FIG. 2 is a frequency response diagram of the LDO voltage regulator.
FIG. 3 is a diagram illustrating a frequency compensation according to the prior art utilized in the LDO voltage regulator of FIG. 1.
FIG. 4 is a diagram illustrating the frequency response of the capacitive feedback frequency compensation of FIG. 3.
FIG. 5 is a diagram illustrating the prior art frequency compensation that improves on the frequency compensation of FIG. 3.
FIG. 6 is a diagram illustrating the prior art frequency-dependent voltage-controlled current source of FIG. 5.
FIG. 7 is a diagram illustrating a voltage regulator according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating the voltage-controlled current source in the voltage regulator of FIG. 7.
FIG. 9 is a diagram illustrating an equivalent schematic of the voltage-controlled current source in the voltage regulator of FIG. 7.
FIG. 10 is a diagram illustrating the frequency response of the voltage regulator of FIG. 7.
FIG. 11 is a diagram of a feedback-controlled system according to a second embodiment of the present invention.
DETAILED DESCRIPTION
Please refer to FIG. 7. FIG. 7 is a diagram illustrating a voltage regulator 100 according to an embodiment of the present invention. The voltage regulator 100 is a low dropout (LDO) voltage regulator that can track the loading current of the voltage regulator 100 to adjust the zero of the voltage regulator 100 . The voltage regulator 100 comprises a pass transistor M p , a voltage divider 101 , an error amplifier 102 , a loading sensing circuit 103 , and a voltage-controlled current source (VCCS) 104 . The pass transistor M p , which is a PMOS transistor, has a source terminal N in coupled to a supply voltage V dd and a drain terminal N out for outputting an output voltage V out . The voltage divider 101 comprises two feedback resistors R F1 and R F2 , connected in series, where the feedback resistor R F1 has a terminal coupled to the drain terminal N out and another terminal coupled to the feedback resistor R F2 . The voltage divider 101 is utilized for providing a feedback voltage level V FB according to the output voltage V out passed by the pass transistor M p . The error amplifier 102 has a first input node (i.e. a non-inverting node) N+ coupled to the voltage divider 101 for receiving the feedback voltage level V FB , a second input node (i.e. an inverting node) N− coupled to the target voltage level V ref , and an output node N g coupled to a gate terminal of the pass transistor M p . The voltage-controlled current source 104 is coupled to the voltage divider 101 (i.e. the first input node N+) for generating an output current I ac at the first input node N+ of the error amplifier 102 , in which the output current I ac is a voltage-controlled AC current. The loading sensing circuit 103 is coupled to the voltage-controlled current source 104 and the gate terminal N g (i.e. the output node) of the pass transistor M P , for sensing the loading current I Load variation of the voltage regulator 100 to adjust the output current I ac of the voltage-controlled current source 104 . Furthermore, the drain terminal N out is coupled to a loading circuit, which is equivalent to a loading resistor R L connected with a loading capacitor C L in parallel. Please note that the loading capacitor C L has an equivalent series resistance of R ESR connected with the loading capacitor C L . The output node N g is connected to a parasitic resistor R PAR and a parasitic capacitor C PAR in parallel.
Please refer to FIG. 8. FIG. 8 is a diagram illustrating the voltage-controlled current source 104 in the voltage regulator 100 of FIG. 7. The voltage-controlled current source 104 comprises a first current mirror 1041 , a first bias current generator 1042 , a second current mirror 1043 , a second bias current generator 1044 , a third current source 1045 , a feedback circuit 1046 , and a fourth current source 1047 . The first current mirror 1041 generates a first mirror current I M1 according to a first bias current I B1 and a current mirror ratio N. The first bias current generator 1042 is coupled to the first current mirror 1041 for providing the first bias current I B1 according to a first current I B and a reference current I ac1 . In this embodiment, the first bias current I B1 is a sum of the first current I B and the reference current I ac1 . The first bias current generator 1042 comprises a first current source, which is implemented using a transistor M 1 , having a gate terminal N g1 biased by a first bias voltage V B1 for generating the first bias current I B1 ; and a capacitive device C 1 coupled to the drain terminal N d1 of the transistor M 1 in parallel for conducting the reference current I ac1 . Therefore, the reference current I ac1 is equal to s*C 1 *V out , where the symbol s represents jω. The second current mirror 1043 generates a second mirror current I M2 according to a second bias current I B2 and the current mirror ratio N. The second bias current generator 1044 is coupled to the second current mirror 1043 and has a second current source, which is implemented using a transistor M 2 having a gate terminal N g2 biased by the first bias voltage V B1 for generating a second current I B2 serving as the second bias current. In this embodiment, the transistors M 1 and M 2 have the same configuration and are biased by the same bias voltage V B1 , thus the first current I B1 is equal to the second current I B2 . The third current source 1045 , which is implemented using a transistor M 3 , has a drain terminal N d3 coupled to an output node of the second current mirror 1043 and the gate terminal N g3 biased by a second bias voltage V B2 for providing a third current I D3 , wherein the second mirror current 1043 is equal to the third current I D3 . The feedback circuit 1046 is coupled to the output node N d3 of the second current mirror 1043 and the third current source 1045 , for tuning the second bias voltage V B2 according to the target voltage level V ref of the voltage regulator 100 and the voltage V d3 at the output node N d3 of the second current mirror 1043 . The fourth current source 1047 , which is implemented using a transistor M 4 has a drain terminal coupled to the output node N d4 of the first current mirror 1041 and the gate terminal N g4 biased by the second bias voltage V B2 for providing a fourth current I D4 . Furthermore, the output current I ac is outputted at the output node of the first current mirror 1041 , which is the first input node N+ of the error amplifier 102 .
The first bias current generator 1042 further comprises a transistor M 5 having a drain terminal N d5 coupled to the first current mirror 1041 , a source terminal coupled to the drain terminal N d1 of the transistor M 1 and a gate terminal N g5 ; and a first error amplifier OP 1 having a first input node N OP1+ coupled to the output voltage V out of the voltage regulator 100 , a second input node N OP1− coupled to the source terminal of the transistor M 5 , and an output node coupled to the gate terminal N g5 of the transistor M 5 . In addition, the second bias current generator 1044 further comprises a transistor M 6 having a drain terminal N d6 coupled to the second current mirror 1043 , a source terminal coupled to a drain terminal N d2 of the transistor M 2 , and a gate terminal N g6 ; and a second error amplifier OP 2 having a first input node N OP2+ coupled to the output voltage V out of the voltage regulator 100 , a second input node N OP2− coupled to the source terminal of the transistor M 6 , and an output node coupled to the gate terminal N d6 of the transistor M 6 . Please note that, in this embodiment, the circuit configuration of the transistor M 5 and the first error amplifier OP 1 is symmetric to that of the transistor M 6 and the second error amplifier OP 2 . As shown in FIG. 8, the feedback circuit 1046 comprises a third error amplifier OP 3 having a first input node N OP3+ coupled to the drain terminal N d3 of the transistor M 3 , a second input node N OP3− coupled to the target voltage level V ref , and an output node coupled to the gate terminal N g3 of the transistor M 3 . The detailed operation of the voltage-controlled current source 104 is illustrated as below.
Please refer to FIG. 7 in conjunction with FIG. 8. Due to the mirroring imperfection between the first bias current I B1 and the first mirror current I M1 of the first current mirror 1041 , the first current mirror 1041 mirrors the first bias current I B1 according to the current mirror ratio N to introduce the mismatch current to the first mirror current I M1 , i.e. I M1 =N*I B1 =N*I B +N*I ac1 +ΔI B1 , where ΔI B1 is the mismatch current induced by the first current mirror 1041 . Similarly, due to the mirroring imperfection between the second bias current I B2 and the second mirror current I M2 of the second current mirror 1043 , the second current mirror 1043 mirrors the second bias current I B2 according to the current mirror ratio N to introduce the mismatch current to the second mirror current I M2 , i.e. I M2 =N*I B2 +ΔI B2 , where ΔI B2 is the mismatch current induced by the second current mirror 1043 . Please note that, since the second current mirror 1043 is a replica of the first current mirror 1041 in this embodiment (i.e. both have the same current mirror ratio N), the mismatch current ΔI B1 is substantially equal to the mismatch current ΔI B2 , i.e. ΔI B1 =ΔI B2 . Additionally, the first error amplifier OP 1 is operative to lock the voltage level at the drain terminal N d2 to the output voltage V out , and the first error amplifier OP 1 is also operative to lock the voltage level at the drain terminal N d2 to the output voltage V out . As shown in FIG. 8, the transistors M 1 and M 2 are both biased by the same bias voltage V B1 . As a result, the first current I B1 is substantially the same as the second current I B2 because of the same bias condition applied to the transistors M 1 and M 2 .
On the other hand, the feedback circuit 1046 , acting as a common mode feedback circuit of the transistors M 3 , is utilized to make the voltage V d3 approach to the target voltage level V ref of the voltage regulator 100 by controlling the transistor M 3 . Furthermore, the feedback voltage level V FB at the output node N d4 also approaches to the target voltage level V ref of the voltage regulator 100 because of the error amplifier 102 . Therefore, both of the transistors M 3 and M 4 are operated under substantially identical bias condition. In this way, as the feedback voltage V FB and the drain voltage V d3 are both equal to the target voltage V ref with the help of the error amplifier 102 and the third error amplifier OP 3 , the third current I D3 of the transistor M 3 is sure to coincide with the fourth current I D4 of the transistor M 4 , i.e. I D3 =I D4 =N*I B2 +ΔI B2 . Accordingly, referring to Kirchhoff's Laws, the output current I ac can be obtained by subtracting the fourth current I D4 from the first mirror current I M1 (i.e. I M1 =N*I B +N*I ac1 +ΔI B1 ), which is the AC current of N*I ac1 (i.e. N*s*C 1 *V out ). Compared with the prior art, the voltage-controlled current source (i.e. the output current I ac ) of N*s*C 1 *V out with no mismatch current ΔI B can be obtained, ideally. In a real application, the induced mismatch current ΔI B is very small, and can be neglected.
Please refer to FIG. 9. FIG. 9 is a diagram illustrating an equivalent schematic of the voltage-controlled current source 104 in the voltage regulator 100 of FIG. 7. Therefore, as one can see, the voltage-controlled current source 104 provides an ideal frequency-dependent voltage-controlled current source, where R mismatch approaches to ∞.
Please refer to FIG. 7 again. In order to obtain a good phase margin for all loading current I Load of the voltage regulator 100 of FIG. 7, a location of zero ω ESR of the voltage regulator 100 should be adjustable with the loading current I Load . In other words, the zero ω ESR is higher for heavy loading current I Load (i.e. small load impedance) and lower for light loading current I Load (i.e. high load impedance) as shown in FIG. 10. FIG. 10 is a diagram illustrating the frequency response of the voltage regulator 100 of FIG. 7. By applying the voltage-controlled current source 104 to compensate the pole of the voltage regulator 100 , the zero ω ESR is directly tuned by modifying the current mirror ratio N of the first current mirror 1041 and the second current mirror 1043 according to the loading current I Load monitored by the loading sensing circuit 103 . According to the aforementioned equation (3), the zero ω ESR of the voltage regulator 100 can be modified as below:
ω ESR =1/( N*R F1 *CF ). (4)
In this embodiment, the loading sensing circuit 103 of the present invention is configured to sense the voltage level at the gate terminal N g (i.e. the output node) of the pass transistor M P to detect the loading current variation. Then the loading sensing circuit 103 changes the current mirror ratio N of the first current mirror 1041 and the second current mirror 1043 to modify the zero ω ESR according to the above equation (4). Therefore, as shown in FIG. 10, a good phase margin can be obtained as compared with the prior art. Please note that, the loading sensing circuit 103 of the present invention is not limited to sensing the voltage level at the gate terminal N g of the pass transistor M P to detect the loading current variation. That is, any other terminal voltage of the voltage regulator 100 that can be referred to for tracking the loading current I Load also can be adopted. These alternative designs all fall in the scope of the present invention. In addition, any conventional means of changing the current mirror ratio N of the first current mirror 1041 and the second current mirror 1043 can be utilized in the present invention. Since the technique of tuning the current mirror ratio is well known to those skilled in this art, further description is omitted here for brevity.
Please refer to FIG. 11. FIG. 11 is a diagram a feedback-controlled system 200 according an embodiment of the present invention. The feedback-controlled system 200 comprises a plurality of operational stages 201 1 , . . . , 201 x cascaded in a closed loop. In addition, a current generating apparatus 202 is implemented and coupled to the operational stages 201 n+m . Each of the operational stages 201 1 , . . . , 201 x has a transfer function of A 1 , . . . , A x , respectively. The current generating apparatus 202 has a control terminal N c coupled to an output of an n th operational stage 201 n and an output terminal N o coupled to an output of a (n+m) th operational stage 201 n+m in the operational stages. The current generating apparatus 202 generates an output current Vn*N*s*C 1 to an output of the (n+m) th operational stage 201 n+m in the operational stages. Please note that, in this embodiment the current generating apparatus 202 is implemented using the above-mentioned voltage-controlled current source 104 shown in FIG. 8, therefore the detailed description is omitted here for brevity. Through the current generating apparatus 202 , a zero can be induced to the feedback-controlled system 200 . According to FIG. 11, the voltage V n+m at the output of the (n+m) th operational stage 201 n+m is represented using the following equation (5):
V n+m =V n *( A n+1 *A n+2 . . . A n+m )+ V n *N*s*C 1 *R IN . (5)
Then,
V n+m /V n =( A n+1 *A n+2 . . . A n+m +N*s*C 1 *R IN ). (6)
Thus, a zero ω z can be obtained from the equation (6),
ω z =( A n+1 *A n+2 . . . A n+m )/( N*C 1 *R IN ),
wherein C 1 is the capacitive device of the voltage-controlled current source 104 of FIG. 8, R IN is the input resistor at the output of the (n+m) th operational stage 201 n+m , and N is the current mirror ratio of the first current mirror 1041 and the second current mirror 1043 . Therefore, by utilizing the current generating apparatus 202 zero ω z can be added to the feedback-controlled system 200 and without introducing any pole.
It should be note that a person skilled in this art can readily appreciate that the voltage regulator is a kind of the feedback-controlled system. Referring to FIG. 7 in conjunction with FIG. 11, it is clear that the voltage regulator 100 includes three operational stages connected in a closed loop, where the pass transistor M P serves as one operational stage, the voltage divider 101 serves as another operation stage, and the error amplifier 102 serves as yet another operational stage.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.