This application is a continuation of prior application Ser. No. 11/737,154, filed Apr. 19, 2007, which is a continuation of prior application Ser. No. 11/194,799, filed Aug. 2, 2005 (now U.S. Pat. No. 7,224,612), which is a continuation of prior application Ser. No. 10/920,161, filed Aug. 28, 2004 (now U.S. Pat. No. 6,940,752), which is a continuation of prior application Ser. no. 10/377,674, filed Mar. 4, 2003 (now U.S. Pat. No. 6,798,698), which is a continuation of prior application Ser. No. 10/187,285, filed Jul. 2, 2002 (now U.S. Pat. No. 6,549,464), which is a continuation of prior application Ser. No. 09/767,152, filed Jan. 23, 2001 (now U.S. Pat. No. 6,434,055), which is a divisional of prior application Ser. No. 09/599,397, filed Jun. 22, 2000 (now U.S. Pat. No. 6,208,560), which is a divisional of prior application Ser. No. 09/078,137, filed May 14, 1998 (now U.S. Pat. No. 6,134,140), which is based on and claims priority to Japanese Patent Application No. 9-124493, filed May 14, 1997, Japanese Patent Application No. 9-224922, filed Aug. 21, 1997, Japanese Patent Application No. 9-340971, filed Dec. 11, 1997, and Japanese Patent Application No. 10-104652, filed Apr. 15, 1998, the contents of which are incorporated herein by reference.
The present invention relates to a nonvolatile semiconductor memory device, more particularly to an EEPROM (Electrically Erasable and Programmable Read-Only Memory).
As an example of a memory cell of EEPROM known as a flash memory, there is a memory cell having an MOSFET structure, which comprises a floating gate and a control gate. The floating gate (i.e., charge storage layer) is provided on a semiconductor substrate, and the control gate is provided on the charge storage layer. The memory cell stores a 1-bit data which is either “0” or “1”, depending on the amount of electric charge accumulated in the floating gate.
Another type of a memory cell is known, which is designed for use in a flash memory having a large storage capacity. This memory cell can store multi-bit data. A four-value memory cell, for example, can store “0”, “1”, “2” and “3” by accumulating, respectively, four different amounts of charge in the floating gate.
How a four-value memory cell stores multi-bit data will be explained below.
A four-value memory cell assumes a neutral state when its floating gate accumulates no electric charge. A condition in which a more positive charge is accumulated than the neutral state is an erased state, storing data “0”. More specifically, a high voltage of about 20V is applied to the substrate, setting the control gate at 0V, whereby erasing the data, i.e., storing data “0”. The threshold voltage of the four-value memory cell may differ from the design value. If so, the voltage applied to the substrate may be too high, and the floating gate may accumulate an excessively large positive charge and the memory cell is, so to speak, “over-erased.” In the four-value memory cell which has been over-erased, the charge accumulated in the floating gate would not change to a predetermined negative level even if an ordinary programming pulse voltage is applied to the memory cell. In this case, data, particularly “0” cannot be programmed into the four-value memory cell.
The four-value memory cell stores data “1” when the floating gate accumulates a first negative charge. The memory cell stores data “2” when the floating gate accumulates a second negative charge greater than the first. The memory cell stores data “3” when the floating gate accumulates a third negative charge greater than the second negative charge.
To program data into the four-value memory cell, the program operation, the substrate, source and drain are set at 0V and a high voltage (about 20V) is applied to the control gate. When the floating gate accumulates the first negative charge, data “1” is programmed into the memory cell. When the floating gate accumulates the second negative charge, data “2” is programmed into the memory cell. When the floating gate accumulates the third negative charge, data “3” is programmed into the memory cell. When the substrate, the source, drain and channel are set at a positive potential and the control gate is applied with the high voltage (about 20V), while the substrate remains at 0V, the floating gate holds the accumulated charge. In this case, data “0” is programmed into the memory cell.
The four-value memory cell can thus store four values “0”, “1”, “2” and “3”.
A NAND-type memory cell unit is known, which is designed to increase the storage capacity of a flash memory. The NAND-type memory cell unit comprises a plurality of memory cells and two selection transistors. The memory cells are connected in series, forming a series circuit. The first selection transistor connects one end of the series circuit to a bit line. The second selection transistor connects the other end of the series circuit to the common source line of the memory cells.
To program “0” into a selected one of the memory cells of the NAND-type memory cell unit, the bit line and the gate of the first selection transistor are set at the power-supply voltage VCC (e.g., 3V), the control gate of the selected memory cell is set at 20V, the control gates of the two memory cells adjacent to the selected memory cell are set at 0V, and the control gate of any other memory cells is set at 11V.
In this case, the voltage applied from the bit line via the first selection transistor to the channel of the memory cell at one end of the series circuit is equal to or lower than the power-supply voltage VCC. Once the first selection transistor is turned off, however, the channel voltage rises due to the electrostatic capacitive coupling between the control gate and channel of the memory cell.
The two memory cells adjacent to the selected memory cell are thereby turned off, too. If the coupling ratio is 50%, the channel potential of the selected memory cell will be 10V, as is obtained by simple calculation. The channel potential of any memory cell not selected will be 5.5V.
When the channel potential of any memory cell not selected is 5.5V, the two memory cells adjacent to the selected memory cell will be turned off if their threshold voltage is equal to or higher than −5.5V. In other words, these memory cells must have a threshold voltage equal to or higher than −5.5V in order to program “0” into the selected memory cell.
To program “1”, “2” or “3” into any selected memory cell of the NAND-type memory cell unit, the bit line is set at 0V. Program verification is performed on the selected memory cell. If a memory cell is found into which the data is not completely programmed, the program operation is effected again on that memory cell.
The threshold voltage of any memory cell is thereby controlled with high precision. The program operation on the NAND-type memory cell unit ends when all the memory cells are verified. Time periods of one cycle for programming “1”, “2” and “3” are set to the same period. Therefore, data “2” and “3” are programmed by controlling the number of cycles for programming. That is, the program operation is effected once to program data “1”, twice to program data “2”, and thrice to program data “3”.
Hence, data “1” is programmed into a memory cell that should store “1” when the program operation is carried out for the first time. Then, data “2” is programmed into a memory cell that should store “2”, and thereafter data “3” is programmed into a memory cell that should store “3.”
There is known another method of programming data into flash memories. In this method, the bit line voltage is changed in accordance with the value of the data to be programmed, whereby “1”, “2” and “3” are written at the same speed, or within the same time period.
The method cannot be used to program data into a NAND-type memory cell unit of the type described above. If the method is so used, however, a voltage higher than 0V of the bit line voltage cannot be transferred to the selected memory cell, if the control gate of the selected memory cell is set at 0V. This is because both memory cells adjacent to the selected memory cell have a threshold voltage which is almost 0V.
The floating gate of a multi-value memory cell must accumulate a larger electric charge to program data into the memory cell than the amount of charge the floating gate of a binary memory cell needs to accumulate to program data. The greater the charge the floating gate accumulates, the higher the rate at which the floating gate is discharged due to a self electromagnetic field. Hence, multi-value memory cells can hold data, but for a shorter time than binary memory cell.
In the conventional nonvolatile memory device having multi-value memory cells, the channel voltage of the selected memory cell at the time of “0” programming rises sufficiently since the channel potential is isolated from the channel voltage any other memory cells. However, when the selected memory cell is over-erased, its threshold voltage decreases excessively and both memory cells adjacent to the selected memory cell cannot be turned off. Consequently, the channel potential of the selected memory cell fails to increase sufficiently, making it impossible to program data “0” into the selected memory cell. It should be noted that the memory cell is over-erased if the erase operation has been performed many times or if an excessively high data-erasing voltage is applied.
Further, the pulse width of a programming pulse which indicates a time period of one cycle of program operation is constant irrespective of the program operations for “1”, “2” and “3”. Therefore, the programming speed for programming “1”, “2” and “3” cannot be made equal. Stated another way, time periods of one cycle for programming “1”, “2” and “3” are set to the same period and data “2” and “3” are written by controlling the number of cycles for programming. Therefore, the programming pulse must be applied at short intervals, and much time is required to rewrite data in the memory.
Further, each multi-value memory cell can hold data, but for a shorter time than a binary memory cell.
Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which the voltage applied to a selected memory cell is low enough to program data “0” reliably into the selected memory cell even if the selected memory cell has been over-erased.
Another object of the invention is to provide a nonvolatile semiconductor memory device in which multi-value data can be programmed into the memory cells at high speed.
Still another object of this invention is to provide a nonvolatile semiconductor memory system in which each memory cell can hold multi-value data for a long time and which can achieve reliable storage of multi-value data.
(1) According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a NAND cell unit comprising a plurality of memory cells connected in series; an erase circuit for applying an erase voltage to all memory cells of the NAND cell unit, thereby to erase data from all memory cells of the NAND cell unit; a soft-programming circuit for applying a soft-program voltage to all memory cells of the NAND cell unit, the soft-program voltage being of a polarity opposite to the polarity of the erase voltage; and a programming circuit for applying a program voltage to any selected one of the memory cells, applying a first voltage to at least one of two memory cells adjacent to the any selected one of the memory cells, and applying a second voltage to the remaining memory cells of the NAND cell unit, thereby to program data into the any selected one of the memory cells.
(2) According to a second aspect of the present invention, there is provided a memory device according to the first aspect, in which the programming circuit for applying the first voltage to both of the two memory cells adjacent to the any selected one of the memory cells.
(3) According to a third aspect of the present invention, there is provided a memory device according to the first aspect, in which the soft-programming circuit applies the soft-program voltage to all the memory cells after the erasing circuit has erased data from all memory cells of the NAND cell unit, and the programming circuit programs the memory cells after the soft-programming circuit has applied the soft-program voltage to all the memory cells.
(4) According to a fourth aspect of the present invention, there is provided a memory device according to the first aspect, in which the soft-program voltage is lower than the program voltage.
(5) According to a fifth aspect of the present invention, there is provided a memory device according to the first aspect, which further comprises an erase-verification circuit for determining whether data has been erased from all the memory cells of the NAND cell unit and have threshold voltages controlled within a predetermined range after the soft-programming circuit has applied the soft-program voltage to all the memory cells, and in which the programming circuit programs data into the any selected one of the memory cells after the soft-programming circuit and the erase-verification circuit have performed a soft-program operation and an erase verification operation.
(6) According to a sixth aspect of the present invention, there is provided a memory device according to the fifth aspect, further comprising a control circuit for causing the soft-programming circuit and the erase-verification circuit to repeat the soft-program operation and the erase verification operation, and for causing the soft-programming circuit to terminate the soft-program operation when at least one of the memory cells of the NAND cell unit has a threshold voltage forced out of the predetermined range.
(7) According to a seventh aspect of the present invention, there is provided a memory device according to the sixth aspect, in which the control circuit causes the erasing circuit to erase data again from all memory cells of the NAND cell unit when the soft-program operation and the erase verification operation have not repeated a predetermined number of times and when at least one of the memory cells of the NAND cell unit is forced out of the predetermined range.
(8) According to an eighth aspect of the present invention, there is provided a memory device according to the first aspect, in which the program voltage is higher than the first and second voltages, and the second voltage is higher than the first voltage.
(9) According to a ninth aspect of the present invention, there is provided a memory device according to the eighth aspect, in which the first voltage is 0V.
(10) According to a tenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a plurality of nonvolatile semiconductor memory cells, each capable of storing n-value data, where n is a natural number greater than 2; and a data-programming circuit for performing a program operation in which program pulses are applied to the plurality of nonvolatile semiconductor memory cells to program n-value data into the plurality of nonvolatile semiconductor memory cells, performing a program verification operation in which it is determined whether or not the n-value data has been programmed into the plurality of nonvolatile semiconductor memory cells and repeating the program operation and the program verification operation, wherein each of the program pulses has a predetermined pulse width in accordance with a value of the n-value data to be programmed into corresponding memory cell.
(11) According to an eleventh aspect of the present invention, there is provided a memory device according to the tenth aspect, in which each program pulse is removed from corresponding memory cell after the program verification operation in which it has been determined that n-value data has been programmed into the corresponding memory cell.
(12) According to a twelfth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the program operation is terminated when it is determined in the program verification operation that all of n-value data have been programmed into the plurality of nonvolatile semiconductor memory cells.
(13) According to a thirteenth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the program operation and the program verification operation are terminated after a limited number of cycles.
(14) According to a fourteenth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the plurality of nonvolatile semiconductor memory cells are connected to one word line.
(15) According to a fifteenth aspect of the present invention, there is provided a memory device according to the tenth aspect, in which the plurality of memory cells are respectively included in corresponding NAND cell units, each NAND cell unit comprising a predetermined number of nonvolatile semiconductor memory cells connected in series, and in the program operation, the data-programming circuit applies a first voltage to at least one of the two memory cells adjacent to the selected memory cells to be programmed and a second voltage to the remaining memory cells.
(16) According to a sixteenth aspect of the present invention, there is provided a memory device according to the fifteenth aspect, in which voltages of the program pulses are higher than the first and second voltages, and the second voltage is higher than the first voltage.
(17) According to a seventeenth aspect of the present invention, there is provided a memory device according to the sixteenth aspect, in which the first voltage is 0V.
(18) According to an eighteenth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell array comprising memory cells arranged in rows and columns, each having a control gate; a programming circuit for programming data into any selected one of the memory cells by applying a program voltage to the control gate of the selected memory cell; an erasing circuit for erasing data from the memory cells by applying an erase voltage opposite in polarity to the program voltage; a soft-programming circuit for applying a soft-program voltage to the memory cells, thereby setting the memory cells into a desirable erased state; a verification read circuit for determining whether the memory cells have been set into the desirable erased state; and an erased-state determining circuit for causing the soft-programming circuit to terminate the soft-program operation upon determining from an output of the verification read circuit that at least two of the memory cells have a threshold voltage which has reached a predetermined value.
(19) According to a nineteenth aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the soft-programming circuit soft-programs the memory cells after the erasing circuit has erased data from the memory cells, and the verification read circuit performs a determination operation after the soft-programming circuit has soft-programmed the memory cells.
(20) According to a twentieth aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the memory cell array includes a plurality of data input/output lines divided into m units (m≧2), and the erase-state determining circuit comprises circuits for detecting erased states of the memory cells based on the data input/output lines of each unit and causing the soft-programming circuit to terminate soft-program operation, upon determining that at least one of the memory cells connected to the data input/output lines of any unit has a threshold voltage which has reached the predetermined value.
(21) According to a twenty-first aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the memory cell array includes a plurality of word lines divided into m units (m≧2), and the erase-state determining circuit comprises circuits for detecting erased states of the memory cells based on the word lines of each unit and causing the soft-programming circuit to terminate soft-program operation, upon determining that at least one of the memory cells connected to the word lines of any unit has a threshold voltage which has reached the predetermined value.
(22) According to a twenty-second aspect of the present invention, there is provided a memory device according to the eighteenth aspect, in which the nonvolatile semiconductor memory cells of the memory cell array form NAND cell units, each comprising a plurality of memory cells connected in series, and the programming circuit applies a first voltage lower than the program voltage to the control gate of at least one of two memory cells adjacent to any selected one of the memory cells of each NAND cell unit, and applies a second voltage between the program voltage and the first voltage, to the remaining memory cells of each NAND cell unit, thereby to program data into the any selected one of the memory cells.
(23) According to a twenty-third aspect of the present invention, there is provided a memory device according to the twenty-second aspect, which further comprises a memory circuit for storing data output from the verification read circuit, and in which the erased-state determining circuit comprises a scan-detection circuit for monitoring the data stored in the memory circuit and counting the memory cells which have a threshold voltage which has reached the predetermined value.
(24) According to a twenty-fourth aspect of the present invention, there is provided a memory device according to the twenty-third aspect, further comprising a control circuit for repeatedly causing the soft-programming circuit to perform a soft-program operation, the verification read circuit to perform a verification read operation and the scan-detection circuit to perform a memory-cell counting operation, and for causing the soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation when the scan-detection circuit counts at least two memory cells having a threshold voltage which has reached the predetermined value.
(25) According to a twenty-fifth aspect of the present invention, there is provided a memory device according to the twenty-fourth aspect, in which the control circuit causes the verification read circuit to perform the verification read operation by applying a margin voltage to the word line of each NAND cell unit after the soft-programming circuit has finished performing the soft-program operation, causes the scan-detection circuit to perform the memory-cell counting operation, and causes the soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation, when the scan-detection circuit detects that all memory cells of each NAND cell unit have a threshold voltage equal to or lower than a predetermined threshold voltage, the predetermined threshold voltage being higher than the predetermined value.
(26) According to a twenty-sixth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell section including at least one memory cell and having first and second ends; a first signal line connected to the first end of the memory cell section; a second signal line connected to the second end of the memory cell section; a reading circuit connected to the first signal line, for reading the memory cell; an erasing circuit for erasing data stored in the memory cell; and an over-erase detecting circuit for detecting whether the memory cell is over-erased, wherein the over-erase detecting circuit applies a first reference potential to the second signal line, thereby outputting a first read potential to the first signal line, and the reading circuit detects the first read potential.
(27) According to a twenty-seventh aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, further comprising a soft-programming circuit for performing soft-program operation on the memory cell when the over-erase detecting circuit detects that the memory cell has been over-erased.
(28) According to a twenty-eighth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a first memory cell section including at least one memory cell; a second memory cell section including at least one memory cell; a first signal line connected to a first end of the first memory cell section; a second signal line connected to a second end of the first memory cell section; a third signal line connected to a first end of the second memory cell section; a fourth signal line connected to a second end of the second memory cell section; a reading circuit connected to the first signal line, for reading the memory cell; an erasing circuit for erasing data stored in the memory cell; and an over-erase detecting circuit for detecting whether the memory cell is over-erased, wherein the over-erase detecting circuit applies a first reference potential to the second signal line, thereby outputting a first read potential to the first signal line and applying a second reference potential to the third signal line, and the reading circuit detects the first read potential.
(29) According to a twenty-ninth aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a first memory cell section including at least one memory cell; a second memory cell section including at least one memory cell; a first signal line connected to a first end of the first memory cell section; a second signal line connected to a second end of the first memory cell section; a third signal line connected to a first end of the second memory cell section; a fourth signal line connected to a second end of the second memory cell section; a reading circuit connected to the first signal line, for reading the memory cell; an erasing circuit for erasing data stored in the memory cell; an over-erase detecting circuit for detecting whether the memory cell is over-erased; and a soft-programming circuit for performing a soft-program operation on the memory cell when the over-erase detecting circuit detects that the memory cell has been over-erased, wherein the over-erase detecting circuit applies a first reference potential to the second signal line, thereby outputting a first read potential to the first signal line and applying a second reference potential to the third signal line, and the reading circuit detects the first read potential.
(30) According to a thirtieth aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node, and a capacitor connected at one end to the first node and at the other end to the second node, and the potential applied to the second node is changed when the sense amplifier detects the potential of the first node.
(31) According to a thirty-first aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node, and a capacitor connected at one end to the first node and at the other end to the second node, the potential applied to the second node is changed when the sense amplifier detects the potential of the first node, the over-erase detecting circuit applies the first reference potential to the second signal line to detect whether the memory cell has been over-erased, the first read potential output to the first signal line is transferred through the first switch to the first node as a second read potential, and the potential of the first node is changed to a third read potential different from the second read potential, by changing potential of the second node.
(32) According to a thirty-second aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the first and third lines are bit lines.
(33) According to a thirty-third aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the first line is a bit line, and the third line is a bit line adjacent to the first line.
(34) According to a thirty-fourth aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the second and fourth lines are source lines.
(35) According to a thirty-fifth aspect of the present invention, there is provided a memory device according to the twenty-ninth aspect, in which the first and second reference potentials are of approximately the same value.
(36) According to a thirty-sixth aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the first reference potential is a power-supply voltage.
(37) According to a thirty-seventh aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which the memory cell section includes a NAND cell unit comprising a plurality of memory cells connected in series.
(38) According to a thirty-eighth aspect of the present invention, there is provided a memory device according to the twenty-sixth aspect, in which when the over-erase detecting circuit applies the first reference potential to the second signal line, a first over-erase detection word-line potential is applied to the gate of any selected memory cell and a second over-erase detection word-line potential is applied to the gates of the memory cells connected in series to the any selected memory cell, thereby the first read potential is output to the first signal line.
(39) According to a thirty-ninth aspect of the present invention, there is provided a memory device according to the thirty-eighth aspect, in which the first and second over-erase detection word-line potentials are of approximately the same value.
(40) According to a fortieth aspect of the present invention, there is provided a memory device according to the thirty-eight aspect, in which the first and second over-erase detection word-line potentials are of different values.
(41) According to a forty-first aspect of the present invention, there is provided a memory device according to the thirty-eighth aspect, in which the first over-erase detection word-line potential is 0V.
(42) According to a forty-second aspect of the present invention, there is provided a memory device according to the thirty-eighth aspect, in which the second over-erase detection word-line potential is a power-supply voltage.
(43) According to a forty-third aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell section including a NAND cell unit comprising a plurality of memory cells connected in series; an erasing circuit for erasing data stored in the memory cells; and an over-erase detecting circuit for detecting whether the memory cells are over-erased.
(44) According to a forty-fourth aspect of the present invention, there is provided a memory device according to the forty-third aspect, further comprising a soft-programming circuit for performing a soft-program operation on any one of the memory cells that has been over-erased.
(45) According to a forty-fifth aspect of the present invention, there is provided a memory device according to the forty-third aspect, which further comprises a first signal line connected to one end of the NAND cell unit, a second signal line connected to the other end of the NAND cell unit, and a reading circuit connected to the first signal line, for reading the memory cells, and in which the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node and a capacitor connected at one end to the first node and at the other end to the second node, and the second node is changed, when the sense amplifier detects the potential of the first node.
(46) According to a forty-sixth aspect of the present invention, there is provided a memory device according to the forty-fifth aspect, further comprising a transistor which includes a gate connected to an output terminal of the sense amplifier and which detects that the second sense amplifier stores the data that has been erased from one of the memory cells.
(47) According to a forty-seventh aspect of the present invention, there is provided a memory device comprising a first signal line connected to one end of a unit of memory cells; a second signal line connected to the other end of the unit of memory cells; and a reading circuit connected to the first signal line, for reading the memory cells, and wherein the reading circuit includes a first switch for connecting the first signal line to a first node, a sense amplifier for detecting a potential of the first node and a capacitor connected at one end to the first node and at the other end to the second node, and the second node is changed, when the sense amplifier detects the potential of the first node.
(48) According to a forty-eighth aspect of the present invention, there is provided a memory device according to the forty-seventh aspect, in which a potential of the second signal line is set to a potential higher than a potential of the first signal line during a reading operation.
(49) According to a forty-ninth aspect of the present invention, there is provided a nonvolatile semiconductor memory system comprising an electrically programmable nonvolatile semiconductor memory device; and a controller for controlling the nonvolatile semiconductor memory device, and wherein the controller determines whether a predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.
(50) According to a fiftieth aspect of the present invention, there is provided a memory system according to the forty-ninth aspect, in which the nonvolatile semiconductor memory device comprises a multi-value memory device.
(51) According to a fifty-first aspect of the present invention, there is provided a memory system according to the forty-ninth aspect, in which the controller refreshes data upon determining that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.
(52) According to a fifty-second aspect of the present invention, there is provided a memory system comprising an electrically programmable nonvolatile semiconductor memory device; a controller for controlling the nonvolatile semiconductor memory; a battery for supplying power to the controller when external power supplies are unavailable; and a terminal for receiving and supplying signals and power from and to an external device, and wherein the controller determines whether a predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.
(53) According to a fifty-third aspect of the present invention, there is provided a memory system comprising an electrically programmable nonvolatile semiconductor memory device; a controller for controlling the nonvolatile semiconductor memory device; a battery for supplying power to the controller when external power supplies are unavailable; a timer for storing data representing a time when data is programmed into the nonvolatile semiconductor memory; a terminal for receiving and supplying signals and power from and to an external device, and wherein the controller determines whether a predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.
(54) According to a fifty-fourth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the nonvolatile semiconductor memory device comprises a multi-value memory device.
(55) According to a fifty-fifth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the controller refreshes data upon determining that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device.
(56) According to a fifty-sixth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, further comprising an indicator for indicating that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device, when the controller determines that the predetermined time has elapsed.
(57) According to a fifty-seventh aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the battery is a chargeable one and is charged while power is supplied from an external power supply.
(58) According to a fifty-eighth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the controller stops supply of power to the nonvolatile semiconductor memory device while no power is being supplied from an external power supply.
(59) According to a fifty-ninth aspect of the present invention, there is provided a memory system according to the fifty-second or fifty-third aspect, in which the controller refreshes data upon determining that the predetermined time has elapsed after data was programmed into the nonvolatile semiconductor memory device, and stops supply of power to the nonvolatile semiconductor memory device while no power is being supplied from an external power supply and while the controller is not refreshing the data.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.
The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the present invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the present invention in which:
FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a diagram showing the memory cell array and data memories according to the first embodiment;
FIGS. 3A and 3B are diagrams showing a memory cell and a selection transistor according to the first embodiment;
FIG. 4 is a sectional view illustrating a NAND-type cell unit according to the first embodiment;
FIG. 5 is a circuit diagram of the data memory shown in FIG. 2;
FIG. 6 is a circuit diagram of the clocked inverter shown in FIG. 5;
FIG. 7 is a circuit diagram of the word line controller shown in FIG. 1;
FIG. 8 is a timing chart explaining the read operation in the first embodiment;
FIG. 9 is a timing chart explaining how the word line controller operates during the read operation in the first embodiment;
FIG. 10 is a timing chart explaining the program operation in the first embodiment;
FIG. 11 is a timing chart explaining how the word line controller operates during the program operation in the first embodiment;
FIG. 12 is a timing chart explaining how program verification is achieved in the first embodiment;
FIG. 13 is a timing chart explaining how the word line controller operates during the program verification operation in the first embodiment;
FIG. 14 is a flow chart representing the programming algorithm in the first embodiment;
FIG. 15 is a timing chart explaining the erase operation in the first embodiment;
FIG. 16 is a timing chart explaining the soft-program operation in the first embodiment;
FIG. 17 is a timing chart explaining how erase verification is achieved in the first embodiment;
FIG. 18 is a timing chart explaining how the word line controller operates during the erase verification operation in the first embodiment;
FIG. 19 is a flow chart representing the erase algorithm in the first embodiment;
FIG. 20 is a block diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention;
FIG. 21 is a flow chart illustrating the algorithm of testing the erase voltage in the second embodiment;
FIG. 22 is a flow chart depicting the algorithm of testing the soft-program voltage in the second embodiment;
FIG. 23 is a flow chart explaining the algorithm of testing the programming voltage in the second embodiment;
FIG. 24 is a timing chart for explaining how erase verification is effected under the control of an externally applied voltage, in the second embodiment;
FIG. 25 is a timing chart for explaining how the word line controller operates during the erase verification operation controlled by the externally applied voltage;
FIG. 26 is a block diagram of a nonvolatile semiconductor memory device according to a third embodiment of the present invention;
FIG. 27 is a block diagram of a nonvolatile semiconductor memory device according to a fourth embodiment of the invention;
FIG. 28 is a perspective view of a flash memory system shaped as a card, which is a modification of the fourth embodiment;
FIG. 29 is a block diagram of a NAND-type flash memory, which is a fifth embodiment of the invention;
FIG. 30 is a flow chart explaining the erase operation in the fifth embodiment;
FIGS. 31A, 31B and 31 C are diagrams showing how the distribution of the threshold voltages of each memory cell changes with time during the erase operation;
FIG. 32 is a diagram explaining one method of dividing the memory cell array into units, before a soft-program operation is conducted in the fifth embodiment;
FIG. 33 is a diagram explaining another method of dividing the memory cell array into units, before a soft-program operation is conducted in the fifth embodiment;
FIG. 34 is a diagram illustrating the memory cell array in the flash memory according to the fifth embodiment;
FIG. 35 shows, in detail, the column scan detection circuit in the fifth embodiment shown in FIG. 29;
FIG. 36 is a timing chart for explaining how the column scan detection circuit operates in the fifth embodiment;
FIG. 37 is a timing chart for explaining how the column scan detection circuit operates in another manner in the fifth embodiment;
FIG. 38 is a flow chart explaining the erase operation in the fifth embodiment;
FIG. 39 is a graph showing how the threshold voltages of the memory cells change with time during the soft-program operation in the fifth embodiment;
FIGS. 40A and 40B are respectively a plan view of a NAND-type EEPROM cell unit for use in a sixth embodiment according to the invention and an equivalent circuit diagram thereof;
FIGS. 41A and 41B are sectional views taken along two different lines in FIG. 40A;
FIG. 42 is a circuit diagram of the memory cell array in the sixth embodiment;
FIG. 43 is a block diagram showing the sixth embodiment;
FIG. 44 is a circuit diagram showing the sense amplifier/latch circuit in the sixth embodiment;
FIG. 45 is a timing chart explaining the read operation in the sixth embodiment;
FIG. 46 is a timing chart explaining the program operation in the sixth embodiment;
FIG. 47 is a timing chart explaining the erase operation in the sixth embodiment;
FIG. 48 is a timing chart explaining the erase-verification read operation in the sixth embodiment;
FIG. 49 is a flow chart explaining the erase operation in the sixth embodiment;
FIG. 50 is a flow chart explaining the over-erase-verification read operation in the sixth embodiment;
FIG. 51 is a timing chart explaining the over-erase-verification read operation in the sixth embodiment;
FIG. 52 is a timing chart explaining the over-erase-verification read operation in the sixth embodiment;
FIG. 53 is a timing chart explaining the soft-program operation in the sixth embodiment;
FIG. 54 is a flow chart explaining the erase operation in the sixth embodiment of the invention;
FIG. 55 is a flow chart explaining the over-erase-verification read operation in a seventh embodiment of the invention;
FIG. 56 is a flow chart explaining the over-erase-verification read operation and the soft-program operation, both in an eight embodiment of the invention;
FIG. 57 is a flow chart explaining the over-erase-verification read operation and the soft-program operation, both in a ninth embodiment of the invention;
FIG. 58 is a circuit diagram of the sense amplifier/latch circuit in the ninth embodiment;
FIG. 59 is a timing chart explaining the over-erase-verification read operation for the selected memory cell by the bit line BLO and the word line WL 8 in the ninth embodiment;
FIG. 60 is a timing chart explaining the over-erase-verification read operation for the selected memory cell by the bit line BLE and the word line WL 7 in the ninth embodiment;
FIG. 61 is a timing chart explaining another mode of the soft-program operation in the ninth embodiment;
FIG. 62 is a flow chart explaining the erase operation in a tenth embodiment of the invention; and
FIG. 63 is a timing chart explaining the over-erase-verification read operation in a twelfth embodiment of the invention.
A preferred embodiment of a nonvolatile semiconductor memory device according to the present invention will now be described with reference to the accompanying drawings.
FIG. 1 shows a nonvolatile semiconductor memory device according to the first embodiment of the invention, which is a four-value NAND flash memory.
The four-value NAND flash memory comprises a memory cell array 1 . The array 1 comprises a plurality of bit lines, a plurality of word lines, a common source line, and a plurality of electrically programmable memory cells. The memory cells are arranged in rows and columns, at intersections of the bit lines and word lines. The flash memory further comprises a bit line controller 2 , a column decoder 3 , data input/output buffer 4 , a data input/output terminal 5 , a word line controller 6 , a control signal and control voltage generator 7 , and a control signal input terminal 8 . The bit line controller 2 controls the bit lines. The word line controller 6 controls the word lines.
The bit line controller 2 performs various functions. It reads data from the memory cells of the array 1 through the bit lines. It detects the states of the memory cells, through the bit lines. It applies a program-control voltage to the memory cells through the bit lines, in order to program data into the memory cells.
The bit line controller 2 includes a plurality of data memories. The data read from the memory cell is stored into the data memory selected by the column decoder 3 . Then, the data read from the data memory is output from the data input/output terminal 5 to an external device through the data input/output buffer 4 . The program data input to the data input/output terminal 5 from an external device is stored in the input/output buffer 4 . The data read from the input/output buffer 4 is input to the data memory selected by the column decoder 3 as initial control data.
The word line controller 6 selects one of the word lines in the memory cell array 1 . It applies a voltage to the selected word line, for reading data from, programming data into, or erasing data in the memory cells connected to the selected word line.
The control signal and control voltage generator 7 controls the memory cell array 1 , bit line controller 2 , column decoder 3 , data input/output buffer 4 and word line controller 6 . The control signal and control voltage generator 7 is, in turn, controlled by a control signal input to the control signal input terminal 8 from an external device.
FIG. 2 shows the memory cell array 1 and the bit line controller 2 .
As shown in FIG. 2, the memory cell array 1 includes a plurality of NAND-type cell units, each comprising four memory cells M connected in series. Each NAND-type cell unit includes one end connected via a selection transistor S 1 to a bit line BL, and the other end connected via a selection transistor S 2 to the common source line SRC. The control gate electrodes of the four memory cells M of each NAND-type memory cell unit are connected to four word lines WL, respectively. The control gate electrodes of the two selection transistors S are connected to selection gate lines SG 1 and SG 2 , respectively.
The memory cells M accessed at the same time, that is, the memory cells M connected to one word line WL, constitute a unit of storage area, called a “page.” The memory cells M of four pages, that is, the memory cells M connected to four adjacent word lines, form a larger unit of storage area, which is called a “block.” Only the memory cells constituting two blocks are illustrated in FIG. 2. Nonetheless, the four-value NAND flash memory of FIG. 1 may have an arbitrary number of blocks, for example, 1,024 blocks. Although 4,224 bit lines BL 0 to BL 4223 are shown in FIG. 2, the four-value NAND flash memory can have any other number of bit lines. For example, it may have 2,112 bit lines.
The bit line controller 2 includes a plurality of data memories 10 . Each data memory 10 is connected to two bit lines BL. Nonetheless, each data memory 10 may be connected to one, four, six or nine bit lines.
The column decoder 3 generates column-selecting signals CSL. Of these column-selecting signals, the signals CSL 0 and CSL 1 select the data memory 10 connected to the bit lines BL 0 and BL 1 . The data read from the memory cells is output to the data input/output buffer 4 .
The signals CSL 2 and CSL 3 select the data memory 10 connected to the bit lines BL 2 and BL 3 . The control data output from the data input/output buffer 4 is initially transferred to the data memory 10 that is connected to the bit lines BL 2 and BL 3 .
In a read operation, each data memory 10 reads data from the memory cell connected to one of the two bit lines which are connected to the data memory 10 . In a program operation, each data memory 10 applies a program-control voltage to the memory cell connected one of the two bit lines, in accordance with control data.
In a program verification operation, each data memory 10 detects the data-storage state of the memory cell connected to one of the two bit lines.
FIG. 3A illustrates one of the memory cells M shown in FIG. 2. FIG. 3B illustrates one of the selection transistors S 1 and S 2 shown in FIG. 2. In FIGS. 3A and 3B, the insulating films of the memory cell M and selection transistor S 1 or S 2 are not illustrated for the sake of simplicity.
The memory cell M and the selection transistor S 1 or S 2 have two n-type diffusion layers 12 each, which are in the surface of a p-type semiconductor substrate 11 (or a p-type well region). The two n-type diffusion layers 12 are a drain and a source.
As shown in FIG. 3A, the memory cell M includes a floating gate 14 and a control gate 16 . The floating gate 14 is formed on an insulating film 13 provided on the semiconductor substrate 11 (or the p-type well). The control gate 16 is formed on an insulating film 15 , which is provided on the floating gate 14 . The control gate 16 functions as a word line WL.
As shown in FIG. 3B, the selection transistor S 1 or S 2 includes a selection gate 18 formed on an insulating film 17 which is provided on the semiconductor substrate 11 (or the p-type well). The selection gate 18 functions as a selection gate line SG.
When a voltage higher than the threshold voltage of the memory cell M is applied to the control gate of the memory cell M, a channel is formed beneath the floating gate 14 of the memory cell M.
Assume that the capacitance between the control gate 16 and the floating gate 14 is 1 fF, that the capacitance between the floating gate 14 and the channel is 1 fF, that the capacitance between the channel and the substrate 11 is 0.25 fF and that the capacitance between the n-type diffusion layer 12 and the substrate 11 is 0.25 fF. Then, the ratio of the capacitive coupling of the control gate 16 to that of the channel (or the n-type diffusion layer 12 ) is 50%. Hence, if the voltage at the control gate 16 rises by 1V while the channel and n-type diffusion layer 12 are in a floating state, the voltage at the channel or the n-type diffusion layer 12 will increase by 0.5V.
FIG. 4 shows the NAND-type cell unit and the two selection transistors connected to the ends of the cell unit, illustrated in FIG. 2.
As FIG. 4 shows, the NAND-type cell unit comprises four memory cells M connected in series. One end of the NAND-type cell unit is connected to the common source line SRC via the first selection transistor S 1 . The other end of the NAND-type cell unit is connected to a bit line BL via the second selection transistor S 2 .
To erase data in the memory cells M of the NAND-type cell unit, the voltage Vsub of the substrate 11 is set at 20V, i.e., an erase voltage, and the selection gate lines SG 1 and SG 2 , common source line SRC and bit line BL are set at 20V, too. When the word lines WL 1 to WL 4 of one block from which data is to be erased are set at 0V, charges move from the floating gates of the memory cells into the substrate 11 . As a result, the memory cells gain a negative threshold voltage (that is, they store data “0”) When the word lines WL 1 to WL 4 connected to the memory cells of said block are set at 20V, charges do not move from the floating gates of these memory cells into the substrate 11 .
Let us assume that the selected word line of the selected block is WL 2 . In the program operation, a program voltage of 20V is applied to the selected word line WL 2 . At this time, a voltage of 0V is applied to the nonselected word lines WL 1 and WL 3 adjacent to the selected word line WL 2 , and a voltage of 11V is applied to the remaining nonselected word line WL 4 .
Further, the power-supply voltage VCC is applied to the selection gate line SG 1 , while the selection gate line SG 2 is set at 0V. All word lines WL and all selection gate lines SG of the nonselected block are set at 0V. The memory cells into which data is to be programmed are selected, one after another, first those connected to the word line WL 4 , then those connected to the word line WL 3 , next those connected to the word line WL 2 , and finally those connected to the word line WL 1 .
The NAND-type cell unit shown in FIG. 4 comprises four memory cells. Instead, each NAND-type cell unit may comprise eight memory cells or 16 memory cells. Assume each NAND-type cell unit comprises 16 memory cells. Then, when the fourth memory cell counted from the bit-line side is selected in the program operation, the program voltage of 20V is applied to the word line to which the control gate of the fourth memory cell is connected.
A voltage of 0V is applied to the two word lines to which the control gates of the third and fifth memory cells, which are adjacent to the fourth memory cell. And, a voltage of 11V is applied to the remaining 13 word lines to which the control gates of the remaining 13 memory cells are connected.
When the second memory cell counted from the bit-line side is selected in the program operation, the program voltage of 20V is applied to the word line to which the control gate of the second memory cell is connected. A voltage of 0V is applied to the two word lines to which the control gates of the first and third memory cells are connected, which are adjacent to the fourth memory cell. And, a voltage of 11V is applied to the remaining 13 word lines to which the control gates of the remaining 13 memory cells are connected.
When the first memory cell counted from the bit-line side is selected in the program operation, the program voltage of 20V is applied to the word line to which the control gate of the first memory cell is connected. A voltage of 0V is applied to the word line to which the control gate of the second memory cell counted from the bit-line side is connected. And, a voltage of 11V is applied to the remaining 14 word lines to which the control gates of the remaining 14 memory cells are connected.
Before programming of data into any selected block of the memory cell array 1 , data is erased at a time from all memory cells constituting the selected block, whereby these memory cells store data “0.” Then, data is programmed into the selected block, in the units of, for example, pages.
In the four-value NAND-type memory cell unit illustrated in FIG. 4, a bit line BL is set at the program-control voltage of 0V in order to program “1”, “2” or “3” into any memory cell connected to the bit line BL. The memory cells are sequentially selected, first the one connected to the word line WL 4 , next the one connected to the word line WL 3 , then the one connected to the word line LW 2 , and finally the one connected to the word line WL 1 . Hence, any memory cell located closer to the bit line than the selected memory cell stays in erased state.
Therefore, the program-control voltage (0V) applied to the bit line can be transferred to the selected memory cell even if the word line to which the memory cell closer to the bit line than the selected memory cell is set at a voltage of 0V.
In the selected memory cell, charges moves from the substrate to the floating gate, whereby the threshold voltage changes to a positive one.
In order to program data “0” into one memory cell, the bit line BL is set at the program-control voltage which is the power-supply voltage VCC. Since the selection gate line SG 1 is set at the power-supply voltage VCC, the selection transistor S 1 connected to the bit line BL are turned off during the program operation. The channel and n-type diffusion layers 12 of each memory cell are set to a floating state.
As a result, the channel potential of the selected memory cell whose corresponding word line is applied with the program voltage of 20V and the channel potential of the nonselected memory cell whose corresponding word line is applied with 11V rise. The two memory cells adjacent to the selected memory cell are turned off when their channel potential changes to a predetermined value, since 0V is applied to the corresponding word line.
If the above-defined ratio of the capacitive coupling of the selected memory cell is 50%, the channel potential of the selected memory cell rises to about 10V by virtue of the program voltage of 20V. In this case, the potential difference between the control gate and channel of the selected memory cell is so small that no charges are injected into the floating gate of the selected memory cell. Data “0” can thereby be programmed into the selected memory cell.
However, the two memory cells adjacent to the selected memory cell are not turned off even when 0V is applied to their control gates in the program operation, if they have excessively large negative threshold voltages. To turn off these memory cells reliably, a so-called soft-program operation is carried out, controlling the threshold voltages of the memory cells after data is erased at a time from all memory cells (of the selected block).
As mentioned above, a bit line BL is set at the program-control voltage of 0V to program “1,” “2” or “3” into the memory cell connected to the bit line BL. The time for which the voltage of 0V is applied to the bit line BL is adjusted in accordance with the data to be programmed into the memory cell, as will be described later in detail.
For example, the program-control voltage of 0V is applied to the bit line BL to program data “1” into the memory cell, for a shorter time than to program data “2” or data “3” into the memory cell. This is because it is sufficient to inject fewer charges into the floating gate of the memory cell to program data “1” than to program data “2” or data “3” into the memory cell.
Further, the program-control voltage of 0V may be applied to the bit line BL for three different periods to program “1”, “2” and “3”, respectively, into one memory cell. More specifically, 0V may be applied to the bit line BL for 1 μsec to program “1”, for 5 μsec to program “2”, and for 25 μsec to program “3.”
In the four-value NAND-type memory cell unit illustrated in FIG. 4, each memory cell must have a threshold voltage lower than 0V to program data “0”, a threshold voltage ranging from 0.3V to 0.7V to program data “1”, a threshold voltage ranging from 1.5V to 1.9V to program data “2”, and a threshold voltage ranging from 2.7V to 3.1V to program data “3.”
Assume that the memory cells connected to, for example, the word line WL 2 are selected. The word line WL 2 is a selected one of the word lines of one block and is at a voltage Vcg. The nonselected word lines WL 1 , WL 3 and WL 4 are set at a voltage Vread of 4.5V. The selection gate lines SG 1 and SG 2 of the selected block are set at the voltage Vread of 4.5V, too. All word lines WL and selection gate line SG 1 of any nonselected block are set at 0V. The common source line SRC is set at 0V or connected to the ground by a parasitic resistance.
Unless the potential of the common source line SRC rises due to the parasitic resistance, the following will occur:
(1) The voltage of the bit line charged to 1V and set in floating state will remain at the value of 1V if Vcg is 0V and the selected memory cell stores “1”, “2” or “3.” If the selected memory cell stores data “0,” the voltage of the bit line charged to 1V and set in floating state will falls to 0.5V.
(2) The voltage of the bit line charged to 1V and set in floating state will remain at the value of 1V if Vcg is 1.1V and the selected memory cell stores “2” or “3.” If the selected memory cell stores data “0” or data “1,” the voltage of the bit line charged to 1V and set in floating state will fall to 0.5V.
(3) The voltage of the bit line charged to 1V and set in floating state will remain at the value of 1V if Vcg is 2.3V and the selected memory cell stores “3.” If the selected memory cell stores data “0,” “1” or “2,” the voltage of the bit line charged to 1V and set in floating state will fall to 0.5V.
Due to the phenomena described in paragraphs (1) to (3), the data stored in any selected memory cell M can be identified.
FIG. 5 shows one of the data memories 10 (FIG. 2) which are identical.
As shown in FIG. 5, the data memory 10 comprises two sub-data circuits SD 1 and SD 2 . The first sub-data circuit SD 1 comprises clocked inverters C 11 and C 12 and n-channel MOS transistors Qn 3 , Qn 4 and Qn 5 . The second sub-data circuit SD 2 comprises clocked inverters C 13 and C 14 and n-channel MOS transistors Qn 10 , Qn 11 and Qn 12 .
In the program operation, the first sub-data circuit SD 1 and the second sub-data circuit SD 2 store first sub-data and second sub-data, respectively. In the read operation, they store first sub-data and second sub-data, respectively.
When the node Nai in the first sub-data circuit SD 1 is at “H” level, the circuit SD 1 stores either first read sub-data of “1” or first sub-data of “1.” When the node Na i+1 in the second sub-data circuit SD 2 is at “H” level, the circuit SD 2 stores either second read sub-data of “1” or second sub-data of “1.”
When the node Nai in the first sub-data circuit SD 1 is at “L” level, the circuit SD 1 stores either first read sub-data of “0” or first sub-data of “0.” When the node Na i+1 in the second sub-data circuit SD 2 is at “L” level, the circuit SD 2 stores either second read sub-data of “0” or second sub-data of “0.”
The data memory 10 further comprises p-channel MOS transistors Qp 1 and Qp 2 and n-channel MOS transistors Qn 1 , Qn 2 , Qn 8 , Qn 9 , Qn 6 , Qn 7 , and Qn 13 to Qn 19 .
The p-channel MOS transistors Qp 1 and Qp 2 receive signals PRSB 1 and PRSB 2 , respectively. When the signals PRSB 1 and PRSB 2 fall to “L” level, the transistor Qp 1 and Qp 2 set sub-data of “0” in the first sub-data circuit SD 1 and the first sub-data circuit SD 2 , respectively.
The n-channel MOS transistors Qn 1 and Qn 8 electrically connect the first sub-data circuit SD 1 and the second sub-data circuit SD 2 to the data input/output lines IOL and IOU, respectively. The gate electrode of the transistor Qn 1 is connected to receive the output CSLi from the column decoder 3 . The gate electrode of the transistor Qn 8 is connected to receive the output CSL i+1 from the column decoder 3 .
When the output CSLi rises to “H” level, the first sub-data circuit SD 1 of the data memory 10 connected to the bit lines BLi and BL i+1 is electrically connected to the data input/output line IOL. The data input/output lines IOL and IOU are connected to the data input/output buffer 4 . The lines IOL and IOU can therefore set sub-data items in the first sub-data circuit SD 1 and the second sub-data circuit SD 2 and output sub-data items read from the first sub-data circuit SD 1 to the data input/output buffer 4 .
The n-channel MOS transistors Qn 2 and Qn 9 detect whether the sub-data items stored in the sub-data circuits SD 1 and SD 2 are all “0” or not. The four-value NAND flash memory of FIG. 1 includes 2,112 data memories 10 . Thus, when 2,112 first sub-data items and 2,112 second sub-data items are all “0,” the common signal line PT and the ground line are electrically disconnected. This is why the n-channel MOS transistors Qn 2 and Qn 9 can detect whether the sub-data items stored in the sub-data circuits SD 1 and SD 2 are all “0” or not.
The n-channel MOS transistors Qn 6 and Qn 7 lower the voltage of the bit lines BL in accordance with the sub-data item stored in the first sub-data circuit SD 1 . The n-channel MOS transistors Qn 13 and Qn 14 lower the voltage of the bit lines BL in accordance with the sub-data item stored in the second sub-data circuit SD 2 . The n-channel MOS transistor Qn 15 charges the bit lines BL.
The n-channel MOS transistors Qn 16 and Qn 18 control the electrical connection between the sub-data circuits SD 1 and SD 2 , on the one hand, and the bit lines BLi and BL i+1 . They electrically connect the sub-data circuits SD 1 and SD 2 to the bit line BLi when signals BLC 1 and BLC 2 are at “H” level and “L” level, respectively.
When the signals BLC 1 and BLC 2 are at “L” level and “H” level, the first and second sub-data circuits SD 1 and SD 2 are connected to the bit line BL i+1 . The n-channel MOS transistors Qn 17 and Qn 19 control the electrical connection between the bit lines BLi and the source of voltage VBL 1 and the electrical connection between the bit line BL i+1 and the source of voltage VBL 2 .
When signal PRE 1 is at “H” level, the bit line BLi is connected to the source of voltage VBL 1 . When signal PRE 2 is at “H” level, the bit line BL i+1 is connected to the source of voltage VBL 2 .
The data stored in the memory cell M or the signal indicating the data-storage state of the memory cell M is transferred through the bit line BL i+1 or the bit line BL. In the first sub-data circuit SD 1 , the clocked inverter C 11 functions as a sense amplifier for detecting the logic level of the signal on the bit line BL. In the second sub-data circuit SD 2 , the clocked inverter C 13 functions as a sense amplifier for detecting the logic level of the signal on the bit line BL.
The clocked inverters C 11 and C 13 are identical in structure. One of them, or an inverter C 1 , will be described with reference to FIG. 6.
As shown in FIG. 6, the clocked inverter C 1 comprises an n-channel MOS transistor Qn 20 , and a p-channel MOS transistor Qp 4 . The inverter circuit includes an input terminal IN and an output terminal OUT. The n-channel MOS transistor Qn 21 and p-channel MOS transistor Qp 3 are provided to activate or deactivate the inverter formed of Qp 4 and Qn 20 in accordance with signals CLOCK and /CLOCK supplied to them, respectively. (The signal /CLOCK has been obtained by inverting the signal CLOCK.) More precisely, the inverter is activated when the signals CLOCK and /CLOCK are respectively at “H” level and “L” level, and is deactivated when the signals CLOCK and /CLOCK are respectively at “L” level and “H” level.
The control signal and control voltage generator 7 shown in FIG. 1 generates various signals SEN 1 , LAT 1 , SEN 2 , LAT 2 , PRO 1 , PRO 2 , BLC 1 , BLC 2 , PRE 1 , PRE 2 , VRFY 1 , VRFY 2 , VRFY 3 , PRO 10 , PRSTB 1 , PRSTB 2 , BIAS, VBL 1 , VBL 2 and VREG. These signals are used, in common, in all data memories 10 (FIG. 2). A signal PT is input to the control signal and control voltage generator 7 . The power-supply voltage VCC is, for example, 3V.
The first sub-data circuit SD 1 and the second sub-data circuit SD 2 store either sub-data “0” or sub-data “1.” Each sub-data circuit is designed to change sub-data “1” to sub-data “0” and hold sub-data “0” thus obtained.
The operation of the sub-data circuit 10 shown in FIG. 5 will be explained below.
First, the n-channel MOS transistors Qn 4 and Qn 5 or the n-channel MOS transistors Qn 11 or Qn 12 adjust the voltage of the bit line BL in accordance with the first sub-data or the second sub-data. Then, the clocked inverter C 11 or C 13 detects the voltage of the bit line BL when the signal PRO 1 or PRO 2 rises to “H” level.
Only when the first sub-data or the second sub-data is “0,” the voltage of the bit line BL rises to “H” level. When the signal PRO 1 or PRO 2 rises to “H” level, the voltage of “H” level on the bit line BL is applied to the input terminal of the clocked inverter C 11 or C 13 . As a result, the node Nai or the node Na i+1 is set at “L” level.
The sub-data “0” is stored by means of the clocked inverters C 12 or C 14 . This means that the sub-data “0” originally stored remains unchanged in the clocked inverters C 12 or C 14 . The sub-data “1” originally stored in the clocked inverters C 12 or C 14 is changed to sub-data “0” when the voltage of the bit line BL is at “H” level. When the voltage of the bit line BL is at “L” level, the sub-data “1” originally stored in the clocked inverters C 12 or C 14 remains unchanged.
The data memories 10 are not limited to the type illustrated in FIG. 5. Rather, the data memories 10 may have any one of various other structures.
FIG. 7 shows the word line controller 6 in detail. Although FIG. 1 shows only one controller 6 , the four-value NAND flash memory of FIG. 1 includes a plurality of word line controllers, each provided for one block of the memory cell array 1 .
As shown in FIG. 7, three block-address signals Pi (i=0 to Np), Qi (i=0 to Nq) and Ri (i=0 to Nr) are input to each word line controller 6 . Only a selected one of the signals Pi is at VCC. Similarly, only a selected one of the signals Qi is at VCC, and only a selected one of the signals Ri is at VCC. Np=7, Nq=7, and Nr=15. Hence, the block-address signals Pi, Qi and Ri can designate 1,024 blocks (=Np×Nq×Nr).
When the signals Pi, Qi and Ri are all at “H” level, the block they designate is selected. The signal Pi is input to an n-channel MOS transistor Qn 25 and a p-channel MOS transistor Qp 5 . The signal Qi is input to an n-channel MOS transistor Qn 26 and a p-channel MOS transistor Qp 6 .
The signal Ri is input to an n-channel MOS transistor Qn 27 and a p-channel MOS transistor Qp 7 . When the signals Pi, Qi and Ri are all at “H” level, the input to an inverter INV 2 is at “L” level, whereby the block designated by the signals Pi, Qi and Ri is selected. If the block thus selected is a defective one, a fuse F 1 will be cut. Once the fuse F 1 is cut, the input to the inverter INV 2 remains at “H” level even if the signals Pi, Qi and Ri are all at “H” level. The inverter INV 2 cooperates with a p-channel MOS transistor Qp 8 , fixing the input to the inverter INV 2 at “H” level.
When this block is selected, the gates of p-channel MOS transistors Qn 28 to Qn 31 are set at “H” level by using a depletion-type n-channel MOS transistor Qnd 1 . Further, signal SGD 1 is supplied to the selection gate line SG 1 , signals WLD 1 to WLD 4 are supplied to the word lines WL 1 to WL 4 , and a signal SGD 2 is supplied to the selection gate line SG 2 .
If the block has not been selected, the output of the NOR logic circuit G 2 will rise to “H” level when a signal WLGNDB is at “L” level. N-channel MOS transistors Qn 32 to Qn 34 are therefore turned on. As a result, the selection gate line SG 1 and the word lines WL 1 to WL 4 are connected to the ground.
N-channel MOS transistors Qn 22 to Qn 24 , capacitors C 1 and C 2 , an inverter INV 1 , and a NAND logic circuit G 1 constitute a circuit for applying a voltage VPPRW to the gates of the n-channel MOS transistors Qn 28 to Qn 31 of a selected block. The voltage VPPRW is higher than the power-supply voltage VCC.
A signal OSC has its level changed between “L” and “H” levels at regular intervals. A signal BWLHB is set at 0V in order to transfer the voltage VPPRW. This is because, in a depletion-type n-channel MOS transistor Qnd 1 , the power-supply voltage VCC can be transferred from the drain to the source when the gate is at the power-source voltage VCC and cannot be so transferred when the gate is at 0V.
Signals OSC, BWLHB, WLGNDB, SGD 1 , WLD 1 to WLD 4 , SGD 2 and VPPRW are control signals output from the control signal and control voltage generator 7 . They are used in common in all blocks of the memory cell array 1 .
FIG. 8 is a timing chart explaining how the four-value data is read from any selected memory cell.
Assume that the bit lines BL 0 , BL 2 , . . . , BLi, . . . , BL 4222 are selected (only the bit line BLi is shown in FIG. 8) and that the word line WL 2 is selected. The signals VBL 1 and VBL 2 remain at 0V, the signal BLC 2 at 0V, and the signal PRE 2 at VCC. The voltage of the bit line BL i+1 , the signals VRFY 1 and VRFY 3 , the signal PRO 10 , the signals CSLi and CSL i+1 and the signal VREG remain at 0V. Therefore, the signals VBL 1 , VBL 2 , BLC 2 , PRE 2 , the voltage of the bit line BL i+1 , the signals VRFY 1 , VRFY 3 , PRO 10 , CSLi and CSL i+1 and VREG are not illustrated in FIG. 8.
First, the gate selection line SG 1 of the selected block is set at 4.5V. At the same time, the signal PRE 1 changes from VCC to 0V and the signal BLC 1 changes from 0V to 7V, selecting the bit line BLi. The signal BIAS changes from 0V to 1.8V, charging the bit line BLi to 0.8V.
It is assumed that the threshold voltage of the n-channel MOS transistors Qn is 1V, unless otherwise specified. When the signal BIAS changes to 0V, the charging of the bit line BLi completes. Then, the selection gate line SG 2 and nonselected word lines WL 1 , WL 3 and WL 4 of the selected block, which have been at 0V, are set at 4.5V, and the selection word line WL 2 , which has been at 0V, is set at 2.3V.
Table 1 presented below shows the relationship between the data items stored in the memory cells and the threshold voltages of the memory cells.
| TABLE 1 | ||
| Memory Cell Data | Threshold Voltage | |
| 0 | lower than 0 V | |
| 1 | 0.3 V to 0.7 V | |
| 2 | 1.5 V to 1.9 V | |
| 3 | 2.7 V to 3.1 V | |
Even after the selected word line WL 2 is set at 2.3V, the bit line BLi remains at 0.8V as long as the memory cell stores data “3.” If the memory cell stores any other data, the bit line BLi is set lower than 0.5V. Upon lapse of a predetermined time, the selection gate line SG 2 and the nonselected word lines WL 1 , WL 3 and WL 4 are set at 0.0V.
After the selection gate line SG 2 is reset at 0V, the signals SEN 2 and LAT 2 are set to 0V from VCC. When the signal PRSTB 2 is set to 0V from VCC, the node Nb i+1 is set at VCC. After the signal PRSTB 2 is reset at VCC, the signal PRO 2 is set to 1.6V from 0V.
As long as the memory cell stores data “3,” the bit line BLi remains at 0.8V. Hence, the n-channel MOS transistor Qn 10 is off, and the node Nbi+1 remains at VCC.
When the memory cell stores data other than “3,” the bit line BLi is lower than 0.5V, n-channel MOS transistor Qn 10 is turned on, and the potential of the node Nb i+1 falls from the power-supply voltage VCC.
Assume that each bit line BL includes a capacitance of 5 pF and that the node Nb i+1 includes a parasitic capacitance of 0.1 pF. Then, the potential of the node Nb i+1 will fall to 0.55V or lower when the power-supply voltage VCC is 3V.
The signal SEN 2 is reset to VCC, activating the clocked inverter C 13 . The voltage of the node Nb i+1 is thereby sensed. The signal LAT 2 is reset to VCC, activating the clocked inverter C 14 . The logic level of the signal detected is latched by the second sub-data circuit SD 2 .
The signal PRO 2 is set at 0V again, electrically disconnecting the bit line BLi from the node Nb i+1 . Then, the signal PRE 1 is reset at VCC, and so is the bit line BL i+1 . It is thus determined whether or not the memory cell M has a threshold voltage of 1.3V or higher.
The sub-data read from the second sub-data circuit SD 2 is “0” only if the memory cell stores data “3.” If the memory cell stores any other data, the sub-data read from the circuit SD 2 is “1.”
Next, it is sensed whether or not the memory cell M has a threshold voltage of 0.0V or higher. The signal PRE 1 is set to 0V from VCC, and the signal BIAS is set to 1.8V from 0V. The bit line BLi is thereby charged to 0.8V. The signal BIAS is then set at 0V, and the bit line BLi is charged no more.
The selection gage line SG 2 and nonselected word lines WL 1 , WL 3 and WL 4 of the selected block are set to 4.5V from 0V. At the same time, the signal VRFY 2 is set to VCC from 0V. If the sub-data read from the second sub-data circuit SD 2 is “0” (that is, if the memory cell M stores data “3”), the n-channel MOS transistor Qn 12 is turned on, whereby the potential of the bit line BLi falls to 0V.
The word line WL 2 selected remains at 0.0V. Hence, the bit line BLi remains at 0.8V if the memory cell stores either “1” or “2.” If the memory cell stores either “0” or “3,” the bit line BLi is set at 0.5V or lower.
Upon lapse of a predetermined time, the selection gate line SG 2 and the nonselected word lines WL 1 , WL 3 and WL 4 are set at 0V. The signal VRFY 2 is also reset at 0V.
After the selection gate line SG 2 is reset at 0V, the signals SEN 1 and LAT 1 are set to 0V from VCC. When the signal PRSTB 1 is set to 0V from VCC, the node Nbi is set at VCC. After the signal PRSTB 1 is reset at VCC, the signal PRO 1 is set to 1.6V from 0V.
If the memory cell stores either “1” or “2,” the bit line BLi remains at 0.8V. The n-channel MOS transistor Qn 3 is therefore off, and the node Nb i+1 remains at VCC.
If the memory cell stores either “0” or “3,” the bit line BLi is at 0.5V or lower. The n-channel MOS transistor Qn 3 is therefore turned on, and the potential of the node Nbi falls from the power-supply voltage VCC.
Assume that each bit line BL includes a capacitance of 5 pF and that the node Nbi includes a parasitic capacitance of 0.1 pF. Then, the potential of the node Nbi falls to about 0.55V or lower.
The signal SEN 1 is reset to VCC, activating the clocked inverter C 11 . The voltage of the node Nbi is thereby sensed. The signal LAT 1 is reset to VCC, activating the clocked inverter C 12 . The logic level of the signal sensed is latched by the first sub-data circuit SD 1 .
The signal PRO 1 is set at 0V again, electrically disconnecting the bit line BLi from the node Nbi. Then, the signal PRE 1 is reset at VCC, and the bit line BLi is reset at 0V. It is thus sensed whether or not the memory cell M has a threshold voltage of 0.0V or higher.
The sub-data read from the first sub-data circuit SD 1 is “0” if the memory cell stores either “1” or “2.” If the memory cell stores either “0” or “3,” the sub-data read from the first sub-data circuit SD 1 is “1.”
Next, it is determined whether or not the memory cell M has a threshold voltage of 1.1V or higher. The signal PRE 1 is set to 0V from VCC, and the signal BIAS is set to 1.8V from 0V. The bit line BLi is thereby charged to 0.8V. The signal BIAS is then set at 0V, and the bit line BLi is charged no more.
The selection gage line SG 2 and nonselected word lines WL 1 , WL 3 and WL 4 of the selected block are set to 4.5V from 0V, and the selected word line WL 2 is set to 1.1V from 0V.
Once the selected word line WL 2 is set at 1.1V, the bit line BLi remains at 0.8V if the memory cell stores either “2” or “3.” If the memory cell stores either “0” or “1,” the bit line BLi is set at 0.5V or lower. Upon lapse of a predetermined time, the selection gate line SG 2 and nonselected word lines WL 1 , WL 3 and WL 4 are set at 0.0V.
After the selection gate line SG 2 is reset at 0V, the signals SEN 2 and LAT 2 are set to 0V from VCC, and the signal PRSTB 2 is set to 0V from VCC. Then, the node Nb i+1 is set at VCC. After the signal PRSTB 2 is reset at VCC, the signal PRO 2 is set to 1.6V from 0V.
If the memory cell stores either “2” or “3,” the bit line BLi remains at 0.8V. The n-channel MOS transistor Qn 10 is therefore off, and the node Nb i+1 remains at VCC.
If the memory cell stores either “0” or “1,” the bit line BLi is at 0.5V or lower. The n-channel MOS transistor Qn 10 is therefore on, and the potential of the node Nb i+1 falls from the power-supply voltage VCC to about 0.55V or lower. The signal SEN 2 is reset at VCC, activating the lock synchronous inverter C 13 . The potential of the node Nb i+1 is thereby sensed.
The signal LAT 2 is reset to VCC, activating the clocked inverter C 14 . The logic level of the signal detected is latched by the second sub-data circuit SD 2 . The signal PRO 2 is set at 0V again, electrically disconnecting the bit line BLi from the node Nb i+1 . Then, the signal PRE 1 is reset at VCC, and the bit line BLi is reset at 0V. It is thus determined whether or not the memory cell M has a threshold voltage of 1.1V or higher.
If the memory cell stores either “2” or “3,” the sub-data read from the second sub-data circuit SD 2 is “0.” If the memory cell stores either “0” or “1,” the sub-data read from the second sub-data circuit SD 2 is “1.” Finally, the selection gate line SG 1 is reset at 0V, and the signal BLC 1 is reset at 0V. The read operation is thereby completed.
As shown in FIG. 8, the data read from the memory cell M is stored into the data memory 10 . When the signals CSLi and CSL i+1 are set to VCC from 0V, the sub-data read from the first sub-data circuit SD 1 is supplied to the data input/output line IOL, and the sub-data read from the second sub-data circuit SD 2 is supplied to the data input/output line IOU. These data items thus supplied are supplied to the data input/output buffer 4 and output from the data input/output terminal 5 .
Table 2 presented below shows the relationship between the data items stored in the memory cells, the sub-data items read from the first sub-data circuit SD 1 , and the sub-data items read from the second sub-data circuit SD 2 .
| TABLE 2 | ||
| Memory | First | Second |
| Cell Data | Sub-Data | Sub-Data |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 2 | 0 | 0 |
| 3 | 1 | 0 |
FIG. 9 is a timing chart explaining how the word line controller 6 operates during the read operation which has been described with reference to FIG. 8.
The address signals Pi, Qi and Ri of the selected block are set to VCC from 0V, the signal BWLHB is set to 0V from VCC, and the signal VPPRW is set to 4.5V from VCC. The signal OSC starts fluctuating between 0V and VCC. Then, the gates of the n-channel MOS transistors Qn 28 to Qn 31 of the selected block are set at 5.5V.
The gate voltage of the n-channel MOS transistors Qn 28 to Qn 31 is the sum of the signal VPPRW and the threshold voltage of the n-channel MOS transistor Qn 24 . Since the signal WLGNDB remains at 0V, the gates of the n-channel MOS transistors Qn 32 to Qn 34 of the selected block are at 0V. Hence, the n-channel MOS transistors Qn 32 to Qn 34 are nonconductive.
Conversely, the gates of the n-channel MOS transistors Qn 28 to Qn 31 of any nonselected block are at the voltage of 0V, and these transistors are nonconductive. The gates of the n-channel MOS transistors Qn 32 to Qn 34 of the any nonselected block are at VCC, and these transistors are conductive.
The signal-selection gate signal SGD 1 is set to 4.5V from VCC, the signal-selection gate signal WLD 2 is set to 2.3V from 0V, and the signal-selection gate signals WLD 1 , WLD 3 and WLD 4 are set to 4.5V from 0V. The selection gate line SG 1 of the selected block is set to 4.5V from 0V. The selected word line WL 2 is set to 2.3V from 0V, and the word lines WL 1 , WL 3 and WL 4 are set to 4.5V from 0V. The selection gate line SG 2 is set to 4.5V from 0V.
Upon lapse of a predetermined time, the signal WLD 2 is reset to 0V from 2.3V, the signals WLD 1 , WLD 3 and WLD 4 are reset to 0V from 4.5V, and the signal-selection gate signal SGD 2 is reset to 0V from 4.5V. The word line WL 2 of the selected block is reset to 0V from 2.3V, and the word lines WL 1 , WL 3 and WL 4 are reset to 0V from 4.5V.
Similarly, the signals WLD 1 , WLD 3 and WLD 4 are set to 4.5V from 0V, and the selection gate SDG 2 is set to 4.5V from 0V. The word lines WL 1 , WL 3 and WL 4 of the selected block are set to 4.5V from 0V. The selection gate line SD 2 is set to 4.5V from 0V.
Upon lapse of a predetermined time, the signals WLD 1 , WLD 3 and WLD 4 are reset to 0V from 4.5V, the word lines WL 1 , WL 3 and WL 4 are reset to 0V from 4.5V, and the selection gate line SG 2 is reset to 0V from 4.5V.
The signal WLD 2 is set again to 1.1V from 0V, the signals WLD 1 , WLD 3 and WLD 4 are set again to 4.5V from 0V, and the signal-selection gate signal SGD 2 is set again to 4.5V from 0V. Also, the selected word line WL 2 of the block is set again to 1.1V from 0V, the word lines WL 1 , WL 3 and WL 4 are set again to 4.5V from 0V, and the selection gate line SG 2 is set again to 4.5V from 0V.
Upon lapse of a predetermined time, the signal WLD 2 is set to 0V from 1.1V, the signals WLD 1 , WLD 3 and WLD 4 are set to 0V from 4.5V, and the signal-selection gate signal SGD 2 is set to 0V from 4.5V. The selected word line WL 2 of the block is reset to 0V from 1.1V, the word lines WL 1 , WL 3 and WL 4 are reset to 0V from 4.5V, and the selection gate line SG 2 is reset to 0V from 4.5V.
The selection gate line SG 1 and word lines WL 1 to WL 4 of the nonselected block are set at 0V by the n-channel MOS transistors Qn 32 to Qn 34 . The address signals Pi, Qi and Ri of the selected block are set to 0V from VCC. The signal BWLHB is set to VCC from 0V, the signal VPPRW is set to VCC from 4.5V, and the signal OSC is set to 0V. The gates of the n-channel MOS transistors Qn 28 to Qn 31 of the selected block are reset to 0V.
The gates of the n-channel MOS transistors Qn 32 to Qn 34 of the selected block are reset to VCC, and these transistors are turned on. The block is, therefore, no longer selected. The selection gate line SG 1 is reset to 0V.
FIG. 10 is a timing chart explaining the program operation (page-programming) in the first embodiment.
Assume that the bit lines BLO, BL 2 , . . . , BLi, . . . and BL 4222 (only the bit line BLi is shown in FIG. 10), and that the word line WL 2 is selected.
Prior to a program operation, control data is initially set in the data memory 10 connected to the bit line BLi, as will be explained below.
The initial sub-data to be stored into the first sub-data circuit SD 1 is supplied to the input/output line IOL, and the initial sub-data to be stored into the second sub-data circuit SD 2 is supplied to the input/output line IOU. The signals CSLi and CSL i+1 are thereby set to VCC from 0V, and the initial sub-data items are stored into the sub-data circuits SD 1 and SD 2 , respectively. Initial control data items can be set in any desired number of data memories 10 by setting the corresponding signals CSL to VCC from 0V.
The initial control data items and the initial sub-data items have the relationship shown in Table 3 presented below:
| TABLE 3 | ||
| Initial | Initial Sub- | Initial Sub- |
| Control Data | Data of SD1 | Data of SD2 |
| 0 | 0 | 0 |
| 1 | 1 | 0 |
| 2 | 1 | 1 |
| 3 | 0 | 1 |
It is desired that the signals PRSTB 1 and PRSTB 2 be set to 0V from VCC and set back to VCC before all initial control data items are set, thereby to reset the control data items to “0” in all data memories 10 .
As will be descried later, the data-storage state of the memory cell M is not changed by the control data “0.” Hence, it suffices to set the initial control data from an external device in only desired ones of the 2,112 data memories 10 . Needless to say, the initial control data may be set in all 2,112 data memories 10 from that external device.
The signals BLC 2 , BIAS, VRFY 1 TO VRFY 3 and PRO 1 remain at 0V, the signals SEN 1 , LAT 1 , SEN 2 , LAT 2 , PRSTB 1 and PRSTB 2 remain at VCC, and the signals CSLi, CSL i+1 , VBL 1 AND VREG remain at 0V. This is why these signals are not shown in FIG. 10.
In the program operation, the selection gate line SG 1 of the selected block is set at VCC. At the same time, the signal PRE 1 is set to 0V from VCC and the signal BLC 1 is set to 7V from 0V, selecting the bit line BLi. If the second sub-data is “0” after the signal PRO 2 has been set at 7V, a program-control voltage of VCC is applied to the bit line BLi.
If the second sub-data is “1,” the bit line BLi remains at 0V. In other words, a program-control voltage of 0V is applied to the bit line BLi. In this case, the signal PRE 2 is set to 7V from VCC and the signal VBL 2 is set to VCC from 0V. A program-control voltage of VCC is thereby applied to the bit line BL i+1 which is not selected. The common source line SRC is set at VCC, too, in order to prevent punch-through of the selection gate line SG 2 of the selected block.
Thereafter, a program voltage Vpgm (16V to 20V) is applied to the selected word line WL 2 of the block. The word lines WL 1 and WL 3 provided on the sides of the word line WL 2 are set at 0V. The remaining word line WL 4 is set at 11V. The