Title:

System and Method for Independently Adjusting Multiple Compensations Applied to a Signal

Document Type and Number:

United States Patent Application 20080056344

Kind Code:

Abstract:

In one embodiment of the present invention, a method for adjusting a signal includes applying a plurality of compensation for distortion to a signal to generate an output signal. The method also includes, using a clock signal, sampling the output signal to generate a plurality of data values and boundary values, each value comprising either a high value or a low value based on the sampling of the output signal. The method also includes detecting a transition in value between two successive data values and determining a sampled boundary value between the two successive data values. The method further includes based at least on the high or low values of the boundary value and a plurality of data values before or after the boundary value, independently adjusting each compensation applied to the signal.

Inventors:

Hidaka, Yasuo (Cupertino, CA, US)

Plaque It!

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority under 35 U.S.C. § 119(e) of U.S. Provisional Application entitled “Adaptive Equalizer,” Ser. No. 60/803,451 filed May 30, 2006.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to signal communication and, more particularly, to a system and method for adjusting multiple compensations applied to a signal.

BACKGROUND OF THE INVENTION

When signals are communicated over communication media, the signals may suffer attenuation from phenomena such as skin effect and dielectric absorption. Signal receivers may include equalizers that compensate for this attenuation in order to improve the accuracy and efficiency of signal communication. It is desirable for the amount of compensation applied by equalizers to match the level of attenuation due to the media as closely as possible, in order to keep the output characteristics of the signal consistent independently of the particular communication path used to communicate the signal.

SUMMARY OF THE INVENTION

One technical advantage of certain embodiments is equalizing output signals. Certain embodiments compensate for signal attenuation resulting from the communication media used to communicate the signal. This allows the output characteristics of the signal to remain consistent independently of the communication path used to communicate the signal. Advantages associated with consistent output characteristics may include improved component response, as the signal level can be selected to fall within the dynamic range of system components. Furthermore, the signal can be maintained at a sufficient level to prevent information from being lost.

Other technical advantages of certain embodiments include adaptability to different communication media. Certain embodiments use variable gain amplifiers to adjust the degree of compensation applied to an incoming signal. Such embodiments may allow the amount of compensation to be adjusted for different media, thus increasing the versatility of equalizers embodying such techniques. Furthermore, such embodiments may also adapt to changes in media characteristics associated with process, voltage, and temperature variations.

Still another technical advantage of certain embodiments is improving the maximum operation speed of the equalizer and/or reducing the power consumed by the equalizer. Certain embodiments use existing clock and data recovery (CDR) functionality to generate output signal values used to monitor residual gain error and/or residual DC offset in the output signal. By using existing CDR functionality to generate the output signal values, a dedicated monitor circuit need not be used. By not using a dedicated monitor circuit, the loading on the equalizer output may be reduced, improving maximum operation speed of the equalizer and/or reducing the power consumed by the equalizer. In addition, chip area may be reduced and existing equalizer components and/or functionality may be reused in particular embodiments. Also, by not using a dedicated monitor circuit, design effort for the equalizer may also be reduced.

Still another technical advantage of certain embodiments is increased flexibility regarding data patterns usable by the equalizer. Particular embodiments may use data patterns with a single transition and are not limited to high frequency data patterns and/or data patterns having at least two transitions. Such flexibility may have several advantages, including, for example, allowing additional filter patterns (i.e., those having a single transition) to be applied to an output signal to counteract duty cycle distortion, discussed below.

Yet another technical advantage of particular embodiments is the ability to adjust more than one independent control parameter associated with an input signal using only output signal values. As discussed above, using output signal values provides several advantages over using a monitor circuit. In addition, adjusting more than one independent control parameter may increase the effectiveness of an equalizer in compensating for signal attenuation.

Still another technical advantage of particular embodiments is controlling gain in an adaptive equalizer consistently for periodic, quasi-periodic, and well-randomized data sequences. Another technical advantage of particular embodiments is reducing the negative effects of duty-cycle distortion and quasi-periodic and periodic signals by applying filter patterns to the signals before adjusting gain. The filter patterns may correspond to patterns of values that arise substantially equally in the sequences that start at even or odd data in the signals. Applying filter patterns to the signals may avoid unacceptable results in the gain control by balancing the adaptive action biases (duty cycle distortion) in the sequences that start at even or odd data.

A further technical advantage of particular embodiments is using a list of useful filter patterns in a balanced manner in conjunction with (quasi-) periodic signals to reduce the negative effects of duty-cycle distortion and the (quasi-) periodic signals. In these embodiments, the list of useful filter patterns associated with the (quasi-) periodic signals may be pre-determined and fixed. In alternative embodiments, the list of useful filter patterns may be adaptable to the incoming (quasi-) periodic signals. The filter patterns in a list may be used in a balanced manner to enhance their applicability to the (quasi-) periodic signals. Filter patterns may be used in a balanced manner by being selected from the list sequentially, randomly, or simultaneously. Timers may be used in particular embodiments to skip over an undetected filter pattern, thereby increasing the frequency of adaptive control actions.

Another technical advantage of certain embodiments is adjusting for residual DC offset observed in output signals. Adjusting DC offset compensation allows for improved component response (e.g., increased sensitivity). In particular embodiments, DC offset compensation may be adjusted using output signal values and without generating data errors in a signal. As discussed above, using output signal values (generated using existing CDR functionality) provides several advantages over using a monitor circuit. In addition, because data errors are not generated in a signal, adjustments to DC offset compensation may be made during receipt of a signal comprising real data traffic and not only during receipt of a signal carrying only test traffic. By making adjustments to DC offset compensation during receipt of a signal comprising real data traffic (and not test traffic only), component sensitivity may be improved during receipt of the real data traffic.

Yet another technical advantage of particular embodiments is correcting for a potential false locking problem in conjunction with adjusting for residual DC offset observed in output signals. The false locking problem arises when a clock recovery and an offset canceller interact improperly, leading to the sampled boundary and data values to be interchanged. Particular embodiments correct for the false locking problem by adjusting DC offset compensation based on the high or low value of each boundary value, regardless of whether the boundary value is between successive data values comprising a transition. To correct for the false locking problem in (quasi-) periodic signals where re-sampling is used, particular embodiments first monitor data DC imbalance (a proxy for the false locking problem) using output signal values. If an imbalance is detected, DC offset compensation is adjusted based on the detected imbalance. If an imbalance is not detected, DC offset compensation is adjusted based on the high or low values of only those boundary values between successive data values comprising transitions. In this way, data DC imbalance may vary within an acceptable range, even if re-sampling is used for a (quasi-) periodic data sequence.

Still another technical advantage of particular embodiments is using output signal values to cancel offsets in each path of a multi-path equalizer. In particular embodiments, offsets in each path may be cancelled without using any additional circuitry to monitor internal residual offset in the equalizer. In addition, in particular embodiments, the offset cancel control may be used during operation of the equalizer (i.e., without turning off any part of the equalizer circuit) and during receipt of a signal comprising real data traffic (and not only during receipt of a signal carrying only test traffic). By making adjustments to DC offset compensation during receipt of a signal comprising real data traffic (and not test traffic only), component sensitivity may be improved during receipt of the real data traffic.

Another technical advantage of particular embodiments where re-sampling is used is avoiding any locking of the re-sampling period with the period of a (quasi-) periodic signal. When locking occurs, the data patterns observed in re-sampled data may be different than the data patterns in the entire (quasi-) periodic signal, potentially skewing the control actions performed by the equalizer controller. Particular embodiments may avoid locking by varying the point at which the (quasi-) periodic signal is re-sampled in each re-sampling cycle.

Yet another technical advantage of particular embodiments is decoupling multiple control loops, such as, for example, the adaptive equalizer control and the offset canceller. Decoupling the multiple control loops may avoid delay in convergence time and potential instability in the control loops. Particular embodiments may decouple multiple control loops by making the loops insensitive to each other. For example, the adaptive equalizer control may be made insensitive to residual offset, and the offset canceller may be made insensitive to residual inter-symbol interference (ISI). To make the adaptive equalizer control and offset canceller insensitive to each other, in particular embodiments, two sets of complementary data patterns may be used in a balanced manner by the adaptive equalizer control and the offset canceller.

Still another technical advantage of particular embodiments is generating a particular average value of a binary objective variable (e.g., ISI level, equalization level, or other suitable objective variable) in an equilibrium state in a bang-bang control system that does not necessarily converge to zero, as is the case in typical bang-bang control systems. The binary objective variable may be, for example, the inverted correlation function applied to a boundary value between opposite data values and to the data value 1.5 bits (or symbols) before the boundary value. In particular circumstances, the optimal average value of a binary objective variable (e.g., ISI level, equalization level, or other suitable objective variable) in equilibrium may be greater or less than zero depending on various conditions, such as, for example, channel loss and the incoming signal itself. Thus, embodiments that generate an average value of the binary objective variable that converges closer to the optimal average value (than does zero) may be advantageous.

Another technical advantage of particular embodiments is dynamically generating a control target for an average value of a binary objective variable (e.g., ISI level, equalization level, or other suitable objective variable) in an equilibrium state. In particular embodiments, the optimal average ISI level is likely to be high for a high loss channel and low for a low loss channel. Thus, embodiments comprising a control target for the average value of a binary objective variable that dynamically varies with the value of the control variable may be advantageous.

Other technical advantages will be readily apparent to one skilled in the art from the attached figures, description, and claims. Moreover, while specific advantages have been enumerated above, particular embodiments may include some, all, or none of the enumerated advantages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example digital signal transmission system;

FIG. 2 is a block diagram illustrating the example digital signal transmission system of FIG. 1 in more detail;

FIG. 3 is a block diagram illustrating an example receiver in the example digital signal transmission system of FIG. 2 according to a particular embodiment;

FIGS. 4A, 4B, and 4C illustrate examples of a clock signal in comparison with an equalizer output signal exhibiting types of inter-symbol interference effects;

FIG. 5 is a flowchart illustrating a method for interpreting output signal values to compensate for residual inter-symbol interference according to a particular embodiment of the invention;

FIG. 6 is a table illustrating an example gain control scheme associated with the method of FIG. 5;

FIG. 7 is a flowchart illustrating an example method for interpreting output signal values for multiple independent control parameters in an analog second-order derivative equalizer according to a particular embodiment of the invention;

FIG. 8 is a table illustrating an example gain control scheme associated with the method of FIG. 7;

FIG. 9 is a flowchart illustrating an example method for interpreting output signal values for multiple equalizer parameters in a 3-tap FIR filter according to a particular embodiment of the invention;

FIG. 10 is a table illustrating an example gain control scheme associated with the method of FIG. 9;

FIG. 11 illustrates example boundary information affected by duty-cycle distortion;

FIG. 12 is a flowchart illustrating an example method for selecting a filter pattern to reduce the negative effect of duty-cycle distortion according to a particular embodiment of the invention;

FIG. 13 is a table illustrating an example distribution of 6-bit data patterns in even and odd 8B10B idle data sequences;

FIG. 14 is a table illustrating an example gain control scheme associated with using the example filter patterns derived from the table of FIG. 13 to adjust the gain applied to unmodified, first-order derivative, and second-order derivative components of an input signal;

FIG. 15 is a table illustrating an example distribution of 6-bit data patterns in even and odd 8B10B CJPAT data sequences;

FIG. 16 is a table illustrating an example gain control scheme associated with using the example filter patterns derived from the table of FIG. 15 to adjust the gain applied to unmodified, first-order derivative, and second-order derivative components of an input signal;

FIG. 17 is a flowchart illustrating an example method for generating a list of useful filter patterns dynamically according to a particular embodiment of the invention;

FIG. 18 is a flowchart illustrating another example method for generating a list of useful filter patterns dynamically according to a particular embodiment of the invention;

FIG. 19 is a flowchart illustrating yet another example method for generating a list of useful filter patterns dynamically according to a particular embodiment of the invention;

FIG. 20 is a flowchart illustrating an example method for using filter patterns in a balanced manner according to a particular embodiment of the invention;

FIG. 21 is a flowchart illustrating another example method for using filter patterns in a balanced manner according to a particular embodiment of the invention;

FIG. 22 is a flowchart illustrating an example method for skipping an undetected filter pattern after a period of time according to a particular embodiment of the invention;

FIGS. 23A, 23B, and 23C illustrate examples of a clock signal in comparison with an equalizer output signal exhibiting types of residual DC offset;

FIG. 24 is a flowchart illustrating a method for interpreting output signal values to cancel residual DC offset according to a particular embodiment of the invention;

FIG. 25 is a table illustrating an example offset control scheme associated with the method of FIG. 24;

FIG. 26 is a flowchart illustrating a method for correcting for false locking in canceling residual DC offset according to a particular embodiment of the invention;

FIG. 27 is a table illustrating an example offset control scheme associated with the method of FIG. 26;

FIG. 28 is a flowchart illustrating another method for correcting for false locking in canceling residual DC offset according to a particular embodiment of the invention;

FIG. 29 is a table illustrating an example offset control scheme associated with the method of FIG. 28;

FIG. 30 illustrates examples of a DC path output exhibiting negative residual DC offset, a first-order derivative path output exhibiting positive residual DC offset, and an equalizer output signal exhibiting mostly zero residual DC offset of an example first-order derivative equalizer in comparison with a clock signal;

FIG. 31 is a flowchart illustrating an example method for canceling residual DC offset in a first-order derivative analog equalizer according to a particular embodiment of the invention;

FIG. 32 is a table illustrating an example offset control scheme associated with the method of FIG. 31;

FIG. 33 is a flowchart illustrating another example method for canceling residual DC offset in a first-order derivative analog equalizer according to a particular embodiment of the invention;

FIG. 34 is a table illustrating an example offset control scheme associated with the method of FIG. 33;

FIG. 35 is a flowchart illustrating yet another example method for canceling residual DC offset in a first-order derivative analog equalizer according to a particular embodiment of the invention;

FIG. 36 is a table illustrating an example offset control scheme associated with the method of FIG. 35;

FIG. 37 is a flowchart illustrating yet another example method for canceling residual DC offset in a first-order derivative analog equalizer according to a particular embodiment of the invention;

FIG. 38 is a table illustrating an example offset control scheme associated with the method of FIG. 37;

FIG. 39 is a flowchart illustrating an example method for canceling residual DC offset in a second-order derivative analog equalizer according to a particular embodiment of the invention;

FIG. 40 is a table illustrating an example offset control scheme associated with the method of FIG. 39;

FIG. 41 is a flowchart illustrating an example method for reducing the effects of duty-cycle distortion according to a particular embodiment of the invention;

FIG. 42 is a flowchart illustrating another example method for reducing the effects of duty-cycle distortion according to a particular embodiment of the invention;

FIG. 43 is a flowchart illustrating an example method for varying the point at which re-sampling occurs in each re-sampling cycle according to a particular embodiment of the invention;

FIG. 44 is a flowchart illustrating another example method for varying the point at which re-sampling occurs in each re-sampling cycle according to a particular embodiment of the invention;

FIG. 45 is a flowchart illustrating yet another example method for varying the point at which re-sampling occurs in each re-sampling cycle according to a particular embodiment of the invention;

FIG. 46 is a flowchart illustrating an example method for decoupling multiple control loops according to a particular embodiment of the invention;

FIG. 47 is a flowchart illustrating another example method for decoupling multiple control loops according a particular embodiment of the invention;

FIG. 48 is a flowchart illustrating an example method for generating a particular average of a binary objective variable (e.g., ISI level, EQ level, or residual offset) in an equilibrium state according to a particular embodiment of the invention;

FIG. 49 is a flowchart illustrating an example method for dynamically generating a control target for an average value of a binary objective variable (e.g., ISI level) in an equilibrium state according to a particular embodiment of the invention;

FIG. 50 is a graph illustrating the results of applying an example control target equation to dynamically generate a control target for an average value of a binary objective variable in an equilibrium state in equalizer gain control according to a particular embodiment of the invention;

FIG. 51 is a table illustrating an example scheme for converting a high-frequency gain code into a DC-path gain code and a first-order-path gain code according to a particular embodiment of the invention; and

FIGS. 52A and 52B are graphs illustrating the results of applying the example scheme of FIG. 51 for converting a high-frequency gain code into a DC-path gain code and a first-order-path gain code according to a particular embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a block diagram illustrating an example digital signal transmission system 10. Digital signal transmission system 10 comprises transmitter 20, communication channel 30, and receiver 40. Transmitter 20 may comprise any suitable transmitter operable to transmit signals carrying digital information to receiver 40 over channel 30. In particular embodiments, transmitter 20 may communicate information at relatively fast rates. Channel 30 may comprise any suitable channel or other communication medium. Channel 30 may include, for example, a cable carrying a signal, an insulator insulating the cable, packaging around the cable, and/or connectors. Channel 30 is operable to receive signals from transmitter 20 and forward these signals to receiver 40. Receiver 40 may comprise any suitable receiver operable to receive signals from transmitter 20 over channel 30 and process the digital information in the received signals suitably.

In typical digital signal transmission systems, such as, for example, high-speed communication systems, the signal received by receiver 40 is typically distorted due to frequency-dependent attenuation, as illustrated in graph 32. Generally, there are two significant causes for signal attenuation in conductive communication media. The first significant cause is skin effect from conduction of the signal along the communication medium. The second significant cause is dielectric absorption of the signal by the communication medium. In general, the amount of signal loss in decibels due to skin effect is the product a_s·x·√f, where a_sis the coefficient of skin effect for the material, x is the length traveled along the material, and f is the frequency of the signal. The amount of loss due to dielectric absorption is the product a_d·x·f, where a_dis the coefficient of dielectric absorption of the material.

The relative significance of the effects can vary widely depending on the material and the frequency of the signal. Thus, for example, cables may have a coefficient of dielectric absorption that is much smaller than the coefficient of skin effect, so that loss due to skin effect dominates except at high frequencies. On the other hand, backplane traces may have higher coefficients of dielectric absorption, so that the loss due to dielectric absorption is comparable to or greater than the amount of loss due to skin effect. Furthermore, changes in operating conditions, such as temperature variations, may also affect signal characteristics.

A signal processed by receiver 40 may also exhibit residual DC offset distortion. Residual DC offset may be caused, for example, by fabrication technology, such as device geometry mismatch or threshold voltage mismatch, and/or by receiver components themselves. As described further below in conjunction with FIGS. 2 and 3, equalizers may be used to compensate for frequency-dependent attenuation, and offset cancellers may be used to cancel residual DC offset.

FIG. 2 is a block diagram illustrating the example digital signal transmission system of FIG. 1 in more detail. As can be observed, transmitter 20 comprises transmitter logic 22 and transmitter equalizer 24. Transmitter logic 22 may comprise any suitable logic operable to encode and transmit information. Transmitter equalizer 24 may comprise any suitable equalizer operable to compensate for distortion that the transmitted signals may experience over channel 30 due to frequency-dependent attenuation (for example, by adjusting the gain of signals to be transmitted). As an example only, in particular embodiments, the gain may be compensated as illustrated in graph 26. In this manner, equalizer 24 may apply pre-compensation (or equalization) to a signal before distortion occurs (using, e.g., transmitter pre-emphasis equalization). In particular embodiments, transmitter equalizer 24 may operate analogously to receiver equalizer 42, described below in conjunction with FIG. 3, based on feedback from receiver logic 47 However, it should be noted that equalizer 24 may apply compensation to the signal before the distortion occurs whereas equalizer 42 may apply compensation to the signal after the distortion occurs. It should also be noted that some or all of the logic in logic 47 (described below) may reside in transmitter 20 or in any other suitable location and not necessarily entirely in receiver 40.

Receiver 40 comprises receiver equalizer 42, equalizer output 46, receiver logic 47, gain control signal 48, and offset control signal 49. Receiver equalizer 42 may comprise any suitable equalizer operable to receive, at an input port, an input signal comprising an input data signal and apply a gain and/or offset to the received input data signal. Receiver logic 47 may comprise any suitable component or set of components, such as a sampler, operable to receive a clock signal. The clock signal may comprise any suitable clock signal, such as, for example, a recovered clock signal, which may be recovered from the input signal by a clock and data recovery (CDR) circuit. Using the received clock signal, receiver logic 47 is operable to sample the equalizer output 46, and based on the sampling, adjust the gain control signal 48 and/or offset control signal 49 applied to the input data signal to compensate for signal distortion, as described further below in conjunction with FIG. 3. As an example only, in particular embodiments, the gain may be compensated as illustrated in graph 52. Compensating the gain may produce, in particular embodiments, an equalizer output 46 that is completely compensated for frequency-dependent distortion, as illustrated in graph 54. In alternative embodiments, the equalizer output 46 may not be completely compensated. In particular embodiments, receiver 40 may be operable to communicate the information in equalizer output 46 downstream in any suitable manner and to any suitable number of one or more components.

As described in more detail below, receiver 40 compensates for signal distortions without using a dedicated monitor circuit to detect the distortions. By not using a dedicated monitor circuit, receiver 40 may achieve one or more technical advantages. These advantages may include, for example, improving the maximum operation speed of equalizer 42 and/or reducing the power consumed by receiver 40. In addition, chip area may be reduced, existing equalizer components and/or functionality may be reused, and/or the design effort necessary to design receiver 40 may be reduced (by not having to design a dedicated monitor circuit).

It should be noted that, in particular embodiments, pre-compensation may not be applied and transmitter 20 may not include an equalizer 24. In these embodiments, receiver 40 may compensate for distortion using equalizer 42. In alternative embodiments, transmitter 20 may include equalizer 24, and pre-compensation may be applied (i.e., transmitter pre-emphasis). In some of these embodiments, receiver 40 may also compensate for distortion using equalizer 42. In others of these embodiments, receiver 40 may not compensate for distortion using equalizer 42, and receiver 40 may not include an equalizer 42.

It should be noted that, in particular embodiments, the components applying compensation to a signal for distortion (e.g., logic 47 and equalizer 42, logic 47 and equalizer 24, and/or logic 47 and multiple equalizers) may be referred to as being part of an adaptive equalizer. It should also be noted that an adaptive equalizer may apply compensation in the manner described herein in contexts other than in a signal transmission system (as described). For example, an adaptive equalizer may apply compensation in the manner described herein (or in an analogous manner) in a recording channel, such as, for example, a magnetic recording channel or an optical recording channel. Also, compensation may be applied as described herein using any suitable type of equalizer, including, for example, a linear equalizer and a decision feedback equalizer.

FIG. 3 is a block diagram illustrating an example receiver 40 in the example digital signal transmission system 10 of FIG. 2 according to a particular embodiment. Equalizer 42 is operable to compensate for attenuation in a signal communicated to equalizer 42 using a communication medium 30. In the depicted embodiment, receiver logic 47 includes an adaptive controller 102 that adjusts the amount of gain applied to each of three signal paths 101A, 101B, and 101C based on the output signal sampled by sampler 104. Performance of equalizer 42 may suffer from residual DC offset. Receiver logic 47 may thus also include an offset controller 106 that adjusts the amount of DC offset compensation applied to an incoming signal based on the DC offset of the output signal sampled by sampler 104. Other components of equalizer 42 include variable gain limiting amplifier 110, mathematical operators (S) 112, delay generators 114, variable gain amplifiers 116, mixer 118, and drive amplifier 120. Other components of receiver logic 47 include the sampler 104 and clock 105. The output signal from sampler 104 is illustrated as output 50.

In order to compensate for frequency-dependent distortion, equalizer 42 may divide (using any suitable divider) the received input signal 108 among three signal paths 101A, 101B, and 101C, and selectively amplify the portion of the signal on each path using variable gain amplifiers 116. The first path 101A applies no mathematical operation to the received portion of the input signal. The second path 101B applies a first-order mathematical operation, such as, for example, a derivative operation, to the signal. This operation may be based on the frequency of the signal and is illustrated as mathematical operator (S) 112. As also described below, the third path 10C applies a second-order mathematical operation, such as, for example, a second-order derivative operation, to the signal. This operation may also be based on the frequency of the signal and is illustrated by the application of two mathematical operators (S) 112. By selectively amplifying the first- and second-order components of the signal, equalizer 42 approximately compensates for the frequency-dependent loss effects in channel 30 of FIG. 2. In alternative embodiments, equalizer 42 may have any suitable number of paths, including, for example, only one path. Equalizer 42 may be an example of an equalizer that applies compensation for distortion in parallel. It should be noted that compensation for distortion may be applied in parallel in any suitable manner (e.g., before and/or after distortion occurs) using any suitable equalization technique (e.g., transmitter pre-emphasis equalization and/or receiver equalization) and any suitable equalizer (e.g., an analog continuous-time first-order derivative filter, an analog continuous-time second-order derivative filter, a multi-tap finite-impulse-response filter, and/or a multi-tap decision-feedback equalizer). It should also be noted that, in alternative embodiments, compensation for distortion may be applied in series in any suitable manner (e.g., before and/or after distortion occurs) using any suitable equalization technique (e.g., transmitter pre-emphasis equalization and/or receiver equalization) and any suitable equalizer (e.g., a linear equalizer and/or a decision-feedback equalizer).

Adaptive controller 102 may comprise any suitable component or combination of components for analyzing information about the output signal of equalizer 42 and for adjusting the respective gain of each of the variable gain amplifiers 116. Adaptive controller 102 may include analog and/or digital electronic components, such as transistors, resistors, amplifiers, constant current sources, or other similar components. Adaptive controller 102 may also include suitable components for converting signals from analog signals to digital signals or vice versa. According to a particular embodiment, adaptive controller 102 includes a digital processor, such as a microprocessor, microcontroller, embedded logic, or other information-processing component.

In particular embodiments, adaptive controller 102 receives data and boundary value information associated with the output signal from sampler 104. This value information may include, for example, a high or low value (such as a “1” or a “0”) associated with each sampled data and/or boundary value. As described further below, based on this value information, adaptive controller 102 is operable to make suitable adjustments to the gain applied to the input data signal. To adjust the gain, in particular embodiments, adaptive controller 102 may adjust the bias current applied to each variable gain amplifier 116 to adjust the gain applied. One advantage of using bias currents to control amplifiers 116 is that it may adjust the amount of gain applied by the amplifier without changing the bandwidth of the amplifier, so that the amplifier can maintain its dynamic range even when the gain is increased.

Sampler 104 may comprise any suitable component configured to receive the equalizer output 46 from, for example, drive amplifier 120 and a clock signal from, for example, clock 105, and to sample the equalizer output 46 at set intervals defined by the clock signal. The sampling may be of data values and/or boundary values associated with the equalizer output 46 and may indicate a high or low value for each of these values. Sampler 104 may be further operable to forward sampled data values and boundary values to adaptive controller 102 and/or offset controller 106. In particular embodiments, sampler 104 may comprise a decision latch that performs sampling and 1-bit analog-to-digital conversion. In alternative embodiments, sampler 104 may comprise an analog sample and hold (S/H) circuit to sample and forward analog information for analog signal processing. In yet alternative embodiments, sampler 104 may comprise a multiple-bit analog-to-digital converter (ADC) and forward digital information for digital signal processing.

Offset controller 106 may comprise any suitable component or combination of components for analyzing information about the equalizer output 46 of equalizer 42 and for adjusting the amount of DC offset compensation applied at one or more stages of variable gain amplifier 116. In particular embodiments, offset controller 106 may include a microprocessor, microcontroller, embedded logic, and/or any other suitable component or combination of components.

In particular embodiments, offset controller 106 receives data and boundary value information associated with the equalizer output 46 from sampler 104. This value information may include, for example, a high or low value for each sampled data and/or boundary value. As described further below, based on this value information, offset controller 106 is operable to make suitable adjustments to the compensation (i.e., correction) voltage applied to the input data signal to correct or compensate (i.e., cancel) for any residual DC offset.

DC offset compensation may be imparted to the signal by various components of equalizer 42, and in particular, by variable gain amplifiers 116. In multi-stage variable gain amplifiers, the DC offset may be cumulative between stages. To correct the offset, offset controller 106 may apply a DC voltage to the signal being amplified by variable gain amplifier 116. According to a particular embodiment, offset controller 106 applies the compensation (i.e., correction) voltage in steps, wherein each step is applied at a different stage of variable gain amplifier 116. In such an embodiment, the amount of voltage applied at each step may be determined in any suitable manner. For example, the total correction voltage may be divided evenly between the steps, or it may be distributed in an amount proportional to the gain of the respective stages. It should be noted that some or all of the tasks performed by offset controller 106 may alternatively be performed by any other suitable component such as, for example, sampler 104.

Variable gain limiting amplifier (VGLA) 110 represents a component or collection of components for conditioning input signals 108 received by equalizer 42. The conditioning process adjusts the overall level of the input signal 108 to keep the signal within the dynamic range of mathematical operator (S) 112 and delay generator 114. In a particular embodiment, the amount of amplification applied by VGLA 110 is controlled by a bias current applied to VGLA 110.

Mathematical operator (S) 112 represents any component or collection of components that produces an output that is linearly proportional to the derivative of the incoming signal with respect to time, referred to as a “first-order operation.” Mathematical operator S 112 may include any suitable electronic components or circuitry such as, for example, a high-pass filter for performing the desired mathematical operation. According to a particular embodiment, the operation is a derivative operation, which takes the derivative of the incoming signal with respect to time, such as, for example, the voltage change of the incoming signal per 100 pico-seconds. Mathematical operator S 112 may be applied to a signal once or multiple times, resulting in an output signal that is proportional to the first, second, third, or higher order derivative of the incoming signal with respect to time based on the number of times S 112 is applied.

Delay generator 114 represents any component or collection of components that introduces a time delay in the communication of a signal. Delay generator 114 may include any suitable electronic components or circuitry. According to a particular embodiment, the delay introduced to a signal by delay generator 114 is approximately equal to the amount of time required for mathematical operator S 112 to be applied to a signal. Thus, delay generators 114 may be used to equalize the amount of time required for each portion of the input signal to travel down the corresponding path 101A, 101B, or 101C. In this way, the respective portions of the signals may be synchronized when they arrive at mixer 118.

Variable gain amplifiers 116 represent any component or components for amplifying a signal. Variable gain amplifiers 116 may include any suitable electronic components, and in a particular embodiment, each variable gain amplifier 116 is controlled by a bias current applied to the particular variable gain amplifier 116. In some cases, the response time of particular components performing the amplification may be too high, so that the amplifier cannot effectively amplify high-frequency signals that change rapidly between high and low values. Accordingly, variable gain amplifier 116 may include a series of stages, each of which performs part of the overall amplifications. Because no stage has the burden of performing all of the amplification, the time required for each stage to apply its respective gain is also less. This allows the multi-stage variable gain amplifier 116 to respond to higher frequency signals.

Variable gain amplifiers 116 may also impart a DC offset compensation to the signal. In multi-stage amplifiers, each stage may impart a DC offset compensation. One method of correcting the DC offset is to apply a correction voltage to correct the DC offset in the signal. The correction voltage may be applied entirely to the initial signal before it is amplified. However, applying the voltage entirely at one point may take the signal out of the dynamic range of one or more stages of amplifier 116. Furthermore, the voltage applied is recalculated and adjusted every time a new stage is added, and if the gain is variable in each stage, the DC offset may be unevenly distributed among the stages. In order to deal with this difficulty, particular embodiments may include applying a correction voltage at multiple stages of amplifier 116. This allows the DC offset for each stage to be corrected at that stage, reducing the chance that a correction will take the signal out of the dynamic range of the amplifier and removing the need to recalculate the DC offset for the entire array each time a stage is added. Furthermore, applying the correction voltage at each stage facilitates correcting the DC offset when the gain of each stage is independently variable, so that different stages may have different gains and may impart different DC offsets.

Mixer 118 represents a component or collection of components for recombining the signals on communications paths 101A, 101B, and 101C into a single signal. Mixer 118 may include any suitable electronic components. Mixer 118 provides the combined signal to drive amplifier 120. Drive amplifier 120 represents any component or collection of components for amplifying the combined signal. Drive amplifier 120 performs any suitable amplification on the combined signal to produce equalizer output 46 from equalizer 42 that has a sufficiently high signal level to allow effective communication of the output signal to sampler 104.

In operation, equalizer 42 receives an input signal 108 comprising an input data signal that has been attenuated by communication through a communication medium. VGLA 110 conditions the signal so that the signal level is within the dynamic range of mathematical operator (S) 112 and delay generator 114. Equalizer 42 divides the input signal among three paths 101A, 101B, and 101C. The signal on path 101A is delayed twice by delay generators 114 to synchronize the signal on path 101A with the signal on path 101B, which is subject to mathematical operator 112 once and delayed once by delay generator 114, and with the signal on path 101C, which is subject to mathematical operators 112 twice. Thus, the input signal components on the three paths 101A, 101B, and 101C correspond to the input signal subject to no mathematical operation, a first-order operation, and a second-order operation, respectively, and the three components are synchronized (using delay generators 114) to arrive at mixer 118 at approximately the same time.

Equalizer 42 then amplifies the signal on each path using the respective variable gain amplifier 116. The gain of each amplifier 116 is controlled by adaptive controller 102, and the gain may be different for each path 10A, 101B, and 101C. This allows equalizer 42 to provide different degrees of compensation for loss effects that have different proportionality relationships with the frequency of the signal. In general, the amount of compensation for a particular effect relative to the base signal is proportional to the ratio of the amplification of the corresponding path to the amplification of the unmodified signal on path 101A. Accordingly, path 101A may apply no gain or a slightly negative gain (in dB) in order to increase the relative effect of the compensation applied to other paths. Offset controller 106 corrects any DC offset imparted to the respective signals on each path 101A, 101B, and 101C by the corresponding amplifier 116 and/or by any other suitable component.

The amplified signals from each path are combined into a single signal by mixer 118. Drive amplifier 120 amplifies this output signal to allow effective communication of the output signal to another destination. Sampler 104 receives the equalizer output signal 46 from drive amplifier 120 and a clock signal from clock 105. Sampler 104 samples the equalizer output signal 46 at set intervals defined by the clock signal to generate data values and boundary values associated with the equalizer output signal 46. Alternatively, sampler 104 may sample the equalizer output signal 46 to generate only data values and forward the sampled data values and other suitable phase information to adaptive controller 102 and offset controller 106. Adaptive controller 102 and offset controller 106 may then derive one or more boundary values using the forwarded data values and phase information. Generally, if the phase is early, the high or low value of the boundary value is the same as the high or low value of the immediately preceding data value. If the phase is late, the high or low value of the boundary value is the same as the high or low value of the immediately following data value.

As described in further detail below, adaptive controller 102 analyzes sampled data and boundary values associated with the equalizer output signal 46 to adjust the amount of gain applied to one or more paths 101A, 101B, and 101C to suitably compensate for residual frequency-dependent attenuation. Offset controller 106 analyzes sampled data and boundary values associated with the equalizer output signal 46 to adjust the amount of correction voltage applied to one or more paths 101A, 101B, and 101C to suitably cancel residual DC offset.

One advantage of not using a dedicated monitor circuit (used in many typical systems) in the adaptive equalizer described above is that the loading on the equalizer output 46 may be reduced in particular embodiments. Especially in high-speed electrical circuits, reducing the loading on equalizer output 46 may improve maximum operation speed of equalizer 42 and/or reduce the power consumed by equalizer 42. Not using a dedicated monitor circuit may also reduce chip area, may efficiently reuse existing receiver components (i.e., clock 105), and may reduce the design effort necessary to design dedicated monitor circuits.

Although particular embodiments of equalizer 42 have been described in detail, there are numerous other possible embodiments. Possible variations include, for example, applying different or additional mathematical operations to paths 101A, 101B, and 101C in order to compensate for different loss properties, increasing or decreasing the number of paths, using manual control for controllers 102 and 106 rather than automatic feedback control, using single-stage amplifiers 116, receiving (and suitably adjusting) a signal comprising differential sequences such as in, for example, low-voltage differential signaling (LVDS), and other variations suggested by the description above. In general, components may be rearranged, modified or omitted in any suitable manner, and the functions performed by components may be distributed among different or additional components or consolidated within single components in any suitable way. Accordingly, it should be understood that implementations of receiver 40, equalizer 42, and receiver logic 47 may include any such variations and that particular embodiments of the present invention may be used in any suitable equalizer context. Reference is made to the Non-Provisional Application entitled “Adaptive Equalizer with DC Offset Compensation,” Ser. No. 10/783,170, filed Feb. 20, 2004, for greater detail about particular example equalizer components that may be used.

As discussed above, a signal transmitted over channel 30 and received at receiver 40 may experience frequency-dependent attenuation. At receiver 40, equalizer 42 may apply a gain to the received input signal to compensate for the attenuation exhibited by the signal. Receiver logic 47 may analyze the adjusted equalizer output signal 46 for residual attenuation and adjust the gain applied by equalizer 42 to the input signal based on this feedback. Specifically, sampler 104 may receive the equalizer output signal 46 (the adjusted input signal) and a clock signal and sample the output signal at particular points determined by the clock signal to generate data values and boundary values. Sampler 104 may then forward these data and boundary values to adaptive controller 102 for suitable analysis (as described below). Based on this analysis, adaptive controller 102 may adjust the gain applied to the incoming input signal.

FIGS. 4A, 4B, and 4C illustrate examples of a clock signal in comparison with an equalizer output signal exhibiting types of inter-symbol interference effects. In particular embodiments, sampler 104 may receive signals such as those illustrated in these figures and sample the output signal according to a 2× over-sampling clock and data recovery (CDR) scheme. In such a scheme, sampler 104 may sample the received signal two times per data bit period, which may be defined by the clock signal. For one data bit period, sampler 104 may, for example, sample the output signal once at a point in the output signal that should correspond to a data value and once at a point in the output signal that should correspond to a boundary value. Based on an analysis of particular data and boundary values, as described further below, adaptive controller 102 may adjust the gain applied to the signal received by equalizer 42.

FIG. 4A illustrates an example 200 of a clock signal in comparison with an equalizer output signal 46 that is in-phase with the clock signal and that exhibits no inter-symbol-interference effects. The clock signal defines data points (illustrated as arrows corresponding to D0-D5) and boundary points (illustrated as arrows corresponding to E0-E4). Sampler 104 may sample the equalizer output signal 46 at a data point to generate a data value (i.e., D0-D5) and at a boundary point to generate a boundary value (i.e., E0-E4). Each sampled data value and boundary value may comprise a low value (illustrated as “L”), a high value (illustrated as “H”), or an random value (illustrated as “X”) that takes either a high value or a low value randomly. In particular embodiments, a low value may comprise a “0,” a high value may comprise a “1,” a random value may randomly comprise either a “0” or a “1,” and an average of random values may comprise “0.5.” In alternative embodiments, a low value may comprise a “−1,” a high value may comprise a “1,” a random value may randomly comprise either a “−1” or a “1,” and an average of random values may comprise “0.” Sampler 104 may forward sampled data values and boundary values to adaptive controller 102 for suitable processing and adjustment of gain.

A change from a high to a low value or from a low to a high value between two successive data values is referred to as a transition. In the illustrated example 200, transitions occur between low data value D2 and high data value D3, between high data value D3 and low data value D4, and between low data value D4 and high data value D5. In a signal exhibiting no residual inter-symbol interference effects, such as in example 200, each boundary value between two successive data values comprising opposite values (e.g., boundary values E2, E3, and E4) typically comprises a random value (illustrated as “X”). For such a signal, adaptive controller 102 may adjust the gain applied to the input signal up or down randomly, as inter-symbol interference effects are already being fully compensated or do not exist. If the numbers of up adjustments and down adjustments are substantially equal, the gain applied to the input signal remains on average at the same level. If the numbers of up adjustments and down adjustments are not substantially equal, the gain applied to the input signal may drift slightly from the initial level. Such drift of the gain level may produce slight residual inter-symbol interference. The equalizer receiver may detect this interference and correct the gain back to the average initial level, as illustrated below.

FIG. 4B illustrates an example 300 of a clock signal in comparison with an equalizer output signal 46 that is in-phase with the clock signal but that exhibits under-compensated residual inter-symbol interference effects. In this case, the equalizer has not compensated the signal sufficiently, and the signal is low-frequency oriented. In a low-frequency oriented signal, if a data pulse (e.g., the data pulse at D3) occurs after several successive data values of the same high or low value have passed (e.g., D0-D2), the data pulse height may be lowered by the lack of high-frequency component. Also, the boundary values before (e.g., E2) and after (e.g., E3) the data pulse will likely be the same as the high or low value of the data value (e.g., D2) before the pulse (i.e., they will not comprise a random value). Thus, as described further below, upon analyzing particular data values and boundary values, adaptive controller 102 may increase the gain applied to the input signal to compensate for the low-frequency distortion. It should be noted, however, that in particular embodiments and as described below, adaptive controller 102 may not be able to compensate for the low-frequency distortion exhibited by the output signal until a transition (e.g., between D2 and D3) occurs. The boundary value after a few successive transitions (e.g., at E4) may comprise a random value “X” because such successive transitions may increase a high-frequency component and decrease a low-frequency component in the signal, and hence, may reduce the sensitivity of the boundary value to the residual inter-symbol interference.

FIG. 4C illustrates an example 400 of a clock signal in comparison with an equalizer output signal 46 that is in-phase with the clock signal but that exhibits over-compensated residual inter-symbol interference effects. In this case, the equalizer has applied too much compensation to the input signal, and the signal is high-frequency oriented. In a high-frequency oriented signal, if a data pulse (e.g., the data pulse at D3) occurs after several successive data values of the same high or low value have passed (e.g., D0-D2), the pulse height may be raised by the emphasized high-frequency component. Also, the boundary values before (e.g., E2) and after (e.g., E3) the data pulse will likely be the opposite of the high or low value of the data value (e.g., D2) before the data pulse (i.e., they will not comprise a random value). Thus, as described further below, upon analyzing particular data values and boundary values, adaptive controller 102 may reduce the gain applied to the input signal to compensate for the high-frequency distortion. It should be noted, however, that in particular embodiments and as described below, adaptive controller 102 may not be able to compensate for the high-frequency distortion exhibited by the output signal until a transition (e.g., between D2 and D3) occurs. The boundary value after a few successive transitions (e.g., at E4) may comprise a random value “X” because such successive transitions may increase a high-frequency component and decrease a low-frequency component in the signal, and hence, may reduce the sensitivity of the boundary value to the residual inter-symbol interference.

FIG. 5 is a flowchart illustrating a method 500 for interpreting output signal values to compensate for residual inter-symbol interference according to a particular embodiment of the invention. The method begins at step 510, in which an output signal is sampled using a clock signal. The output signal may be the output of an equalizer, and the output signal may be sampled according to a clock signal, as described above in conjunction with FIG. 3.

In particular embodiments, the output signal may be sampled at reference data points and boundary points determined by the clock signal. Alternatively, the output signal may not be sampled at boundary points, and boundary values corresponding to these non-sampled points may be derived. In particular embodiments, adaptive controller 102 may derive boundary values from sampled data values and other phase information (i.e., whether the phase of the output signal is early or late). For example, if the phase of the output signal is early, adaptive controller 102 may determine that the high or low value of the boundary value is the same as the high or low value of the data value immediately preceding the boundary value. If the phase of the output signal is late, adaptive controller 102 may determine that the high or low value of the boundary value is the same as the high or low value of the data value immediately after the boundary value.

At step 520, after the output signal is sampled, the sampled data values may be analyzed to determine if a transition has occurred in the values. This analysis may be performed, for example, by adaptive controller 102. At step 530, if a transition is not detected, the method returns to step 520. If a transition is detected between successive data values, the method proceeds to step 540. It should be noted that, in particular embodiments, a transition may be detected by comparing the received data values to each other directly. In alternative embodiments, a transition may be detected by comparing the received data values and boundary values to pre-defined value patterns that comprise a transition (and that correspond to particular adaptive control actions). It should further be noted that, in particular embodiments, adaptive action may take place after detecting only one transition.

If a transition is detected, at step 540, the boundary value between the successive data values comprising the transition is compared to the data value 1.5 bits (or symbols) before the boundary value. In particular embodiments, the relationship between the boundary value and the data value 1.5 bits (or symbols) before the boundary value may determine the adaptive equalizer action response. For example, in particular embodiments, an exclusive-OR (XOR) operation (or an exclusive-NOR (XNOR) operation) may be applied to the two values. In such embodiments, the result of the XOR operation (or XNOR operation) may correspond to a particular type of inter-symbol interference exhibited by the output signal and, thus, may be used to determine the adaptive equalizer action response. In alternative embodiments, an inverted correlation function (or a correlation function) may be applied to the two values. In such embodiments, the result of the inverted correlation function (or correlation function) may correspond to a particular type of inter-symbol interference exhibited by the output signal and, thus, may be used to determine the adaptive equalizer action response. In yet alternative embodiments, the boundary value and the data value 1.5 bits (or symbols) before the boundary value may be compared by comparing the received data values and boundary values to pre-defined value patterns (that correspond to particular adaptive control actions). Also, in alternative embodiments, data values closer or farther from the boundary value may be used, and not necessarily the data value 1.5 bits (or symbols) before the boundary value. It should be noted that although some of the discussion herein is phrased in terms of bits, such discussion may alternatively be interpreted to refer to symbols, if appropriate.

It should also be noted that the analysis of boundary values described above (and below) is an example only. More generally, error values, such as, for example, the particular boundary values described, may indicate residue of distortion (frequency-dependent distortion and/or DC-offset distortion, discussed further below) based on a sampling of an output signal. Based on the error value generated, the loss compensation (and/or the offset compensation) applied to a data signal may be adjusted. In particular embodiments, for example, the error value may comprise a pulse-width value (wide, narrow, or typical), and the pulse-width value may be derived from two successive boundary values and an in-between data value in three successive data values with two transitions. The pulse-width value may be used to adjust the loss compensation applied.

At step 550, a determination is made whether the boundary value and the data value 1.5 bits (or symbols) before the boundary value have the same high or low value. In particular embodiments, the two values may be compared in the XOR (or XNOR) operation, as described above. In alternative embodiments, an inverted correlation function (or correlation function) may be applied to the two values. In yet alternative embodiments, the two values may be compared by comparing them to pre-defined patterns. If the two values have the same high or low value (e.g., if the XOR result equals “0”, if the inverted correlation function result equals “−1”, or if the values correspond to a particular pre-defined value pattern), the method proceeds to step 560. At step 560, the equalizer increases the gain applied to the signal. The increase in gain compensates, in particular embodiments, for the under-compensated residual inter-symbol interference exhibited by the signal. Such interference is suggested by the “0” XOR result, as illustrated in FIG. 4B.

It should be noted that, in alternative embodiments, the adaptive control action may be any suitable adaptive control action in various conventional adaptive control algorithms. For instance, the adaptive control action may be based on conventional adaptive control algorithms, such as the Least-Mean-Square (LMS) algorithm, the Sign-Sign-Least-Mean-Square (SS-LMS) algorithm, the Zero-Forcing (ZF) algorithm, and so on.

If, at step 550, a determination is made that the boundary value and the data value 1.5 bits (or symbols) before the boundary value have the opposite high or low value (e.g., if the XOR result equals “1”, if the inverted correlation function result equals “+1”, or if the values correspond to a particular pre-defined value pattern), the method proceeds to step 570. At step 570, the equalizer decreases the gain applied to the signal. The decrease in gain compensates, in particular embodiments, for the over-compensated residual inter-symbol interference exhibited by the signal. Such interference is suggested by the “1” XOR result, as illustrated in FIG. 4C.

It should be noted that, in particular embodiments, steps 550, 560, and 570 may be performed by adaptive controller 102, and the applied gain may be adjusted using variable gain amplifiers 116. Also, in particular embodiments, if gain is applied to more than one signal path (e.g., to paths 101 in example equalizer 42), the applied gain may be adjusted in one path and fixed for the other paths. In alternative embodiments, an independent control variable may be mapped to the plurality of paths using a particular function, and gain may be applied to the paths according to the mapping. Alternatively, gain may be adjusted independently for each path, as discussed further below in conjunction with FIGS. 7-10.

FIG. 6 is a table 600 illustrating an example gain control scheme associated with the method 500 of FIG. 5. Each row 602 corresponds to a particular pattern of values for which a particular adaptive equalizer control action is performed. Columns 610 include a high or low value (“+1” or “−1” in this particular example, although it may be “1” or “0,” or any other suitable values, in other examples) for each of a series of sampled data and boundary values. Column “D1” includes a first sampled data value of an output signal, column “D2” includes a second sampled data value of the output signal, column “D3” includes a third sampled data value of the output signal, and column “E2” includes the boundary value between the second and third data values. These values are similar to those illustrated in FIGS. 4A-4C. As can be observed, a transition occurs between data values in columns “D2” and “D3” in each pattern.

It should be noted that the pattern of values in each row 602 may be sampled by sampler 104 and sent to adaptive controller 102. In particular embodiments, adaptive controller 102 may receive a greater number of values than that illustrated, including, for example, the boundary value between data values in columns “D1” and “D2.” Alternatively, as discussed above, adaptive controller 102 may receive only sampled data values and other phase information, and particular boundary values (including, for example, boundary values in column E2) may be derived from the data values and phase information (and may not be sampled by sampler 104).

Column 612 includes ISI levels. An ISI level is derived from particular values associated with an output signal. For example, an ISI level may be the result of an inverted correlation function applied to a boundary value between two data values comprising a transition and the data value 1.5 bits before the boundary value. In particular embodiments, the ISI level may be calculated as the inverted value of the product of the boundary value and the data value using “+1/−1” values corresponding to “high/low” values. In table 600, an ISI level in column 612 is the result of an inverted correlation function applied to the boundary value in column E2 and the data value in column D1 (1.5 bits before the boundary value) in the same row 602. The ISI level may be calculated as the inverted value of the product of E2 and D1 using “+1/−1” values corresponding to “high/low” values. As illustrated in columns 614 and 616, an ISI level of “−1” is associated with an under-compensated equalization level and an increase in equalizer compensation. An ISI level of “+1” is associated with an over-compensated equalization level and a decrease in equalizer compensation. Thus, based on the ISI level, a particular adaptive equalizer action is applied. In alternative embodiments, the received data and boundary values may be compared to pre-defined value patterns, and these pre-defined value patterns may correspond to particular adaptive control actions.

It should be noted that, in particular embodiments, adaptive controller 102 may receive a stream of sampled values and select appropriate ones of these values (e.g., the boundary value between two data values comprising a transition and the data value 1.5 bits before the boundary value). Adaptive controller 102 may then, for example, derive ISI levels from these selected values by applying an inverted correlation function to these selected values. Adaptive controller 102 may then apply a suitable adaptive control action based on the result of the inverted correlation function. Alternatively, adaptive controller 102 may compare the sampled values to pre-defined patterns of values (that correspond to particular adaptive control actions). Based on the particular pre-defined pattern of values to which the sampled values corresponds, adaptive controller 102 may apply the corresponding adaptive control action.

Modifications, additions, or omissions may be made to the systems and methods described without departing from the scope of the invention. The components of the systems and methods described may be integrated or separated according to particular needs. Moreover, the operations of the systems and methods described may be performed by more, fewer, or other components.

In particular embodiments, an equalizer, such as equalizer 42 of FIG. 3, may control more than one independent parameter, such as, for example, the unmodified, first-order, and second-order components of a signal. Examples of multi-parameter (multi-dimensional) equalizers include second-order derivative equalizers and 3-tap finite impulse response (FIR) filters. As discussed above, method 500 may be used in multi-dimensional equalizers if, for example, the applied gain is adjusted for one parameter and fixed for the other parameters. Alternatively, method 500 may be used in multi-dimensional equalizers if the applied gain is adjusted according to a particular function that incorporates the plurality of independent parameters (but does not adjust gain independently for each independent parameter). In the alternative, the applied gain may be adjusted independently for each independent control parameter. In a 3-tap FIR filter, for example, the second and third tap coefficients may be adjusted independently, and each of these adjustments may comprise an adjustment to compensation for distortion, as described further below.

Compensation, such as, for example, gain, may be adjusted independently for each independent control parameter based on particular relationships between one or more sampled data values and the sampled data value 1.5 bits before a boundary value that is between successive data values that comprise a transition. Particular relationships may, for example, correspond to particular types of inter-symbol interference for particular independent control parameters. When, for example, adaptive controller 102 detects such relationships among a plurality of sampled data values (e.g., using pre-defined data value patterns), adaptive controller 102 may apply particular adaptive equalizer control actions to adjust the particular one or more independent control parameters.

The pre-defined data value patterns used by adaptive controller 102 to compare to the incoming stream of sampled data values may be particularly sensitive to inter-symbol interference for particular independent control parameters. These patterns may be selected, for example, based on the sensitivity of the boundary value between the data values comprising a transition to the independent control parameter being adjusted. In particular, these patterns may be selected based on the partial derivative of the equalized-channel impulse response with respect to that independent control parameter (e.g., on the sign and magnitude of the partial derivative). This is because equalizer output signal 46 is represented as a convolution of the transmit data sequence and the equalized-channel impulse response.

For example, in an analog, second-order derivative equalizer, the partial derivative of the equalized-channel impulse response with respect to the first-order derivative gain may be assumed to be negative at 1.5 and 2.5 bits after the peak. Hence, if the first-order derivative gain is too high, a correlation between a boundary value and a data value 1.5 and 2.5 bits before the boundary value will be likely both negative. On the other hand, if the first-order derivative gain is too low, a correlation between a boundary value and a data value 1.5 and 2.5 bits before the boundary value will be likely both positive. This is because the data corresponds to the peak of the impulse response and the boundary corresponds to the tail after the peak in the impulse response. The partial derivative of the equalized-channel impulse response with respect to the second-order derivative gain may be assumed to be negative at 1.5 bits after the peak and positive at 2.5 bits after the peak. Hence, if the second-order derivative gain is too high, a correlation between a boundary value and a data value 1.5 bits before the boundary value will be likely negative, and a correlation between a boundary value and a data value 2.5 bits before the boundary value will be likely positive. On the other hand, if the second-order derivative gain is too low, a correlation between a boundary value and a data value 1.5 bits before the boundary value will be likely positive, and a correlation between a boundary value and a data value 2.5 bits before the boundary value will be likely negative. Using these relationships, various techniques (e.g., method 700, described below) may be used to adjust the gain applied to a first-order derivative component of an input signal and the gain applied to a second-order derivative component of the input signal.

As another example, in a 3-tap finite impulse response (FIR) filter equalizer where the main tap is the first tap, the partial derivative of the equalized-channel impulse response with respect to the second tap coefficient may be assumed to be positive at 1.5 and 2.5 bits after the peak. The partial derivative of the equalized-channel impulse response with respect to the third tap coefficient may be assumed to be zero at 1.5 bits after the peak and positive at 2.5 bits after the peak. Using these relationships, various techniques (e.g., method 1000, described below) may be used to adjust the second tap coefficient and the third tap coefficient. In this manner, the FIR filter equalizer may apply multi-tap FIR-filter equalization in parallel. It should be noted that different relationships may be used for different types of equalizers. For example, different relationships may be used for a multi-tap decision-feedback equalizer applying multi-tap decision-feedback equalization in parallel.

FIG. 7 is a flowchart illustrating an example method 700 for interpreting output signal values for multiple independent control parameters in an analog second-order derivative equalizer according to a particular embodiment of the invention. For an analog second-order derivative equalizer, three independent control parameters may be controlled, including, for example, the gain applied to an unmodified portion of an input signal, the gain applied to a portion of the input signal modified to be the first-order derivative of the input signal, and the gain applied to a portion of the input signal modified to be the second-order derivative of the input signal. Parallel compensation may be applied, for example, by analog continuous-time first-order derivative-filter equalization and/or by analog continuous-time second-order derivative filter equalization.

Method 700 begins at step 710. Steps 710-770 may be the same as steps 510-570 in method 500 described above and thus will not be described in detail again. It should be noted, however, that in steps 710-770, the first independent parameter may be controlled for a first path. For example, steps 710-770 may be used to adjust the gain applied to an unmodified portion of an input signal in a first path (such as path 101A of equalizer 42). In particular embodiments, increasing equalizer compensation in the first path may be implemented by decreasing the gain applied to an unmodified portion of an input signal in a first path, and decreasing equalizer compensation in the first path may be implemented by increasing the gain applied to an unmodified portion of an input signal in a first path. This is because the amount of equalizer compensation may depend on the relative gain of the second and third paths to the first path, and thus, increasing the gain of the first path will effectively decrease the relative gain of the second and third paths to the first path. In steps 780-850, the second and third independent parameters may be controlled for a second path and third path, respectively. For example, steps 780-850 may be used to adjust the gain applied to a portion of the input signal modified to be the first-order derivative of the input signal in a second path (such as path 101B of equalizer 42) and to adjust the gain applied to a portion of the input signal modified to be the second-order derivative of the input signal in a third path (such as path 101C of equalizer 42).

At steps 780 and 790, if the boundary value between the data values that comprise the transition and the data value 1.5 bits before the boundary value have a different value (high or low), a determination is made whether the value (high or low) of the data value 1.5 bits before the boundary value is the same as or opposite of the value of the data value 2.5 bits before the boundary value. This determination may be made, for example, by performing a suitable operation or by comparing the received data values and boundary values to pre-defined value patterns (that correspond to particular adaptive control actions). If the two values are different (opposite), method 700 proceeds to step 800, and the gain applied to the second-order derivative component of the input signal in the third path is decreased. If the two values are the same, method 700 proceeds to step 810, and the gain applied to the first-order derivative component of the input signal in the second path is decreased.

At steps 820 and 830, if the boundary value between the data values that comprise the transition and the data value 1.5 bits before the boundary value have the same value (high or low), a determination is made whether the value (high or low) of the data value 1.5 bits before the boundary value is the same as or opposite of the value of the data value 2.5 bits before the boundary value. Again, this determination may be made, for example, by performing a suitable operation or by comparing the received data values and boundary values to pre-defined value patterns (that correspond to particular adaptive control actions). If the two values are different (opposite), method 700 proceeds to step 840, and the gain applied to the second-order derivative component in the third path is increased. If the two values are the same, method 700 proceeds to step 850, and the gain applied to the first-order derivative component in the second path is increased.

It should be noted that, as described above in method 700, the number of independent control parameters may be the same as the number of adjusted parameters in particular embodiments. In alternative embodiments, the number of independent control parameters may be less than the number of adjusted parameters. For example, in an analog 2nd-order derivative equalizer, there may be two independent control parameters (i.e., a first gain applied to the first-order derivative component of the input signal and a second gain applied to the second-order derivative component of the input signal), and there may be three adjusted parameters (i.e., a third, fixed gain applied to the unmodified component of the input signal). As another example, a first independent control variable may control the relationship between the gain applied to the unmodified component and the gain applied to the first-order derivative component, and a second control variable may control the relationship between the gain applied to the second-order derivative component and the greater of the gain applied to the unmodified component and the gain applied to the first-order derivative component. Method 700 may be modified, as appropriate, to satisfy these different situations.

FIG. 8 is a table 900 illustrating an example gain control scheme associated with the method 700 of FIG. 7. Each row 902 corresponds to a particular pattern of values for which a particular adaptive equalizer control action is performed. Column 910 includes patterns of sampled data and boundary values, where a value may have a high (“1”) or a low (“0”) value. Column “D0” includes a zeroeth sampled data value of an output signal, column “D1” includes a first sampled data value of the output signal, column “D2” includes a second sampled data value of the output signal, column “D3” includes a third sampled data value of the output signal, and column “E2” includes the boundary value between the second and third data values. These values are similar to those illustrated in FIGS. 4A-4C. As can be observed, a transition occurs between data values in columns “D2” and “D3” in each pattern.

It should be noted that the values in each row 902 may be sampled by sampler 104 and sent to adaptive controller 102. Adaptive controller 102 may compare the sampled values to one or more pre-determined patterns of values. In particular embodiments, upon detecting a match, adaptive controller 102 may take an associated set of one or more adaptive equalizer actions. In such embodiments, particular relationships among the values may already be known (e.g., because a pre-determined pattern of values is being used), and thus one or more of the steps described above in method 700 need not be performed (e.g., steps 780, 790, 820, and 830).

It should further be noted that in particular embodiments, adaptive controller 102 may receive a greater number of values than that illustrated, including, for example, the boundary value between data values in columns “D0” and “D1” and the boundary value between data values in columns “D1” and “D2.” Alternatively, as discussed above, adaptive controller 102 may receive only sampled data values and other phase information, and particular boundary values (including, for example, boundary values in column E2) may be derived from the data values and other phase information (and may not be sampled by sampler 104).

Column 920 includes alternative boundary values at column “E2” for each row 902. Column 924 includes, for particular patterns, particular compensation levels and adaptive equalizer actions associated with the unmodified component of the input signal. The adaptive equalizer actions may be applied as discussed above in method 700. Column 930 includes, for particular patterns, particular compensation levels and adaptive equalizer actions associated with the first-order derivative component of the input signal. These adaptive equalizer actions may also be applied as discussed above in method 700. Column 940 includes, for particular patterns, particular compensation levels and adaptive equalizer actions associated with the second-order derivative component of the input signal. These adaptive equalizer actions may also be applied as discussed above in method 700.

FIG. 9 is a flowchart illustrating an example method 1000 for interpreting output signal values for multiple equalizer parameters in a 3-tap FIR filter according to a particular embodiment of the invention. Method 1000 begins at step 1010. Steps 1010-1030 may be similar to steps 510-530 in method 500 described above and thus will not be described again in detail. In particular embodiments, the first tap coefficient may be fixed and not adjusted by the adaptive control. Steps 1080-1170 may adjust the second and third tap coefficients. It should be noted that, in a 3-tap FIR filter, the second and third tap coefficients may be adjusted independently, as described further below, and each of these adjustments may comprise an adjustment to compensation for distortion. In general, whether in the context of the 3-tap FIR filter equalizer, the analog derivative filter equalizer, or any other suitable equalizer, even if each path performs only part of the compensation and the compensation occurs only in the aggregate when the outputs from all the paths are combined together, the action performed on each path may be referred to as an application of or adjustment to compensation for distortion.

At steps 1080 and 1090, a determination is made whether the value (high or low) of the data value 1.5 bits before the boundary value that is between the data values that comprise the transition is the same as or opposite of the value of the data value 2.5 bits before the boundary value. This determination may be made, for example, by performing a suitable operation or by comparing the received data values and boundary values to pre-defined value patterns (that correspond to particular adaptive control actions). If the two values are different (opposite), method 1000 proceeds to step 1100. If the two values are the same, method 1000 proceeds to step 1140.

At steps 1100 and 1110, a determination is made whether the value (high or low) of the data value 2.5 bits before the boundary value that is between the data values that comprise the transition is the same as or opposite of the value of the boundary value. This determination may be made, for example, by performing a suitable operation or by comparing the received data values and boundary values to pre-defined value patterns (that correspond to particular adaptive control actions). If the two values are different (opposite), method 1000 proceeds to step 1120, and the third tap coefficient is increased. If the two values are the same, method 1000 proceeds to step 1130, and the third tap coefficient is decreased.

At steps 1140 and 1150, a determination is made whether the value (high or low) of the data value 2.5 bits before the boundary value that is between the data values that comprise the transition is the same as or opposite of the value of the boundary value. Again, this determination may be made, for example, by performing a suitable operation or by comparing the received data values and boundary values to pre-defined value patterns (that correspond to particular adaptive control actions). If the two values are different (opposite), method 1000 proceeds to step 1160, and the second and third tap coefficients are increased. If the two values are the same, method 1000 proceeds to step 1170, and the second and third tap coefficients are decreased.

FIG. 10 is a table 1200 illustrating an example gain control scheme associated with the method of FIG. 9. Each row 1202 corresponds to a particular pattern of values for which a particular adaptive equalizer control action is performed. Column 1210 includes patterns of sampled data and boundary values, where a value may be a high (“1”) or a low (“0”) value. Column “D0” includes a zeroeth sampled data value of an output signal, column “D1” includes a first sampled data value of the output signal, column “D2” includes a second sampled data value of the output signal, column “D3” includes a third sampled data value of the output signal, and column “E2” includes the boundary value between the second and third data values. These values are similar to those illustrated in FIGS. 4A-4C. As can be observed, a transition occurs between data values in columns “D2” and “D3” in each pattern.

It should be noted that the pattern of values in each row 1202 may be sampled by sampler 104 and sent to adaptive controller 102. Adaptive controller 102 may compare the sampled values to one or more predetermined patterns of values. In particular embodiments, upon detecting a match, adaptive controller 102 may take an associated set of one or more adaptive equalizer actions. In such embodiments, particular relationships among the values may already be known (e.g., because a pre-determined pattern of values is being used), and thus one or more of the steps described above in method 1000 need not be performed (e.g., step 1080).

It should further be noted that in particular embodiments, adaptive controller 102 may receive a greater number of values than that illustrated, including, for example, the boundary value between data values in columns “D0” and “D1” and the boundary value between data values in columns “D1” and “D2.” Alternatively, as discussed above, adaptive controller 102 may receive only sampled data values and other phase information, and particular boundary values (including, for example, boundary values in column E2) may be derived from data values and other phase information (and may not be sampled by sampler 104).

Column 1220 includes alternative boundary values at column “E2” for each row 1202. Column 1230 includes, for particular patterns, particular coefficient levels and adaptive equalizer actions associated with the second tap coefficient. These adaptive equalizer actions may also be applied as discussed above in method 1000. Column 1240 includes, for particular patterns, particular coefficient levels and adaptive equalizer actions associated with the third tap coefficient. These adaptive equalizer actions may also be applied as discussed above in method 1000.

As discussed above in conjunction with FIG. 5, the relationship between a boundary value between successive data values comprising a transition and the data value 1.5 bits before the boundary value may correlate to particular equalization levels of a signal. The correlation may be particularly accurate for a signal having well-randomized data sequences. However, if a signal has periodic or quasi-periodic data sequences, the correlation may be affected by the periodicity of the sequences. In particular, the correlation may be even more heavily affected by the periodicity of the sequences, if the incoming signal or the clock signal has duty cycle distortion.

In general, the periodic or quasi-periodic data sequence has strong correlation between data values such as adjacent data values, and affects the frequency spectrum of the signal. For instance, if adjacent data values are more likely the same value than different values, the signal is low-frequency oriented, and if adjacent data values are more likely different values than the same value, the signal is high-frequency oriented. Such distortion in the frequency spectrum of the signal may affect an adaptive equalizer's ability to make the spectrum of the signal flat. In general, the periodic or quasi-periodic data sequences have such negative effect on an equalizer's adaptive gain control, even if there is no duty cycle distortion.

Duty cycle distortion may emphasize such negative effect of periodic and quasi-periodic sequences on an equalizer's adaptive gain control. For example, suppose an incoming data may be labeled as even data and odd data in turn. Boundary between data may also be labeled as even boundary and odd boundary in turn. Here, even boundary may refer to boundary after even data and before odd data, and odd boundary may refer to boundary after odd data and before even data. The duty cycle distortion may cause the receiver logic's even and odd boundary values heavily biased to “early” phase (i.e., same as the previous data value) or “late” phase (i.e., same as the next data value). For instance, even boundary value may be biased to “early” phase, and odd boundary value may be biased to “late” phase.

If the period of periodic or quasi-periodic data sequence is a multiple of two data values, the number of transitions at even boundary and the number of transitions at odd boundary may be biased as well. For instance, transitions may occur more frequently at even boundary than odd boundary in a periodic or quasi-periodic data sequence. The equalizer control may be affected by how the boundary value is biased (i.e., whether “early” phase or “late” phase) due to duty-cycle distortion at the even or odd boundary which dominates transitions in the periodic or quasi-periodic data sequence. Such effect may not be deterministic until the recovered clock locks to the incoming periodic or quasi-periodic incoming data sequence, because the correspondence between the bias of boundary values having “early or late” phase due to duty-cycle distortion and the bias of boundary having “dominant or non-dominant” transition due to periodic or quasi-periodic data sequence may depend on how the recovered clock with duty-cycle distortion locks to the incoming periodic or quasi-periodic data sequence.

Due to such bias of boundary value, either “early” phase or “late” phase, at the “even” or “odd” boundary which dominates transitions in the periodic or quasi-periodic data sequence, equalizer control actions may also be biased. An unbalanced bias toward a particular equalizer control action may produce an unacceptable result in the equalizer control.

FIG. 11 illustrates example boundary information 1300 affected by duty-cycle distortion. A signal 1310 is received at the receiver logic and sampled using a four-phase half-rate clock with duty-cycle distortion. Even data values may be sampled at rising edges of clock A (CLKA) 1320, odd data values may be sampled at rising edges of clock C (CLKC) 1340, even boundary values may be sampled at rising edges of clock B (CLKB) 1330, and odd boundary values may be sampled at rising edges of clock D (CLKD) 1350. In the example, the duty cycle of clock B 1330 is more than 50%, and the duty cycle of clock D 1350 is less than 50%. As a result, the even boundary values sampled at the rising edge of clock B 1330 are heavily biased to an “early” phase, and the odd boundary values sampled at the rising edge of clock D 1350 are heavily biased to a “late” phase. The clock recovery loop can lock in this phase position if it takes the average of “early” counts and “late” counts. If the incoming periodic or quasi-periodic signal has biased transitions between even and odd boundary, biased phase at the boundary that dominates transitions will bias the adaptive control actions. For example, if even boundary being sampled at rising edges of clock B (CLKB) 1330 has more transitions than odd boundary being sampled at rising edges of clock D (CLKD) 1350, the adaptive control actions are biased to “early” phase at the even boundary. If these biases are not accounted for in the adaptive gain controller of the equalizer, the result of the equalizer's adaptive operation may be affected.

One way of accounting for opposite biases in even and odd boundary values is by balancing the biases. This balance may be achieved by applying adaptive equalizer actions only when the controller detects particular data patterns that are distributed substantially equally (having substantially equal probabilities of occurrence) in the two phases. These particular data patterns (which may be referred to as filter patterns) may be used to balance biases arising in (quasi-) periodic data sequences and may also be used, without a problem, with well-randomized data sequences. In this way, the characteristics of the adaptive equalizer control may be made consistent for (quasi-) periodic data sequences and well-randomized data sequences. If more than one independent control parameter exists, the adaptive equalizer control may use particular filter patterns to control the gain applied to each particular independent control parameter. In particular embodiments, the filter patterns used to control the gain applied to a particular control parameter may be selected from the set of substantially equally occurring patterns and according to the partial gradient of the equalized-channel impulse response for the parameter, as discussed above in conjunction with FIGS. 7-10.

FIG. 12 is a flowchart illustrating an example method 1400 for selecting a filter pattern to reduce the negative effect of duty-cycle distortion according to a particular embodiment of the invention. Method 1400 may be used to select filter patterns for use with periodic or quasi-periodic data sequences such as, for example, the 8B10B idle sequences and the 8B10B CJPAT test sequences defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3ae standard.

Method 1400 begins at step 1410 where a set of even and odd data sequences are monitored. The set of even data sequences comprise data sequences that start from even data (i.e., at even phase), and then are followed by odd data, even data, odd data, and so on. The set of odd data sequences comprises data sequences that start from odd data (i.e., at odd phase), and then are followed by even data, odd data, even data, and so on. At step 1420, the distribution of data patterns in the even and odd data sequences is determined. In particular embodiments, the data patterns may include six bits. In alternative embodiments, the data patterns may include five bits. In yet alternative embodiments, the data patterns may include any other suitable number of bits. At steps 1430 and 1440, only those patterns that are observed in both the even and odd data sequences are further analyzed. Those patterns that are not observed in both sequences are not selected as filter patterns at step 1500.

At steps 1450 and 1460, for those patterns that are observed in the data pattern distributions of both even and odd data sequences, a determination is made whether any of these patterns are equally (or substantially equally) distributed in both the even and odd data sequences. As discussed above, selecting substantially equally distributed data patterns as filter patterns may cancel the biases produced by duty-cycle distortion. For those patterns that are equally (or substantially equally) distributed, method 1400 proceed to step 1470. Any patterns that are not substantiall