1. Field of the Invention
The present invention relates to an access monitoring method and device for shared memory, and in particular to an access monitoring method and device for shared memory in a multi-processor system where a plurality of processors access a shared memory.
2. Description of the Related Art
Prior art examples [1] and [2] of an access monitoring technology for shared memory as mentioned above will now be described referring to FIGS. 11 and 12.
Prior Art Example [1] (Common Bus Type): FIG. 11
A multi-processor system 10 shown in FIG. 11 is composed of a shared memory board 100 on which a shared memory SM is mounted, processor boards 200 _ 1 - 200 — n (hereinafter, occasionally represented by a reference numeral 200 ) on which “n” units of processors 210 _ 1 - 210 — n (hereinafter, occasionally represented by a reference numeral 210 ) connected to the shared memory board 100 through a common bus CB and “n” units of cache memories CM 1 -CMn (hereinafter, occasionally represented by a reference character CM) are respectively mounted, and a bus arbitration device 300 connected to the common bus CB to arbitrate accesses to the shared memory SM from the processors 210 _ 1 - 210 — n, which is generally called a common bus type multi-processor system.
In the multi-processor system 10 , when an arbitrary processor, e.g. the processor 210 _ 1 performs data read or write (access) to the shared memory SM as shown by the dotted lines in FIG. 11, the other processors 210 _ 2 - 210 — n respectively monitor (snoop) through the common bus CB access information (namely, information indicating whether or not the arbitrary processor is accessing the shared memory SM) as well as the date read or written, so that the access information and the data read or written are reflected in the cache memories CM 2 -CMn as shown by the dashed-dotted lines in FIG. 11.
Thus, each processor 210 can acquire the latest data of the shared memory SM by having only to access the cache memory CM within its own processor board 200 , thereby reducing a processing time required for accessing the shared memory SM.
However, the common bus type multi-processor system has problems described in the following (1)-(4):
In order to address these problems, the following prior art example [2] has already been proposed:
Prior Art Example [2[ (Star Type): FIG. 12
In a multi-processor system 10 shown in FIG. 10, the processor boards 200 _ 1 - 200 — n are respectively connected to the shared memory board 100 one-on-one with “n” sets of serial buses SB, different from the arrangement described in the above-mentioned prior art example [1]. This system is generally called a star type multi-processor system.
Also, in place of the bus arbitration device 300 described in the above-mentioned prior art example [1], the processor boards 200 _ 1 - 200 — n and the shared memory board 100 respectively have bus interfaces 220 _ 1 - 220 — n and 110 controlling the access to the shared memory SM. The bus interfaces 220 _ 1 - 220 — n and 110 are mutually connected, so that the processors 210 _ 1 - 210 — n and the cache memories CM 1 -CMn are connected to the shared memory SM through processor buses PB 1 -PBn, as well as the bus interfaces 220 _ 1 - 220 — n and 110 .
In the multi-processor system 10 , each of the processors 210 _ 1 - 210 n can respectively access the shared memory SM in parallel, so that the data write in the shared memory SM can be performed at an arbitrary timing, and only necessary data can be read from the shared memory SM to be stored in the cache memory CM (see e.g. patent documents 1-3).
In a star type multi-processor system like the above-mentioned prior art example [2], while the processors can access the shared memory in parallel, there has been a problem that monitoring the access information to the shared memory of the other processors, which is an advantage of a common bus type multi-processor system like the above-mentioned prior art example [1], can not be performed.
In this case, a delay may occur by having other processors which request an access without recognizing the access to the shared memory by a certain processor wait for the access to the shared memory. Also, a transaction load due to concurrent requests of access to the shared memory from the processors may degrade the throughput of the whole system.
It is accordingly an object of the present invention to provide an access monitoring method and device for shared memory which can monitor access information to a shared memory from an arbitrary processor regardless of the type of a multi-processor system.
Namely, on a receiving side (shared memory side) of a request packet, at the second step (or means), when an acquisition request of an access right to a shared memory is set in the request packet having received at the first step (or means), an identifier of a request source processor set in the request packet is set in the shared memory, thereby having the request source processor acquire the access right to the shared memory.
At the third step (or means), an answer packet indicating the acquisition of the access right is generated and broadcast to all of the processors.
The request packet has only to be transmitted only between the request source processor and the shared memory. Also, the answer packet can be transmitted common to each processor. Therefore, in the star type multi-processor system described in the prior art example [2] as well as the common bus type multi-processor system described in the above-mentioned prior art example [1], it is possible to inform other processors other than the request source processor that any one of the processors has accessed the shared memory.
Also, when a release request of the access right is set in the request packet, the second step (or means) resets the identifier of the request source processor in the shared memory, thereby releasing the access right having been acquired by the request source processor.
At the third step (or means), an answer packet indicating the release of the access right is generated and broadcast to all of the processors.
Thus, it is possible to have the other processors recognize that none of the processors has accessed the shared memory so that all of the processors can access the shared memory.
Namely, it is possible to simply control the acquisition and the release of the access right by dividing the shared memory into a data area and an exclusive control information area.
Also, the fifth means updates a access right display bit to a release status only when an identifier of a processor set in an identifier display bit coincides with the identifier of the request source processor, so that the other processors other than the request source processor can not intentionally release the access right.
Namely, even when the shared memory is divided so as to be effectively used, it is possible to acquire or release the access right of the arbitrary processor per data block, so that it is possible to have each processor monitor access information per data block.
Namely, each data block is divided per a single address, so that it is possible to uniquely specify data which should be read when the processor acquires the access right. Therefore, the answer packet in which the read data is set can be transmitted to the processor.
Thus, the processor having acquired the access right can acquire desired data without performing the data read, so that it is possible to reduce a transaction load according to the access to the shared memory.
Namely, on a transmitting side (processor side) of the request packet, at the first step (or means), the answer packet described in the above-mentioned [1] is received from the shared memory. It is to be noted that the answer packet is received in both cases where the processor itself has transmitted the request packet to the shared memory (namely, the processor itself is the request source processor), and when the request packet has been transmitted from another processor.
Thus, at the second step (or means), it can be recognized without access to the shared memory that any one of the processors has accessed the shared memory or that none of the processors has accessed the shared memory.
Namely, even when various divisions are performed to the shared memory as the above-mentioned [6] and [7], each of the processors respectively and sequentially records the acquisition or release of the access right in a cache memory including an area identical to the exclusive control information area in the shared memory, thereby enabling the identical and latest access information to be constantly shared. Therefore, it is possible to prevent the processor from unnecessarily waiting for the access to the shared memory upon the request thereof and a plurality of processors from concurrently requesting the access.
Thus, when the identifier of the request source processor is included in the answer packet, each processor records the identifier of the processor which acquires or releases the access right in the cache memory. Therefore, even when a certain processor in which a failure has occurred keeps the access right acquired, it is possible to easily specify the processor in which the failure has occurred by referring to the cache memory, and to rapidly perform recovery operations.
According to the present invention, particularly in the star type multi-processor system, it is possible to monitor the access information to the shared memory from the arbitrary processor, thereby enabling the processing time required for accessing the shared memory to be reduced, and enabling throughputs of each processor and the whole system to be upgraded.
Since it is made possible to simply perform monitoring of the access information to the shared memory and control of the access right, the present invention can be easily applied to the existing system.
The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which the reference numerals refer to like parts throughout and in which:
FIG. 1 is a block diagram showing an arrangement of a multi-processor system to which an access monitoring method and device for shared memory according to the present invention are applied;
FIGS. 2A and 2B are block diagrams showing an arrangement (1) of a shared memory and a cache memory used for the present invention;
FIG. 3 is a sequence diagram showing an access right acquisition operation example (1) of the present invention;
FIGS. 4A and 4B are diagrams showing a format example of a request packet used for the present invention;
FIGS. 5A and 5B are diagrams showing a format example of an answer packet used for the present invention;
FIG. 6 is a sequence diagram showing an access right release operation example of the present invention;
FIG. 7 is a sequence diagram showing a data read operation example of the present invention;
FIG. 8 is a sequence diagram showing a data write operation example of the present invention;
FIG. 9 is a block diagram showing an arrangement (2) of a shared memory used for the present invention;
FIG. 10 is a sequence diagram showing an access right acquisition operation example (2) of the present invention;
FIG. 11 is a block diagram showing a prior art example [1] of a multi-processor system; and
FIG. 12 is a block diagram showing a prior art example [2] of a multi-processor system.
Embodiment of the access monitoring method for shared memory and the device using the method according to the present invention will now be described referring to FIGS. 1, 2A, 2 B, 3 , 4 A, 4 B, 5 A, 5 B, and 6 - 10 in the following order:
A multi-processor system 10 shown in FIG. 1 is a system where the access monitoring method and device for shared memory according to the present invention are applied to the prior art star type multi-processor system shown in FIG. 12.
In the multi-processor system 10 , the bus interface 110 within the shared memory board 100 has, in addition to the arrangement shown in FIG. 12, a packet receiver/processor 111 receiving a request packet which requests an acquisition or a release of an access right to the shared memory SM from an arbitrary request source processor among the processors 210 _ 1 - 210 — n, acquiring or releasing the access right of the request source processor, and producing generation instructions of an answer packet indicating the acquisition or release of the access right, and a answer packet generator 112 generating the answer packet upon receiving the answer packet generation instructions and broadcasting the answer packet to all of the processors 210 _ 1 - 210 — n.
Also, the bus interface 220 _ 1 - 220 — n within the processor boards 200 _ 1 - 200 — n respectively have request packet generators 221 _ 1 - 221 — n (hereinafter, occasionally represented by a reference numeral 221 ) generating the request packet to be transmitted to the shared memory board 100 side, and packet determining portions 222 _ 1 - 222 — n (hereinafter, occasionally represented by a reference numeral 222 ) receiving the answer packet to be determined.
It is to be noted that while the bus interface 110 is configured by being divided into the packet receiver/processor 111 and the answer packet generator 112 , both of them may be configured as a single function block. In this case, the following description can be similarly applied.
I.2. Arrangement (1) of Shared Memory and Cache Memory: FIGS. 2A and 2B
The shared memory SM is divided, as shown in FIG. 2A, into a data area AR 1 storing data read or written by the processor 210 and an area AR 2 of exclusive control information to the data area AR 1 . The data area AR 1 is divided per range of addresses “0”-“x” and has “m+1” units of data blocks D 0 -Dm whose addresses are “B0-0”-“B0-x”, “B1-0”-“B1-x”, “B2-0”-“B2-x”, . . . , and “Bm-0”-“Bm-x”. In the exclusive control information area AR 2 , exclusive control information I 0 -Im whose addresses are A 0 , A 1 , A 2 , . . . , and Am are provided respectively corresponding to the data blocks D 0 -Dm.
Also, the exclusive control information includes an access right display bit b 1 indicating a status of an acquisition “1” (acquisition completion) or a release “0” (release completion) of the access right to corresponding data block, and a display bit b 2 displaying an ID (identifier) of a processor having acquired the access right.
Also, the cache memory CM includes, as shown in FIG. 2B, an area identical to the exclusive control information area AR 2 of the shared memory SM.
II. Operation Example: FIGS. 3, 4A, 4 B, 5 A, 5 B, and 6 - 10
Hereinafter, an operation of the multi-processor system 10 shown in FIG. 1 will be described. Firstly, an operation example (1) where the shared memory SM and the cache memory CM have the same arrangement as shown in FIGS. 2A and 2B will be described referring to FIGS. 3, 4A, 4 B, 5 A, 5 B, and 6 - 8 . Then, an operation example (2) where the arrangement of the shared memory SM has an arrangement (FIG. 9) different from FIG. 2A will be described referring to FIGS. 9 and 10.
II.1. Operation Example (1): FIGS. 3, 4A, 4 B, 5 A, 5 B, and 6 - 8
Hereinafter, the operation of the multi-processor system 10 will be described in the order of an access right acquisition operation example, an access right release operation example, a data read operation example, and a data write operation example.
Also, in the following operation examples, a case where the processor 210 _ 1 among the processors 210 _ 1 - 210 — n accesses e.g. the data block D 2 in the shared memory SM shown in FIG. 2A will be described.
It is to be noted that the following description is similarly applied to cases where other processors 210 _ 2 - 210 — n other than the processor 210 _ 1 access the shared memory and where the data blocks D 1 , and D 3 -Dm other than the data block D 2 are accessed.
II.1.A. Access Right Acquisition Operation Example (1): FIGS. 3, 4A, 4 B, 5 A, and 5 B
Firstly, the processor 210 _ 1 which requests the access to the data block D 2 provides, as shown in FIG. 3, an access right acquisition request to the request packet generator 221 _ 1 forming the bus interface 220 _ 1 (at step S 1 ).
The request packet generator 221 _ 1 having received the access right acquisition request generates a request packet RP as described below (at step S 2 ).
Namely, the request packet generator 221 _ 1 sets an access right acquisition request RQ 1 shown in FIG. 4B, the address A 2 of the exclusive control information I 2 corresponding to the data block D 2 , and “210 — 1”, respectively to a request type RP 1 , address information RP 2 , and a request source processor ID RP 4 in the request packet RP shown in FIG. 4A.
It is to be noted that while nothing is set to data RP 3 in the request packet RP and the data RP 3 is empty except in the data write (namely, when a data write request RQ 4 is set to the request type RP 1 ), data is set to the data RP 3 in the data write operation example as will be described later.
The request packet generator 221 _ 1 transmits the request packet RP generated to the bus interface 110 within the shared memory board 100 (at step S 3 ).
The packet receiver/processor 111 forming the interface 110 and having received the request packet RP extracts the request type RP 1 from the request packet RP for the determination (at step S 4 ). As a result, when determining that the access right acquisition request RQ 1 is set in the request type RP 1 , the packet receiver/processor 111 refers to the access right display bit b 1 in the exclusive control information I 2 designated by the address A 2 set in the address information RP 2 (at step S 5 ).
The packet receiver/processor 111 determines whether or not the access right display bit b 1 indicates the access right release status “0” (at step S 6 ). As a result, when determining that the access right display bit b 1 indicates the access right release status “0”, the packet receiver/processor 111 updates the access right display bit b 1 to the access right acquisition status “1”, and sets the processor ID display bit b 2 with “210 — 1” (at step S 7 ).
Thus, the packet receiver/processor 111 can have the processor 210 _ 1 acquire the access right to the data block D 2 .
The packet receiver/processor 111 provides generation instructions of an answer packet AP indicating the acquisition of the access right to the data block D 2 by the processor 210 _ 1 to the answer packet generator 112 (at step S 8 ). The answer packet generator 112 having received the instructions generates the answer packet AP as described below (at step S 9 ).
Namely, the answer packet generator 112 sets an access right acquisition ACK 1 shown in FIG. 5B, the address A 2 , and “210 — 1”, respectively to a response type AP 1 , address information AP 2 , and a request source processor ID AP 4 in the answer packet AP shown in FIG. 5A.
It is to be noted that while nothing is set to data AP 3 in the answer packet AP and the data AP 3 is empty except in the data read (namely, when a data read ACK 3 is set to the response type AP 1 ), data is set to the data AP 3 in the data read operation example and the operation example (2) as will be described later.
The answer packet generator 112 broadcasts the answer packet AP generated to the bus interfaces 220 _ 1 - 220 — n within all of the processor boards 200 _ 1 - 200 — n (at step S 10 ).
The packet determining portions 222 _ 1 - 222 — n forming the bus interfaces 220 _ 1 - 220 — n and having received the answer packet AP broadcast respectively extract the response type AP 1 from the answer packet AP for the determination (at steps S 11 _ 1 -S 11 — n ). As a result, when determining that the access right acquisition ACK 1 is set in the response type AP 1 , the packet determining portions 222 _ 1 - 222 — n update to the access right acquisition status “1” the access right display bit b 1 of the exclusive control information I 2 in the cache memories CM 1 -CMn designated by the address A 2 set in the address information AP 2 , and set the processor ID display bit b 2 with “210 — 1” set in the request source processor ID AP 4 (at steps S 12 _ 1 -S 12 — n ).
Each of the packet determining portions 222 _ 1 - 222 — n determines whether or not the processor ID set in the request source processor ID AP 4 coincides with its own processor ID. In this example, only the packet determining portion 222 _ 1 determines that both processor IDs are coincident, and transfers the answer packet AP to the processor 210 _ 1 (at step S 13 ).
The processor 210 _ 1 having received the answer packet AP recognizes that the access right to the data block D 2 is acquired, and performs the data read or write as will be described later referring to FIG. 7 or 8 (at step S 41 or S 61 ).
II.1.B. Access Right Release Operation Example: FIG. 6
The processor 210 _ 1 having completed the data read or write provides, as shown in FIG. 6, an access right release request to the request packet generator 221 _ 1 in order to release the access right to the data block D 2 (at step S 21 ).
The request packet generator 221 _ 1 having received the request generates the request packet RP as described below (at step S 22 ).
Namely, the request packet generator 221 _ 1 sets an access right release request RQ 2 shown in FIG. 4B, the address A 2 of the exclusive control information 12 corresponding to the data block D 2 , and “210 — 1”, respectively to the request type RP 1 , the address information RP 2 , and the request source processor ID RP 4 in the request packet RP.
The request packet generator 221 _ 1 transmits the request packet RP generated to the packet receiver/processor 111 (at step S 23 ).
The packet receiver/processor 111 having received the request packet RP extracts the request type RP 1 from the request packet RP for the determination (at step S 24 ). As a result, when determining that the access right release request RQ 2 is set in the request type RP 1 , the packet receiver/processor 111 refers to the access right display bit b 1 and the processor ID display bit b 2 in the exclusive control information 12 designated by the address A 2 set in the address information RP 2 (at step S 25 ).
The packet receiver/processor 111 determines whether or not the access right display bit b 1 and the processor ID display bit b 2 respectively indicate the access right acquisition status “1” and “210 — 1” having been set in the request source processor ID RP 4 (at step S 26 ). As a result, when determining that the access right display bit b 1 and the processor ID display bit b 2 respectively indicate the access right acquisition status “1” and “210 — 1”, the packet receiver/processor 111 updates the access right display bit b 1 to the access right release status “0”, and deletes “210 — 1” having been set in the processor ID display bit b 2 (at step S 27 ).
Thus, the packet receiver/processor 111 can release the access right to the data block D 2 having been acquired by the processor 210 _ 1 . The packet receiver/processor 111 provides generation instructions of the answer packet AP indicating the release of the access right to the data block D 2 by the processor 210 _ 1 to the answer packet generator 112 (at step S 28 ).
The answer packet generator 112 having received the instructions generates the answer packet AP as described below (at step S 29 ). Namely, the answer packet generator 112 sets an access right release ACK 2 shown in FIG. 5B, the address A 2 , and “210 — 1”, respectively to the response type AP 1 , the address information AP 2 , and the request source processor ID AP 4 in the answer packet AP.
The answer packet generator 112 broadcasts the answer packet AP generated to all of the packet determining portions 222 _ 1 - 222 — n (at step S 30 ).
The packet determining portions 222 _ 1 - 222 — n having received the answer packet AP broadcast respectively extract the response type AP 1 from the answer packet AP for the determination (at steps S 31 _ 1 -S 31 — n ). As a result, when determining that the access right release ACK 2 is set in the response type AP 1 , the packet determining portions 222 _ 1 - 222 — n update to the access right release status “0” the access right display bit b 1 of the exclusive control information 12 in the cache memories CM 1 -CMn designated by the address A 2 set in the address information AP 2 , and delete “210 — 1” set in the processor ID display bit b 2 (at steps S 32 _ 1 -S 32 — n ).
It is to be noted that the processor 210 _ 1 having requested the release of the access right to the data block D 2 can directly update the cache memory CM 1 upon the request. However, when the cache memory CM 1 is directly updated, the content of the cache memory CM 1 may not coincide with the contents of the cache memories CM 2 _CMn within the other processors 210 _ 2 - 210 — n and the shared memory SM due to influences of loss or the like of the request packet RP or the answer packet AP due to a transmission failure of the serial bus SB. Therefore, the processor 210 _ 1 (packet determining portion 222 _ 1 ) updates the cache memory CM 1 after the determination of the above-mentioned step S 31 _ 1 .
II.1.C. Data Read Operation Example: FIG. 7
The processor 210 _ 1 having acquired the access right to the data block D 2 provides, as shown in FIG. 7, a data read request from a desired address in the data block D 2 , e.g. the address “B2-0” to the request packet generator 221 _ 1 (at step S 41 ).
The request packet generator 221 _ 1 having received the data read request generates the request packet RP as described below (at step S 42 ).
Namely, the request packet generator 221 _ 1 sets a data read request RQ 3 shown in FIG. 4B, the address “B2-0”, and “210 — 1”, respectively to the request type RP 1 , the address information RP 2 , and the request source processor ID RP 4 in the request packet RP.
The request packet generator 221 _ 1 transmits the request packet RP generated to the packet receiver/processor 111 (at step S 43 ).
The packet receiver/processor 111 having received the request packet RP extracts the request type RP 1 from the request packet RP for the determination (at step S 44 ). As a result, when determining that the data read request RQ 3 is set in the request type RP 1 , the packet receiver/processor 111 reads data “DT2-0” from an area designated by the address “B2-0” set in the address information RP 2 (at step S 45 ).
The packet receiver/processor 111 provides generation instructions of the answer packet AP set with the data “DT2-0” read to the answer packet generator 112 (at step S 46 ).
The answer packet generator 112 having received the instructions generates the answer packet AP as described below (at step S 47 ).
Namely, the answer packet generator 112 sets a data read ACK 3 shown in FIG. 5B, the address “B2-0”, the data “DT2-0”, and “210 — 1”, respectively to the response type AP 1 , the address information AP 2 , the data AP 3 , and the request source processor ID AP 4 in the answer packet AP.
The answer packet generator 112 transmits the answer packet AP generated only to the packet determining portion 222 _ 1 (at step S 48 ).
The packet determining portion 222 _ 1 having received the answer packet AP extracts the response type AP 1 from the answer packet AP for the determination (at step S 49 ). When determining that the data read ACK 3 is set in the response type AP 1 , the packet determining portion 222 _ 1 transfers the answer packet AP to the processor 210 _ 1 (at step S 50 ).
The processor 210 _ 1 having received the answer packet AP acquires the data “DT2-0” from the data AP 3 in the answer packet AP (at step S 51 ).
II.1.D. Data Write Operation Example: FIG. 8
The processor 210 _ 1 having acquired the access right to the data block D 2 provides, as shown in FIG. 8, a data write request of desired data DTy to a desired address in the data block D 2 , e.g. the address “B2-0” to the request packet generator 221 _ 1 (at step S 61 ).
The request packet generator 221 _ 1 having received the data write request generates the request packet RP as described below (at step S 62 ).
Namely, the request packet generator 221 _ 1 sets a data write request RQ 4 shown in FIG. 4B, the address “B2-0”, the data DTy, and “210 — 1”, respectively to the request type RP 1 , the address information RP 2 , the data RP 3 , and the request source processor ID RP 4 in the request packet RP.
The request packet generator 221 _ 1 transmits the request packet RP generated to the packet receiver/processor 111 (at step S 63 ).
The packet receiver/processor 111 having received the request packet RP extracts the request type RP 1 from the request packet RP for the determination (at step S 64 ). As a result, when determining that the data write request RQ 4 is set in the request type RP 1 , the packet receiver/processor 111 writes in an area designated by the address “B2-0” set in the address information RP 2 the data DTy set in the data RP 3 in the request packet RP (at step S 65 ).
It is to be noted that the answer packet AP is not transmitted/received between the shared memory board 100 and the processor board 200 upon the data read, and the processor 210 regards that the execution of the data write is completed when performing the data write request indicated at the above-mentioned step S 61 .
II.2. Operation Example (2): FIGS. 9 and 10
Hereinafter, an access right acquisition operation example of the multi-processor system 10 where the shared memory SM has an arrangement shown in FIG. 9 will be described referring to FIG. 10. It is to be noted that since the access right release operation example, the data read operation example, and the data write operation example are the same as those in the above-mentioned operation example (1), the description thereof will be omitted.
II.2.A. Arrangement (2) of Shared Memory: FIG. 9
A shared memory SM shown in FIG. 9 is different from the arrangement ( 1 ) of the shared memory shown in FIG. 2A in that the data blocks D 0 -Dm are respectively divided according to addresses B 0 , B 1 , B 2 , B 2 , . . . , and Bm.
Also, each of the exclusive control information I 0 -Im is provided, in the same way as the above-mentioned arrangement (1) of the shared memory, corresponding to each of the data blocks D 0 -Dm, and includes the access right display bit b 1 and the processor ID display bit b 2 .
II.2.B. Access Right Acquisition Operation Example (2): FIG. 10
The access right acquisition operation example shown in FIG. 10 is different from the access right acquisition operation example (1) shown in FIG. 3 only in processes of steps S 70 -S 73 .
Namely, at step S 7 , the packet receiver/processor 111 having had the processor 210 _ 1 acquire the access right to the data block D 2 reads data DT 2 from the data block D 2 corresponding to the exclusive control information I 2 designated by the address A 2 set in the address information RP 2 in the request packet RP (at step S 70 ).
The packet receiver/processor 111 provides instructions for setting the data DT 2 read with the acquisition of the access right to the answer packet AP to the answer packet generator 112 (at step S 71 ).
The answer packet generator 112 having received the instructions sets, in the same way as the above-mentioned access right acquisition operation example (1), to the response type AP 1 , the address information AP 2 , and the request source processor ID AP 4 in the answer packet AP the access right acquisition ACK 1 , the address A 2 , and “210 — 1” respectively, and sets the data DT 2 to the data AP 3 which is not used in the above-mentioned access right acquisition operation example (1) (at step S 72 ).
Thus, the answer packet in which the data DT 2 is set is to be broadcast to all of the packet determining portions 222 _ 1 - 222 — n.
At step S 13 , the processor 210 _ 1 to which the answer packet AP has been transferred acquires the data DT 2 from the data AP 3 in the answer packet AP (at step S 73 ).
Thus, the processor 210 _ 1 can acquire the data DT 2 stored in the data block D 2 without performing the data read request indicated at the step 41 of FIG. 7 by concurrently performing the access right acquisition and the data read. It is to be noted that when performing the data write in the data block D 2 , the processor 210 _ 1 has only to discard the data DT 2 acquired and to perform a write request of desired data in the same way as the step S 61 of FIG. 8.
It is to be noted that the present invention is not limited by the above-mentioned embodiments, and it is obvious that various modifications may be made by one skilled in the art based on the recitation of the claims.