OBLON, SPIVAK, MCCLELLAND MAIER & NEUSTADT, P.C. (1940 DUKE STREET, ALEXANDRIA, VA, 22314, US)
Claims:
1. A method of manufacturing a semiconductor memory device comprising: forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.
2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the trenches are provided in a matrix on a surface of a memory formation region in the semiconductor substrate.
3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the trenches are provided in a drain formation region of the memory element, not in a source formation region of the memory element.
4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the memory element includes a floating body in an electrically floating state, and the memory element is a floating body cell storing therein data according to number of majority carriers accumulated in the floating body.
5. The method of manufacturing a semiconductor memory device according to claim 1, wherein opening diameters of the trenches are respectively equal to distances between two adjacent trenches of the trenches.
6. The method of manufacturing a semiconductor memory device according to claim 1, wherein a depth of each of the trenches is twice as large as an opening diameter of each of the trenches.
7. The method of manufacturing a semiconductor memory device according to claim 1, wherein the heat treatment under the hydrogen atmosphere is performed at an atmospheric pressure of 300 Torr under the hydrogen atmosphere at 1100° C.
8. The method of manufacturing a semiconductor memory device according to claim 2, wherein the heat treatment under the hydrogen atmosphere is performed at an atmospheric pressure of 300 Torr under the hydrogen atmosphere at 1100° C.
9. The method of manufacturing a semiconductor memory device according to claim 3, wherein the heat treatment under the hydrogen atmosphere is performed at an atmospheric pressure of 300 Torr under the hydrogen atmosphere at 1100° C.
10. The method of manufacturing a semiconductor memory device according to claim 1 further comprising: forming an element isolation region by forming an insulating film on the electrode material in the isolation formation area.
11. A semiconductor memory device comprising: a semiconductor substrate; a source and a drain formed in a surface region of the semiconductor substrate; a support column provided below the source and intervening between the source and the semiconductor substrate; a floating body provided between the source and the drain and accumulating or releasing charges to store data; a gate insulating film provided on the floating body; a gate electrode provided on the gate insulating film; and a plate electrode provided below the drain and the floating body, and electrically isolated from the floating body and the semiconductor substrate, wherein the drain and the floating body are electrically isolated from the semiconductor substrate by the plate electrode.
12. The semiconductor memory device according to claim 11, wherein the support column includes a insulation material.
13. The semiconductor memory device according to claim 11, wherein the support column includes a conductive material.
14. The semiconductor memory device according to claim 11, wherein the support column electrically connects the source to the semiconductor substrate.
15. The semiconductor memory device according to claim 11 further comprising: a memory region in which memory cells respectively including the floating body are provided; and a logic region in which a logic circuit controlling the memory cell is provided, wherein a plurality of support columns are provided equidistantly in the memory region other than a boundary between the memory region and the logic region.