1. Field of the Invention
The present invention relates to a semiconductor memory device and a construction of a portion related to data reading for reading data accurately at high speed. Specifically, the present invention relates to a construction for achieving high-speed data reading in a non-volatile semiconductor memory device.
2. Description of Background Art
A non-volatile semiconductor memory device such as a flash memory is widely used in the field of portable equipments and the like as it can store data in a non-volatile manner. A memory cell structure of the non-volatile semiconductor memory device is roughly divided into a structure utilizing a stacked gate type transistor in which charges are stored in a conductive floating gate formed of polysilicon or the like, and insulating film trap type memory cell structure in which charges are stored in an insulation film such as a nitride film. In either memory cell structure, a threshold voltage of the memory cell transistor is set in accordance with the amount of trapped charges, and the data is stored in accordance with the magnitude of the threshold voltage.
Such a non-volatile semiconductor memory device is characterized in that it has smaller area of cell occupation per bit as compared with an SRAM (Static Random Access Memory) that typically requires six transistors per memory cell, and that a refresh operation for holding data required in a DRAM (dynamic Random Access Memory) is unnecessary. Storage of a large amount of data such as sound or image is required also for a non-volatile semiconductor memory device, and hence, increase in storage capacity thereof has been desired.
In such a non-volatile semiconductor memory device having large storage capacity, a construction is generally used in which the memory array is divided into a plurality of blocks, an X decoder and a Y decoder for selecting memory cells are arranged for each block, and memory cell selection is performed in a block basis. As only a selected block is operated, power consumption can be reduced. Further, the number of memory cells connected to a bit line can be reduced by such block division, and therefore, load of the bit line is reduced, achieving higher speed of accessing.
Such a construction of the non-volatile semiconductor memory device having large storage capacity is disclosed, for example, in “An Overview of Flash Architectural Developments”, PROCEEDINGS of the IEEE, Vol. 91, No. 4, April 2003, pp. 523-536.
As disclosed in the reference above, in a non-volatile semiconductor memory device, an address decode circuit (including a predecode circuit) is provided for each memory array block. An address signal applied in synchronization with an external clock signal is latched by an address latch circuit arranged commonly to the memory array blocks, predecoded and then, supplied to each address decode circuit.
In the non-volatile semiconductor memory device, a command designating an operation mode is supplied to an address input circuit through an address signal line. The address latch circuit is arranged on one end side of the memory array, in the vicinity of the address input circuit. Further, the predecode circuit is arranged on one end side of the memory array in the vicinity of the address latch circuit, in order to reduce the number of internal address signal lines and to reduce charging/discharging current of the internal address signal lines, and supplies a predecode signal to each address decode circuit. Therefore, when the memory array size increases as the storage capacity increases, the signal line transmitting the internal address signal from the address predecode circuit to each address decode circuit becomes longer to have an increased load. Consequently, the address predecode signal comes to have large skew, that is, difference in arrival time of address predecode signal becomes larger between the leading end and terminating end of the address predecode signal transmitting line. Accordingly, a margin for the timing of starting memory cell selection becomes smaller, making it difficult to guarantee accurate memory cell selecting operation. In order to ensure sufficient margin for the memory cell selecting operation and the data reading operation, it is necessary to set the timing of memory cell selection/data reading operation, taking into account the worst case of arrival of the address predecode signal to the address decode circuit, which makes it difficult to achieve a high-speed operation.
For accurate data reading, it is necessary to correct an erroneous bit if present. Provision of the error correction function (ECC function) improves efficiency in repairing a defective bit, and hence improves production yield. When the bit width of the internal read data increases to 64 bits or to 128 bits, the number of bits for error detection/correction must be increased for accurate error detection/correction.
When an error of the stored data is simply to be detected, an even/odd parity bit (s) is added, and typically, 1 bit of parity bit is added on the basis of 8-bit unit. In this case, whether there is an error or not can be detected, dependent on whether the least significant bit of the addition result value of the read out 8 bit data matches the parity bit or not. Parity check using even/odd parity bit (s) can detect an error while it cannot specify the bit that causes the error. Therefore, error correction is impossible. When an ECC code is used to realize the error detection/correction function, typically, an ECC code typically of 7 bits is added to the data of 64 bits. Here, information data and the ECC data must be read at the same speed, to perform error detection and correction. In the aforementioned reference, the manner how the data bit for error detection/correction is stored in the memory array and how the data bit and the ECC code bit are read substantially at the same speed to achieve high-speed reading are not at all considered.
In order to achieve high-speed data reading, it is necessary to initialize the internal circuitry at a timing as fast as possible, to be ready for the next reading cycle. Generally, a non-volatile semiconductor memory device operates in a static manner like an SRAM, for decoding an address and providing data output. In a large storage capacity memory, signal lines in the data reading path are of different length, propagation time of internal data differs dependent on the position of a selected memory cell, and hence the timing at which the data is made definite differs for each data bit in the data output circuit. Therefore, in this case also, in order to read data accurately, the data reading timing and the timing for initializing the data output path must be set considering the worst case. Therefore, the cycle time of data reading cannot be reduced, and it becomes difficult to achieve high-speed reading.
An object of the present invention is to provide a non-volatile semiconductor memory device capable of reading data accurately at high speed.
Another object of the present invention is to provide a semiconductor memory device having an enlarged operation margin for data reading.
According to a first aspect, the present invention provides a non-volatile semiconductor memory device including: a memory array having a plurality of memory cells, arranged in rows and columns, each storing data in a non-volatile manner; predecode circuitry arranged along one side of the memory array, for predecoding an address signal designating a memory cell of the memory array and generating a predecoded address signal; address latch circuitry arranged along one side of the memory array in correspondence with the predecode circuitry, for latching the predecoded address signal from the predecode circuitry; cell selecting circuitry responsive to address latched by the address latch circuitry, for selecting an addressed memory cell of the memory array, in accordance with the latched address signal from the address latch circuitry; and data reading circuitry for reading data of the memory cell selected by the cell selecting circuitry in a data reading mode of operation.
According to a second aspect, the present invention provides a semiconductor memory device including: a memory array having a plurality of memory cells arranged in rows and columns; address latch circuitry for latching an address signal designating a memory cell of the memory cell array; cell selecting circuitry for selecting an addressed memory cell of the memory array in accordance with the latched address signal of the address latch circuitry; and data reading circuitry for reading data of the memory cell selected by the cell selecting circuitry in a data reading mode of operation, for generating internal data. In the data reading mode of operation, the cell selecting circuitry resets the address latch circuitry to the initial state, after a memory cell is selected.
According to a third aspect, the present invention provides a semiconductor memory including a memory array divided into a plurality of memory mats. Each memory mat includes a plurality of memory cells and memory cell selection and data reading are performed in parallel in a data reading mode of operation. Each memory mat includes a data region for storing data bits, and an error correction bit region for storing parity bits forming error correction codes for the data.
A predecoded signal from the predecode circuitry is latched by the address latch circuitry and then, the latched address signal is transmitted from the address latch circuitry to the address decode circuit, for selecting a memory cell. The predecode circuitry and the address latch circuitry are arranged along one side of the memory array. Therefore, time difference of transmission of the latch address to the cell selecting circuitry can be reduced, and data reading margin can be enlarged.
Further, in the data reading cycle, after a memory cell is selected, the address latch circuitry is reset. Therefore, the direction of change of the latch address signal in the next reading cycle can be set always in one direction from the reset state (inactive state) to a state different from the reset state (active state), so that occurrence of multi-selection state can be prevented regardless of the designated address. Thus, the timing of address change can always be made substantially the same, and the reading timing can be made faster.
Further, as the parity bits for error correction are arranged dispersed over the memory mats, the size of the memory mats can be made the same, so that memory cell selecting lines can have substantially the same load, and data can be read from each memory mat at substantially the same timing. Further, in a nonvolatile semiconductor memory device, the number of memory cells connected to each source line can be made the same. Therefore, increase in source line potential at the time of data reading can be suppressed, and accordingly, the current that can be driven by the selected memory cell in each memory mat can be made uniform. Thus, accurate data reading at high Speed becomes possible.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
FIG. 1 schematically shows a construction of a main portion of a non-volatile semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 schematically shows a structure of a memory cell used in the non-volatile semiconductor memory device shown in FIG. 1.
FIG. 3 shows an exemplary construction of an address input circuit shown in FIG. 1.
FIG. 4 is a timing diagram representing timings of address latching and decoding operations of the non-volatile semiconductor memory device shown in FIG. 1.
FIG. 5 shows a specific construction of a memory block in accordance with a second embodiment of the present invention.
FIG. 6A schematically shows distribution of a source line current when ECC codes are arranged in a concentrated manner, and FIG. 6B schematically shows distribution of source current when ECC codes are stored in a dispersed manner, in accordance with the first embodiment of the present invention.
FIG. 7 schematically shows a construction of a portion related to one sense amplifier of a non-volatile semiconductor memory device in accordance with a third embodiment of the present invention.
FIG. 8 schematically shows constructions of a sense amplifier, a selector and a reference current supplying circuit shown in FIG. 7.
FIG. 9 is a timing diagram representing an operation of the circuits shown in FIGS. 7 and 8.
FIG. 10 schematically shows an operation of the circuit shown in FIG. 8 at the time of precharging.
FIG. 11 schematically shows circuit connection of the circuit shown in FIG. 8 at the time of a sensing operation.
FIG. 12 schematically shows a construction of a portion generating a precharge signal, shown in FIG. 8.
FIG. 13 schematically shows a construction of a memory mat in accordance with a fourth embodiment of the present invention.
FIG. 14 schematically shows a construction of a control gate block shown in FIG. 13.
FIG. 15 schematically shows a construction of a control gate group shown in FIG. 14.
FIG. 16 shows an example of a specific construction of an address latch circuit and an address decode circuit in accordance with the fourth embodiment of the present invention.
FIG. 17 more specifically shows the configuration of the X decoder shown in FIG. 16.
FIG. 18 is a timing diagram representing an operation of the circuit shown in FIG. 16.
FIG. 19 is a diagram of signal waveforms showing timings in a test operation of the circuit shown in FIG. 17.
FIG. 20 schematically shows a construction of a main portion of a non-volatile semiconductor memory device in accordance with a fifth embodiment of the present invention.
FIG. 21 is a timing diagram representing an operation of the circuit arrangement shown in FIG. 20.
FIG. 22 schematically shows a construction of an internal data transmitting portion of the non-volatile semiconductor memory device in accordance with the fifth embodiment of the present invention.
FIG. 23 shows an exemplary construction of a sense amplifier control circuit shown in FIG. 22.
FIG. 24 schematically shows a construction of an input signal generating portion shown in FIG. 23.
FIG. 25 is a diagram of signal waveforms representing an operation of the circuit shown in FIG. 24.
FIG. 26 schematically shows a construction of a precharge/sense control signal generating circuit shown in FIG. 23.
FIG. 27 shows an exemplary configuration of a delay circuit shown in FIG. 26.
FIG. 28 shows an example of a second delay circuit shown in FIG. 26.
FIG. 29 schematically shows an equivalent construction of the circuit shown in FIG. 26 in a normal reading mode.
FIG. 30 is a timing diagram representing an operation of the circuit shown in FIG. 29.
FIG. 31 shows an exemplary construction of a Y decoder in accordance with the fifth embodiment of the present invention.
FIG. 32 shows exemplary constructions of an output latch and an output buffer shown in FIG. 22.
FIG. 33 shows an exemplary construction of an output control circuit shown in FIG. 20.
FIG. 34 is a timing diagram representing an operation of the output control circuit shown in FIG. 33.
FIG. 35 schematically shows a construction of a sense amplifier band in the fifth embodiment of the present invention.
FIG. 36 schematically shows propagation paths of an internal read data and a monitor signal, in a sixth embodiment of the present invention.
FIG. 37 is a timing diagram representing an operation of the circuit shown in FIG. 36.
FIG. 38 schematically shows a construction of a main portion of the non-volatile semiconductor memory device in accordance with the sixth embodiment of the present invention.
FIG. 39 is a diagram of signal waveforms representing an operation of the non-volatile semiconductor memory device shown in FIG. 38.
FIG. 1 schematically shows a construction of a main portion of a non-volatile semiconductor memory device in accordance with the first embodiment of the present invention.
FIG. 1 shows only the construction of the portion related to data reading, and constructions of portions related to data writing (programming) and erasure are not shown.
Referring to FIG. 1, the non-volatile semiconductor memory device includes a memory array 1 having non-volatile memory cells arranged in rows and columns. Memory array 1 is divided into two memory blocks MBA and MBB. Memory blocks MBA and MBB each store information (data) bits and parity bits for forming ECC codes for error detection/correction of the information bits. The parity bits are stored dispersed uniformly in each of the memory blocks MBA and MBB.
The non-volatile semiconductor memory device further includes: an address input circuit 2 taking an external command CMD and an address signal ADD in accordance with a clock signal CLK; predecoders 3 A and 3 B provided corresponding to memory blocks MBA and MBB, respectively, for predecoding an internal address signal from address input circuit 2 ; address latch circuits 4 A and 4 B latching predecoded signals from predecoders 3 A and 3 B, respectively; and decode circuits 5 A and 5 B further decoding the latched predecoded signals from address latch circuits 4 A and 4 B, and generating selection signals for selecting memory cells in corresponding memory blocks MBA and MBB.
Address input circuit 2 is arranged on one end side (lower side) of the memory array, takes in an external address signal in synchronization with the clock signal CLK to generate an internal address signal, and transmits the internal address signal to predecoders 3 A and 3 B.
Predecoders 3 A and 3 B are activated when an address signal from address input circuit 2 designates the corresponding memory blocks, perform predecoding operation and generate predecoded signals, which in turn are transmitted to corresponding address latch circuits 4 A and 4 B. Therefore, in memory blocks MBA and MBB, memory cell selecting operation is performed alternatively in data reading.
Predecoders 3 A and 3 B are provided corresponding to memory blocks MBA and MBB, respectively. Interconnection lines from address input circuit 2 to predecoders 3 A and to 3 B have substantially the same length. The distance of interconnection is the same from predecoders 3 A and 3 B to address latch circuits 4 A and 4 B. Therefore, when the predecoded signal is transmitted from one end (lower side) of memory array 1 to the other end side (upper side) of memory array 1 , propagation delay of the predecoded signal can be suppressed, address skew can be suppressed, and hence reading at a faster timing becomes possible.
Further, the distance of interconnection for the address signals is the same from address latch circuits 4 A and 4 B to decode circuits 5 A and 5 B, respectively, so that the timing at which the address is made definite in memory blocks MBA and MBB can be made the same. Thus, a margin for the decoding operation can be enlarged, achieving stable and high-speed reading.
The non-volatile semiconductor memory device further includes: an output latch circuit 6 receiving data of a selected memory cell of memory block MBA or MBB through a read main bit line RMBL and generating an internal output data; an ECC circuit (error detection/correction circuit) 8 receiving the internal output data from output latch circuit 6 through a read data bus RDB, for performing error detection/correction of information bits based on parity bits; and a selector 9 selecting, from the information bits from ECC circuit 8 , data of the number of bits corresponding to the output data bit width, and generating an external read data Q.
By way of example, from memory block MBA or MBB, 64 information bits and 7 parity bits are read in parallel and applied to output latch circuit 6 . From 64 bits of data that have been subjected to error detection/correction by ECC circuit 8 , selector 9 selects 32 bits or 16 bits, to generate external read data Q.
The non-volatile semiconductor memory device further includes an output control circuit 7 that resets output latch circuit 6 , in accordance with the state of transfer of data read to read main bit line RMBL. The output control circuit 7 monitors the state of reading of the internal read data, and in accordance with the result of monitoring, resets the output latch circuit after the internal output data is reliably generated in accordance with the internal read data.
As the output control circuit 7 resets the output latch circuit 6 at a certain timing after the data is latched, even when the propagation time of the internal read data differs dependent on the position of the selected memories, the latched data of output latch circuit 6 is read after the data has been latched and read in the output latch circuit 6 . Therefore, the timing of read control can be made the same regardless of the positions of the selected memory cells in memory array 1 , and operation margin for data reading can be enlarged.
FIG. 2 shows an exemplary structure of the non-volatile memory cell included in memory array 1 shown in FIG. 1. Referring to FIG. 2, non-volatile memory cell MC includes impurity regions 10 b and 10 c formed spaced apart from each other on a surface of a substrate region 10 a, a control gate 10 e formed on substrate surface 10 a close to impurity region 10 b, with a gate insulating film 10 d interposed, and a memory gate 10 f formed on insulating film 10 g, close to impurity region 10 c. Insulating layer 10 g is formed extended between control gate 10 e and memory gate 10 f Insulating layer 10 g is formed, for example, of an ONO film (silicon Oxide-Nitride-Oxide film), and includes a charge trap layer 10 j formed, for example, of a silicon nitride film.
On a sidewall of memory gate 10 f, a sidewall insulating film 10 i reaching impurity region 10 c is formed. On a sidewall of control gate 10 e, a sidewall insulating film 10 k reaching impurity region 10 b is formed. A low resistance metal 10 h such as Cobalt Silicide film (CoSi film), for example, is formed on the control gate 10 e.
Impurity regions 10 b and 10 c function as drain and source, respectively, at the time of data reading, and impurity region 10 b is connected to a bit line BL and impurity region 10 c is connected to a source line SL. Control gate 10 e is connected to a control gate line CGL, and memory gate 10 f is connected to a word line WL. Low-resistance metal layer 10 h on control gate 10 e lowers resistance of control gate line CGL.
In non-volatile memory cell MC shown in FIG. 2, when charges are stored in charge trap layer 10 j (in writing operation), a voltage, for example, of 1.5V is applied to control gate line CGL, and a high voltage of, for example, 11V is applied to word line WL, so as to form a channel below control gate 10 e. Substrate region 10 a is held at the ground potential level. At the time of writing, a voltage, for example, of 5.5V is applied to source line SL, and a constant current source is connected to the drain through bit line BL. A current is caused to flow from source line SL to bit line BL, so that electric field is concentrated in substrate region 10 a between control gate 10 e and memory gate 10 f By the high electric field, hot carriers (electrons) are generated and the generated hot carriers are accelerated in accordance with the voltage applied to memory gate 10 f, and captured in charge trap layer 10 j (source side injection). By this writing operation, the threshold voltage of the memory cell is set to a voltage level higher than the memory gate voltage (for example, 1.5V) applied at the time of data reading.
In erasure, impurity region (drain) 10 b is set to an open state, control gate 10 e is set to the ground voltage level through control gate line CGL, and substrate region 10 a is kept at the ground voltage level. A negative voltage of, for example, −6V is applied to memory gate 10 f through word line WL, and a voltage of 5.5V, for example, is applied to impurity region (source) 10 c through source line SL. In this state, hot carriers (holes) generated by the high electric field below memory gate 10 f are injected to charge trap layer 10 j, attracted by the negative voltage of memory gate 10 f and combined to the trapped electrons, so that electrons stored in the charge trap layer 10 j are neutralized. By this erasing operation, the threshold voltage of the memory cell decreases to a voltage level lower than the memory gate voltage applied at the time of reading.
In data reading, a read voltage of 1.5V is applied to memory gate 10 f, and impurity region 10 c is kept at the ground voltage level. To impurity region 10 b, a read voltage of about 1.5V is supplied through bit line BL. To control gate 10 e, 1.5V is applied through control gate line CGL. Dependent on the amount of accumulated carriers in charge trap layer 10 j, memory cell MC assumes either a state in which the threshold voltage has large absolute value, or a state in which the threshold value has small absolute value, in the case when binary data is stored.
When control gate line CGL is driven to the selected state, a channel is formed below control gate 10 e. When electrons are trapped in charge trap layer 10 j and the threshold voltage is high (for the case of N channel transistor), an inversion layer is not formed below charge trap layer 10 j, and therefore, a current does not flow between impurity regions 10 b and 10 c. On the other hand, when the amount of electrons trapped in charge trap layer 10 j is small because of hole injection or when the amount of holes is large and the threshold voltage is low (for the case of N channel transistor), an inversion layer is formed below charge trap layer 10 j, and a current flows between impurity regions 10 b and 10 c. By sensing the amount of current flowing through bit line BL, the data stored in non-volatile memory cell MC is read.
The structure of non-volatile memory cell MC is not limited to the one shown in FIG. 2, and other memory cell structures may be used. Further, different methods may be employed for the method of writing/erasing data. By way of example, by discharging the electrons trapped in charge trap layer 10 j to substrate region 10 a or to memory gate 10 f, erasure may be performed.
Further, the erased state of the memory cell may be the state having high threshold voltage, and the written state may be the state of low threshold voltage.
In the memory cell structure, a memory transistor for storing data and a selection transistor for selecting the memory transistor are connected in series between the bit line and the source line. Therefore, even when the memory transistor enters an over-erased state and the threshold voltage attains negative, data reading of the selected memory cell is not affected by the over-erased cell, as long as the selection transistor is in a non-conductive state. Therefore, the step of adjusting threshold voltage to prevent the over-erased state becomes unnecessary, and thus, the time for writing can be reduced. Further, the influence of the over-erased cell on the data reading can be suppressed, and a defective cell can be repaired simply by replacement with a redundant cell.
FIG. 3 shows an exemplary construction of address input circuit 2 shown in FIG. 1. Referring to FIG. 3, address input circuit 2 includes an inverter 2 a inverting the clock signal CLK, an AND gate 2 b receiving the clock signal CLK and an external address signal ADD, an AND gate 2 c receiving an output signal from inverter 2 a and an external command CMD, and an NOR gate 2 d receiving output signals from AND gates 2 b and 2 c and generating an internal address signal IADD. These gates 2 b to 2 d are formed by a composite gate.
In the address input circuit 2 shown in FIG. 3, when clock signal CLK is at an H level (logical high level), internal address signal IADD is generated in accordance with the external address signal ADD. When the clock signal CLK attains to an L level (logical low level), the output signal of inverter 2 a attains to the H level, and based on command CMD, internal address IADD is generated and applied to predecoders 3 A and 3 B shown in FIG. 1. Command CMD and address signal ADD are generally applied through a common terminal. Command CMD designates an operation mode such as data writing, erasure, and test mode. When command CMD is applied, internal address signal IADD is applied, as a command, to a sequence controller, not shown, and decoded, whereby the designated operation is executed.
In address input circuit 2 , by taking the command CMD and the address signal ADD at different phases of the clock signal CLK, the address signal and the command can surely be distinguished from each other, even when an operation mode (write or erase) is designated in accordance with a write enable signal.
FIG. 4 schematically shows propagation waveforms of the address signal in the non-volatile semiconductor memory device shown in FIG. 1. In response to a rise of clock signal CLK, address input circuit 2 generates, from external address signal ADD, an internal address signal IADD. Interconnection distance from address input circuit 2 to predecoder 3 A is substantially the same as that to predecoder 3 B, and therefore, predecoders 3 A and 3 B start predecoding operation substantially at the same timing. The predecoded signals are transmitted to corresponding address latch circuits 4 A and 4 B. Therefore, in a selected memory block, only the predecoded address signal is transmitted from an associated predecoder over a short interconnection distance, and therefore, it can be transmitted stably with small skew to the address latch circuit. Therefore, address latch timing in address latch circuits 4 A and 4 B can be set faster.
The latch predecoded signal is simply transmitted from address latch circuit 4 A or 4 B to the corresponding decode circuit 5 A or 5 B, and the interconnection distance therebetween is short. Therefore, when decode circuit 5 A or 5 B generates a decode signal in accordance with the latched address, high speed transmission is possible, and hence, address decode circuit 5 A or 5 B can perform the decoding operation and generate the decode signal at a faster timing. Therefore, in this case also, the decode signal can be generated from the latched address from address latch circuits 3 A and 3 B and can attain to the definite state in a short period of time, and hence, the decode signal can be driven to the definite and settled state at high speed. Accordingly, the margin for reading operation can be enlarged, and the timing for starting the reading operation can be made faster. Thus, high-speed reading becomes possible.
As described above, according to the first embodiment of the present invention, the memory array is divided into memory blocks, and for each memory block, a predecoder, an address latch circuit and an address decode circuit are arranged, whereby the address decoding operation can be performed in accordance with the internal address signal transmitted with sufficiently small skew from the address input circuit. Consequently, the margin for the timing of starting a reading operation can be enlarged, and accurate and high-speed reading is achieved.
FIG. 5 more schematically shows the construction of memory array 1 and decode circuits 5 a and 5 b shown in FIG. 1. FIG. 5 shows a construction in one memory block of memory blocks MBA and MBB of memory array 1 . Memory block MB (MBA or MBB) includes 8 memory mats MM 0 U-MM 3 U and MM 0 L-MM 3 L. Each of the memory mats MM 0 U-MM 3 U and MMOL-MM 3 L includes an information bit region IBR for storing information (data) bits and a parity region PBR for storing parity bits. In information bit region IBR, 16 bit line blocks each including 32 bit lines (subbit lines) are provided, and a total of 512 bit lines (subbit lines) are arranged.
Decode circuit 5 ( 5 A or 5 B) includes an X decoder 12 u provided corresponding to memory mats MM 0 U-MM 3 U arranged in alignment in a row extending direction, an X decoder 12 l provided corresponding to memory mats MM 0 L-MM 3 L arranged in the row extending direction, and a Y decoder 13 . X decoders 12 u and 12 l decode a latched address (predecode address signal) from corresponding address latch circuit 4 , and based on the result of decoding, drive a control gate line through a driver included in a driver band 14 .
The control gate line from X decoder 12 u is arranged extending commonly to corresponding memory mats MM 0 U-MM 3 U. A control gate driving signal applied from X decoder 12 l through driver band 14 is commonly applied to memory mats M 0 L-M 3 L, One of X decoders 12 u and 12 l is selected, and either in the upper memory mats MM 0 U-MM 3 U or in lower memory mats MM 0 L-MM 3 L, a control gate line is driven to a selected state.
It is noted, however, that one of the memory blocks MBA and MBB is driven to the selected state, and the control gate lines are not simultaneously driven to the selected state in both of the blocks.
Further, as will be described in detail later, in one memory block, two sets of memory mats MM 0 U-MM 3 U and MM 0 L-MM 3 L shown in FIG. 5 are arranged. In the second embodiment, for simplicity of drawings, only one set of memory mat trains MM 0 U-MM 3 U and MM 0 L-MM 3 L is shown.
Corresponding to memory mats MM 0 U-MM 3 U, selectors YG 0 U-YG 3 U are provided, for selecting a corresponding bit line in accordance with a Y selection signal from Y decoder 13 , and corresponding to memory mats MM 0 L-MM 3 L, selectors YG 0 L-YG 3 L are provided, each for selecting a column (bit line) from a respective memory mat. Between these selectors YG 0 U-YG 3 U and selectors YG 0 L-YG 3 L, sense amplifier circuits SK 0 -SK 3 for sensing and amplifying selected memory cell data in accordance with a sense amplifier enabling signal from Y decoder 13 are provided.
In data reading, in each of memory mats MM 0 U-MM 3 U or MM 0 L-MM 3 L, 16 information bits are read, and a total of 64 information bits are read. For detecting and correcting any error in 64 bits of information, an ECC code of 7 bits is used. The ECC code is formed by dividing 64 information bits into 7 sets of bits in accordance with a prescribed algorithm, and by finding a parity bit for the bits of each divided set. The parity bits forming the ECC code are arranged uniformly dispersed over memory mats MM 0 U-MM 3 U or MM 0 L-MM 3 L. Specifically, in each of memory mats MM 0 U-MM 2 U, 2 parity bits are stored in the parity region PBR, and in memory mat MM 0 U, 1 parity bit is stored in the parity region PBR. The length MML of each of memory mats MM 0 U-MM 3 U and MM 0 L-MM 3 L is set to be as equal as possible among the memory mats.
Between memory mats MM 0 U-MM 3 U and MM 0 L-MM 3 L, source line driver portions SLD 0 -SLD 2 are provided. These source line driver portions SLD 0 -SLD 2 supply a prescribed voltage to the source lines in writing or erasing data. In data reading, source line driver portions SLD 0 -SLD 2 maintain the source lines of the corresponding memory mats at the ground voltage level. As the parity bits are stored being uniformly dispersed over memory mats MM 0 U-MM 3 U and MM 0 L-MM 3 L, the following effects can be provided.
Assume that the ECC code is arranged concentrated on one memory mat MM, as shown in FIG. 6A. In this case, in data reading, common source line CSL is coupled to the ground potential at the source line driver portion SLD, as shown in FIG. 6A. The common source line CSL is arranged extending commonly over information bit region IBR and parity bit region PBR in one memory mat. At the time of data reading, 16 bits of memory cells MC 0 -MC 15 are coupled to common source line CSL in the information bit region IBR, and 7 bits of memory cells MC 16 -MC 22 are coupled to common source line CSL in the parity bit region PBR. Reading of data is performed by sensing a magnitude of a memory cell current Im flowing from bit line BL through memory cells MC (MC 0 -MC 22 ).
Here, as there is a line resistance Rp of common source line CSL, in the case when a total of 23 memory cells are coupled, the common source line CSL becomes longer and comes to have larger line resistance Rp. Therefore, when the memory cell current Im flows, the potential of the common source line CSL floats up much greater, because of the large line resistance and the increase in current resulting from the increased number of memory cells through which the memory cell current flows. As a result, source potential distribution occurs among memory cells MC 0 -MC 22 , and possibly the magnitude of memory current Im to be driven in the state of same threshold voltage may differ. Particularly, in a memory cell at which the source line potential floats up significantly, the memory cell current Im becomes smaller, and therefore, a state having a small threshold voltage may possibly be determined erroneously as a state having large threshold voltage.
When the parity bit region PBR is arranged uniformly in each memory mat as shown in FIG. 6B, it follows that the memory cells MC 16 and MC 17 storing parity bits of at most 2 bits are coupled to one common source line CSL, through which the memory cell current Im flows. In this case, the length of common source line CSL becomes shorter than in FIG. 6A, line resistance Rpp becomes smaller, and the driving source line current is also reduced. Therefore, floating up of the potential of common source line CSL can be suppressed, the memory cell current Im corresponding to the threshold voltage of the memory cell can be driven stably, and accurate data reading is achieved.
Therefore, when the memory mat MM is set to have the equal length ML as shown in FIG. 5, the length of the common source line CSL can be made equal, variation in floating up of the source potential among memory cells of a memory mat can be suppressed, and stable data reading becomes possible.
The arrangement of the common source line CSL is similar in a hierarchical structure having a sub source line connected common to memory cells MC connected to 32 bit lines BL and a global source line arranged common to the sub source lines of the memory mat. Floating up of potential of the global source line is transmitted to the common sub source line, causing the same problem. Therefore, by arranging the memory cells storing parity bits uniformly dispersed over a plurality of memory mats, the number of selected memory cells connected to one global source line can be made uniform, and the variation in source potential can be suppressed.
Further, the number of selected memory cells connected to the common source line CSL becomes smaller, the total sum of memory cell currents Im flowing into the common source line is reduced, and accordingly, floating up of the potential of common source line CSL can further be suppressed.
In the construction described above, 64 bits of data are stored dispersedly in four memory mats. The bit width of information (data) may be of a different size, and the number of divided memory mats is not limited to 4, and may be 8 or other number of divisions.
As described above, according to the second embodiment of the present invention, the parity bits of the ECC code are stored uniformly dispersed over divided regions of the memory block, that is, over a plurality of memory mats, and in each memory mat, the memory cell current flowing into a source line and a source line resistance can be made uniform, for each of the source line driver portions SDL 0 -SDL 3 . Thus, floating up of the potential of the common source line can be suppressed. Accordingly, sufficient memory cell current flows in each memory cell, enabling accurate and high speed data reading.
FIG. 7 schematically shows a construction of a portion for reading 1 bit of internal data, of the non-volatile semiconductor memory device according to the third embodiment of the present invention. In FIG. 7, a construction of a portion for reading 1 bit of memory cell data from memory mats MMk and MMj is shown as a representative. Memory mats MMk and MMj correspond to the memory mat MMU (MM 0 U-MM 3 U) and MML (MM 0 L-MM 3 L) shown in FIG. 5.
In each of memory mats MMk and NMj, one bit line (subbit line) is selected from 32 bit lines (subbit lines) SBL. Here, 32 subbit lines are divided into subbit line groups BLG 0 -BLG 3 each including 8 subbit lines SBL. A memory cell is connected to a subbit line SBL. Here, in an internal data reading path, the data is successively transmitted through the common bit line to the main bit line, and therefore, the bit line to which the memory cell is connected will be referred to as the subbit line.
In memory mat MMk, there are provided a first selector 20 k for selecting one subbit line in accordance with a Y selection signal YRA from each of the subbit line groups BLG 0 -BLG 3 , and a second selector 21 k for selecting one subbit line from four subbit lines selected by the first selector 20 k in accordance with a Y selection signal YRB. Similarly, in memory mat MMj, there are provided a first selector 20 j for selecting 1 bit of subbit line in accordance with the Y selection signal YRA from each of the subbit line groups BLG 0 -BLG 3 , and a second selector 21 j for selecting one subbit line from the four subbit lines selected by the first selector 20 j in accordance with the Y selection signal YRB.
The first selector 20 k and the second selector 21 k are included in a set of selectors YG 0 U-YG 3 U or selectors YG 0 L-YG 3 L shown in FIG. 5, and the first selector 20 j and the second selector 21 j are included in the other set of selectors.
To the data lines (common bit lines) between the first selector 20 k and the second selector 21 k and to the common bit lines between the first selector 20 j and the second selector 21 j, reference current supplying circuits VRF 0 -VRF 3 are coupled, respectively. In accordance with a block selection signal RFBS, these reference current supplying circuits VRF 0 -VRF 3 supply a reference current to (extract the reference current from) the unselected memory mats.
Outputs of the second selectors 21 k and 21 j are coupled to a sense amplifier circuit SA. The sense amplifier circuit SA differentially amplifies a current flowing through the common bit lines selected by the second selectors 21 k and 21 j, in accordance with activation of a sense amplifier activating signal (sense amplifier enabling signal) SAE, and drives sense output lines (internal data read lines) Ibk and Ibj in accordance with the result of amplification. The internal read data lines Ibk and Ibj are coupled to an internal read buffer circuit, not shown, and the sense amplifier circuit output signal is further amplified, so that the amplified internal read data is transmitted to output latch circuit 6 (see FIG. 1).
In memory mats MMk and MMj, 16 sets of subbit line groups BLG 0 -BLG 3 are provided in the information bit region, and 1 bit of memory cell is selected in each set, so that a total of 16 bits of memory cell data (information bits) are read. Similar construction is provided in the parity region, and 1 bit or 2 bits of parity bits are read simultaneously in parallel.
FIG. 8 more specifically shows the configuration of the selectors, the reference current supplying circuits and the sense amplifier circuit for two subbit line groups in the internal data reading portion shown in FIG. 7. Referring to FIG. 8, in each of memory mats MMk and MMj, subbit line group BLG 0 includes subbit lines SBL 0 -SBL 7 and subbit line group BLG 1 includes subbit lines SBL 8 -SBL 15 .
Each of the first selectors 20 k and 20 j includes subbit line selecting gates T 0 -T 7 formed of P channel MOS transistors provided corresponding to 8 subbit lines of each subbit line group. To the subbit line selecting gates T 0 -T 7 , first Y selection signals yra < 0 >-yra < 7 > are applied, respectively. One of the first Y selection signals yra < 0 >-yra < 7 > is set to a selected state (L level), one of the subbit line selecting gates T 0 -T 7 is set to the selected state, and the selected subbit line is coupled to the corresponding common bit line. When the Y selection signal yra < 0 > attains to the selected state of L level, subbit line selecting gate T 0 is rendered conductive, and subbit lines SBL 0 and SBL 8 are coupled to common bit lines CBL 0 (CBLk 0 , CBLj 0 ) and CBL 1 (CBLk 1 , CBLj 1 ), respectively. The common bit lines are arranged corresponding to each subbit line group, and the selected subbit line of each subbit line group is coupled to the corresponding common bit line.
The first Y selection signals yra < 0 >-yra < 7 > correspond to Y selection signal YRA shown in FIG. 7.
Each of the second selectors 21 k and 21 j includes common bit line selecting gates G 0 -G 3 formed of P channel MOS transistors provided corresponding to common bit lines CBL 0 (CBLk 0 , CBLJ 0 )-CBL 3 (CBLk 3 , CBLj 3 ), respectively. To the gates of these common bit line selecting gates G 0 -G 3 , second Y selection signals yrb < 0 >-yrb < 3 > are applied, respectively. These second Y selection signals yrb < 0 >-yrb < 3 > correspond to the Y selection signal YRB shown in FIG. 7.
One of the second Y selection signals yrb < 0 >-yrb < 3 > is driven to the selected state, a corresponding one of the common bit line selecting gates G 0 -G 3 is turned on and the corresponding one of the common bit lines CBLk 0 -CBLk 3 and the corresponding one of common bit lines CBLj 0 -CBLj 3 are coupled to the sense amplifier circuit SA.
Reference current supplying circuit VRF 0 is coupled to common bit lines CBLk 0 and CBLj 0 , and reference current supplying circuit VRF 1 is coupled to common bit lines CBLk 1 and CBLj 1 . Reference current supplying circuits VRF 0 and VRF 1 have the same construction, and corresponding components are denoted by the same reference characters.
Reference current supplying circuit VRF 0 includes: P channel MOS transistors PG 1 and PG 2 rendered conductive in response to a precharge designating signal pc< 0 > and coupling common bit lines CBLk 0 and CBLj 0 to a power supply node when made conductive; a P channel MOS transistor PG 0 isolating the common bit lines CBLk 0 and CBLj 0 in response to precharge designating signal pc< 0 > an N channel MOS transistor NG 1 receiving, at its gate, a reference voltage Vmsg; a P channel MOS transistor PG 4 coupling N channel MOS transistor NG 1 to common bit line CBLj in response to a reference block selection signal VFDCjN; and a P channel MOS transistor PG 3 rendered conductive in response to the reference block selection signal VFDCkN and coupling N channel MOS transistor NG 1 to common bit line CBLk 0 when made conductive.
Similarly, reference current supplying circuit VRF 1 includes: precharging P channel MOS transistors PG 1 and PG 2 coupling common bit lines CBLk 1 and CBLj 1 to a power supply node in response to a precharge designating signal pc< 1 > a P channel MOS transistor PG 0 isolating the common bit lines CBLk 1 and CBLj 1 in response to the precharge designating signal pc< 1 > an N channel MOS transistor NG 1 receiving, at its gate, the reference voltage Vmsg and serving as a constant current source; and P channel MOS transistors PG 4 and PG 3 coupling N channel MOS transistor NG 1 to common bit lines CBLk 1 and CBLj 1 in accordance with the reference block selection signals VFDCjN and VFDCkN, respectively.
In these reference current supplying circuits VRF 0 and VRF 1 , when the precharge designating signals pc< 0 > and pc< 1 > are at the active state of L level, common bit lines CBLk 0 and CBLj 0 are precharged to and equalized at the power supply voltage level, and common bit lines CBLk 1 and CBLj 1 are precharged to and equalized at the power supply voltage level, by P channel MOS transistors PG 0 -PG 2 . When the precharge designating signals pc< 0 > and pc< 1 > attain to the inactive state of H level, the precharging operation is finished, and the equalizing operation of the common bit lines is finished.
In data reading, one of the reference block selection signals VFDCjN and VFDCkN attains to the active state of L level. Therefore, the common bit lines are discharged through constant current source MOS transistor NG 1 to the memory mat different from the memory mat including the selected memory cell, that is, the reference block. FIG. 8 shows, as an example, a state in which no memory cell is selected in memory mat MMk, through the selected subbit line selecting gate of the first selector 20 k, the charging subbit line current is discharged through the reference current supplying circuit VRF 0 , and in memory mat MMj, the precharged current flows on the subbit line SBL through the selected memory cell.
The reference current driven by the reference current supplying circuit VRF 0 or VRF 1 is compared with the subbit line current driven by the memory cell, by the sense amplifier circuit SA.
The sense amplifier circuit SA includes a P channel MOS transistor PG 5 and an N channel MOS transistor NG 4 rendered conductive when the sense amplifier activating signal SAE is active (at H level); a P channel MOS transistor PG 6 and an N channel MOS transistor NG 3 connected between MOS transistors PG 5 and NG 4 and forming a CMOS inverter; and a P channel MOS transistor PG 7 and an N channel MOS transistor NG 2 connected between MOS transistors PG 5 and NG 4 and forming a CMOS inverter. MOS transistors PG 6 and NG 3 have their gates coupled to sense output line (internal data read line) Ibj, and MOS transistors PG 7 and NG 2 have their gates coupled to sense output line (internal data read line) Ibk.
Sense amplifier circuit SA further includes a P channel MOS transistor PG 8 precharging a common source node of MOS transistors NG 2 and NG 3 to the level of the power supply potential, when the sense amplifier activating signal SAE is rendered inactive.
The sense amplifier circuit SA is a CMOS inverter latch circuit, and by the cross-coupled MOS transistors PG 6 and PG 7 and cross-coupled N channel MOS transistors NG 3 and NG 2 , it differentially amplifies and latches the potentials of sense output lines Ibk and Ibj reflecting the difference between the memory cell current and the reference current.
Therefore, through sense output lines (internal data read lines) Ibk and Ibj, complementary differential signals are transmitted. The potentials on sense output lines Ibk and Iblj are amplified by an internal read buffer circuit, not shown, and transmitted to a read main bit line.
The current, ire, driven by reference current supplying circuits VRF 0 and VRF 1 is set to a current level of an intermediate value (½) between the current driven by a memory cell storing data of H level and a current driven by a memory cell storing L level. By comparing the reference current, ire, with the memory cell current Im, the data stored in the selected memory cell can be read.
Here, the correspondence between the threshold voltage of the memory cell and data of H and L levels may be appropriately defined. Specifically, the state of high threshold voltage and the state of low threshold voltage may correspond to the H level data and L level data, respectively, or vice versa. Further, the correspondence between the written (programmed) state and erased state and the state of high threshold voltage and the state of low threshold voltage may be appropriately defined, as described above.
FIG. 9 is a timing diagram representing an operation of the internal data reading portion shown in FIG. 8.
The operation of the internal data reading portion shown in FIG. 8 will be described with reference to FIG. 9.
In synchronization with a rise of a main clock signal CKM (clock signal CLK), an internal address signal is generated from the address input circuit, transmitted through a predecoder to the address latch circuit, and a latch address (predecoded address) signal LADD output from the address latch circuit is made definite (see FIGS. 1 and 5).
When the main clock signal CKM rises, the address latch circuit is set in the latch state and the latched address signal LADD is made definite and settled, a subbit line discharge signal, dc, is driven to the L level, and an internal data reading cycle starts. In this state, memory cell selecting operation is not yet performed in the memory mat, the control gate signals cg <N: 0 > driving the control gate lines CGL are all at the L level, and the memory cells are all at the unselected state. In one memory mat, as an example, 256 control gate lines are arranged (N=255).
The precharge signals pc < 3 : 0 > are all at the H level, and reference current supplying circuits VRF 0 -VRF 3 are all inactive. Further, the sense amplifier activating signal SAE is also at the L level, and sense amplifier circuit SA is in the inactive state, as MOS transistors PG 5 and NG 4 are off.
Further, subbit lines SBL < 511 : 0 > (512 subbit lines for storing information bits in one memory mat) are all at the unselected state of L level.
When the internal read cycle starts, first, by the Y decoder, one common bit line selection signal among the second Y selection signals (common bit line selection signals) yrb < 3 : 0 > is driven to the selected state (L level), and in each of the second selectors 21 k and 21 j, one of the common bit line selecting gates G 0 -G 3 is set to the on state, and the sense amplifier circuit SA is coupled to the selected common bit lines.
After a prescribed time period AT from settlement of the common bit line selection signals yrb < 3 : 0 >, the first Y selection signals (subbit line selection signals) yra < 7 : 0 > are driven to the definite state similarly by the Y decoder. By the subbit line selection signals yra < 7 : 0 >, in the first selectors 20 k and 20 j, one of the subbit line selecting gates T 0 -T 7 is rendered conductive, and corresponding subbit lines are connected to the corresponding common bit lines, respectively. To the common bit lines CBL 0 -CBL 3 , reference current supplying circuits VRF 0 -VRF 3 are coupled, respectively. Based on the common bit line selection signals yrb < 3 : 0 > and a precharge end enable signal pcend, one of the precharge signals pc < 3 : 0 > is driven to the selected state. In FIG. 9, the selected state is denoted by “sel” and the unselected state is denoted by “usel”. Consequently, the reference current supplying circuit connected to the common bit line coupled to the sense amplifier circuit is activated, the common bit line is precharged to a prescribed voltage (power supply voltage) by MOS transistors PG 0 -PG 2 , the precharge current is supplied to the selected subbit line, and the voltage level of the selected subbit line SBL increases. In this case, in each of the memory mats MMk and MMj, precharge current is supplied to the subbit line of the same position, and the potential of the selected subbit line increases to the H level. At the time of precharging operation, in the reference current supplying circuit VRF (any of VRF 0 -VRF 3 ), MOS transistors PG 3 and PG 4 are both on, and therefore, the reference current is driven in accordance with the reference voltage Vmsg.
When the selected subbit line is precharged to a prescribed voltage level, one of the reference block selection signals VFDCjN and VFDCkN attains to the H level immediately before the start of decoding operation by the X decoder, and in the reference current supplying circuit, one of the MOS transistors PG 3 and PG 4 turns off, so that the common bit line of the selected memory mat is isolated from MOS transistor NG 1 serving as the constant current source.
Then, X decoders 12 u and 12 l shown in FIG. 5 perform the decoding operation, and drive one of the control gate signals cg <N: 0 > to the selected state. The control gate signals cg <N: 0 > are transmitted to the control gate lines (CGL) to each of which memory cells are connected, and in the memory cell connected to the selected control gate line, an inversion layer is formed at a surface of the substrate region immediately below the control gate. Though memory gates are similarly driven to the selected state, the inversion layer is selectively formed below the memory gate, dependent on the stored data. In one of the memory mats MMk and MMj, the control gate line CGL is driven to the selected state and in the other memory mat, the control gates are all at the unselected state.
In synchronization with the driving of the control gate line to the selected state, the precharge end enable signal pcend attains to the H level and, in response, the precharge signal pc in the selected state (any of pc < 3 : 0 >) attains to the H level, MOS transistors PG 0 -PG 2 turn off in the reference current supplying circuit VRF (VRF 0 -VRF 3 ) corresponding to the selected common bit line, and the precharge operation is completed.
By establishing synchronization as much as possible between the timings of driving the memory cell current and driving the reference current to the subbit line, the potential difference in accordance with the reference current and the memory cell current is reliably transmitted to internal read data lines (sense output lines) Ibk and Ibj. In FIG. 9, the rise of the main clock signal CKM is used as a reference and after the delay time of DL 2 , the subbit line is driven by the constant current, thereafter, the control gate line is driven to the selected state, and after the delay time DL 1 from the rise of the main clock signal CKM, the precharge end enable signal pcend is activated to finish the precharging operation. There is an overlapping period, ΔT, between the precharging operation of the selected subbit line and driving of the selected control gate line CGL to the selected state. Thus, erroneous reading resulting from unstable memory cell current, which may occur when the control gate line CGL is at the state of intermediate voltage level, can be prevented.
In the subbit line connected to the selected memory cell, the voltage level changes at different speed dependent on the data stored in the memory cell. FIG. 9 shows both changes in potential of the subbit line SBL in the cases of high threshold voltage and low threshold voltage. The subbit line SBL driven by the reference current is discharged by the MOS transistor NG 1 serving as a constant current source, and therefore, the potential level thereof decreases gradually. The speed of change of the potential of reference subbit line SBL is intermediate between the speeds of change of the potential to the H level and to the L level, of the selected subbit line SBL to which the selected memory cell is connected.
Because of the change in potential of the selected subbit line and the reference subbit line, potential difference appears in the voltage levels of sense output lines Ibk and Ibj connected to the sense amplifier circuit, and when the difference becomes about 10 mV, the sense amplifier activating signal SAE is activated, and the potential difference between the internal read data lines (sense output lines) Ibk and Ibj is differentially amplified.
In response to activation of the sense amplifier activating signal SAE, a subbit line discharge signal dc, the subbit line selection signals yra < 7 : 0 > and the common bit line selection signals yrb < 3 : 0 > are inactivated (Y decoder is inactivated). In response, sense amplifier circuit SA is isolated from the common bit lines and subbit lines, the load thereon is alleviated, and high speed sensing operation is achieved. The sensing operation is performed on 64 bits of data (not considering parity bits), that is, data Ibj < 63 : 0 > and Ibk < 63 : 0 > in parallel, and 64 bits of data (71 bits of data including parity bits) are internally read in parallel.
After a prescribed time period from activation of the sense amplifier activating signal SAE, the X decoder is inactivated provided that the subbit line discharge signal dc is inactivated, the control gate signals cg <N: 0 > are inactivated, and the control gate lines are driven to the ground voltage level. As the sense amplifier has been activated, the subbit line SBL is isolated from the reference current supplying circuit, and thus, the subbit line SBL is discharged to the ground voltage level (as will be described later, there is provided a subbit line discharging transistor).
Thereafter, of the reference current control signals VFDCjN and VFDCkN, one that corresponds to the selected memory mat is driven to the inactive state, and by the transistor NG 1 serving as the constant current source of the reference current supplying circuit, the common bit line is discharged to the ground voltage level.
Thereafter, the sense amplifier activating signal SAE is inactivated, and thus one data reading cycle ends.
Further, as shown in FIG. 9, in response to activation of the sense amplifier activating signal SAE, the subbit lines are driven to the unselected state, that is, the Y decoder is inactivated and the control gate line CGL is inactivated (X decoder is reset). Therefore, at the start of the next reading cycle, what is required is simply to drive the Y selection signal, that is, the subbit line selection signals yra < 7 : 0 > and the common bit line selection signals yrb < 3 : 0 > from the initial state of H level to the L level, for the selected signal. Different from the static decoding operation, it is unnecessary to drive the subbit line selection signals and the common bit line selection signals from the H level to the L level and from the L level to the H level at high speed. Therefore, the driving power of the Y decoder can be reduced (high-speed operation is required only for activation). Further, the subbit line selection signals yra < 7 : 0 > and the common bit line selection signals yrb < 3 : 0 > are not set to a multi-selection state (transition to the unselected state and transition to the selected state do not overlap), and hence, can be driven to the definite and settled state at a faster timing.
Further, as the control gate line is inactivated (X decoder is reset) in accordance with the sense amplifier activating signal SAE, the end time of the reading cycle can be made earlier, and hence, the start timing of the next reading cycle can be set faster.
Further, the predecoded address signal is latched by the address latch circuit to generate the latched address signal LADD, and when the address latch circuit enters the latching state, the latched address signal LADD has already been settled, and therefore, the skew of the latched address signal LADD can be reduced. Therefore, the decoding operation can be performed at a faster timing in the address decode circuit (X decoder and Y decoder) in accordance with the latched address signal (latched predecoded signal) LADD, so that the margin for the decoding operation can be enlarged and the reading timing can be set faster.
FIG. 10 schematically shows a state of a portion related to the sense amplifier at the time of precharging, in a data reading. As shown in FIG. 10, at the time of precharging, the reference current supplying circuit VRF supplies the power supply voltage VCC to subbit lines SBLk and SBLj through common bit lines CBLk and CBLj, and drives a constant current by constant current source transistor NG 1 (as the signals VFDCjN and VFDCkN are both at the L level). At this time, the common bit lines CBLj and CBLk are equalized (by MOS transistor PG 0 ).
Thereafter, there is an overlap period between driving of the selected control gate line to the selected state and precharging operation of the subbit line, and then, the memory cell data is read, from the subbit line currents, as shown in FIG. 11. Here, as an example, a memory cell MC is connected to subbit line SBLk, and the memory cell current Im corresponding to the stored data is driven to the source line SL. For subbit line SBLj, the control gate line is in the unselected state, and from common bit line CBLj, the reference current iref is driven (discharged), by the constant current source transistor NG 1 in the reference current supplying circuit VRF. The constant current source transistor NG 1 is isolated from the common bit line CBLk. When the potential difference between the sense nodes (sense output lines Ibk and Ibj) of the sense amplifier circuit SA increases because of the difference between the memory cell current Im and the reference current iref, the sense amplifier circuit SA is isolated from common bit lines CBLk and CBLj, to perform the sensing operation.
Therefore, in the unselected subbit line groups, even when the subbit line is coupled to the common bit line by the first selector, the corresponding common bit line is simply discharged to the ground voltage level by the constant current source transistor of the reference current supplying circuit, and precharging operation is not performed (the precharge signal pc is kept at the H level). Therefore, current is not consumed in the unselected subbit line groups.
Particularly, as the decoder is reset after reading, the common bit line selection signal can be set to the initial state at the start of the next data read cycle, and the precharge signal can easily be generated based on the common bit line selection signal.
FIG. 12 shows an example of the construction of a circuit for generating the precharge signals pc < 3 : 0 >.
Referring to FIG. 12, the precharge signal generating portion includes an OR circuit 24 that receives the precharge end enable signal, pcend, and the common bit line selection signals yrb < 3 : 0 >. The OR circuit 24 includes OR gates provided for respective bits of the common bit line selection signal yrb < 3 : 0 >, and generates a precharge signal pc < 3 : 0 > of 4 bits. Therefore, when the precharge end enable signal, pcend, and one of the common bit line selection signals yrb < 3 : 0 > both attain to the L level, the corresponding one of precharge signals pc < 3 : 0 > attains to the L level, and the precharge operation is executed for the selected subbit line.
In each memory mat, in accordance with the common bit line selection signals yrb < 3 : 0 > from the Y decoder and the main precharge end enable signal, pcend, the corresponding one of precharge signals pc < 3 : 0 > is generated, and therefore, in each memory mat, the precharge signal can be generated at high speed, alleviating the load on the precharge signal.
In the above described construction, using the reference current supplying circuit VRF, the reference current for the memory cell is driven. It is noted, however, that a dummy cell may be provided in the memory mat, and the reference current may be generated using such dummy cell.
As described above, according to the third embodiment of the present invention, the address decode circuit is reset by the sense amplifier activating signal SAE, so that internal reading circuitry can be recovered at high speed to the initial state. Therefore, the read cycle can be made shorter, and high-speed data reading becomes possible.
Further, the direction of signal change in the next cycle is simply in the direction to the activation state. Thus, it is unnecessary to perform both activation and inactivation of signals. Consequently, various selection signals and control signals can be reliably driven to the active state at high speed.
Further, the precharge signal is generated based on the main precharge control signal and the common bit line selection signals. Therefore, what is necessary is simply to generate the precharge signal in each memory mat. Thus, based on the common bit line selection signal in the reset state, the precharge signal can be generated accurately.
FIG. 13 schematically shows correspondence between an output of one X decoder ( 12 u or 12 l ) and the control gate lines of memory mat MM, of the non-volatile semiconductor memory device according to the present invention. Memory mat MM corresponds to one memory mat (MM 0 U-MM 3 U (MMU) and MM 0 L-MM 3 L (L)) shown in FIG. 5 described previously.
Referring to FIG. 13, by the X decoder outputs, memory mat MM is divided into control gate blocks SCT 0 -SCT 31 each including 32 control gate lines CGL. Each of the control gate blocks SCT 0 -SCT 31 may form one sector, and erasure may be performed in units of sectors. Control gate blocks SCT 0 -SCT 31 are designated by the predecoded block designating signals bs < 0 >-bs < 31 >, respectively. The predecoded block designating signals bs < 0 >-bs < 31 > are generated from the X decoder ( 12 u or 12 l ) shown in FIG. 5. Therefore, it follows that 1024 control gate lines are arranged on one memory mat. In a selected memory block (memory block MBA or MBB of FIG. 1), one control gate block is designated.
FIG. 14 shows a more detailed construction of the control gate block shown in FIG. 13. As shown in FIG. 14, control gate block SCT (one of SCT 0 -SCT 31 ) is divided into control gate groups SSCT 0 -SSCT 7 each including four control gate lines CGL. The control gate groups SSCT 0 -SSCT 7 are specified by the predecoded signal bits xclka < 0 >-xclka < 7 >, respectively. The predecoded signal bits xclka < 0 >-xclka < 7 > are applied from the address latch circuit shown in FIG. 5, namely, they are the predecoded signal bits generated from predecoder 3 ( 3 A or 3 B) shown in FIG. 1. The control gate group SCCT includes four control gate lines CGL, and one control gate block includes 8 control gate groups, and therefore, 32 control gate lines CGL are included in total in one control gate block.
As will be described later, a memory mat corresponding to one sense amplifier band (sense amplifiers) includes 8 control gate blocks. Therefore, in a memory mat corresponding to one sense amplifier band, there are 256 control gate lines CGL. The control gate lines are shared by memory cells aligned along the column direction (word line extending direction), in one memory block.
FIG. 15 shows a detailed construction of the control gate group shown in FIG. 14. Each control gate group SSCT (one of SSCT 0 -SSCT 7 ) includes four control gate lines CGL 0 -CGL 3 . The control gate lines CGL 0 -CGL 3 are specified by the predecoded signal bits xclkb < 0 >-xclkb < 3 >, respectively. The predecoded signal bits xclkb < 0 >-xclkb < 3 > are also the predecoded signal bits applied from address latch circuit 4 shown in FIG. 5.
As shown in FIGS. 13 to 15 , in the selected memory block, in accordance with the combination of predecode block designating signal bits bs < 0 : 3 : 1 > and predecoded signal bits xclka < 0 : 7 > and xclkb < 0 : 3 >, one control gate line CGL is driven to the selected state, in accordance with the output signals from X decoder.
FIG. 16 schematically shows constructions of the address latch circuit and the decode circuit in accordance with the fourth embodiment of the present invention. FIG. 16 shows address latch circuit 4 , X decoder 12 and Y decoder 13 that are provided for one memory block (MB). X decoder 12 corresponds to the construction shown in FIG. 5 that includes X decoders 12 u and 12 l.
Address latch circuit 4 includes a latch circuit 30 for latching an 8-bit predecoded signal from the predecoder in accordance with a set designating signal SETAN and outputting an 8-bit latch predecoded signal ltbsa; a latch circuit 31 for latching the predecoded signal from the predecoder in accordance with a set designating signal SETBN and outputting a 4-bit latch predecoded signal ltbsb; a latch circuit 32 for latching the predecoded signal from the predecoder in accordance with the set designating signal SETBN and outputting an 8-bit latch predecoded signal XCLKA; a latch circuit 33 for latching the predecoded signal of 4 bits from the predecoder in accordance with the latch designating signal SETBN and outputting a 4-bit latch predecoded signal XCLKB; and a block decode circuit 34 for decoding the latch predecoded signals ltbsa and ltbsb and driving a control gate block designating signal BS of 32 bits.
The set designating signals SETAN and SETBN are activated when the corresponding memory block is selected, and latch the predecoded signal applied from the predecoder. The set designating signals SETAN and SETBN are generated, therefore, based on the address latch timing signal and the block address signal predecoded by the predecoder.
The latch predecoded signals XCLKA and XCLKB correspond to the predecoded signal bits xclka < 0 : 7 > and—xclkb < 0 : 3 >, respectively. Block decode circuit 34 is formed of an AND type decode circuit, and generates, from the 8-bit latch predecoded signal ltbsa and the 4-bit latch predecoded signal ltbsb, the control gate block signal BS (control gate block designating signals bs < 0 : 31 >) that designates one control gate block among 32 control gate blocks.
To latch circuits 30 - 33 , X address reset signal XRST is applied. When the reset signal XRST is active (H level), the contents held by the latch circuits 30 - 33 are reset to the initial state (unselected state).
In latch circuits 30 - 33 , when in a set state, a corresponding one of the predecoded signal bits is set to the active state when selected in accordance with the output signal from the predecoder, and the remaining bits are kept at the unselected state.
X decoder 12 (X decoder 12 u and 12 l of FIG. 5) includes: a control gate power supply circuit 40 ; an X unit decode circuit XDEC receiving 1 bit from each of the control gate block designating signals bs < 0 : 31 > and the predecode signals xclka < 0 : 7 > and xclkb < 0 : 3 > and a control gate drive circuit CDV provided corresponding to each unit decode circuit XDEC, receiving the power supply from control gate power supply circuit 40 as an operational power supply voltage, and driving the corresponding control gate line CGL in accordance with an output signal from the corresponding X unit decode circuit XDEC.
The X unit decode circuit XDEC and the control gate drive circuit CDV are arranged for the control gate line CGL provided in the corresponding memory block.
The control gate block designating signal BS designates one of 32 control gate blocks, and by the predecoded signals xclka and xclkb, one control gate group and a control gate are designated. Therefore, in X decoder 12 , 32×32=1024 X unit decode circuits are provided, and one of 1024 control gate lines CGL is driven to the selected state.
Control gate power supply circuit 40 includes: an N channel MOS transistor 40 c for transmitting a control gate voltage Vcg to a power supply node 41 in accordance with a test mode designating signal TEST 1 ; an inverter 40 a receiving a data read mode designating signal MDSA; a P channel MOS transistor 40 b for transmitting the control gate voltage Vcg to power supply node 41 in accordance with an output signal from inverter 40 a; an inverter 40 d receiving a test mode designating signal TEST 2 ; and a P channel MOS transistor 40 e for transmitting a test voltage VF to power supply node 41 in accordance with an output signal from inverter 40 d.
In the read mode, in accordance with the data read mode designating signal MDSA, the control gate voltage Vcg is supplied to the control gate line drive circuit CDV through P channel MOS transistor 40 b. In the test mode, in accordance with the test mode designating signal TEST 1 , a voltage of Vcg—Vth is transmitted to the control gate line drive circuit CDV. Here, Vth represents threshold voltage of MOS transistor 40 c. When the test mode designating signal TEST 1 is activated, the read mode designating signal MDSA is at the inactive state of L level, and internal data reading is stopped (column selecting operation is stopped).
When the test mode designating signal TEST 2 is activated, the test voltage VF is supplied as an operational power supply voltage to control gate drive circuit CDV. By changing the voltage VF, the margin for the control gate voltage, for example, in the write mode is measured.
Y decoder 13 includes: a latch circuit 42 for latching a 4-bit predecoded signal from the predecoder in response to activation of a set designating signal YRSETN; an inversion buffer circuit YBFB for generating, when activated, a 4-bit Y selection signal (common bit line selection signal) YRBN (yrb < 0 : 3 >) in accordance with a latch predecoded signal outputted from latch circuit 42 ; a latch circuit 43 for latching the predecoded signal from the predecoder in response to activation of the set designating signal YRSETN; an inversion buffer circuit YBFA for outputting, when activated, a Y selection signal (subbit line selection signal) YRAN (yra < 0 : 7 >) in accordance with a latch predecoded signal from latch circuit 43 ; a delay portion 44 for generating a Y related control signal controlling various operations related to column selection (Y related circuitry operation) in accordance with transition of the output signal from latch circuit 43 ; a buffer circuit 45 for outputting a sense amplifier activating signal SAE in accordance with an output signal CKSAEF of delay portion 44 and the read mode designating signal MDSA; an NOR gate 46 receiving the output signal CKSAEF of delay portion 44 and the test mode designating signal MTEST; an inverter 48 receiving an output signal of NOR gate 46 ; and a buffer circuit 50 receiving an output signal of NOR gate 46 and the read mode designating signal MDSA and outputting an X address reset signal XRST.
Inversion buffer circuits YBFA and YBFB are both activated when the output signal from inverter 48 is at the H level and the read mode designating signal MDSA is at the active state of H level, invert the latch predecoded signal from corresponding latch circuits 43 and 42 , and output the Y selection signals YRAN and YRBN.
The test mode designating signal MTEST is set to the H level when the test mode is designated in the non-volatile semiconductor memory device, the output signal of NOR gate 46 is fixed to the L level and, in response, the X address reset signal XRST is fixed to the L level.
Y decoder 13 further includes an AND circuit 47 receiving an output signal of NOR gate 46 and the read mode designating signal MDSA and outputting a reset signal YRRST. When the output signal YRRST of AND circuit 47 attains to the H level, latch circuits 42 and 43 are reset. Accordingly, when the test mode designating signal MTEST is at the active state, the reset signal YRRST for the latch circuits 42 and 43 are fixed to the L level. Therefore, in a test operation, when one control gate line is to be continuously kept at the selected state, or when switching of memory cell selection/unselection is to be performed in synchronization with the clock signal, activation of the reset signals XRST and YRRST in response to activation of the sense amplifier is inhibited.
FIG. 17 shows a specific construction of a portion of four X unit decode circuits of the X decoder shown in FIG. 16. Referring to FIG. 17, the X decode circuit (four X unit decode circuits) includes: P channel MOS transistors PQA 0 -PQA 3 connected to output nodes ND 0 -ND 3 , respectively, and commonly receiving, at their gates, a predecode signal xclka <m> P channel MOS transistors PQB 0 -PQB 3 connected to output nodes ND 0 -ND 3 , respectively, and receiving, at their gates, the predecode signals xclkb < 0 >-xclkb < 3 >, respectively; N channel MOS transistors NQB 0 -NQB 3 connected to output nodes ND 0 -ND 3 , respectively, and receiving, at their respective gates, the predecode signals xclkb < 0 >-xclkb < 3 > an N channel MOS transistor NQA connected commonly to MOS transistors NQB 0 -NQB—and receiving, at its gate, the predecode signal xclka <m> an N channel MOS transistor NQC coupled to MOS transistor NQA and to a ground node, and receiving, at its gate, a predecoded block designating signal bs for selecting a control gate block; P channel MOS transistors PP 0 -PP 3 provided for output nodes ND 0 -ND 3 , respectively, and commonly receiving, at their gates, the predecoded block designating signal bs for selecting a control gate block; and inverter drivers IV 0 -IV 3 provided for output nodes ND 0 -ND 3 , respectively.
In accordance with the output signals xe < 0 >-xe < 3 > of inverter drivers IV 0 -IV 3 , control gate lines CGL 0 -CGL 3 are driven to the selected or unselected state.
MOS transistor NQC is provided commonly to 32 X unit decode circuits receiving the predecode block designating signal bs. MOS transistor NQA is provided commonly to 8 unit X decode circuits arranged corresponding to 8 control gate lines included in the control gate block.
When the predecoded block designating signal bs for designating a control gate block is in the unselected state, the output nodes ND 0 -ND 3 are precharged and maintained at the power supply voltage level by MOS transistors PP 0 -PP 3 . Further, as the MOS transistor NQC is off and the discharge path of output nodes ND 0 -ND 3 is shut off, the output signals xe < 0 >-xe < 3 > of inverter drivers IV 0 -IV 3 all attain to the L level. Therefore, when the control gate block shown in FIG. 13 is in the unselected state, the control gate driving signals for 32 control gate lines CGL included therein are all kept at the inactive state of L level.
When the predecoded block designating signal bs attains to the selected state of H level, MOS transistor NQC turns on and MOS transistors PP 0 -PP 3 are kept off.
When the predecoded signal bit xclka <m> is at the L level, MOS transistor NQA turns off and MOS transistors PQA 0 -PQA 3 turn on, output nodes ND 0 -ND 3 are kept at the power supply voltage level, and corresponding control gate lines CGL 0 -CGL 3 are set to the unselected state. Therefore, even when control gate block SCT (any of SCT 0 -SCT 31 ) shown in FIG. 13 is selected, the corresponding control gate lines CGL 0 -CGL 3 are kept unselected, as long as the control gate group SSCT (any of SSCT 0 -SSCT 7 ) shown in FIG. 14 is in the unselected state.
When the predecoded block designating signal bs and the predecoded signal bit xclka <m> are set to the selected state, MOS transistors NQC and NQA turn on and MOS transistors PQA 0 -PQA 3 and PP 0 -PP 3 are all kept off. In this case, one of the predecoded signal bits xclakb < 0 >-xclkb < 3 > attains to the selected state of H level, and a corresponding one of output nodes ND 0 -ND 3 is driven to the ground voltage level. In response, the corresponding one of the output xes < 0 >-xe < 3 > of inverter drivers IV 0 -IV 3 is driven to the H level, and one of the four control gate lines of the corresponding control gate group SSCT is driven to the selected state.
As shown in FIG. 17, in the X decoder, MOS transistor NQC selecting a control gate block is arranged common to 32 X unit decode circuits provided for the control gate block, and MOS transistor NQA is arranged common to 8 X unit decode circuits included in the control gate group, whereby the number of elements forming the X decoder circuit can be reduced and power consumption can be reduced. Further, load on the predecoded signals bs and xclkb <m> can be alleviated (associated gate capacitance is small), and therefore, decoding operation can be performed at high speed in accordance with the predecoded signal.
FIG. 18 is a timing diagram representing operations of address latch circuit 4 , X decoder 12 and Y decoder 13 shown in FIG. 16. The operations of the circuits shown in FIG. 16 will be described with reference to FIG. 18.
In response to a rise of the clock signal CKM (CLK), the internal address signal IADD is output from the address input circuit. When a command (write enable signal) designates a data read mode before the rise of clock signal CLM, the read mode designating signal MDSA attains to the H level.
When the internal address signal IADD is predecoded by a predecoder, the latch designating signals SETAN and SETBN as well as YRFSTN for the selected memory block (MBA or MBB) attain to the active state of L level. In response, latch circuits 30 - 33 and 42 and 43 attain to the latching state, latching the predecoded signal applied from the predecoder.
In address latch circuit 4 , by X address decode circuit 34 , the predecoded block selection signal BS (bs < 0 : 31 >) is output, and the latch predecoded signals btbsb, XCLKA and XCLKB output from latch circuits 31 - 33 attain to the definite state. These predecode signals are at the H level in the selected state (sel) and L level in the unselected state (usel).
In Y decoder 13 , as the signal MDSA and the output signal of inverter 48 are at the H level, inversion buffer circuits YBFA and YBFB buffer (invert the logic of) the output signals from latch circuits 43 and 42 , and output the Y selection signals YRAN and YRBN. The subbit line selection signal YRAN (yra < 0 : 7 >) and the common bit line selection signal YRBN (yrb < 0 : 3 >) are at the L level in the selected state and at the H level in the unselected state. In accordance with the buffered predecoded signals YRAN and YRBN, a subbit line is selected and coupled to a corresponding sense amplifier. Further, in accordance with these signals BS, XCLKA and XCLKB, a control gate line CGL is driven to the selected state.
In accordance with the change in the output signal of latch circuit 43 , delay portion 44 successively activates/inactivates the Y related control signals, charging/discharging the sub bit line. Then, when the signal CKSAEF from delay portion 44 is activated, the sense amplifier activating signal SAE from buffer circuit 45 is driven to the active state, and a sensing operation is performed. When the output signal CKSAEF of delay portion 44 attains to the H level, the output signal of NOR gate 46 attains to the H level. As the read mode designating signal MDSA is at the H level, the output signal YRRST of buffer circuit 47 attains to the H level, latch circuits 42 and 43 are reset, the latch predecoded signals are returned to the initial state of unselected state, and accordingly, the signals YRAN and YRBN are also driven to the unselected state.
Further, in accordance with an output signal from NOR gate 46 , the X address reset signal XRST from buffer circuit 50 attains to the H level, latch circuits 30 - 33 are reset, and the latched predecoded signals are returned to the initial state. In accordance with the activation of the X address reset signal XRST, the signals BS, XCLKA and XCLKB are set to the unselected state, and in response, control gate line CGL is driven to the unselected state.
When the output signal CKSAEF of delay portion 44 is driven to the inactive state as Y decoder 13 is reset, the sense amplifier activating signal SAE is inactivated in response, and the reset signals YRRST and XRST are both inactivated.
In this data reading, after activation of the sense amplifier, the predecoded signals latched by latch circuits 30 - 33 , 42 and 43 are reset, and therefore, the time Tsm until the next read cycle can be made longer, the data reading process of the next cycle can be started at a faster timing, and high-speed reading becomes possible.
Further, not only the latch circuits but also the Y selection signals YRAN and YRBN are reset. Therefore, even in such a situation that only resetting of the predecoded signals of latch circuits would cause any delay of resetting operation because of gate propagation delay in decode circuits and others of the succeeding stage, the output signal of the Y decoder can be reset quickly, and similarly, at the start of the next cycle, the internal state can reliably be returned to the initial state (inactive state).
In the construction described above, the reset signal is not applied to the X unit decoder circuit XDEC driving the control gate line CGL. The X address reset signal XRST may be applied also to the unit X decoder XDEC. In this case also, the timing of inactivating control gate line CGL can be made faster and therefore, the reading operation can surely be started earlier in the next cycle.
FIG. 19 is a signal waveform diagram representing an operation in the case when the test mode designating signal MTEST shown in FIG. 16 is set to the H level. When the test mode designating signal MTEST is set to the H level, the output signal of NOR gate 46 shown in FIG. 16 is fixed at the L level, and in response, the output signals of AND circuits 47 and 50 are fixed to the L level. The output signal of inverter 48 is kept at the H level.
As shown in FIG. 19, in accordance with the internal address signal LADD, the predecoded signals XCLKA and XCLKB change, and the predecoded block designating signal BS (bs) for designating a control gate block also changes in accordance with the latched internal address signal. After the control gate CGL is driven to the selected state (sel), the reset control signal CKSAEF is driven to the active state by delay portion 44 , and thereafter, the sense amplifier activating signal SAE is activated. After a prescribed time period, the reset signal CKSAEF from delay portion 44 attains to the L level and the sense amplifier activating signal SAE is inactivated.
Even when the reset control signal CKSAEF is generated (activated) from delay portion 44 , the reset signals XRST and YRRST are fixed at the L level, and therefore, the states of selected control gate line CGL and selected subbit line do not change.
In the next cycle, when the internal address signal IADD changes, again, the control gate block designating signal BS (bs) and the predecode signals XCLKA, XCLKB, YRAN and YRBN change in accordance with the new internal address signal. In accordance with such signal changes, the control gate line CGL is changed, and the selected subbit line is changed.
Therefore, when the test mode designating signal MTEST is set to the H level, the control gate line and the subbit line selection signal are switched in accordance with the internal address signal latched in accordance with the clock signal CKM (CLK). Therefore, it becomes possible to test the margin for the internal operation for the cycle time of main clock signal CKM.
When the internal address signal is latched and then, the clock signal CLM (CLK) is kept at the L level, the internal state is kept unchanged, and therefore, a control gate line CGL can be continuously maintained at the selected state, and therefore, a voltage stress acceleration test, for example, can be performed.
Thus, when the activation of reset signals YRST and XRST is inhibited using the test mode designating signal MTEST, it is possible to inhibit resetting of the control gate line selection signal and the subbit line selection signal in one read cycle. The test mode designating signal MTEST is generated from an internal control circuit such as a sequence controller (CPU), not shown, in accordance with an external command. Specific functions of the test mode designating signal MTEST will be described in detail later. Here, it is described simply as a signal for setting the test mode.
As described above, according to the fourth embodiment, the address latch circuit and the Y decode circuit are configured to be reset internally in the data read cycle, so that the internal state can be returned to the initial state with sufficient margin with respect to the next read cycle, and therefore, the next read cycle can be started at a faster timing.
Further, by inhibiting the reset operation in the test mode, the control gate line and the subbit line can be selected in a static manner, in accordance with an address signal applied in synchronization with the clock signal.
FIG. 20 schematically shows a construction of a data reading portion according to the fifth embodiment of the present invention. Referring to FIG. 20, corresponding to memory blocks (A and MBB), sense amplifier bands SKA and SKB are arranged, respectively. The sense amplifier bands SKA and SKB each include sense amplifiers SK 0 -SB 3 shown in FIG. 5. As will be described in detail later, one memory block is divided into four trains of memory mats, and two trains of sense amplifiers are arranged. Here, the propagation time of internal read data will be discussed, and therefore, a construction in which a sense amplifier band is arranged for each memory block is shown as a representative example.
A read main bit line group RMBL is arranged common to sense amplifier bands SKA and SKB, and the data amplified by sense amplifier circuits in sense amplifier band SKA or SKB are transmitted through main bit line group RMBL to output latch circuit 6 . By way of example, the read main bit line group RMBL includes, for transmitting 64-bit data and 7-bit ECC code in parallel, read main bit lines rmbl < 0 >-rmbl < 70 > of 71 bits.
Sense amplifier bands SKA and SKB have their subbit line precharge/equalize and sensing operations controlled in accordance with a precharge end enable signal, pcend, and the sense amplifier activating signal SAE applied from sense amplifier control circuits 60 A and 60 B, respectively. Sense amplifier control circuits 60 A and 60 B also generate a monitor signal MSAE in synchronization with the sense amplifier activating signal SAE and transmit the monitor signal MSAE to output control circuit 7 , through a monitor signal line 62 . Monitor signal line 62 has the same load as read main bit line RMBL, and the monitor signal MSAE reflects the state of propagation of the internal read data to output latch circuit 6 .
In accordance with the monitor signal MSAE, output control circuit 7 outputs an output reset signal QRST including a buffer reset signal, rstqbn, and a main bit line precharge designating signal, mblpcn, for resetting output latch circuit 6 . Consequently, even if the propagation time of internal read data varies dependent on the position of the selected memory cell (dependent on the position of the activated sense amplifier band), the operation of output latch circuit 6 can be controlled accurately in accordance with the state of propagation of the internal read data.
FIG. 21 schematically shows an operation of the internal data reading portion shown in FIG. 20. In the following, an operation of the internal data reading portion shown in FIG. 20 will be described with reference to FIG. 21.
Sense amplifier control circuit 60 A or 60 B activates the sense amplifier activating signal SAE, to activate the sense amplifier circuit of the corresponding sense amplifier band SKA or SKB. In the activated sense amplifier band SKA or SKB, the sense amplifier circuits perform a sensing operation, amplifying the data read from the memory cells. Based on the amplified data, the read main bit line group RMBL is driven, so that its potential changes. To the read main bit line group RMBL, differential signals reflecting the outputs of the sense amplifier circuits are transmitted, as will be described later.
In synchronization with activation of the sense amplifier activating signal SAE, the monitor signal MSAE is generated (activated) from sense amplifier control circuit 60 A or 60 B and outputted to monitor signal line 62 . After a prescribed time period from activation of the transmitted monitor signal MSAE, output control circuit 7 activates the reset signal QRST, and the latch data of output latch circuit 6 is reset.
The monitor signal line 62 has the same signal propagation time as the data propagation time of sense output line (Ibk, Ibj) as the internal read data transmission line and of the read main bit line group RMBL. The monitor signal MSAE and the sense amplifier activating signal SAE are output from the same circuit. Therefore, the monitor signal MSAE and the internal read data sensed and amplified by the sense amplifier circuit and transmitted on read main bit line group RMBL have substantially the same flight time. Therefore, output control circuit 7 can accurately monitor the state of propagation of the internal read data, using the monitor signal MSAE. By controlling the operation of output latch circuit 6 based on the monitor signal MSAE, it becomes possible to drive the output latch circuit 6 to the reset state accurately, after the read data is latched in output latch circuit 6 and the internal data is transferred to the ECC circuit.
Specifically, dependent on the position of the selected memory block, propagation time of the internal read data to output latch circuit 6 varies. Therefore, if the circuit were reset at a faster timing, the internal read data would be reset and inverted before it reaches and latched by output latch circuit 6 . However, by using the monitor signal MSAE, the margin for the reset timing of each data transfer can be ensured, and thus, undesired inversion of the read data caused by resetting of the output latch circuit 6 during data reading can be prevented.
More specifically, the distance between output latch circuit 6 and sense amplifier band SKA or SKB is different, and therefore, the time necessary for the read data from the selected memory block (or sense amplifier column) to reach the output latch circuit 6 is different. When resetting of output latch circuit 6 is controlled by using the monitor signal MSAE, the data holding time can be made constant, regardless of the position of the selected memory block, in output latch circuit 6 .
By the resetting operation in accordance with the state of internal data reading of output latch circuit 6 , the data holding period of time and the margin for the reset timing of output latch circuit 6 can be made constant, regardless of the position of the selected memory block, whereby accurate data reading becomes possible. Further, by the resetting of the read main bit line and output latch circuit 6 , the internal state can be returned to the initial state at a fast timing for the next read cycle, to be ready for the next reading operation.
FIG. 22 specifically shows a construction of a portion related to 1 bit data reading of the internal data reading portion shown in FIG. 20. In sense amplifier band SKA, there are provided a sense amplifier SAA and a read buffer 70 A driving read main bit lines rmblk and rmblj in accordance with output signal lines (sense output lines) Ibj and Ibk of the sense amplifier SAA.
In sense amplifier band SKB, there are provided a sense amplifier SAB, and a read buffer 70 B driving read main bit lines rmblk and rmblj in accordance with an output signal from sense amplifier SAB. Read main bit lines rmblk and rmblj form the read main bit line rmbl <m>, and transmit complementary data.
Output latch circuit 6 includes an output latch 72 latching the internal read data on read main bit line rmbl <m>, and output buffer 74 generating a single end internal output data q <m> from output latch 72 .
The reset signal QRST includes a read main bit line precharge signal mblpc applied to output latch 72 , and a buffer reset signal rstqdbn applied to output buffer 74 .
Read buffers 70 A and 70 B have the same construction, and therefore, only the specific construction of read buffer 70 A is shown in FIG. 22.
Read buffer 70 A includes: gate circuits 70 a and 70 b buffering and transmitting signals transmitted from sense amplifier SAA to sense output lines (internal data read line) Ibj and Ibk when an inverted signal, saeba, of sense amplifier activating signal, saea, is activated (L level); p channel MOS transistors 70 c and 70 f rendered conductive in response to activation of the sense amplifier activating signal saeba; a p channel MOS transistor 70 d rendered conductive when an output signal from gate circuit 70 a is at the L level, for coupling P channel MOS transistor 70 c to the read main bit line rmblk; an N channel MOS transistor 70 e rendered conductive when an output signal from gate circuit 70 a is at the H level, for coupling the read main bit line rmblk to the ground voltage VSS; a p channel MOS transistor 70 g rendered conductive when an output signal from gate circuit 70 b is at the L level, for coupling MOS transistor 70 f to the read main bit line rmblj; and an n channel MOS transistor 70 h rendered conductive when an output signal of gate circuit 70 b is at the H level for coupling the read main bit line rmblj to the ground voltage VSS.
Gate circuits 70 a and 70 b output a signal of L level, when the sense amplifier activating signal saeba is inactive (H level). At this time, MOS transistors 70 d and 70 g are on, while MOS transistors 70 c and 70 f are off, so that read buffer 70 A is at an output high impedance state.
When the sense amplifier activating signal saeba is activated (attains to the L level), MOS transistors 70 c and 70 f turn on, MOS transistors 70 d and 70 e form a CMOS inverter, and MOS transistors 70 g and 70 h form another CMOS inverter. Gate circuits 70 a and 70 b operate as a buffer circuit, and respectively output the buffered signals of the signals transmitted from sense amplifier SAA to sense output lines Ibj and Ibk.
By MOS transistors 70 d and 70 e, the output signal of gate circuit 70 a is inverted and transmitted to read main bit line rmblk, and by MOS transistors 70 g and 70 h, the output signal of gate circuit 70 b is inverted and transmitted to read main bit line rmblj.
In the sensing operation of sense amplifier band SKA, the sense amplifier activating signal saebb for sense amplifier band SKB is inactive, and read buffer 70 B is at the output high impedance state. Therefore, the output data of read buffer 70 A is transmitted over read main bit line rmbl <m> to output latch 72 .
On the contrary, when sense amplifier band SKB is in operation, sense amplifier band SKA is inactive, and read buffer 70 A is kept at the output high impedance state.
FIG. 23 schematically shows the constructions of sense amplifier control ci