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The present continuation application claims the benefit of priority under 35 U.S.C. §120 application Ser. No. 11/171,316, filed Jul. 1, 2005, and under 35 U.S.C. §119 from Japanese Patent Application No. 2004-196159, filed on Jul. 2, 2004, the entire contents of both are incorporated herein by reference.
The present invention relates to a semiconductor device including a current mirror circuit.
A current multiplication circuit using a current mirror circuit has been widely used as a constant current circuit for use of a bias circuit requiring a large output current or an active load. A conventional current multiplication circuit is disclosed in Japanese Patent Publication (Kokai) No. 11-234135.
In the current multiplication circuit disclosed in the Publication, a plurality of output transistors of a current mirror circuit are connected in parallel so that the output current may have a desired value.
In a portable device typified by a cellular phone, it has been required at a transmission output stage that a bias current circuit covers an output current (a bias current) having a dynamic range of two to three digits. Furthermore, in such an application, there is a limitation that, in order to suppress switching noises to be produced at the time a bias current is switched, it is necessary to avoid turning on and off a plurality of output transistors of a bias current circuit simultaneously. Therefore, it is difficult to adopt a decode system to select an output transistor, so that it is necessary to connect output transistors of the number equivalent to required current steps in parallel.
However, in the conventional current multiplication circuit as described above, there has been an essential problem that a layout area increases in proportion to a ratio of an output current to a reference current. Particularly, a problem arises in the case where the output transistors connected in parallel are selected sequentially by means of switches in order to suppress the switching noises. The problem is that the layout area increases to the extent that the bias current circuit occupies a large portion of a core circuit, when the bias current circuit covers a wide dynamic range, for example, several hundreds μA to several tens mA.
According to an aspect of the present invention, a semiconductor device is provided which comprises a plurality of current mirror circuits respectively having an output terminal and a reference input terminal which is provided with a current having a different current value, a current output terminal connected to each of the output terminals of the current mirror circuits, and a control circuit to control output currents of the current mirror circuits.
FIG. 1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a graph showing a relation between steps and layout areas in the semiconductor device according to the embodiment of the present invention.
FIG. 3 is a block diagram showing a transmission output circuit using the semiconductor device according to the embodiment of the present invention.
An embodiment of the present invention will be described with reference to the accompanying drawings below.
FIG. 1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention. The semiconductor device generates a current value of fifteen steps increasing exponentially. The semiconductor device is provided with three current mirror circuits CM 11 to CM 13 and control circuit C. The current mirror circuits CM 11 to CM 13 include reference transistors Q 21 to Q 23 , output transistors Q 1 to Q 15 and switching elements S 2 to S 15 . The control circuit C provides control signal CONT of 14 bits to the switching elements S 2 to S 15 . The reference transistors Q 21 to Q 23 and the output transistors Q 1 to Q 15 are an N-channel type transistor, for example, a N-channel type MOS FET.
The reference input terminals of the current mirror circuits CM 11 to CM 13 are respectively provided with reference currents Iref 1 to Iref 3 having different current values.
The reference current Iref 1 is provided to the reference input terminal R 11 of the current mirror circuit CM 11 . The current mirror circuit CM 11 has an output terminal T 11 connected to a current output terminal OUT.
The reference current Iref 2 is provided to the reference input terminal R 12 of the current mirror circuit CM 12 . The current mirror circuit M 12 has an output terminal T 12 connected to the current output terminal OUT.
The reference current Iref 3 is provided to the reference input terminal R 13 of the current mirror circuit CM 13 . The current mirror circuit CM 13 has an output terminal T 13 connected to the current output terminal OUT.
The current mirror circuit CM 11 includes the reference transistor Q 21 connected to the reference input terminal R 11 , and the five output transistors Q 1 to Q 5 connected to the output terminal T 11 .
Drain and gate terminals of the output transistor Q 21 are connected to the reference input terminal R 11 of the current mirror circuit CM 11 . A source terminal of the output transistor Q 21 is connected to a power supply (hereinafter referred to as “Vss”).
The drain terminal of the output transistor Q 1 is connected to the output terminal T 11 of the current mirror circuit CM 11 . The gate terminal of the output transistor Q 1 is connected to the drain terminal of the reference transistor Q 21 . The source terminal of the output transistor Q 1 is connected to the Vss.
The drain terminal of the output transistor Q 2 is connected to the output terminal T 11 of the current mirror circuit CM 11 . The gate terminal of the output transistor Q 2 is connected to the drain terminal of the reference transistor Q 21 through the switching element S 2 . The source terminal of the output transistor Q 2 is connected to the Vss.
The output transistors Q 3 to Q 5 are connected to the output terminal T 11 , the switching elements S 3 to S 5 , the drain terminal of the reference transistor Q 21 and the Vss respectively as in the case of the output transistor Q 2 . Gate terminals of the output transistors Q 3 to Q 5 are respectively connected to a drain terminal of the reference transistor Q 21 through the switching elements S 3 to S 5 .
The switching elements S 2 to S 5 are turned ON/OFF based on a control signal CONT of 14 bits being provided from a control circuit C to switch a mirror ratio. By the control signal CONT [2:5], value of a mirror current flowing through the output terminal T 11 of the current mirror circuit CM 11 is controlled.
The expression “control signal CONT [2:5]” implies that four bits among a control signal CONT [2:15] of 14 bits are used to control the switching elements S 2 to S 5 . The same is applied to the expressions “CONT [6:10]” and “CONT [11:15]” which will be described hereinafter.
The current mirror circuit CM 12 includes a reference transistor Q 22 connected to the reference input terminal R 12 and the five output transistors Q 6 to Q 10 connected to the output terminal T 12 .
Drain and gate terminals of the reference transistor Q 22 are connected to the reference input terminal R 12 of the current mirror CM 12 . The source terminal of the output transistor Q 22 is connected to the Vss.
A drain terminal of the output transistor Q 6 is connected to the output terminal T 12 of the current mirror circuit CM 12 . The gate terminal of the output transistor Q 6 is connected to the drain terminal of the reference transistor Q 22 through the switching element S 6 . The source terminal of the output transistor Q 6 is connected to the Vss.
The output transistors Q 7 to Q 10 are connected to the output terminal T 12 , the switching elements S 7 to S 10 , the drain terminal of the reference transistor Q 22 and the Vss respectively as in the case of the output transistor Q 6 . The gate terminals of the output transistors Q 7 to Q 10 are respectively connected to the drain terminal of the reference transistor Q 22 through the switching elements S 7 to S 10 .
The switching elements S 6 to S 10 are turned ON/OFF based on the control signal CONT [6:10]. By the control signal CONT [6:10], value of a mirror current flowing through the output terminal T 12 of the current mirror circuit CM 12 is controlled.
The current mirror circuit CM 13 includes the reference transistor Q 23 connected to the reference input terminal R 12 and the five output transistors Q 11 to Q 15 connected to the output terminal T 13 .
A structure of the current mirror circuit CM 13 is the same as that of the current mirror circuit CM 12 . The gate terminals of the output transistors Q 11 to Q 15 are connected to the drain terminal of the reference transistor Q 23 via the switching elements S 11 to S 15 . The switching elements S 11 to S 15 are turned ON/OFF based on the control signal CONT [11:15]. By the control signal CONT [11:15], value of a mirror current flowing through the output terminal T 13 of the current mirror circuit CM 13 is controlled.
Table 1 shows examples of sizes of the transistors and current values flowing through the output transistors Q 1 to Q 15 shown in FIG. 1.
| TABLE 1 | ||||
| Reference | Output | Size | Current Value | |
| Current (mA) | transistor | Ratio | (mA) | |
| 0.1 | Q1 | 1.00 | 0.1 | |
| (Iref1) | Q2 | 1.41 | 0.141 | |
| Q3 | 2.00 | 0.2 | ||
| Q4 | 2.83 | 0.283 | ||
| Q5 | 4.00 | 0.4 | ||
| 0.4 | Q6 | 1.41 | 0.566 | |
| (Iref2) | Q7 | 2.00 | 0.8 | |
| Q8 | 2.83 | 1.131 | ||
| Q9 | 4.00 | 1.6 | ||
| Q10 | 5.66 | 2.263 | ||
| 1.6 | Q11 | 2.00 | 3.2 | |
| (Iref3) | Q12 | 2.83 | 4.525 | |
| Q13 | 4.00 | 6.4 | ||
| Q14 | 5.66 | 9.051 | ||
| Q15 | 8.00 | 12.8 | ||
In Table 1, the sizes of the output transistors Q 1 to Q 15 are represented by a ratio at the time when sizes of the output transistors Q 21 to Q 23 are set to 1. Accordingly, the respective current values flowing through the output transistors Q 1 to Q 15 are (reference current)×(size ratio) when the output transistors Q 1 to Q 15 are in an ON state. Here, the reference current is each of Iref 1 to Iref 3 .
For example, the current value flowing through the output transistor Q 13 is 1.6 mA×4.00 (=6.4 mA) when the output transistor Q 13 is in an ON state, as shown in Table 1.
An operation of the semiconductor device having the above described structure will be described.
The turning ON/OFF of the output transistors Q 2 to Q 15 is controlled based on the control signal CONT. The output transistors which have been turned ON generate mirror currents corresponding to the size ratios of the output transistors Q 2 to Q 15 at the output terminals T 11 to T 13 .
Since the output terminals T 11 to T 13 of the current mirror circuits CM 11 to CM 13 are connected to the current output terminal OUT, the total sum of the mirror currents, which are generated by the output transistors in an ON state, flows through the OUT as a bias current Ibias to apply to a power amplifier, for example.
Table 2 shows a relation between a bias current Ibias and the sum of the layout areas of the output transistors in an ON state in each step corresponding to the number of the output transistors which are in an ON state.
| TABLE 2 | ||
| bias | ||
| current | Layout Area | |
| Step | Ibias (mA) | (μm 2 ) |
| 1 | 0.1 | 1.00 |
| 2 | 0.241 | 2.41 |
| 3 | 0.441 | 4.41 |
| 4 | 0.724 | 7.24 |
| 5 | 1.124 | 11.24 |
| 6 | 1.69 | 12.66 |
| 7 | 2.49 | 14.66 |
| 8 | 3.621 | 17.49 |
| 9 | 5.221 | 21.49 |
| 10 | 7.484 | 27.14 |
| 11 | 10.684 | 29.14 |
| 12 | 15.21 | 31.97 |
| 13 | 21.61 | 35.97 |
| 14 | 30.661 | 41.63 |
| 15 | 43.461 | 49.63 |
Herein, the ON/OFF states of the switching elements S 2 to S 15 correspond uniquely to each state of the steps. The state transition from a step to another step always occurs one by one. In other words, the number of the output transistors Q 2 to Q 15 in ON or OFF state increases or decreases one by one. Each of the output transistors Q 2 to Q 15 is turned on or off in a predetermined order.
The output transistors Q 2 to Q 15 are turned on or off one after adjacent another. In the semiconductor device, time intervals are provided among the switching timings of the output transistors Q 2 to Q 15 .
As shown in Table 2, the states of the steps maybe regarded as a one-dimensional sequence. Accordingly, the state transition is always limited to that transiting to an adjacent state. Turning ON/OFF of the switching elements S 2 to S 15 is selective, and more than one transition is not performed simultaneously. This is because switching noises at the time of switching the bias current Ibias is suppressed as possible.
For example, the step 8 corresponds to the operation of the switching element S 8 . When the step transits from the state 7 to the state 8 , the switching element S 8 is turned ON. When the step transits from the state 8 to the state 7 , the switching element S 8 is turned OFF.
Furthermore, when the step transits from the state 8 to the state 9 , or when the step transits from the state 9 to the state 8 , the switching element S 8 keeps its ON state.
Accordingly, when the step takes the state 8 , all of the switching elements S 2 to S 8 are in an ON state, and all of the switching elements S 9 to S 15 are in an OFF state. Therefore, bias current Ibias is the total sum of the mirror currents flowing through the output transistors Q 1 to Q 8 .
As shown in Table 1, the transistor sizes of the output transistors Q 1 to Q 5 , the transistor sizes of the output transistors Q 6 to Q 10 , and the transistor sizes of the output transistors Q 11 to Q 15 are set so as to form a geometric progression. The reference currents Iref 1 to Iref 3 are also set so as to form a geometrical progression.
Accordingly, the bias current Ibias increases geometrically in accordance with the increase of the number of the step as follows.
Ibias=0.1×Σ2 (s−1)/2 (mA) (1)
where s is a number indicating the state of the step shown in Table 2.
Furthermore, since the three reference currents having the different current values, that is, Iref 1 equals to 0.1 mA, Iref 2 equals to 0.4 mA and Iref 3 equals to 1.6 mA, are used in the semiconductor device according to the embodiment of the present invention, it is possible to suppress the sum of the layout areas of the output transistors drastically.
FIG. 2 is a graph showing a suppression effect of the layout area in the semiconductor device according to the embodiment of the present invention.
In FIG. 2, the solid line indicates the layout area of the embodiment, and the dashed line indicates a layout area of a conventional semiconductor device having the equal dynamic range and the equal number of steps. The horizontal axis represents numbers indicating the states of the step shown in Table 2, and the vertical axis represents the total sum of the layout areas of the output transistors which are in the an ON state in the respective steps.
From this graph, according to the embodiment, it is seen that the layout area can be reduced approximately to 1/10 compared with the conventional circuit structure having the dynamic range equal to the embodiment of the present invention. The reduction of the layout area may arise because different reference currents are employed in the embodiment.
According to the above described embodiment, since the size of the output transistor occupying the large part of the layout area may be suppressed drastically, it is possible to realize the semiconductor device having a wide dynamic range of output current while increase of the layout area is suppressed.
Furthermore, according to the embodiment, since more than one transistor is not turned ON/OFF simultaneously, it is possible to reduce the switching noises at the time of switching of the output current drastically.
FIG. 3 is a block diagram showing a transmission output circuit using the semiconductor device according to the embodiment of the present invention.
In FIG. 3, a power is provided to a transmission output circuit 33 from an alternate power supply 31 . The transmission output circuit 33 may be a power amplifier. The transmission output circuit 33 provides an output signal to an external antenna 32 . The gain of the transmission output circuit 33 is controlled by a bias current circuit 34 . By adopting this embodiment as the bias current circuit 32 , it is possible to realize the transmission output circuit having a wide output dynamic range while increase of the layout area is suppressed.
In the foregoing embodiment, the circuit example is shown, which realizes the bias current Ibias shown in equation (1) with the 15 steps. The present invention is not limited to this, and the present invention may be applicable to any semiconductor device principally as long as the semiconductor device is a current circuit simulating a monotonously increasing function. The output of the current output terminal OUT may be utilized as various currents other than the bias current. Furthermore, though the number of the output transistors of each of the current mirror circuits CM 11 to CM 13 is set to five, the present invention is not limited to this.
Furthermore, in the foregoing embodiment, though the three reference currents Iref 1 to Iref 3 which are quadruple to each other are used, the present invention is not limited to this. It is possible to mount a semiconductor device based on a bias current value to be targeted, the number of the steps and the layout area to be achieved.
Though the output transistor Q 1 is always made to be turned ON irrespective of the state of the step, the present invention is not limited to this. The output transistor Q 1 may be connected to Iref 1 through a switching element as in the case of other output transistors. The output transistors Q 2 to Q 15 may be controlled by using switches to be provided in the control circuit C andwhich are controlledby the control signal, instead of switch elements S 2 to S 15 .