DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment

[0035] FIG. 1 is a top plan view showing a structure of a semiconductor device according to a first preferred embodiment of the present invention. Element forming regions AR 1 and AR 2 having a substantially H-shaped upper surface structure are defined by an element isolating insulation film 4 . The element forming regions AR 1 and AR 2 are spaced apart from each other and aligned along a Y direction.

[0036] In the element forming region AR 1 , a first transistor is formed that has a source region 1 S, a drain region 1 D, a doped channel region 1 C, and a gate structure 3 . Likewise, in the element forming region AR 2 , a second transistor is formed that has a source region 2 S, a drain region 2 D, a doped channel region 2 C, and the gate structure 3 . In the example shown in FIG. 1 , the gate structure 3 that the first transistor has and the gate structure 3 that the second transistor has are connected to each other. The first and second transistors are, for example, memory cell transistors of a DRAM, transistors constituting a peripheral circuit thereof, or transistors constituting a logic circuit thereof. In the following, an example in which the first and second transistors are both N-channel MOSFETs is described.

[0037] The source region 1 S, the doped channel region 1 C, and the drain region 1 D are aligned in that order along an X direction. Likewise, the source region 2 S, the doped channel region 2 C, and the drain region 2 D are aligned in that order along the X direction. The source region 1 S and the source region 2 S, the doped channel region 1 C and the doped channel region 2 C, and the drain region 1 D and the drain region 2 D, are each mutually spaced apart and aligned along the Y direction. An interval W 1 between the doped channel region 1 C and the doped channel region 2 C is wider than an interval W 2 between the source region 1 S and the source region 2 S and the interval W 2 between the drain region 1 D and the drain region 2 D.

[0038] FIG. 2 depicts cross-sectional views showing a cross-sectional structure of the semiconductor device shown in FIG. 1 . In FIG. 2 , views (A), (B), and (C) show the cross-sectional structures taken along the lines IIA-IIA, IIB-IIB, and IIC-IIC shown in FIG. 1 , respectively.

[0039] FIGS. 3 and 5 to 11 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to the first preferred embodiment. The views (A) to (C) in each of the figures correspond to the views (A) to (C) of FIG. 2 , respectively.

[0040] First, referring to FIG. 3 , a silicon oxide film and a silicon nitride film are formed in that order entirely on an upper surface of an n-type silicon substrate 10 . It should be noted, however, that a silicon oxynitride film may be formed in place of the silicon oxide film. Alternatively, in place of the silicon nitride film, a polysilicon film or a layered film of a silicon nitride film and a polysilicon film may be formed. Next, by patterning these films, a silicon oxide film 20 and a silicon nitride film 21 are formed. Subsequently, using the silicon nitride film 21 as an etch mask, the silicon substrate 10 is etched away by a predetermined film thickness using an anisotropic dry etching technique. This forms a recessed portion 22 in the upper surface of the silicon substrate 10 . Then, using an oxidation furnace or a single wafer-type lamp oxidation apparatus, a silicon oxide film 13 having a film thickness of about several nanometers to several tens of nanometers is formed on the side surfaces and the bottom surface of the recessed portion 22 by a thermal oxidation technique at about 900 to 1150° C. This recovers crystal defects in the silicon substrate 10 that are produced by damages arising from the etching for forming the recessed portion 22 .

[0041] FIG. 4 is a top plan view showing a formation pattern of the silicon nitride film 21 corresponding to FIG. 1 . The silicon nitride film 21 that corresponds to the element forming region AR 1 (denoted by reference character 21 a in FIG. 4 ) has a first portion 21 ₁ , a second portion 21 ₂ , and a third portion 21 ₃ , which are connected in that order along the X direction. The silicon nitride film 21 a has a substantially H-shaped upper surface structure, and the dimension of the second portion 21 ₂ with respect to the Y direction is smaller than the dimensions of the first portion 21 ₁ and the third portion 21 ₃ with respect to the Y direction. Likewise, the silicon nitride film 21 that corresponds to the element forming region AR 2 (denoted by reference character 21 b in FIG. 4 ) has a fourth portion 21 ₄ , a fifth portion 21 ₅ , and a sixth portion 21 ₆ , which are connected in that order along the X direction. The silicon nitride film 21 b has a substantially H-shaped upper surface structure, and the dimension of the fifth portion 21 ₅ with respect to the Y direction is smaller than the dimensions of the fourth portion 21 ₄ and the sixth portion 21 ₆ with respect to the Y direction. The first portion 21 ₁ and the fourth portion 21 ₄ , the second portion 21 ₂ and the fifth portion 21 ₅ , and the third portion 21 ₃ and the sixth portion 21 ₆ are each mutually spaced apart and aligned along the Y direction. The recessed portion 22 has first to sixth side surfaces 10 A ₁ to 10 A ₆ defined by the silicon substrate 10 below the first to sixth portions 21 ₁ to 21 ₆ .

[0042] Subsequent to FIG. 3 , referring to FIG. 5 , ions 23 ₁ , 23 ₂ of a p-type impurity such as B, BF ₂ , or In are implanted at a concentration of about 1E11/cm ² to 1E14/cm ² in the Y direction from diagonally above, with the silicon oxide film 20 and the silicon nitride film 21 having been formed. The ion implantation is sequentially carried out in opposing directions +Y and −Y, as indicated by arrows Y 1 and Y 2 in FIG. 1 .

[0043] As for implant angle α of the ion implantation (that is, an angle formed by an implant direction of the impurity ions 23 ₁ and 23 ₂ and a direction of the normal to the upper surface of the silicon substrate 10 ), an implant angle is adopted that falls within a range that satisfies the relationship tan ⁻¹ (W 2 /T)<α≦tan ⁻¹ (W 1 /T), where W 2 represents an interval between the first portion 21 ₁ and the fourth portion 21 ₄ and an internal between the third portion 21 ₃ and the sixth portion 21 ₆ shown in FIG. 4 , W 1 is an interval between the second portion 21 ₂ and the fifth portion 21 ₅ , and T is a total film thickness of the silicon oxide film 20 and the silicon nitride film 21 .

[0044] When the implant angle a is controlled within that range, the impurity ions 23 ₁ and 23 ₂ are implanted through the silicon oxide film 13 in the second side surface 10 A ₂ and the fifth side surface 10 A ₅ shown in FIG. 4 . As a result, as shown in view (A) of FIG. 5 , p-type doped channel regions 5 ₁ and 5 ₂ are formed within the upper surface of the silicon substrate 10 that is in the element forming regions AR 1 and AR 2 , respectively. On the other hand, due to the shadowing effect of the silicon oxide film 20 and the silicon nitride film 21 , the impurity ions 23 ₁ and 23 ₂ are not implanted to the first side surface 10 A ₁ , the third side surface 10 A ₃ , the fourth side surface 10 A ₄ , and the sixth side surface 10 A ₆ that are shown in FIG. 4 . As a result, as shown in view (B) of FIG. 5 , the doped channel regions 5 ₁ and 5 ₂ are not formed.

[0045] Next, referring to FIG. 6 , a silicon oxide film 24 having such a film thickness that it can completely fill up the recessed portion 22 is entirely formed by a coating technique or a CVD technique using high density plasma. The silicon oxide film 24 may be doped with impurity such as F, P, or B.

[0046] Then, referring to FIG. 7 , the silicon oxide film 24 is polished by a CMP technique until an upper surface of the silicon nitride film 21 is exposed.

[0047] Subsequently, referring to FIG. 8 , in order to adjust the height of an upper surface of the element isolating insulation film 4 , the silicon oxide film 24 is removed by a desired film thickness using an aqueous solution of HF or the like. Next, the silicon nitride film 21 is removed using a hot phosphoric acid solution.

[0048] Then, referring to FIG. 9 , in order to form a CMOS transistor, an impurity such as B is ion-implanted into the silicon substrate 10 through the silicon oxide film 20 , thereby forming a p-type well region 11 . Reference numeral 11 in FIG. 9 represents a location in which the impurity concentration shows a peak in the well region. Subsequently, in order to improve isolation breakdown voltage, a p-type channel cut region 12 is formed by ion-implanting an impurity such as B, BF ₂ , or In into the silicon substrate 10 through the silicon oxide film 20 . Next, in order to adjust the threshold voltage of the transistors, an impurity such as B, BF ₂ , or In is ion-implanted at a concentration of about 1E11/cm ² to 1E14/cm ² into the silicon substrate 10 through the silicon oxide film 20 . Thus, p-type doped channel regions 1 C and 2 C are formed in the upper surface of the silicon substrate 10 . Thereafter, the impurities that have been ion-implanted in the silicon substrate 10 are activated by carrying out a heat treatment at about 800 to 1100° C. using a lamp annealing technique.

[0049] Next, referring to FIG. 10 , the silicon oxide film 20 is removed using an aqueous solution of HF or the like. Thus, the upper surface of the silicon substrate 10 that is in the element forming regions AR 1 and AR 2 is exposed. Also, a portion of the silicon oxide film 24 is removed to form a silicon oxide film 14 , thus forming a trench-shaped element isolating insulation film 4 having the silicon oxide films 13 and 14 . Subsequently, using an oxidation furnace at about 700 to 850° C., or a lamp oxidation apparatus at about 900 to 1100° C., silicon oxide films 15 ₁ and 15 ₂ functioning as gate insulating films are formed on the upper surface of the silicon substrate 10 that is in the element forming regions AR 1 and AR 2 . It should be noted that a silicon oxynitride film, or a layered film of a silicon oxide film and a silicon oxynitride film may be formed in place of the silicon oxide films 15 ₁ and 15 ₂ . Then, by a CVD technique or the like, a conductive film 16 is formed on the silicon oxide films 15 ₁ and 15 ₂ and on the element isolating insulation film 4 . The conductive film 16 is a polysilicon film, a metal film (W, Ti, Al, Cu, or the like), a metal silicide film, a metal nitride film, or a layered film thereof. Next, using a CVD technique or the like, a silicon nitride film 17 is formed on the conductive film 16 . It should be noted that a silicon oxide film, or a layered film of a silicon oxide film and a silicon nitride film may be formed in place of the silicon nitride film 17 .

[0050] Next, referring to FIG. 11 , the silicon nitride film 17 is patterned by a photolithography technique and an anisotropic dry etching technique. Then, using the silicon nitride film 17 as an etch mask, the conductive film 16 is etched by an anisotropic dry etching technique. The portion of the conductive film 16 that has not been etched away functions as a gate electrode. Next, using a lamp oxidation technique or a normal thermal oxidation technique, the conductive film 16 is oxidized or nitrided in a mixed gas atmosphere of O ₂ , NO, N ₂ O, NH ₃ , H ₂ , etc., to form an insulating film 18 .

[0051] Subsequently, using the silicon nitride film 17 as an implant mask, an impurity such as P, As, or Sb is ion-implanted so as to form n-type source regions 1 S and 2 S and n-type drain regions 1 D, 2 D in the upper surfaces of the silicon substrate 10 . With the manufacturing steps thus described, the structure shown in FIG. 2 is obtained.

[0052] As described above, in the method of manufacturing the semiconductor device according to the first preferred embodiment, the silicon oxide films 15 ₁ and 15 ₂ , which function as the gate insulating films, are formed in the step shown in FIG. 10 , after the doped channel regions 5 ₁ and 5 ₂ are formed in the step shown in FIG. 5 and then the doped channel regions 1 C and 2 C are formed in the step shown in FIG. 9 . Therefore, even if part of the impurity contained in the doped channel regions 5 ₁ , 5 ₂ , 1 C and 2 C are absorbed in the gate insulating films because of the heat treatment for forming the gate insulating films, it is possible to suppress reduction in the impurity concentration in the doped channel regions in comparison with the conventional manufacturing methods in which the doped channel regions 5 ₁ and 5 ₂ are not formed. As a consequence, reduction in the threshold voltages of the first and second transistors can be suppressed.

[0053] Moreover, as shown in FIG. 1 , the doped channel regions 5 ₁ and 5 ₂ are formed under the gate structure 3 and in the boundary portions between the element isolating insulation film 4 and the doped channel regions 1 C and 2 C; therefore, the inverse narrow width effect is effectively prevented from occurring.

[0054] Furthermore, in the step shown in FIG. 5 , the p-type impurity ions 23 ₁ , 23 ₂ are implanted in the Y direction from diagonally above, and in addition, the implant angle α of the ion implantation is controlled within the range tan ⁻¹ (W 2 /T)<α≦tan ⁻¹ (W 1 /T); therefore, of the first to sixth side surfaces 10 A ₁ to 10 A ₆ shown in FIG. 4 , only in the second side surface 10 A ₂ and the fifth side surface 10 A ₅ , the doped channel regions 5 ₁ and 5 ₂ are formed in a self-aligned manner. Consequently, reduction in the impurity concentrations in the n-type source regions 1 S and 2 S as well as the drain regions 1 D and 2 D because of the formation of the p-type doped channel regions 5 ₁ and 5 ₂ can be appropriately avoided.

Second Preferred Embodiment

[0055] The second preferred embodiment describes an example in which the invention according to the foregoing first preferred embodiment is applied to DRAM memory cells.

[0056] FIG. 12 depicts a top plan view showing a structure of a semiconductor device according to a second preferred embodiment of the present invention. FIG. 13 depicts a cross-sectional view showing a cross-sectional structure concerning a position along the line XIII-XIII shown in FIG. 12 . Referring to FIG. 12 , a plurality of element forming regions AR (represented by reference characters AR ₁₁ , AR ₁₂ , AR ₂₁ , AR ₃₁ , and AR ₃₂ in FIG. 12 ) are defined by the element isolating insulation film 4 . The element forming region AR ₁₁ and the element forming region AR ₃₁ , both of which belong to a common column in a memory cell array, and the element forming region AR ₁₂ and the element forming region AR ₃₂ , both of which belong to another common column, are each mutually spaced apart and aligned along the Y direction. The element forming region AR ₁₁ and the element forming region AR ₁₂ , both of which belong to a common row, and the element forming region AR ₃₁ and the element forming region AR ₃₂ , both of which belong to a common row, are each mutually spaced apart and aligned along the X direction. The element forming region AR ₂₁ is formed so that it is staggered with respect to the element forming region AR ₁₁ by half of the formation pitch of the element forming regions AR along the X direction. That is, a so-called half pitch cell is constructed.

[0057] Referring to FIGS. 12 and 13 , in each one of the element forming regions AR, two memory cell transistors are formed sharing a drain region 56 D. On the drain region 56 D, a contact plug 32 is formed that is connected to a bit line 48 . Contact plugs 30 and 31 respectively connected to polysilicon films 52 and 53 , which function as capacitor lower electrodes, are formed on respective source regions 5 S and 6 S. Since the half pitch cell is constructed, the source regions 5 S and 6 S formed in the element forming regions AR that belong to different rows are mutually spaced apart at an interval W 2 and aligned along the Y direction. The drain regions 56 D as well as doped channel regions 38 , 44 formed in the element forming regions AR that belong to different rows are mutually spaced apart at an interval W 1 that is wider than the interval W 2 and aligned along the Y direction.

[0058] In each of the element forming regions AR, doped channel regions 5 , which correspond to the doped channel regions 5 ₁ and 5 ₂ of the foregoing first preferred embodiment, are formed. As in the step shown in FIG. 5 , the doped channel regions 5 are formed by implanting p-type impurity ions 23 ₁ , 23 ₂ in the Y direction from diagonally above so that an implant angle α of the ion implantation controlled within a range tan ⁻¹ (W 2 /T)<α≦tan ⁻¹ (W 1 /T). Thus, the doped channel regions 5 are formed in the doped channel regions 38 and 44 and in the drain region 56 D, but are not formed in the source regions 5 S and 6 S. In the second preferred embodiment, for one example, the interval W 1 is about 370 nm, the interval W 2 is about 110 nm, and the film thickness T is about 120 nm.

[0059] FIGS. 15 through 19 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing the semiconductor device according to the second preferred embodiment. First, memory cell transistors shown in FIG. 15 are formed through similar manufacturing steps to those in the foregoing first preferred embodiment.

[0060] FIG. 14 is a top plan view showing a formation pattern of a silicon nitride film 21 when forming the element isolating insulation film 4 , corresponding to a portion of FIG. 12 . The silicon nitride film 21 corresponding to the element forming region AR ₁₁ (denoted by reference character 21 a in FIG. 14 ) has a first portion 21 ₁ , a second portion 21 ₂ , and a third portion 21 ₃ , which are connected in that order along the X direction. Likewise, the silicon nitride film 21 that corresponds to the element forming region AR ₂₁ (denoted by reference character 21 b in FIG. 14 ) has a fourth portion 21 ₄ , a fifth portion 21 ₅ , and a sixth portion 21 ₆ , which are connected in that order along the X direction. Likewise, the silicon nitride film 21 that corresponds to the element forming region AR ₃₁ (denoted by reference character 21 c in FIG. 14 ) has a seventh portion 21 ₇ , an eighth portion 21 ₈ , and a ninth portion 21 ₉ , which are connected in that order along the X direction.

[0061] The third portion 21 ₃ , the fourth portion 21 ₄ , and the ninth portion 21 ₉ correspond to the source regions 5 S and 6 S. The second portion 21 ₂ , the fifth portion 21 ₅ , and the eighth portion 21 ₈ correspond to the doped channel regions 38 and 44 . The first portion 21 ₁ , the sixth portion 21 ₆ , and the seventh portion 21 ₇ correspond to the drain region 56 D.

[0062] The third portion 21 ₃ , the fourth portion 21 ₄ , and the ninth portion 21 ₉ are spaced apart from each other and aligned in that order along the Y direction. The second portion 21 ₂ and the eighth portion 21 ₈ are spaced apart from each other and are aligned along the Y direction. The first portion 21 ₁ and the seventh portion 21 ₇ are spaced apart from each other and are aligned along the Y direction. The second portion 21 ₂ and the fifth portion 21 ₅ are not aligned along the Y direction, and the first portion 21 ₁ and the sixth portion 21 ₆ are not aligned along the Y direction either. The recessed portion 22 has first to ninth side surfaces 10 A ₁ to 10 A ₉ that are defined by the silicon substrate 10 below the first to ninth portions 21 ₁ to 21 ₉ , respectively.

[0063] In a similar manner to the manufacturing step shown in FIG. 5 , the doped channel regions 5 are formed by implanting p-type impurity ions 23 ₁ , 23 ₂ in the Y direction from diagonally above while an implant angle α of the ion implantation is controlled within a range tan ⁻¹ (W 2 /T)<α≦tan ⁻¹ (W 1 /T), with the silicon oxide film 20 and the silicon nitride film 21 having been formed. As a result, the doped channel regions 5 are formed, of the second side surface 10 A ₂ and the third side surface 10 A ₃ , only in the second side surface 10 A ₂ , of the fourth side surface 10 A ₄ and the fifth side surface 10 A ₅ , only in the fifth side surface 10 A ₅ , and of the eighth side surface 10 A ₈ and the ninth side surface 10 A ₉ , only in the eighth side surface 10 A ₈ .

[0064] Referring to FIG. 15 , after a transistor structure similar to that of FIG. 2 is obtained, a silicon nitride film is entirely formed by a CVD technique. Next, the silicon nitride film is etched back by an anisotropic dry etching technique, thereby forming sidewalls 37 and 43 . This provides gate structures 3 ₅ and 3 ₆ having silicon oxide films 33 and 39 , conductive films 34 and 40 , silicon nitride films 35 and 41 , insulating films 36 and 42 , and the sidewalls 37 and 43 , respectively.

[0065] Next, referring to FIG. 16 , a silicon oxide film 44 doped with an impurity such as B or P is entirely formed by a coating technique or a CVD technique so as to cover the gate structures 3 ₅ and 3 ₆ . Subsequently, annealing is performed in an O ₂ , N ₂ , or H ₂ atmosphere. Then, contact holes respectively connected to the source regions 5 S, 6 S and the drain region 56 D are formed in the silicon oxide film 44 by a photolithography technique and an anisotropic dry etching technique. Thereafter, contact plugs 30 to 32 respectively connected to the source regions 5 S, 6 S and the drain region 56 D are formed by filling up the contact holes with a polysilicon film doped with an impurity such as P, As, or Sb.

[0066] Next, referring to FIG. 17 , a silicon oxide film 45 is entirely formed by a CVD technique. Then, a contact hole connected to the contact plug 32 is formed in the silicon oxide film 45 by a photolithography technique and an anisotropic dry etching technique. Thereafter, a bit line 48 connected to the contact plug 32 is formed by filling up the contact hole with a barrier metal film 46 of TiN, TaN, WN, TiSi ₂ , COSi ₂ or the like, and a metal film 47 of W, Ti, Cu, Al, or the like.

[0067] Subsequently, referring to FIG. 18 , a silicon oxide film 49 is entirely formed by a CVD technique. Then, contact holes respectively connected to the contact plugs 30 and 31 are formed in the silicon oxide films 45 and 49 by a photolithography technique and an anisotropic dry etching technique. Next, contact plugs 50 and 51 respectively connected to the contact plugs 30 and 31 are formed by filling the contact holes with a polysilicon film doped with an impurity such as P, As, or Sb. Depending upon the material of which a later-formed capacitor lower electrode is formed, the material of the contact plugs 50 and 51 may be Ti, W, TiN, WN, TaN, or the like.

[0068] Then, referring to FIG. 19 , a silicon oxide film 56 is entirely formed by a CVD technique. Thereafter, recesses respectively connected to contact plugs 50 and 51 are formed in the silicon oxide film 56 by a photolithography technique and an anisotropic dry etching technique. Subsequently, a polysilicon film doped with an impurity such as P, As, or Sb is entirely formed by a CVD technique. Then, the polysilicon film is polished by a CMP technique until an upper surface of the silicon oxide film 56 is exposed. This forms polysilicon films 52 and 53 respectively connected to the contact plugs 50 and 51 . The polysilicon films 52 and 53 function as capacitor lower electrodes. It should be noted, however, that a metal film of Ti, W, TiN, WN, Pt, Ru, or the like may be formed in place of the polysilicon films 52 and 53 .

[0069] Next, the silicon oxide film 56 is removed by an etching technique using HF. It should be noted, however, that a lower portion of the silicon oxide film 56 may be left unremoved in order to prevent the polysilicon films 52 and 53 from collapsing due to mechanical stress during the process. Subsequently, an insulating film 54 of SiO ₂ , Si ₃ N ₄ , Ta ₂ O ₅ , Al ₂ O ₃ , HfO, or the like is entirely formed. The insulating film 54 functions as a capacitor dielectric film. Then, a conductive film 55 of polysilicon, Ti, W, TiN, WN, Pt, Ru, or like is entirely formed. The conductive film 55 functions as a capacitor upper electrode. With the manufacturing steps described above, a structure shown in FIG. 13 is obtained.

[0070] Thus, with the method of manufacturing the semiconductor device according to the second preferred embodiment, it is possible to suppress reduction in the threshold voltage of memory cell transistors and the occurrence of the inverse narrow width effect, for the same reasons as those in the foregoing first preferred embodiment.

[0071] Moreover, because the doped channel regions 5 are not formed in the source regions 5 S and 6 S, the n-type source regions 5 S and 6 S do not suffer from reduction in the impurity concentration arising from the formation of the p-type doped channel regions 5 . Therefore, the contact resistance between the respective source regions 5 S, 6 S and the contact plugs 30 , 31 do not increase, and consequently, degradation in data write characteristics can be avoided. Furthermore, degradation in refresh characteristics can be avoided because the electric field strength of the source regions 5 S and 6 S does not become high.

Third Preferred Embodiment

[0072] FIGS. 20 and 21 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a third preferred embodiment of the present invention. First, a structure shown in FIG. 8 is obtained through the manufacturing steps similar to those in the foregoing first preferred embodiment. Next, the silicon oxide film 20 is removed using an aqueous solution of HF or the like. Then, referring to FIG. 20 , the silicon oxide films 151 and 152 functioning as the gate insulating film are formed on the upper surface of the silicon substrate 10 that is in the element forming regions AR 1 and AR 2 . Subsequently, the conductive film 16 is formed on the silicon oxide films 15 ₁ and 15 ₂ as well as on the element isolating insulation film 4 by a CVD technique or the like. Thereafter, the silicon nitride film 17 is formed on the conductive film 16 by a CVD technique or the like.

[0073] Next, referring to FIG. 21 , an impurity such as B is ion-implanted into silicon substrate 10 through the silicon nitride film 17 , the conductive film 16 , and the silicon oxide film 15 ₁ and 15 ₂ . This forms a p-type well region 11 . Then, an impurity such as B, BF ₂ , or In is ion-implanted into the silicon substrate 10 through the silicon nitride film 17 , the conductive film 16 , and the silicon oxide films 15 ₁ and 15 ₂ . This forms the p-type channel cut region 12 . Subsequently, an impurity such as B, BF ₂ , or In is ion-implanted into the silicon substrate 10 through the silicon nitride film 17 , the conductive film 16 , and the silicon oxide films 15 ₁ and 15 ₂ . This forms the p-type doped channel regions 1 C and 2 C. Thereafter, the above-mentioned impurities that have been ion-implanted in the silicon substrate 10 are activated by carrying out a heat treatment.

[0074] Next, the silicon nitride film 17 is patterned by a photolithography technique and an anisotropic dry etching technique. Subsequently, using the silicon nitride film 17 as an etch mask, the conductive film 16 is etched by an anisotropic dry etching technique. Then, an insulating film 18 is formed by oxidizing the conductive film 16 with a lamp oxidation technique or the like. Thereafter, the n-type source regions 1 S and 2 S as well as the n-type drain regions 1 D and 2 D are formed in the upper surface of the silicon substrate 10 by ion-implanting an impurity such as P, As, or Sb using the silicon nitride film 17 as an implant mask. With the manufacturing steps described above, a structure shown in FIG. 2 is obtained.

[0075] As described above, in the method of manufacturing the semiconductor device according to the third preferred embodiment, the silicon oxide films 15 ₁ and 15 ₂ , which function as the gate insulating films, are formed in the manufacturing step shown in FIG. 20 . Thereafter, the doped channel regions 1 C and 2 C are formed in the manufacturing step shown in FIG. 21 . Consequently, the impurity contained in the doped channel regions 1 C and 2 C is not absorbed in the gate insulating films by the heat treatment for forming the gate insulating films. As a result, it is possible to avoid the reduction in threshold voltage and the occurrence of the inverse narrow width effect that are caused by reduction in the impurity concentration in the doped channel regions 1 C and 2 C.

[0076] Accordingly, when forming the doped channel regions 1 C and 2 C, it is unnecessary to ion-implant a p-type impurity at a higher concentration than a desired value; therefore, it is possible to avoid degradations in data write characteristics and refresh characteristics.

[0077] It should be noted that in the third preferred embodiment, the above-described advantageous effects may be obtained even without forming the doped channel regions 5 ₁ and 5 ₂ , but it is more effective if the doped channel regions 5 ₁ and 5 ₂ are formed.

Fourth Preferred Embodiment

[0078] FIGS. 22 and 23 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a fourth preferred embodiment of the present invention. First, a structure shown in FIG. 15 is obtained through the manufacturing steps similar to those in the foregoing second preferred embodiment. Next, referring to FIG. 22 , a silicon oxide film 44 is entirely formed by a CVD technique or the like so as to cover the gate structures 3 ₅ and 3 ₆ . Subsequently, contact holes 60 , 62 , and 61 respectively connected to the source regions 5 S and 6 S and the drain region 56 D are formed in the silicon oxide film 44 by a photolithography technique and an anisotropic dry etching technique.

[0079] Next, referring to FIG. 23 , a photoresist 63 having such a pattern that portions thereof that are above the contact holes 60 and 62 are opened is formed by a photolithography technique. Then, using the photoresist 63 as an implant mask, an impurity such as P, As, or Sb is ion-implanted at a concentration of about 1E12/cm ² to 1E14/cm ² . This forms n-type impurity-introduced regions 100 in the respective upper surfaces of the source regions 5 S and 6 S.

[0080] Next, the photoresist 63 is removed. Then, contact plugs 30 to 32 are formed by filling the contact holes 60 to 62 with a polysilicon film doped with an impurity such as P, As, or Sb. From this point on, the processes that follow the step shown in FIG. 17 are performed, thus completing a semiconductor device.

[0081] As described above, with the method of manufacturing the semiconductor device according to the fourth preferred embodiment, the electric field strength of the source regions 5 S and 6 S can be further lowered in comparison with the second preferred embodiment by forming the impurity-introduced regions 100 in the upper surfaces of the source regions 5 S and 6 S. As a consequence, device characteristics such as refresh characteristics and hot carrier characteristics can be further improved, which accordingly enhances device reliability. Moreover, since the impurity-introduced regions 100 are formed only in the source regions 5 S and 6 S, degradation in short channel characteristics of the memory cell transistors can be avoided.

Fifth Preferred Embodiment

[0082] FIG. 24 is a top plan view showing a structure of a semiconductor device according to a fifth preferred embodiment of the present invention. FIG. 25 is a cross-sectional view showing a cross-sectional structure concerning a position along the line XXV-XXV shown in FIG. 24 . Referring to FIG. 24 , a plurality of element forming regions AR (denoted by reference characters ARa to ARe in FIG. 24 ) are defined by the element isolating insulation film 4 . The element forming region ARa and the element forming region ARb, which belong to a common row in a memory cell array, and the element forming region ARd and the element forming region ARe, which belong to a common row, are each mutually spaced apart and aligned along the X direction. Referring to FIGS. 24 and 25 , in each of the element forming regions AR, impurity-introduced regions 70 and 73 are formed in ends of the source regions 5 S and 6 S with respect to the X direction. It should be noted that the doped channel regions 5 may be formed in each of the element forming regions AR, as in the foregoing second preferred embodiment.

[0083] FIGS. 26 and 27 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing the semiconductor device according to the fifth preferred embodiment of the present invention. First, referring to FIG. 26 , the silicon oxide film 20 and the silicon nitride film 21 are formed in a similar manner to the foregoing first preferred embodiment. In addition, a recessed portion 22 a is formed in the upper surface of the silicon substrate 10 by overetching in the etching for patterning the silicon oxide film 20 and the silicon nitride film 21 .

[0084] Next, referring to FIG. 27 , with the silicon oxide film 20 and the silicon nitride film 21 having been formed, ions 76 and 77 of an n-type impurity such as P, As, or Sb are implanted at a concentration of about 1E12/cm ² to 1E14/cm ² , in the X direction from diagonally above. The ion implantation is sequentially carried out in opposing directions +X and −X, as indicated by arrows X 1 and X 2 in FIG. 24 .

[0085] As for implant angle β of the ion implantation (that is, an angle formed by an implant direction of the impurity ions 76 , 77 and a direction of the normal to the upper surface of the silicon substrate 10 ), an implant angle is adopted that satisfies the relationship tan ⁻¹ (V/U)≦β≦tan ⁻¹ (V/T), where V is the interval between the silicon nitride films 21 adjacent to each other along the X direction, T is the total film thickness of the silicon oxide film 20 and the silicon nitride film 21 , U is the depth from the upper surface of the silicon nitride film 21 to the bottom surface of the recessed portion 22 a . For one example, the interval V is about 390 nm, and the depth U is about 170 nm.

[0086] When the implant angle β is controlled within that range, the impurity ions 76 and 77 are implanted into portions of the side surfaces of the recessed portion 22 a that are perpendicular to the X direction. For example, of the side surface of the recessed portion 22 a that corresponds to the third side surface 10 A ₃ shown in FIG. 14 , impurity ions 76 and 77 are implanted into a portion perpendicular to the X direction. As result, as shown in FIG. 27 , n-type impurity-introduced regions 70 and 73 are formed within the upper surface of the silicon substrate 10 that is in the element forming regions ARd and ARe, respectively. Meanwhile, because the ion implantation is performed in the X direction from diagonally above, impurity ions 76 and 77 are not implanted in portions of the side surfaces of the recessed portion 22 a that are perpendicular to the Y direction.

[0087] Thereafter, the recessed portion 22 is formed and the a silicon oxide film 13 is formed on the side surfaces and the bottom surface of the recessed portion 22 , followed by performing the processes subsequent to the manufacturing step shown in FIG. 6 , as in the second preferred embodiment; thus, a semiconductor device is completed.

[0088] As described above, in the method of manufacturing the semiconductor device according to the fifth preferred embodiment, the impurity-introduced regions 70 and 73 are respectively formed within the upper surface of the silicon substrate 10 that is in the element forming regions AR. Therefore, even if crystal defects are caused in the silicon substrate 10 due to damages arising from, for example, the etching for forming the recessed portion 22 , the crystal defects can be covered by the impurity-introduced regions 70 and 73 . As a result, leakage current resulting from the crystal defects can be suppressed, and refresh characteristics can therefore be improved.

[0089] Moreover, the impurity-introduced regions 70 and 73 are formed only in portions of the source regions 5 S and 6 S that are in the vicinity of their interfaces with the element isolating insulation film 4 , and therefore, it is possible to avoid degradation in short channel characteristics of memory cell transistors.

Sixth Preferred Embodiment

[0090] FIGS. 28 through 31 are cross-sectional views showing, in order of manufacturing steps, a method of manufacturing a semiconductor device according to a sixth preferred embodiment of the present invention. FIGS. 28 to 31 show a structure of a memory cell array section in the silicon substrate 10 , in which a memory cell array is formed, and a structure of a peripheral circuit section therein, in which a peripheral circuit is formed. The following describes an example in which p-channel MOSFETs are formed in the peripheral circuit section.

[0091] First, referring to FIG. 28 , the silicon oxide film 20 , the silicon nitride film 21 , the recessed portion 22 , and the silicon oxide film 13 are formed in the memory cell array section and the peripheral circuit section in a similar manner to the foregoing first preferred embodiment. In addition, the doped channel regions 5 ₁ and 5 ₂ are formed in the memory cell array section. Next, a photoresist 80 that covers the peripheral circuit section is formed by a photolithography technique. Then, using the photoresist 80 as an implant mask, ions of an impurity such as B or In are implanted into the silicon substrate 10 in a direction perpendicular to the upper surface of the silicon substrate 10 through the recessed portion 22 and the silicon oxide film 13 . This forms a p-type channel cut region 81 in the bottom surface of the recessed portion 22 that is in the memory cell array section.

[0092] Next, referring to FIG. 29 , after removing the photoresist 80 , the manufacturing steps shown in FIGS. 6 through 8 are carried out in a similar manner to those in the foregoing first preferred embodiment. Specifically, a silicon oxide film 24 having such a film thickness that it can completely fill up the recessed portion 22 is entirely formed, and subsequently, the silicon oxide film 24 is polished until the upper surface of the silicon nitride film 21 is exposed; thereafter, the silicon oxide film 24 is removed to a desired film thickness, and then, the silicon nitride film 21 is removed.

[0093] Then, referring to FIG. 30 , a photoresist 82 that covers the peripheral circuit section is formed by a photolithography technique. Thereafter, the p-type doped channel regions 1 C and 2 C as well as the p-type well region 11 are formed within the silicon substrate 10 that is in the memory cell array section by implanting ions of a p-type impurity, using the photoresist 82 as an implant mask.

[0094] Next, referring to FIG. 31 , after removing the photoresist 82 , a photoresist 83 that covers the memory cell array section is formed by a photolithography technique. Then, n-type doped channel regions 86 , an n-type channel cut region 85 , and an n-type well region 84 are formed in the silicon substrate 10 that is in the peripheral circuit section by ion-implanting an n-type impurity using the photoresist 83 as an implant mask.

[0095] After removing the photoresist 83 , the processes subsequent to the manufacturing step shown in FIG. 10 are performed in a similar manner to the foregoing second preferred embodiment, thus completing a semiconductor device.

[0096] As described above, in the method of manufacturing the semiconductor device according to the sixth preferred embodiment, the channel cut regions 81 are formed only within the bottom surface of the recessed portion 22 in the memory cell array section. In other words, the p-type channel cut regions 81 are not formed in portions below the n-type source regions 5 S and 6 S. For this reason, the electric field strength of the source regions 5 S and 6 S is further relaxed in comparison with the foregoing second preferred embodiment, and therefore, it becomes possible to improve refresh characteristics.

[0097] Further, the peripheral circuit section is covered by the photoresist 80 when performing the ion implantation for forming the channel cut regions 81 . Therefore, it is possible to avoid formation of unnecessary channel cut regions 81 within the silicon substrate