DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

[0017] The present invention now will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout.

[0018] FIG. 1 is a schematic diagram illustrating a general dual bank memory system 100 according to some embodiments of the present invention. The system 100 includes a control circuit 10 and a memory module 20 . The memory module 20 comprises memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n , of which memory devices 20 - 11 to 20 - 1 n are arranged in a first column on the memory module 20 , and memory devices 20 - 21 to 20 - 2 n are arranged in a second column on the memory module 20 .

[0019] Signal transmission between the control circuit 10 and memory devices 20 - 11 to 20 -in, 20 - 21 to 20 - 2 n will now be described. A first chip select signal line cs 1 b 1 connects a first chip select signal terminal CS 1 B of the control unit 10 to chip select signal terminals CSB of the memory devices 20 - 11 to 20 - 1 n . A second chip select signal line cs 2 b 1 connects a second chip select signal terminal CS 2 B of the control unit 10 to inverted chip select signal terminals CSB of the memory devices 20 - 21 to 20 - 2 n . A row address strobe signal line rasb 1 , a column address strobe signal line casb 1 , a write enable signal line web 1 , and an address signal line respectively connect a row address strobe signal terminal RASB, a column address strobe signal terminal CASB, a write enable signal terminal WEB, and an address signal terminal ADD of the control unit 10 to respective ones of row address strobe signal terminals RASB, column address strobe signal terminals CASB, write enable signal terminals WEB, and address signal terminals ADD of the memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n . A data input/output line dq 11 connects a data input/output terminal DQ 1 of the control unit 10 to data input/output terminals DQ of the memory devices 20 - 11 , 20 - 21 , and a data input/output line dq 21 connects a data input/output terminal DQ 2 of the control unit 10 to data input/output terminals DQ of the memory devices 20 - 12 , 20 - 22 . Similarly, a data input/output line dqn 1 connects a data input/output terminal DQn of the control unit 10 to data input/output terminals DQ of the memory devices 20 - 1 n , 20 - 2 n .

[0020] In the dual bank system of FIG. 1 , memory devices 20 - 11 to 20 - 1 n in the first column of the memory module 20 are selected when the control unit 10 generates a chip select signal cs 1 b having a “low” level, and data dq 1 to dqn are simultaneously applied to memory devices ( 20 - 11 , 20 - 21 ), ( 20 - 12 , 20 - 22 ), ( 20 - 1 n , 20 - 2 n) in the first and second columns of the memory module 20 when the control unit 10 generates data dq 1 to dqn with a write enable signal web having a “low” level. In other words, in the dual bank system, when the memory devices 20 - 11 to 20 - 1 n in the first column are to receive data in a write operation, the same data is also applied to the memory devices 20 - 21 to 20 - 2 n in the second column. Similarly, when memory devices 20 - 21 to 20 - 2 n in the second column of the memory module 20 are to receive data in a write operation, the data is also applied to the memory devices 20 - 11 to 20 - 1 n in the first column of the memory module 20 .

[0021] FIG. 2 is a block diagram illustrating an ODT control circuit 200 of an ODT circuit in a memory device, such as the devices 20 - 11 to 20 - 1 n and 20 - 21 to 20 - 2 n , that may be used in the dual bank system shown in FIG. 1 in accordance with further embodiments of the present invention. The ODT control circuit 200 includes a command decoder 30 , OR gates OR 1 , OR 2 , and an on-die-termination (hereinafter, referred to as ODT) control signal generating unit 32 . The command decoder 30 decodes command signals, including a clock signal clk, a chip select signal csb, a row address strobe signal rasb, a column address strobe signal casb, and a write enable signal web applied from an external source, to generate a write enable signal WE, a dummy write enable signal DWE, a dummy read signal DRD, and a read signal RD. The OR gate OR 1 performs a logical OR between the write enable signal WE and the dummy write enable signal DWE to generate the ODT enable signal ODTEN. The OR gate OR 2 performs a logical OR between the dummy read signal DRD and the read signal RD to generate the ODT disable signal ODTDIS. The ODT control signal generating unit 32 activates an ODT control signal PODT in response to the ODT enable signal ODTEN, and deactivates the ODT control signal PODT in response to the ODT disable signal ODTDIS.

[0022] The command decoder 30 generates the dummy write signal DWE and the dummy read signal DRD in addition to the write signal WE and the read signal RD. Table 1 shows exemplary operations of the memory configuration of FIG. 2 (in Table 1, L represents a “low” level, and H represents a “high” level, respectively): 1

[0023] The command decoder 30 activates the write signal WE when the chip select signal csb is a “low” level and the other command signals, including the row address strobe signal rasb, the column address strobe signal casb, and the write enable signal web are at a “high” level, a “low” level, and a “low” level, respectively. The OR gate OR 1 activates the ODT enable signal ODTEN a “high” level when the high-level write signal WE or the dummy write signal DWE have a “high” level. The ODT control signal generating unit 32 activates the ODT control signal PODT to a “high” level when the ODT enable signal ODTEN has a “high” level.

[0024] The command decoder 30 activates the read signal RD when the chip select signal csb is at a “low” level and the row address strobe signal rasb, the column address strobe signal casb, and the write enable signal web, are at a “high” level, a “low” level, and a “high” level, respectively. The OR gate OR 2 activates the ODT disable signal ODTDIS to a “high” level when the dummy read signal DRD is at a “high” level. The ODT control signal generating unit 32 deactivates the ODT control signal PODT to a “low” level when the ODT disable signal ODTDIS is at a “high” level. In other words, the ODT control signal PODT is activated in response to a write operation, irrespective of the state of the chip select signal csb, and the ODT control signal PODT is deactivated to a “low” level responsive to a read operation. Accordingly, energy dissipation in the on-die-termination circuit can be reduced.

[0025] Referring back to FIG. 1 , when writing data, ODT circuits of memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n of the memory module 20 are enabled to terminate signals applied to memories 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n . That is, because the dual bank system is configured such that data is applied to both columns of memory devices when performing a write operation, the ODT circuits in the devices that are actually not being written to are enabled to terminate the data signals and reduce signal reflections from the non-selected memory devices.

[0026] FIG. 3 is a circuit diagram illustrating an ODT control signal generating circuit 300 which may be used in the circuit 200 shown in FIG. 2 . The circuit 300 includes a delay circuit 40 , a delay and inverter circuit 42 , a NAND gate NAND, and an inverter II. The delay circuit 40 delays the ODT enable signal ODTEN by a first predetermined time. The delay and inverter circuit 42 delays the ODT disable signal ODTDIS by a second predetermined time. The NAND gate NAND and the inverter I 1 perform a logical AND of the signals produced by the delay circuit 40 and the delay and inverter circuit 42 to generate the ODT control signal PODT. The ODT control signal PODT is activated in response to the activation of the ODT enable signal ODTEN, and is deactivated in response to the deactivation of the ODT enable signal ODTEN. The ODT control signal PODT is deactivated in response to the activation of the ODT disable signal ODTDIS, irrespective of the state of the ODT enable signal ODTEN. In other words, the ODT control signal PODT is activated during a period in which data is input to the memory device. This can be done by appropriately adjusting the first predetermined time of the delay circuit 40 and the second predetermined time of the delay and inverter circuit 42 . Although the ODT control signal generating circuit shown in FIG. 3 includes the delay circuit 40 and the delay and inverter circuit 42 , in some cases, a configuration without the delay circuit 40 and the delay and inverter circuit 42 is also possible.

[0027] FIG. 4 is a circuit diagram of a termination circuit 400 according to further embodiments of the present invention. The termination circuit 400 includes an inverter 12 , a PMOS transistor P, an NMOS transistor N, and resistors Ru, Rd. In FIG. 4 , a termination node A is connected to a data input/output (or input) pad (not shown). When the ODT control signal PODT transitions to a “high” level, the inverter 12 produces a “low” level signal. Consequently, the NMOS transistor N and the PMOS transistor P are turned on. Therefore, the resistors Ru, Rd are coupled to power supply voltage VCC and a ground voltage to provide a termination for the node A.

[0028] FIGS. SA and 5 B are timing diagrams illustrating exemplary operations of a dual bank memory system according to further embodiments of the present invention, where a write command and a read command are sequentially applied to memory devices that are operated in Double Data Rate (DDR) mode with a write latency of 4 , a CAS latency of 5 , and a burst length of 4 . As shown in the above Table 1, when the first chip select signal cs 1 b, the row address strobe signal rasb, the column address strobe signal casb, and the write enable signal web, in response to a rising edge of a clock signal clk, transition to a “low” level, a “high” level, a “low” level, and a “low” level, respectively, the memory devices 20 - 11 to 20 - 1 n in the first column generate the write enable signal WE as illustrated in FIG. 5A , and the memory devices 20 - 21 to 20 - 2 n in the second column generate the dummy write signal DWE as illustrated in FIG. 5B .

[0029] The memory devices 20 - 11 to 20 - 1 n transition the ODT enable signal ODTEN to a “high” level in response to the write signal WE, as illustrated in FIG. 5A , while memory devices 20 - 21 to 20 - 2 n transition the ODT signal ODTEN to a “high” level in response to the dummy write signal DWE, as illustrated in FIG. 5B . Consequently, each of memory devices 20 - 11 to 20 -in, 20 - 21 to 20 - 2 n transitions the ODT control signal PODT to a “high” level in response to the ODT enable signal ODTEN, as illustrated in FIGS. 5A and 5B . Accordingly, the ODT circuits of the memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n are activated to provide signal terminations for the associated data lines. As noted above, although memories 20 - 21 to 20 - 2 n in the second column do not perform an actual write operation, the ODT circuits in these devices provide appropriate signal termination impedances as data applied to the memory devices 20 - 11 to 20 - 1 n in the first column is also applied to the memory devices 20 - 21 to 20 - 2 n in the second column.

[0030] Two clock cycles after the write command is applied, when the first chip select signal cs 1 b, the row address strobe signal rasb, the column address strobe signal casb, and the write enable signal web have a “low” level, a “high” level, a “low” level, and a “high” level, respectively, the memory devices 20 - 11 to 20 - 1 n in the first column activate read signals RD as illustrated in FIG. 5A and the memory devices 20 - 21 to 20 - 2 n in the second column activate dummy read signal DRD as illustrated in FIG. 5B . Then, the memory devices 20 - 11 to 20 - 1 n in the first column transition the ODT disable signal ODTDIS to a “low” level in response to the read signal RD as illustrated in FIG. 5A , while memory devices 20 - 21 to 20 - 2 n in the second column transition the ODT disable signal ODTDIS to a “low” level in response to the dummy read signal DRD as illustrated in FIG. 5B . Therefore, each of memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n transitions its ODT control signal PODT to a “low” level in response to the ODT disable signal ODTDIS as illustrated in FIGS. 5A and 5B . Accordingly, the ODT circuits of the memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n in both columns are deactivated, i.e., provide higher termination impedances.

[0031] FIGS. 6A and 6B are timing diagrams for illustrating exemplary operations of a dual bank memory system according to further embodiments of the present invention, where a write command is applied to memory devices operating in a DDR mode with a write latency of 4 , a CAS latency of 5 , and a burst length of 4 . As shown in the above Table 1, when the first chip select signal cs 1 b, the row address strobe signal rasb, the column address strobe signal casb, and the write enable signal web, in response to the rising edge of the clock signal clk, take on a “low” level, a “high” level, a “low” level, and a “low” level, respectively, the memory devices 20 - 11 to 20 - 1 n in the first column activate the write enable signal WE as illustrated in FIG. 6A . Then, the ODT control signal PODT transitions to a “high” level in response to the write enable signal WE. The operation where the write enable signal WE is generated will be easily understood with reference to the above description of FIGS. 5A and 5 B.

[0032] When their write enable signals WE transition to a “low” level, the memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n transition their ODT enable signals ODTEN to a “low” level in response to the write enable signals WE. The ODT control signals PODT then transition to a “low” level in response to the ODT enable signals ODTEN. Accordingly, the memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n deactivate their ODT circuits. In other words, the ODT control signals PODT of the memory devices 20 - 11 to 20 - 1 n , 20 - 21 to 20 - 2 n in the first and second columns are activated when their write enable signals WE are activated, and deactivate their ODT control signals PODT when their write enable signals WE are deactivated. Therefore, in a dual bank memory system according to some embodiments of the present invention, ODT circuits operate to fit the duration in which data is input to memories 20 - 11 to 20 -in, 20 - 21 to 20 - 2 n , which can reduce power dissipation in the ODT circuits.

[0033] In the above-described embodiments, a multi-bank memory system, memory devices used for the same, and the ODT control operations thereof are described for DDR operation. It will be understood, however, that types of memory operation other than DDR may be used with the present invention. In addition, although the above-described embodiments use memory devices mounted in columns in a memory module, other memory device configurations may be used with the present invention, such as arrangements in which memory devices are mounted on a system board.

[0034] In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.