DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0019] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0020] The present invention will be described with respect to preferred embodiments in a specific context, namely semiconductor devices having one or more metallization layers in which conductive lines are formed to form interconnects. Processes are described herein which bear on the elimination of an inorganic cap layer by recessing the surface of the copper conductors and vias to provide for a thicker, conducting diffusion barrier while still maintaining the overall thickness requirements for the metal/insulator stack. It is to be noted that the low-k dielectrics described herein may be either organic, such as SiLK™, as an example, or inorganic, such as HSQ, and therefore, the term “low-k dielectrics” will be used to refer to both organic and inorganic low-k insulators. The low k-dielectrics may be of porous or non-porous nature. In particular, this term does not include materials such as SiO ₂ or Si ₃ N ₄ , which have k values of about 4 and about 8, respectively. However, embodiments of the present invention are not restricted to low k dielectrics; they may be also implemented in structures having more traditional dielectrics like SiO ₂ or FSG, as examples.

[0021] An embodiment of the present invention will first be summarized, with reference to FIG. 1 . FIG. 1 shows a cross-sectional view of a semiconductor device 10 structure which comprises a plurality of logic circuitry of a microprocessor or ASIC, or, alternatively, as an example, memory cells of a dynamic random access memory (DRAM) represented by a drain region 14 formed in a semiconductor substrate 12 in accordance with a preferred embodiment of the present invention. A first insulating (Pre-Metal Dielectric, PMD) layer 18 , typically comprising silicon oxide (SiO2) is deposited onto a silicon substrate surface 16 of a semiconductor substrate 12 and is patterned, lithographically, to form contact openings (not shown) which are overfilled with a first conducting layer 20 , typically tungsten (W), which becomes the contact metallurgy to the semiconductor drain region 14 . The surface is planarized using a chemical-mechanical polishing (CMP) process, for example, to result in an essentially planar surface 22 . A low-k dielectric insulating layer (Inter-Metal Dielectric, IMD) 24 , comprising a material having a low dielectric constant, for example, typically about 3.7 or less, is deposited over the first inorganic insulating layer 18 . A single damascene process is used to form openings (not shown) in insulating layer 24 and the openings (trenches) are lined with a second conductor material 26 , typically, of tantalum nitride (TaN) or titanium nitride (TiN), as examples. Alternatively the liner 26 may comprise Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof, for example.

[0022] The lined openings are filled with a third conductor material 28 A, typically Cu, to form conductors and to make contact to the first conductor layer 20 . The surface is then planarized, using CMP, for example, to form a planar surface 30 . The exposed copper layer 28 A is etched to result in a recessed top surface 28 B. A catalytic activation layer 34 , typically comprising palladium (Pd), for example, is deposited over the copper top surface 28 B to provide a catalytically activated copper surface. A barrier layer 36 , typically comprising cobalt tungsten phosphide (CoWP) and alternatively comprising CoWB, CoP, NiMoP, Re or Ru, as examples, is deposited selectively and preferably electrolessly, onto a surface 32 of the Pd layer to form a surface 38 which is essentially co-planar with the surface 30 of the low-k dielectric layer 24 .

[0023] One or more insulating layers and conductive structures may subsequently be formed, in accordance with embodiments of the present invention. For example, in FIG. 1 , a low-k dielectric insulating layer 40 , comprising a material having a low dielectric constant, typically k equals about 3.7 or less, is deposited over the resulting structure. Layer 40 is etched to form a dual damascene structure with both trench and via hole openings (not shown) having surfaces 40 B, which are then covered with a liner layer 44 , typically comprising TaN, TiN, WN or other similar materials. Alternatively the liner 44 may comprise Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof, for example. The trench and hole openings are then overfilled with copper 46 , and the surface is planarized, for example, using CMP. The planarized copper 46 is then etched to form a recessed top surface 50 A. A catalytic activation layer 48 , typically comprising palladium (Pd), for example, is deposited over the copper surface 50 A. The Pd activation layer 48 is then covered, preferably selectively and electrolessly, with a conductive barrier layer 52 , typically comprising CoWP and alternatively comprising CoWB, CoP, NiMoP, Re or Ru, as examples. An optional touch-up CMP process can be performed after the CoWP deposition to remove any CoWP overgrowth and CoWP islands (spots) on the top surface of the dielectric layer 40 . It is, however, recommended that a CoWP layer having a thickness greater than 10 nm thick remains in the recessed areas above the copper line. A surface 52 A of the barrier layer 52 is then essentially co-planar with the low-k dielectric insulator layer 40 surface 46 A.

[0024] Again, additional insulating layers may be deposited over the structure. For example, shown in FIG. 1 , a low-k dielectric insulating material having a dielectric constant of about 3.7 or less, is then deposited to form an insulating layer 54 into which a via opening (not shown) is etched. The via opening is lined with a conductor material 56 , typically comprising TaN or TiN, as examples. Alternatively the liner 56 may comprise Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof, for example. The via opening is then overfilled with layer 58 , typically comprising copper, and the surface of the insulating layer 54 is planarized using CMP, for example. The exposed copper 58 is etched to form a recessed top surface 62 . A catalytic activation layer 66 , typically comprising Pd, for example, is deposited onto the top surface 62 layer and has a top surface 66 A. A conductive barrier layer 68 is then deposited, selectively and electrolessly, onto the surface 66 A forming a top surface 68 A which is essentially co-planar with surface 60 of insulating layer 54 . A second layer 64 , typically comprising SiO ₂ , is deposited onto the resulting structure and a third inorganic layer 70 , typically comprising Si ₃ N ₄ , is deposited onto the surface 64 A. Conducting vias (not shown) are formed through layers 64 and 70 and in other layers as required to facilitate electrical contact with terminals (not shown) on a package in which the semiconductor structure 10 is housed.

[0025] An embodiment of the present invention will next be described in more detail, with reference to FIGS. 2 through 8 . FIG. 2 shows a cross-sectional view of a semiconductor device 10 structure at an early stage of fabrication with an element region 14 which may comprise a drain region, for example, is formed in a semiconductor substrate 12 . A first inorganic insulating layer 18 , typically comprising silicon oxide (SiO ₂ ) and alternatively comprising B-type doped oxide, such as boron phosphosilicate glass (BPSG) or boron silicate glass (BSG), P-doped oxide, such as BPSG or phosphosilicate glass (PSG), or fluorine-doped oxide (FSG), as examples, and typically comprising a thickness of 200 nm-1000 nm, is deposited onto a silicon surface 16 of semiconductor substrate 12 . The first inorganic insulating layer 18 is lithographically patterned to form contact openings, exposing a top surface of the underlying element region 14 . The contact openings are filled with a first conducting layer 20 , typically comprising tungsten (W), for example, and alternatively comprising other conductive material. The first conducting layer 20 becomes the contact metallurgy to the element region 14 . The surface of the first inorganic insulating layer 18 is planarized, for example, using chemical-mechanical polishing (CMP) and alternatively comprising a reactive ion etch (RIE) to form a top surface 22 .

[0026] FIG. 3 shows a cross-sectional view of the semiconductor structure 10 shown in FIG. 2 , in which an insulating layer 24 , preferably comprising a low-k dielectric material having a dielectric constant of about 3.7 or less. For example the low-k insulating layer 24 may be deposited or spun onto the surface of the semiconductor substrate 12 , e.g., over the top surface 22 of the first insulating layer 18 . A single damascene process is then used to form openings in layer 24 , exposing the first conductive layer 20 and portions of the first insulating layer 18 . The openings are lined with a second conducting layer 26 comprising a barrier layer to the diffusion of copper. For example, the second conducting layer 26 typically comprises tantalum nitride (TaN) or titanium nitride (TiN). Alternatively the liner 26 may comprise Ta, W, Mo, TiW, TiN, Tan, WN, TiSiN, TaSiN, or a combination thereof, for example.

[0027] The opening (e.g., trench) lined with layer 26 is overfilled with a third conducting layer 28 , typically comprising copper or other conductive materials, for example, to form conductors and to make contact to the first conductor layer 20 . The resulting surface may then be planarized, using CMP or RIE, as examples, to form a planar surface 30 .

[0028] In accordance with an embodiment of the present invention, next, the third conducting layer 28 is etched to recess the third conducting layer 28 below the top surface 30 of the insulating layer 24 , as shown in FIG. 4 . The recessed layer 28 A is preferably recessed below the insulating layer 24 top surface 30 by approximately 10-20 nm and has a top surface 28 B. The liner layer 26 will be left intact if a wet chemical etch, comprising ammonium persulfate, for example, is used to recess the third conducting layer 28 A, because such an etch has good selectivity for copper, whereas, the liner layer 26 will be partially or completely removed if a reactive ion etch (RIE) is used.

[0029] The top surface 28 B of the recessed third conducting layer 28 A is then covered with a catalytic activation layer 34 , as shown in FIG. 5 . The catalytic activation layer 34 preferably comprises of palladium (Pd) and may alternatively comprise other materials, for example. The catalytic activation layer 34 is preferably, approximately one to three atom layers thick, which is useful to activate the Cu surface. A conductive barrier layer 36 , typically comprising cobalt-tungsten-phosphide (CoWP), and alternatively comprising CoWB, CoP, NiMoP, Re or Ru, as examples, is then deposited onto the top surface of the palladium layer 34 by selective, electroless deposition. Preferably the CoWP surface 36 A is essentially co-planar with the surface 30 of insulator layer 24 after the selective deposition of the conductive barrier layer 36 .

[0030] In an optional step, if any excess conductive barrier layer 36 and/or catalytic activation layer 34 is left remaining on the top surface 30 of the insulating layer 24 , this excess material 36 or 34 may be removed a CMP or RIE process, as examples (not shown).

[0031] Next, additional insulating layers 40 and 54 may be deposited over the top surface 30 and 36 A, as shown in FIGS. 6 through 8 , to be described herein. Each conductive layer that is formed is recessed below a top surface of the insulating layer the conductive lines are formed in, and a conductive barrier layer is selectively formed over the conductive lines, leaving a top surface of the conductive lines that is co-planar with the insulating layer the conductive lines are formed in.

[0032] In particular, FIG. 6 shows a cross-sectional view of the semiconductor structure 10 as shown in FIG. 5 , in which a layer 40 , (a low-k dielectric material with a dielectric constant, typically about 3.7 or less), is deposited onto the essentially planar surfaces 30 and 36 A. Layer 40 is etched to form a dual damascene structure resulting in both a via and trench opening, thereby creating new surfaces 42 on modified layer 40 . The surfaces 42 are covered, conformally, with a liner layer 44 , typically comprising TaN or TiN. Alternatively the liner 44 may comprise Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof, for example. The via and trench openings are then overfilled with a conductive layer 46 which may comprise copper, for example, and the surface of insulating layer 40 is planarized using CMP or RIE, as examples, to form a top surface 46 A.

[0033] FIG. 7 shows a cross-sectional view of the semi-conductor structure 10 shown in FIG. 6 , in which the Cu layer is 46 is etched, typically with a wet etch of ammonium persulfate, to form a recessed surface 50 A in the Cu layer 46 . An activation layer 48 , typically comprising Pd, one to three atom layers thick, is then deposited to cover the recessed Cu surface 50 A. A layer 52 , typically comprising cobalt tungsten phosphide (CoWP), and alternatively comprising CoWB, CoP, NiMoP, Re or Ru, as examples, is selectively and electrolessly deposited onto activation layer 48 to form a new surface 52 A. The thickness of CoWP layer 52 makes the surface 52 A essentially co-planar with the surface 46 A of layer 40 . If needed, an optional additional “touch-up” CMP process may be performed on the semiconductor device 10 to remove any excess barrier layer 52 and/or activation layer 48 from the top surface 46 A of the device 10 .

[0034] FIG. 8 shows a cross-sectional view of the semiconductor structure 10 of FIG. 7 , in which the surface 46 A is covered with an insulating layer 54 which preferably comprises a low-k dielectric materials having a dielectric constant, typically of about 3.7 or less, for example. A via is formed in layer 54 and is then lined with a layer 56 of a conductor material, typically comprising TaN or TiN, as examples. Alternatively the liner 56 may comprise Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof, for example. The via is then overfilled with a conductive material such as copper 58 , and the surface is planarized using a CMP or RIE, as examples, to form surface 60 .

[0035] Referring again to FIG. 1 , therein is shown the resulting semiconductor structure 10 after the Cu via fill 58 has been recessed, 10-20 nm, by a wet or dry etch, as examples. The Cu surface 62 is covered with an activation layer 66 , typically of Pd, which forms surface 66 A. A layer 68 , typically comprising CoWP, and alternatively comprising CoWB, CoP, NiMoP, Re or Ru, as examples, is selectively and electrolessly deposited onto Pd surface 66 A to a thickness that makes the surface co-planar with surface 60 . An inorganic insulator layer 65 , typically of SiO ₂ , is then deposited onto surface 60 . This is followed by the deposition of a second inorganic insulating layer 70 , typically comprising silicon nitride (Si ₃ N ₄ ), for example, onto surface 64 A. Vias and trenches are formed into layer 64 and 70 , and conductors are then formed in the vias and trenches to facilitate electrical contact with terminals on a package in which the semiconductor 10 is housed.

[0036] It is to be noted that the specific embodiment that has been described herein is illustrative of the general principles of the invention. Various other embodiments can be devised without departing from the spirit and scope of the invention. For example, other organic or inorganic materials can be used for the insulating layers and other materials can be used to replace the diffusion barrier materials of the liners and selective cap layers.

[0037] While only one conductive line and/or via interconnect is shown within each insulating layer in the figures, there may be many conductive lines and via connections within each insulating layer. Also, while 3 insulating layers and interconnect layers are shown in the Figures, there may be only one interconnect layer, or 8 or more interconnect layers in the semiconductor device 10 , as examples. One or more of the interconnect layers may include recessed damascene conductive lines over which barrier layers are selectively formed, in accordance with embodiments of the invention.

[0038] In accordance with one embodiment of the present invention, a semiconductor device 10 includes a first insulating layer 24 formed over a substrate 12 , the first insulating layer 10 being patterned with a pattern for at least one conductive line, and a first conductive material 28 A disposed within the patterned first insulating layer 24 , the first conductive material 28 A being recessed below a top surface 30 of the first insulating layer 24 . The device 10 includes an activation layer 34 disposed over the recessed first conductive material 28 A, and a barrier layer 36 disposed over the activation layer 34 , wherein the activation layer 34 and barrier layer 36 do not extend beyond the top surface 30 of the first insulating layer 24 .

[0039] Advantages of embodiments of the present invention include the prevention of line shorting by lateral growth of the barrier layers 32 , 52 and 68 . Because the conductive lines 28 A, 46 and 58 described herein are recessed below a top surface of the insulating layers 24 , 40 and 54 they are formed in, respectively, no lateral growth of the barrier layers 32 , 52 or 68 can occur during the selective formation of the barrier layers 32 , 52 or 68 .

[0040] An advantage of a preferred embodiment of the present invention is the introduction of a recess etch of damascene metal lines or other features to allow the deposition of a sufficiently thick selective deposited metallic cap layer without creating shorts in narrow features.

[0041] A further advantage of a preferred embodiment of the present invention is that the recess etch can be combined with an additional optional “touch-up” CMP process to remove overfill or any unintentional deposition on the dielectric material.

[0042] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.