DETAILED DESCRIPTION OF THE INVENTION

[0030] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or other changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention.

[0031] As mentioned above, in many instances it is desirable to perform a linear operation (e.g., addition, subtraction, averaging, weighted averaging) on sampled signals in the analog, or charge domain, of a CMOS sensor. In accordance with the present invention, the operation of the column decoder (e.g., 450 of FIG. 3 ) is programmable such that column decoder 450 may select a plurality of column buffer circuits (e.g,. 432 , 434 , 436 , FIG. 3 ) at substantially the same time for read out. These multiple values that are read out are then forwarded to the gain stage circuit 455 (of FIG. 3 ) to be combined during a linear operation in the analog domain.

[0032] FIG. 3 shows a block diagram of an APS array and signal processing system in accordance with an exemplary embodiment of the invention. The FIG. 3 APS array and signal processing system 400 differs from the system 100 in several significant ways and which are described in greater detail below.

[0033] The column decoder 450 of the APS system 400 differs from the column decoder 150 of the APS system 100 in that column decoder 450 is programmed to operate so that signals can be read from more than one column buffer circuit 432 , 434 , 436 at substantially the same time. That is, for example, respective sets of output signals from two or more output buffers e.g., 434 , 436 may be applied substantially simultaneously to the differential inputs of the gain stage 455 .

[0034] FIG. 4 shows the column buffer circuits 432 , 434 , 436 and gain stage 455 of the FIG. 3 APS system 400 in greater detail. The column buffer circuit 436 , which is representative of column buffer circuits 432 , 434 , differs from the column buffer circuit 136 ( FIG. 2 ) by including a polarity reversing circuit 695 for use in the subtraction operation described in greater detail below. Further, the column buffer circuit 436 differs from the column buffer circuit 136 ( FIG. 2 ) by including variable capacitors 622 , 626 for use in the average and weighted sum operation described in greater detail below. The gain stage 455 differs from the gain stage 155 ( FIG. 2 ) by including variable capacitors 678 , 680 for use in the average and weighted sum operation described in greater detail below.

[0035] In the column buffer circuit 436 shown in FIG. 4 , the first input node 210 receives reset voltage Vin_p and is coupled to a first terminal of a first sampling switch 214 . Switch 214 , and the other switches within the FIG. 4 circuit, is typically implemented as MOSFETs. The second input node 212 receives signal voltage Vin_n and is coupled to a first terminal of a second sampling switch 216 . The first switch 214 has a second terminal mutually coupled to a first terminal of a switch 690 and a first terminal of a switch 694 of the polarity reversing circuit 695 . The second switch 216 has a second terminal mutually coupled to a first terminal of a switch 692 and a first terminal of a switch 696 of polarity reversing circuit 695 .

[0036] Switch 694 has a second terminal mutually coupled to a first terminal of a crawbar switch 218 and a first terminal of a sample-and-hold variable capacitor 622 . Switch 690 has a second terminal mutually coupled to a second terminal of crawbar switch 218 and a first terminal of a sample-and-hold variable capacitor 626 . Switch 696 has second terminal mutually coupled to a first terminal of crawbar switch 218 and a first terminal of sample-and-hold capacitor 622 . Switch 692 has second terminal mutually coupled to a second terminal of crawbar switch 218 and a first terminal of sample-and-hold capacitor 626 .

[0037] The reverse polarity circuit 695 directs the storage of the set of signals Vrst, Vsig to capacitors 622 , 626 . When the reverse polarity circuit 695 operates in a standard, normal, or non-inverting, mode, the Vin_p signal carried on line 210 is stored on capacitor 622 and the Vin_n signal carried on line 212 is stored on capacitor 626 . When the reverse polarity circuit 695 operates in a reversing, or inverting, mode, (e.g., in the subtraction operation) the Vin_p signal carried on line 210 is stored on capacitor 626 and the Vin_n signal carried on line 212 is stored on capacitor 622 . In another embodiment, the reverse polarity circuit 695 is disposed between the respective capacitors 622 , 626 and the respective nodes 242 , 242 and permits inverting the polarity of the signals after storing the signals in the respective capacitors and before reaching the nodes 232 , 240 . In another aspect, the reverse polarity circuit 695 may not be included in an APS systems 400 in which there is no desire to perform a subtraction operation.

[0038] Still referring to FIG. 4 , a second terminal of the first sample and hold capacitor 622 is mutually coupled to a first terminal of a first clamping switch 230 and to a first terminal of a select switch 232 . A second terminal of the second sample and hold capacitor 626 is mutually coupled to a first terminal of a second clamping switch 238 and to a first terminal of a second select switch 240 . The respective second terminals of the first and second clamping switches 230 , 238 are coupled to a source of a clamping voltage Vcl. The respective second terminals of the first and second select switches 232 , 240 are coupled to respective output nodes 242 , 244 of the buffer circuit 436 .

[0039] A column decoder circuit 450 (as shown in FIG. 3 ) controls the operation of the switches ( 214 , 216 , 218 , 230 , 232 , 238 , 240 ) of the buffer circuit 436 . The output nodes 242 , 244 of the buffer circuit 436 are coupled respectively to first and second inputs of gain stage 455 . The gain stage 455 contains a differential amplifier 464 , variable feedback capacitors 678 , 680 , and switches 674 , 676 . Differential amplifier 464 receives a set of signals from a plurality of pixel cells and outputs differential voltages of the received signals.

[0040] The variable capacitors 622 , 626 of the column buffer circuits 432 , 434 , 436 and the variable capacitors 678 , 680 of the gain stage 455 of FIG. 4 are used to implement a gain in the signals carried between the capacitors in a conventional manner. For instance, the signal gain is equivalent to the ratio between the capacitance value (e.g., Csi) of the variable capacitors 622 , 626 of the column buffer circuits 432 , 434 , 436 and the capacitance value of the variable capacitors 678 , 680 of the gain stage 455 , i.e., (e.g., Cf). Therefore, the gain is Csi/Cf.

[0041] FIG. 5 shows the sample-and-hold variable capacitors 622 , 626 (of FIG. 4 ) in greater detail. Each variable capacitor 626 , 622 contains a plurality of substantially similar, switchably coupled, parallel connected capacitors. Variable capacitor 626 has a capacitor 626 _ 0 switchably connected in parallel with capacitors 626 _ 1 , 626 _ 2 , . . . 626 _N through respective switches 626 _G_ 1 , 626 _G_ 2 , . . . 626 _G_N. The capacitance of the variable capacitor 626 is thereby controlled by selectively closing a desired combination of switches 626 _G_ 1 , 626 _G_ 2 , . . . 626 _G_N. Variable capacitor 622 performs similarly to variable capacitor 626 . In another aspect, variable capacitors 622 , 626 may not be included in an APS systems 400 in which there is no desire to perform average and weighted sum operations.

[0042] FIG. 6 shows the gain stage 455 and variable capacitors 680 , 678 (of FIG. 4 ) in greater detail. First and second outputs 862 , 864 of the gain stage amplifier 464 are respectively fed back to gain stage amplifier 464 inputs 852 , 854 through respective parallel combinations of reset switches 674 , 676 and variable feedback capacitors 678 , 680 . Each variable feedback capacitor 678 , 680 contains of a plurality of switchably coupled parallel connected, substantially similar capacitors. Variable capacitor 678 has a capacitor 678 _ 0 switchably connected in parallel with capacitor 678 _ 1 , 678 _ 2 , . . . 678 _N through respective switches 678 _Ga_ 1 , 678 _Ga_ 2 , . . . 678 _Ga_N. The capacitance of the variable capacitor 678 is controlled by selectively closing any combination of switches 678 _Ga_ 1 , 678 _Ga_ 2 , . . . 678 _Ga_N. Similarly, variable capacitor 680 has a capacitor 680 _ 0 switchably connected in parallel with capacitor 680 _ 1 , 680 _ 2 , . . . 680 _N through respective switches 680 _Ga_ 1 , 680 _Ga_ 2 , . . . 680 _Ga_N. In another aspect, variable capacitors 680 may not be included in an APS systems 400 in which there is not desire to perform average and weighted sum operations.

[0043] An APS system 400 , as shown in FIGS. 3-6 , can combine at least two sets of pixel signals received from different column buffer circuits 432 , 434 , 436 in the charge domain prior to the signals being digitized. The differential output of a conventional APS system 100 is described above in Eq. (1). The present invention, which combines sets of signals received from at least two column buffer circuits, provides the following output signal: 1 $\begin{array}{cc}\mathrm{Vout}=\sum _i^N\left[{\alpha }_iCs_i/Cf\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]& \left(2\right)\\ =\sum _i^N\left[{\alpha }_iCs_i/Cf\left({\mathrm{Vdiff}}_i\right)\right]& \left(3\right)\end{array}$

[0044] i corresponds to the number of column buffer circuits that are combined and can range from i=1 (e.g., a single column buffer circuit) to i=N (e.g., any number of column buffer circuits). ( FIG. 2 .)

[0045] α _i represents the polarity of the i ^th column buffer circuit and is either 1 or −1. If α _i =1, then the polarity of the signals is normal. For example, when a column buffer circuit 436 has a normal polarity, then a signal Vin_p carried at input 210 would be stored on capacitor 622 and a signal Vin_n carried at input 212 would be stored on capacitor 626 . If α _i =−1, then the polarity of the signals are inverted. For example, when a column buffer circuit 436 has a reverse polarity, then a signal Vin_p carried at input 210 would be stored on capacitor 626 and a signal Vin_n carried at input 212 would be stored on capacitor 622 . For example, during a subtraction operation a first set of signals is subtracted from a second set of signals. To implement this operation the first set of signals is ‘negatived’ and added to the second set of signals. The first set of signals is ‘negatived’ by inverting the polarity of the first set of signals (i.e., reversing the Vin-p and Vin-n signals), which is represented in Eq. 3 by the α of the first set of signals being equivalent to “−1”).

[0046] Cs _i corresponds to the capacitance of capacitors 622 , 626 of the i ^th column buffer circuit. Cf corresponds to the capacitance of feedback capacitors 680 , 678 of the gain stage circuit 455 .

[0047] Vdiff _i corresponds to the differential output of a differential amplifier receiving a set of signals from the i ^th column buffer.

[0048] To implement an addition operation on a plurality of sets of signals received from a plurality of column buffer circuits, the signals stored in respective capacitors 622 from the selected columns buffer circuits are combined in the gain stage circuit 455 , and the signals stored in respective capacitors 626 from the selected columns buffer circuits are combined in the gain stage circuit 455 . The signals stored in respective capacitors 622 from the selected columns buffer circuits are combined by coupling the respective capacitors 622 at substantially the same time to each other and also each variable capacitor 678 from gain circuit 455 . Similarly, the signals stored in respective capacitors 626 from the selected columns buffer circuits are combined by coupling the respective capacitors 626 at substantially the same time to each other and also to variable capacitor 680 from gain circuit 455 .

[0049] For example, all the selected Vin_p signals are combined and all the selected Vin_n signals are combined. Based on Eq. 2, α _i =1, i.e., no reverse polarity, and Cs _i =Cf. (i.e., no gain between capacitors), then: 2 $\begin{array}{cc}\mathrm{Vout}=\sum _i^N\left[{\alpha }_iCs_i/Cf\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]=\sum _i^N\left[\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]=\sum _i^N{\mathrm{Vdiff}}_i& \left(4\right)\end{array}$

[0050] Therefore, the output of the gain stage 455 is the difference between the combined signals, i.e., the difference between the combined signals from respective capacitors 622 and the combined signals from respective capacitors 626 that are input to the gain stage 455 .

[0051] To implement a subtraction operation, a set of signals received from a first selected column buffer circuit(s) are combined with a set of inverted signals received from a second selected column buffer circuit. For example, to subtract signals stored in column buffer circuit 434 from the signals stored in column buffer circuit 436 , the signals stored in column buffer circuit 434 are inverted when they are stored. For instance, the Vin_p input at 210 is stored on capacitor 626 of column buffer circuit 434 and the Vin_n input at 212 is stored on capacitor 622 of column buffer circuit 434 .

[0052] The signals stored in column buffer circuit 436 are not inverted when they are stored. The Vin_p input at 210 is stored on capacitor 622 of column buffer circuit 436 and the Vin_n input at 212 is stored on capacitor 626 of column buffer circuit 436 . Therefore, when the sets of signals received from the column buffer circuits 434 , 436 are combined in the gain stage 455 , Vin_p of column buffer circuit 436 stored on capacitor 622 is combined with Vin_n of column buffer circuit 434 stored on capacitor 622 . And Vin_n of column buffer circuit 436 stored on capacitor 626 is combined with Vin_p of column buffer circuit 434 stored on capacitor 626 . With reference to Eq. 2, α _i =−1, e.g., inverted polarity where the differential output of the i ^th column buffer circuit is sought to be reversed (i.e., negatived) (e.g., if column buffer circuit 434 corresponds to i=1 and column buffer circuit 436 corresponds to i=2, then α ₁ =−1 and α ₂ =1), and Cs _i =Cf; e.g., no gain between capacitors, and N=2 (i.e., since there are two column buffer circuits 434 , 436 that are being combined), then: 3 $\begin{array}{cc}\mathrm{Vout}=\sum _i^N\left[{\alpha }_iCs_i/Cf\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]=\sum _i^N\left[\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]={\mathrm{Vdiff}}_i-{\mathrm{Vdiff}}_2& \left(5\right)\end{array}$

[0053] Therefore the output of the gain stage 455 is the difference between the combined signals, i.e., the difference between the signals from column buffer circuit 434 and the signals from column buffer circuit 436 . The difference is determined between the combined signals by combining the signals in two groups, where the first group of combined signals constitutes Vin_p of column buffer circuit 436 stored on capacitor 622 and Vin_n of column buffer circuit 434 stored on capacitor 622 (i.e., combining the signals received from respective capacitors 622 ) and the second group of combined signals constitutes Vin_n of column buffer circuit 436 stored on capacitor 626 and Vin_p of column buffer circuit 434 stored on capacitor 626 (i.e., combining the signals received respective capacitors 626 ). And then determining the difference between the two groups.

[0054] To implement an average operation, similar to an addition operation, the signals stored in respective capacitors 622 from the selected columns are combined in the gain stage circuit 455 , and the signals stored in respective capacitors 626 from the selected columns are combined in the gain stage circuit 455 . Additionally, the capacitance of the respective sampling capacitor 622 , 626 is established as a ratio of a respective feed back capacitor 678 , 680 .

[0055] For example, all of the selected Vin_p signals are combined, all of the selected Vin_n are combined, then a difference of all of the combined signals is determined. Each respective signal, e.g., Vin_p, Vin_n, is weighted relative to the number of column buffer circuits being averaged. With reference to Eq. 2, α _i =1, (i.e., no inverted polarity), and Cs _i =1/N (Cf), where N is the number of column buffer circuits being averaged, then: 4 $\begin{array}{cc}\mathrm{Vout}=\sum _i\left[{\alpha }_iCs_i/Cf\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]=\sum _i\left[\left(1/N\right)\left(Cf\right)\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]=1/N\sum _i{\mathrm{Vdiff}}_i& \left(6\right)\end{array}$

[0056] Therefore the output of the gain stage 455 is the difference between the combined signals divided by the number of column buffer circuits that are combined, i.e., the difference between the combined signals received from respective capacitors 622 and the combined signals received from respective capacitors 626 that are input to the gain stage divided by the number of column buffer circuits that are combined. A differential amplifier receives the combined values in two groups (e.g., the first group being the combined signals received from capacitors 622 , the second group being the combined signals received from capacitors 626 ) and provides a differential output of these two groups of signals.

[0057] Implementing a weighted sum operation is similar to implementing an average operation, however, the biasing potential of the variable capacitors is used. In the weighted sum operation, Cs _i =W _i (Cf), where W _i is the weight factor of the i ^th column buffer circuit: 5 $\begin{array}{cc}\mathrm{Vout}=\sum _i\left[{\alpha }_iCs_i/Cf\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]=\sum _i\left[\left(W_i\right)\left(\mathrm{Vin\_p}-\mathrm{Vin\_n}\right),i\right]=\sum _iW_i\left({\mathrm{Vdiff}}_i\right)& \left(7\right)\end{array}$

[0058] Therefore, the output of the gain stage 455 is the weighted difference between the combined signals, i.e., the difference between the combined signals from respective capacitors 622 and the combined signals from respective capacitors 626 that are input to the gain stage and weighted by the ratio of the respective variable capacitors 622 and 678 or 626 and 680 .

[0059] Turning to FIG. 7 an addition operation implemented by the operation of the FIGS. 3-6 circuits is now described. In this example, it is assumed that the values stored by the column buffer circuit 434 are being combined with the values stored by the column buffer circuit 436 .

[0060] With reference to FIG. 7 , various signals are shown over two defined time intervals 990 , 992 . The first time interval 990 is a sample and hold time interval. During sample and hold time interval 990 the sampling capacitors 622 , 626 of each respective column buffer circuit 434 , 436 are charged with respect to the clamp voltage to the respective voltages present at the first and second inputs 210 , 212 of the respective column buffer circuit 434 , 436 .

[0061] The second time interval 992 is a read out time interval. During the read out time interval 992 the sampling capacitors 622 , 626 of column buffer circuit 434 are transferred to the respective inputs of the gain stage 455 through respective selection switches 232 , 240 of column buffer circuit 434 . Also during the read out time interval 992 the sampling capacitors 622 , 626 of column buffer circuit 436 are transferred to the respective inputs of the gain stage 455 through respective selection switches 232 , 240 of column buffer circuit 436 . In the gain stage 455 the set of signals received from column buffer circuit 436 is combined with the set of signals received from column buffer circuit 434 .

[0062] Throughout FIG. 7 a logic high signal indicates that a corresponding switch of FIGS. 3-6 is closed (conductive), while a logic low signal indicates that the corresponding switch of FIGS. 3-6 is open (non-conductive). Signal 906 SHR corresponds to the state of sampling switch 214 in both column buffer circuits 434 , 436 . Signal 912 SHR corresponds to the state of sampling switch 216 in both column buffer circuits 434 , 436 . Signal 916 CLAMP corresponds to the state of clamp voltage switches 230 and 238 in both column buffer circuits 434 , 436 . Signal 922 RESET corresponds to the state of reset switches 674 , 676 . Signal 928 SEL 1 corresponds to the state of selection switches 232 and 240 in column buffer circuit 434 . Signal 932 SEL 2 corresponds to the state of selection switches 232 and 240 in column buffer circuit 436 . Signal 936 CB 1 corresponds to the state of crawbar switch 218 in column buffer circuit 434 . Signal 940 CB 2 corresponds to the state of crawbar switch 218 in column buffer circuit 436 .

[0063] No signals are shown for variable capacitors 622 , 626 , 678 , 680 in the example provided because no variability in the variable capacitors 622 , 626 , 678 , 680 is being demonstrated. Furthermore, in the addition operation being illustrated, the reverse polarity circuit 695 does not invert the polarity of any signals. Therefore, switches 692 , 694 are closed and conducting, and switches 690 , 696 are open and non-conducting.

[0064] As indicated in FIG. 7 , initially all switches are open (non-conductive) except for reset switches 674 and 676 . During a time interval 918 , the CLAMP signal goes logic high and switches 230 and 238 close to charge capacitors 622 and 626 in each respective column buffer circuit 434 , 436 to the clamp voltage supplied by clamp voltage source 234 . While the clamp switches 230 , 238 in each respective column buffer circuit 434 , 436 are closed, sampling switch 214 in each respective column buffer circuit 434 , 436 closes for a first time interval 908 and, subsequently, sampling switch 216 in each respective column buffer circuit 434 , 436 closes for a second time interval 913 . As a result, the other side of capacitors 622 and 626 in each column buffer circuit is charged to the respective voltage levels of Vin_p and Vin_n.

[0065] Selection switches 232 and 240 in column buffer circuit 434 then close for the duration of time interval 930 . At substantially the same time, during time interval 932 , selection switches 232 and 240 in column buffer circuit 436 close. During time intervals 930 and 932 , reset switches 674 and 676 open, and remain open for a time interval 924 that extends until a time after the end of time interval 930 and 932 . Shortly after the reset switches 674 and 676 open, and while the selection switches 232 , 240 of both column buffer circuits 434 , 436 are closed, crawbar switches 218 in column buffer circuits 434 , 436 close at substantially the same time for respective time intervals 938 , 942 . Time intervals 938 , 942 end prior to the end of respective time interval 930 , 932 .

[0066] Summarizing the FIG. 7 cycle, during the sample and hold time interval 990 , Vsig and Vrst signals are acquired from a pixel cell 104 and stored on first and second sampling capacitors 622 , 626 in column buffer circuit 436 . Also during the sample and hold time interval 990 , Vsig and Vrst signals are acquired from a different pixel cell 104 and stored on first and second sampling capacitors 622 , 626 in column buffer circuit 434 .

[0067] During read out time interval 992 , the set of signals received from the column buffer circuit 436 is combined with the set of signals received from the column buffer circuit 434 in the gain stage 455 .

[0068] FIG. 8 shows another timing diagram for implementing an addition operation with the APS array and associated processing circuitry of FIGS. 3-6 . The operation of FIG. 8 differs from the operation of FIG. 7 in that the signals SEL, CB are staggered.

[0069] Turning to FIG. 9 a subtraction operation implemented by the operation of the FIGS. 3-6 circuits is now described. In this example, it is assumed that the values stored by the column buffer circuit 434 are being subtracted from the values stored by the column buffer circuit 436 . The FIG. 9 subtraction operation is similar to the FIG. 7 addition operation except that the reverse polarity circuit is utilized.

[0070] Signal 1260 corresponds to the state of switches 692 , 694 in column buffer circuit 434 and signal 1264 corresponds to the state of switches 690 , 696 in column buffer circuit 434 . Signal 1270 corresponds to the state of switches 692 , 694 in column buffer circuit 436 and signal 1274 corresponds to the state of switches 690 , 696 in column buffer circuit 436 .

[0071] As indicated in FIG. 9 , initially all switches are open (non-conductive) except for reset switches 674 and 676 . During a time interval 1218 the CLAMP signal goes logic high and clamp switches 230 and 238 close to charge capacitors 622 and 626 in each respective column buffer circuit 434 , 436 to the clamp voltage supplied by clamp source 234 . While the clamp switches 230 , 238 in each respective column buffer circuit 434 , 436 are closed, sampling switch 214 in each respective column buffer circuit 434 , 436 closes for a first time interval 1208 and, subsequently, sampling switch 216 in each respective column buffer circuit 434 , 436 closes for a second time interval 1213 .

[0072] While the clamp switches 230 , 238 in each respective column buffer circuit 434 , 436 are closed, switches 690 , 696 in column buffer circuit 434 and switches 692 , 694 in column buffer circuit 436 close for representative time intervals 1266 , 1272 . Time intervals 1266 , 1272 begin before time intervals 1208 , 1213 begin and ending after time intervals 1208 , 1213 end. Thereafter, both clamping switches 230 , 238 in each respective column buffer circuit 434 , 436 open. As a result, the other side of capacitors 622 and 626 in column buffer circuit 436 are charged to the respective voltage levels of Vin_p and Vin_n. And correspondingly, the other side of capacitors 622 and 626 in column buffer circuit 434 are charged to the respective voltage levels of Vin_n and Vin_p.

[0073] Selection switches 232 and 240 in column buffer circuit 434 close for the duration of time interval 1230 . Selection switches 232 and 240 in column buffer circuit 436 close for the duration of time interval 1232 . During time interval 1230 and 1232 , reset switches 674 and 676 open, and remain open for a time interval 1224 that extends until a time after the end of time interval 1230 and 1232 . Shortly after the reset switches 674 and 676 open, crawbar switches 218 in column buffer circuits 434 , 436 close for respective time intervals 1238 , 1242 that ends prior to the end of respective time interval 1230 , 1232 .

[0074] Summarizing the FIG. 9 cycle, during the sample and hold time interval 1290 , Vsig and Vrst signals are acquired from a pixel cell 104 and respectively stored on first and second sampling capacitors 626 , 622 in column buffer circuit 436 respectively. Also during the sample and hold time interval 1290 , Vrst and Vsig signals are acquired from a different pixel cell 112 and respectively stored on first and second sampling capacitors 626 , 622 in column buffer circuit 434 respectively.

[0075] During read out time interval 1292 , the values stored on first sampling capacitors 622 , in column buffer circuits 436 and 434 are combined by the closure of the crawbar switch 218 in each respective column buffer circuit 436 , 434 , and applied to the respective input of the gain stage 455 . Also during read out time interval 1292 , the values stored on second sampling capacitors 626 , in column buffer circuits 436 and 434 are combined by the closure of the crawbar switch 218 in each respective column buffer circuit 436 , 434 , and applied to the respective input of the gain stage 455 . Thus, the set of signals received from the column buffer circuit 434 is subtracted from the set of signals received from the column buffer circuit 436 in the gain stage 455 .

[0076] FIG. 10 shows another subtraction operation implemented by the operation of the FIGS. 3-6 circuits. The operation of FIG. 10 differs from the operation of FIG. 9 in that the signals SEL, CB are staggered.

[0077] Turning to FIG. 11 an average operation implemented by the operation of the FIGS. 3-6 circuits is now described. In this example, it is assumed that the values received from column buffer circuit 434 are being averaged with the values received from column buffer circuit 436 . The FIG. 11 average operation is similar to the FIG. 7 addition operation except that the variable capacitors ( 680 , 678 of FIG. 6 ) are enabled. The capacitance values of the variable capacitors are established such that each respective variable capacitor Csi=(1/N) Cf.

[0078] Signal 1560 corresponds to the state of switches 692 , 694 in both buffer column circuits 434 , 436 . Signal 1564 corresponds to the state of switches 690 , 696 in both buffer column circuits 434 , 436 . Signal 1570 G 1 corresponds to the state of switch G 1 in both buffer column circuits 434 , 436 . Signal 1574 G 2 corresponds to the state of switch G 2 in both buffer column circuits 434 , 436 . Signal 1576 GN corresponds to the state of switch GN in both buffer column circuits 434 , 436 . Signal 1580 Ga 1 corresponds to the state of switches Ga 1 in gain stage 455 . Signal 1584 Ga 2 corresponds to the state of switches Ga 2 in gain stage 455 . Signal 1586 GaN corresponds to the state of switches GaN in gain stage 455 .

[0079] As indicated in FIG. 11 , initially all switches are open (non-conductive) except for reset switches 674 and 676 . During a time interval 1518 the CLAMP signal goes logic high and switches 230 and 238 close to charge capacitors 622 and 626 in each respective column buffer circuit 434 , 436 to the CLAMP voltage supplied by clamp voltage source 234 . While the clamp switches 230 , 238 in each respective column buffer circuit 434 , 436 are closed, sampling switch 214 in each respective column buffer circuit 434 , 436 closes for a first time interval 1508 and, subsequently, sampling switch 216 in each respective column buffer circuit 434 , 436 closes for a second time interval 1513 . While the clamp switches 230 , 238 in each respective column buffer circuit 434 , 436 are closed, switches 692 , 694 in column buffer circuit 436 close for time interval 1562 beginning before time intervals 1508 , 1513 begin and ending after time intervals 1508 , 1513 end. Thereafter, both clamping switches 230 , 238 in each respective column buffer circuit 434 , 436 open. As a result, the other side of capacitors 622 and 626 in column buffer circuits 434 , 436 are charged to the respective voltage levels of Vin_p and Vin_n.

[0080] Selection switches 232 and 240 in column buffer circuit 434 then close for the duration of time interval 1530 . During the time interval 1532 selection switches 232 and 240 in column buffer circuit 436 close at substantially the same time. During time intervals 1530 and 1532 , reset switches 674 and 676 open, and remain open for a time interval 1524 that extends until a time after the end of time interval 1530 and 1532 . Shortly after the reset switches 674 and 676 open, and while the selection switches 232 , 240 of both column buffer circuits 434 , 436 are closed, crawbar switches 218 in column buffer circuits 434 , 436 close at substantially the same time for respective time intervals 1538 , 1542 . The time intervals 1538 , 1542 end prior to the end of respective time interval 1530 , 1532 .

[0081] Summarizing the FIG. 11 cycle, during the sample and hold time interval 1590 , Vsig and Vrst signals are acquired from a pixel cell 104 and stored on first and second variable sampling capacitors 622 , 626 in column buffer circuit 436 . Also during the sample and hold time interval 1590 , Vrst and Vsig signals are acquired from a different pixel cell 104 and stored on first and second variable sampling capacitors 622 , 626 in column buffer circuit 434 . During read out time interval 1592 , the set of signals received from the column buffer circuit 434 is averaged with the set of signals received from the column buffer circuit 436 .

[0082] Turning to FIG. 12 a weighted sum operation implemented by the operation of the FIGS. 3-6 circuits is now described. In this example, it is assumed that the values stored by the column buffer circuit 434 are being weighted and combined with the values stored by the column buffer circuit 436 which are also weighted. The FIG. 12 weighted sum operation differs from the FIG. 11 average operation in that the weight associated with column buffer circuit 434 may be different from the weight associated with the column buffer circuit 436 . Therefore, the various control signals that correspond to the variable capacitors of column buffer circuit 434 may be different from the various control signals that correspond to the variable capacitors of the column buffer circuit 436

[0083] In the average operation described above, Csi=1/N (Cf), however, in the weighted sum operation, Wi=Cf/ Csi, (i.e., the weighting factor corresponding to the ith set of signals received from the ith column buffer circuit being the ratio of the feedback capacitors to the capacitors in the ith column buffer circuit) where Wi may not be substantially the same as Wi+1. FIG. 12 depicts the linear operation implemented by the FIGS. 3-6 circuits combining signals received from column buffer circuit 434 with signals received from column buffer circuit 436 , where the respective signals received from each column buffer circuit 434 , 436 is weighted differently.

[0084] In FIG. 12 , signal 1670 G 1 corresponds to the state of switch G 1 in buffer column circuit 434 . Signal 1674 G 2 corresponds to the state of switch G 2 in buffer column circuit 434 . Signal 1676 GN corresponds to the state of switch GN in buffer column circuit 434 . Signal 1680 G 1 corresponds to the state of switch G 1 in buffer column circuit 436 . Signal 1684 G 2 corresponds to the state of switch G 2 in buffer column circuit 436 . Signal 1686 GN corresponds to the state of switch GN in buffer column circuit 436 . Thus, in the example of the FIG. 12 operation of the FIGS. 3-6 circuit, combination of capacitors used in column buffer circuit 434 is different from the combination of capacitors used in column buffer circuit 436 . Thus the capacitance value of the variable capacitor in column buffer circuit 434 is different from the capacitance value used in column buffer circuit 436 . Consequently, the signals received from column buffer circuit 434 is weighted differently than the signals received from column buffer circuit 436 .

[0085] FIG. 13 shows a portion of the FIG. 3 block diagram in greater detail in accordance with another exemplary embodiment of the invention. The gain stage 1755 of FIG. 13 differs from the gain stage 455 of FIGS. 3 and 4 in the inclusion of a second amplifier 1765 . The gain stage circuit 1755 has two pipelined amplifiers 1764 , 1765 with corresponding respective reset switches 1776 , 1774 , 1777 , 1775 and feedback capacitors 1780 , 1778 , 1781 , and 1779 . Furthermore, the respective outputs of the first amplifier 1764 are coupled through capacitor 1790 , 1791 to the respective inputs of the second amplifier 1765 .

[0086] Having more than one amplifier in the gain stage 1755 improves the ability to provide a differential output. This improvement is due to the increase in the gain of the signals before the signals are processed by the differential amplifier. The dual amplifier setup also enables a more variable ratio between the variable capacitors 622 , 626 in the column buffer circuits 432 , 434 , 436 and the variable capacitors 1778 , 1780 , 1779 , 1781 in the gain stage 1755 .

[0087] FIG. 14 shows a portion of the FIG. 3 block diagram in greater detail in accordance with yet another exemplary embodiment of the invention. The gain stage 1855 of the FIG. 14 circuit differs from the gain stage 455 of the FIG. 3 circuit in several significant ways and which will be described in detail below.