DETAILED DESCRIPTION OF THE INVENTION AND PREFERRED EMBODIMENTS

[0073] A method of the present invention in which a minute hole with an aspect ratio of 13 or higher is formed in a silicon oxide film, using a hard mask, while preventing or suppressing a shape defect called the bowing, is described below.

[0074] FIG. 1 is a series of cross-sectional views as well as a bird's eye view in explaining the steps of First Embodiment.

[0075] There is provided a silicon substrate 100 on which a polysilicon film 102 that is to be used as a hard mask for etching is formed, overlying an oxide silicon film 101.

[0076] Next, by means of photolithography, an opening is set in a photoresist formed on the polysilicon 102 and, through that opening, the polysilicon 102 is dry etched to form a hard mask for etching. After that, the photoresist is removed (FIG. 1(1))

[0077] The polysilicon 102 can be replaced by Si₃N₄, SiGe or Ge.

[0078] Through the hard mask, a first etching is applied thereto and a hole (an opening section) with an aspect ratio of 7 to 12 where no bowing occurs is formed in the silicon oxide film 101 (FIG. 1(2)). Next, a Si₃N₄ film 103 is formed by the low pressure CVD method (FIG. 1(3)). Instead of the Si₃N₄ film, a silicon oxynitride film, a polysilicon film, a SiGe film or a Ge film can be used.

[0079] Next, the entire surface thereof is dry etched and the Si₃N₄ film 103 formed on the polysilicon 102 and on the bottom face of the hole is removed (FIG. 1(4)).

[0080] The Si₃N₄ film 103 remaining on the sidewall of the hole is required to cover at least in the place of the hole corresponding to the aspect ratios of 2 to 7 where the bowing is liable to occur. After that, by applying a second etching thereto, the Si₃N₄film 103 remaining on the lateral face of the hole is removed, while the silicon oxide film 101 is dry etched (FIG. 1(5)), and an opening to reach the silicon substrate 100 is formed (FIG. 1(6)).

[0081] FIG. 1(5) herein is a view depicting a state in which the Si₃N₄ film 103 is etched simultaneously with the silicon oxide film 101 by the second etching.

[0082] In the present embodiment, by the entire surface etching (in the case that the entire surface etching and the second etching have the same etching conditions, the initial state of the second etching), the Si₃N₄ film 103 is etched back and a sidewall of the Si₃N₄ film is formed on the surface of the hole wall. The side wall Si₃N₄ film is simultaneously removed when the silicon oxide film is etched still deeper by the second etching. If the sidewall Si₃N₄ film is completely etched away before formation of the hole to reach the silicon substrate 100 is completed, a bowing may occur so that the thickness of the Si₃N₄ film must be set appropriately so as not to allow such a thing happening.

[0083] Apart from the film thickness of the Si₃N₄ film, the condition of the etching selection ratio between the Si₃N₄ film and the silicon oxide film can be met, needless to say, by a set of two different conditions, etching conditions for the entire surface etching of the Si₃N₄ film and etching conditions for the etching of the silicon oxide film.

[0084] In the present embodiment, since, even if a hole to reach the silicon substrate is formed and its aspect ratio exceeds the aspect ratio of 13 with which a bowing is liable to occur, the very place of the hole wall surface where the bowing is liable to occur is covered with the Si₃N₄ film whose etching selection ratio is lower than that of the oxide film, the hole wall surface cannot be subjected to the aberrant etching till the Si₃N₄ film is removed and no bowing develops.

[0085] Although the silicon oxide film 101 in FIG. 1 is formed immediately above the silicon substrate 100, it goes without saying that a semiconductor element, an interconnection, an insulating film or the like formed on a silicon substrate 100 can be laid under the silicon oxide film 101.

[0086] To suppress the bowing from developing in the opening by the second etching, the etching rate in the horizontal direction for the Si₃N₄ film is preferably equal to or less than {fraction (1/10)} of the etching rate in the horizontal direction for the silicon oxide film.

[0087] A modified embodiment of First Embodiment is shown in FIG. 2.

[0088] In FIG. 2, there is formed a Si₃N₄ film 104, which is to function as an etching stopper, between a first silicon oxide film 101-1 and a second silicon oxide film 101-2.

[0089] The silicon oxide films 101-1 and 101-2 can be made of silicon oxide being formed by the CVD method, non-doped silicate glass, silicate glass containing at least either of boron and phosphorus or silicon oxide which is formed by sintering a coating of siloxane applied thereto by the spin-on-glass method.

[0090] As shown in FIG. 1(1), a polysilicon film 102 is set to be used as a hard mask for dry etching (FIG. 2(1)) and an oxide film 101-2 being dry etched by a first dry etching, a hole is formed so as to reach a Si₃N₄ film 104 (FIG. 2(2)). Next, a Si₃N₄ film 103 is formed by the low pressure CVD method (FIG. 2(3)).

[0091] Next, the entire surface thereof is dry etched and the Si₃N₄ film103 formed on the polysilicon 102 and on the bottom face of the hole as well as the Si₃N₄ film 104 lying on the bottom face of the hole, which acts as an etching stopper, are removed (FIG. 2(4)). After that, by applying a second etching thereto, the Si₃N₄film 103 remaining on the wall surface of the hole is removed, while the silicon oxide film 101-1 is dry etched (FIG. 2(5)) and an opening to reach the silicon substrate 100 is formed (FIG. 2(6)).

[0092] Needless to say, the entire surface dry etching and the second dry etching can be performed continuously under the same conditions.

[0093] In the present embodiment, at the time of the first etching, because etching is stopped at the etching stopper layer, overetching does not happen. Accordingly, it is possible to provide some extra time in the step of bringing the etching to a halt. Further, anisotropic etching normally forms the diameter at the hole bottom narrower than that at the top of the hole. When an etching stopper layer is set, etching in the direction of the depth is stopped once and thereafter etching in the horizontal direction starts at the hole bottom, and, therefore, the cross-section of the hole can take the form of more regular rectangle.

[0094] In the present embodiment, in the second half of the hole etching of the silicon oxide film when a bowing is liable to occur, a sidewall Si₃N₄ film is provided for the upper section of the hole which is the very place that the bowing is liable to appear so that the bowing can be prevented or suppressed from occurring. The sidewall Si₃N₄ film formed on the sidewall of the hole may be removed while the silicon oxide film 101-1 is etched in the second half of the second hole etching.

[0095] In the above description of the present embodiment, the Si₃N₄ film formed on the sidewall of the hole is completely removed when the formation of the hole is accomplished. However, in the case of a via hole for connecting an upper layer interconnection with a lower layer interconnection, the Si₃N₄ film can be left on the wall surface of the hole.

[0096] If the situation allows the Si₃N₄ film to remain on the wall surface of the hole, the Si₃N₄ film 103 can be formed to have a substantial thickness.

[0097] The material of the sidewall formed on the wall surface of the hole can be, apart from the Si₃N₄ film, any material whose etching rate is lower than the etching rate of the material that is to be used to fill up the hole, and must be appropriately chosen, depending on the hole filling material.

[0098] In the case that the hole filling material is a silicon oxide film, a silicon oxynitride film, a polysilicon film, a SiGe film, a Ge film or the like can be used as the sidewall material, apart from a Si₃N₄ film.

EXAMPLE 1

[0099] As First Example of the present invention, a manufacturing method of a cylindrical capacitor of a DRAM is described below, referring to FIG. 5.

[0100] On a silicon substrate 100, a Si₃N₄ film 105 that is to be used as a bottom film of a cylindrical capacitor when formed is grown by the low pressure CVD method and thereon a silicon oxide film 101 that is to be used as a capacitor film of the cylindrical capacitor is formed to a thickness of 2 μm by the low pressure CVD method.

[0101] An underlying layer of the Si₃N₄ film 105 that is to function as a bottom film of the cylindrical capacitor varies with the structure of the DRAM but, herein, it is omitted because it is not particularly related to the present example.

[0102] The thickness of the silicon oxide film or the depth of the hole into which a cylindrical capacitor is to be formed is the parameter of the utmost importance to determine the amount of the capacitance of the cylindrical capacitor. Viewed in the light of device characteristics, a large capacitance is normally preferable so that the film thickness is set to be as thick as possible within the range of the workable thickness and, thus, not limited to 2 μm.

[0103] As a hard mask, a polysilicon film 102 with a thickness of 100 nm to 150 nm is grown immediately above the silicon oxide film 101. This film functions as a mask when dry etching is applied to the silicon oxide film, and may be a film made of a material with an etching rate lower than that of the silicon oxide film. Apart from polysilicon, doped polysilicon, Si₃N₄, SiGe, Ge or such can be employed therefor.

[0104] These silicon oxide films and polysilicon films can be formed also by the plasma CVD method.

[0105] Next, patterning (exposure, development and such) is carried out by a known technique of lithography. When the minimum diameter of the hole pattern is 0.15 μm, the aspect ratio becomes 13.3 (2 μm/0.15 m=13.3).

[0106] Next, using a photoresist as a mask, dry etching for formation of a polysilicon hard mask is performed. After dry etching, remaining photoresists, etching deposition residuals and the likes are removed with a SPM (a mixed solution of sulfuric acid and hydrogen peroxide), an APM (a mixed solution of ammonia and hydrogen peroxide), a diluted hydrofluoric acid solution or the like.

[0107] These dry etching conditions for the polysilicon are ordinary ones and an anisotropic etching treatment may be made with a chlorine-based mixed gas, a mixed gas containing HBr or the like.

[0108] Next, a treatment is made using a two-frequency type RIE (Reactive Ion Etching) apparatus shown in FIG. 6. The apparatus is characterized by the presence of two types of RF (Radio Frequency) generators, providing an upper band of RF frequencies between 13.56 MHz and 100 MHz and a lower band of RF frequencies between 400 KHz and 2 MHz, and, in recent years, has been used widely by the present inventors.

[0109] Firstly, a first etching of the silicon oxide film is performed. The details of the conditions are as follows.

[0110] Wafer susceptor temperature: 40° C. to 60° C.

[0111] C₄F₈ (Fluorocarbon gas such as C₅F₈ , C₄F₆ can be also used): 20 sccm to 40 sccm (standard cubic centimeters minute)

[0112] Ar: 500 sccm to 800 sccm

[0113] O₂: 20 sccm to 40 sccm

[0114] Upper RF: 1000 W to 2000W

[0115] Lower RF: 1000 W to 2000 W

[0116] Under these conditions, the etching rate ratio in the direction of the depth, that is, the etching rate of the oxide film/the etching rate of the Si₃N₄ film is approximately 10, while the etching rate ratio in the horizontal direction is approximately 20.

[0117] After the first etching of the silicon oxide film, a state shown in FIG. 5(2) is obtained. The depth possible to be etched while keeping a bowingless state corresponds to an aspect ratio of 7 to 12. In other words, in the present example with an aperture of 0.15 μm, down to a depth of 1.05 μm to 1.8 μm a bowing does not occur. Accordingly, the depth for the first etching of the silicon oxide film may be set to be 1.05 μm to 1.8 μm. Meanwhile, in a hole with an aspect ratio of 12 or greater, the place where a bowing occurs has a depth equivalent to aspect ratios of 2 to 7, and when an aperture of the hole is 0.15 μm, this corresponds to a region at depths of 300 nm to 1.05 μm. It is this place a bowing is liable to occur that a sidewall which is to be set in the next step is required to be formed. In effect, when the depth of the first etching is set to be 1.05 μm to 1.8 μm, the sidewall Si₃N₄ film which is to be formed in the next step can be optimally set in the very place where a bowing is liable to occur when the second etching is made.

[0118] In the present example, the etching was carried our for the time period calculated from the etching rate so as to reach the depth of 1.5 μm or so.

[0119] Under the first etching conditions, fluorocarbon gas is employed. The dry etching with fluorocarbon gas is liable to leave fluorocarbon-based deposition residuals on the wafer surface. It is therefore preferable to remove, after the etching, reaction products using the plasma peeling-off method or a solution such as a diluted hydrofluoric acid solution, an APM or a SPM.

[0120] Next, a Si₃N₄ film with a thickness of 4 nm is formed by the low pressure CVD method so as to have a uniform thickness (FIG. 5(3)). For this, it is also possible to use any other method than the low pressure CVD method as long as a film of dense quality (excelling in etching resistance) with a capability to provide good coverage (a high conformability) can be obtained.

[0121] In the present example, a Si₃N₄ film with a thickness of 4 nm was formed. This can be explained from a fact that, in removing the silicon oxide by the second etching, if the Si₃N₄ film formed on the wall surface of the hole is removed prior to the completion of the hole, there occurs a bowing. The actual thickness of the Si₃N₄ film is determined, depending on the conditions of the second etching, but a film thickness of 2 nm to 5 nm is, in general, suitable.

[0122] At the time the opening just reaches the silicon substrate 100, the opening is taper-shaped. The aperture of the opening on the side of the substrate is narrow and the contact resistance, when filled up, becomes high. Overetching is preferably performed until the aperture of the opening on the side of the substrate becomes the same as that of the top. The film thickness is, therefore, preferably set, taking overetching into consideration. The film thickness of 4 nm set in the present example is the one obtained under the condition that overetching is performed for approximately 20 seconds after the hole reaches the silicon substrate 100. The overetching condition differs in etching conditions as well as the etching apparatus and it is apparent that an actual value must be set appropriately, independent of the value obtained in the present example.

[0123] Next, applying dry etching to the entire surface thereof, portions of the Si₃N₄ film 103 formed on the surface of the polysilicon that is to be used as a hard mask as well as on the bottom of the hole are removed (FIG. 5(4)). After that, second dry etching is performed consecutively to remove the silicon oxide 101 and form a hole down to reach the Si₃N₄ film 105 that is to become a bottom film of a cylindrical capacitor (FIG. 5(5)). In the present example, the opening which is not taper-shaped but rectangular was successfully formed.

[0124] In the present example, for the entire surface dry etching and the second etching, the same conditions as for the first etching are employed.

[0125] In this way, formation of a hole for a bowingless cylindrical capacitor with a high aspect ratio can be accomplished.

EXAMPLE 2

[0126] Referring to FIG. 9, Second Example, which is a modified example of First Example, is described below.

[0127] In FIG. 9, differing from in FIG. 5, a Si₃N₄ film 104, which is to function as an etching stopper, is formed in a layer 101 of silicon oxide through which a hole for a cylindrical capacitor is formed.

[0128] On a silicon substrate 100, a Si₃N₄ film 105 that is to be used as a bottom film of a cylindrical capacitor when formed is grown by the low pressure CVD method and thereon a lower layer of silicon oxide 101-1 with a thickness of 0.5 μm, a Si₃N₄ layer 104 with a thickness of 15 nm which is to function as an etching stopper, an upper layer of silicon oxide 101-2 with a thickness of 1.5 μm and a polysilicon film 102 with a thickness of 100 nm which is to be used as a hard mask are formed, in this order, by the low pressure CVD method or the plasma CVD method.

[0129] An underlying layer of the Si₃N₄ film 105 that is to function as a bottom film of the cylindrical capacitor varies with the structure of the DRAM but, herein, it is omitted because it is not particularly related to the present example.

[0130] The thickness of the silicon oxide film or the depth of the hole into which a cylindrical capacitor is to be formed is the parameter of the utmost importance to determine the amount of the capacitance of the cylindrical capacitor. Viewed in the light of device characteristics, a large capacitance is normally preferable so that the film thickness is set to be as thick as possible within the range of the workable thickness, and although the combined thicknesses of the upper layer of silicon oxide and the lower layer of silicon oxide herein is 2 μm, they are not necessarily limited to this thickness.

[0131] The polysilicon film 102 with a thickness of 100 nm, which is to be used as a hard mask, functions as a mask when dry etching is applied to the silicon oxide film. For this, a film made of a material with an etching rate lower than that of the silicon oxide film is chosen, and, apart from polysilicon, doped polysilicon, Si₃N₄, SiGe, Ge or such can be employed therefor.

[0132] Next, patterning (exposure, development and such) is carried out by a known technique of lithography. When the minimum diameter of the hole pattern is 0.15 μm, the aspect ratio becomes 13.3 (2 μm/0.15 μm=13.3).

[0133] Next, using a photoresist as a mask, dry etching for formation of a polysilicon hard mask is performed. After dry etching, remaining photoresists, etching deposition residuals and the likes are removed with a SPM (Sulfuric Peroxide Mix) (a mixed solution of sulfuric acid and hydrogen peroxide), an APM (Ammonia Peroxide Mix) (a mixed solution of ammonia and hydrogen peroxide), a diluted hydrofluoric acid solution or the like.

[0134] These dry etching conditions for the polysilicon are ordinary ones and an anisotropic etching treatment may be made with a chlorine-based mixed gas, a mixed gas containing HBr or the like.

[0135] Next, a treatment is made using a two-frequency type RIE (Reactive Ion Etching) apparatus shown in FIG. 6. The apparatus is characterized by the presence of two types of RF (Radio Frequency) generators, providing an upper band of RF frequencies between 13.56 MHz and 100 MHz and a lower band of RF frequencies between 400 KHz and 2 MHz, and, in recent years, has been used widely by the present inventors.

[0136] Firstly, a first etching of the silicon oxide film is performed. The details of the conditions are as follows.

[0137] Wafer susceptor temperature: 40° C. to 60° C.

[0138] C₄F₈ (Fluorocarbon gas such as C₅F₈ , C₄F₆ can be also used): 20 sccm to 40 sccm

[0139] Ar: 500 sccm to 800 sccm

[0140] O₂: 20 sccm to 40 sccm

[0141] Upper RF: 1000 W to 2000W

[0142] Lower RF: 1000 W to 2000 W

[0143] After the first etching of the silicon oxide film, a state shown in FIG. 9(2) is obtained. The depth possible to be etched while keeping a bowingless state corresponds to an aspect ratio of 7 to 12. In other words, in the present example with an aperture of 0.15 μm, down to a depth of 1.05 μm to 1.8 μm a bowing does not occur. Accordingly, the film thickness of the upper layer of silicon oxide 101-2 may be set to be 1.5 μm and, immediately under the upper layer of silicon oxide 101-2, a Si₃N₄ film 104 which is to act as an etching stopper may be formed.

[0144] Meanwhile, in a hole with an aspect ratio of 12 or greater, the place where a bowing occurs has a depth equivalent to aspect ratios of 2 to 7. When an aperture of the hole is 0.15 μm, this corresponds to a region at depths of 300 nm to 1.05 μm, and it is this place a bowing is liable to occur that a sidewall which is to be set in the next step is required to be formed. In effect, when the depth of the first etching is set to be 1.05 μm to 1.8 μm, the sidewall Si₃N₄ film which is to be formed in the next step can be optimally set in the very place where a bowing is liable to occur when the second etching is made.

[0145] In the present example, the etching stopper is formed at a depth of 1.5 μm.

[0146] In the present example, because the Si₃N₄ film 104 is formed to function as an etching stopper, even if extra first etching time period is provided, the etching does not proceed deeper than designed. It is, therefore, possible to give some extra time to the first etching time period. Further, this etching stopper has the effect of preventing excessive etching to take place even if the etching rate increases due to a change in etching conditions.

[0147] Under the first etching conditions, fluorocarbon gas is employed. The dry etching with fluorocarbon gas is liable to leave fluorocarbon-based deposition residuals on the wafer surface. It is therefore preferable to remove, after the etching, reaction products using the plasma peeling-off method or a solution such as a diluted hydrofluoric acid solution, an APM or a SPM.

[0148] Next, a Si₃N₄ film with a thickness of 10 nm is formed by the low pressure CVD method so as to have a uniform thickness (FIG. 9(3)). The thickness of the Si₃N₄ film is optimally 5 nm to 15 nm. Further, it is also possible to use any other method than the low pressure CVD method as long as a film of dense quality (excelling in etching resistance) with a capability to provide good coverage (a high conformability) can be obtained.

[0149] In the present example, a Si₃N₄ film with a thickness of 2 nm to 5 nm was formed. This can be explained from a fact that, in removing the silicon oxide by the second etching, if the Si₃N₄ film formed on the wall surface of the hole is removed prior to the completion of the hole, there occurs a bowing. The actual thickness of the Si₃N₄ film is determined, depending on the conditions of the second etching.

[0150] Next, applying dry etching to the entire surface thereof, portions of the Si₃N₄ film 103 formed on the surface of the polysilicon that is to be used as a hard mask as well as on the bottom of the hole are removed (FIG. 9(4)). After that, second dry etching is consecutively applied thereto through the polysilicon hard mask to remove the silicon oxide 101 and form a hole down to reach the Si₃N₄ film 105 that is to become a bottom film of a cylindrical capacitor (FIG. 9(5)). In the present example, too, overetching was performed for approximately 20 seconds after the opening reached the silicon substrate 100, and thereby modification of the taper-like shape was made.

[0151] In the present example, for the entire surface dry etching and the second etching, the same conditions as for the first etching are employed.

[0152] In this way, formation of a hole for a bowingless cylindrical capacitor with a high aspect ratio can be accomplished.

EXAMPLE 3

[0153] As Third Example of the present invention, a manufacturing method of a contact hole (a hole interconnection running in the vertical direction and connecting an interconnection with a Si substrate) or a via hole (a hole interconnection running in the vertical direction and connecting an upper layer interconnection layer with a lower layer interconnection layer) shown in FIG. 8 is described below.

[0154] In recent years, the semiconductor integrated circuit device has become large in scale, and the multi-layered interconnection with three layers or more is commonly in use. In FIG. 8, there is shown an example of a double-layered interconnection, comprising a semiconductor element or an interconnection formed on a silicon substrate and interconnections formed on two layer levels. In this case, when the interconnection on the second layer level is connected with the interconnection lying on the substrate, an aspect ratio of a hole exceeds 13 and a bowing may occur therein. Because the spacing of the neighbouring interconnections is narrow, when the bowing occurs, the interconnections in neighbouring contact holes may make a short circuit. Further, even if no short-circuit is made, the distance between the neighbouring contact holes become shorter than designed so that the parasitic capacitance increases and the device characteristics deteriorate.

[0155] Now, referring to FIG. 10, the present example is described below.

[0156] While a manufacturing method of a via hole to connect an interconnection on the first layer level with an interconnection on the third layer level (not shown in the drawings) is shown in FIG. 10, it is apparent that the method is not limited to the case shown therein.

[0157] There are comprised a first interconnection 111 and a second interlayer insulating film112 formed on a first interlayer insulating film 110; a second interconnection 113 formed on the second interlayer insulating film 112; a third interlayer insulating film 114 formed on the second interconnection 113; and a polysilicon film 115 formed on the third interlayer insulating film 114, which is to be used as a hard mask for etching.

[0158] The first interlayer insulating film 110, the second interlayer insulating film 112 and the third interlayer insulating film 114 are each a silicon oxide film with a thickness of 1.5 μm. The first interconnection 111 and the second interconnection 113 are each an interconnection of polysilicon doped with dopants. The interconnections can be also made of TiN, W, AlCu, Ti, CoSi, TiSi or such. The polysilicon film 115 that is to be used as a hard mask for etching is an insulating film with a thickness of 100 nm to 150 nm into which no dopants are doped. The silicon oxide films and the polysilicon films are formed by the low pressure CVD method or the plasma CVD method.

[0159] A hard mask for etching made of polysilicon is used as a mask in etching the silicon oxide films, and, therefore, without being limited to polysilicon, can utilize any material having a high etching selection ratio to the silicon oxide film. Examples for the material include, apart from polysilicon, a silicon nitride film (Si₃N₄ film), a silicon oxynitride film, a SiGe film and a Ge film.

[0160] Next, patterning (exposure, development and such) is carried out by a known technique of lithography. A hole pattern with a diameter of 0.2 μm is formed (FIG. 10(11) ).

[0161] Next, using a photoresist as a mask, etching for formation of a polysilicon hard mask is performed. After etching, remaining photoresists, etching deposition residuals and the likes are removed with a SPM or such.

[0162] The dry etching conditions for the polysilicon are ordinary ones and a treatment may be made under the conditions of a chlorine-based mixed gas, a mixed gas containing HBr or the like.

[0163] Next, a treatment is made using a two-frequency type RIE (Reactive Ion Etching) apparatus shown in FIG. 6. The apparatus is characterized by the presence of two types of RF (Radio Frequency) generators, providing an upper band of RF frequencies between 13.56 MHz and 100 MHz and a lower band of RF frequencies between 400 KHz and 2 MHz, and, in recent years, has been used widely by the present inventors.

[0164] A first etching of the silicon oxide film is then performed. The details of the conditions are as follows.

[0165] Wafer susceptor temperature: 40° C. to 60° C.

[0166] C₄F₈ (Fluorocarbon gas such as C₅F₈ , C₄F₆ can be also used): 20 sccm to 40 sccm

[0167] Ar: 500 sccm to 800 sccm

[0168] O₂: 20 sccm to 40 sccm

[0169] Upper RF: 1000 W to 2000W

[0170] Lower RF: 1000 W to 2000 W

[0171] After the first etching of the silicon oxide film, a state shown in FIG. 10(2) is obtained.

[0172] The depth possible to be etched while keeping a bowingless state corresponds to an aspect ratio of 7 to 12. In other words, in the present example with an aperture of 0.2 μm, down to a depth of 1.4 μm to 2.4 μm a bowing does not occur. Accordingly, the depth for the first etching of the silicon oxide film may be set to be 1.4 μm to 2.4 μm.

[0173] In the present example, a hole with a depth of 2.0 μm was formed by the first silicon oxide etching.

[0174] Under the first etching conditions, fluorocarbon gas is employed. The dry etching with fluorocarbon gas is liable to leave fluorocarbon-based deposition residuals on the wafer surface. It is therefore preferable to remove, after the etching, reaction products using the plasma peeling-off method or a solution such as a diluted hydrofluoric acid solution, an APM or a SPM.

[0175] Next, a Si₃N₄ film 116 with a thickness of 20 nm is formed by the low pressure CVD method so as to have a uniform thickness (FIG. 10(3)) . For this, it is also possible to use any other method than the low pressure CVD method as long as a film of dense quality (excelling in etching resistance) with a capability to provide good coverage (a high conformability) can be obtained.

[0176] Next, the entire surface etching is applied onto the Si₃N₄ film under the following conditions and portions of the Si₃N₄ film 103 lying on the surface of the polysilicon film 115 as well as on the bottom of the hole are removed (FIG. 10(4)) .

[0177] Wafer susceptor temperature: 40° C. to 60° C.

[0178] C₄F₈ (or CHF₃): 30 sccm to 100 sccm

[0179] Ar: 200 sccm

[0180] O₂: 15 sccm to 50 sccm

[0181] Upper RF: 1000 W to 2000W

[0182] Lower RF: 1000 W to 2000 W

[0183] The reason why the etching conditions for the entire surface etching are changed from the etching conditions for First Example, Second Example and first etching and second etching of Third Example solely lies in a fact that a nitride film in this case is formed considerably thick. With the above conditions, the etching rate of the nitride film is set high. It is a matter of course that, in the case that the etching time period is not particularly limited, the etching conditions for the entire surface etching can be the same as those for the first silicon oxide etching and the second silicon oxide etching.

[0184] Under these above conditions, the etching rate ratio in the direction of the depth, that is, the etching rate of the oxide film/the etching rate of the Si₃N₄ film is approximately 5.

[0185] After that, under the same conditions for the first silicon oxide etching, the second silicon oxide etching is carried out, and, thereby, the formation of a via hole is accomplished (FIG. 10(6)) .

[0186] While the Si₃N₄film in First Example is 2 nm to 5 nm in thickness, the Si₃N₄film in Third Example is 20 nm in thickness. Further, in First Example and Second Example, the Si₃N₄ films formed on the sidewalls are thoroughly removed, but, in Third Example, the film is etched by mere 2 nm to 5 nm (FIG. 10(5)) .

[0187] This results in a via hole having an aperture of approximately 0.15 μm, which is narrower than the aperture of 0.2 μm the hard mask has.

[0188] This makes the aspect ratio of the finished via hole 20 (3 μm/0.15 μm=20). Meanwhile, the height corresponding to the aspect ratios of 7 to 20, with which the bowing is liable to occur is 1.05 μm to 1.8 μm, and on the sidewall of the hole in this region, the Si₃N₄ film 116 still remains. In effect, a bowingless via hole with a high aspect ratio can be obtained.