DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0016] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like numbers refer to like elements throughout the description of the figures. In the figures, the dimensions of layers and regions are exaggerated for clarity. Each embodiment described herein also includes its complementary conductivity type embodiment.

[0017] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. It will be understood that if part of an element, such as a surface, is referred to as “inner,” it is farther from the outside of the device than other parts of the element. Furthermore, relative terms such as “beneath” or “overlies” may be used herein to describe a relationship of one layer or region to another layer or region relative to a substrate or base layer as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. Finally, the term “directly” means that there are no intervening elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0018] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and, similarly, a second without departing from the teachings of the present invention.

[0019] Embodiments of the present invention will now be described, generally, with reference to GaN-based light-emitting diodes (LEDs) on non-conductive substrates, such as, for example, sapphire (Al ₂ O ₃ )-based substrates. The present invention, however, is not limited to such structures. Embodiments of the invention may use other substrates, including conductive substrates. Accordingly, combinations can include an AlGaInP diode on a GaP substrate, a GaN diode on a SiC substrate, an SiC diode on an SiC substrate, an SiC diode on a sapphire substrate, and/or a nitride-based diode on a gallium nitride, silicon carbide, aluminum nitride, zinc oxide and/or other substrate. Moreover, the present invention is not limited to the use of a diode region as an active region. Other types of active regions may also be used in accordance with some embodiments of the present invention.

[0020] Examples of light-emitting devices that may be used in embodiments of the present invention include, but are not limited to, the devices described in the following U.S. Pat. Nos.: 6,201,262, 6,187,606, 6,120,600, 5,912,477, 5,739,554, 5,631,190, 5,604,135, 5,523,589, 5,416,342, 5,393,993, 5,338,944, 5,210,051, 5,027,168, 5,027,168, 4,966,862 and/or 4,918,497, the disclosures of which are incorporated herein by reference. Other suitable LEDs and/or lasers are described in U.S. patent application Ser. No. 10/140,796, entitled “GROUP III NITRIDE BASED LIGHT EMITTING DIODE STRUCTURES WITH A QUANTUM WELL AND SUPERLATTICE, GROUP III NITRIDE BASED QUANTUM WELL STRUCTURES AND GROUP III NITRIDE BASED SUPERLATTICE STRUCTURES”, filed May 7, 2002, as well as U.S. patent application Ser. No. 10/057,821, filed Jan. 25, 2002 entitled “LIGHT EMITTING DIODES INCLUDING SUBSTRATE MODIFICATIONS FOR LIGHT EXTRACTION AND MANUFACTURING METHODS THEREFOR” the disclosures of which are incorporated herein as if set forth fully. Furthermore, phosphor coated LEDs, such as those described in U.S. patent application Ser. No. 10/659,241 entitled “PHOSPHOR-COATED LIGHT EMITTING DIODES INCLUDING TAPERED SIDEWALLS, AND FABRICATION METHODS THEREFOR,” filed Sep. 9, 2003, the disclosure of which is incorporated by reference herein as if set forth full, may also be suitable for use in embodiments of the present invention.

[0021] The LEDs and/or lasers may be configured to operate in a “flip-chip” configuration such that light emission occurs through the substrate. In such embodiments, the substrate may be patterned so as to enhance light output of the devices as is described, for example, in U.S. patent application Ser. No. 10/057,821, filed Jan. 25, 2002 entitled “LIGHT EMITTING DIODES INCLUDING SUBSTRATE MODIFICATIONS FOR LIGHT EXTRACTION AND MANUFACTURING METHODS THEREFOR” the disclosure of which is incorporated herein by reference as if set forth fully herein.

[0022] Referring now to FIGS. 2A-2H , light-emitting devices and methods of forming same, in accordance with some embodiments of the present invention, will now be described. As shown in FIG. 2A , a substrate 205 , such as, for example, a sapphire substrate, is provided. A sapphire substrate is generally non-conductive; however, as discussed above, conductive substrates may also be used in accordance with other embodiments of the present invention. The substrate 205 has a first surface 210 a and a second surface 210 b and may be at least partially transparent to optical radiation. An ohmic contact layer 220 may optionally be formed on the first surface 210 a . In accordance with various embodiments of the present invention, the ohmic contact layer 220 may comprise TiN, platinum, nickel/gold, nickel oxide/gold, nickel oxide/platinum, Ti, titanium/gold and/or alloys thereof. The ohmic contact layer 220 may have a thickness between about 10 Å and about 100 Å and may be at least partially transparent to optical radiation in accordance with some embodiments of the present invention.

[0023] Referring now to FIGS. 2B and 2C , an active region, such as, for example, a diode region comprising an n-type layer 225 and a p-type layer 230 may be epitaxially grown on the ohmic contact layer 220 . The diode region, including the n-type layer 225 and/or the p-type layer 230 may comprise gallium nitride-based semiconductor layers, including alloys thereof, such as indium gallium nitride and/or aluminum indium gallium nitride. The fabrication of gallium nitride layers is described, for example, in the above-incorporated U.S. Pat. No. 6,177,688. A buffer layer or layers comprising aluminum nitride, for example, may be provided between the n-type gallium nitride layer 225 and the substrate 205 , as described in the above-incorporated U.S. Pat. Nos. 5,393,993, 5,523,589, 6,177,688, and application Ser. No. 09/154,363 entitled Vertical Geometry InGaN Light Emitting Diode. The n-type gallium nitride layer 225 may comprise silicon-doped gallium nitride, while the p-type gallium nitride layer 230 may comprise magnesium-doped gallium nitride.

[0024] Referring now to FIG. 2D , a first electrical contact 235 is formed on the diode region as shown. The first electrical contact 235 for the p-type gallium nitride layer 230 may comprise platinum, nickel, titanium/gold and/or alloys thereof. In other embodiments, a reflective electrical contact comprising, for example, aluminum and/or silver, may be used. Other suitable materials that form ohmic contact to p-type gallium nitride may be used for the first electrical contact 235 . Examples of ohmic contacts to p-type gallium nitride layers are described, for example, in the above-incorporated U.S. Pat. No. 5,767,581.

[0025] Referring now to FIG. 2E , a via is formed in the substrate 205 between the first and second surfaces 210 a and 210 b , respectively. In some embodiments, the via may be formed by etching the substrate 205 using the ohmic contact layer 220 as an etch stop layer. Various etching techniques may be used in accordance with different embodiments of the present invention, including, but not limited to, wet etching, dry etching, and micro-machining. In particular embodiments of the present invention, the via may be formed in substantial alignment with the first electrical contact 235 to reduce light loss due to “shading.” In other embodiments, the via may be formed so that the via and the first electrical contact 235 are offset from one another. The offset configuration may be used to reduce stress on the gallium nitride-based layers 225 and 230 .

[0026] Referring now to FIG. 2F , a contact plug 240 is formed in the via by, for example, plating the via with a conductive material, such as gold, silver, gold alloys, and/or silver alloys, in accordance with some embodiments of the present invention.

[0027] Referring now to FIG. 2G , a second electrical contact 245 is formed adjacent to the second surface 210 b such that the contact plug 240 couples the second electrical contact 235 to the ohmic contact layer 220 . Advantageously, because the ohmic contact layer 220 contacts the n-type gallium nitride layer 225 across a relatively broad surface area, improved current spreading may be provided. The second electrical contact 245 for the n-type gallium nitride layer 225 may comprise aluminum, titanium, and/or alloys thereof. Other suitable materials that form ohmic contact to n-type gallium nitride may be used for the second electrical contact 245 . Examples of ohmic contacts to n-type gallium nitride layers are described, for example, in the above-incorporated U.S. Pat. 5,767,581. FIG. 2H shows the structure of FIG. 2G inverted with the diode region on top of the substrate 205 .

[0028] Although described above with respect to non-conductive substrate embodiments, conductive substrates, such as SiC substrates, may also be used in accordance with other embodiments of the present invention. In such embodiments, a high resistivity SiC substrate may be used to reduce parasitic (free carrier) absorption. In addition, the forward biased diode offset voltage may be reduced by reducing the heterobarrier between the n-type SiC substrate and the n-type GaN layer.

[0029] Exemplary operations for forming light-emitting devices, in accordance with some embodiments of the present invention, will now be described with reference to the flowcharts of FIGS. 3-5 . Referring now to FIG. 3 , operations begin at block 300 where a first substrate is provided. A diode region is formed on a surface of the first substrate at block 305 as described above with reference to FIGS. 2B and 2C . An electrical contact may then be formed on the diode region at block 310 as described above with reference to FIG. 2D .

[0030] Referring now to FIG. 4 , additional operations, which may be performed in parallel with the operations of FIG. 3 , begin at block 400 where a second substrate is provided. An ohmic contact/etch stop layer may be formed on the second substrate as described above with reference to FIG. 2A . A via is then be formed in the second substrate at block 410 using, for example, the ohmic contact layer as an etch stop layer as described above with reference to FIG. 2E . At block 415 , the via may be filled with a conductive material to form a contact plug as described above with reference to FIG. 2F . An electrical contact may then be formed on the contact plug at block 420 as described above with reference to FIG. 2G .

[0031] Referring now to FIG. 5 , the diode region and the electrical contact disposed thereon is transferred from the first substrate to the second substrate, such that the diode region is disposed on the ohmic contact layer at block 500 . Advantageously, the second substrate, which may be viewed as a “surrogate” substrate, may be selected to have particular material properties that may enhance light extraction from the light-emitting device structure.

[0032] Embodiments of the invention have been described above in which a diode is shown as an example of an active region. It should be understood, however, that an active region may include, but is not limited to, quantum wells, heterojunctions, homojunctions, multiple layers, combinations of the foregoing, or the like, in accordance with some embodiments of the present invention. For example, layers 225 and 230 may be embodied as described in the above-referenced patents and/or applications. Moreover, additional layers, such as lattice strain layers, may also be incorporated in light-emitting devices in accordance with further embodiments of the present invention.

[0033] In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.